1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 #include <asm/intel_pt.h> 73 74 #define CREATE_TRACE_POINTS 75 #include "trace.h" 76 77 #define MAX_IO_MSRS 256 78 #define KVM_MAX_MCE_BANKS 32 79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 81 82 #define emul_to_vcpu(ctxt) \ 83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 84 85 /* EFER defaults: 86 * - enable syscall per default because its emulated by KVM 87 * - enable LME and LMA per default on 64 bit KVM 88 */ 89 #ifdef CONFIG_X86_64 90 static 91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 92 #else 93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 94 #endif 95 96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 98 99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 101 102 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 103 static void process_nmi(struct kvm_vcpu *vcpu); 104 static void enter_smm(struct kvm_vcpu *vcpu); 105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 106 static void store_regs(struct kvm_vcpu *vcpu); 107 static int sync_regs(struct kvm_vcpu *vcpu); 108 109 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 110 EXPORT_SYMBOL_GPL(kvm_x86_ops); 111 112 static bool __read_mostly ignore_msrs = 0; 113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 114 115 static bool __read_mostly report_ignored_msrs = true; 116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 117 118 unsigned int min_timer_period_us = 200; 119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 120 121 static bool __read_mostly kvmclock_periodic_sync = true; 122 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 123 124 bool __read_mostly kvm_has_tsc_control; 125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 126 u32 __read_mostly kvm_max_guest_tsc_khz; 127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 128 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 130 u64 __read_mostly kvm_max_tsc_scaling_ratio; 131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 132 u64 __read_mostly kvm_default_tsc_scaling_ratio; 133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 134 135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 136 static u32 __read_mostly tsc_tolerance_ppm = 250; 137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 138 139 /* 140 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 141 * adaptive tuning starting from default advancment of 1000ns. '0' disables 142 * advancement entirely. Any other value is used as-is and disables adaptive 143 * tuning, i.e. allows priveleged userspace to set an exact advancement time. 144 */ 145 static int __read_mostly lapic_timer_advance_ns = -1; 146 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 147 148 static bool __read_mostly vector_hashing = true; 149 module_param(vector_hashing, bool, S_IRUGO); 150 151 bool __read_mostly enable_vmware_backdoor = false; 152 module_param(enable_vmware_backdoor, bool, S_IRUGO); 153 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 154 155 static bool __read_mostly force_emulation_prefix = false; 156 module_param(force_emulation_prefix, bool, S_IRUGO); 157 158 #define KVM_NR_SHARED_MSRS 16 159 160 struct kvm_shared_msrs_global { 161 int nr; 162 u32 msrs[KVM_NR_SHARED_MSRS]; 163 }; 164 165 struct kvm_shared_msrs { 166 struct user_return_notifier urn; 167 bool registered; 168 struct kvm_shared_msr_values { 169 u64 host; 170 u64 curr; 171 } values[KVM_NR_SHARED_MSRS]; 172 }; 173 174 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 175 static struct kvm_shared_msrs __percpu *shared_msrs; 176 177 struct kvm_stats_debugfs_item debugfs_entries[] = { 178 { "pf_fixed", VCPU_STAT(pf_fixed) }, 179 { "pf_guest", VCPU_STAT(pf_guest) }, 180 { "tlb_flush", VCPU_STAT(tlb_flush) }, 181 { "invlpg", VCPU_STAT(invlpg) }, 182 { "exits", VCPU_STAT(exits) }, 183 { "io_exits", VCPU_STAT(io_exits) }, 184 { "mmio_exits", VCPU_STAT(mmio_exits) }, 185 { "signal_exits", VCPU_STAT(signal_exits) }, 186 { "irq_window", VCPU_STAT(irq_window_exits) }, 187 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 188 { "halt_exits", VCPU_STAT(halt_exits) }, 189 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 190 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 191 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 192 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 193 { "hypercalls", VCPU_STAT(hypercalls) }, 194 { "request_irq", VCPU_STAT(request_irq_exits) }, 195 { "irq_exits", VCPU_STAT(irq_exits) }, 196 { "host_state_reload", VCPU_STAT(host_state_reload) }, 197 { "fpu_reload", VCPU_STAT(fpu_reload) }, 198 { "insn_emulation", VCPU_STAT(insn_emulation) }, 199 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 200 { "irq_injections", VCPU_STAT(irq_injections) }, 201 { "nmi_injections", VCPU_STAT(nmi_injections) }, 202 { "req_event", VCPU_STAT(req_event) }, 203 { "l1d_flush", VCPU_STAT(l1d_flush) }, 204 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 205 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 206 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 207 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 208 { "mmu_flooded", VM_STAT(mmu_flooded) }, 209 { "mmu_recycled", VM_STAT(mmu_recycled) }, 210 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 211 { "mmu_unsync", VM_STAT(mmu_unsync) }, 212 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 213 { "largepages", VM_STAT(lpages) }, 214 { "max_mmu_page_hash_collisions", 215 VM_STAT(max_mmu_page_hash_collisions) }, 216 { NULL } 217 }; 218 219 u64 __read_mostly host_xcr0; 220 221 struct kmem_cache *x86_fpu_cache; 222 EXPORT_SYMBOL_GPL(x86_fpu_cache); 223 224 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 225 226 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 227 { 228 int i; 229 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 230 vcpu->arch.apf.gfns[i] = ~0; 231 } 232 233 static void kvm_on_user_return(struct user_return_notifier *urn) 234 { 235 unsigned slot; 236 struct kvm_shared_msrs *locals 237 = container_of(urn, struct kvm_shared_msrs, urn); 238 struct kvm_shared_msr_values *values; 239 unsigned long flags; 240 241 /* 242 * Disabling irqs at this point since the following code could be 243 * interrupted and executed through kvm_arch_hardware_disable() 244 */ 245 local_irq_save(flags); 246 if (locals->registered) { 247 locals->registered = false; 248 user_return_notifier_unregister(urn); 249 } 250 local_irq_restore(flags); 251 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 252 values = &locals->values[slot]; 253 if (values->host != values->curr) { 254 wrmsrl(shared_msrs_global.msrs[slot], values->host); 255 values->curr = values->host; 256 } 257 } 258 } 259 260 static void shared_msr_update(unsigned slot, u32 msr) 261 { 262 u64 value; 263 unsigned int cpu = smp_processor_id(); 264 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 265 266 /* only read, and nobody should modify it at this time, 267 * so don't need lock */ 268 if (slot >= shared_msrs_global.nr) { 269 printk(KERN_ERR "kvm: invalid MSR slot!"); 270 return; 271 } 272 rdmsrl_safe(msr, &value); 273 smsr->values[slot].host = value; 274 smsr->values[slot].curr = value; 275 } 276 277 void kvm_define_shared_msr(unsigned slot, u32 msr) 278 { 279 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 280 shared_msrs_global.msrs[slot] = msr; 281 if (slot >= shared_msrs_global.nr) 282 shared_msrs_global.nr = slot + 1; 283 } 284 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 285 286 static void kvm_shared_msr_cpu_online(void) 287 { 288 unsigned i; 289 290 for (i = 0; i < shared_msrs_global.nr; ++i) 291 shared_msr_update(i, shared_msrs_global.msrs[i]); 292 } 293 294 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 295 { 296 unsigned int cpu = smp_processor_id(); 297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 298 int err; 299 300 if (((value ^ smsr->values[slot].curr) & mask) == 0) 301 return 0; 302 smsr->values[slot].curr = value; 303 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 304 if (err) 305 return 1; 306 307 if (!smsr->registered) { 308 smsr->urn.on_user_return = kvm_on_user_return; 309 user_return_notifier_register(&smsr->urn); 310 smsr->registered = true; 311 } 312 return 0; 313 } 314 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 315 316 static void drop_user_return_notifiers(void) 317 { 318 unsigned int cpu = smp_processor_id(); 319 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 320 321 if (smsr->registered) 322 kvm_on_user_return(&smsr->urn); 323 } 324 325 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 326 { 327 return vcpu->arch.apic_base; 328 } 329 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 330 331 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 332 { 333 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 334 } 335 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 336 337 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 338 { 339 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 340 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 341 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 342 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 343 344 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 345 return 1; 346 if (!msr_info->host_initiated) { 347 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 348 return 1; 349 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 350 return 1; 351 } 352 353 kvm_lapic_set_base(vcpu, msr_info->data); 354 return 0; 355 } 356 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 357 358 asmlinkage __visible void kvm_spurious_fault(void) 359 { 360 /* Fault while not rebooting. We want the trace. */ 361 BUG(); 362 } 363 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 364 365 #define EXCPT_BENIGN 0 366 #define EXCPT_CONTRIBUTORY 1 367 #define EXCPT_PF 2 368 369 static int exception_class(int vector) 370 { 371 switch (vector) { 372 case PF_VECTOR: 373 return EXCPT_PF; 374 case DE_VECTOR: 375 case TS_VECTOR: 376 case NP_VECTOR: 377 case SS_VECTOR: 378 case GP_VECTOR: 379 return EXCPT_CONTRIBUTORY; 380 default: 381 break; 382 } 383 return EXCPT_BENIGN; 384 } 385 386 #define EXCPT_FAULT 0 387 #define EXCPT_TRAP 1 388 #define EXCPT_ABORT 2 389 #define EXCPT_INTERRUPT 3 390 391 static int exception_type(int vector) 392 { 393 unsigned int mask; 394 395 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 396 return EXCPT_INTERRUPT; 397 398 mask = 1 << vector; 399 400 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 401 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 402 return EXCPT_TRAP; 403 404 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 405 return EXCPT_ABORT; 406 407 /* Reserved exceptions will result in fault */ 408 return EXCPT_FAULT; 409 } 410 411 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 412 { 413 unsigned nr = vcpu->arch.exception.nr; 414 bool has_payload = vcpu->arch.exception.has_payload; 415 unsigned long payload = vcpu->arch.exception.payload; 416 417 if (!has_payload) 418 return; 419 420 switch (nr) { 421 case DB_VECTOR: 422 /* 423 * "Certain debug exceptions may clear bit 0-3. The 424 * remaining contents of the DR6 register are never 425 * cleared by the processor". 426 */ 427 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 428 /* 429 * DR6.RTM is set by all #DB exceptions that don't clear it. 430 */ 431 vcpu->arch.dr6 |= DR6_RTM; 432 vcpu->arch.dr6 |= payload; 433 /* 434 * Bit 16 should be set in the payload whenever the #DB 435 * exception should clear DR6.RTM. This makes the payload 436 * compatible with the pending debug exceptions under VMX. 437 * Though not currently documented in the SDM, this also 438 * makes the payload compatible with the exit qualification 439 * for #DB exceptions under VMX. 440 */ 441 vcpu->arch.dr6 ^= payload & DR6_RTM; 442 break; 443 case PF_VECTOR: 444 vcpu->arch.cr2 = payload; 445 break; 446 } 447 448 vcpu->arch.exception.has_payload = false; 449 vcpu->arch.exception.payload = 0; 450 } 451 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 452 453 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 454 unsigned nr, bool has_error, u32 error_code, 455 bool has_payload, unsigned long payload, bool reinject) 456 { 457 u32 prev_nr; 458 int class1, class2; 459 460 kvm_make_request(KVM_REQ_EVENT, vcpu); 461 462 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 463 queue: 464 if (has_error && !is_protmode(vcpu)) 465 has_error = false; 466 if (reinject) { 467 /* 468 * On vmentry, vcpu->arch.exception.pending is only 469 * true if an event injection was blocked by 470 * nested_run_pending. In that case, however, 471 * vcpu_enter_guest requests an immediate exit, 472 * and the guest shouldn't proceed far enough to 473 * need reinjection. 474 */ 475 WARN_ON_ONCE(vcpu->arch.exception.pending); 476 vcpu->arch.exception.injected = true; 477 if (WARN_ON_ONCE(has_payload)) { 478 /* 479 * A reinjected event has already 480 * delivered its payload. 481 */ 482 has_payload = false; 483 payload = 0; 484 } 485 } else { 486 vcpu->arch.exception.pending = true; 487 vcpu->arch.exception.injected = false; 488 } 489 vcpu->arch.exception.has_error_code = has_error; 490 vcpu->arch.exception.nr = nr; 491 vcpu->arch.exception.error_code = error_code; 492 vcpu->arch.exception.has_payload = has_payload; 493 vcpu->arch.exception.payload = payload; 494 /* 495 * In guest mode, payload delivery should be deferred, 496 * so that the L1 hypervisor can intercept #PF before 497 * CR2 is modified (or intercept #DB before DR6 is 498 * modified under nVMX). However, for ABI 499 * compatibility with KVM_GET_VCPU_EVENTS and 500 * KVM_SET_VCPU_EVENTS, we can't delay payload 501 * delivery unless userspace has enabled this 502 * functionality via the per-VM capability, 503 * KVM_CAP_EXCEPTION_PAYLOAD. 504 */ 505 if (!vcpu->kvm->arch.exception_payload_enabled || 506 !is_guest_mode(vcpu)) 507 kvm_deliver_exception_payload(vcpu); 508 return; 509 } 510 511 /* to check exception */ 512 prev_nr = vcpu->arch.exception.nr; 513 if (prev_nr == DF_VECTOR) { 514 /* triple fault -> shutdown */ 515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 516 return; 517 } 518 class1 = exception_class(prev_nr); 519 class2 = exception_class(nr); 520 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 521 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 522 /* 523 * Generate double fault per SDM Table 5-5. Set 524 * exception.pending = true so that the double fault 525 * can trigger a nested vmexit. 526 */ 527 vcpu->arch.exception.pending = true; 528 vcpu->arch.exception.injected = false; 529 vcpu->arch.exception.has_error_code = true; 530 vcpu->arch.exception.nr = DF_VECTOR; 531 vcpu->arch.exception.error_code = 0; 532 vcpu->arch.exception.has_payload = false; 533 vcpu->arch.exception.payload = 0; 534 } else 535 /* replace previous exception with a new one in a hope 536 that instruction re-execution will regenerate lost 537 exception */ 538 goto queue; 539 } 540 541 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 542 { 543 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 544 } 545 EXPORT_SYMBOL_GPL(kvm_queue_exception); 546 547 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 548 { 549 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 550 } 551 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 552 553 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 554 unsigned long payload) 555 { 556 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 557 } 558 559 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 560 u32 error_code, unsigned long payload) 561 { 562 kvm_multiple_exception(vcpu, nr, true, error_code, 563 true, payload, false); 564 } 565 566 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 567 { 568 if (err) 569 kvm_inject_gp(vcpu, 0); 570 else 571 return kvm_skip_emulated_instruction(vcpu); 572 573 return 1; 574 } 575 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 576 577 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 578 { 579 ++vcpu->stat.pf_guest; 580 vcpu->arch.exception.nested_apf = 581 is_guest_mode(vcpu) && fault->async_page_fault; 582 if (vcpu->arch.exception.nested_apf) { 583 vcpu->arch.apf.nested_apf_token = fault->address; 584 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 585 } else { 586 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 587 fault->address); 588 } 589 } 590 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 591 592 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 593 { 594 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 595 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 596 else 597 vcpu->arch.mmu->inject_page_fault(vcpu, fault); 598 599 return fault->nested_page_fault; 600 } 601 602 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 603 { 604 atomic_inc(&vcpu->arch.nmi_queued); 605 kvm_make_request(KVM_REQ_NMI, vcpu); 606 } 607 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 608 609 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 610 { 611 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 612 } 613 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 614 615 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 616 { 617 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 618 } 619 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 620 621 /* 622 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 623 * a #GP and return false. 624 */ 625 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 626 { 627 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 628 return true; 629 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 630 return false; 631 } 632 EXPORT_SYMBOL_GPL(kvm_require_cpl); 633 634 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 635 { 636 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 637 return true; 638 639 kvm_queue_exception(vcpu, UD_VECTOR); 640 return false; 641 } 642 EXPORT_SYMBOL_GPL(kvm_require_dr); 643 644 /* 645 * This function will be used to read from the physical memory of the currently 646 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 647 * can read from guest physical or from the guest's guest physical memory. 648 */ 649 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 650 gfn_t ngfn, void *data, int offset, int len, 651 u32 access) 652 { 653 struct x86_exception exception; 654 gfn_t real_gfn; 655 gpa_t ngpa; 656 657 ngpa = gfn_to_gpa(ngfn); 658 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 659 if (real_gfn == UNMAPPED_GVA) 660 return -EFAULT; 661 662 real_gfn = gpa_to_gfn(real_gfn); 663 664 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 665 } 666 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 667 668 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 669 void *data, int offset, int len, u32 access) 670 { 671 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 672 data, offset, len, access); 673 } 674 675 /* 676 * Load the pae pdptrs. Return true is they are all valid. 677 */ 678 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 679 { 680 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 681 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 682 int i; 683 int ret; 684 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 685 686 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 687 offset * sizeof(u64), sizeof(pdpte), 688 PFERR_USER_MASK|PFERR_WRITE_MASK); 689 if (ret < 0) { 690 ret = 0; 691 goto out; 692 } 693 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 694 if ((pdpte[i] & PT_PRESENT_MASK) && 695 (pdpte[i] & 696 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) { 697 ret = 0; 698 goto out; 699 } 700 } 701 ret = 1; 702 703 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 704 __set_bit(VCPU_EXREG_PDPTR, 705 (unsigned long *)&vcpu->arch.regs_avail); 706 __set_bit(VCPU_EXREG_PDPTR, 707 (unsigned long *)&vcpu->arch.regs_dirty); 708 out: 709 710 return ret; 711 } 712 EXPORT_SYMBOL_GPL(load_pdptrs); 713 714 bool pdptrs_changed(struct kvm_vcpu *vcpu) 715 { 716 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 717 bool changed = true; 718 int offset; 719 gfn_t gfn; 720 int r; 721 722 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu)) 723 return false; 724 725 if (!test_bit(VCPU_EXREG_PDPTR, 726 (unsigned long *)&vcpu->arch.regs_avail)) 727 return true; 728 729 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 730 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 731 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 732 PFERR_USER_MASK | PFERR_WRITE_MASK); 733 if (r < 0) 734 goto out; 735 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 736 out: 737 738 return changed; 739 } 740 EXPORT_SYMBOL_GPL(pdptrs_changed); 741 742 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 743 { 744 unsigned long old_cr0 = kvm_read_cr0(vcpu); 745 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 746 747 cr0 |= X86_CR0_ET; 748 749 #ifdef CONFIG_X86_64 750 if (cr0 & 0xffffffff00000000UL) 751 return 1; 752 #endif 753 754 cr0 &= ~CR0_RESERVED_BITS; 755 756 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 757 return 1; 758 759 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 760 return 1; 761 762 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 763 #ifdef CONFIG_X86_64 764 if ((vcpu->arch.efer & EFER_LME)) { 765 int cs_db, cs_l; 766 767 if (!is_pae(vcpu)) 768 return 1; 769 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 770 if (cs_l) 771 return 1; 772 } else 773 #endif 774 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 775 kvm_read_cr3(vcpu))) 776 return 1; 777 } 778 779 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 780 return 1; 781 782 kvm_x86_ops->set_cr0(vcpu, cr0); 783 784 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 785 kvm_clear_async_pf_completion_queue(vcpu); 786 kvm_async_pf_hash_reset(vcpu); 787 } 788 789 if ((cr0 ^ old_cr0) & update_bits) 790 kvm_mmu_reset_context(vcpu); 791 792 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 793 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 794 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 795 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 796 797 return 0; 798 } 799 EXPORT_SYMBOL_GPL(kvm_set_cr0); 800 801 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 802 { 803 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 804 } 805 EXPORT_SYMBOL_GPL(kvm_lmsw); 806 807 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 808 { 809 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 810 !vcpu->guest_xcr0_loaded) { 811 /* kvm_set_xcr() also depends on this */ 812 if (vcpu->arch.xcr0 != host_xcr0) 813 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 814 vcpu->guest_xcr0_loaded = 1; 815 } 816 } 817 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0); 818 819 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 820 { 821 if (vcpu->guest_xcr0_loaded) { 822 if (vcpu->arch.xcr0 != host_xcr0) 823 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 824 vcpu->guest_xcr0_loaded = 0; 825 } 826 } 827 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0); 828 829 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 830 { 831 u64 xcr0 = xcr; 832 u64 old_xcr0 = vcpu->arch.xcr0; 833 u64 valid_bits; 834 835 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 836 if (index != XCR_XFEATURE_ENABLED_MASK) 837 return 1; 838 if (!(xcr0 & XFEATURE_MASK_FP)) 839 return 1; 840 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 841 return 1; 842 843 /* 844 * Do not allow the guest to set bits that we do not support 845 * saving. However, xcr0 bit 0 is always set, even if the 846 * emulated CPU does not support XSAVE (see fx_init). 847 */ 848 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 849 if (xcr0 & ~valid_bits) 850 return 1; 851 852 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 853 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 854 return 1; 855 856 if (xcr0 & XFEATURE_MASK_AVX512) { 857 if (!(xcr0 & XFEATURE_MASK_YMM)) 858 return 1; 859 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 860 return 1; 861 } 862 vcpu->arch.xcr0 = xcr0; 863 864 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 865 kvm_update_cpuid(vcpu); 866 return 0; 867 } 868 869 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 870 { 871 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 872 __kvm_set_xcr(vcpu, index, xcr)) { 873 kvm_inject_gp(vcpu, 0); 874 return 1; 875 } 876 return 0; 877 } 878 EXPORT_SYMBOL_GPL(kvm_set_xcr); 879 880 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 881 { 882 unsigned long old_cr4 = kvm_read_cr4(vcpu); 883 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 884 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 885 886 if (cr4 & CR4_RESERVED_BITS) 887 return 1; 888 889 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 890 return 1; 891 892 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 893 return 1; 894 895 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 896 return 1; 897 898 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 899 return 1; 900 901 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 902 return 1; 903 904 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 905 return 1; 906 907 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) 908 return 1; 909 910 if (is_long_mode(vcpu)) { 911 if (!(cr4 & X86_CR4_PAE)) 912 return 1; 913 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 914 && ((cr4 ^ old_cr4) & pdptr_bits) 915 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 916 kvm_read_cr3(vcpu))) 917 return 1; 918 919 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 920 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 921 return 1; 922 923 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 924 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 925 return 1; 926 } 927 928 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 929 return 1; 930 931 if (((cr4 ^ old_cr4) & pdptr_bits) || 932 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 933 kvm_mmu_reset_context(vcpu); 934 935 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 936 kvm_update_cpuid(vcpu); 937 938 return 0; 939 } 940 EXPORT_SYMBOL_GPL(kvm_set_cr4); 941 942 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 943 { 944 bool skip_tlb_flush = false; 945 #ifdef CONFIG_X86_64 946 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 947 948 if (pcid_enabled) { 949 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 950 cr3 &= ~X86_CR3_PCID_NOFLUSH; 951 } 952 #endif 953 954 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 955 if (!skip_tlb_flush) { 956 kvm_mmu_sync_roots(vcpu); 957 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 958 } 959 return 0; 960 } 961 962 if (is_long_mode(vcpu) && 963 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) 964 return 1; 965 else if (is_pae(vcpu) && is_paging(vcpu) && 966 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 967 return 1; 968 969 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); 970 vcpu->arch.cr3 = cr3; 971 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 972 973 return 0; 974 } 975 EXPORT_SYMBOL_GPL(kvm_set_cr3); 976 977 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 978 { 979 if (cr8 & CR8_RESERVED_BITS) 980 return 1; 981 if (lapic_in_kernel(vcpu)) 982 kvm_lapic_set_tpr(vcpu, cr8); 983 else 984 vcpu->arch.cr8 = cr8; 985 return 0; 986 } 987 EXPORT_SYMBOL_GPL(kvm_set_cr8); 988 989 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 990 { 991 if (lapic_in_kernel(vcpu)) 992 return kvm_lapic_get_cr8(vcpu); 993 else 994 return vcpu->arch.cr8; 995 } 996 EXPORT_SYMBOL_GPL(kvm_get_cr8); 997 998 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 999 { 1000 int i; 1001 1002 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1003 for (i = 0; i < KVM_NR_DB_REGS; i++) 1004 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1005 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1006 } 1007 } 1008 1009 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 1010 { 1011 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1012 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 1013 } 1014 1015 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 1016 { 1017 unsigned long dr7; 1018 1019 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1020 dr7 = vcpu->arch.guest_debug_dr7; 1021 else 1022 dr7 = vcpu->arch.dr7; 1023 kvm_x86_ops->set_dr7(vcpu, dr7); 1024 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1025 if (dr7 & DR7_BP_EN_MASK) 1026 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1027 } 1028 1029 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1030 { 1031 u64 fixed = DR6_FIXED_1; 1032 1033 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1034 fixed |= DR6_RTM; 1035 return fixed; 1036 } 1037 1038 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1039 { 1040 switch (dr) { 1041 case 0 ... 3: 1042 vcpu->arch.db[dr] = val; 1043 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1044 vcpu->arch.eff_db[dr] = val; 1045 break; 1046 case 4: 1047 /* fall through */ 1048 case 6: 1049 if (val & 0xffffffff00000000ULL) 1050 return -1; /* #GP */ 1051 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1052 kvm_update_dr6(vcpu); 1053 break; 1054 case 5: 1055 /* fall through */ 1056 default: /* 7 */ 1057 if (val & 0xffffffff00000000ULL) 1058 return -1; /* #GP */ 1059 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1060 kvm_update_dr7(vcpu); 1061 break; 1062 } 1063 1064 return 0; 1065 } 1066 1067 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1068 { 1069 if (__kvm_set_dr(vcpu, dr, val)) { 1070 kvm_inject_gp(vcpu, 0); 1071 return 1; 1072 } 1073 return 0; 1074 } 1075 EXPORT_SYMBOL_GPL(kvm_set_dr); 1076 1077 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1078 { 1079 switch (dr) { 1080 case 0 ... 3: 1081 *val = vcpu->arch.db[dr]; 1082 break; 1083 case 4: 1084 /* fall through */ 1085 case 6: 1086 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1087 *val = vcpu->arch.dr6; 1088 else 1089 *val = kvm_x86_ops->get_dr6(vcpu); 1090 break; 1091 case 5: 1092 /* fall through */ 1093 default: /* 7 */ 1094 *val = vcpu->arch.dr7; 1095 break; 1096 } 1097 return 0; 1098 } 1099 EXPORT_SYMBOL_GPL(kvm_get_dr); 1100 1101 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1102 { 1103 u32 ecx = kvm_rcx_read(vcpu); 1104 u64 data; 1105 int err; 1106 1107 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1108 if (err) 1109 return err; 1110 kvm_rax_write(vcpu, (u32)data); 1111 kvm_rdx_write(vcpu, data >> 32); 1112 return err; 1113 } 1114 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1115 1116 /* 1117 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1118 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1119 * 1120 * This list is modified at module load time to reflect the 1121 * capabilities of the host cpu. This capabilities test skips MSRs that are 1122 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1123 * may depend on host virtualization features rather than host cpu features. 1124 */ 1125 1126 static u32 msrs_to_save[] = { 1127 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1128 MSR_STAR, 1129 #ifdef CONFIG_X86_64 1130 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1131 #endif 1132 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1133 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1134 MSR_IA32_SPEC_CTRL, 1135 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1136 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1137 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1138 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1139 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1140 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1141 }; 1142 1143 static unsigned num_msrs_to_save; 1144 1145 static u32 emulated_msrs[] = { 1146 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1147 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1148 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1149 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1150 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1151 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1152 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1153 HV_X64_MSR_RESET, 1154 HV_X64_MSR_VP_INDEX, 1155 HV_X64_MSR_VP_RUNTIME, 1156 HV_X64_MSR_SCONTROL, 1157 HV_X64_MSR_STIMER0_CONFIG, 1158 HV_X64_MSR_VP_ASSIST_PAGE, 1159 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1160 HV_X64_MSR_TSC_EMULATION_STATUS, 1161 1162 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1163 MSR_KVM_PV_EOI_EN, 1164 1165 MSR_IA32_TSC_ADJUST, 1166 MSR_IA32_TSCDEADLINE, 1167 MSR_IA32_ARCH_CAPABILITIES, 1168 MSR_IA32_MISC_ENABLE, 1169 MSR_IA32_MCG_STATUS, 1170 MSR_IA32_MCG_CTL, 1171 MSR_IA32_MCG_EXT_CTL, 1172 MSR_IA32_SMBASE, 1173 MSR_SMI_COUNT, 1174 MSR_PLATFORM_INFO, 1175 MSR_MISC_FEATURES_ENABLES, 1176 MSR_AMD64_VIRT_SPEC_CTRL, 1177 MSR_IA32_POWER_CTL, 1178 1179 MSR_K7_HWCR, 1180 }; 1181 1182 static unsigned num_emulated_msrs; 1183 1184 /* 1185 * List of msr numbers which are used to expose MSR-based features that 1186 * can be used by a hypervisor to validate requested CPU features. 1187 */ 1188 static u32 msr_based_features[] = { 1189 MSR_IA32_VMX_BASIC, 1190 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1191 MSR_IA32_VMX_PINBASED_CTLS, 1192 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1193 MSR_IA32_VMX_PROCBASED_CTLS, 1194 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1195 MSR_IA32_VMX_EXIT_CTLS, 1196 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1197 MSR_IA32_VMX_ENTRY_CTLS, 1198 MSR_IA32_VMX_MISC, 1199 MSR_IA32_VMX_CR0_FIXED0, 1200 MSR_IA32_VMX_CR0_FIXED1, 1201 MSR_IA32_VMX_CR4_FIXED0, 1202 MSR_IA32_VMX_CR4_FIXED1, 1203 MSR_IA32_VMX_VMCS_ENUM, 1204 MSR_IA32_VMX_PROCBASED_CTLS2, 1205 MSR_IA32_VMX_EPT_VPID_CAP, 1206 MSR_IA32_VMX_VMFUNC, 1207 1208 MSR_F10H_DECFG, 1209 MSR_IA32_UCODE_REV, 1210 MSR_IA32_ARCH_CAPABILITIES, 1211 }; 1212 1213 static unsigned int num_msr_based_features; 1214 1215 u64 kvm_get_arch_capabilities(void) 1216 { 1217 u64 data; 1218 1219 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data); 1220 1221 /* 1222 * If we're doing cache flushes (either "always" or "cond") 1223 * we will do one whenever the guest does a vmlaunch/vmresume. 1224 * If an outer hypervisor is doing the cache flush for us 1225 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1226 * capability to the guest too, and if EPT is disabled we're not 1227 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1228 * require a nested hypervisor to do a flush of its own. 1229 */ 1230 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1231 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1232 1233 return data; 1234 } 1235 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities); 1236 1237 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1238 { 1239 switch (msr->index) { 1240 case MSR_IA32_ARCH_CAPABILITIES: 1241 msr->data = kvm_get_arch_capabilities(); 1242 break; 1243 case MSR_IA32_UCODE_REV: 1244 rdmsrl_safe(msr->index, &msr->data); 1245 break; 1246 default: 1247 if (kvm_x86_ops->get_msr_feature(msr)) 1248 return 1; 1249 } 1250 return 0; 1251 } 1252 1253 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1254 { 1255 struct kvm_msr_entry msr; 1256 int r; 1257 1258 msr.index = index; 1259 r = kvm_get_msr_feature(&msr); 1260 if (r) 1261 return r; 1262 1263 *data = msr.data; 1264 1265 return 0; 1266 } 1267 1268 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1269 { 1270 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1271 return false; 1272 1273 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1274 return false; 1275 1276 if (efer & (EFER_LME | EFER_LMA) && 1277 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1278 return false; 1279 1280 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1281 return false; 1282 1283 return true; 1284 1285 } 1286 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1287 { 1288 if (efer & efer_reserved_bits) 1289 return false; 1290 1291 return __kvm_valid_efer(vcpu, efer); 1292 } 1293 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1294 1295 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1296 { 1297 u64 old_efer = vcpu->arch.efer; 1298 u64 efer = msr_info->data; 1299 1300 if (efer & efer_reserved_bits) 1301 return false; 1302 1303 if (!msr_info->host_initiated) { 1304 if (!__kvm_valid_efer(vcpu, efer)) 1305 return 1; 1306 1307 if (is_paging(vcpu) && 1308 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1309 return 1; 1310 } 1311 1312 efer &= ~EFER_LMA; 1313 efer |= vcpu->arch.efer & EFER_LMA; 1314 1315 kvm_x86_ops->set_efer(vcpu, efer); 1316 1317 /* Update reserved bits */ 1318 if ((efer ^ old_efer) & EFER_NX) 1319 kvm_mmu_reset_context(vcpu); 1320 1321 return 0; 1322 } 1323 1324 void kvm_enable_efer_bits(u64 mask) 1325 { 1326 efer_reserved_bits &= ~mask; 1327 } 1328 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1329 1330 /* 1331 * Writes msr value into into the appropriate "register". 1332 * Returns 0 on success, non-0 otherwise. 1333 * Assumes vcpu_load() was already called. 1334 */ 1335 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1336 { 1337 switch (msr->index) { 1338 case MSR_FS_BASE: 1339 case MSR_GS_BASE: 1340 case MSR_KERNEL_GS_BASE: 1341 case MSR_CSTAR: 1342 case MSR_LSTAR: 1343 if (is_noncanonical_address(msr->data, vcpu)) 1344 return 1; 1345 break; 1346 case MSR_IA32_SYSENTER_EIP: 1347 case MSR_IA32_SYSENTER_ESP: 1348 /* 1349 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1350 * non-canonical address is written on Intel but not on 1351 * AMD (which ignores the top 32-bits, because it does 1352 * not implement 64-bit SYSENTER). 1353 * 1354 * 64-bit code should hence be able to write a non-canonical 1355 * value on AMD. Making the address canonical ensures that 1356 * vmentry does not fail on Intel after writing a non-canonical 1357 * value, and that something deterministic happens if the guest 1358 * invokes 64-bit SYSENTER. 1359 */ 1360 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1361 } 1362 return kvm_x86_ops->set_msr(vcpu, msr); 1363 } 1364 EXPORT_SYMBOL_GPL(kvm_set_msr); 1365 1366 /* 1367 * Adapt set_msr() to msr_io()'s calling convention 1368 */ 1369 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1370 { 1371 struct msr_data msr; 1372 int r; 1373 1374 msr.index = index; 1375 msr.host_initiated = true; 1376 r = kvm_get_msr(vcpu, &msr); 1377 if (r) 1378 return r; 1379 1380 *data = msr.data; 1381 return 0; 1382 } 1383 1384 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1385 { 1386 struct msr_data msr; 1387 1388 msr.data = *data; 1389 msr.index = index; 1390 msr.host_initiated = true; 1391 return kvm_set_msr(vcpu, &msr); 1392 } 1393 1394 #ifdef CONFIG_X86_64 1395 struct pvclock_gtod_data { 1396 seqcount_t seq; 1397 1398 struct { /* extract of a clocksource struct */ 1399 int vclock_mode; 1400 u64 cycle_last; 1401 u64 mask; 1402 u32 mult; 1403 u32 shift; 1404 } clock; 1405 1406 u64 boot_ns; 1407 u64 nsec_base; 1408 u64 wall_time_sec; 1409 }; 1410 1411 static struct pvclock_gtod_data pvclock_gtod_data; 1412 1413 static void update_pvclock_gtod(struct timekeeper *tk) 1414 { 1415 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1416 u64 boot_ns; 1417 1418 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1419 1420 write_seqcount_begin(&vdata->seq); 1421 1422 /* copy pvclock gtod data */ 1423 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1424 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1425 vdata->clock.mask = tk->tkr_mono.mask; 1426 vdata->clock.mult = tk->tkr_mono.mult; 1427 vdata->clock.shift = tk->tkr_mono.shift; 1428 1429 vdata->boot_ns = boot_ns; 1430 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1431 1432 vdata->wall_time_sec = tk->xtime_sec; 1433 1434 write_seqcount_end(&vdata->seq); 1435 } 1436 #endif 1437 1438 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1439 { 1440 /* 1441 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1442 * vcpu_enter_guest. This function is only called from 1443 * the physical CPU that is running vcpu. 1444 */ 1445 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1446 } 1447 1448 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1449 { 1450 int version; 1451 int r; 1452 struct pvclock_wall_clock wc; 1453 struct timespec64 boot; 1454 1455 if (!wall_clock) 1456 return; 1457 1458 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1459 if (r) 1460 return; 1461 1462 if (version & 1) 1463 ++version; /* first time write, random junk */ 1464 1465 ++version; 1466 1467 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1468 return; 1469 1470 /* 1471 * The guest calculates current wall clock time by adding 1472 * system time (updated by kvm_guest_time_update below) to the 1473 * wall clock specified here. guest system time equals host 1474 * system time for us, thus we must fill in host boot time here. 1475 */ 1476 getboottime64(&boot); 1477 1478 if (kvm->arch.kvmclock_offset) { 1479 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1480 boot = timespec64_sub(boot, ts); 1481 } 1482 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1483 wc.nsec = boot.tv_nsec; 1484 wc.version = version; 1485 1486 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1487 1488 version++; 1489 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1490 } 1491 1492 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1493 { 1494 do_shl32_div32(dividend, divisor); 1495 return dividend; 1496 } 1497 1498 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1499 s8 *pshift, u32 *pmultiplier) 1500 { 1501 uint64_t scaled64; 1502 int32_t shift = 0; 1503 uint64_t tps64; 1504 uint32_t tps32; 1505 1506 tps64 = base_hz; 1507 scaled64 = scaled_hz; 1508 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1509 tps64 >>= 1; 1510 shift--; 1511 } 1512 1513 tps32 = (uint32_t)tps64; 1514 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1515 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1516 scaled64 >>= 1; 1517 else 1518 tps32 <<= 1; 1519 shift++; 1520 } 1521 1522 *pshift = shift; 1523 *pmultiplier = div_frac(scaled64, tps32); 1524 1525 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1526 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1527 } 1528 1529 #ifdef CONFIG_X86_64 1530 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1531 #endif 1532 1533 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1534 static unsigned long max_tsc_khz; 1535 1536 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1537 { 1538 u64 v = (u64)khz * (1000000 + ppm); 1539 do_div(v, 1000000); 1540 return v; 1541 } 1542 1543 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1544 { 1545 u64 ratio; 1546 1547 /* Guest TSC same frequency as host TSC? */ 1548 if (!scale) { 1549 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1550 return 0; 1551 } 1552 1553 /* TSC scaling supported? */ 1554 if (!kvm_has_tsc_control) { 1555 if (user_tsc_khz > tsc_khz) { 1556 vcpu->arch.tsc_catchup = 1; 1557 vcpu->arch.tsc_always_catchup = 1; 1558 return 0; 1559 } else { 1560 WARN(1, "user requested TSC rate below hardware speed\n"); 1561 return -1; 1562 } 1563 } 1564 1565 /* TSC scaling required - calculate ratio */ 1566 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1567 user_tsc_khz, tsc_khz); 1568 1569 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1570 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1571 user_tsc_khz); 1572 return -1; 1573 } 1574 1575 vcpu->arch.tsc_scaling_ratio = ratio; 1576 return 0; 1577 } 1578 1579 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1580 { 1581 u32 thresh_lo, thresh_hi; 1582 int use_scaling = 0; 1583 1584 /* tsc_khz can be zero if TSC calibration fails */ 1585 if (user_tsc_khz == 0) { 1586 /* set tsc_scaling_ratio to a safe value */ 1587 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1588 return -1; 1589 } 1590 1591 /* Compute a scale to convert nanoseconds in TSC cycles */ 1592 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1593 &vcpu->arch.virtual_tsc_shift, 1594 &vcpu->arch.virtual_tsc_mult); 1595 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1596 1597 /* 1598 * Compute the variation in TSC rate which is acceptable 1599 * within the range of tolerance and decide if the 1600 * rate being applied is within that bounds of the hardware 1601 * rate. If so, no scaling or compensation need be done. 1602 */ 1603 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1604 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1605 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1606 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1607 use_scaling = 1; 1608 } 1609 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1610 } 1611 1612 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1613 { 1614 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1615 vcpu->arch.virtual_tsc_mult, 1616 vcpu->arch.virtual_tsc_shift); 1617 tsc += vcpu->arch.this_tsc_write; 1618 return tsc; 1619 } 1620 1621 static inline int gtod_is_based_on_tsc(int mode) 1622 { 1623 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; 1624 } 1625 1626 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1627 { 1628 #ifdef CONFIG_X86_64 1629 bool vcpus_matched; 1630 struct kvm_arch *ka = &vcpu->kvm->arch; 1631 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1632 1633 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1634 atomic_read(&vcpu->kvm->online_vcpus)); 1635 1636 /* 1637 * Once the masterclock is enabled, always perform request in 1638 * order to update it. 1639 * 1640 * In order to enable masterclock, the host clocksource must be TSC 1641 * and the vcpus need to have matched TSCs. When that happens, 1642 * perform request to enable masterclock. 1643 */ 1644 if (ka->use_master_clock || 1645 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1646 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1647 1648 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1649 atomic_read(&vcpu->kvm->online_vcpus), 1650 ka->use_master_clock, gtod->clock.vclock_mode); 1651 #endif 1652 } 1653 1654 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1655 { 1656 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1657 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1658 } 1659 1660 /* 1661 * Multiply tsc by a fixed point number represented by ratio. 1662 * 1663 * The most significant 64-N bits (mult) of ratio represent the 1664 * integral part of the fixed point number; the remaining N bits 1665 * (frac) represent the fractional part, ie. ratio represents a fixed 1666 * point number (mult + frac * 2^(-N)). 1667 * 1668 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1669 */ 1670 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1671 { 1672 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1673 } 1674 1675 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1676 { 1677 u64 _tsc = tsc; 1678 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1679 1680 if (ratio != kvm_default_tsc_scaling_ratio) 1681 _tsc = __scale_tsc(ratio, tsc); 1682 1683 return _tsc; 1684 } 1685 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1686 1687 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1688 { 1689 u64 tsc; 1690 1691 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1692 1693 return target_tsc - tsc; 1694 } 1695 1696 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1697 { 1698 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1699 1700 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1701 } 1702 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1703 1704 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1705 { 1706 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset); 1707 } 1708 1709 static inline bool kvm_check_tsc_unstable(void) 1710 { 1711 #ifdef CONFIG_X86_64 1712 /* 1713 * TSC is marked unstable when we're running on Hyper-V, 1714 * 'TSC page' clocksource is good. 1715 */ 1716 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) 1717 return false; 1718 #endif 1719 return check_tsc_unstable(); 1720 } 1721 1722 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1723 { 1724 struct kvm *kvm = vcpu->kvm; 1725 u64 offset, ns, elapsed; 1726 unsigned long flags; 1727 bool matched; 1728 bool already_matched; 1729 u64 data = msr->data; 1730 bool synchronizing = false; 1731 1732 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1733 offset = kvm_compute_tsc_offset(vcpu, data); 1734 ns = ktime_get_boot_ns(); 1735 elapsed = ns - kvm->arch.last_tsc_nsec; 1736 1737 if (vcpu->arch.virtual_tsc_khz) { 1738 if (data == 0 && msr->host_initiated) { 1739 /* 1740 * detection of vcpu initialization -- need to sync 1741 * with other vCPUs. This particularly helps to keep 1742 * kvm_clock stable after CPU hotplug 1743 */ 1744 synchronizing = true; 1745 } else { 1746 u64 tsc_exp = kvm->arch.last_tsc_write + 1747 nsec_to_cycles(vcpu, elapsed); 1748 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1749 /* 1750 * Special case: TSC write with a small delta (1 second) 1751 * of virtual cycle time against real time is 1752 * interpreted as an attempt to synchronize the CPU. 1753 */ 1754 synchronizing = data < tsc_exp + tsc_hz && 1755 data + tsc_hz > tsc_exp; 1756 } 1757 } 1758 1759 /* 1760 * For a reliable TSC, we can match TSC offsets, and for an unstable 1761 * TSC, we add elapsed time in this computation. We could let the 1762 * compensation code attempt to catch up if we fall behind, but 1763 * it's better to try to match offsets from the beginning. 1764 */ 1765 if (synchronizing && 1766 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1767 if (!kvm_check_tsc_unstable()) { 1768 offset = kvm->arch.cur_tsc_offset; 1769 pr_debug("kvm: matched tsc offset for %llu\n", data); 1770 } else { 1771 u64 delta = nsec_to_cycles(vcpu, elapsed); 1772 data += delta; 1773 offset = kvm_compute_tsc_offset(vcpu, data); 1774 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1775 } 1776 matched = true; 1777 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1778 } else { 1779 /* 1780 * We split periods of matched TSC writes into generations. 1781 * For each generation, we track the original measured 1782 * nanosecond time, offset, and write, so if TSCs are in 1783 * sync, we can match exact offset, and if not, we can match 1784 * exact software computation in compute_guest_tsc() 1785 * 1786 * These values are tracked in kvm->arch.cur_xxx variables. 1787 */ 1788 kvm->arch.cur_tsc_generation++; 1789 kvm->arch.cur_tsc_nsec = ns; 1790 kvm->arch.cur_tsc_write = data; 1791 kvm->arch.cur_tsc_offset = offset; 1792 matched = false; 1793 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1794 kvm->arch.cur_tsc_generation, data); 1795 } 1796 1797 /* 1798 * We also track th most recent recorded KHZ, write and time to 1799 * allow the matching interval to be extended at each write. 1800 */ 1801 kvm->arch.last_tsc_nsec = ns; 1802 kvm->arch.last_tsc_write = data; 1803 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1804 1805 vcpu->arch.last_guest_tsc = data; 1806 1807 /* Keep track of which generation this VCPU has synchronized to */ 1808 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1809 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1810 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1811 1812 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1813 update_ia32_tsc_adjust_msr(vcpu, offset); 1814 1815 kvm_vcpu_write_tsc_offset(vcpu, offset); 1816 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1817 1818 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1819 if (!matched) { 1820 kvm->arch.nr_vcpus_matched_tsc = 0; 1821 } else if (!already_matched) { 1822 kvm->arch.nr_vcpus_matched_tsc++; 1823 } 1824 1825 kvm_track_tsc_matching(vcpu); 1826 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1827 } 1828 1829 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1830 1831 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1832 s64 adjustment) 1833 { 1834 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1835 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 1836 } 1837 1838 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1839 { 1840 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1841 WARN_ON(adjustment < 0); 1842 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1843 adjust_tsc_offset_guest(vcpu, adjustment); 1844 } 1845 1846 #ifdef CONFIG_X86_64 1847 1848 static u64 read_tsc(void) 1849 { 1850 u64 ret = (u64)rdtsc_ordered(); 1851 u64 last = pvclock_gtod_data.clock.cycle_last; 1852 1853 if (likely(ret >= last)) 1854 return ret; 1855 1856 /* 1857 * GCC likes to generate cmov here, but this branch is extremely 1858 * predictable (it's just a function of time and the likely is 1859 * very likely) and there's a data dependence, so force GCC 1860 * to generate a branch instead. I don't barrier() because 1861 * we don't actually need a barrier, and if this function 1862 * ever gets inlined it will generate worse code. 1863 */ 1864 asm volatile (""); 1865 return last; 1866 } 1867 1868 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) 1869 { 1870 long v; 1871 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1872 u64 tsc_pg_val; 1873 1874 switch (gtod->clock.vclock_mode) { 1875 case VCLOCK_HVCLOCK: 1876 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 1877 tsc_timestamp); 1878 if (tsc_pg_val != U64_MAX) { 1879 /* TSC page valid */ 1880 *mode = VCLOCK_HVCLOCK; 1881 v = (tsc_pg_val - gtod->clock.cycle_last) & 1882 gtod->clock.mask; 1883 } else { 1884 /* TSC page invalid */ 1885 *mode = VCLOCK_NONE; 1886 } 1887 break; 1888 case VCLOCK_TSC: 1889 *mode = VCLOCK_TSC; 1890 *tsc_timestamp = read_tsc(); 1891 v = (*tsc_timestamp - gtod->clock.cycle_last) & 1892 gtod->clock.mask; 1893 break; 1894 default: 1895 *mode = VCLOCK_NONE; 1896 } 1897 1898 if (*mode == VCLOCK_NONE) 1899 *tsc_timestamp = v = 0; 1900 1901 return v * gtod->clock.mult; 1902 } 1903 1904 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) 1905 { 1906 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1907 unsigned long seq; 1908 int mode; 1909 u64 ns; 1910 1911 do { 1912 seq = read_seqcount_begin(>od->seq); 1913 ns = gtod->nsec_base; 1914 ns += vgettsc(tsc_timestamp, &mode); 1915 ns >>= gtod->clock.shift; 1916 ns += gtod->boot_ns; 1917 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1918 *t = ns; 1919 1920 return mode; 1921 } 1922 1923 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 1924 { 1925 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1926 unsigned long seq; 1927 int mode; 1928 u64 ns; 1929 1930 do { 1931 seq = read_seqcount_begin(>od->seq); 1932 ts->tv_sec = gtod->wall_time_sec; 1933 ns = gtod->nsec_base; 1934 ns += vgettsc(tsc_timestamp, &mode); 1935 ns >>= gtod->clock.shift; 1936 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1937 1938 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1939 ts->tv_nsec = ns; 1940 1941 return mode; 1942 } 1943 1944 /* returns true if host is using TSC based clocksource */ 1945 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 1946 { 1947 /* checked again under seqlock below */ 1948 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1949 return false; 1950 1951 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, 1952 tsc_timestamp)); 1953 } 1954 1955 /* returns true if host is using TSC based clocksource */ 1956 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 1957 u64 *tsc_timestamp) 1958 { 1959 /* checked again under seqlock below */ 1960 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1961 return false; 1962 1963 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 1964 } 1965 #endif 1966 1967 /* 1968 * 1969 * Assuming a stable TSC across physical CPUS, and a stable TSC 1970 * across virtual CPUs, the following condition is possible. 1971 * Each numbered line represents an event visible to both 1972 * CPUs at the next numbered event. 1973 * 1974 * "timespecX" represents host monotonic time. "tscX" represents 1975 * RDTSC value. 1976 * 1977 * VCPU0 on CPU0 | VCPU1 on CPU1 1978 * 1979 * 1. read timespec0,tsc0 1980 * 2. | timespec1 = timespec0 + N 1981 * | tsc1 = tsc0 + M 1982 * 3. transition to guest | transition to guest 1983 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1984 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1985 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1986 * 1987 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1988 * 1989 * - ret0 < ret1 1990 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1991 * ... 1992 * - 0 < N - M => M < N 1993 * 1994 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1995 * always the case (the difference between two distinct xtime instances 1996 * might be smaller then the difference between corresponding TSC reads, 1997 * when updating guest vcpus pvclock areas). 1998 * 1999 * To avoid that problem, do not allow visibility of distinct 2000 * system_timestamp/tsc_timestamp values simultaneously: use a master 2001 * copy of host monotonic time values. Update that master copy 2002 * in lockstep. 2003 * 2004 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2005 * 2006 */ 2007 2008 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2009 { 2010 #ifdef CONFIG_X86_64 2011 struct kvm_arch *ka = &kvm->arch; 2012 int vclock_mode; 2013 bool host_tsc_clocksource, vcpus_matched; 2014 2015 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2016 atomic_read(&kvm->online_vcpus)); 2017 2018 /* 2019 * If the host uses TSC clock, then passthrough TSC as stable 2020 * to the guest. 2021 */ 2022 host_tsc_clocksource = kvm_get_time_and_clockread( 2023 &ka->master_kernel_ns, 2024 &ka->master_cycle_now); 2025 2026 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2027 && !ka->backwards_tsc_observed 2028 && !ka->boot_vcpu_runs_old_kvmclock; 2029 2030 if (ka->use_master_clock) 2031 atomic_set(&kvm_guest_has_master_clock, 1); 2032 2033 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2034 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2035 vcpus_matched); 2036 #endif 2037 } 2038 2039 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2040 { 2041 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2042 } 2043 2044 static void kvm_gen_update_masterclock(struct kvm *kvm) 2045 { 2046 #ifdef CONFIG_X86_64 2047 int i; 2048 struct kvm_vcpu *vcpu; 2049 struct kvm_arch *ka = &kvm->arch; 2050 2051 spin_lock(&ka->pvclock_gtod_sync_lock); 2052 kvm_make_mclock_inprogress_request(kvm); 2053 /* no guest entries from this point */ 2054 pvclock_update_vm_gtod_copy(kvm); 2055 2056 kvm_for_each_vcpu(i, vcpu, kvm) 2057 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2058 2059 /* guest entries allowed */ 2060 kvm_for_each_vcpu(i, vcpu, kvm) 2061 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2062 2063 spin_unlock(&ka->pvclock_gtod_sync_lock); 2064 #endif 2065 } 2066 2067 u64 get_kvmclock_ns(struct kvm *kvm) 2068 { 2069 struct kvm_arch *ka = &kvm->arch; 2070 struct pvclock_vcpu_time_info hv_clock; 2071 u64 ret; 2072 2073 spin_lock(&ka->pvclock_gtod_sync_lock); 2074 if (!ka->use_master_clock) { 2075 spin_unlock(&ka->pvclock_gtod_sync_lock); 2076 return ktime_get_boot_ns() + ka->kvmclock_offset; 2077 } 2078 2079 hv_clock.tsc_timestamp = ka->master_cycle_now; 2080 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2081 spin_unlock(&ka->pvclock_gtod_sync_lock); 2082 2083 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2084 get_cpu(); 2085 2086 if (__this_cpu_read(cpu_tsc_khz)) { 2087 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2088 &hv_clock.tsc_shift, 2089 &hv_clock.tsc_to_system_mul); 2090 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2091 } else 2092 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 2093 2094 put_cpu(); 2095 2096 return ret; 2097 } 2098 2099 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 2100 { 2101 struct kvm_vcpu_arch *vcpu = &v->arch; 2102 struct pvclock_vcpu_time_info guest_hv_clock; 2103 2104 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 2105 &guest_hv_clock, sizeof(guest_hv_clock)))) 2106 return; 2107 2108 /* This VCPU is paused, but it's legal for a guest to read another 2109 * VCPU's kvmclock, so we really have to follow the specification where 2110 * it says that version is odd if data is being modified, and even after 2111 * it is consistent. 2112 * 2113 * Version field updates must be kept separate. This is because 2114 * kvm_write_guest_cached might use a "rep movs" instruction, and 2115 * writes within a string instruction are weakly ordered. So there 2116 * are three writes overall. 2117 * 2118 * As a small optimization, only write the version field in the first 2119 * and third write. The vcpu->pv_time cache is still valid, because the 2120 * version field is the first in the struct. 2121 */ 2122 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2123 2124 if (guest_hv_clock.version & 1) 2125 ++guest_hv_clock.version; /* first time write, random junk */ 2126 2127 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2128 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2129 &vcpu->hv_clock, 2130 sizeof(vcpu->hv_clock.version)); 2131 2132 smp_wmb(); 2133 2134 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2135 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2136 2137 if (vcpu->pvclock_set_guest_stopped_request) { 2138 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2139 vcpu->pvclock_set_guest_stopped_request = false; 2140 } 2141 2142 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2143 2144 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2145 &vcpu->hv_clock, 2146 sizeof(vcpu->hv_clock)); 2147 2148 smp_wmb(); 2149 2150 vcpu->hv_clock.version++; 2151 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2152 &vcpu->hv_clock, 2153 sizeof(vcpu->hv_clock.version)); 2154 } 2155 2156 static int kvm_guest_time_update(struct kvm_vcpu *v) 2157 { 2158 unsigned long flags, tgt_tsc_khz; 2159 struct kvm_vcpu_arch *vcpu = &v->arch; 2160 struct kvm_arch *ka = &v->kvm->arch; 2161 s64 kernel_ns; 2162 u64 tsc_timestamp, host_tsc; 2163 u8 pvclock_flags; 2164 bool use_master_clock; 2165 2166 kernel_ns = 0; 2167 host_tsc = 0; 2168 2169 /* 2170 * If the host uses TSC clock, then passthrough TSC as stable 2171 * to the guest. 2172 */ 2173 spin_lock(&ka->pvclock_gtod_sync_lock); 2174 use_master_clock = ka->use_master_clock; 2175 if (use_master_clock) { 2176 host_tsc = ka->master_cycle_now; 2177 kernel_ns = ka->master_kernel_ns; 2178 } 2179 spin_unlock(&ka->pvclock_gtod_sync_lock); 2180 2181 /* Keep irq disabled to prevent changes to the clock */ 2182 local_irq_save(flags); 2183 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2184 if (unlikely(tgt_tsc_khz == 0)) { 2185 local_irq_restore(flags); 2186 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2187 return 1; 2188 } 2189 if (!use_master_clock) { 2190 host_tsc = rdtsc(); 2191 kernel_ns = ktime_get_boot_ns(); 2192 } 2193 2194 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2195 2196 /* 2197 * We may have to catch up the TSC to match elapsed wall clock 2198 * time for two reasons, even if kvmclock is used. 2199 * 1) CPU could have been running below the maximum TSC rate 2200 * 2) Broken TSC compensation resets the base at each VCPU 2201 * entry to avoid unknown leaps of TSC even when running 2202 * again on the same CPU. This may cause apparent elapsed 2203 * time to disappear, and the guest to stand still or run 2204 * very slowly. 2205 */ 2206 if (vcpu->tsc_catchup) { 2207 u64 tsc = compute_guest_tsc(v, kernel_ns); 2208 if (tsc > tsc_timestamp) { 2209 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2210 tsc_timestamp = tsc; 2211 } 2212 } 2213 2214 local_irq_restore(flags); 2215 2216 /* With all the info we got, fill in the values */ 2217 2218 if (kvm_has_tsc_control) 2219 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2220 2221 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2222 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2223 &vcpu->hv_clock.tsc_shift, 2224 &vcpu->hv_clock.tsc_to_system_mul); 2225 vcpu->hw_tsc_khz = tgt_tsc_khz; 2226 } 2227 2228 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2229 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2230 vcpu->last_guest_tsc = tsc_timestamp; 2231 2232 /* If the host uses TSC clocksource, then it is stable */ 2233 pvclock_flags = 0; 2234 if (use_master_clock) 2235 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2236 2237 vcpu->hv_clock.flags = pvclock_flags; 2238 2239 if (vcpu->pv_time_enabled) 2240 kvm_setup_pvclock_page(v); 2241 if (v == kvm_get_vcpu(v->kvm, 0)) 2242 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2243 return 0; 2244 } 2245 2246 /* 2247 * kvmclock updates which are isolated to a given vcpu, such as 2248 * vcpu->cpu migration, should not allow system_timestamp from 2249 * the rest of the vcpus to remain static. Otherwise ntp frequency 2250 * correction applies to one vcpu's system_timestamp but not 2251 * the others. 2252 * 2253 * So in those cases, request a kvmclock update for all vcpus. 2254 * We need to rate-limit these requests though, as they can 2255 * considerably slow guests that have a large number of vcpus. 2256 * The time for a remote vcpu to update its kvmclock is bound 2257 * by the delay we use to rate-limit the updates. 2258 */ 2259 2260 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2261 2262 static void kvmclock_update_fn(struct work_struct *work) 2263 { 2264 int i; 2265 struct delayed_work *dwork = to_delayed_work(work); 2266 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2267 kvmclock_update_work); 2268 struct kvm *kvm = container_of(ka, struct kvm, arch); 2269 struct kvm_vcpu *vcpu; 2270 2271 kvm_for_each_vcpu(i, vcpu, kvm) { 2272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2273 kvm_vcpu_kick(vcpu); 2274 } 2275 } 2276 2277 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2278 { 2279 struct kvm *kvm = v->kvm; 2280 2281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2282 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2283 KVMCLOCK_UPDATE_DELAY); 2284 } 2285 2286 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2287 2288 static void kvmclock_sync_fn(struct work_struct *work) 2289 { 2290 struct delayed_work *dwork = to_delayed_work(work); 2291 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2292 kvmclock_sync_work); 2293 struct kvm *kvm = container_of(ka, struct kvm, arch); 2294 2295 if (!kvmclock_periodic_sync) 2296 return; 2297 2298 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2299 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2300 KVMCLOCK_SYNC_PERIOD); 2301 } 2302 2303 /* 2304 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2305 */ 2306 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2307 { 2308 /* McStatusWrEn enabled? */ 2309 if (guest_cpuid_is_amd(vcpu)) 2310 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2311 2312 return false; 2313 } 2314 2315 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2316 { 2317 u64 mcg_cap = vcpu->arch.mcg_cap; 2318 unsigned bank_num = mcg_cap & 0xff; 2319 u32 msr = msr_info->index; 2320 u64 data = msr_info->data; 2321 2322 switch (msr) { 2323 case MSR_IA32_MCG_STATUS: 2324 vcpu->arch.mcg_status = data; 2325 break; 2326 case MSR_IA32_MCG_CTL: 2327 if (!(mcg_cap & MCG_CTL_P) && 2328 (data || !msr_info->host_initiated)) 2329 return 1; 2330 if (data != 0 && data != ~(u64)0) 2331 return 1; 2332 vcpu->arch.mcg_ctl = data; 2333 break; 2334 default: 2335 if (msr >= MSR_IA32_MC0_CTL && 2336 msr < MSR_IA32_MCx_CTL(bank_num)) { 2337 u32 offset = msr - MSR_IA32_MC0_CTL; 2338 /* only 0 or all 1s can be written to IA32_MCi_CTL 2339 * some Linux kernels though clear bit 10 in bank 4 to 2340 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2341 * this to avoid an uncatched #GP in the guest 2342 */ 2343 if ((offset & 0x3) == 0 && 2344 data != 0 && (data | (1 << 10)) != ~(u64)0) 2345 return -1; 2346 2347 /* MCi_STATUS */ 2348 if (!msr_info->host_initiated && 2349 (offset & 0x3) == 1 && data != 0) { 2350 if (!can_set_mci_status(vcpu)) 2351 return -1; 2352 } 2353 2354 vcpu->arch.mce_banks[offset] = data; 2355 break; 2356 } 2357 return 1; 2358 } 2359 return 0; 2360 } 2361 2362 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2363 { 2364 struct kvm *kvm = vcpu->kvm; 2365 int lm = is_long_mode(vcpu); 2366 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2367 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2368 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2369 : kvm->arch.xen_hvm_config.blob_size_32; 2370 u32 page_num = data & ~PAGE_MASK; 2371 u64 page_addr = data & PAGE_MASK; 2372 u8 *page; 2373 int r; 2374 2375 r = -E2BIG; 2376 if (page_num >= blob_size) 2377 goto out; 2378 r = -ENOMEM; 2379 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2380 if (IS_ERR(page)) { 2381 r = PTR_ERR(page); 2382 goto out; 2383 } 2384 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2385 goto out_free; 2386 r = 0; 2387 out_free: 2388 kfree(page); 2389 out: 2390 return r; 2391 } 2392 2393 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2394 { 2395 gpa_t gpa = data & ~0x3f; 2396 2397 /* Bits 3:5 are reserved, Should be zero */ 2398 if (data & 0x38) 2399 return 1; 2400 2401 vcpu->arch.apf.msr_val = data; 2402 2403 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2404 kvm_clear_async_pf_completion_queue(vcpu); 2405 kvm_async_pf_hash_reset(vcpu); 2406 return 0; 2407 } 2408 2409 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2410 sizeof(u32))) 2411 return 1; 2412 2413 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2414 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2415 kvm_async_pf_wakeup_all(vcpu); 2416 return 0; 2417 } 2418 2419 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2420 { 2421 vcpu->arch.pv_time_enabled = false; 2422 } 2423 2424 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2425 { 2426 ++vcpu->stat.tlb_flush; 2427 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); 2428 } 2429 2430 static void record_steal_time(struct kvm_vcpu *vcpu) 2431 { 2432 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2433 return; 2434 2435 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2436 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2437 return; 2438 2439 /* 2440 * Doing a TLB flush here, on the guest's behalf, can avoid 2441 * expensive IPIs. 2442 */ 2443 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) 2444 kvm_vcpu_flush_tlb(vcpu, false); 2445 2446 if (vcpu->arch.st.steal.version & 1) 2447 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2448 2449 vcpu->arch.st.steal.version += 1; 2450 2451 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2452 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2453 2454 smp_wmb(); 2455 2456 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2457 vcpu->arch.st.last_steal; 2458 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2459 2460 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2461 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2462 2463 smp_wmb(); 2464 2465 vcpu->arch.st.steal.version += 1; 2466 2467 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2468 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2469 } 2470 2471 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2472 { 2473 bool pr = false; 2474 u32 msr = msr_info->index; 2475 u64 data = msr_info->data; 2476 2477 switch (msr) { 2478 case MSR_AMD64_NB_CFG: 2479 case MSR_IA32_UCODE_WRITE: 2480 case MSR_VM_HSAVE_PA: 2481 case MSR_AMD64_PATCH_LOADER: 2482 case MSR_AMD64_BU_CFG2: 2483 case MSR_AMD64_DC_CFG: 2484 case MSR_F15H_EX_CFG: 2485 break; 2486 2487 case MSR_IA32_UCODE_REV: 2488 if (msr_info->host_initiated) 2489 vcpu->arch.microcode_version = data; 2490 break; 2491 case MSR_IA32_ARCH_CAPABILITIES: 2492 if (!msr_info->host_initiated) 2493 return 1; 2494 vcpu->arch.arch_capabilities = data; 2495 break; 2496 case MSR_EFER: 2497 return set_efer(vcpu, msr_info); 2498 case MSR_K7_HWCR: 2499 data &= ~(u64)0x40; /* ignore flush filter disable */ 2500 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2501 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2502 2503 /* Handle McStatusWrEn */ 2504 if (data == BIT_ULL(18)) { 2505 vcpu->arch.msr_hwcr = data; 2506 } else if (data != 0) { 2507 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2508 data); 2509 return 1; 2510 } 2511 break; 2512 case MSR_FAM10H_MMIO_CONF_BASE: 2513 if (data != 0) { 2514 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2515 "0x%llx\n", data); 2516 return 1; 2517 } 2518 break; 2519 case MSR_IA32_DEBUGCTLMSR: 2520 if (!data) { 2521 /* We support the non-activated case already */ 2522 break; 2523 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2524 /* Values other than LBR and BTF are vendor-specific, 2525 thus reserved and should throw a #GP */ 2526 return 1; 2527 } 2528 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2529 __func__, data); 2530 break; 2531 case 0x200 ... 0x2ff: 2532 return kvm_mtrr_set_msr(vcpu, msr, data); 2533 case MSR_IA32_APICBASE: 2534 return kvm_set_apic_base(vcpu, msr_info); 2535 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2536 return kvm_x2apic_msr_write(vcpu, msr, data); 2537 case MSR_IA32_TSCDEADLINE: 2538 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2539 break; 2540 case MSR_IA32_TSC_ADJUST: 2541 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2542 if (!msr_info->host_initiated) { 2543 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2544 adjust_tsc_offset_guest(vcpu, adj); 2545 } 2546 vcpu->arch.ia32_tsc_adjust_msr = data; 2547 } 2548 break; 2549 case MSR_IA32_MISC_ENABLE: 2550 vcpu->arch.ia32_misc_enable_msr = data; 2551 break; 2552 case MSR_IA32_SMBASE: 2553 if (!msr_info->host_initiated) 2554 return 1; 2555 vcpu->arch.smbase = data; 2556 break; 2557 case MSR_IA32_TSC: 2558 kvm_write_tsc(vcpu, msr_info); 2559 break; 2560 case MSR_SMI_COUNT: 2561 if (!msr_info->host_initiated) 2562 return 1; 2563 vcpu->arch.smi_count = data; 2564 break; 2565 case MSR_KVM_WALL_CLOCK_NEW: 2566 case MSR_KVM_WALL_CLOCK: 2567 vcpu->kvm->arch.wall_clock = data; 2568 kvm_write_wall_clock(vcpu->kvm, data); 2569 break; 2570 case MSR_KVM_SYSTEM_TIME_NEW: 2571 case MSR_KVM_SYSTEM_TIME: { 2572 struct kvm_arch *ka = &vcpu->kvm->arch; 2573 2574 kvmclock_reset(vcpu); 2575 2576 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2577 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2578 2579 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2580 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2581 2582 ka->boot_vcpu_runs_old_kvmclock = tmp; 2583 } 2584 2585 vcpu->arch.time = data; 2586 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2587 2588 /* we verify if the enable bit is set... */ 2589 if (!(data & 1)) 2590 break; 2591 2592 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2593 &vcpu->arch.pv_time, data & ~1ULL, 2594 sizeof(struct pvclock_vcpu_time_info))) 2595 vcpu->arch.pv_time_enabled = false; 2596 else 2597 vcpu->arch.pv_time_enabled = true; 2598 2599 break; 2600 } 2601 case MSR_KVM_ASYNC_PF_EN: 2602 if (kvm_pv_enable_async_pf(vcpu, data)) 2603 return 1; 2604 break; 2605 case MSR_KVM_STEAL_TIME: 2606 2607 if (unlikely(!sched_info_on())) 2608 return 1; 2609 2610 if (data & KVM_STEAL_RESERVED_MASK) 2611 return 1; 2612 2613 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2614 data & KVM_STEAL_VALID_BITS, 2615 sizeof(struct kvm_steal_time))) 2616 return 1; 2617 2618 vcpu->arch.st.msr_val = data; 2619 2620 if (!(data & KVM_MSR_ENABLED)) 2621 break; 2622 2623 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2624 2625 break; 2626 case MSR_KVM_PV_EOI_EN: 2627 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 2628 return 1; 2629 break; 2630 2631 case MSR_IA32_MCG_CTL: 2632 case MSR_IA32_MCG_STATUS: 2633 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2634 return set_msr_mce(vcpu, msr_info); 2635 2636 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2637 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2638 pr = true; /* fall through */ 2639 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2640 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2641 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2642 return kvm_pmu_set_msr(vcpu, msr_info); 2643 2644 if (pr || data != 0) 2645 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2646 "0x%x data 0x%llx\n", msr, data); 2647 break; 2648 case MSR_K7_CLK_CTL: 2649 /* 2650 * Ignore all writes to this no longer documented MSR. 2651 * Writes are only relevant for old K7 processors, 2652 * all pre-dating SVM, but a recommended workaround from 2653 * AMD for these chips. It is possible to specify the 2654 * affected processor models on the command line, hence 2655 * the need to ignore the workaround. 2656 */ 2657 break; 2658 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2659 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2660 case HV_X64_MSR_CRASH_CTL: 2661 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2662 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2663 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2664 case HV_X64_MSR_TSC_EMULATION_STATUS: 2665 return kvm_hv_set_msr_common(vcpu, msr, data, 2666 msr_info->host_initiated); 2667 case MSR_IA32_BBL_CR_CTL3: 2668 /* Drop writes to this legacy MSR -- see rdmsr 2669 * counterpart for further detail. 2670 */ 2671 if (report_ignored_msrs) 2672 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2673 msr, data); 2674 break; 2675 case MSR_AMD64_OSVW_ID_LENGTH: 2676 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2677 return 1; 2678 vcpu->arch.osvw.length = data; 2679 break; 2680 case MSR_AMD64_OSVW_STATUS: 2681 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2682 return 1; 2683 vcpu->arch.osvw.status = data; 2684 break; 2685 case MSR_PLATFORM_INFO: 2686 if (!msr_info->host_initiated || 2687 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2688 cpuid_fault_enabled(vcpu))) 2689 return 1; 2690 vcpu->arch.msr_platform_info = data; 2691 break; 2692 case MSR_MISC_FEATURES_ENABLES: 2693 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2694 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2695 !supports_cpuid_fault(vcpu))) 2696 return 1; 2697 vcpu->arch.msr_misc_features_enables = data; 2698 break; 2699 default: 2700 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2701 return xen_hvm_config(vcpu, data); 2702 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2703 return kvm_pmu_set_msr(vcpu, msr_info); 2704 if (!ignore_msrs) { 2705 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2706 msr, data); 2707 return 1; 2708 } else { 2709 if (report_ignored_msrs) 2710 vcpu_unimpl(vcpu, 2711 "ignored wrmsr: 0x%x data 0x%llx\n", 2712 msr, data); 2713 break; 2714 } 2715 } 2716 return 0; 2717 } 2718 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2719 2720 2721 /* 2722 * Reads an msr value (of 'msr_index') into 'pdata'. 2723 * Returns 0 on success, non-0 otherwise. 2724 * Assumes vcpu_load() was already called. 2725 */ 2726 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2727 { 2728 return kvm_x86_ops->get_msr(vcpu, msr); 2729 } 2730 EXPORT_SYMBOL_GPL(kvm_get_msr); 2731 2732 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 2733 { 2734 u64 data; 2735 u64 mcg_cap = vcpu->arch.mcg_cap; 2736 unsigned bank_num = mcg_cap & 0xff; 2737 2738 switch (msr) { 2739 case MSR_IA32_P5_MC_ADDR: 2740 case MSR_IA32_P5_MC_TYPE: 2741 data = 0; 2742 break; 2743 case MSR_IA32_MCG_CAP: 2744 data = vcpu->arch.mcg_cap; 2745 break; 2746 case MSR_IA32_MCG_CTL: 2747 if (!(mcg_cap & MCG_CTL_P) && !host) 2748 return 1; 2749 data = vcpu->arch.mcg_ctl; 2750 break; 2751 case MSR_IA32_MCG_STATUS: 2752 data = vcpu->arch.mcg_status; 2753 break; 2754 default: 2755 if (msr >= MSR_IA32_MC0_CTL && 2756 msr < MSR_IA32_MCx_CTL(bank_num)) { 2757 u32 offset = msr - MSR_IA32_MC0_CTL; 2758 data = vcpu->arch.mce_banks[offset]; 2759 break; 2760 } 2761 return 1; 2762 } 2763 *pdata = data; 2764 return 0; 2765 } 2766 2767 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2768 { 2769 switch (msr_info->index) { 2770 case MSR_IA32_PLATFORM_ID: 2771 case MSR_IA32_EBL_CR_POWERON: 2772 case MSR_IA32_DEBUGCTLMSR: 2773 case MSR_IA32_LASTBRANCHFROMIP: 2774 case MSR_IA32_LASTBRANCHTOIP: 2775 case MSR_IA32_LASTINTFROMIP: 2776 case MSR_IA32_LASTINTTOIP: 2777 case MSR_K8_SYSCFG: 2778 case MSR_K8_TSEG_ADDR: 2779 case MSR_K8_TSEG_MASK: 2780 case MSR_VM_HSAVE_PA: 2781 case MSR_K8_INT_PENDING_MSG: 2782 case MSR_AMD64_NB_CFG: 2783 case MSR_FAM10H_MMIO_CONF_BASE: 2784 case MSR_AMD64_BU_CFG2: 2785 case MSR_IA32_PERF_CTL: 2786 case MSR_AMD64_DC_CFG: 2787 case MSR_F15H_EX_CFG: 2788 msr_info->data = 0; 2789 break; 2790 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 2791 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2792 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2793 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2794 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2795 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2796 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2797 msr_info->data = 0; 2798 break; 2799 case MSR_IA32_UCODE_REV: 2800 msr_info->data = vcpu->arch.microcode_version; 2801 break; 2802 case MSR_IA32_ARCH_CAPABILITIES: 2803 if (!msr_info->host_initiated && 2804 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 2805 return 1; 2806 msr_info->data = vcpu->arch.arch_capabilities; 2807 break; 2808 case MSR_IA32_TSC: 2809 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; 2810 break; 2811 case MSR_MTRRcap: 2812 case 0x200 ... 0x2ff: 2813 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2814 case 0xcd: /* fsb frequency */ 2815 msr_info->data = 3; 2816 break; 2817 /* 2818 * MSR_EBC_FREQUENCY_ID 2819 * Conservative value valid for even the basic CPU models. 2820 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2821 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2822 * and 266MHz for model 3, or 4. Set Core Clock 2823 * Frequency to System Bus Frequency Ratio to 1 (bits 2824 * 31:24) even though these are only valid for CPU 2825 * models > 2, however guests may end up dividing or 2826 * multiplying by zero otherwise. 2827 */ 2828 case MSR_EBC_FREQUENCY_ID: 2829 msr_info->data = 1 << 24; 2830 break; 2831 case MSR_IA32_APICBASE: 2832 msr_info->data = kvm_get_apic_base(vcpu); 2833 break; 2834 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2835 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2836 break; 2837 case MSR_IA32_TSCDEADLINE: 2838 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2839 break; 2840 case MSR_IA32_TSC_ADJUST: 2841 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2842 break; 2843 case MSR_IA32_MISC_ENABLE: 2844 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2845 break; 2846 case MSR_IA32_SMBASE: 2847 if (!msr_info->host_initiated) 2848 return 1; 2849 msr_info->data = vcpu->arch.smbase; 2850 break; 2851 case MSR_SMI_COUNT: 2852 msr_info->data = vcpu->arch.smi_count; 2853 break; 2854 case MSR_IA32_PERF_STATUS: 2855 /* TSC increment by tick */ 2856 msr_info->data = 1000ULL; 2857 /* CPU multiplier */ 2858 msr_info->data |= (((uint64_t)4ULL) << 40); 2859 break; 2860 case MSR_EFER: 2861 msr_info->data = vcpu->arch.efer; 2862 break; 2863 case MSR_KVM_WALL_CLOCK: 2864 case MSR_KVM_WALL_CLOCK_NEW: 2865 msr_info->data = vcpu->kvm->arch.wall_clock; 2866 break; 2867 case MSR_KVM_SYSTEM_TIME: 2868 case MSR_KVM_SYSTEM_TIME_NEW: 2869 msr_info->data = vcpu->arch.time; 2870 break; 2871 case MSR_KVM_ASYNC_PF_EN: 2872 msr_info->data = vcpu->arch.apf.msr_val; 2873 break; 2874 case MSR_KVM_STEAL_TIME: 2875 msr_info->data = vcpu->arch.st.msr_val; 2876 break; 2877 case MSR_KVM_PV_EOI_EN: 2878 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2879 break; 2880 case MSR_IA32_P5_MC_ADDR: 2881 case MSR_IA32_P5_MC_TYPE: 2882 case MSR_IA32_MCG_CAP: 2883 case MSR_IA32_MCG_CTL: 2884 case MSR_IA32_MCG_STATUS: 2885 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2886 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 2887 msr_info->host_initiated); 2888 case MSR_K7_CLK_CTL: 2889 /* 2890 * Provide expected ramp-up count for K7. All other 2891 * are set to zero, indicating minimum divisors for 2892 * every field. 2893 * 2894 * This prevents guest kernels on AMD host with CPU 2895 * type 6, model 8 and higher from exploding due to 2896 * the rdmsr failing. 2897 */ 2898 msr_info->data = 0x20000000; 2899 break; 2900 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2901 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2902 case HV_X64_MSR_CRASH_CTL: 2903 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2904 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2905 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2906 case HV_X64_MSR_TSC_EMULATION_STATUS: 2907 return kvm_hv_get_msr_common(vcpu, 2908 msr_info->index, &msr_info->data, 2909 msr_info->host_initiated); 2910 break; 2911 case MSR_IA32_BBL_CR_CTL3: 2912 /* This legacy MSR exists but isn't fully documented in current 2913 * silicon. It is however accessed by winxp in very narrow 2914 * scenarios where it sets bit #19, itself documented as 2915 * a "reserved" bit. Best effort attempt to source coherent 2916 * read data here should the balance of the register be 2917 * interpreted by the guest: 2918 * 2919 * L2 cache control register 3: 64GB range, 256KB size, 2920 * enabled, latency 0x1, configured 2921 */ 2922 msr_info->data = 0xbe702111; 2923 break; 2924 case MSR_AMD64_OSVW_ID_LENGTH: 2925 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2926 return 1; 2927 msr_info->data = vcpu->arch.osvw.length; 2928 break; 2929 case MSR_AMD64_OSVW_STATUS: 2930 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2931 return 1; 2932 msr_info->data = vcpu->arch.osvw.status; 2933 break; 2934 case MSR_PLATFORM_INFO: 2935 if (!msr_info->host_initiated && 2936 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 2937 return 1; 2938 msr_info->data = vcpu->arch.msr_platform_info; 2939 break; 2940 case MSR_MISC_FEATURES_ENABLES: 2941 msr_info->data = vcpu->arch.msr_misc_features_enables; 2942 break; 2943 case MSR_K7_HWCR: 2944 msr_info->data = vcpu->arch.msr_hwcr; 2945 break; 2946 default: 2947 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2948 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2949 if (!ignore_msrs) { 2950 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2951 msr_info->index); 2952 return 1; 2953 } else { 2954 if (report_ignored_msrs) 2955 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2956 msr_info->index); 2957 msr_info->data = 0; 2958 } 2959 break; 2960 } 2961 return 0; 2962 } 2963 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2964 2965 /* 2966 * Read or write a bunch of msrs. All parameters are kernel addresses. 2967 * 2968 * @return number of msrs set successfully. 2969 */ 2970 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2971 struct kvm_msr_entry *entries, 2972 int (*do_msr)(struct kvm_vcpu *vcpu, 2973 unsigned index, u64 *data)) 2974 { 2975 int i; 2976 2977 for (i = 0; i < msrs->nmsrs; ++i) 2978 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2979 break; 2980 2981 return i; 2982 } 2983 2984 /* 2985 * Read or write a bunch of msrs. Parameters are user addresses. 2986 * 2987 * @return number of msrs set successfully. 2988 */ 2989 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2990 int (*do_msr)(struct kvm_vcpu *vcpu, 2991 unsigned index, u64 *data), 2992 int writeback) 2993 { 2994 struct kvm_msrs msrs; 2995 struct kvm_msr_entry *entries; 2996 int r, n; 2997 unsigned size; 2998 2999 r = -EFAULT; 3000 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3001 goto out; 3002 3003 r = -E2BIG; 3004 if (msrs.nmsrs >= MAX_IO_MSRS) 3005 goto out; 3006 3007 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3008 entries = memdup_user(user_msrs->entries, size); 3009 if (IS_ERR(entries)) { 3010 r = PTR_ERR(entries); 3011 goto out; 3012 } 3013 3014 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3015 if (r < 0) 3016 goto out_free; 3017 3018 r = -EFAULT; 3019 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3020 goto out_free; 3021 3022 r = n; 3023 3024 out_free: 3025 kfree(entries); 3026 out: 3027 return r; 3028 } 3029 3030 static inline bool kvm_can_mwait_in_guest(void) 3031 { 3032 return boot_cpu_has(X86_FEATURE_MWAIT) && 3033 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3034 boot_cpu_has(X86_FEATURE_ARAT); 3035 } 3036 3037 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3038 { 3039 int r = 0; 3040 3041 switch (ext) { 3042 case KVM_CAP_IRQCHIP: 3043 case KVM_CAP_HLT: 3044 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3045 case KVM_CAP_SET_TSS_ADDR: 3046 case KVM_CAP_EXT_CPUID: 3047 case KVM_CAP_EXT_EMUL_CPUID: 3048 case KVM_CAP_CLOCKSOURCE: 3049 case KVM_CAP_PIT: 3050 case KVM_CAP_NOP_IO_DELAY: 3051 case KVM_CAP_MP_STATE: 3052 case KVM_CAP_SYNC_MMU: 3053 case KVM_CAP_USER_NMI: 3054 case KVM_CAP_REINJECT_CONTROL: 3055 case KVM_CAP_IRQ_INJECT_STATUS: 3056 case KVM_CAP_IOEVENTFD: 3057 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3058 case KVM_CAP_PIT2: 3059 case KVM_CAP_PIT_STATE2: 3060 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3061 case KVM_CAP_XEN_HVM: 3062 case KVM_CAP_VCPU_EVENTS: 3063 case KVM_CAP_HYPERV: 3064 case KVM_CAP_HYPERV_VAPIC: 3065 case KVM_CAP_HYPERV_SPIN: 3066 case KVM_CAP_HYPERV_SYNIC: 3067 case KVM_CAP_HYPERV_SYNIC2: 3068 case KVM_CAP_HYPERV_VP_INDEX: 3069 case KVM_CAP_HYPERV_EVENTFD: 3070 case KVM_CAP_HYPERV_TLBFLUSH: 3071 case KVM_CAP_HYPERV_SEND_IPI: 3072 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3073 case KVM_CAP_HYPERV_CPUID: 3074 case KVM_CAP_PCI_SEGMENT: 3075 case KVM_CAP_DEBUGREGS: 3076 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3077 case KVM_CAP_XSAVE: 3078 case KVM_CAP_ASYNC_PF: 3079 case KVM_CAP_GET_TSC_KHZ: 3080 case KVM_CAP_KVMCLOCK_CTRL: 3081 case KVM_CAP_READONLY_MEM: 3082 case KVM_CAP_HYPERV_TIME: 3083 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3084 case KVM_CAP_TSC_DEADLINE_TIMER: 3085 case KVM_CAP_DISABLE_QUIRKS: 3086 case KVM_CAP_SET_BOOT_CPU_ID: 3087 case KVM_CAP_SPLIT_IRQCHIP: 3088 case KVM_CAP_IMMEDIATE_EXIT: 3089 case KVM_CAP_GET_MSR_FEATURES: 3090 case KVM_CAP_MSR_PLATFORM_INFO: 3091 case KVM_CAP_EXCEPTION_PAYLOAD: 3092 r = 1; 3093 break; 3094 case KVM_CAP_SYNC_REGS: 3095 r = KVM_SYNC_X86_VALID_FIELDS; 3096 break; 3097 case KVM_CAP_ADJUST_CLOCK: 3098 r = KVM_CLOCK_TSC_STABLE; 3099 break; 3100 case KVM_CAP_X86_DISABLE_EXITS: 3101 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE; 3102 if(kvm_can_mwait_in_guest()) 3103 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3104 break; 3105 case KVM_CAP_X86_SMM: 3106 /* SMBASE is usually relocated above 1M on modern chipsets, 3107 * and SMM handlers might indeed rely on 4G segment limits, 3108 * so do not report SMM to be available if real mode is 3109 * emulated via vm86 mode. Still, do not go to great lengths 3110 * to avoid userspace's usage of the feature, because it is a 3111 * fringe case that is not enabled except via specific settings 3112 * of the module parameters. 3113 */ 3114 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE); 3115 break; 3116 case KVM_CAP_VAPIC: 3117 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 3118 break; 3119 case KVM_CAP_NR_VCPUS: 3120 r = KVM_SOFT_MAX_VCPUS; 3121 break; 3122 case KVM_CAP_MAX_VCPUS: 3123 r = KVM_MAX_VCPUS; 3124 break; 3125 case KVM_CAP_PV_MMU: /* obsolete */ 3126 r = 0; 3127 break; 3128 case KVM_CAP_MCE: 3129 r = KVM_MAX_MCE_BANKS; 3130 break; 3131 case KVM_CAP_XCRS: 3132 r = boot_cpu_has(X86_FEATURE_XSAVE); 3133 break; 3134 case KVM_CAP_TSC_CONTROL: 3135 r = kvm_has_tsc_control; 3136 break; 3137 case KVM_CAP_X2APIC_API: 3138 r = KVM_X2APIC_API_VALID_FLAGS; 3139 break; 3140 case KVM_CAP_NESTED_STATE: 3141 r = kvm_x86_ops->get_nested_state ? 3142 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0; 3143 break; 3144 default: 3145 break; 3146 } 3147 return r; 3148 3149 } 3150 3151 long kvm_arch_dev_ioctl(struct file *filp, 3152 unsigned int ioctl, unsigned long arg) 3153 { 3154 void __user *argp = (void __user *)arg; 3155 long r; 3156 3157 switch (ioctl) { 3158 case KVM_GET_MSR_INDEX_LIST: { 3159 struct kvm_msr_list __user *user_msr_list = argp; 3160 struct kvm_msr_list msr_list; 3161 unsigned n; 3162 3163 r = -EFAULT; 3164 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3165 goto out; 3166 n = msr_list.nmsrs; 3167 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3168 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3169 goto out; 3170 r = -E2BIG; 3171 if (n < msr_list.nmsrs) 3172 goto out; 3173 r = -EFAULT; 3174 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3175 num_msrs_to_save * sizeof(u32))) 3176 goto out; 3177 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3178 &emulated_msrs, 3179 num_emulated_msrs * sizeof(u32))) 3180 goto out; 3181 r = 0; 3182 break; 3183 } 3184 case KVM_GET_SUPPORTED_CPUID: 3185 case KVM_GET_EMULATED_CPUID: { 3186 struct kvm_cpuid2 __user *cpuid_arg = argp; 3187 struct kvm_cpuid2 cpuid; 3188 3189 r = -EFAULT; 3190 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3191 goto out; 3192 3193 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3194 ioctl); 3195 if (r) 3196 goto out; 3197 3198 r = -EFAULT; 3199 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3200 goto out; 3201 r = 0; 3202 break; 3203 } 3204 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 3205 r = -EFAULT; 3206 if (copy_to_user(argp, &kvm_mce_cap_supported, 3207 sizeof(kvm_mce_cap_supported))) 3208 goto out; 3209 r = 0; 3210 break; 3211 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3212 struct kvm_msr_list __user *user_msr_list = argp; 3213 struct kvm_msr_list msr_list; 3214 unsigned int n; 3215 3216 r = -EFAULT; 3217 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3218 goto out; 3219 n = msr_list.nmsrs; 3220 msr_list.nmsrs = num_msr_based_features; 3221 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3222 goto out; 3223 r = -E2BIG; 3224 if (n < msr_list.nmsrs) 3225 goto out; 3226 r = -EFAULT; 3227 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3228 num_msr_based_features * sizeof(u32))) 3229 goto out; 3230 r = 0; 3231 break; 3232 } 3233 case KVM_GET_MSRS: 3234 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3235 break; 3236 } 3237 default: 3238 r = -EINVAL; 3239 } 3240 out: 3241 return r; 3242 } 3243 3244 static void wbinvd_ipi(void *garbage) 3245 { 3246 wbinvd(); 3247 } 3248 3249 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3250 { 3251 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3252 } 3253 3254 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3255 { 3256 /* Address WBINVD may be executed by guest */ 3257 if (need_emulate_wbinvd(vcpu)) { 3258 if (kvm_x86_ops->has_wbinvd_exit()) 3259 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3260 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3261 smp_call_function_single(vcpu->cpu, 3262 wbinvd_ipi, NULL, 1); 3263 } 3264 3265 kvm_x86_ops->vcpu_load(vcpu, cpu); 3266 3267 /* Apply any externally detected TSC adjustments (due to suspend) */ 3268 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3269 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3270 vcpu->arch.tsc_offset_adjustment = 0; 3271 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3272 } 3273 3274 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3275 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3276 rdtsc() - vcpu->arch.last_host_tsc; 3277 if (tsc_delta < 0) 3278 mark_tsc_unstable("KVM discovered backwards TSC"); 3279 3280 if (kvm_check_tsc_unstable()) { 3281 u64 offset = kvm_compute_tsc_offset(vcpu, 3282 vcpu->arch.last_guest_tsc); 3283 kvm_vcpu_write_tsc_offset(vcpu, offset); 3284 vcpu->arch.tsc_catchup = 1; 3285 } 3286 3287 if (kvm_lapic_hv_timer_in_use(vcpu)) 3288 kvm_lapic_restart_hv_timer(vcpu); 3289 3290 /* 3291 * On a host with synchronized TSC, there is no need to update 3292 * kvmclock on vcpu->cpu migration 3293 */ 3294 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3295 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3296 if (vcpu->cpu != cpu) 3297 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3298 vcpu->cpu = cpu; 3299 } 3300 3301 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3302 } 3303 3304 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3305 { 3306 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3307 return; 3308 3309 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; 3310 3311 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 3312 &vcpu->arch.st.steal.preempted, 3313 offsetof(struct kvm_steal_time, preempted), 3314 sizeof(vcpu->arch.st.steal.preempted)); 3315 } 3316 3317 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3318 { 3319 int idx; 3320 3321 if (vcpu->preempted) 3322 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 3323 3324 /* 3325 * Disable page faults because we're in atomic context here. 3326 * kvm_write_guest_offset_cached() would call might_fault() 3327 * that relies on pagefault_disable() to tell if there's a 3328 * bug. NOTE: the write to guest memory may not go through if 3329 * during postcopy live migration or if there's heavy guest 3330 * paging. 3331 */ 3332 pagefault_disable(); 3333 /* 3334 * kvm_memslots() will be called by 3335 * kvm_write_guest_offset_cached() so take the srcu lock. 3336 */ 3337 idx = srcu_read_lock(&vcpu->kvm->srcu); 3338 kvm_steal_time_set_preempted(vcpu); 3339 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3340 pagefault_enable(); 3341 kvm_x86_ops->vcpu_put(vcpu); 3342 vcpu->arch.last_host_tsc = rdtsc(); 3343 /* 3344 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3345 * on every vmexit, but if not, we might have a stale dr6 from the 3346 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3347 */ 3348 set_debugreg(0, 6); 3349 } 3350 3351 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3352 struct kvm_lapic_state *s) 3353 { 3354 if (vcpu->arch.apicv_active) 3355 kvm_x86_ops->sync_pir_to_irr(vcpu); 3356 3357 return kvm_apic_get_state(vcpu, s); 3358 } 3359 3360 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3361 struct kvm_lapic_state *s) 3362 { 3363 int r; 3364 3365 r = kvm_apic_set_state(vcpu, s); 3366 if (r) 3367 return r; 3368 update_cr8_intercept(vcpu); 3369 3370 return 0; 3371 } 3372 3373 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3374 { 3375 return (!lapic_in_kernel(vcpu) || 3376 kvm_apic_accept_pic_intr(vcpu)); 3377 } 3378 3379 /* 3380 * if userspace requested an interrupt window, check that the 3381 * interrupt window is open. 3382 * 3383 * No need to exit to userspace if we already have an interrupt queued. 3384 */ 3385 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3386 { 3387 return kvm_arch_interrupt_allowed(vcpu) && 3388 !kvm_cpu_has_interrupt(vcpu) && 3389 !kvm_event_needs_reinjection(vcpu) && 3390 kvm_cpu_accept_dm_intr(vcpu); 3391 } 3392 3393 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3394 struct kvm_interrupt *irq) 3395 { 3396 if (irq->irq >= KVM_NR_INTERRUPTS) 3397 return -EINVAL; 3398 3399 if (!irqchip_in_kernel(vcpu->kvm)) { 3400 kvm_queue_interrupt(vcpu, irq->irq, false); 3401 kvm_make_request(KVM_REQ_EVENT, vcpu); 3402 return 0; 3403 } 3404 3405 /* 3406 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3407 * fail for in-kernel 8259. 3408 */ 3409 if (pic_in_kernel(vcpu->kvm)) 3410 return -ENXIO; 3411 3412 if (vcpu->arch.pending_external_vector != -1) 3413 return -EEXIST; 3414 3415 vcpu->arch.pending_external_vector = irq->irq; 3416 kvm_make_request(KVM_REQ_EVENT, vcpu); 3417 return 0; 3418 } 3419 3420 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3421 { 3422 kvm_inject_nmi(vcpu); 3423 3424 return 0; 3425 } 3426 3427 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3428 { 3429 kvm_make_request(KVM_REQ_SMI, vcpu); 3430 3431 return 0; 3432 } 3433 3434 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3435 struct kvm_tpr_access_ctl *tac) 3436 { 3437 if (tac->flags) 3438 return -EINVAL; 3439 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3440 return 0; 3441 } 3442 3443 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3444 u64 mcg_cap) 3445 { 3446 int r; 3447 unsigned bank_num = mcg_cap & 0xff, bank; 3448 3449 r = -EINVAL; 3450 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3451 goto out; 3452 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3453 goto out; 3454 r = 0; 3455 vcpu->arch.mcg_cap = mcg_cap; 3456 /* Init IA32_MCG_CTL to all 1s */ 3457 if (mcg_cap & MCG_CTL_P) 3458 vcpu->arch.mcg_ctl = ~(u64)0; 3459 /* Init IA32_MCi_CTL to all 1s */ 3460 for (bank = 0; bank < bank_num; bank++) 3461 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3462 3463 if (kvm_x86_ops->setup_mce) 3464 kvm_x86_ops->setup_mce(vcpu); 3465 out: 3466 return r; 3467 } 3468 3469 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3470 struct kvm_x86_mce *mce) 3471 { 3472 u64 mcg_cap = vcpu->arch.mcg_cap; 3473 unsigned bank_num = mcg_cap & 0xff; 3474 u64 *banks = vcpu->arch.mce_banks; 3475 3476 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3477 return -EINVAL; 3478 /* 3479 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3480 * reporting is disabled 3481 */ 3482 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3483 vcpu->arch.mcg_ctl != ~(u64)0) 3484 return 0; 3485 banks += 4 * mce->bank; 3486 /* 3487 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3488 * reporting is disabled for the bank 3489 */ 3490 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3491 return 0; 3492 if (mce->status & MCI_STATUS_UC) { 3493 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3494 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3495 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3496 return 0; 3497 } 3498 if (banks[1] & MCI_STATUS_VAL) 3499 mce->status |= MCI_STATUS_OVER; 3500 banks[2] = mce->addr; 3501 banks[3] = mce->misc; 3502 vcpu->arch.mcg_status = mce->mcg_status; 3503 banks[1] = mce->status; 3504 kvm_queue_exception(vcpu, MC_VECTOR); 3505 } else if (!(banks[1] & MCI_STATUS_VAL) 3506 || !(banks[1] & MCI_STATUS_UC)) { 3507 if (banks[1] & MCI_STATUS_VAL) 3508 mce->status |= MCI_STATUS_OVER; 3509 banks[2] = mce->addr; 3510 banks[3] = mce->misc; 3511 banks[1] = mce->status; 3512 } else 3513 banks[1] |= MCI_STATUS_OVER; 3514 return 0; 3515 } 3516 3517 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3518 struct kvm_vcpu_events *events) 3519 { 3520 process_nmi(vcpu); 3521 3522 /* 3523 * The API doesn't provide the instruction length for software 3524 * exceptions, so don't report them. As long as the guest RIP 3525 * isn't advanced, we should expect to encounter the exception 3526 * again. 3527 */ 3528 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 3529 events->exception.injected = 0; 3530 events->exception.pending = 0; 3531 } else { 3532 events->exception.injected = vcpu->arch.exception.injected; 3533 events->exception.pending = vcpu->arch.exception.pending; 3534 /* 3535 * For ABI compatibility, deliberately conflate 3536 * pending and injected exceptions when 3537 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 3538 */ 3539 if (!vcpu->kvm->arch.exception_payload_enabled) 3540 events->exception.injected |= 3541 vcpu->arch.exception.pending; 3542 } 3543 events->exception.nr = vcpu->arch.exception.nr; 3544 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3545 events->exception.error_code = vcpu->arch.exception.error_code; 3546 events->exception_has_payload = vcpu->arch.exception.has_payload; 3547 events->exception_payload = vcpu->arch.exception.payload; 3548 3549 events->interrupt.injected = 3550 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3551 events->interrupt.nr = vcpu->arch.interrupt.nr; 3552 events->interrupt.soft = 0; 3553 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3554 3555 events->nmi.injected = vcpu->arch.nmi_injected; 3556 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3557 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3558 events->nmi.pad = 0; 3559 3560 events->sipi_vector = 0; /* never valid when reporting to user space */ 3561 3562 events->smi.smm = is_smm(vcpu); 3563 events->smi.pending = vcpu->arch.smi_pending; 3564 events->smi.smm_inside_nmi = 3565 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3566 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3567 3568 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3569 | KVM_VCPUEVENT_VALID_SHADOW 3570 | KVM_VCPUEVENT_VALID_SMM); 3571 if (vcpu->kvm->arch.exception_payload_enabled) 3572 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 3573 3574 memset(&events->reserved, 0, sizeof(events->reserved)); 3575 } 3576 3577 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 3578 3579 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3580 struct kvm_vcpu_events *events) 3581 { 3582 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3583 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3584 | KVM_VCPUEVENT_VALID_SHADOW 3585 | KVM_VCPUEVENT_VALID_SMM 3586 | KVM_VCPUEVENT_VALID_PAYLOAD)) 3587 return -EINVAL; 3588 3589 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 3590 if (!vcpu->kvm->arch.exception_payload_enabled) 3591 return -EINVAL; 3592 if (events->exception.pending) 3593 events->exception.injected = 0; 3594 else 3595 events->exception_has_payload = 0; 3596 } else { 3597 events->exception.pending = 0; 3598 events->exception_has_payload = 0; 3599 } 3600 3601 if ((events->exception.injected || events->exception.pending) && 3602 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 3603 return -EINVAL; 3604 3605 /* INITs are latched while in SMM */ 3606 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3607 (events->smi.smm || events->smi.pending) && 3608 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3609 return -EINVAL; 3610 3611 process_nmi(vcpu); 3612 vcpu->arch.exception.injected = events->exception.injected; 3613 vcpu->arch.exception.pending = events->exception.pending; 3614 vcpu->arch.exception.nr = events->exception.nr; 3615 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3616 vcpu->arch.exception.error_code = events->exception.error_code; 3617 vcpu->arch.exception.has_payload = events->exception_has_payload; 3618 vcpu->arch.exception.payload = events->exception_payload; 3619 3620 vcpu->arch.interrupt.injected = events->interrupt.injected; 3621 vcpu->arch.interrupt.nr = events->interrupt.nr; 3622 vcpu->arch.interrupt.soft = events->interrupt.soft; 3623 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3624 kvm_x86_ops->set_interrupt_shadow(vcpu, 3625 events->interrupt.shadow); 3626 3627 vcpu->arch.nmi_injected = events->nmi.injected; 3628 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3629 vcpu->arch.nmi_pending = events->nmi.pending; 3630 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3631 3632 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3633 lapic_in_kernel(vcpu)) 3634 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3635 3636 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3637 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 3638 if (events->smi.smm) 3639 vcpu->arch.hflags |= HF_SMM_MASK; 3640 else 3641 vcpu->arch.hflags &= ~HF_SMM_MASK; 3642 kvm_smm_changed(vcpu); 3643 } 3644 3645 vcpu->arch.smi_pending = events->smi.pending; 3646 3647 if (events->smi.smm) { 3648 if (events->smi.smm_inside_nmi) 3649 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3650 else 3651 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3652 if (lapic_in_kernel(vcpu)) { 3653 if (events->smi.latched_init) 3654 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3655 else 3656 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3657 } 3658 } 3659 } 3660 3661 kvm_make_request(KVM_REQ_EVENT, vcpu); 3662 3663 return 0; 3664 } 3665 3666 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3667 struct kvm_debugregs *dbgregs) 3668 { 3669 unsigned long val; 3670 3671 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3672 kvm_get_dr(vcpu, 6, &val); 3673 dbgregs->dr6 = val; 3674 dbgregs->dr7 = vcpu->arch.dr7; 3675 dbgregs->flags = 0; 3676 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3677 } 3678 3679 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3680 struct kvm_debugregs *dbgregs) 3681 { 3682 if (dbgregs->flags) 3683 return -EINVAL; 3684 3685 if (dbgregs->dr6 & ~0xffffffffull) 3686 return -EINVAL; 3687 if (dbgregs->dr7 & ~0xffffffffull) 3688 return -EINVAL; 3689 3690 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3691 kvm_update_dr0123(vcpu); 3692 vcpu->arch.dr6 = dbgregs->dr6; 3693 kvm_update_dr6(vcpu); 3694 vcpu->arch.dr7 = dbgregs->dr7; 3695 kvm_update_dr7(vcpu); 3696 3697 return 0; 3698 } 3699 3700 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3701 3702 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3703 { 3704 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 3705 u64 xstate_bv = xsave->header.xfeatures; 3706 u64 valid; 3707 3708 /* 3709 * Copy legacy XSAVE area, to avoid complications with CPUID 3710 * leaves 0 and 1 in the loop below. 3711 */ 3712 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3713 3714 /* Set XSTATE_BV */ 3715 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3716 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3717 3718 /* 3719 * Copy each region from the possibly compacted offset to the 3720 * non-compacted offset. 3721 */ 3722 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3723 while (valid) { 3724 u64 xfeature_mask = valid & -valid; 3725 int xfeature_nr = fls64(xfeature_mask) - 1; 3726 void *src = get_xsave_addr(xsave, xfeature_nr); 3727 3728 if (src) { 3729 u32 size, offset, ecx, edx; 3730 cpuid_count(XSTATE_CPUID, xfeature_nr, 3731 &size, &offset, &ecx, &edx); 3732 if (xfeature_nr == XFEATURE_PKRU) 3733 memcpy(dest + offset, &vcpu->arch.pkru, 3734 sizeof(vcpu->arch.pkru)); 3735 else 3736 memcpy(dest + offset, src, size); 3737 3738 } 3739 3740 valid -= xfeature_mask; 3741 } 3742 } 3743 3744 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3745 { 3746 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 3747 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3748 u64 valid; 3749 3750 /* 3751 * Copy legacy XSAVE area, to avoid complications with CPUID 3752 * leaves 0 and 1 in the loop below. 3753 */ 3754 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3755 3756 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3757 xsave->header.xfeatures = xstate_bv; 3758 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3759 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3760 3761 /* 3762 * Copy each region from the non-compacted offset to the 3763 * possibly compacted offset. 3764 */ 3765 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3766 while (valid) { 3767 u64 xfeature_mask = valid & -valid; 3768 int xfeature_nr = fls64(xfeature_mask) - 1; 3769 void *dest = get_xsave_addr(xsave, xfeature_nr); 3770 3771 if (dest) { 3772 u32 size, offset, ecx, edx; 3773 cpuid_count(XSTATE_CPUID, xfeature_nr, 3774 &size, &offset, &ecx, &edx); 3775 if (xfeature_nr == XFEATURE_PKRU) 3776 memcpy(&vcpu->arch.pkru, src + offset, 3777 sizeof(vcpu->arch.pkru)); 3778 else 3779 memcpy(dest, src + offset, size); 3780 } 3781 3782 valid -= xfeature_mask; 3783 } 3784 } 3785 3786 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3787 struct kvm_xsave *guest_xsave) 3788 { 3789 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3790 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3791 fill_xsave((u8 *) guest_xsave->region, vcpu); 3792 } else { 3793 memcpy(guest_xsave->region, 3794 &vcpu->arch.guest_fpu->state.fxsave, 3795 sizeof(struct fxregs_state)); 3796 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3797 XFEATURE_MASK_FPSSE; 3798 } 3799 } 3800 3801 #define XSAVE_MXCSR_OFFSET 24 3802 3803 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3804 struct kvm_xsave *guest_xsave) 3805 { 3806 u64 xstate_bv = 3807 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3808 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3809 3810 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3811 /* 3812 * Here we allow setting states that are not present in 3813 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3814 * with old userspace. 3815 */ 3816 if (xstate_bv & ~kvm_supported_xcr0() || 3817 mxcsr & ~mxcsr_feature_mask) 3818 return -EINVAL; 3819 load_xsave(vcpu, (u8 *)guest_xsave->region); 3820 } else { 3821 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3822 mxcsr & ~mxcsr_feature_mask) 3823 return -EINVAL; 3824 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 3825 guest_xsave->region, sizeof(struct fxregs_state)); 3826 } 3827 return 0; 3828 } 3829 3830 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3831 struct kvm_xcrs *guest_xcrs) 3832 { 3833 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3834 guest_xcrs->nr_xcrs = 0; 3835 return; 3836 } 3837 3838 guest_xcrs->nr_xcrs = 1; 3839 guest_xcrs->flags = 0; 3840 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3841 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3842 } 3843 3844 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3845 struct kvm_xcrs *guest_xcrs) 3846 { 3847 int i, r = 0; 3848 3849 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3850 return -EINVAL; 3851 3852 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3853 return -EINVAL; 3854 3855 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3856 /* Only support XCR0 currently */ 3857 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3858 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3859 guest_xcrs->xcrs[i].value); 3860 break; 3861 } 3862 if (r) 3863 r = -EINVAL; 3864 return r; 3865 } 3866 3867 /* 3868 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3869 * stopped by the hypervisor. This function will be called from the host only. 3870 * EINVAL is returned when the host attempts to set the flag for a guest that 3871 * does not support pv clocks. 3872 */ 3873 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3874 { 3875 if (!vcpu->arch.pv_time_enabled) 3876 return -EINVAL; 3877 vcpu->arch.pvclock_set_guest_stopped_request = true; 3878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3879 return 0; 3880 } 3881 3882 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3883 struct kvm_enable_cap *cap) 3884 { 3885 int r; 3886 uint16_t vmcs_version; 3887 void __user *user_ptr; 3888 3889 if (cap->flags) 3890 return -EINVAL; 3891 3892 switch (cap->cap) { 3893 case KVM_CAP_HYPERV_SYNIC2: 3894 if (cap->args[0]) 3895 return -EINVAL; 3896 /* fall through */ 3897 3898 case KVM_CAP_HYPERV_SYNIC: 3899 if (!irqchip_in_kernel(vcpu->kvm)) 3900 return -EINVAL; 3901 return kvm_hv_activate_synic(vcpu, cap->cap == 3902 KVM_CAP_HYPERV_SYNIC2); 3903 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3904 if (!kvm_x86_ops->nested_enable_evmcs) 3905 return -ENOTTY; 3906 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version); 3907 if (!r) { 3908 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 3909 if (copy_to_user(user_ptr, &vmcs_version, 3910 sizeof(vmcs_version))) 3911 r = -EFAULT; 3912 } 3913 return r; 3914 3915 default: 3916 return -EINVAL; 3917 } 3918 } 3919 3920 long kvm_arch_vcpu_ioctl(struct file *filp, 3921 unsigned int ioctl, unsigned long arg) 3922 { 3923 struct kvm_vcpu *vcpu = filp->private_data; 3924 void __user *argp = (void __user *)arg; 3925 int r; 3926 union { 3927 struct kvm_lapic_state *lapic; 3928 struct kvm_xsave *xsave; 3929 struct kvm_xcrs *xcrs; 3930 void *buffer; 3931 } u; 3932 3933 vcpu_load(vcpu); 3934 3935 u.buffer = NULL; 3936 switch (ioctl) { 3937 case KVM_GET_LAPIC: { 3938 r = -EINVAL; 3939 if (!lapic_in_kernel(vcpu)) 3940 goto out; 3941 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 3942 GFP_KERNEL_ACCOUNT); 3943 3944 r = -ENOMEM; 3945 if (!u.lapic) 3946 goto out; 3947 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3948 if (r) 3949 goto out; 3950 r = -EFAULT; 3951 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3952 goto out; 3953 r = 0; 3954 break; 3955 } 3956 case KVM_SET_LAPIC: { 3957 r = -EINVAL; 3958 if (!lapic_in_kernel(vcpu)) 3959 goto out; 3960 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3961 if (IS_ERR(u.lapic)) { 3962 r = PTR_ERR(u.lapic); 3963 goto out_nofree; 3964 } 3965 3966 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3967 break; 3968 } 3969 case KVM_INTERRUPT: { 3970 struct kvm_interrupt irq; 3971 3972 r = -EFAULT; 3973 if (copy_from_user(&irq, argp, sizeof(irq))) 3974 goto out; 3975 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3976 break; 3977 } 3978 case KVM_NMI: { 3979 r = kvm_vcpu_ioctl_nmi(vcpu); 3980 break; 3981 } 3982 case KVM_SMI: { 3983 r = kvm_vcpu_ioctl_smi(vcpu); 3984 break; 3985 } 3986 case KVM_SET_CPUID: { 3987 struct kvm_cpuid __user *cpuid_arg = argp; 3988 struct kvm_cpuid cpuid; 3989 3990 r = -EFAULT; 3991 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3992 goto out; 3993 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3994 break; 3995 } 3996 case KVM_SET_CPUID2: { 3997 struct kvm_cpuid2 __user *cpuid_arg = argp; 3998 struct kvm_cpuid2 cpuid; 3999 4000 r = -EFAULT; 4001 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4002 goto out; 4003 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4004 cpuid_arg->entries); 4005 break; 4006 } 4007 case KVM_GET_CPUID2: { 4008 struct kvm_cpuid2 __user *cpuid_arg = argp; 4009 struct kvm_cpuid2 cpuid; 4010 4011 r = -EFAULT; 4012 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4013 goto out; 4014 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4015 cpuid_arg->entries); 4016 if (r) 4017 goto out; 4018 r = -EFAULT; 4019 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4020 goto out; 4021 r = 0; 4022 break; 4023 } 4024 case KVM_GET_MSRS: { 4025 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4026 r = msr_io(vcpu, argp, do_get_msr, 1); 4027 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4028 break; 4029 } 4030 case KVM_SET_MSRS: { 4031 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4032 r = msr_io(vcpu, argp, do_set_msr, 0); 4033 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4034 break; 4035 } 4036 case KVM_TPR_ACCESS_REPORTING: { 4037 struct kvm_tpr_access_ctl tac; 4038 4039 r = -EFAULT; 4040 if (copy_from_user(&tac, argp, sizeof(tac))) 4041 goto out; 4042 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4043 if (r) 4044 goto out; 4045 r = -EFAULT; 4046 if (copy_to_user(argp, &tac, sizeof(tac))) 4047 goto out; 4048 r = 0; 4049 break; 4050 }; 4051 case KVM_SET_VAPIC_ADDR: { 4052 struct kvm_vapic_addr va; 4053 int idx; 4054 4055 r = -EINVAL; 4056 if (!lapic_in_kernel(vcpu)) 4057 goto out; 4058 r = -EFAULT; 4059 if (copy_from_user(&va, argp, sizeof(va))) 4060 goto out; 4061 idx = srcu_read_lock(&vcpu->kvm->srcu); 4062 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4063 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4064 break; 4065 } 4066 case KVM_X86_SETUP_MCE: { 4067 u64 mcg_cap; 4068 4069 r = -EFAULT; 4070 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4071 goto out; 4072 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4073 break; 4074 } 4075 case KVM_X86_SET_MCE: { 4076 struct kvm_x86_mce mce; 4077 4078 r = -EFAULT; 4079 if (copy_from_user(&mce, argp, sizeof(mce))) 4080 goto out; 4081 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4082 break; 4083 } 4084 case KVM_GET_VCPU_EVENTS: { 4085 struct kvm_vcpu_events events; 4086 4087 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4088 4089 r = -EFAULT; 4090 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4091 break; 4092 r = 0; 4093 break; 4094 } 4095 case KVM_SET_VCPU_EVENTS: { 4096 struct kvm_vcpu_events events; 4097 4098 r = -EFAULT; 4099 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4100 break; 4101 4102 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4103 break; 4104 } 4105 case KVM_GET_DEBUGREGS: { 4106 struct kvm_debugregs dbgregs; 4107 4108 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4109 4110 r = -EFAULT; 4111 if (copy_to_user(argp, &dbgregs, 4112 sizeof(struct kvm_debugregs))) 4113 break; 4114 r = 0; 4115 break; 4116 } 4117 case KVM_SET_DEBUGREGS: { 4118 struct kvm_debugregs dbgregs; 4119 4120 r = -EFAULT; 4121 if (copy_from_user(&dbgregs, argp, 4122 sizeof(struct kvm_debugregs))) 4123 break; 4124 4125 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4126 break; 4127 } 4128 case KVM_GET_XSAVE: { 4129 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4130 r = -ENOMEM; 4131 if (!u.xsave) 4132 break; 4133 4134 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4135 4136 r = -EFAULT; 4137 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4138 break; 4139 r = 0; 4140 break; 4141 } 4142 case KVM_SET_XSAVE: { 4143 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4144 if (IS_ERR(u.xsave)) { 4145 r = PTR_ERR(u.xsave); 4146 goto out_nofree; 4147 } 4148 4149 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4150 break; 4151 } 4152 case KVM_GET_XCRS: { 4153 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4154 r = -ENOMEM; 4155 if (!u.xcrs) 4156 break; 4157 4158 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4159 4160 r = -EFAULT; 4161 if (copy_to_user(argp, u.xcrs, 4162 sizeof(struct kvm_xcrs))) 4163 break; 4164 r = 0; 4165 break; 4166 } 4167 case KVM_SET_XCRS: { 4168 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4169 if (IS_ERR(u.xcrs)) { 4170 r = PTR_ERR(u.xcrs); 4171 goto out_nofree; 4172 } 4173 4174 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4175 break; 4176 } 4177 case KVM_SET_TSC_KHZ: { 4178 u32 user_tsc_khz; 4179 4180 r = -EINVAL; 4181 user_tsc_khz = (u32)arg; 4182 4183 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 4184 goto out; 4185 4186 if (user_tsc_khz == 0) 4187 user_tsc_khz = tsc_khz; 4188 4189 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4190 r = 0; 4191 4192 goto out; 4193 } 4194 case KVM_GET_TSC_KHZ: { 4195 r = vcpu->arch.virtual_tsc_khz; 4196 goto out; 4197 } 4198 case KVM_KVMCLOCK_CTRL: { 4199 r = kvm_set_guest_paused(vcpu); 4200 goto out; 4201 } 4202 case KVM_ENABLE_CAP: { 4203 struct kvm_enable_cap cap; 4204 4205 r = -EFAULT; 4206 if (copy_from_user(&cap, argp, sizeof(cap))) 4207 goto out; 4208 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4209 break; 4210 } 4211 case KVM_GET_NESTED_STATE: { 4212 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4213 u32 user_data_size; 4214 4215 r = -EINVAL; 4216 if (!kvm_x86_ops->get_nested_state) 4217 break; 4218 4219 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4220 r = -EFAULT; 4221 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4222 break; 4223 4224 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state, 4225 user_data_size); 4226 if (r < 0) 4227 break; 4228 4229 if (r > user_data_size) { 4230 if (put_user(r, &user_kvm_nested_state->size)) 4231 r = -EFAULT; 4232 else 4233 r = -E2BIG; 4234 break; 4235 } 4236 4237 r = 0; 4238 break; 4239 } 4240 case KVM_SET_NESTED_STATE: { 4241 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4242 struct kvm_nested_state kvm_state; 4243 4244 r = -EINVAL; 4245 if (!kvm_x86_ops->set_nested_state) 4246 break; 4247 4248 r = -EFAULT; 4249 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 4250 break; 4251 4252 r = -EINVAL; 4253 if (kvm_state.size < sizeof(kvm_state)) 4254 break; 4255 4256 if (kvm_state.flags & 4257 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 4258 | KVM_STATE_NESTED_EVMCS)) 4259 break; 4260 4261 /* nested_run_pending implies guest_mode. */ 4262 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 4263 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 4264 break; 4265 4266 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); 4267 break; 4268 } 4269 case KVM_GET_SUPPORTED_HV_CPUID: { 4270 struct kvm_cpuid2 __user *cpuid_arg = argp; 4271 struct kvm_cpuid2 cpuid; 4272 4273 r = -EFAULT; 4274 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4275 goto out; 4276 4277 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, 4278 cpuid_arg->entries); 4279 if (r) 4280 goto out; 4281 4282 r = -EFAULT; 4283 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4284 goto out; 4285 r = 0; 4286 break; 4287 } 4288 default: 4289 r = -EINVAL; 4290 } 4291 out: 4292 kfree(u.buffer); 4293 out_nofree: 4294 vcpu_put(vcpu); 4295 return r; 4296 } 4297 4298 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 4299 { 4300 return VM_FAULT_SIGBUS; 4301 } 4302 4303 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 4304 { 4305 int ret; 4306 4307 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 4308 return -EINVAL; 4309 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 4310 return ret; 4311 } 4312 4313 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 4314 u64 ident_addr) 4315 { 4316 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); 4317 } 4318 4319 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 4320 unsigned long kvm_nr_mmu_pages) 4321 { 4322 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 4323 return -EINVAL; 4324 4325 mutex_lock(&kvm->slots_lock); 4326 4327 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 4328 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 4329 4330 mutex_unlock(&kvm->slots_lock); 4331 return 0; 4332 } 4333 4334 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 4335 { 4336 return kvm->arch.n_max_mmu_pages; 4337 } 4338 4339 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4340 { 4341 struct kvm_pic *pic = kvm->arch.vpic; 4342 int r; 4343 4344 r = 0; 4345 switch (chip->chip_id) { 4346 case KVM_IRQCHIP_PIC_MASTER: 4347 memcpy(&chip->chip.pic, &pic->pics[0], 4348 sizeof(struct kvm_pic_state)); 4349 break; 4350 case KVM_IRQCHIP_PIC_SLAVE: 4351 memcpy(&chip->chip.pic, &pic->pics[1], 4352 sizeof(struct kvm_pic_state)); 4353 break; 4354 case KVM_IRQCHIP_IOAPIC: 4355 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4356 break; 4357 default: 4358 r = -EINVAL; 4359 break; 4360 } 4361 return r; 4362 } 4363 4364 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4365 { 4366 struct kvm_pic *pic = kvm->arch.vpic; 4367 int r; 4368 4369 r = 0; 4370 switch (chip->chip_id) { 4371 case KVM_IRQCHIP_PIC_MASTER: 4372 spin_lock(&pic->lock); 4373 memcpy(&pic->pics[0], &chip->chip.pic, 4374 sizeof(struct kvm_pic_state)); 4375 spin_unlock(&pic->lock); 4376 break; 4377 case KVM_IRQCHIP_PIC_SLAVE: 4378 spin_lock(&pic->lock); 4379 memcpy(&pic->pics[1], &chip->chip.pic, 4380 sizeof(struct kvm_pic_state)); 4381 spin_unlock(&pic->lock); 4382 break; 4383 case KVM_IRQCHIP_IOAPIC: 4384 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4385 break; 4386 default: 4387 r = -EINVAL; 4388 break; 4389 } 4390 kvm_pic_update_irq(pic); 4391 return r; 4392 } 4393 4394 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4395 { 4396 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4397 4398 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4399 4400 mutex_lock(&kps->lock); 4401 memcpy(ps, &kps->channels, sizeof(*ps)); 4402 mutex_unlock(&kps->lock); 4403 return 0; 4404 } 4405 4406 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4407 { 4408 int i; 4409 struct kvm_pit *pit = kvm->arch.vpit; 4410 4411 mutex_lock(&pit->pit_state.lock); 4412 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4413 for (i = 0; i < 3; i++) 4414 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4415 mutex_unlock(&pit->pit_state.lock); 4416 return 0; 4417 } 4418 4419 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4420 { 4421 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4422 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4423 sizeof(ps->channels)); 4424 ps->flags = kvm->arch.vpit->pit_state.flags; 4425 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4426 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4427 return 0; 4428 } 4429 4430 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4431 { 4432 int start = 0; 4433 int i; 4434 u32 prev_legacy, cur_legacy; 4435 struct kvm_pit *pit = kvm->arch.vpit; 4436 4437 mutex_lock(&pit->pit_state.lock); 4438 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4439 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4440 if (!prev_legacy && cur_legacy) 4441 start = 1; 4442 memcpy(&pit->pit_state.channels, &ps->channels, 4443 sizeof(pit->pit_state.channels)); 4444 pit->pit_state.flags = ps->flags; 4445 for (i = 0; i < 3; i++) 4446 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4447 start && i == 0); 4448 mutex_unlock(&pit->pit_state.lock); 4449 return 0; 4450 } 4451 4452 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4453 struct kvm_reinject_control *control) 4454 { 4455 struct kvm_pit *pit = kvm->arch.vpit; 4456 4457 if (!pit) 4458 return -ENXIO; 4459 4460 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4461 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4462 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4463 */ 4464 mutex_lock(&pit->pit_state.lock); 4465 kvm_pit_set_reinject(pit, control->pit_reinject); 4466 mutex_unlock(&pit->pit_state.lock); 4467 4468 return 0; 4469 } 4470 4471 /** 4472 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 4473 * @kvm: kvm instance 4474 * @log: slot id and address to which we copy the log 4475 * 4476 * Steps 1-4 below provide general overview of dirty page logging. See 4477 * kvm_get_dirty_log_protect() function description for additional details. 4478 * 4479 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 4480 * always flush the TLB (step 4) even if previous step failed and the dirty 4481 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 4482 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 4483 * writes will be marked dirty for next log read. 4484 * 4485 * 1. Take a snapshot of the bit and clear it if needed. 4486 * 2. Write protect the corresponding page. 4487 * 3. Copy the snapshot to the userspace. 4488 * 4. Flush TLB's if needed. 4489 */ 4490 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 4491 { 4492 bool flush = false; 4493 int r; 4494 4495 mutex_lock(&kvm->slots_lock); 4496 4497 /* 4498 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4499 */ 4500 if (kvm_x86_ops->flush_log_dirty) 4501 kvm_x86_ops->flush_log_dirty(kvm); 4502 4503 r = kvm_get_dirty_log_protect(kvm, log, &flush); 4504 4505 /* 4506 * All the TLBs can be flushed out of mmu lock, see the comments in 4507 * kvm_mmu_slot_remove_write_access(). 4508 */ 4509 lockdep_assert_held(&kvm->slots_lock); 4510 if (flush) 4511 kvm_flush_remote_tlbs(kvm); 4512 4513 mutex_unlock(&kvm->slots_lock); 4514 return r; 4515 } 4516 4517 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) 4518 { 4519 bool flush = false; 4520 int r; 4521 4522 mutex_lock(&kvm->slots_lock); 4523 4524 /* 4525 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4526 */ 4527 if (kvm_x86_ops->flush_log_dirty) 4528 kvm_x86_ops->flush_log_dirty(kvm); 4529 4530 r = kvm_clear_dirty_log_protect(kvm, log, &flush); 4531 4532 /* 4533 * All the TLBs can be flushed out of mmu lock, see the comments in 4534 * kvm_mmu_slot_remove_write_access(). 4535 */ 4536 lockdep_assert_held(&kvm->slots_lock); 4537 if (flush) 4538 kvm_flush_remote_tlbs(kvm); 4539 4540 mutex_unlock(&kvm->slots_lock); 4541 return r; 4542 } 4543 4544 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4545 bool line_status) 4546 { 4547 if (!irqchip_in_kernel(kvm)) 4548 return -ENXIO; 4549 4550 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4551 irq_event->irq, irq_event->level, 4552 line_status); 4553 return 0; 4554 } 4555 4556 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4557 struct kvm_enable_cap *cap) 4558 { 4559 int r; 4560 4561 if (cap->flags) 4562 return -EINVAL; 4563 4564 switch (cap->cap) { 4565 case KVM_CAP_DISABLE_QUIRKS: 4566 kvm->arch.disabled_quirks = cap->args[0]; 4567 r = 0; 4568 break; 4569 case KVM_CAP_SPLIT_IRQCHIP: { 4570 mutex_lock(&kvm->lock); 4571 r = -EINVAL; 4572 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4573 goto split_irqchip_unlock; 4574 r = -EEXIST; 4575 if (irqchip_in_kernel(kvm)) 4576 goto split_irqchip_unlock; 4577 if (kvm->created_vcpus) 4578 goto split_irqchip_unlock; 4579 r = kvm_setup_empty_irq_routing(kvm); 4580 if (r) 4581 goto split_irqchip_unlock; 4582 /* Pairs with irqchip_in_kernel. */ 4583 smp_wmb(); 4584 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4585 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4586 r = 0; 4587 split_irqchip_unlock: 4588 mutex_unlock(&kvm->lock); 4589 break; 4590 } 4591 case KVM_CAP_X2APIC_API: 4592 r = -EINVAL; 4593 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4594 break; 4595 4596 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4597 kvm->arch.x2apic_format = true; 4598 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4599 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4600 4601 r = 0; 4602 break; 4603 case KVM_CAP_X86_DISABLE_EXITS: 4604 r = -EINVAL; 4605 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4606 break; 4607 4608 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4609 kvm_can_mwait_in_guest()) 4610 kvm->arch.mwait_in_guest = true; 4611 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 4612 kvm->arch.hlt_in_guest = true; 4613 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4614 kvm->arch.pause_in_guest = true; 4615 r = 0; 4616 break; 4617 case KVM_CAP_MSR_PLATFORM_INFO: 4618 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 4619 r = 0; 4620 break; 4621 case KVM_CAP_EXCEPTION_PAYLOAD: 4622 kvm->arch.exception_payload_enabled = cap->args[0]; 4623 r = 0; 4624 break; 4625 default: 4626 r = -EINVAL; 4627 break; 4628 } 4629 return r; 4630 } 4631 4632 long kvm_arch_vm_ioctl(struct file *filp, 4633 unsigned int ioctl, unsigned long arg) 4634 { 4635 struct kvm *kvm = filp->private_data; 4636 void __user *argp = (void __user *)arg; 4637 int r = -ENOTTY; 4638 /* 4639 * This union makes it completely explicit to gcc-3.x 4640 * that these two variables' stack usage should be 4641 * combined, not added together. 4642 */ 4643 union { 4644 struct kvm_pit_state ps; 4645 struct kvm_pit_state2 ps2; 4646 struct kvm_pit_config pit_config; 4647 } u; 4648 4649 switch (ioctl) { 4650 case KVM_SET_TSS_ADDR: 4651 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4652 break; 4653 case KVM_SET_IDENTITY_MAP_ADDR: { 4654 u64 ident_addr; 4655 4656 mutex_lock(&kvm->lock); 4657 r = -EINVAL; 4658 if (kvm->created_vcpus) 4659 goto set_identity_unlock; 4660 r = -EFAULT; 4661 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 4662 goto set_identity_unlock; 4663 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4664 set_identity_unlock: 4665 mutex_unlock(&kvm->lock); 4666 break; 4667 } 4668 case KVM_SET_NR_MMU_PAGES: 4669 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4670 break; 4671 case KVM_GET_NR_MMU_PAGES: 4672 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4673 break; 4674 case KVM_CREATE_IRQCHIP: { 4675 mutex_lock(&kvm->lock); 4676 4677 r = -EEXIST; 4678 if (irqchip_in_kernel(kvm)) 4679 goto create_irqchip_unlock; 4680 4681 r = -EINVAL; 4682 if (kvm->created_vcpus) 4683 goto create_irqchip_unlock; 4684 4685 r = kvm_pic_init(kvm); 4686 if (r) 4687 goto create_irqchip_unlock; 4688 4689 r = kvm_ioapic_init(kvm); 4690 if (r) { 4691 kvm_pic_destroy(kvm); 4692 goto create_irqchip_unlock; 4693 } 4694 4695 r = kvm_setup_default_irq_routing(kvm); 4696 if (r) { 4697 kvm_ioapic_destroy(kvm); 4698 kvm_pic_destroy(kvm); 4699 goto create_irqchip_unlock; 4700 } 4701 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4702 smp_wmb(); 4703 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4704 create_irqchip_unlock: 4705 mutex_unlock(&kvm->lock); 4706 break; 4707 } 4708 case KVM_CREATE_PIT: 4709 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4710 goto create_pit; 4711 case KVM_CREATE_PIT2: 4712 r = -EFAULT; 4713 if (copy_from_user(&u.pit_config, argp, 4714 sizeof(struct kvm_pit_config))) 4715 goto out; 4716 create_pit: 4717 mutex_lock(&kvm->lock); 4718 r = -EEXIST; 4719 if (kvm->arch.vpit) 4720 goto create_pit_unlock; 4721 r = -ENOMEM; 4722 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4723 if (kvm->arch.vpit) 4724 r = 0; 4725 create_pit_unlock: 4726 mutex_unlock(&kvm->lock); 4727 break; 4728 case KVM_GET_IRQCHIP: { 4729 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4730 struct kvm_irqchip *chip; 4731 4732 chip = memdup_user(argp, sizeof(*chip)); 4733 if (IS_ERR(chip)) { 4734 r = PTR_ERR(chip); 4735 goto out; 4736 } 4737 4738 r = -ENXIO; 4739 if (!irqchip_kernel(kvm)) 4740 goto get_irqchip_out; 4741 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4742 if (r) 4743 goto get_irqchip_out; 4744 r = -EFAULT; 4745 if (copy_to_user(argp, chip, sizeof(*chip))) 4746 goto get_irqchip_out; 4747 r = 0; 4748 get_irqchip_out: 4749 kfree(chip); 4750 break; 4751 } 4752 case KVM_SET_IRQCHIP: { 4753 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4754 struct kvm_irqchip *chip; 4755 4756 chip = memdup_user(argp, sizeof(*chip)); 4757 if (IS_ERR(chip)) { 4758 r = PTR_ERR(chip); 4759 goto out; 4760 } 4761 4762 r = -ENXIO; 4763 if (!irqchip_kernel(kvm)) 4764 goto set_irqchip_out; 4765 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4766 if (r) 4767 goto set_irqchip_out; 4768 r = 0; 4769 set_irqchip_out: 4770 kfree(chip); 4771 break; 4772 } 4773 case KVM_GET_PIT: { 4774 r = -EFAULT; 4775 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4776 goto out; 4777 r = -ENXIO; 4778 if (!kvm->arch.vpit) 4779 goto out; 4780 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4781 if (r) 4782 goto out; 4783 r = -EFAULT; 4784 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4785 goto out; 4786 r = 0; 4787 break; 4788 } 4789 case KVM_SET_PIT: { 4790 r = -EFAULT; 4791 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 4792 goto out; 4793 r = -ENXIO; 4794 if (!kvm->arch.vpit) 4795 goto out; 4796 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4797 break; 4798 } 4799 case KVM_GET_PIT2: { 4800 r = -ENXIO; 4801 if (!kvm->arch.vpit) 4802 goto out; 4803 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4804 if (r) 4805 goto out; 4806 r = -EFAULT; 4807 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4808 goto out; 4809 r = 0; 4810 break; 4811 } 4812 case KVM_SET_PIT2: { 4813 r = -EFAULT; 4814 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4815 goto out; 4816 r = -ENXIO; 4817 if (!kvm->arch.vpit) 4818 goto out; 4819 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4820 break; 4821 } 4822 case KVM_REINJECT_CONTROL: { 4823 struct kvm_reinject_control control; 4824 r = -EFAULT; 4825 if (copy_from_user(&control, argp, sizeof(control))) 4826 goto out; 4827 r = kvm_vm_ioctl_reinject(kvm, &control); 4828 break; 4829 } 4830 case KVM_SET_BOOT_CPU_ID: 4831 r = 0; 4832 mutex_lock(&kvm->lock); 4833 if (kvm->created_vcpus) 4834 r = -EBUSY; 4835 else 4836 kvm->arch.bsp_vcpu_id = arg; 4837 mutex_unlock(&kvm->lock); 4838 break; 4839 case KVM_XEN_HVM_CONFIG: { 4840 struct kvm_xen_hvm_config xhc; 4841 r = -EFAULT; 4842 if (copy_from_user(&xhc, argp, sizeof(xhc))) 4843 goto out; 4844 r = -EINVAL; 4845 if (xhc.flags) 4846 goto out; 4847 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 4848 r = 0; 4849 break; 4850 } 4851 case KVM_SET_CLOCK: { 4852 struct kvm_clock_data user_ns; 4853 u64 now_ns; 4854 4855 r = -EFAULT; 4856 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4857 goto out; 4858 4859 r = -EINVAL; 4860 if (user_ns.flags) 4861 goto out; 4862 4863 r = 0; 4864 /* 4865 * TODO: userspace has to take care of races with VCPU_RUN, so 4866 * kvm_gen_update_masterclock() can be cut down to locked 4867 * pvclock_update_vm_gtod_copy(). 4868 */ 4869 kvm_gen_update_masterclock(kvm); 4870 now_ns = get_kvmclock_ns(kvm); 4871 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4872 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4873 break; 4874 } 4875 case KVM_GET_CLOCK: { 4876 struct kvm_clock_data user_ns; 4877 u64 now_ns; 4878 4879 now_ns = get_kvmclock_ns(kvm); 4880 user_ns.clock = now_ns; 4881 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4882 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4883 4884 r = -EFAULT; 4885 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4886 goto out; 4887 r = 0; 4888 break; 4889 } 4890 case KVM_MEMORY_ENCRYPT_OP: { 4891 r = -ENOTTY; 4892 if (kvm_x86_ops->mem_enc_op) 4893 r = kvm_x86_ops->mem_enc_op(kvm, argp); 4894 break; 4895 } 4896 case KVM_MEMORY_ENCRYPT_REG_REGION: { 4897 struct kvm_enc_region region; 4898 4899 r = -EFAULT; 4900 if (copy_from_user(®ion, argp, sizeof(region))) 4901 goto out; 4902 4903 r = -ENOTTY; 4904 if (kvm_x86_ops->mem_enc_reg_region) 4905 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); 4906 break; 4907 } 4908 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 4909 struct kvm_enc_region region; 4910 4911 r = -EFAULT; 4912 if (copy_from_user(®ion, argp, sizeof(region))) 4913 goto out; 4914 4915 r = -ENOTTY; 4916 if (kvm_x86_ops->mem_enc_unreg_region) 4917 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); 4918 break; 4919 } 4920 case KVM_HYPERV_EVENTFD: { 4921 struct kvm_hyperv_eventfd hvevfd; 4922 4923 r = -EFAULT; 4924 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 4925 goto out; 4926 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 4927 break; 4928 } 4929 default: 4930 r = -ENOTTY; 4931 } 4932 out: 4933 return r; 4934 } 4935 4936 static void kvm_init_msr_list(void) 4937 { 4938 u32 dummy[2]; 4939 unsigned i, j; 4940 4941 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4942 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4943 continue; 4944 4945 /* 4946 * Even MSRs that are valid in the host may not be exposed 4947 * to the guests in some cases. 4948 */ 4949 switch (msrs_to_save[i]) { 4950 case MSR_IA32_BNDCFGS: 4951 if (!kvm_mpx_supported()) 4952 continue; 4953 break; 4954 case MSR_TSC_AUX: 4955 if (!kvm_x86_ops->rdtscp_supported()) 4956 continue; 4957 break; 4958 case MSR_IA32_RTIT_CTL: 4959 case MSR_IA32_RTIT_STATUS: 4960 if (!kvm_x86_ops->pt_supported()) 4961 continue; 4962 break; 4963 case MSR_IA32_RTIT_CR3_MATCH: 4964 if (!kvm_x86_ops->pt_supported() || 4965 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 4966 continue; 4967 break; 4968 case MSR_IA32_RTIT_OUTPUT_BASE: 4969 case MSR_IA32_RTIT_OUTPUT_MASK: 4970 if (!kvm_x86_ops->pt_supported() || 4971 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 4972 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 4973 continue; 4974 break; 4975 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { 4976 if (!kvm_x86_ops->pt_supported() || 4977 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >= 4978 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 4979 continue; 4980 break; 4981 } 4982 default: 4983 break; 4984 } 4985 4986 if (j < i) 4987 msrs_to_save[j] = msrs_to_save[i]; 4988 j++; 4989 } 4990 num_msrs_to_save = j; 4991 4992 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4993 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i])) 4994 continue; 4995 4996 if (j < i) 4997 emulated_msrs[j] = emulated_msrs[i]; 4998 j++; 4999 } 5000 num_emulated_msrs = j; 5001 5002 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { 5003 struct kvm_msr_entry msr; 5004 5005 msr.index = msr_based_features[i]; 5006 if (kvm_get_msr_feature(&msr)) 5007 continue; 5008 5009 if (j < i) 5010 msr_based_features[j] = msr_based_features[i]; 5011 j++; 5012 } 5013 num_msr_based_features = j; 5014 } 5015 5016 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 5017 const void *v) 5018 { 5019 int handled = 0; 5020 int n; 5021 5022 do { 5023 n = min(len, 8); 5024 if (!(lapic_in_kernel(vcpu) && 5025 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 5026 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 5027 break; 5028 handled += n; 5029 addr += n; 5030 len -= n; 5031 v += n; 5032 } while (len); 5033 5034 return handled; 5035 } 5036 5037 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 5038 { 5039 int handled = 0; 5040 int n; 5041 5042 do { 5043 n = min(len, 8); 5044 if (!(lapic_in_kernel(vcpu) && 5045 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5046 addr, n, v)) 5047 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5048 break; 5049 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5050 handled += n; 5051 addr += n; 5052 len -= n; 5053 v += n; 5054 } while (len); 5055 5056 return handled; 5057 } 5058 5059 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5060 struct kvm_segment *var, int seg) 5061 { 5062 kvm_x86_ops->set_segment(vcpu, var, seg); 5063 } 5064 5065 void kvm_get_segment(struct kvm_vcpu *vcpu, 5066 struct kvm_segment *var, int seg) 5067 { 5068 kvm_x86_ops->get_segment(vcpu, var, seg); 5069 } 5070 5071 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5072 struct x86_exception *exception) 5073 { 5074 gpa_t t_gpa; 5075 5076 BUG_ON(!mmu_is_nested(vcpu)); 5077 5078 /* NPT walks are always user-walks */ 5079 access |= PFERR_USER_MASK; 5080 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5081 5082 return t_gpa; 5083 } 5084 5085 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5086 struct x86_exception *exception) 5087 { 5088 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5089 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5090 } 5091 5092 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 5093 struct x86_exception *exception) 5094 { 5095 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5096 access |= PFERR_FETCH_MASK; 5097 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5098 } 5099 5100 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 5101 struct x86_exception *exception) 5102 { 5103 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5104 access |= PFERR_WRITE_MASK; 5105 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5106 } 5107 5108 /* uses this to access any guest's mapped memory without checking CPL */ 5109 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 5110 struct x86_exception *exception) 5111 { 5112 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 5113 } 5114 5115 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5116 struct kvm_vcpu *vcpu, u32 access, 5117 struct x86_exception *exception) 5118 { 5119 void *data = val; 5120 int r = X86EMUL_CONTINUE; 5121 5122 while (bytes) { 5123 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 5124 exception); 5125 unsigned offset = addr & (PAGE_SIZE-1); 5126 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 5127 int ret; 5128 5129 if (gpa == UNMAPPED_GVA) 5130 return X86EMUL_PROPAGATE_FAULT; 5131 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 5132 offset, toread); 5133 if (ret < 0) { 5134 r = X86EMUL_IO_NEEDED; 5135 goto out; 5136 } 5137 5138 bytes -= toread; 5139 data += toread; 5140 addr += toread; 5141 } 5142 out: 5143 return r; 5144 } 5145 5146 /* used for instruction fetching */ 5147 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 5148 gva_t addr, void *val, unsigned int bytes, 5149 struct x86_exception *exception) 5150 { 5151 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5152 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5153 unsigned offset; 5154 int ret; 5155 5156 /* Inline kvm_read_guest_virt_helper for speed. */ 5157 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 5158 exception); 5159 if (unlikely(gpa == UNMAPPED_GVA)) 5160 return X86EMUL_PROPAGATE_FAULT; 5161 5162 offset = addr & (PAGE_SIZE-1); 5163 if (WARN_ON(offset + bytes > PAGE_SIZE)) 5164 bytes = (unsigned)PAGE_SIZE - offset; 5165 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 5166 offset, bytes); 5167 if (unlikely(ret < 0)) 5168 return X86EMUL_IO_NEEDED; 5169 5170 return X86EMUL_CONTINUE; 5171 } 5172 5173 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 5174 gva_t addr, void *val, unsigned int bytes, 5175 struct x86_exception *exception) 5176 { 5177 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5178 5179 /* 5180 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5181 * is returned, but our callers are not ready for that and they blindly 5182 * call kvm_inject_page_fault. Ensure that they at least do not leak 5183 * uninitialized kernel stack memory into cr2 and error code. 5184 */ 5185 memset(exception, 0, sizeof(*exception)); 5186 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 5187 exception); 5188 } 5189 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 5190 5191 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 5192 gva_t addr, void *val, unsigned int bytes, 5193 struct x86_exception *exception, bool system) 5194 { 5195 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5196 u32 access = 0; 5197 5198 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) 5199 access |= PFERR_USER_MASK; 5200 5201 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 5202 } 5203 5204 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 5205 unsigned long addr, void *val, unsigned int bytes) 5206 { 5207 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5208 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 5209 5210 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 5211 } 5212 5213 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5214 struct kvm_vcpu *vcpu, u32 access, 5215 struct x86_exception *exception) 5216 { 5217 void *data = val; 5218 int r = X86EMUL_CONTINUE; 5219 5220 while (bytes) { 5221 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 5222 access, 5223 exception); 5224 unsigned offset = addr & (PAGE_SIZE-1); 5225 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 5226 int ret; 5227 5228 if (gpa == UNMAPPED_GVA) 5229 return X86EMUL_PROPAGATE_FAULT; 5230 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 5231 if (ret < 0) { 5232 r = X86EMUL_IO_NEEDED; 5233 goto out; 5234 } 5235 5236 bytes -= towrite; 5237 data += towrite; 5238 addr += towrite; 5239 } 5240 out: 5241 return r; 5242 } 5243 5244 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 5245 unsigned int bytes, struct x86_exception *exception, 5246 bool system) 5247 { 5248 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5249 u32 access = PFERR_WRITE_MASK; 5250 5251 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) 5252 access |= PFERR_USER_MASK; 5253 5254 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5255 access, exception); 5256 } 5257 5258 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 5259 unsigned int bytes, struct x86_exception *exception) 5260 { 5261 /* kvm_write_guest_virt_system can pull in tons of pages. */ 5262 vcpu->arch.l1tf_flush_l1d = true; 5263 5264 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5265 PFERR_WRITE_MASK, exception); 5266 } 5267 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 5268 5269 int handle_ud(struct kvm_vcpu *vcpu) 5270 { 5271 int emul_type = EMULTYPE_TRAP_UD; 5272 enum emulation_result er; 5273 char sig[5]; /* ud2; .ascii "kvm" */ 5274 struct x86_exception e; 5275 5276 if (force_emulation_prefix && 5277 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 5278 sig, sizeof(sig), &e) == 0 && 5279 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) { 5280 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 5281 emul_type = 0; 5282 } 5283 5284 er = kvm_emulate_instruction(vcpu, emul_type); 5285 if (er == EMULATE_USER_EXIT) 5286 return 0; 5287 if (er != EMULATE_DONE) 5288 kvm_queue_exception(vcpu, UD_VECTOR); 5289 return 1; 5290 } 5291 EXPORT_SYMBOL_GPL(handle_ud); 5292 5293 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5294 gpa_t gpa, bool write) 5295 { 5296 /* For APIC access vmexit */ 5297 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5298 return 1; 5299 5300 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 5301 trace_vcpu_match_mmio(gva, gpa, write, true); 5302 return 1; 5303 } 5304 5305 return 0; 5306 } 5307 5308 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5309 gpa_t *gpa, struct x86_exception *exception, 5310 bool write) 5311 { 5312 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 5313 | (write ? PFERR_WRITE_MASK : 0); 5314 5315 /* 5316 * currently PKRU is only applied to ept enabled guest so 5317 * there is no pkey in EPT page table for L1 guest or EPT 5318 * shadow page table for L2 guest. 5319 */ 5320 if (vcpu_match_mmio_gva(vcpu, gva) 5321 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 5322 vcpu->arch.access, 0, access)) { 5323 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 5324 (gva & (PAGE_SIZE - 1)); 5325 trace_vcpu_match_mmio(gva, *gpa, write, false); 5326 return 1; 5327 } 5328 5329 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5330 5331 if (*gpa == UNMAPPED_GVA) 5332 return -1; 5333 5334 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 5335 } 5336 5337 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 5338 const void *val, int bytes) 5339 { 5340 int ret; 5341 5342 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 5343 if (ret < 0) 5344 return 0; 5345 kvm_page_track_write(vcpu, gpa, val, bytes); 5346 return 1; 5347 } 5348 5349 struct read_write_emulator_ops { 5350 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 5351 int bytes); 5352 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 5353 void *val, int bytes); 5354 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5355 int bytes, void *val); 5356 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5357 void *val, int bytes); 5358 bool write; 5359 }; 5360 5361 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 5362 { 5363 if (vcpu->mmio_read_completed) { 5364 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 5365 vcpu->mmio_fragments[0].gpa, val); 5366 vcpu->mmio_read_completed = 0; 5367 return 1; 5368 } 5369 5370 return 0; 5371 } 5372 5373 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5374 void *val, int bytes) 5375 { 5376 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 5377 } 5378 5379 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5380 void *val, int bytes) 5381 { 5382 return emulator_write_phys(vcpu, gpa, val, bytes); 5383 } 5384 5385 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 5386 { 5387 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 5388 return vcpu_mmio_write(vcpu, gpa, bytes, val); 5389 } 5390 5391 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5392 void *val, int bytes) 5393 { 5394 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 5395 return X86EMUL_IO_NEEDED; 5396 } 5397 5398 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5399 void *val, int bytes) 5400 { 5401 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 5402 5403 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 5404 return X86EMUL_CONTINUE; 5405 } 5406 5407 static const struct read_write_emulator_ops read_emultor = { 5408 .read_write_prepare = read_prepare, 5409 .read_write_emulate = read_emulate, 5410 .read_write_mmio = vcpu_mmio_read, 5411 .read_write_exit_mmio = read_exit_mmio, 5412 }; 5413 5414 static const struct read_write_emulator_ops write_emultor = { 5415 .read_write_emulate = write_emulate, 5416 .read_write_mmio = write_mmio, 5417 .read_write_exit_mmio = write_exit_mmio, 5418 .write = true, 5419 }; 5420 5421 static int emulator_read_write_onepage(unsigned long addr, void *val, 5422 unsigned int bytes, 5423 struct x86_exception *exception, 5424 struct kvm_vcpu *vcpu, 5425 const struct read_write_emulator_ops *ops) 5426 { 5427 gpa_t gpa; 5428 int handled, ret; 5429 bool write = ops->write; 5430 struct kvm_mmio_fragment *frag; 5431 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5432 5433 /* 5434 * If the exit was due to a NPF we may already have a GPA. 5435 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5436 * Note, this cannot be used on string operations since string 5437 * operation using rep will only have the initial GPA from the NPF 5438 * occurred. 5439 */ 5440 if (vcpu->arch.gpa_available && 5441 emulator_can_use_gpa(ctxt) && 5442 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 5443 gpa = vcpu->arch.gpa_val; 5444 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5445 } else { 5446 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5447 if (ret < 0) 5448 return X86EMUL_PROPAGATE_FAULT; 5449 } 5450 5451 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5452 return X86EMUL_CONTINUE; 5453 5454 /* 5455 * Is this MMIO handled locally? 5456 */ 5457 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5458 if (handled == bytes) 5459 return X86EMUL_CONTINUE; 5460 5461 gpa += handled; 5462 bytes -= handled; 5463 val += handled; 5464 5465 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5466 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5467 frag->gpa = gpa; 5468 frag->data = val; 5469 frag->len = bytes; 5470 return X86EMUL_CONTINUE; 5471 } 5472 5473 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5474 unsigned long addr, 5475 void *val, unsigned int bytes, 5476 struct x86_exception *exception, 5477 const struct read_write_emulator_ops *ops) 5478 { 5479 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5480 gpa_t gpa; 5481 int rc; 5482 5483 if (ops->read_write_prepare && 5484 ops->read_write_prepare(vcpu, val, bytes)) 5485 return X86EMUL_CONTINUE; 5486 5487 vcpu->mmio_nr_fragments = 0; 5488 5489 /* Crossing a page boundary? */ 5490 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5491 int now; 5492 5493 now = -addr & ~PAGE_MASK; 5494 rc = emulator_read_write_onepage(addr, val, now, exception, 5495 vcpu, ops); 5496 5497 if (rc != X86EMUL_CONTINUE) 5498 return rc; 5499 addr += now; 5500 if (ctxt->mode != X86EMUL_MODE_PROT64) 5501 addr = (u32)addr; 5502 val += now; 5503 bytes -= now; 5504 } 5505 5506 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5507 vcpu, ops); 5508 if (rc != X86EMUL_CONTINUE) 5509 return rc; 5510 5511 if (!vcpu->mmio_nr_fragments) 5512 return rc; 5513 5514 gpa = vcpu->mmio_fragments[0].gpa; 5515 5516 vcpu->mmio_needed = 1; 5517 vcpu->mmio_cur_fragment = 0; 5518 5519 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5520 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5521 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5522 vcpu->run->mmio.phys_addr = gpa; 5523 5524 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5525 } 5526 5527 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5528 unsigned long addr, 5529 void *val, 5530 unsigned int bytes, 5531 struct x86_exception *exception) 5532 { 5533 return emulator_read_write(ctxt, addr, val, bytes, 5534 exception, &read_emultor); 5535 } 5536 5537 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5538 unsigned long addr, 5539 const void *val, 5540 unsigned int bytes, 5541 struct x86_exception *exception) 5542 { 5543 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5544 exception, &write_emultor); 5545 } 5546 5547 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5548 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5549 5550 #ifdef CONFIG_X86_64 5551 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5552 #else 5553 # define CMPXCHG64(ptr, old, new) \ 5554 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5555 #endif 5556 5557 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5558 unsigned long addr, 5559 const void *old, 5560 const void *new, 5561 unsigned int bytes, 5562 struct x86_exception *exception) 5563 { 5564 struct kvm_host_map map; 5565 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5566 gpa_t gpa; 5567 char *kaddr; 5568 bool exchanged; 5569 5570 /* guests cmpxchg8b have to be emulated atomically */ 5571 if (bytes > 8 || (bytes & (bytes - 1))) 5572 goto emul_write; 5573 5574 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5575 5576 if (gpa == UNMAPPED_GVA || 5577 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5578 goto emul_write; 5579 5580 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 5581 goto emul_write; 5582 5583 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 5584 goto emul_write; 5585 5586 kaddr = map.hva + offset_in_page(gpa); 5587 5588 switch (bytes) { 5589 case 1: 5590 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5591 break; 5592 case 2: 5593 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5594 break; 5595 case 4: 5596 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5597 break; 5598 case 8: 5599 exchanged = CMPXCHG64(kaddr, old, new); 5600 break; 5601 default: 5602 BUG(); 5603 } 5604 5605 kvm_vcpu_unmap(vcpu, &map, true); 5606 5607 if (!exchanged) 5608 return X86EMUL_CMPXCHG_FAILED; 5609 5610 kvm_page_track_write(vcpu, gpa, new, bytes); 5611 5612 return X86EMUL_CONTINUE; 5613 5614 emul_write: 5615 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5616 5617 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5618 } 5619 5620 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5621 { 5622 int r = 0, i; 5623 5624 for (i = 0; i < vcpu->arch.pio.count; i++) { 5625 if (vcpu->arch.pio.in) 5626 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5627 vcpu->arch.pio.size, pd); 5628 else 5629 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5630 vcpu->arch.pio.port, vcpu->arch.pio.size, 5631 pd); 5632 if (r) 5633 break; 5634 pd += vcpu->arch.pio.size; 5635 } 5636 return r; 5637 } 5638 5639 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5640 unsigned short port, void *val, 5641 unsigned int count, bool in) 5642 { 5643 vcpu->arch.pio.port = port; 5644 vcpu->arch.pio.in = in; 5645 vcpu->arch.pio.count = count; 5646 vcpu->arch.pio.size = size; 5647 5648 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5649 vcpu->arch.pio.count = 0; 5650 return 1; 5651 } 5652 5653 vcpu->run->exit_reason = KVM_EXIT_IO; 5654 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5655 vcpu->run->io.size = size; 5656 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5657 vcpu->run->io.count = count; 5658 vcpu->run->io.port = port; 5659 5660 return 0; 5661 } 5662 5663 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5664 int size, unsigned short port, void *val, 5665 unsigned int count) 5666 { 5667 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5668 int ret; 5669 5670 if (vcpu->arch.pio.count) 5671 goto data_avail; 5672 5673 memset(vcpu->arch.pio_data, 0, size * count); 5674 5675 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5676 if (ret) { 5677 data_avail: 5678 memcpy(val, vcpu->arch.pio_data, size * count); 5679 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5680 vcpu->arch.pio.count = 0; 5681 return 1; 5682 } 5683 5684 return 0; 5685 } 5686 5687 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5688 int size, unsigned short port, 5689 const void *val, unsigned int count) 5690 { 5691 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5692 5693 memcpy(vcpu->arch.pio_data, val, size * count); 5694 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5695 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5696 } 5697 5698 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5699 { 5700 return kvm_x86_ops->get_segment_base(vcpu, seg); 5701 } 5702 5703 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 5704 { 5705 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 5706 } 5707 5708 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 5709 { 5710 if (!need_emulate_wbinvd(vcpu)) 5711 return X86EMUL_CONTINUE; 5712 5713 if (kvm_x86_ops->has_wbinvd_exit()) { 5714 int cpu = get_cpu(); 5715 5716 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5717 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5718 wbinvd_ipi, NULL, 1); 5719 put_cpu(); 5720 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5721 } else 5722 wbinvd(); 5723 return X86EMUL_CONTINUE; 5724 } 5725 5726 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5727 { 5728 kvm_emulate_wbinvd_noskip(vcpu); 5729 return kvm_skip_emulated_instruction(vcpu); 5730 } 5731 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5732 5733 5734 5735 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5736 { 5737 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5738 } 5739 5740 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5741 unsigned long *dest) 5742 { 5743 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5744 } 5745 5746 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5747 unsigned long value) 5748 { 5749 5750 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5751 } 5752 5753 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5754 { 5755 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5756 } 5757 5758 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5759 { 5760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5761 unsigned long value; 5762 5763 switch (cr) { 5764 case 0: 5765 value = kvm_read_cr0(vcpu); 5766 break; 5767 case 2: 5768 value = vcpu->arch.cr2; 5769 break; 5770 case 3: 5771 value = kvm_read_cr3(vcpu); 5772 break; 5773 case 4: 5774 value = kvm_read_cr4(vcpu); 5775 break; 5776 case 8: 5777 value = kvm_get_cr8(vcpu); 5778 break; 5779 default: 5780 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5781 return 0; 5782 } 5783 5784 return value; 5785 } 5786 5787 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5788 { 5789 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5790 int res = 0; 5791 5792 switch (cr) { 5793 case 0: 5794 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5795 break; 5796 case 2: 5797 vcpu->arch.cr2 = val; 5798 break; 5799 case 3: 5800 res = kvm_set_cr3(vcpu, val); 5801 break; 5802 case 4: 5803 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5804 break; 5805 case 8: 5806 res = kvm_set_cr8(vcpu, val); 5807 break; 5808 default: 5809 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5810 res = -1; 5811 } 5812 5813 return res; 5814 } 5815 5816 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5817 { 5818 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5819 } 5820 5821 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5822 { 5823 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5824 } 5825 5826 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5827 { 5828 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5829 } 5830 5831 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5832 { 5833 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5834 } 5835 5836 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5837 { 5838 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5839 } 5840 5841 static unsigned long emulator_get_cached_segment_base( 5842 struct x86_emulate_ctxt *ctxt, int seg) 5843 { 5844 return get_segment_base(emul_to_vcpu(ctxt), seg); 5845 } 5846 5847 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5848 struct desc_struct *desc, u32 *base3, 5849 int seg) 5850 { 5851 struct kvm_segment var; 5852 5853 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5854 *selector = var.selector; 5855 5856 if (var.unusable) { 5857 memset(desc, 0, sizeof(*desc)); 5858 if (base3) 5859 *base3 = 0; 5860 return false; 5861 } 5862 5863 if (var.g) 5864 var.limit >>= 12; 5865 set_desc_limit(desc, var.limit); 5866 set_desc_base(desc, (unsigned long)var.base); 5867 #ifdef CONFIG_X86_64 5868 if (base3) 5869 *base3 = var.base >> 32; 5870 #endif 5871 desc->type = var.type; 5872 desc->s = var.s; 5873 desc->dpl = var.dpl; 5874 desc->p = var.present; 5875 desc->avl = var.avl; 5876 desc->l = var.l; 5877 desc->d = var.db; 5878 desc->g = var.g; 5879 5880 return true; 5881 } 5882 5883 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5884 struct desc_struct *desc, u32 base3, 5885 int seg) 5886 { 5887 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5888 struct kvm_segment var; 5889 5890 var.selector = selector; 5891 var.base = get_desc_base(desc); 5892 #ifdef CONFIG_X86_64 5893 var.base |= ((u64)base3) << 32; 5894 #endif 5895 var.limit = get_desc_limit(desc); 5896 if (desc->g) 5897 var.limit = (var.limit << 12) | 0xfff; 5898 var.type = desc->type; 5899 var.dpl = desc->dpl; 5900 var.db = desc->d; 5901 var.s = desc->s; 5902 var.l = desc->l; 5903 var.g = desc->g; 5904 var.avl = desc->avl; 5905 var.present = desc->p; 5906 var.unusable = !var.present; 5907 var.padding = 0; 5908 5909 kvm_set_segment(vcpu, &var, seg); 5910 return; 5911 } 5912 5913 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5914 u32 msr_index, u64 *pdata) 5915 { 5916 struct msr_data msr; 5917 int r; 5918 5919 msr.index = msr_index; 5920 msr.host_initiated = false; 5921 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5922 if (r) 5923 return r; 5924 5925 *pdata = msr.data; 5926 return 0; 5927 } 5928 5929 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5930 u32 msr_index, u64 data) 5931 { 5932 struct msr_data msr; 5933 5934 msr.data = data; 5935 msr.index = msr_index; 5936 msr.host_initiated = false; 5937 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5938 } 5939 5940 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5941 { 5942 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5943 5944 return vcpu->arch.smbase; 5945 } 5946 5947 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5948 { 5949 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5950 5951 vcpu->arch.smbase = smbase; 5952 } 5953 5954 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5955 u32 pmc) 5956 { 5957 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5958 } 5959 5960 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5961 u32 pmc, u64 *pdata) 5962 { 5963 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5964 } 5965 5966 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5967 { 5968 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5969 } 5970 5971 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5972 struct x86_instruction_info *info, 5973 enum x86_intercept_stage stage) 5974 { 5975 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5976 } 5977 5978 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5979 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5980 { 5981 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5982 } 5983 5984 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5985 { 5986 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5987 } 5988 5989 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5990 { 5991 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5992 } 5993 5994 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5995 { 5996 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5997 } 5998 5999 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 6000 { 6001 return emul_to_vcpu(ctxt)->arch.hflags; 6002 } 6003 6004 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 6005 { 6006 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 6007 } 6008 6009 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 6010 const char *smstate) 6011 { 6012 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate); 6013 } 6014 6015 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 6016 { 6017 kvm_smm_changed(emul_to_vcpu(ctxt)); 6018 } 6019 6020 static const struct x86_emulate_ops emulate_ops = { 6021 .read_gpr = emulator_read_gpr, 6022 .write_gpr = emulator_write_gpr, 6023 .read_std = emulator_read_std, 6024 .write_std = emulator_write_std, 6025 .read_phys = kvm_read_guest_phys_system, 6026 .fetch = kvm_fetch_guest_virt, 6027 .read_emulated = emulator_read_emulated, 6028 .write_emulated = emulator_write_emulated, 6029 .cmpxchg_emulated = emulator_cmpxchg_emulated, 6030 .invlpg = emulator_invlpg, 6031 .pio_in_emulated = emulator_pio_in_emulated, 6032 .pio_out_emulated = emulator_pio_out_emulated, 6033 .get_segment = emulator_get_segment, 6034 .set_segment = emulator_set_segment, 6035 .get_cached_segment_base = emulator_get_cached_segment_base, 6036 .get_gdt = emulator_get_gdt, 6037 .get_idt = emulator_get_idt, 6038 .set_gdt = emulator_set_gdt, 6039 .set_idt = emulator_set_idt, 6040 .get_cr = emulator_get_cr, 6041 .set_cr = emulator_set_cr, 6042 .cpl = emulator_get_cpl, 6043 .get_dr = emulator_get_dr, 6044 .set_dr = emulator_set_dr, 6045 .get_smbase = emulator_get_smbase, 6046 .set_smbase = emulator_set_smbase, 6047 .set_msr = emulator_set_msr, 6048 .get_msr = emulator_get_msr, 6049 .check_pmc = emulator_check_pmc, 6050 .read_pmc = emulator_read_pmc, 6051 .halt = emulator_halt, 6052 .wbinvd = emulator_wbinvd, 6053 .fix_hypercall = emulator_fix_hypercall, 6054 .intercept = emulator_intercept, 6055 .get_cpuid = emulator_get_cpuid, 6056 .set_nmi_mask = emulator_set_nmi_mask, 6057 .get_hflags = emulator_get_hflags, 6058 .set_hflags = emulator_set_hflags, 6059 .pre_leave_smm = emulator_pre_leave_smm, 6060 .post_leave_smm = emulator_post_leave_smm, 6061 }; 6062 6063 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 6064 { 6065 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 6066 /* 6067 * an sti; sti; sequence only disable interrupts for the first 6068 * instruction. So, if the last instruction, be it emulated or 6069 * not, left the system with the INT_STI flag enabled, it 6070 * means that the last instruction is an sti. We should not 6071 * leave the flag on in this case. The same goes for mov ss 6072 */ 6073 if (int_shadow & mask) 6074 mask = 0; 6075 if (unlikely(int_shadow || mask)) { 6076 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 6077 if (!mask) 6078 kvm_make_request(KVM_REQ_EVENT, vcpu); 6079 } 6080 } 6081 6082 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 6083 { 6084 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6085 if (ctxt->exception.vector == PF_VECTOR) 6086 return kvm_propagate_fault(vcpu, &ctxt->exception); 6087 6088 if (ctxt->exception.error_code_valid) 6089 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 6090 ctxt->exception.error_code); 6091 else 6092 kvm_queue_exception(vcpu, ctxt->exception.vector); 6093 return false; 6094 } 6095 6096 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 6097 { 6098 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6099 int cs_db, cs_l; 6100 6101 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 6102 6103 ctxt->eflags = kvm_get_rflags(vcpu); 6104 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 6105 6106 ctxt->eip = kvm_rip_read(vcpu); 6107 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 6108 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 6109 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 6110 cs_db ? X86EMUL_MODE_PROT32 : 6111 X86EMUL_MODE_PROT16; 6112 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 6113 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 6114 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 6115 6116 init_decode_cache(ctxt); 6117 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6118 } 6119 6120 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 6121 { 6122 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6123 int ret; 6124 6125 init_emulate_ctxt(vcpu); 6126 6127 ctxt->op_bytes = 2; 6128 ctxt->ad_bytes = 2; 6129 ctxt->_eip = ctxt->eip + inc_eip; 6130 ret = emulate_int_real(ctxt, irq); 6131 6132 if (ret != X86EMUL_CONTINUE) 6133 return EMULATE_FAIL; 6134 6135 ctxt->eip = ctxt->_eip; 6136 kvm_rip_write(vcpu, ctxt->eip); 6137 kvm_set_rflags(vcpu, ctxt->eflags); 6138 6139 return EMULATE_DONE; 6140 } 6141 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 6142 6143 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 6144 { 6145 int r = EMULATE_DONE; 6146 6147 ++vcpu->stat.insn_emulation_fail; 6148 trace_kvm_emulate_insn_failed(vcpu); 6149 6150 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) 6151 return EMULATE_FAIL; 6152 6153 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 6154 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6155 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6156 vcpu->run->internal.ndata = 0; 6157 r = EMULATE_USER_EXIT; 6158 } 6159 6160 kvm_queue_exception(vcpu, UD_VECTOR); 6161 6162 return r; 6163 } 6164 6165 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 6166 bool write_fault_to_shadow_pgtable, 6167 int emulation_type) 6168 { 6169 gpa_t gpa = cr2; 6170 kvm_pfn_t pfn; 6171 6172 if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) 6173 return false; 6174 6175 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 6176 return false; 6177 6178 if (!vcpu->arch.mmu->direct_map) { 6179 /* 6180 * Write permission should be allowed since only 6181 * write access need to be emulated. 6182 */ 6183 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 6184 6185 /* 6186 * If the mapping is invalid in guest, let cpu retry 6187 * it to generate fault. 6188 */ 6189 if (gpa == UNMAPPED_GVA) 6190 return true; 6191 } 6192 6193 /* 6194 * Do not retry the unhandleable instruction if it faults on the 6195 * readonly host memory, otherwise it will goto a infinite loop: 6196 * retry instruction -> write #PF -> emulation fail -> retry 6197 * instruction -> ... 6198 */ 6199 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 6200 6201 /* 6202 * If the instruction failed on the error pfn, it can not be fixed, 6203 * report the error to userspace. 6204 */ 6205 if (is_error_noslot_pfn(pfn)) 6206 return false; 6207 6208 kvm_release_pfn_clean(pfn); 6209 6210 /* The instructions are well-emulated on direct mmu. */ 6211 if (vcpu->arch.mmu->direct_map) { 6212 unsigned int indirect_shadow_pages; 6213 6214 spin_lock(&vcpu->kvm->mmu_lock); 6215 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 6216 spin_unlock(&vcpu->kvm->mmu_lock); 6217 6218 if (indirect_shadow_pages) 6219 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6220 6221 return true; 6222 } 6223 6224 /* 6225 * if emulation was due to access to shadowed page table 6226 * and it failed try to unshadow page and re-enter the 6227 * guest to let CPU execute the instruction. 6228 */ 6229 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6230 6231 /* 6232 * If the access faults on its page table, it can not 6233 * be fixed by unprotecting shadow page and it should 6234 * be reported to userspace. 6235 */ 6236 return !write_fault_to_shadow_pgtable; 6237 } 6238 6239 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 6240 unsigned long cr2, int emulation_type) 6241 { 6242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6243 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 6244 6245 last_retry_eip = vcpu->arch.last_retry_eip; 6246 last_retry_addr = vcpu->arch.last_retry_addr; 6247 6248 /* 6249 * If the emulation is caused by #PF and it is non-page_table 6250 * writing instruction, it means the VM-EXIT is caused by shadow 6251 * page protected, we can zap the shadow page and retry this 6252 * instruction directly. 6253 * 6254 * Note: if the guest uses a non-page-table modifying instruction 6255 * on the PDE that points to the instruction, then we will unmap 6256 * the instruction and go to an infinite loop. So, we cache the 6257 * last retried eip and the last fault address, if we meet the eip 6258 * and the address again, we can break out of the potential infinite 6259 * loop. 6260 */ 6261 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 6262 6263 if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) 6264 return false; 6265 6266 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 6267 return false; 6268 6269 if (x86_page_table_writing_insn(ctxt)) 6270 return false; 6271 6272 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 6273 return false; 6274 6275 vcpu->arch.last_retry_eip = ctxt->eip; 6276 vcpu->arch.last_retry_addr = cr2; 6277 6278 if (!vcpu->arch.mmu->direct_map) 6279 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 6280 6281 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6282 6283 return true; 6284 } 6285 6286 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 6287 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 6288 6289 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 6290 { 6291 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 6292 /* This is a good place to trace that we are exiting SMM. */ 6293 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 6294 6295 /* Process a latched INIT or SMI, if any. */ 6296 kvm_make_request(KVM_REQ_EVENT, vcpu); 6297 } 6298 6299 kvm_mmu_reset_context(vcpu); 6300 } 6301 6302 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 6303 unsigned long *db) 6304 { 6305 u32 dr6 = 0; 6306 int i; 6307 u32 enable, rwlen; 6308 6309 enable = dr7; 6310 rwlen = dr7 >> 16; 6311 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 6312 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 6313 dr6 |= (1 << i); 6314 return dr6; 6315 } 6316 6317 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 6318 { 6319 struct kvm_run *kvm_run = vcpu->run; 6320 6321 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 6322 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 6323 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 6324 kvm_run->debug.arch.exception = DB_VECTOR; 6325 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6326 *r = EMULATE_USER_EXIT; 6327 } else { 6328 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 6329 } 6330 } 6331 6332 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 6333 { 6334 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6335 int r = EMULATE_DONE; 6336 6337 kvm_x86_ops->skip_emulated_instruction(vcpu); 6338 6339 /* 6340 * rflags is the old, "raw" value of the flags. The new value has 6341 * not been saved yet. 6342 * 6343 * This is correct even for TF set by the guest, because "the 6344 * processor will not generate this exception after the instruction 6345 * that sets the TF flag". 6346 */ 6347 if (unlikely(rflags & X86_EFLAGS_TF)) 6348 kvm_vcpu_do_singlestep(vcpu, &r); 6349 return r == EMULATE_DONE; 6350 } 6351 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 6352 6353 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 6354 { 6355 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 6356 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 6357 struct kvm_run *kvm_run = vcpu->run; 6358 unsigned long eip = kvm_get_linear_rip(vcpu); 6359 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6360 vcpu->arch.guest_debug_dr7, 6361 vcpu->arch.eff_db); 6362 6363 if (dr6 != 0) { 6364 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 6365 kvm_run->debug.arch.pc = eip; 6366 kvm_run->debug.arch.exception = DB_VECTOR; 6367 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6368 *r = EMULATE_USER_EXIT; 6369 return true; 6370 } 6371 } 6372 6373 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 6374 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 6375 unsigned long eip = kvm_get_linear_rip(vcpu); 6376 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6377 vcpu->arch.dr7, 6378 vcpu->arch.db); 6379 6380 if (dr6 != 0) { 6381 vcpu->arch.dr6 &= ~15; 6382 vcpu->arch.dr6 |= dr6 | DR6_RTM; 6383 kvm_queue_exception(vcpu, DB_VECTOR); 6384 *r = EMULATE_DONE; 6385 return true; 6386 } 6387 } 6388 6389 return false; 6390 } 6391 6392 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 6393 { 6394 switch (ctxt->opcode_len) { 6395 case 1: 6396 switch (ctxt->b) { 6397 case 0xe4: /* IN */ 6398 case 0xe5: 6399 case 0xec: 6400 case 0xed: 6401 case 0xe6: /* OUT */ 6402 case 0xe7: 6403 case 0xee: 6404 case 0xef: 6405 case 0x6c: /* INS */ 6406 case 0x6d: 6407 case 0x6e: /* OUTS */ 6408 case 0x6f: 6409 return true; 6410 } 6411 break; 6412 case 2: 6413 switch (ctxt->b) { 6414 case 0x33: /* RDPMC */ 6415 return true; 6416 } 6417 break; 6418 } 6419 6420 return false; 6421 } 6422 6423 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 6424 unsigned long cr2, 6425 int emulation_type, 6426 void *insn, 6427 int insn_len) 6428 { 6429 int r; 6430 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6431 bool writeback = true; 6432 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6433 6434 vcpu->arch.l1tf_flush_l1d = true; 6435 6436 /* 6437 * Clear write_fault_to_shadow_pgtable here to ensure it is 6438 * never reused. 6439 */ 6440 vcpu->arch.write_fault_to_shadow_pgtable = false; 6441 kvm_clear_exception_queue(vcpu); 6442 6443 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6444 init_emulate_ctxt(vcpu); 6445 6446 /* 6447 * We will reenter on the same instruction since 6448 * we do not set complete_userspace_io. This does not 6449 * handle watchpoints yet, those would be handled in 6450 * the emulate_ops. 6451 */ 6452 if (!(emulation_type & EMULTYPE_SKIP) && 6453 kvm_vcpu_check_breakpoint(vcpu, &r)) 6454 return r; 6455 6456 ctxt->interruptibility = 0; 6457 ctxt->have_exception = false; 6458 ctxt->exception.vector = -1; 6459 ctxt->perm_ok = false; 6460 6461 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6462 6463 r = x86_decode_insn(ctxt, insn, insn_len); 6464 6465 trace_kvm_emulate_insn_start(vcpu); 6466 ++vcpu->stat.insn_emulation; 6467 if (r != EMULATION_OK) { 6468 if (emulation_type & EMULTYPE_TRAP_UD) 6469 return EMULATE_FAIL; 6470 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6471 emulation_type)) 6472 return EMULATE_DONE; 6473 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 6474 return EMULATE_DONE; 6475 if (emulation_type & EMULTYPE_SKIP) 6476 return EMULATE_FAIL; 6477 return handle_emulation_failure(vcpu, emulation_type); 6478 } 6479 } 6480 6481 if ((emulation_type & EMULTYPE_VMWARE) && 6482 !is_vmware_backdoor_opcode(ctxt)) 6483 return EMULATE_FAIL; 6484 6485 if (emulation_type & EMULTYPE_SKIP) { 6486 kvm_rip_write(vcpu, ctxt->_eip); 6487 if (ctxt->eflags & X86_EFLAGS_RF) 6488 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6489 return EMULATE_DONE; 6490 } 6491 6492 if (retry_instruction(ctxt, cr2, emulation_type)) 6493 return EMULATE_DONE; 6494 6495 /* this is needed for vmware backdoor interface to work since it 6496 changes registers values during IO operation */ 6497 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6498 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6499 emulator_invalidate_register_cache(ctxt); 6500 } 6501 6502 restart: 6503 /* Save the faulting GPA (cr2) in the address field */ 6504 ctxt->exception.address = cr2; 6505 6506 r = x86_emulate_insn(ctxt); 6507 6508 if (r == EMULATION_INTERCEPTED) 6509 return EMULATE_DONE; 6510 6511 if (r == EMULATION_FAILED) { 6512 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6513 emulation_type)) 6514 return EMULATE_DONE; 6515 6516 return handle_emulation_failure(vcpu, emulation_type); 6517 } 6518 6519 if (ctxt->have_exception) { 6520 r = EMULATE_DONE; 6521 if (inject_emulated_exception(vcpu)) 6522 return r; 6523 } else if (vcpu->arch.pio.count) { 6524 if (!vcpu->arch.pio.in) { 6525 /* FIXME: return into emulator if single-stepping. */ 6526 vcpu->arch.pio.count = 0; 6527 } else { 6528 writeback = false; 6529 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6530 } 6531 r = EMULATE_USER_EXIT; 6532 } else if (vcpu->mmio_needed) { 6533 if (!vcpu->mmio_is_write) 6534 writeback = false; 6535 r = EMULATE_USER_EXIT; 6536 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6537 } else if (r == EMULATION_RESTART) 6538 goto restart; 6539 else 6540 r = EMULATE_DONE; 6541 6542 if (writeback) { 6543 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6544 toggle_interruptibility(vcpu, ctxt->interruptibility); 6545 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6546 kvm_rip_write(vcpu, ctxt->eip); 6547 if (r == EMULATE_DONE && ctxt->tf) 6548 kvm_vcpu_do_singlestep(vcpu, &r); 6549 if (!ctxt->have_exception || 6550 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 6551 __kvm_set_rflags(vcpu, ctxt->eflags); 6552 6553 /* 6554 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6555 * do nothing, and it will be requested again as soon as 6556 * the shadow expires. But we still need to check here, 6557 * because POPF has no interrupt shadow. 6558 */ 6559 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6560 kvm_make_request(KVM_REQ_EVENT, vcpu); 6561 } else 6562 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6563 6564 return r; 6565 } 6566 6567 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 6568 { 6569 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 6570 } 6571 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 6572 6573 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 6574 void *insn, int insn_len) 6575 { 6576 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 6577 } 6578 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 6579 6580 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 6581 { 6582 vcpu->arch.pio.count = 0; 6583 return 1; 6584 } 6585 6586 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 6587 { 6588 vcpu->arch.pio.count = 0; 6589 6590 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 6591 return 1; 6592 6593 return kvm_skip_emulated_instruction(vcpu); 6594 } 6595 6596 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6597 unsigned short port) 6598 { 6599 unsigned long val = kvm_rax_read(vcpu); 6600 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 6601 size, port, &val, 1); 6602 if (ret) 6603 return ret; 6604 6605 /* 6606 * Workaround userspace that relies on old KVM behavior of %rip being 6607 * incremented prior to exiting to userspace to handle "OUT 0x7e". 6608 */ 6609 if (port == 0x7e && 6610 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 6611 vcpu->arch.complete_userspace_io = 6612 complete_fast_pio_out_port_0x7e; 6613 kvm_skip_emulated_instruction(vcpu); 6614 } else { 6615 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6616 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 6617 } 6618 return 0; 6619 } 6620 6621 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6622 { 6623 unsigned long val; 6624 6625 /* We should only ever be called with arch.pio.count equal to 1 */ 6626 BUG_ON(vcpu->arch.pio.count != 1); 6627 6628 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 6629 vcpu->arch.pio.count = 0; 6630 return 1; 6631 } 6632 6633 /* For size less than 4 we merge, else we zero extend */ 6634 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 6635 6636 /* 6637 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 6638 * the copy and tracing 6639 */ 6640 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 6641 vcpu->arch.pio.port, &val, 1); 6642 kvm_rax_write(vcpu, val); 6643 6644 return kvm_skip_emulated_instruction(vcpu); 6645 } 6646 6647 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 6648 unsigned short port) 6649 { 6650 unsigned long val; 6651 int ret; 6652 6653 /* For size less than 4 we merge, else we zero extend */ 6654 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 6655 6656 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 6657 &val, 1); 6658 if (ret) { 6659 kvm_rax_write(vcpu, val); 6660 return ret; 6661 } 6662 6663 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6664 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 6665 6666 return 0; 6667 } 6668 6669 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 6670 { 6671 int ret; 6672 6673 if (in) 6674 ret = kvm_fast_pio_in(vcpu, size, port); 6675 else 6676 ret = kvm_fast_pio_out(vcpu, size, port); 6677 return ret && kvm_skip_emulated_instruction(vcpu); 6678 } 6679 EXPORT_SYMBOL_GPL(kvm_fast_pio); 6680 6681 static int kvmclock_cpu_down_prep(unsigned int cpu) 6682 { 6683 __this_cpu_write(cpu_tsc_khz, 0); 6684 return 0; 6685 } 6686 6687 static void tsc_khz_changed(void *data) 6688 { 6689 struct cpufreq_freqs *freq = data; 6690 unsigned long khz = 0; 6691 6692 if (data) 6693 khz = freq->new; 6694 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6695 khz = cpufreq_quick_get(raw_smp_processor_id()); 6696 if (!khz) 6697 khz = tsc_khz; 6698 __this_cpu_write(cpu_tsc_khz, khz); 6699 } 6700 6701 #ifdef CONFIG_X86_64 6702 static void kvm_hyperv_tsc_notifier(void) 6703 { 6704 struct kvm *kvm; 6705 struct kvm_vcpu *vcpu; 6706 int cpu; 6707 6708 spin_lock(&kvm_lock); 6709 list_for_each_entry(kvm, &vm_list, vm_list) 6710 kvm_make_mclock_inprogress_request(kvm); 6711 6712 hyperv_stop_tsc_emulation(); 6713 6714 /* TSC frequency always matches when on Hyper-V */ 6715 for_each_present_cpu(cpu) 6716 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 6717 kvm_max_guest_tsc_khz = tsc_khz; 6718 6719 list_for_each_entry(kvm, &vm_list, vm_list) { 6720 struct kvm_arch *ka = &kvm->arch; 6721 6722 spin_lock(&ka->pvclock_gtod_sync_lock); 6723 6724 pvclock_update_vm_gtod_copy(kvm); 6725 6726 kvm_for_each_vcpu(cpu, vcpu, kvm) 6727 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6728 6729 kvm_for_each_vcpu(cpu, vcpu, kvm) 6730 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 6731 6732 spin_unlock(&ka->pvclock_gtod_sync_lock); 6733 } 6734 spin_unlock(&kvm_lock); 6735 } 6736 #endif 6737 6738 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 6739 { 6740 struct kvm *kvm; 6741 struct kvm_vcpu *vcpu; 6742 int i, send_ipi = 0; 6743 6744 /* 6745 * We allow guests to temporarily run on slowing clocks, 6746 * provided we notify them after, or to run on accelerating 6747 * clocks, provided we notify them before. Thus time never 6748 * goes backwards. 6749 * 6750 * However, we have a problem. We can't atomically update 6751 * the frequency of a given CPU from this function; it is 6752 * merely a notifier, which can be called from any CPU. 6753 * Changing the TSC frequency at arbitrary points in time 6754 * requires a recomputation of local variables related to 6755 * the TSC for each VCPU. We must flag these local variables 6756 * to be updated and be sure the update takes place with the 6757 * new frequency before any guests proceed. 6758 * 6759 * Unfortunately, the combination of hotplug CPU and frequency 6760 * change creates an intractable locking scenario; the order 6761 * of when these callouts happen is undefined with respect to 6762 * CPU hotplug, and they can race with each other. As such, 6763 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 6764 * undefined; you can actually have a CPU frequency change take 6765 * place in between the computation of X and the setting of the 6766 * variable. To protect against this problem, all updates of 6767 * the per_cpu tsc_khz variable are done in an interrupt 6768 * protected IPI, and all callers wishing to update the value 6769 * must wait for a synchronous IPI to complete (which is trivial 6770 * if the caller is on the CPU already). This establishes the 6771 * necessary total order on variable updates. 6772 * 6773 * Note that because a guest time update may take place 6774 * anytime after the setting of the VCPU's request bit, the 6775 * correct TSC value must be set before the request. However, 6776 * to ensure the update actually makes it to any guest which 6777 * starts running in hardware virtualization between the set 6778 * and the acquisition of the spinlock, we must also ping the 6779 * CPU after setting the request bit. 6780 * 6781 */ 6782 6783 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 6784 6785 spin_lock(&kvm_lock); 6786 list_for_each_entry(kvm, &vm_list, vm_list) { 6787 kvm_for_each_vcpu(i, vcpu, kvm) { 6788 if (vcpu->cpu != cpu) 6789 continue; 6790 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6791 if (vcpu->cpu != smp_processor_id()) 6792 send_ipi = 1; 6793 } 6794 } 6795 spin_unlock(&kvm_lock); 6796 6797 if (freq->old < freq->new && send_ipi) { 6798 /* 6799 * We upscale the frequency. Must make the guest 6800 * doesn't see old kvmclock values while running with 6801 * the new frequency, otherwise we risk the guest sees 6802 * time go backwards. 6803 * 6804 * In case we update the frequency for another cpu 6805 * (which might be in guest context) send an interrupt 6806 * to kick the cpu out of guest context. Next time 6807 * guest context is entered kvmclock will be updated, 6808 * so the guest will not see stale values. 6809 */ 6810 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 6811 } 6812 } 6813 6814 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 6815 void *data) 6816 { 6817 struct cpufreq_freqs *freq = data; 6818 int cpu; 6819 6820 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 6821 return 0; 6822 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 6823 return 0; 6824 6825 for_each_cpu(cpu, freq->policy->cpus) 6826 __kvmclock_cpufreq_notifier(freq, cpu); 6827 6828 return 0; 6829 } 6830 6831 static struct notifier_block kvmclock_cpufreq_notifier_block = { 6832 .notifier_call = kvmclock_cpufreq_notifier 6833 }; 6834 6835 static int kvmclock_cpu_online(unsigned int cpu) 6836 { 6837 tsc_khz_changed(NULL); 6838 return 0; 6839 } 6840 6841 static void kvm_timer_init(void) 6842 { 6843 max_tsc_khz = tsc_khz; 6844 6845 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 6846 #ifdef CONFIG_CPU_FREQ 6847 struct cpufreq_policy policy; 6848 int cpu; 6849 6850 memset(&policy, 0, sizeof(policy)); 6851 cpu = get_cpu(); 6852 cpufreq_get_policy(&policy, cpu); 6853 if (policy.cpuinfo.max_freq) 6854 max_tsc_khz = policy.cpuinfo.max_freq; 6855 put_cpu(); 6856 #endif 6857 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6858 CPUFREQ_TRANSITION_NOTIFIER); 6859 } 6860 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6861 6862 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6863 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6864 } 6865 6866 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6867 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 6868 6869 int kvm_is_in_guest(void) 6870 { 6871 return __this_cpu_read(current_vcpu) != NULL; 6872 } 6873 6874 static int kvm_is_user_mode(void) 6875 { 6876 int user_mode = 3; 6877 6878 if (__this_cpu_read(current_vcpu)) 6879 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6880 6881 return user_mode != 0; 6882 } 6883 6884 static unsigned long kvm_get_guest_ip(void) 6885 { 6886 unsigned long ip = 0; 6887 6888 if (__this_cpu_read(current_vcpu)) 6889 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6890 6891 return ip; 6892 } 6893 6894 static void kvm_handle_intel_pt_intr(void) 6895 { 6896 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 6897 6898 kvm_make_request(KVM_REQ_PMI, vcpu); 6899 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 6900 (unsigned long *)&vcpu->arch.pmu.global_status); 6901 } 6902 6903 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6904 .is_in_guest = kvm_is_in_guest, 6905 .is_user_mode = kvm_is_user_mode, 6906 .get_guest_ip = kvm_get_guest_ip, 6907 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 6908 }; 6909 6910 static void kvm_set_mmio_spte_mask(void) 6911 { 6912 u64 mask; 6913 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6914 6915 /* 6916 * Set the reserved bits and the present bit of an paging-structure 6917 * entry to generate page fault with PFER.RSV = 1. 6918 */ 6919 6920 /* 6921 * Mask the uppermost physical address bit, which would be reserved as 6922 * long as the supported physical address width is less than 52. 6923 */ 6924 mask = 1ull << 51; 6925 6926 /* Set the present bit. */ 6927 mask |= 1ull; 6928 6929 /* 6930 * If reserved bit is not supported, clear the present bit to disable 6931 * mmio page fault. 6932 */ 6933 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52) 6934 mask &= ~1ull; 6935 6936 kvm_mmu_set_mmio_spte_mask(mask, mask); 6937 } 6938 6939 #ifdef CONFIG_X86_64 6940 static void pvclock_gtod_update_fn(struct work_struct *work) 6941 { 6942 struct kvm *kvm; 6943 6944 struct kvm_vcpu *vcpu; 6945 int i; 6946 6947 spin_lock(&kvm_lock); 6948 list_for_each_entry(kvm, &vm_list, vm_list) 6949 kvm_for_each_vcpu(i, vcpu, kvm) 6950 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6951 atomic_set(&kvm_guest_has_master_clock, 0); 6952 spin_unlock(&kvm_lock); 6953 } 6954 6955 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6956 6957 /* 6958 * Notification about pvclock gtod data update. 6959 */ 6960 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6961 void *priv) 6962 { 6963 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6964 struct timekeeper *tk = priv; 6965 6966 update_pvclock_gtod(tk); 6967 6968 /* disable master clock if host does not trust, or does not 6969 * use, TSC based clocksource. 6970 */ 6971 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 6972 atomic_read(&kvm_guest_has_master_clock) != 0) 6973 queue_work(system_long_wq, &pvclock_gtod_work); 6974 6975 return 0; 6976 } 6977 6978 static struct notifier_block pvclock_gtod_notifier = { 6979 .notifier_call = pvclock_gtod_notify, 6980 }; 6981 #endif 6982 6983 int kvm_arch_init(void *opaque) 6984 { 6985 int r; 6986 struct kvm_x86_ops *ops = opaque; 6987 6988 if (kvm_x86_ops) { 6989 printk(KERN_ERR "kvm: already loaded the other module\n"); 6990 r = -EEXIST; 6991 goto out; 6992 } 6993 6994 if (!ops->cpu_has_kvm_support()) { 6995 printk(KERN_ERR "kvm: no hardware support\n"); 6996 r = -EOPNOTSUPP; 6997 goto out; 6998 } 6999 if (ops->disabled_by_bios()) { 7000 printk(KERN_ERR "kvm: disabled by bios\n"); 7001 r = -EOPNOTSUPP; 7002 goto out; 7003 } 7004 7005 /* 7006 * KVM explicitly assumes that the guest has an FPU and 7007 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 7008 * vCPU's FPU state as a fxregs_state struct. 7009 */ 7010 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 7011 printk(KERN_ERR "kvm: inadequate fpu\n"); 7012 r = -EOPNOTSUPP; 7013 goto out; 7014 } 7015 7016 r = -ENOMEM; 7017 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 7018 __alignof__(struct fpu), SLAB_ACCOUNT, 7019 NULL); 7020 if (!x86_fpu_cache) { 7021 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 7022 goto out; 7023 } 7024 7025 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 7026 if (!shared_msrs) { 7027 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 7028 goto out_free_x86_fpu_cache; 7029 } 7030 7031 r = kvm_mmu_module_init(); 7032 if (r) 7033 goto out_free_percpu; 7034 7035 kvm_set_mmio_spte_mask(); 7036 7037 kvm_x86_ops = ops; 7038 7039 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 7040 PT_DIRTY_MASK, PT64_NX_MASK, 0, 7041 PT_PRESENT_MASK, 0, sme_me_mask); 7042 kvm_timer_init(); 7043 7044 perf_register_guest_info_callbacks(&kvm_guest_cbs); 7045 7046 if (boot_cpu_has(X86_FEATURE_XSAVE)) 7047 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 7048 7049 kvm_lapic_init(); 7050 #ifdef CONFIG_X86_64 7051 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 7052 7053 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7054 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 7055 #endif 7056 7057 return 0; 7058 7059 out_free_percpu: 7060 free_percpu(shared_msrs); 7061 out_free_x86_fpu_cache: 7062 kmem_cache_destroy(x86_fpu_cache); 7063 out: 7064 return r; 7065 } 7066 7067 void kvm_arch_exit(void) 7068 { 7069 #ifdef CONFIG_X86_64 7070 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7071 clear_hv_tscchange_cb(); 7072 #endif 7073 kvm_lapic_exit(); 7074 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 7075 7076 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7077 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 7078 CPUFREQ_TRANSITION_NOTIFIER); 7079 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 7080 #ifdef CONFIG_X86_64 7081 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 7082 #endif 7083 kvm_x86_ops = NULL; 7084 kvm_mmu_module_exit(); 7085 free_percpu(shared_msrs); 7086 kmem_cache_destroy(x86_fpu_cache); 7087 } 7088 7089 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 7090 { 7091 ++vcpu->stat.halt_exits; 7092 if (lapic_in_kernel(vcpu)) { 7093 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 7094 return 1; 7095 } else { 7096 vcpu->run->exit_reason = KVM_EXIT_HLT; 7097 return 0; 7098 } 7099 } 7100 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 7101 7102 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 7103 { 7104 int ret = kvm_skip_emulated_instruction(vcpu); 7105 /* 7106 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 7107 * KVM_EXIT_DEBUG here. 7108 */ 7109 return kvm_vcpu_halt(vcpu) && ret; 7110 } 7111 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 7112 7113 #ifdef CONFIG_X86_64 7114 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 7115 unsigned long clock_type) 7116 { 7117 struct kvm_clock_pairing clock_pairing; 7118 struct timespec64 ts; 7119 u64 cycle; 7120 int ret; 7121 7122 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 7123 return -KVM_EOPNOTSUPP; 7124 7125 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 7126 return -KVM_EOPNOTSUPP; 7127 7128 clock_pairing.sec = ts.tv_sec; 7129 clock_pairing.nsec = ts.tv_nsec; 7130 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 7131 clock_pairing.flags = 0; 7132 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 7133 7134 ret = 0; 7135 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 7136 sizeof(struct kvm_clock_pairing))) 7137 ret = -KVM_EFAULT; 7138 7139 return ret; 7140 } 7141 #endif 7142 7143 /* 7144 * kvm_pv_kick_cpu_op: Kick a vcpu. 7145 * 7146 * @apicid - apicid of vcpu to be kicked. 7147 */ 7148 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 7149 { 7150 struct kvm_lapic_irq lapic_irq; 7151 7152 lapic_irq.shorthand = 0; 7153 lapic_irq.dest_mode = 0; 7154 lapic_irq.level = 0; 7155 lapic_irq.dest_id = apicid; 7156 lapic_irq.msi_redir_hint = false; 7157 7158 lapic_irq.delivery_mode = APIC_DM_REMRD; 7159 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 7160 } 7161 7162 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 7163 { 7164 if (!lapic_in_kernel(vcpu)) { 7165 WARN_ON_ONCE(vcpu->arch.apicv_active); 7166 return; 7167 } 7168 if (!vcpu->arch.apicv_active) 7169 return; 7170 7171 vcpu->arch.apicv_active = false; 7172 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 7173 } 7174 7175 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 7176 { 7177 unsigned long nr, a0, a1, a2, a3, ret; 7178 int op_64_bit; 7179 7180 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 7181 return kvm_hv_hypercall(vcpu); 7182 7183 nr = kvm_rax_read(vcpu); 7184 a0 = kvm_rbx_read(vcpu); 7185 a1 = kvm_rcx_read(vcpu); 7186 a2 = kvm_rdx_read(vcpu); 7187 a3 = kvm_rsi_read(vcpu); 7188 7189 trace_kvm_hypercall(nr, a0, a1, a2, a3); 7190 7191 op_64_bit = is_64_bit_mode(vcpu); 7192 if (!op_64_bit) { 7193 nr &= 0xFFFFFFFF; 7194 a0 &= 0xFFFFFFFF; 7195 a1 &= 0xFFFFFFFF; 7196 a2 &= 0xFFFFFFFF; 7197 a3 &= 0xFFFFFFFF; 7198 } 7199 7200 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 7201 ret = -KVM_EPERM; 7202 goto out; 7203 } 7204 7205 switch (nr) { 7206 case KVM_HC_VAPIC_POLL_IRQ: 7207 ret = 0; 7208 break; 7209 case KVM_HC_KICK_CPU: 7210 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 7211 ret = 0; 7212 break; 7213 #ifdef CONFIG_X86_64 7214 case KVM_HC_CLOCK_PAIRING: 7215 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 7216 break; 7217 #endif 7218 case KVM_HC_SEND_IPI: 7219 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 7220 break; 7221 default: 7222 ret = -KVM_ENOSYS; 7223 break; 7224 } 7225 out: 7226 if (!op_64_bit) 7227 ret = (u32)ret; 7228 kvm_rax_write(vcpu, ret); 7229 7230 ++vcpu->stat.hypercalls; 7231 return kvm_skip_emulated_instruction(vcpu); 7232 } 7233 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 7234 7235 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 7236 { 7237 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7238 char instruction[3]; 7239 unsigned long rip = kvm_rip_read(vcpu); 7240 7241 kvm_x86_ops->patch_hypercall(vcpu, instruction); 7242 7243 return emulator_write_emulated(ctxt, rip, instruction, 3, 7244 &ctxt->exception); 7245 } 7246 7247 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 7248 { 7249 return vcpu->run->request_interrupt_window && 7250 likely(!pic_in_kernel(vcpu->kvm)); 7251 } 7252 7253 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 7254 { 7255 struct kvm_run *kvm_run = vcpu->run; 7256 7257 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 7258 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 7259 kvm_run->cr8 = kvm_get_cr8(vcpu); 7260 kvm_run->apic_base = kvm_get_apic_base(vcpu); 7261 kvm_run->ready_for_interrupt_injection = 7262 pic_in_kernel(vcpu->kvm) || 7263 kvm_vcpu_ready_for_interrupt_injection(vcpu); 7264 } 7265 7266 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 7267 { 7268 int max_irr, tpr; 7269 7270 if (!kvm_x86_ops->update_cr8_intercept) 7271 return; 7272 7273 if (!lapic_in_kernel(vcpu)) 7274 return; 7275 7276 if (vcpu->arch.apicv_active) 7277 return; 7278 7279 if (!vcpu->arch.apic->vapic_addr) 7280 max_irr = kvm_lapic_find_highest_irr(vcpu); 7281 else 7282 max_irr = -1; 7283 7284 if (max_irr != -1) 7285 max_irr >>= 4; 7286 7287 tpr = kvm_lapic_get_cr8(vcpu); 7288 7289 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 7290 } 7291 7292 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 7293 { 7294 int r; 7295 7296 /* try to reinject previous events if any */ 7297 7298 if (vcpu->arch.exception.injected) 7299 kvm_x86_ops->queue_exception(vcpu); 7300 /* 7301 * Do not inject an NMI or interrupt if there is a pending 7302 * exception. Exceptions and interrupts are recognized at 7303 * instruction boundaries, i.e. the start of an instruction. 7304 * Trap-like exceptions, e.g. #DB, have higher priority than 7305 * NMIs and interrupts, i.e. traps are recognized before an 7306 * NMI/interrupt that's pending on the same instruction. 7307 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 7308 * priority, but are only generated (pended) during instruction 7309 * execution, i.e. a pending fault-like exception means the 7310 * fault occurred on the *previous* instruction and must be 7311 * serviced prior to recognizing any new events in order to 7312 * fully complete the previous instruction. 7313 */ 7314 else if (!vcpu->arch.exception.pending) { 7315 if (vcpu->arch.nmi_injected) 7316 kvm_x86_ops->set_nmi(vcpu); 7317 else if (vcpu->arch.interrupt.injected) 7318 kvm_x86_ops->set_irq(vcpu); 7319 } 7320 7321 /* 7322 * Call check_nested_events() even if we reinjected a previous event 7323 * in order for caller to determine if it should require immediate-exit 7324 * from L2 to L1 due to pending L1 events which require exit 7325 * from L2 to L1. 7326 */ 7327 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 7328 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 7329 if (r != 0) 7330 return r; 7331 } 7332 7333 /* try to inject new event if pending */ 7334 if (vcpu->arch.exception.pending) { 7335 trace_kvm_inj_exception(vcpu->arch.exception.nr, 7336 vcpu->arch.exception.has_error_code, 7337 vcpu->arch.exception.error_code); 7338 7339 WARN_ON_ONCE(vcpu->arch.exception.injected); 7340 vcpu->arch.exception.pending = false; 7341 vcpu->arch.exception.injected = true; 7342 7343 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 7344 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 7345 X86_EFLAGS_RF); 7346 7347 if (vcpu->arch.exception.nr == DB_VECTOR) { 7348 /* 7349 * This code assumes that nSVM doesn't use 7350 * check_nested_events(). If it does, the 7351 * DR6/DR7 changes should happen before L1 7352 * gets a #VMEXIT for an intercepted #DB in 7353 * L2. (Under VMX, on the other hand, the 7354 * DR6/DR7 changes should not happen in the 7355 * event of a VM-exit to L1 for an intercepted 7356 * #DB in L2.) 7357 */ 7358 kvm_deliver_exception_payload(vcpu); 7359 if (vcpu->arch.dr7 & DR7_GD) { 7360 vcpu->arch.dr7 &= ~DR7_GD; 7361 kvm_update_dr7(vcpu); 7362 } 7363 } 7364 7365 kvm_x86_ops->queue_exception(vcpu); 7366 } 7367 7368 /* Don't consider new event if we re-injected an event */ 7369 if (kvm_event_needs_reinjection(vcpu)) 7370 return 0; 7371 7372 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 7373 kvm_x86_ops->smi_allowed(vcpu)) { 7374 vcpu->arch.smi_pending = false; 7375 ++vcpu->arch.smi_count; 7376 enter_smm(vcpu); 7377 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 7378 --vcpu->arch.nmi_pending; 7379 vcpu->arch.nmi_injected = true; 7380 kvm_x86_ops->set_nmi(vcpu); 7381 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 7382 /* 7383 * Because interrupts can be injected asynchronously, we are 7384 * calling check_nested_events again here to avoid a race condition. 7385 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 7386 * proposal and current concerns. Perhaps we should be setting 7387 * KVM_REQ_EVENT only on certain events and not unconditionally? 7388 */ 7389 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 7390 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 7391 if (r != 0) 7392 return r; 7393 } 7394 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 7395 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 7396 false); 7397 kvm_x86_ops->set_irq(vcpu); 7398 } 7399 } 7400 7401 return 0; 7402 } 7403 7404 static void process_nmi(struct kvm_vcpu *vcpu) 7405 { 7406 unsigned limit = 2; 7407 7408 /* 7409 * x86 is limited to one NMI running, and one NMI pending after it. 7410 * If an NMI is already in progress, limit further NMIs to just one. 7411 * Otherwise, allow two (and we'll inject the first one immediately). 7412 */ 7413 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 7414 limit = 1; 7415 7416 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 7417 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 7418 kvm_make_request(KVM_REQ_EVENT, vcpu); 7419 } 7420 7421 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 7422 { 7423 u32 flags = 0; 7424 flags |= seg->g << 23; 7425 flags |= seg->db << 22; 7426 flags |= seg->l << 21; 7427 flags |= seg->avl << 20; 7428 flags |= seg->present << 15; 7429 flags |= seg->dpl << 13; 7430 flags |= seg->s << 12; 7431 flags |= seg->type << 8; 7432 return flags; 7433 } 7434 7435 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 7436 { 7437 struct kvm_segment seg; 7438 int offset; 7439 7440 kvm_get_segment(vcpu, &seg, n); 7441 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 7442 7443 if (n < 3) 7444 offset = 0x7f84 + n * 12; 7445 else 7446 offset = 0x7f2c + (n - 3) * 12; 7447 7448 put_smstate(u32, buf, offset + 8, seg.base); 7449 put_smstate(u32, buf, offset + 4, seg.limit); 7450 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 7451 } 7452 7453 #ifdef CONFIG_X86_64 7454 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 7455 { 7456 struct kvm_segment seg; 7457 int offset; 7458 u16 flags; 7459 7460 kvm_get_segment(vcpu, &seg, n); 7461 offset = 0x7e00 + n * 16; 7462 7463 flags = enter_smm_get_segment_flags(&seg) >> 8; 7464 put_smstate(u16, buf, offset, seg.selector); 7465 put_smstate(u16, buf, offset + 2, flags); 7466 put_smstate(u32, buf, offset + 4, seg.limit); 7467 put_smstate(u64, buf, offset + 8, seg.base); 7468 } 7469 #endif 7470 7471 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 7472 { 7473 struct desc_ptr dt; 7474 struct kvm_segment seg; 7475 unsigned long val; 7476 int i; 7477 7478 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 7479 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 7480 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 7481 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 7482 7483 for (i = 0; i < 8; i++) 7484 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 7485 7486 kvm_get_dr(vcpu, 6, &val); 7487 put_smstate(u32, buf, 0x7fcc, (u32)val); 7488 kvm_get_dr(vcpu, 7, &val); 7489 put_smstate(u32, buf, 0x7fc8, (u32)val); 7490 7491 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7492 put_smstate(u32, buf, 0x7fc4, seg.selector); 7493 put_smstate(u32, buf, 0x7f64, seg.base); 7494 put_smstate(u32, buf, 0x7f60, seg.limit); 7495 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 7496 7497 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7498 put_smstate(u32, buf, 0x7fc0, seg.selector); 7499 put_smstate(u32, buf, 0x7f80, seg.base); 7500 put_smstate(u32, buf, 0x7f7c, seg.limit); 7501 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 7502 7503 kvm_x86_ops->get_gdt(vcpu, &dt); 7504 put_smstate(u32, buf, 0x7f74, dt.address); 7505 put_smstate(u32, buf, 0x7f70, dt.size); 7506 7507 kvm_x86_ops->get_idt(vcpu, &dt); 7508 put_smstate(u32, buf, 0x7f58, dt.address); 7509 put_smstate(u32, buf, 0x7f54, dt.size); 7510 7511 for (i = 0; i < 6; i++) 7512 enter_smm_save_seg_32(vcpu, buf, i); 7513 7514 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 7515 7516 /* revision id */ 7517 put_smstate(u32, buf, 0x7efc, 0x00020000); 7518 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 7519 } 7520 7521 #ifdef CONFIG_X86_64 7522 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 7523 { 7524 struct desc_ptr dt; 7525 struct kvm_segment seg; 7526 unsigned long val; 7527 int i; 7528 7529 for (i = 0; i < 16; i++) 7530 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7531 7532 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7533 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7534 7535 kvm_get_dr(vcpu, 6, &val); 7536 put_smstate(u64, buf, 0x7f68, val); 7537 kvm_get_dr(vcpu, 7, &val); 7538 put_smstate(u64, buf, 0x7f60, val); 7539 7540 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7541 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7542 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7543 7544 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7545 7546 /* revision id */ 7547 put_smstate(u32, buf, 0x7efc, 0x00020064); 7548 7549 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7550 7551 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7552 put_smstate(u16, buf, 0x7e90, seg.selector); 7553 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7554 put_smstate(u32, buf, 0x7e94, seg.limit); 7555 put_smstate(u64, buf, 0x7e98, seg.base); 7556 7557 kvm_x86_ops->get_idt(vcpu, &dt); 7558 put_smstate(u32, buf, 0x7e84, dt.size); 7559 put_smstate(u64, buf, 0x7e88, dt.address); 7560 7561 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7562 put_smstate(u16, buf, 0x7e70, seg.selector); 7563 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7564 put_smstate(u32, buf, 0x7e74, seg.limit); 7565 put_smstate(u64, buf, 0x7e78, seg.base); 7566 7567 kvm_x86_ops->get_gdt(vcpu, &dt); 7568 put_smstate(u32, buf, 0x7e64, dt.size); 7569 put_smstate(u64, buf, 0x7e68, dt.address); 7570 7571 for (i = 0; i < 6; i++) 7572 enter_smm_save_seg_64(vcpu, buf, i); 7573 } 7574 #endif 7575 7576 static void enter_smm(struct kvm_vcpu *vcpu) 7577 { 7578 struct kvm_segment cs, ds; 7579 struct desc_ptr dt; 7580 char buf[512]; 7581 u32 cr0; 7582 7583 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7584 memset(buf, 0, 512); 7585 #ifdef CONFIG_X86_64 7586 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7587 enter_smm_save_state_64(vcpu, buf); 7588 else 7589 #endif 7590 enter_smm_save_state_32(vcpu, buf); 7591 7592 /* 7593 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7594 * vCPU state (e.g. leave guest mode) after we've saved the state into 7595 * the SMM state-save area. 7596 */ 7597 kvm_x86_ops->pre_enter_smm(vcpu, buf); 7598 7599 vcpu->arch.hflags |= HF_SMM_MASK; 7600 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7601 7602 if (kvm_x86_ops->get_nmi_mask(vcpu)) 7603 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7604 else 7605 kvm_x86_ops->set_nmi_mask(vcpu, true); 7606 7607 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7608 kvm_rip_write(vcpu, 0x8000); 7609 7610 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7611 kvm_x86_ops->set_cr0(vcpu, cr0); 7612 vcpu->arch.cr0 = cr0; 7613 7614 kvm_x86_ops->set_cr4(vcpu, 0); 7615 7616 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7617 dt.address = dt.size = 0; 7618 kvm_x86_ops->set_idt(vcpu, &dt); 7619 7620 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7621 7622 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7623 cs.base = vcpu->arch.smbase; 7624 7625 ds.selector = 0; 7626 ds.base = 0; 7627 7628 cs.limit = ds.limit = 0xffffffff; 7629 cs.type = ds.type = 0x3; 7630 cs.dpl = ds.dpl = 0; 7631 cs.db = ds.db = 0; 7632 cs.s = ds.s = 1; 7633 cs.l = ds.l = 0; 7634 cs.g = ds.g = 1; 7635 cs.avl = ds.avl = 0; 7636 cs.present = ds.present = 1; 7637 cs.unusable = ds.unusable = 0; 7638 cs.padding = ds.padding = 0; 7639 7640 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7641 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 7642 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 7643 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 7644 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 7645 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 7646 7647 #ifdef CONFIG_X86_64 7648 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7649 kvm_x86_ops->set_efer(vcpu, 0); 7650 #endif 7651 7652 kvm_update_cpuid(vcpu); 7653 kvm_mmu_reset_context(vcpu); 7654 } 7655 7656 static void process_smi(struct kvm_vcpu *vcpu) 7657 { 7658 vcpu->arch.smi_pending = true; 7659 kvm_make_request(KVM_REQ_EVENT, vcpu); 7660 } 7661 7662 void kvm_make_scan_ioapic_request(struct kvm *kvm) 7663 { 7664 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 7665 } 7666 7667 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 7668 { 7669 if (!kvm_apic_present(vcpu)) 7670 return; 7671 7672 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 7673 7674 if (irqchip_split(vcpu->kvm)) 7675 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 7676 else { 7677 if (vcpu->arch.apicv_active) 7678 kvm_x86_ops->sync_pir_to_irr(vcpu); 7679 if (ioapic_in_kernel(vcpu->kvm)) 7680 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 7681 } 7682 7683 if (is_guest_mode(vcpu)) 7684 vcpu->arch.load_eoi_exitmap_pending = true; 7685 else 7686 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 7687 } 7688 7689 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 7690 { 7691 u64 eoi_exit_bitmap[4]; 7692 7693 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7694 return; 7695 7696 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 7697 vcpu_to_synic(vcpu)->vec_bitmap, 256); 7698 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 7699 } 7700 7701 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 7702 unsigned long start, unsigned long end, 7703 bool blockable) 7704 { 7705 unsigned long apic_address; 7706 7707 /* 7708 * The physical address of apic access page is stored in the VMCS. 7709 * Update it when it becomes invalid. 7710 */ 7711 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7712 if (start <= apic_address && apic_address < end) 7713 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 7714 7715 return 0; 7716 } 7717 7718 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 7719 { 7720 struct page *page = NULL; 7721 7722 if (!lapic_in_kernel(vcpu)) 7723 return; 7724 7725 if (!kvm_x86_ops->set_apic_access_page_addr) 7726 return; 7727 7728 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7729 if (is_error_page(page)) 7730 return; 7731 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 7732 7733 /* 7734 * Do not pin apic access page in memory, the MMU notifier 7735 * will call us again if it is migrated or swapped out. 7736 */ 7737 put_page(page); 7738 } 7739 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 7740 7741 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 7742 { 7743 smp_send_reschedule(vcpu->cpu); 7744 } 7745 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 7746 7747 /* 7748 * Returns 1 to let vcpu_run() continue the guest execution loop without 7749 * exiting to the userspace. Otherwise, the value will be returned to the 7750 * userspace. 7751 */ 7752 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 7753 { 7754 int r; 7755 bool req_int_win = 7756 dm_request_for_irq_injection(vcpu) && 7757 kvm_cpu_accept_dm_intr(vcpu); 7758 7759 bool req_immediate_exit = false; 7760 7761 if (kvm_request_pending(vcpu)) { 7762 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) 7763 kvm_x86_ops->get_vmcs12_pages(vcpu); 7764 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 7765 kvm_mmu_unload(vcpu); 7766 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 7767 __kvm_migrate_timers(vcpu); 7768 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 7769 kvm_gen_update_masterclock(vcpu->kvm); 7770 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 7771 kvm_gen_kvmclock_update(vcpu); 7772 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 7773 r = kvm_guest_time_update(vcpu); 7774 if (unlikely(r)) 7775 goto out; 7776 } 7777 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 7778 kvm_mmu_sync_roots(vcpu); 7779 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu)) 7780 kvm_mmu_load_cr3(vcpu); 7781 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 7782 kvm_vcpu_flush_tlb(vcpu, true); 7783 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 7784 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 7785 r = 0; 7786 goto out; 7787 } 7788 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 7789 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 7790 vcpu->mmio_needed = 0; 7791 r = 0; 7792 goto out; 7793 } 7794 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 7795 /* Page is swapped out. Do synthetic halt */ 7796 vcpu->arch.apf.halted = true; 7797 r = 1; 7798 goto out; 7799 } 7800 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 7801 record_steal_time(vcpu); 7802 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 7803 process_smi(vcpu); 7804 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 7805 process_nmi(vcpu); 7806 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 7807 kvm_pmu_handle_event(vcpu); 7808 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 7809 kvm_pmu_deliver_pmi(vcpu); 7810 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 7811 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 7812 if (test_bit(vcpu->arch.pending_ioapic_eoi, 7813 vcpu->arch.ioapic_handled_vectors)) { 7814 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 7815 vcpu->run->eoi.vector = 7816 vcpu->arch.pending_ioapic_eoi; 7817 r = 0; 7818 goto out; 7819 } 7820 } 7821 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 7822 vcpu_scan_ioapic(vcpu); 7823 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 7824 vcpu_load_eoi_exitmap(vcpu); 7825 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 7826 kvm_vcpu_reload_apic_access_page(vcpu); 7827 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 7828 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7829 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 7830 r = 0; 7831 goto out; 7832 } 7833 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 7834 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7835 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 7836 r = 0; 7837 goto out; 7838 } 7839 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 7840 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 7841 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 7842 r = 0; 7843 goto out; 7844 } 7845 7846 /* 7847 * KVM_REQ_HV_STIMER has to be processed after 7848 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 7849 * depend on the guest clock being up-to-date 7850 */ 7851 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 7852 kvm_hv_process_stimers(vcpu); 7853 } 7854 7855 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 7856 ++vcpu->stat.req_event; 7857 kvm_apic_accept_events(vcpu); 7858 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 7859 r = 1; 7860 goto out; 7861 } 7862 7863 if (inject_pending_event(vcpu, req_int_win) != 0) 7864 req_immediate_exit = true; 7865 else { 7866 /* Enable SMI/NMI/IRQ window open exits if needed. 7867 * 7868 * SMIs have three cases: 7869 * 1) They can be nested, and then there is nothing to 7870 * do here because RSM will cause a vmexit anyway. 7871 * 2) There is an ISA-specific reason why SMI cannot be 7872 * injected, and the moment when this changes can be 7873 * intercepted. 7874 * 3) Or the SMI can be pending because 7875 * inject_pending_event has completed the injection 7876 * of an IRQ or NMI from the previous vmexit, and 7877 * then we request an immediate exit to inject the 7878 * SMI. 7879 */ 7880 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 7881 if (!kvm_x86_ops->enable_smi_window(vcpu)) 7882 req_immediate_exit = true; 7883 if (vcpu->arch.nmi_pending) 7884 kvm_x86_ops->enable_nmi_window(vcpu); 7885 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 7886 kvm_x86_ops->enable_irq_window(vcpu); 7887 WARN_ON(vcpu->arch.exception.pending); 7888 } 7889 7890 if (kvm_lapic_enabled(vcpu)) { 7891 update_cr8_intercept(vcpu); 7892 kvm_lapic_sync_to_vapic(vcpu); 7893 } 7894 } 7895 7896 r = kvm_mmu_reload(vcpu); 7897 if (unlikely(r)) { 7898 goto cancel_injection; 7899 } 7900 7901 preempt_disable(); 7902 7903 kvm_x86_ops->prepare_guest_switch(vcpu); 7904 7905 /* 7906 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 7907 * IPI are then delayed after guest entry, which ensures that they 7908 * result in virtual interrupt delivery. 7909 */ 7910 local_irq_disable(); 7911 vcpu->mode = IN_GUEST_MODE; 7912 7913 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7914 7915 /* 7916 * 1) We should set ->mode before checking ->requests. Please see 7917 * the comment in kvm_vcpu_exiting_guest_mode(). 7918 * 7919 * 2) For APICv, we should set ->mode before checking PID.ON. This 7920 * pairs with the memory barrier implicit in pi_test_and_set_on 7921 * (see vmx_deliver_posted_interrupt). 7922 * 7923 * 3) This also orders the write to mode from any reads to the page 7924 * tables done while the VCPU is running. Please see the comment 7925 * in kvm_flush_remote_tlbs. 7926 */ 7927 smp_mb__after_srcu_read_unlock(); 7928 7929 /* 7930 * This handles the case where a posted interrupt was 7931 * notified with kvm_vcpu_kick. 7932 */ 7933 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 7934 kvm_x86_ops->sync_pir_to_irr(vcpu); 7935 7936 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 7937 || need_resched() || signal_pending(current)) { 7938 vcpu->mode = OUTSIDE_GUEST_MODE; 7939 smp_wmb(); 7940 local_irq_enable(); 7941 preempt_enable(); 7942 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7943 r = 1; 7944 goto cancel_injection; 7945 } 7946 7947 if (req_immediate_exit) { 7948 kvm_make_request(KVM_REQ_EVENT, vcpu); 7949 kvm_x86_ops->request_immediate_exit(vcpu); 7950 } 7951 7952 trace_kvm_entry(vcpu->vcpu_id); 7953 if (lapic_in_kernel(vcpu) && 7954 vcpu->arch.apic->lapic_timer.timer_advance_ns) 7955 wait_lapic_expire(vcpu); 7956 guest_enter_irqoff(); 7957 7958 fpregs_assert_state_consistent(); 7959 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 7960 switch_fpu_return(); 7961 7962 if (unlikely(vcpu->arch.switch_db_regs)) { 7963 set_debugreg(0, 7); 7964 set_debugreg(vcpu->arch.eff_db[0], 0); 7965 set_debugreg(vcpu->arch.eff_db[1], 1); 7966 set_debugreg(vcpu->arch.eff_db[2], 2); 7967 set_debugreg(vcpu->arch.eff_db[3], 3); 7968 set_debugreg(vcpu->arch.dr6, 6); 7969 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7970 } 7971 7972 kvm_x86_ops->run(vcpu); 7973 7974 /* 7975 * Do this here before restoring debug registers on the host. And 7976 * since we do this before handling the vmexit, a DR access vmexit 7977 * can (a) read the correct value of the debug registers, (b) set 7978 * KVM_DEBUGREG_WONT_EXIT again. 7979 */ 7980 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7981 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7982 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7983 kvm_update_dr0123(vcpu); 7984 kvm_update_dr6(vcpu); 7985 kvm_update_dr7(vcpu); 7986 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7987 } 7988 7989 /* 7990 * If the guest has used debug registers, at least dr7 7991 * will be disabled while returning to the host. 7992 * If we don't have active breakpoints in the host, we don't 7993 * care about the messed up debug address registers. But if 7994 * we have some of them active, restore the old state. 7995 */ 7996 if (hw_breakpoint_active()) 7997 hw_breakpoint_restore(); 7998 7999 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 8000 8001 vcpu->mode = OUTSIDE_GUEST_MODE; 8002 smp_wmb(); 8003 8004 kvm_before_interrupt(vcpu); 8005 kvm_x86_ops->handle_external_intr(vcpu); 8006 kvm_after_interrupt(vcpu); 8007 8008 ++vcpu->stat.exits; 8009 8010 guest_exit_irqoff(); 8011 8012 local_irq_enable(); 8013 preempt_enable(); 8014 8015 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8016 8017 /* 8018 * Profile KVM exit RIPs: 8019 */ 8020 if (unlikely(prof_on == KVM_PROFILING)) { 8021 unsigned long rip = kvm_rip_read(vcpu); 8022 profile_hit(KVM_PROFILING, (void *)rip); 8023 } 8024 8025 if (unlikely(vcpu->arch.tsc_always_catchup)) 8026 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8027 8028 if (vcpu->arch.apic_attention) 8029 kvm_lapic_sync_from_vapic(vcpu); 8030 8031 vcpu->arch.gpa_available = false; 8032 r = kvm_x86_ops->handle_exit(vcpu); 8033 return r; 8034 8035 cancel_injection: 8036 kvm_x86_ops->cancel_injection(vcpu); 8037 if (unlikely(vcpu->arch.apic_attention)) 8038 kvm_lapic_sync_from_vapic(vcpu); 8039 out: 8040 return r; 8041 } 8042 8043 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 8044 { 8045 if (!kvm_arch_vcpu_runnable(vcpu) && 8046 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 8047 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8048 kvm_vcpu_block(vcpu); 8049 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8050 8051 if (kvm_x86_ops->post_block) 8052 kvm_x86_ops->post_block(vcpu); 8053 8054 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 8055 return 1; 8056 } 8057 8058 kvm_apic_accept_events(vcpu); 8059 switch(vcpu->arch.mp_state) { 8060 case KVM_MP_STATE_HALTED: 8061 vcpu->arch.pv.pv_unhalted = false; 8062 vcpu->arch.mp_state = 8063 KVM_MP_STATE_RUNNABLE; 8064 /* fall through */ 8065 case KVM_MP_STATE_RUNNABLE: 8066 vcpu->arch.apf.halted = false; 8067 break; 8068 case KVM_MP_STATE_INIT_RECEIVED: 8069 break; 8070 default: 8071 return -EINTR; 8072 break; 8073 } 8074 return 1; 8075 } 8076 8077 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 8078 { 8079 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8080 kvm_x86_ops->check_nested_events(vcpu, false); 8081 8082 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 8083 !vcpu->arch.apf.halted); 8084 } 8085 8086 static int vcpu_run(struct kvm_vcpu *vcpu) 8087 { 8088 int r; 8089 struct kvm *kvm = vcpu->kvm; 8090 8091 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8092 vcpu->arch.l1tf_flush_l1d = true; 8093 8094 for (;;) { 8095 if (kvm_vcpu_running(vcpu)) { 8096 r = vcpu_enter_guest(vcpu); 8097 } else { 8098 r = vcpu_block(kvm, vcpu); 8099 } 8100 8101 if (r <= 0) 8102 break; 8103 8104 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 8105 if (kvm_cpu_has_pending_timer(vcpu)) 8106 kvm_inject_pending_timer_irqs(vcpu); 8107 8108 if (dm_request_for_irq_injection(vcpu) && 8109 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 8110 r = 0; 8111 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 8112 ++vcpu->stat.request_irq_exits; 8113 break; 8114 } 8115 8116 kvm_check_async_pf_completion(vcpu); 8117 8118 if (signal_pending(current)) { 8119 r = -EINTR; 8120 vcpu->run->exit_reason = KVM_EXIT_INTR; 8121 ++vcpu->stat.signal_exits; 8122 break; 8123 } 8124 if (need_resched()) { 8125 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8126 cond_resched(); 8127 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8128 } 8129 } 8130 8131 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8132 8133 return r; 8134 } 8135 8136 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 8137 { 8138 int r; 8139 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8140 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 8141 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8142 if (r != EMULATE_DONE) 8143 return 0; 8144 return 1; 8145 } 8146 8147 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 8148 { 8149 BUG_ON(!vcpu->arch.pio.count); 8150 8151 return complete_emulated_io(vcpu); 8152 } 8153 8154 /* 8155 * Implements the following, as a state machine: 8156 * 8157 * read: 8158 * for each fragment 8159 * for each mmio piece in the fragment 8160 * write gpa, len 8161 * exit 8162 * copy data 8163 * execute insn 8164 * 8165 * write: 8166 * for each fragment 8167 * for each mmio piece in the fragment 8168 * write gpa, len 8169 * copy data 8170 * exit 8171 */ 8172 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 8173 { 8174 struct kvm_run *run = vcpu->run; 8175 struct kvm_mmio_fragment *frag; 8176 unsigned len; 8177 8178 BUG_ON(!vcpu->mmio_needed); 8179 8180 /* Complete previous fragment */ 8181 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 8182 len = min(8u, frag->len); 8183 if (!vcpu->mmio_is_write) 8184 memcpy(frag->data, run->mmio.data, len); 8185 8186 if (frag->len <= 8) { 8187 /* Switch to the next fragment. */ 8188 frag++; 8189 vcpu->mmio_cur_fragment++; 8190 } else { 8191 /* Go forward to the next mmio piece. */ 8192 frag->data += len; 8193 frag->gpa += len; 8194 frag->len -= len; 8195 } 8196 8197 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 8198 vcpu->mmio_needed = 0; 8199 8200 /* FIXME: return into emulator if single-stepping. */ 8201 if (vcpu->mmio_is_write) 8202 return 1; 8203 vcpu->mmio_read_completed = 1; 8204 return complete_emulated_io(vcpu); 8205 } 8206 8207 run->exit_reason = KVM_EXIT_MMIO; 8208 run->mmio.phys_addr = frag->gpa; 8209 if (vcpu->mmio_is_write) 8210 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 8211 run->mmio.len = min(8u, frag->len); 8212 run->mmio.is_write = vcpu->mmio_is_write; 8213 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8214 return 0; 8215 } 8216 8217 /* Swap (qemu) user FPU context for the guest FPU context. */ 8218 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8219 { 8220 fpregs_lock(); 8221 8222 copy_fpregs_to_fpstate(¤t->thread.fpu); 8223 /* PKRU is separately restored in kvm_x86_ops->run. */ 8224 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 8225 ~XFEATURE_MASK_PKRU); 8226 8227 fpregs_mark_activate(); 8228 fpregs_unlock(); 8229 8230 trace_kvm_fpu(1); 8231 } 8232 8233 /* When vcpu_run ends, restore user space FPU context. */ 8234 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8235 { 8236 fpregs_lock(); 8237 8238 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu); 8239 copy_kernel_to_fpregs(¤t->thread.fpu.state); 8240 8241 fpregs_mark_activate(); 8242 fpregs_unlock(); 8243 8244 ++vcpu->stat.fpu_reload; 8245 trace_kvm_fpu(0); 8246 } 8247 8248 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 8249 { 8250 int r; 8251 8252 vcpu_load(vcpu); 8253 kvm_sigset_activate(vcpu); 8254 kvm_load_guest_fpu(vcpu); 8255 8256 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 8257 if (kvm_run->immediate_exit) { 8258 r = -EINTR; 8259 goto out; 8260 } 8261 kvm_vcpu_block(vcpu); 8262 kvm_apic_accept_events(vcpu); 8263 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 8264 r = -EAGAIN; 8265 if (signal_pending(current)) { 8266 r = -EINTR; 8267 vcpu->run->exit_reason = KVM_EXIT_INTR; 8268 ++vcpu->stat.signal_exits; 8269 } 8270 goto out; 8271 } 8272 8273 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 8274 r = -EINVAL; 8275 goto out; 8276 } 8277 8278 if (vcpu->run->kvm_dirty_regs) { 8279 r = sync_regs(vcpu); 8280 if (r != 0) 8281 goto out; 8282 } 8283 8284 /* re-sync apic's tpr */ 8285 if (!lapic_in_kernel(vcpu)) { 8286 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 8287 r = -EINVAL; 8288 goto out; 8289 } 8290 } 8291 8292 if (unlikely(vcpu->arch.complete_userspace_io)) { 8293 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 8294 vcpu->arch.complete_userspace_io = NULL; 8295 r = cui(vcpu); 8296 if (r <= 0) 8297 goto out; 8298 } else 8299 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 8300 8301 if (kvm_run->immediate_exit) 8302 r = -EINTR; 8303 else 8304 r = vcpu_run(vcpu); 8305 8306 out: 8307 kvm_put_guest_fpu(vcpu); 8308 if (vcpu->run->kvm_valid_regs) 8309 store_regs(vcpu); 8310 post_kvm_run_save(vcpu); 8311 kvm_sigset_deactivate(vcpu); 8312 8313 vcpu_put(vcpu); 8314 return r; 8315 } 8316 8317 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8318 { 8319 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 8320 /* 8321 * We are here if userspace calls get_regs() in the middle of 8322 * instruction emulation. Registers state needs to be copied 8323 * back from emulation context to vcpu. Userspace shouldn't do 8324 * that usually, but some bad designed PV devices (vmware 8325 * backdoor interface) need this to work 8326 */ 8327 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 8328 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8329 } 8330 regs->rax = kvm_rax_read(vcpu); 8331 regs->rbx = kvm_rbx_read(vcpu); 8332 regs->rcx = kvm_rcx_read(vcpu); 8333 regs->rdx = kvm_rdx_read(vcpu); 8334 regs->rsi = kvm_rsi_read(vcpu); 8335 regs->rdi = kvm_rdi_read(vcpu); 8336 regs->rsp = kvm_rsp_read(vcpu); 8337 regs->rbp = kvm_rbp_read(vcpu); 8338 #ifdef CONFIG_X86_64 8339 regs->r8 = kvm_r8_read(vcpu); 8340 regs->r9 = kvm_r9_read(vcpu); 8341 regs->r10 = kvm_r10_read(vcpu); 8342 regs->r11 = kvm_r11_read(vcpu); 8343 regs->r12 = kvm_r12_read(vcpu); 8344 regs->r13 = kvm_r13_read(vcpu); 8345 regs->r14 = kvm_r14_read(vcpu); 8346 regs->r15 = kvm_r15_read(vcpu); 8347 #endif 8348 8349 regs->rip = kvm_rip_read(vcpu); 8350 regs->rflags = kvm_get_rflags(vcpu); 8351 } 8352 8353 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8354 { 8355 vcpu_load(vcpu); 8356 __get_regs(vcpu, regs); 8357 vcpu_put(vcpu); 8358 return 0; 8359 } 8360 8361 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8362 { 8363 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 8364 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8365 8366 kvm_rax_write(vcpu, regs->rax); 8367 kvm_rbx_write(vcpu, regs->rbx); 8368 kvm_rcx_write(vcpu, regs->rcx); 8369 kvm_rdx_write(vcpu, regs->rdx); 8370 kvm_rsi_write(vcpu, regs->rsi); 8371 kvm_rdi_write(vcpu, regs->rdi); 8372 kvm_rsp_write(vcpu, regs->rsp); 8373 kvm_rbp_write(vcpu, regs->rbp); 8374 #ifdef CONFIG_X86_64 8375 kvm_r8_write(vcpu, regs->r8); 8376 kvm_r9_write(vcpu, regs->r9); 8377 kvm_r10_write(vcpu, regs->r10); 8378 kvm_r11_write(vcpu, regs->r11); 8379 kvm_r12_write(vcpu, regs->r12); 8380 kvm_r13_write(vcpu, regs->r13); 8381 kvm_r14_write(vcpu, regs->r14); 8382 kvm_r15_write(vcpu, regs->r15); 8383 #endif 8384 8385 kvm_rip_write(vcpu, regs->rip); 8386 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 8387 8388 vcpu->arch.exception.pending = false; 8389 8390 kvm_make_request(KVM_REQ_EVENT, vcpu); 8391 } 8392 8393 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8394 { 8395 vcpu_load(vcpu); 8396 __set_regs(vcpu, regs); 8397 vcpu_put(vcpu); 8398 return 0; 8399 } 8400 8401 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 8402 { 8403 struct kvm_segment cs; 8404 8405 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8406 *db = cs.db; 8407 *l = cs.l; 8408 } 8409 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 8410 8411 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8412 { 8413 struct desc_ptr dt; 8414 8415 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8416 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8417 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8418 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8419 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8420 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8421 8422 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8423 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8424 8425 kvm_x86_ops->get_idt(vcpu, &dt); 8426 sregs->idt.limit = dt.size; 8427 sregs->idt.base = dt.address; 8428 kvm_x86_ops->get_gdt(vcpu, &dt); 8429 sregs->gdt.limit = dt.size; 8430 sregs->gdt.base = dt.address; 8431 8432 sregs->cr0 = kvm_read_cr0(vcpu); 8433 sregs->cr2 = vcpu->arch.cr2; 8434 sregs->cr3 = kvm_read_cr3(vcpu); 8435 sregs->cr4 = kvm_read_cr4(vcpu); 8436 sregs->cr8 = kvm_get_cr8(vcpu); 8437 sregs->efer = vcpu->arch.efer; 8438 sregs->apic_base = kvm_get_apic_base(vcpu); 8439 8440 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 8441 8442 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 8443 set_bit(vcpu->arch.interrupt.nr, 8444 (unsigned long *)sregs->interrupt_bitmap); 8445 } 8446 8447 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 8448 struct kvm_sregs *sregs) 8449 { 8450 vcpu_load(vcpu); 8451 __get_sregs(vcpu, sregs); 8452 vcpu_put(vcpu); 8453 return 0; 8454 } 8455 8456 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 8457 struct kvm_mp_state *mp_state) 8458 { 8459 vcpu_load(vcpu); 8460 8461 kvm_apic_accept_events(vcpu); 8462 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 8463 vcpu->arch.pv.pv_unhalted) 8464 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 8465 else 8466 mp_state->mp_state = vcpu->arch.mp_state; 8467 8468 vcpu_put(vcpu); 8469 return 0; 8470 } 8471 8472 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 8473 struct kvm_mp_state *mp_state) 8474 { 8475 int ret = -EINVAL; 8476 8477 vcpu_load(vcpu); 8478 8479 if (!lapic_in_kernel(vcpu) && 8480 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 8481 goto out; 8482 8483 /* INITs are latched while in SMM */ 8484 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 8485 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 8486 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 8487 goto out; 8488 8489 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 8490 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 8491 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 8492 } else 8493 vcpu->arch.mp_state = mp_state->mp_state; 8494 kvm_make_request(KVM_REQ_EVENT, vcpu); 8495 8496 ret = 0; 8497 out: 8498 vcpu_put(vcpu); 8499 return ret; 8500 } 8501 8502 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 8503 int reason, bool has_error_code, u32 error_code) 8504 { 8505 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 8506 int ret; 8507 8508 init_emulate_ctxt(vcpu); 8509 8510 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 8511 has_error_code, error_code); 8512 8513 if (ret) 8514 return EMULATE_FAIL; 8515 8516 kvm_rip_write(vcpu, ctxt->eip); 8517 kvm_set_rflags(vcpu, ctxt->eflags); 8518 kvm_make_request(KVM_REQ_EVENT, vcpu); 8519 return EMULATE_DONE; 8520 } 8521 EXPORT_SYMBOL_GPL(kvm_task_switch); 8522 8523 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8524 { 8525 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 8526 (sregs->cr4 & X86_CR4_OSXSAVE)) 8527 return -EINVAL; 8528 8529 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 8530 /* 8531 * When EFER.LME and CR0.PG are set, the processor is in 8532 * 64-bit mode (though maybe in a 32-bit code segment). 8533 * CR4.PAE and EFER.LMA must be set. 8534 */ 8535 if (!(sregs->cr4 & X86_CR4_PAE) 8536 || !(sregs->efer & EFER_LMA)) 8537 return -EINVAL; 8538 } else { 8539 /* 8540 * Not in 64-bit mode: EFER.LMA is clear and the code 8541 * segment cannot be 64-bit. 8542 */ 8543 if (sregs->efer & EFER_LMA || sregs->cs.l) 8544 return -EINVAL; 8545 } 8546 8547 return 0; 8548 } 8549 8550 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8551 { 8552 struct msr_data apic_base_msr; 8553 int mmu_reset_needed = 0; 8554 int cpuid_update_needed = 0; 8555 int pending_vec, max_bits, idx; 8556 struct desc_ptr dt; 8557 int ret = -EINVAL; 8558 8559 if (kvm_valid_sregs(vcpu, sregs)) 8560 goto out; 8561 8562 apic_base_msr.data = sregs->apic_base; 8563 apic_base_msr.host_initiated = true; 8564 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 8565 goto out; 8566 8567 dt.size = sregs->idt.limit; 8568 dt.address = sregs->idt.base; 8569 kvm_x86_ops->set_idt(vcpu, &dt); 8570 dt.size = sregs->gdt.limit; 8571 dt.address = sregs->gdt.base; 8572 kvm_x86_ops->set_gdt(vcpu, &dt); 8573 8574 vcpu->arch.cr2 = sregs->cr2; 8575 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 8576 vcpu->arch.cr3 = sregs->cr3; 8577 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 8578 8579 kvm_set_cr8(vcpu, sregs->cr8); 8580 8581 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 8582 kvm_x86_ops->set_efer(vcpu, sregs->efer); 8583 8584 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 8585 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 8586 vcpu->arch.cr0 = sregs->cr0; 8587 8588 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 8589 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & 8590 (X86_CR4_OSXSAVE | X86_CR4_PKE)); 8591 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 8592 if (cpuid_update_needed) 8593 kvm_update_cpuid(vcpu); 8594 8595 idx = srcu_read_lock(&vcpu->kvm->srcu); 8596 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) { 8597 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 8598 mmu_reset_needed = 1; 8599 } 8600 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8601 8602 if (mmu_reset_needed) 8603 kvm_mmu_reset_context(vcpu); 8604 8605 max_bits = KVM_NR_INTERRUPTS; 8606 pending_vec = find_first_bit( 8607 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 8608 if (pending_vec < max_bits) { 8609 kvm_queue_interrupt(vcpu, pending_vec, false); 8610 pr_debug("Set back pending irq %d\n", pending_vec); 8611 } 8612 8613 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8614 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8615 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8616 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8617 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8618 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8619 8620 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8621 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8622 8623 update_cr8_intercept(vcpu); 8624 8625 /* Older userspace won't unhalt the vcpu on reset. */ 8626 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 8627 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 8628 !is_protmode(vcpu)) 8629 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8630 8631 kvm_make_request(KVM_REQ_EVENT, vcpu); 8632 8633 ret = 0; 8634 out: 8635 return ret; 8636 } 8637 8638 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 8639 struct kvm_sregs *sregs) 8640 { 8641 int ret; 8642 8643 vcpu_load(vcpu); 8644 ret = __set_sregs(vcpu, sregs); 8645 vcpu_put(vcpu); 8646 return ret; 8647 } 8648 8649 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 8650 struct kvm_guest_debug *dbg) 8651 { 8652 unsigned long rflags; 8653 int i, r; 8654 8655 vcpu_load(vcpu); 8656 8657 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 8658 r = -EBUSY; 8659 if (vcpu->arch.exception.pending) 8660 goto out; 8661 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 8662 kvm_queue_exception(vcpu, DB_VECTOR); 8663 else 8664 kvm_queue_exception(vcpu, BP_VECTOR); 8665 } 8666 8667 /* 8668 * Read rflags as long as potentially injected trace flags are still 8669 * filtered out. 8670 */ 8671 rflags = kvm_get_rflags(vcpu); 8672 8673 vcpu->guest_debug = dbg->control; 8674 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 8675 vcpu->guest_debug = 0; 8676 8677 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 8678 for (i = 0; i < KVM_NR_DB_REGS; ++i) 8679 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 8680 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 8681 } else { 8682 for (i = 0; i < KVM_NR_DB_REGS; i++) 8683 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 8684 } 8685 kvm_update_dr7(vcpu); 8686 8687 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8688 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 8689 get_segment_base(vcpu, VCPU_SREG_CS); 8690 8691 /* 8692 * Trigger an rflags update that will inject or remove the trace 8693 * flags. 8694 */ 8695 kvm_set_rflags(vcpu, rflags); 8696 8697 kvm_x86_ops->update_bp_intercept(vcpu); 8698 8699 r = 0; 8700 8701 out: 8702 vcpu_put(vcpu); 8703 return r; 8704 } 8705 8706 /* 8707 * Translate a guest virtual address to a guest physical address. 8708 */ 8709 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 8710 struct kvm_translation *tr) 8711 { 8712 unsigned long vaddr = tr->linear_address; 8713 gpa_t gpa; 8714 int idx; 8715 8716 vcpu_load(vcpu); 8717 8718 idx = srcu_read_lock(&vcpu->kvm->srcu); 8719 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 8720 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8721 tr->physical_address = gpa; 8722 tr->valid = gpa != UNMAPPED_GVA; 8723 tr->writeable = 1; 8724 tr->usermode = 0; 8725 8726 vcpu_put(vcpu); 8727 return 0; 8728 } 8729 8730 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8731 { 8732 struct fxregs_state *fxsave; 8733 8734 vcpu_load(vcpu); 8735 8736 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 8737 memcpy(fpu->fpr, fxsave->st_space, 128); 8738 fpu->fcw = fxsave->cwd; 8739 fpu->fsw = fxsave->swd; 8740 fpu->ftwx = fxsave->twd; 8741 fpu->last_opcode = fxsave->fop; 8742 fpu->last_ip = fxsave->rip; 8743 fpu->last_dp = fxsave->rdp; 8744 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 8745 8746 vcpu_put(vcpu); 8747 return 0; 8748 } 8749 8750 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8751 { 8752 struct fxregs_state *fxsave; 8753 8754 vcpu_load(vcpu); 8755 8756 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 8757 8758 memcpy(fxsave->st_space, fpu->fpr, 128); 8759 fxsave->cwd = fpu->fcw; 8760 fxsave->swd = fpu->fsw; 8761 fxsave->twd = fpu->ftwx; 8762 fxsave->fop = fpu->last_opcode; 8763 fxsave->rip = fpu->last_ip; 8764 fxsave->rdp = fpu->last_dp; 8765 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 8766 8767 vcpu_put(vcpu); 8768 return 0; 8769 } 8770 8771 static void store_regs(struct kvm_vcpu *vcpu) 8772 { 8773 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 8774 8775 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 8776 __get_regs(vcpu, &vcpu->run->s.regs.regs); 8777 8778 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 8779 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 8780 8781 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 8782 kvm_vcpu_ioctl_x86_get_vcpu_events( 8783 vcpu, &vcpu->run->s.regs.events); 8784 } 8785 8786 static int sync_regs(struct kvm_vcpu *vcpu) 8787 { 8788 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 8789 return -EINVAL; 8790 8791 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 8792 __set_regs(vcpu, &vcpu->run->s.regs.regs); 8793 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 8794 } 8795 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 8796 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 8797 return -EINVAL; 8798 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 8799 } 8800 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 8801 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 8802 vcpu, &vcpu->run->s.regs.events)) 8803 return -EINVAL; 8804 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 8805 } 8806 8807 return 0; 8808 } 8809 8810 static void fx_init(struct kvm_vcpu *vcpu) 8811 { 8812 fpstate_init(&vcpu->arch.guest_fpu->state); 8813 if (boot_cpu_has(X86_FEATURE_XSAVES)) 8814 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 8815 host_xcr0 | XSTATE_COMPACTION_ENABLED; 8816 8817 /* 8818 * Ensure guest xcr0 is valid for loading 8819 */ 8820 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8821 8822 vcpu->arch.cr0 |= X86_CR0_ET; 8823 } 8824 8825 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 8826 { 8827 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 8828 8829 kvmclock_reset(vcpu); 8830 8831 kvm_x86_ops->vcpu_free(vcpu); 8832 free_cpumask_var(wbinvd_dirty_mask); 8833 } 8834 8835 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 8836 unsigned int id) 8837 { 8838 struct kvm_vcpu *vcpu; 8839 8840 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 8841 printk_once(KERN_WARNING 8842 "kvm: SMP vm created on host with unstable TSC; " 8843 "guest TSC will not be reliable\n"); 8844 8845 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 8846 8847 return vcpu; 8848 } 8849 8850 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 8851 { 8852 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 8853 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 8854 kvm_vcpu_mtrr_init(vcpu); 8855 vcpu_load(vcpu); 8856 kvm_vcpu_reset(vcpu, false); 8857 kvm_init_mmu(vcpu, false); 8858 vcpu_put(vcpu); 8859 return 0; 8860 } 8861 8862 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 8863 { 8864 struct msr_data msr; 8865 struct kvm *kvm = vcpu->kvm; 8866 8867 kvm_hv_vcpu_postcreate(vcpu); 8868 8869 if (mutex_lock_killable(&vcpu->mutex)) 8870 return; 8871 vcpu_load(vcpu); 8872 msr.data = 0x0; 8873 msr.index = MSR_IA32_TSC; 8874 msr.host_initiated = true; 8875 kvm_write_tsc(vcpu, &msr); 8876 vcpu_put(vcpu); 8877 mutex_unlock(&vcpu->mutex); 8878 8879 if (!kvmclock_periodic_sync) 8880 return; 8881 8882 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 8883 KVMCLOCK_SYNC_PERIOD); 8884 } 8885 8886 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 8887 { 8888 vcpu->arch.apf.msr_val = 0; 8889 8890 vcpu_load(vcpu); 8891 kvm_mmu_unload(vcpu); 8892 vcpu_put(vcpu); 8893 8894 kvm_x86_ops->vcpu_free(vcpu); 8895 } 8896 8897 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 8898 { 8899 kvm_lapic_reset(vcpu, init_event); 8900 8901 vcpu->arch.hflags = 0; 8902 8903 vcpu->arch.smi_pending = 0; 8904 vcpu->arch.smi_count = 0; 8905 atomic_set(&vcpu->arch.nmi_queued, 0); 8906 vcpu->arch.nmi_pending = 0; 8907 vcpu->arch.nmi_injected = false; 8908 kvm_clear_interrupt_queue(vcpu); 8909 kvm_clear_exception_queue(vcpu); 8910 vcpu->arch.exception.pending = false; 8911 8912 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 8913 kvm_update_dr0123(vcpu); 8914 vcpu->arch.dr6 = DR6_INIT; 8915 kvm_update_dr6(vcpu); 8916 vcpu->arch.dr7 = DR7_FIXED_1; 8917 kvm_update_dr7(vcpu); 8918 8919 vcpu->arch.cr2 = 0; 8920 8921 kvm_make_request(KVM_REQ_EVENT, vcpu); 8922 vcpu->arch.apf.msr_val = 0; 8923 vcpu->arch.st.msr_val = 0; 8924 8925 kvmclock_reset(vcpu); 8926 8927 kvm_clear_async_pf_completion_queue(vcpu); 8928 kvm_async_pf_hash_reset(vcpu); 8929 vcpu->arch.apf.halted = false; 8930 8931 if (kvm_mpx_supported()) { 8932 void *mpx_state_buffer; 8933 8934 /* 8935 * To avoid have the INIT path from kvm_apic_has_events() that be 8936 * called with loaded FPU and does not let userspace fix the state. 8937 */ 8938 if (init_event) 8939 kvm_put_guest_fpu(vcpu); 8940 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 8941 XFEATURE_BNDREGS); 8942 if (mpx_state_buffer) 8943 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 8944 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 8945 XFEATURE_BNDCSR); 8946 if (mpx_state_buffer) 8947 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 8948 if (init_event) 8949 kvm_load_guest_fpu(vcpu); 8950 } 8951 8952 if (!init_event) { 8953 kvm_pmu_reset(vcpu); 8954 vcpu->arch.smbase = 0x30000; 8955 8956 vcpu->arch.msr_misc_features_enables = 0; 8957 8958 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8959 } 8960 8961 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 8962 vcpu->arch.regs_avail = ~0; 8963 vcpu->arch.regs_dirty = ~0; 8964 8965 vcpu->arch.ia32_xss = 0; 8966 8967 kvm_x86_ops->vcpu_reset(vcpu, init_event); 8968 } 8969 8970 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 8971 { 8972 struct kvm_segment cs; 8973 8974 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8975 cs.selector = vector << 8; 8976 cs.base = vector << 12; 8977 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8978 kvm_rip_write(vcpu, 0); 8979 } 8980 8981 int kvm_arch_hardware_enable(void) 8982 { 8983 struct kvm *kvm; 8984 struct kvm_vcpu *vcpu; 8985 int i; 8986 int ret; 8987 u64 local_tsc; 8988 u64 max_tsc = 0; 8989 bool stable, backwards_tsc = false; 8990 8991 kvm_shared_msr_cpu_online(); 8992 ret = kvm_x86_ops->hardware_enable(); 8993 if (ret != 0) 8994 return ret; 8995 8996 local_tsc = rdtsc(); 8997 stable = !kvm_check_tsc_unstable(); 8998 list_for_each_entry(kvm, &vm_list, vm_list) { 8999 kvm_for_each_vcpu(i, vcpu, kvm) { 9000 if (!stable && vcpu->cpu == smp_processor_id()) 9001 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9002 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 9003 backwards_tsc = true; 9004 if (vcpu->arch.last_host_tsc > max_tsc) 9005 max_tsc = vcpu->arch.last_host_tsc; 9006 } 9007 } 9008 } 9009 9010 /* 9011 * Sometimes, even reliable TSCs go backwards. This happens on 9012 * platforms that reset TSC during suspend or hibernate actions, but 9013 * maintain synchronization. We must compensate. Fortunately, we can 9014 * detect that condition here, which happens early in CPU bringup, 9015 * before any KVM threads can be running. Unfortunately, we can't 9016 * bring the TSCs fully up to date with real time, as we aren't yet far 9017 * enough into CPU bringup that we know how much real time has actually 9018 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 9019 * variables that haven't been updated yet. 9020 * 9021 * So we simply find the maximum observed TSC above, then record the 9022 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 9023 * the adjustment will be applied. Note that we accumulate 9024 * adjustments, in case multiple suspend cycles happen before some VCPU 9025 * gets a chance to run again. In the event that no KVM threads get a 9026 * chance to run, we will miss the entire elapsed period, as we'll have 9027 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 9028 * loose cycle time. This isn't too big a deal, since the loss will be 9029 * uniform across all VCPUs (not to mention the scenario is extremely 9030 * unlikely). It is possible that a second hibernate recovery happens 9031 * much faster than a first, causing the observed TSC here to be 9032 * smaller; this would require additional padding adjustment, which is 9033 * why we set last_host_tsc to the local tsc observed here. 9034 * 9035 * N.B. - this code below runs only on platforms with reliable TSC, 9036 * as that is the only way backwards_tsc is set above. Also note 9037 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 9038 * have the same delta_cyc adjustment applied if backwards_tsc 9039 * is detected. Note further, this adjustment is only done once, 9040 * as we reset last_host_tsc on all VCPUs to stop this from being 9041 * called multiple times (one for each physical CPU bringup). 9042 * 9043 * Platforms with unreliable TSCs don't have to deal with this, they 9044 * will be compensated by the logic in vcpu_load, which sets the TSC to 9045 * catchup mode. This will catchup all VCPUs to real time, but cannot 9046 * guarantee that they stay in perfect synchronization. 9047 */ 9048 if (backwards_tsc) { 9049 u64 delta_cyc = max_tsc - local_tsc; 9050 list_for_each_entry(kvm, &vm_list, vm_list) { 9051 kvm->arch.backwards_tsc_observed = true; 9052 kvm_for_each_vcpu(i, vcpu, kvm) { 9053 vcpu->arch.tsc_offset_adjustment += delta_cyc; 9054 vcpu->arch.last_host_tsc = local_tsc; 9055 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 9056 } 9057 9058 /* 9059 * We have to disable TSC offset matching.. if you were 9060 * booting a VM while issuing an S4 host suspend.... 9061 * you may have some problem. Solving this issue is 9062 * left as an exercise to the reader. 9063 */ 9064 kvm->arch.last_tsc_nsec = 0; 9065 kvm->arch.last_tsc_write = 0; 9066 } 9067 9068 } 9069 return 0; 9070 } 9071 9072 void kvm_arch_hardware_disable(void) 9073 { 9074 kvm_x86_ops->hardware_disable(); 9075 drop_user_return_notifiers(); 9076 } 9077 9078 int kvm_arch_hardware_setup(void) 9079 { 9080 int r; 9081 9082 r = kvm_x86_ops->hardware_setup(); 9083 if (r != 0) 9084 return r; 9085 9086 if (kvm_has_tsc_control) { 9087 /* 9088 * Make sure the user can only configure tsc_khz values that 9089 * fit into a signed integer. 9090 * A min value is not calculated because it will always 9091 * be 1 on all machines. 9092 */ 9093 u64 max = min(0x7fffffffULL, 9094 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 9095 kvm_max_guest_tsc_khz = max; 9096 9097 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 9098 } 9099 9100 kvm_init_msr_list(); 9101 return 0; 9102 } 9103 9104 void kvm_arch_hardware_unsetup(void) 9105 { 9106 kvm_x86_ops->hardware_unsetup(); 9107 } 9108 9109 void kvm_arch_check_processor_compat(void *rtn) 9110 { 9111 kvm_x86_ops->check_processor_compatibility(rtn); 9112 } 9113 9114 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 9115 { 9116 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 9117 } 9118 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 9119 9120 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 9121 { 9122 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 9123 } 9124 9125 struct static_key kvm_no_apic_vcpu __read_mostly; 9126 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 9127 9128 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 9129 { 9130 struct page *page; 9131 int r; 9132 9133 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 9134 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 9135 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9136 else 9137 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 9138 9139 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 9140 if (!page) { 9141 r = -ENOMEM; 9142 goto fail; 9143 } 9144 vcpu->arch.pio_data = page_address(page); 9145 9146 kvm_set_tsc_khz(vcpu, max_tsc_khz); 9147 9148 r = kvm_mmu_create(vcpu); 9149 if (r < 0) 9150 goto fail_free_pio_data; 9151 9152 if (irqchip_in_kernel(vcpu->kvm)) { 9153 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 9154 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 9155 if (r < 0) 9156 goto fail_mmu_destroy; 9157 } else 9158 static_key_slow_inc(&kvm_no_apic_vcpu); 9159 9160 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 9161 GFP_KERNEL_ACCOUNT); 9162 if (!vcpu->arch.mce_banks) { 9163 r = -ENOMEM; 9164 goto fail_free_lapic; 9165 } 9166 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 9167 9168 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 9169 GFP_KERNEL_ACCOUNT)) { 9170 r = -ENOMEM; 9171 goto fail_free_mce_banks; 9172 } 9173 9174 fx_init(vcpu); 9175 9176 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 9177 9178 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 9179 9180 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 9181 9182 kvm_async_pf_hash_reset(vcpu); 9183 kvm_pmu_init(vcpu); 9184 9185 vcpu->arch.pending_external_vector = -1; 9186 vcpu->arch.preempted_in_kernel = false; 9187 9188 kvm_hv_vcpu_init(vcpu); 9189 9190 return 0; 9191 9192 fail_free_mce_banks: 9193 kfree(vcpu->arch.mce_banks); 9194 fail_free_lapic: 9195 kvm_free_lapic(vcpu); 9196 fail_mmu_destroy: 9197 kvm_mmu_destroy(vcpu); 9198 fail_free_pio_data: 9199 free_page((unsigned long)vcpu->arch.pio_data); 9200 fail: 9201 return r; 9202 } 9203 9204 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 9205 { 9206 int idx; 9207 9208 kvm_hv_vcpu_uninit(vcpu); 9209 kvm_pmu_destroy(vcpu); 9210 kfree(vcpu->arch.mce_banks); 9211 kvm_free_lapic(vcpu); 9212 idx = srcu_read_lock(&vcpu->kvm->srcu); 9213 kvm_mmu_destroy(vcpu); 9214 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9215 free_page((unsigned long)vcpu->arch.pio_data); 9216 if (!lapic_in_kernel(vcpu)) 9217 static_key_slow_dec(&kvm_no_apic_vcpu); 9218 } 9219 9220 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 9221 { 9222 vcpu->arch.l1tf_flush_l1d = true; 9223 kvm_x86_ops->sched_in(vcpu, cpu); 9224 } 9225 9226 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 9227 { 9228 if (type) 9229 return -EINVAL; 9230 9231 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 9232 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 9233 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 9234 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 9235 9236 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 9237 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 9238 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 9239 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 9240 &kvm->arch.irq_sources_bitmap); 9241 9242 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 9243 mutex_init(&kvm->arch.apic_map_lock); 9244 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 9245 9246 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 9247 pvclock_update_vm_gtod_copy(kvm); 9248 9249 kvm->arch.guest_can_read_msr_platform_info = true; 9250 9251 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 9252 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 9253 9254 kvm_hv_init_vm(kvm); 9255 kvm_page_track_init(kvm); 9256 kvm_mmu_init_vm(kvm); 9257 9258 if (kvm_x86_ops->vm_init) 9259 return kvm_x86_ops->vm_init(kvm); 9260 9261 return 0; 9262 } 9263 9264 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 9265 { 9266 vcpu_load(vcpu); 9267 kvm_mmu_unload(vcpu); 9268 vcpu_put(vcpu); 9269 } 9270 9271 static void kvm_free_vcpus(struct kvm *kvm) 9272 { 9273 unsigned int i; 9274 struct kvm_vcpu *vcpu; 9275 9276 /* 9277 * Unpin any mmu pages first. 9278 */ 9279 kvm_for_each_vcpu(i, vcpu, kvm) { 9280 kvm_clear_async_pf_completion_queue(vcpu); 9281 kvm_unload_vcpu_mmu(vcpu); 9282 } 9283 kvm_for_each_vcpu(i, vcpu, kvm) 9284 kvm_arch_vcpu_free(vcpu); 9285 9286 mutex_lock(&kvm->lock); 9287 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 9288 kvm->vcpus[i] = NULL; 9289 9290 atomic_set(&kvm->online_vcpus, 0); 9291 mutex_unlock(&kvm->lock); 9292 } 9293 9294 void kvm_arch_sync_events(struct kvm *kvm) 9295 { 9296 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 9297 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 9298 kvm_free_pit(kvm); 9299 } 9300 9301 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9302 { 9303 int i, r; 9304 unsigned long hva; 9305 struct kvm_memslots *slots = kvm_memslots(kvm); 9306 struct kvm_memory_slot *slot, old; 9307 9308 /* Called with kvm->slots_lock held. */ 9309 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 9310 return -EINVAL; 9311 9312 slot = id_to_memslot(slots, id); 9313 if (size) { 9314 if (slot->npages) 9315 return -EEXIST; 9316 9317 /* 9318 * MAP_SHARED to prevent internal slot pages from being moved 9319 * by fork()/COW. 9320 */ 9321 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 9322 MAP_SHARED | MAP_ANONYMOUS, 0); 9323 if (IS_ERR((void *)hva)) 9324 return PTR_ERR((void *)hva); 9325 } else { 9326 if (!slot->npages) 9327 return 0; 9328 9329 hva = 0; 9330 } 9331 9332 old = *slot; 9333 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 9334 struct kvm_userspace_memory_region m; 9335 9336 m.slot = id | (i << 16); 9337 m.flags = 0; 9338 m.guest_phys_addr = gpa; 9339 m.userspace_addr = hva; 9340 m.memory_size = size; 9341 r = __kvm_set_memory_region(kvm, &m); 9342 if (r < 0) 9343 return r; 9344 } 9345 9346 if (!size) 9347 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 9348 9349 return 0; 9350 } 9351 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 9352 9353 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9354 { 9355 int r; 9356 9357 mutex_lock(&kvm->slots_lock); 9358 r = __x86_set_memory_region(kvm, id, gpa, size); 9359 mutex_unlock(&kvm->slots_lock); 9360 9361 return r; 9362 } 9363 EXPORT_SYMBOL_GPL(x86_set_memory_region); 9364 9365 void kvm_arch_destroy_vm(struct kvm *kvm) 9366 { 9367 if (current->mm == kvm->mm) { 9368 /* 9369 * Free memory regions allocated on behalf of userspace, 9370 * unless the the memory map has changed due to process exit 9371 * or fd copying. 9372 */ 9373 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 9374 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 9375 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 9376 } 9377 if (kvm_x86_ops->vm_destroy) 9378 kvm_x86_ops->vm_destroy(kvm); 9379 kvm_pic_destroy(kvm); 9380 kvm_ioapic_destroy(kvm); 9381 kvm_free_vcpus(kvm); 9382 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 9383 kvm_mmu_uninit_vm(kvm); 9384 kvm_page_track_cleanup(kvm); 9385 kvm_hv_destroy_vm(kvm); 9386 } 9387 9388 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 9389 struct kvm_memory_slot *dont) 9390 { 9391 int i; 9392 9393 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9394 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 9395 kvfree(free->arch.rmap[i]); 9396 free->arch.rmap[i] = NULL; 9397 } 9398 if (i == 0) 9399 continue; 9400 9401 if (!dont || free->arch.lpage_info[i - 1] != 9402 dont->arch.lpage_info[i - 1]) { 9403 kvfree(free->arch.lpage_info[i - 1]); 9404 free->arch.lpage_info[i - 1] = NULL; 9405 } 9406 } 9407 9408 kvm_page_track_free_memslot(free, dont); 9409 } 9410 9411 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 9412 unsigned long npages) 9413 { 9414 int i; 9415 9416 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9417 struct kvm_lpage_info *linfo; 9418 unsigned long ugfn; 9419 int lpages; 9420 int level = i + 1; 9421 9422 lpages = gfn_to_index(slot->base_gfn + npages - 1, 9423 slot->base_gfn, level) + 1; 9424 9425 slot->arch.rmap[i] = 9426 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 9427 GFP_KERNEL_ACCOUNT); 9428 if (!slot->arch.rmap[i]) 9429 goto out_free; 9430 if (i == 0) 9431 continue; 9432 9433 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 9434 if (!linfo) 9435 goto out_free; 9436 9437 slot->arch.lpage_info[i - 1] = linfo; 9438 9439 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 9440 linfo[0].disallow_lpage = 1; 9441 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 9442 linfo[lpages - 1].disallow_lpage = 1; 9443 ugfn = slot->userspace_addr >> PAGE_SHIFT; 9444 /* 9445 * If the gfn and userspace address are not aligned wrt each 9446 * other, or if explicitly asked to, disable large page 9447 * support for this slot 9448 */ 9449 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 9450 !kvm_largepages_enabled()) { 9451 unsigned long j; 9452 9453 for (j = 0; j < lpages; ++j) 9454 linfo[j].disallow_lpage = 1; 9455 } 9456 } 9457 9458 if (kvm_page_track_create_memslot(slot, npages)) 9459 goto out_free; 9460 9461 return 0; 9462 9463 out_free: 9464 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9465 kvfree(slot->arch.rmap[i]); 9466 slot->arch.rmap[i] = NULL; 9467 if (i == 0) 9468 continue; 9469 9470 kvfree(slot->arch.lpage_info[i - 1]); 9471 slot->arch.lpage_info[i - 1] = NULL; 9472 } 9473 return -ENOMEM; 9474 } 9475 9476 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 9477 { 9478 /* 9479 * memslots->generation has been incremented. 9480 * mmio generation may have reached its maximum value. 9481 */ 9482 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 9483 } 9484 9485 int kvm_arch_prepare_memory_region(struct kvm *kvm, 9486 struct kvm_memory_slot *memslot, 9487 const struct kvm_userspace_memory_region *mem, 9488 enum kvm_mr_change change) 9489 { 9490 return 0; 9491 } 9492 9493 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 9494 struct kvm_memory_slot *new) 9495 { 9496 /* Still write protect RO slot */ 9497 if (new->flags & KVM_MEM_READONLY) { 9498 kvm_mmu_slot_remove_write_access(kvm, new); 9499 return; 9500 } 9501 9502 /* 9503 * Call kvm_x86_ops dirty logging hooks when they are valid. 9504 * 9505 * kvm_x86_ops->slot_disable_log_dirty is called when: 9506 * 9507 * - KVM_MR_CREATE with dirty logging is disabled 9508 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 9509 * 9510 * The reason is, in case of PML, we need to set D-bit for any slots 9511 * with dirty logging disabled in order to eliminate unnecessary GPA 9512 * logging in PML buffer (and potential PML buffer full VMEXT). This 9513 * guarantees leaving PML enabled during guest's lifetime won't have 9514 * any additional overhead from PML when guest is running with dirty 9515 * logging disabled for memory slots. 9516 * 9517 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 9518 * to dirty logging mode. 9519 * 9520 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 9521 * 9522 * In case of write protect: 9523 * 9524 * Write protect all pages for dirty logging. 9525 * 9526 * All the sptes including the large sptes which point to this 9527 * slot are set to readonly. We can not create any new large 9528 * spte on this slot until the end of the logging. 9529 * 9530 * See the comments in fast_page_fault(). 9531 */ 9532 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 9533 if (kvm_x86_ops->slot_enable_log_dirty) 9534 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 9535 else 9536 kvm_mmu_slot_remove_write_access(kvm, new); 9537 } else { 9538 if (kvm_x86_ops->slot_disable_log_dirty) 9539 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 9540 } 9541 } 9542 9543 void kvm_arch_commit_memory_region(struct kvm *kvm, 9544 const struct kvm_userspace_memory_region *mem, 9545 const struct kvm_memory_slot *old, 9546 const struct kvm_memory_slot *new, 9547 enum kvm_mr_change change) 9548 { 9549 if (!kvm->arch.n_requested_mmu_pages) 9550 kvm_mmu_change_mmu_pages(kvm, 9551 kvm_mmu_calculate_default_mmu_pages(kvm)); 9552 9553 /* 9554 * Dirty logging tracks sptes in 4k granularity, meaning that large 9555 * sptes have to be split. If live migration is successful, the guest 9556 * in the source machine will be destroyed and large sptes will be 9557 * created in the destination. However, if the guest continues to run 9558 * in the source machine (for example if live migration fails), small 9559 * sptes will remain around and cause bad performance. 9560 * 9561 * Scan sptes if dirty logging has been stopped, dropping those 9562 * which can be collapsed into a single large-page spte. Later 9563 * page faults will create the large-page sptes. 9564 */ 9565 if ((change != KVM_MR_DELETE) && 9566 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 9567 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 9568 kvm_mmu_zap_collapsible_sptes(kvm, new); 9569 9570 /* 9571 * Set up write protection and/or dirty logging for the new slot. 9572 * 9573 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 9574 * been zapped so no dirty logging staff is needed for old slot. For 9575 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 9576 * new and it's also covered when dealing with the new slot. 9577 * 9578 * FIXME: const-ify all uses of struct kvm_memory_slot. 9579 */ 9580 if (change != KVM_MR_DELETE) 9581 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 9582 } 9583 9584 void kvm_arch_flush_shadow_all(struct kvm *kvm) 9585 { 9586 kvm_mmu_zap_all(kvm); 9587 } 9588 9589 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 9590 struct kvm_memory_slot *slot) 9591 { 9592 kvm_page_track_flush_slot(kvm, slot); 9593 } 9594 9595 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 9596 { 9597 return (is_guest_mode(vcpu) && 9598 kvm_x86_ops->guest_apic_has_interrupt && 9599 kvm_x86_ops->guest_apic_has_interrupt(vcpu)); 9600 } 9601 9602 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 9603 { 9604 if (!list_empty_careful(&vcpu->async_pf.done)) 9605 return true; 9606 9607 if (kvm_apic_has_events(vcpu)) 9608 return true; 9609 9610 if (vcpu->arch.pv.pv_unhalted) 9611 return true; 9612 9613 if (vcpu->arch.exception.pending) 9614 return true; 9615 9616 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 9617 (vcpu->arch.nmi_pending && 9618 kvm_x86_ops->nmi_allowed(vcpu))) 9619 return true; 9620 9621 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 9622 (vcpu->arch.smi_pending && !is_smm(vcpu))) 9623 return true; 9624 9625 if (kvm_arch_interrupt_allowed(vcpu) && 9626 (kvm_cpu_has_interrupt(vcpu) || 9627 kvm_guest_apic_has_interrupt(vcpu))) 9628 return true; 9629 9630 if (kvm_hv_has_stimer_pending(vcpu)) 9631 return true; 9632 9633 return false; 9634 } 9635 9636 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 9637 { 9638 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 9639 } 9640 9641 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 9642 { 9643 return vcpu->arch.preempted_in_kernel; 9644 } 9645 9646 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 9647 { 9648 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 9649 } 9650 9651 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 9652 { 9653 return kvm_x86_ops->interrupt_allowed(vcpu); 9654 } 9655 9656 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 9657 { 9658 if (is_64_bit_mode(vcpu)) 9659 return kvm_rip_read(vcpu); 9660 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 9661 kvm_rip_read(vcpu)); 9662 } 9663 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 9664 9665 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 9666 { 9667 return kvm_get_linear_rip(vcpu) == linear_rip; 9668 } 9669 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 9670 9671 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 9672 { 9673 unsigned long rflags; 9674 9675 rflags = kvm_x86_ops->get_rflags(vcpu); 9676 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9677 rflags &= ~X86_EFLAGS_TF; 9678 return rflags; 9679 } 9680 EXPORT_SYMBOL_GPL(kvm_get_rflags); 9681 9682 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9683 { 9684 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 9685 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 9686 rflags |= X86_EFLAGS_TF; 9687 kvm_x86_ops->set_rflags(vcpu, rflags); 9688 } 9689 9690 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9691 { 9692 __kvm_set_rflags(vcpu, rflags); 9693 kvm_make_request(KVM_REQ_EVENT, vcpu); 9694 } 9695 EXPORT_SYMBOL_GPL(kvm_set_rflags); 9696 9697 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 9698 { 9699 int r; 9700 9701 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 9702 work->wakeup_all) 9703 return; 9704 9705 r = kvm_mmu_reload(vcpu); 9706 if (unlikely(r)) 9707 return; 9708 9709 if (!vcpu->arch.mmu->direct_map && 9710 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu)) 9711 return; 9712 9713 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true); 9714 } 9715 9716 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 9717 { 9718 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 9719 } 9720 9721 static inline u32 kvm_async_pf_next_probe(u32 key) 9722 { 9723 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 9724 } 9725 9726 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9727 { 9728 u32 key = kvm_async_pf_hash_fn(gfn); 9729 9730 while (vcpu->arch.apf.gfns[key] != ~0) 9731 key = kvm_async_pf_next_probe(key); 9732 9733 vcpu->arch.apf.gfns[key] = gfn; 9734 } 9735 9736 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 9737 { 9738 int i; 9739 u32 key = kvm_async_pf_hash_fn(gfn); 9740 9741 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 9742 (vcpu->arch.apf.gfns[key] != gfn && 9743 vcpu->arch.apf.gfns[key] != ~0); i++) 9744 key = kvm_async_pf_next_probe(key); 9745 9746 return key; 9747 } 9748 9749 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9750 { 9751 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 9752 } 9753 9754 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9755 { 9756 u32 i, j, k; 9757 9758 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 9759 while (true) { 9760 vcpu->arch.apf.gfns[i] = ~0; 9761 do { 9762 j = kvm_async_pf_next_probe(j); 9763 if (vcpu->arch.apf.gfns[j] == ~0) 9764 return; 9765 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 9766 /* 9767 * k lies cyclically in ]i,j] 9768 * | i.k.j | 9769 * |....j i.k.| or |.k..j i...| 9770 */ 9771 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 9772 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 9773 i = j; 9774 } 9775 } 9776 9777 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 9778 { 9779 9780 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 9781 sizeof(val)); 9782 } 9783 9784 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 9785 { 9786 9787 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 9788 sizeof(u32)); 9789 } 9790 9791 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 9792 struct kvm_async_pf *work) 9793 { 9794 struct x86_exception fault; 9795 9796 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 9797 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 9798 9799 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 9800 (vcpu->arch.apf.send_user_only && 9801 kvm_x86_ops->get_cpl(vcpu) == 0)) 9802 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 9803 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 9804 fault.vector = PF_VECTOR; 9805 fault.error_code_valid = true; 9806 fault.error_code = 0; 9807 fault.nested_page_fault = false; 9808 fault.address = work->arch.token; 9809 fault.async_page_fault = true; 9810 kvm_inject_page_fault(vcpu, &fault); 9811 } 9812 } 9813 9814 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 9815 struct kvm_async_pf *work) 9816 { 9817 struct x86_exception fault; 9818 u32 val; 9819 9820 if (work->wakeup_all) 9821 work->arch.token = ~0; /* broadcast wakeup */ 9822 else 9823 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 9824 trace_kvm_async_pf_ready(work->arch.token, work->gva); 9825 9826 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 9827 !apf_get_user(vcpu, &val)) { 9828 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 9829 vcpu->arch.exception.pending && 9830 vcpu->arch.exception.nr == PF_VECTOR && 9831 !apf_put_user(vcpu, 0)) { 9832 vcpu->arch.exception.injected = false; 9833 vcpu->arch.exception.pending = false; 9834 vcpu->arch.exception.nr = 0; 9835 vcpu->arch.exception.has_error_code = false; 9836 vcpu->arch.exception.error_code = 0; 9837 vcpu->arch.exception.has_payload = false; 9838 vcpu->arch.exception.payload = 0; 9839 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 9840 fault.vector = PF_VECTOR; 9841 fault.error_code_valid = true; 9842 fault.error_code = 0; 9843 fault.nested_page_fault = false; 9844 fault.address = work->arch.token; 9845 fault.async_page_fault = true; 9846 kvm_inject_page_fault(vcpu, &fault); 9847 } 9848 } 9849 vcpu->arch.apf.halted = false; 9850 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9851 } 9852 9853 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 9854 { 9855 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 9856 return true; 9857 else 9858 return kvm_can_do_async_pf(vcpu); 9859 } 9860 9861 void kvm_arch_start_assignment(struct kvm *kvm) 9862 { 9863 atomic_inc(&kvm->arch.assigned_device_count); 9864 } 9865 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 9866 9867 void kvm_arch_end_assignment(struct kvm *kvm) 9868 { 9869 atomic_dec(&kvm->arch.assigned_device_count); 9870 } 9871 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 9872 9873 bool kvm_arch_has_assigned_device(struct kvm *kvm) 9874 { 9875 return atomic_read(&kvm->arch.assigned_device_count); 9876 } 9877 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 9878 9879 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 9880 { 9881 atomic_inc(&kvm->arch.noncoherent_dma_count); 9882 } 9883 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 9884 9885 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 9886 { 9887 atomic_dec(&kvm->arch.noncoherent_dma_count); 9888 } 9889 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 9890 9891 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 9892 { 9893 return atomic_read(&kvm->arch.noncoherent_dma_count); 9894 } 9895 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 9896 9897 bool kvm_arch_has_irq_bypass(void) 9898 { 9899 return kvm_x86_ops->update_pi_irte != NULL; 9900 } 9901 9902 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 9903 struct irq_bypass_producer *prod) 9904 { 9905 struct kvm_kernel_irqfd *irqfd = 9906 container_of(cons, struct kvm_kernel_irqfd, consumer); 9907 9908 irqfd->producer = prod; 9909 9910 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 9911 prod->irq, irqfd->gsi, 1); 9912 } 9913 9914 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 9915 struct irq_bypass_producer *prod) 9916 { 9917 int ret; 9918 struct kvm_kernel_irqfd *irqfd = 9919 container_of(cons, struct kvm_kernel_irqfd, consumer); 9920 9921 WARN_ON(irqfd->producer != prod); 9922 irqfd->producer = NULL; 9923 9924 /* 9925 * When producer of consumer is unregistered, we change back to 9926 * remapped mode, so we can re-use the current implementation 9927 * when the irq is masked/disabled or the consumer side (KVM 9928 * int this case doesn't want to receive the interrupts. 9929 */ 9930 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 9931 if (ret) 9932 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 9933 " fails: %d\n", irqfd->consumer.token, ret); 9934 } 9935 9936 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 9937 uint32_t guest_irq, bool set) 9938 { 9939 if (!kvm_x86_ops->update_pi_irte) 9940 return -EINVAL; 9941 9942 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 9943 } 9944 9945 bool kvm_vector_hashing_enabled(void) 9946 { 9947 return vector_hashing; 9948 } 9949 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 9950 9951 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 9952 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 9953 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 9954 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 9955 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 9956 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 9957 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 9958 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 9959 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 9960 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 9961 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 9962 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 9963 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 9964 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 9965 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 9966 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 9967 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 9968 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 9969 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 9970