1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 #include <linux/suspend.h> 62 63 #include <trace/events/kvm.h> 64 65 #include <asm/debugreg.h> 66 #include <asm/msr.h> 67 #include <asm/desc.h> 68 #include <asm/mce.h> 69 #include <asm/pkru.h> 70 #include <linux/kernel_stat.h> 71 #include <asm/fpu/api.h> 72 #include <asm/fpu/xcr.h> 73 #include <asm/fpu/xstate.h> 74 #include <asm/pvclock.h> 75 #include <asm/div64.h> 76 #include <asm/irq_remapping.h> 77 #include <asm/mshyperv.h> 78 #include <asm/hypervisor.h> 79 #include <asm/tlbflush.h> 80 #include <asm/intel_pt.h> 81 #include <asm/emulate_prefix.h> 82 #include <asm/sgx.h> 83 #include <clocksource/hyperv_timer.h> 84 85 #define CREATE_TRACE_POINTS 86 #include "trace.h" 87 88 #define MAX_IO_MSRS 256 89 #define KVM_MAX_MCE_BANKS 32 90 91 struct kvm_caps kvm_caps __read_mostly = { 92 .supported_mce_cap = MCG_CTL_P | MCG_SER_P, 93 }; 94 EXPORT_SYMBOL_GPL(kvm_caps); 95 96 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 97 98 #define emul_to_vcpu(ctxt) \ 99 ((struct kvm_vcpu *)(ctxt)->vcpu) 100 101 /* EFER defaults: 102 * - enable syscall per default because its emulated by KVM 103 * - enable LME and LMA per default on 64 bit KVM 104 */ 105 #ifdef CONFIG_X86_64 106 static 107 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 108 #else 109 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 110 #endif 111 112 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 113 114 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 115 116 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE 117 118 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 119 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 120 121 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 122 static void process_nmi(struct kvm_vcpu *vcpu); 123 static void process_smi(struct kvm_vcpu *vcpu); 124 static void enter_smm(struct kvm_vcpu *vcpu); 125 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 126 static void store_regs(struct kvm_vcpu *vcpu); 127 static int sync_regs(struct kvm_vcpu *vcpu); 128 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); 129 130 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 131 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 132 133 struct kvm_x86_ops kvm_x86_ops __read_mostly; 134 135 #define KVM_X86_OP(func) \ 136 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 137 *(((struct kvm_x86_ops *)0)->func)); 138 #define KVM_X86_OP_OPTIONAL KVM_X86_OP 139 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP 140 #include <asm/kvm-x86-ops.h> 141 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 142 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 143 144 static bool __read_mostly ignore_msrs = 0; 145 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 146 147 bool __read_mostly report_ignored_msrs = true; 148 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 149 EXPORT_SYMBOL_GPL(report_ignored_msrs); 150 151 unsigned int min_timer_period_us = 200; 152 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 153 154 static bool __read_mostly kvmclock_periodic_sync = true; 155 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 156 157 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 158 static u32 __read_mostly tsc_tolerance_ppm = 250; 159 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 160 161 /* 162 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 163 * adaptive tuning starting from default advancement of 1000ns. '0' disables 164 * advancement entirely. Any other value is used as-is and disables adaptive 165 * tuning, i.e. allows privileged userspace to set an exact advancement time. 166 */ 167 static int __read_mostly lapic_timer_advance_ns = -1; 168 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 169 170 static bool __read_mostly vector_hashing = true; 171 module_param(vector_hashing, bool, S_IRUGO); 172 173 bool __read_mostly enable_vmware_backdoor = false; 174 module_param(enable_vmware_backdoor, bool, S_IRUGO); 175 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 176 177 static bool __read_mostly force_emulation_prefix = false; 178 module_param(force_emulation_prefix, bool, S_IRUGO); 179 180 int __read_mostly pi_inject_timer = -1; 181 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 182 183 /* Enable/disable PMU virtualization */ 184 bool __read_mostly enable_pmu = true; 185 EXPORT_SYMBOL_GPL(enable_pmu); 186 module_param(enable_pmu, bool, 0444); 187 188 bool __read_mostly eager_page_split = true; 189 module_param(eager_page_split, bool, 0644); 190 191 /* 192 * Restoring the host value for MSRs that are only consumed when running in 193 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 194 * returns to userspace, i.e. the kernel can run with the guest's value. 195 */ 196 #define KVM_MAX_NR_USER_RETURN_MSRS 16 197 198 struct kvm_user_return_msrs { 199 struct user_return_notifier urn; 200 bool registered; 201 struct kvm_user_return_msr_values { 202 u64 host; 203 u64 curr; 204 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 205 }; 206 207 u32 __read_mostly kvm_nr_uret_msrs; 208 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 209 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 210 static struct kvm_user_return_msrs __percpu *user_return_msrs; 211 212 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 213 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 214 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 215 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) 216 217 u64 __read_mostly host_efer; 218 EXPORT_SYMBOL_GPL(host_efer); 219 220 bool __read_mostly allow_smaller_maxphyaddr = 0; 221 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 222 223 bool __read_mostly enable_apicv = true; 224 EXPORT_SYMBOL_GPL(enable_apicv); 225 226 u64 __read_mostly host_xss; 227 EXPORT_SYMBOL_GPL(host_xss); 228 229 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 230 KVM_GENERIC_VM_STATS(), 231 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 232 STATS_DESC_COUNTER(VM, mmu_pte_write), 233 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 234 STATS_DESC_COUNTER(VM, mmu_flooded), 235 STATS_DESC_COUNTER(VM, mmu_recycled), 236 STATS_DESC_COUNTER(VM, mmu_cache_miss), 237 STATS_DESC_ICOUNTER(VM, mmu_unsync), 238 STATS_DESC_ICOUNTER(VM, pages_4k), 239 STATS_DESC_ICOUNTER(VM, pages_2m), 240 STATS_DESC_ICOUNTER(VM, pages_1g), 241 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 242 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 243 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 244 }; 245 246 const struct kvm_stats_header kvm_vm_stats_header = { 247 .name_size = KVM_STATS_NAME_SIZE, 248 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 249 .id_offset = sizeof(struct kvm_stats_header), 250 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 251 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 252 sizeof(kvm_vm_stats_desc), 253 }; 254 255 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 256 KVM_GENERIC_VCPU_STATS(), 257 STATS_DESC_COUNTER(VCPU, pf_taken), 258 STATS_DESC_COUNTER(VCPU, pf_fixed), 259 STATS_DESC_COUNTER(VCPU, pf_emulate), 260 STATS_DESC_COUNTER(VCPU, pf_spurious), 261 STATS_DESC_COUNTER(VCPU, pf_fast), 262 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created), 263 STATS_DESC_COUNTER(VCPU, pf_guest), 264 STATS_DESC_COUNTER(VCPU, tlb_flush), 265 STATS_DESC_COUNTER(VCPU, invlpg), 266 STATS_DESC_COUNTER(VCPU, exits), 267 STATS_DESC_COUNTER(VCPU, io_exits), 268 STATS_DESC_COUNTER(VCPU, mmio_exits), 269 STATS_DESC_COUNTER(VCPU, signal_exits), 270 STATS_DESC_COUNTER(VCPU, irq_window_exits), 271 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 272 STATS_DESC_COUNTER(VCPU, l1d_flush), 273 STATS_DESC_COUNTER(VCPU, halt_exits), 274 STATS_DESC_COUNTER(VCPU, request_irq_exits), 275 STATS_DESC_COUNTER(VCPU, irq_exits), 276 STATS_DESC_COUNTER(VCPU, host_state_reload), 277 STATS_DESC_COUNTER(VCPU, fpu_reload), 278 STATS_DESC_COUNTER(VCPU, insn_emulation), 279 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 280 STATS_DESC_COUNTER(VCPU, hypercalls), 281 STATS_DESC_COUNTER(VCPU, irq_injections), 282 STATS_DESC_COUNTER(VCPU, nmi_injections), 283 STATS_DESC_COUNTER(VCPU, req_event), 284 STATS_DESC_COUNTER(VCPU, nested_run), 285 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 286 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 287 STATS_DESC_COUNTER(VCPU, preemption_reported), 288 STATS_DESC_COUNTER(VCPU, preemption_other), 289 STATS_DESC_ICOUNTER(VCPU, guest_mode), 290 STATS_DESC_COUNTER(VCPU, notify_window_exits), 291 }; 292 293 const struct kvm_stats_header kvm_vcpu_stats_header = { 294 .name_size = KVM_STATS_NAME_SIZE, 295 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 296 .id_offset = sizeof(struct kvm_stats_header), 297 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 298 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 299 sizeof(kvm_vcpu_stats_desc), 300 }; 301 302 u64 __read_mostly host_xcr0; 303 304 static struct kmem_cache *x86_emulator_cache; 305 306 /* 307 * When called, it means the previous get/set msr reached an invalid msr. 308 * Return true if we want to ignore/silent this failed msr access. 309 */ 310 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 311 { 312 const char *op = write ? "wrmsr" : "rdmsr"; 313 314 if (ignore_msrs) { 315 if (report_ignored_msrs) 316 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 317 op, msr, data); 318 /* Mask the error */ 319 return true; 320 } else { 321 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 322 op, msr, data); 323 return false; 324 } 325 } 326 327 static struct kmem_cache *kvm_alloc_emulator_cache(void) 328 { 329 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 330 unsigned int size = sizeof(struct x86_emulate_ctxt); 331 332 return kmem_cache_create_usercopy("x86_emulator", size, 333 __alignof__(struct x86_emulate_ctxt), 334 SLAB_ACCOUNT, useroffset, 335 size - useroffset, NULL); 336 } 337 338 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 339 340 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 341 { 342 int i; 343 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 344 vcpu->arch.apf.gfns[i] = ~0; 345 } 346 347 static void kvm_on_user_return(struct user_return_notifier *urn) 348 { 349 unsigned slot; 350 struct kvm_user_return_msrs *msrs 351 = container_of(urn, struct kvm_user_return_msrs, urn); 352 struct kvm_user_return_msr_values *values; 353 unsigned long flags; 354 355 /* 356 * Disabling irqs at this point since the following code could be 357 * interrupted and executed through kvm_arch_hardware_disable() 358 */ 359 local_irq_save(flags); 360 if (msrs->registered) { 361 msrs->registered = false; 362 user_return_notifier_unregister(urn); 363 } 364 local_irq_restore(flags); 365 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 366 values = &msrs->values[slot]; 367 if (values->host != values->curr) { 368 wrmsrl(kvm_uret_msrs_list[slot], values->host); 369 values->curr = values->host; 370 } 371 } 372 } 373 374 static int kvm_probe_user_return_msr(u32 msr) 375 { 376 u64 val; 377 int ret; 378 379 preempt_disable(); 380 ret = rdmsrl_safe(msr, &val); 381 if (ret) 382 goto out; 383 ret = wrmsrl_safe(msr, val); 384 out: 385 preempt_enable(); 386 return ret; 387 } 388 389 int kvm_add_user_return_msr(u32 msr) 390 { 391 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 392 393 if (kvm_probe_user_return_msr(msr)) 394 return -1; 395 396 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 397 return kvm_nr_uret_msrs++; 398 } 399 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 400 401 int kvm_find_user_return_msr(u32 msr) 402 { 403 int i; 404 405 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 406 if (kvm_uret_msrs_list[i] == msr) 407 return i; 408 } 409 return -1; 410 } 411 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 412 413 static void kvm_user_return_msr_cpu_online(void) 414 { 415 unsigned int cpu = smp_processor_id(); 416 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 417 u64 value; 418 int i; 419 420 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 421 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 422 msrs->values[i].host = value; 423 msrs->values[i].curr = value; 424 } 425 } 426 427 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 428 { 429 unsigned int cpu = smp_processor_id(); 430 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 431 int err; 432 433 value = (value & mask) | (msrs->values[slot].host & ~mask); 434 if (value == msrs->values[slot].curr) 435 return 0; 436 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 437 if (err) 438 return 1; 439 440 msrs->values[slot].curr = value; 441 if (!msrs->registered) { 442 msrs->urn.on_user_return = kvm_on_user_return; 443 user_return_notifier_register(&msrs->urn); 444 msrs->registered = true; 445 } 446 return 0; 447 } 448 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 449 450 static void drop_user_return_notifiers(void) 451 { 452 unsigned int cpu = smp_processor_id(); 453 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 454 455 if (msrs->registered) 456 kvm_on_user_return(&msrs->urn); 457 } 458 459 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 460 { 461 return vcpu->arch.apic_base; 462 } 463 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 464 465 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 466 { 467 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 468 } 469 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 470 471 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 472 { 473 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 474 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 475 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 476 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 477 478 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 479 return 1; 480 if (!msr_info->host_initiated) { 481 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 482 return 1; 483 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 484 return 1; 485 } 486 487 kvm_lapic_set_base(vcpu, msr_info->data); 488 kvm_recalculate_apic_map(vcpu->kvm); 489 return 0; 490 } 491 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 492 493 /* 494 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 495 * 496 * Hardware virtualization extension instructions may fault if a reboot turns 497 * off virtualization while processes are running. Usually after catching the 498 * fault we just panic; during reboot instead the instruction is ignored. 499 */ 500 noinstr void kvm_spurious_fault(void) 501 { 502 /* Fault while not rebooting. We want the trace. */ 503 BUG_ON(!kvm_rebooting); 504 } 505 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 506 507 #define EXCPT_BENIGN 0 508 #define EXCPT_CONTRIBUTORY 1 509 #define EXCPT_PF 2 510 511 static int exception_class(int vector) 512 { 513 switch (vector) { 514 case PF_VECTOR: 515 return EXCPT_PF; 516 case DE_VECTOR: 517 case TS_VECTOR: 518 case NP_VECTOR: 519 case SS_VECTOR: 520 case GP_VECTOR: 521 return EXCPT_CONTRIBUTORY; 522 default: 523 break; 524 } 525 return EXCPT_BENIGN; 526 } 527 528 #define EXCPT_FAULT 0 529 #define EXCPT_TRAP 1 530 #define EXCPT_ABORT 2 531 #define EXCPT_INTERRUPT 3 532 533 static int exception_type(int vector) 534 { 535 unsigned int mask; 536 537 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 538 return EXCPT_INTERRUPT; 539 540 mask = 1 << vector; 541 542 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 543 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 544 return EXCPT_TRAP; 545 546 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 547 return EXCPT_ABORT; 548 549 /* Reserved exceptions will result in fault */ 550 return EXCPT_FAULT; 551 } 552 553 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 554 { 555 unsigned nr = vcpu->arch.exception.nr; 556 bool has_payload = vcpu->arch.exception.has_payload; 557 unsigned long payload = vcpu->arch.exception.payload; 558 559 if (!has_payload) 560 return; 561 562 switch (nr) { 563 case DB_VECTOR: 564 /* 565 * "Certain debug exceptions may clear bit 0-3. The 566 * remaining contents of the DR6 register are never 567 * cleared by the processor". 568 */ 569 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 570 /* 571 * In order to reflect the #DB exception payload in guest 572 * dr6, three components need to be considered: active low 573 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 574 * DR6_BS and DR6_BT) 575 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 576 * In the target guest dr6: 577 * FIXED_1 bits should always be set. 578 * Active low bits should be cleared if 1-setting in payload. 579 * Active high bits should be set if 1-setting in payload. 580 * 581 * Note, the payload is compatible with the pending debug 582 * exceptions/exit qualification under VMX, that active_low bits 583 * are active high in payload. 584 * So they need to be flipped for DR6. 585 */ 586 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 587 vcpu->arch.dr6 |= payload; 588 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 589 590 /* 591 * The #DB payload is defined as compatible with the 'pending 592 * debug exceptions' field under VMX, not DR6. While bit 12 is 593 * defined in the 'pending debug exceptions' field (enabled 594 * breakpoint), it is reserved and must be zero in DR6. 595 */ 596 vcpu->arch.dr6 &= ~BIT(12); 597 break; 598 case PF_VECTOR: 599 vcpu->arch.cr2 = payload; 600 break; 601 } 602 603 vcpu->arch.exception.has_payload = false; 604 vcpu->arch.exception.payload = 0; 605 } 606 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 607 608 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 609 unsigned nr, bool has_error, u32 error_code, 610 bool has_payload, unsigned long payload, bool reinject) 611 { 612 u32 prev_nr; 613 int class1, class2; 614 615 kvm_make_request(KVM_REQ_EVENT, vcpu); 616 617 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 618 queue: 619 if (reinject) { 620 /* 621 * On vmentry, vcpu->arch.exception.pending is only 622 * true if an event injection was blocked by 623 * nested_run_pending. In that case, however, 624 * vcpu_enter_guest requests an immediate exit, 625 * and the guest shouldn't proceed far enough to 626 * need reinjection. 627 */ 628 WARN_ON_ONCE(vcpu->arch.exception.pending); 629 vcpu->arch.exception.injected = true; 630 if (WARN_ON_ONCE(has_payload)) { 631 /* 632 * A reinjected event has already 633 * delivered its payload. 634 */ 635 has_payload = false; 636 payload = 0; 637 } 638 } else { 639 vcpu->arch.exception.pending = true; 640 vcpu->arch.exception.injected = false; 641 } 642 vcpu->arch.exception.has_error_code = has_error; 643 vcpu->arch.exception.nr = nr; 644 vcpu->arch.exception.error_code = error_code; 645 vcpu->arch.exception.has_payload = has_payload; 646 vcpu->arch.exception.payload = payload; 647 if (!is_guest_mode(vcpu)) 648 kvm_deliver_exception_payload(vcpu); 649 return; 650 } 651 652 /* to check exception */ 653 prev_nr = vcpu->arch.exception.nr; 654 if (prev_nr == DF_VECTOR) { 655 /* triple fault -> shutdown */ 656 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 657 return; 658 } 659 class1 = exception_class(prev_nr); 660 class2 = exception_class(nr); 661 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 662 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 663 /* 664 * Generate double fault per SDM Table 5-5. Set 665 * exception.pending = true so that the double fault 666 * can trigger a nested vmexit. 667 */ 668 vcpu->arch.exception.pending = true; 669 vcpu->arch.exception.injected = false; 670 vcpu->arch.exception.has_error_code = true; 671 vcpu->arch.exception.nr = DF_VECTOR; 672 vcpu->arch.exception.error_code = 0; 673 vcpu->arch.exception.has_payload = false; 674 vcpu->arch.exception.payload = 0; 675 } else 676 /* replace previous exception with a new one in a hope 677 that instruction re-execution will regenerate lost 678 exception */ 679 goto queue; 680 } 681 682 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 683 { 684 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 685 } 686 EXPORT_SYMBOL_GPL(kvm_queue_exception); 687 688 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 689 { 690 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 691 } 692 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 693 694 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 695 unsigned long payload) 696 { 697 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 698 } 699 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 700 701 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 702 u32 error_code, unsigned long payload) 703 { 704 kvm_multiple_exception(vcpu, nr, true, error_code, 705 true, payload, false); 706 } 707 708 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 709 { 710 if (err) 711 kvm_inject_gp(vcpu, 0); 712 else 713 return kvm_skip_emulated_instruction(vcpu); 714 715 return 1; 716 } 717 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 718 719 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) 720 { 721 if (err) { 722 kvm_inject_gp(vcpu, 0); 723 return 1; 724 } 725 726 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 727 EMULTYPE_COMPLETE_USER_EXIT); 728 } 729 730 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 731 { 732 ++vcpu->stat.pf_guest; 733 vcpu->arch.exception.nested_apf = 734 is_guest_mode(vcpu) && fault->async_page_fault; 735 if (vcpu->arch.exception.nested_apf) { 736 vcpu->arch.apf.nested_apf_token = fault->address; 737 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 738 } else { 739 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 740 fault->address); 741 } 742 } 743 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 744 745 /* Returns true if the page fault was immediately morphed into a VM-Exit. */ 746 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 747 struct x86_exception *fault) 748 { 749 struct kvm_mmu *fault_mmu; 750 WARN_ON_ONCE(fault->vector != PF_VECTOR); 751 752 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 753 vcpu->arch.walk_mmu; 754 755 /* 756 * Invalidate the TLB entry for the faulting address, if it exists, 757 * else the access will fault indefinitely (and to emulate hardware). 758 */ 759 if ((fault->error_code & PFERR_PRESENT_MASK) && 760 !(fault->error_code & PFERR_RSVD_MASK)) 761 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 762 fault_mmu->root.hpa); 763 764 /* 765 * A workaround for KVM's bad exception handling. If KVM injected an 766 * exception into L2, and L2 encountered a #PF while vectoring the 767 * injected exception, manually check to see if L1 wants to intercept 768 * #PF, otherwise queuing the #PF will lead to #DF or a lost exception. 769 * In all other cases, defer the check to nested_ops->check_events(), 770 * which will correctly handle priority (this does not). Note, other 771 * exceptions, e.g. #GP, are theoretically affected, #PF is simply the 772 * most problematic, e.g. when L0 and L1 are both intercepting #PF for 773 * shadow paging. 774 * 775 * TODO: Rewrite exception handling to track injected and pending 776 * (VM-Exit) exceptions separately. 777 */ 778 if (unlikely(vcpu->arch.exception.injected && is_guest_mode(vcpu)) && 779 kvm_x86_ops.nested_ops->handle_page_fault_workaround(vcpu, fault)) 780 return true; 781 782 fault_mmu->inject_page_fault(vcpu, fault); 783 return false; 784 } 785 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 786 787 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 788 { 789 atomic_inc(&vcpu->arch.nmi_queued); 790 kvm_make_request(KVM_REQ_NMI, vcpu); 791 } 792 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 793 794 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 795 { 796 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 797 } 798 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 799 800 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 801 { 802 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 803 } 804 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 805 806 /* 807 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 808 * a #GP and return false. 809 */ 810 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 811 { 812 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 813 return true; 814 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 815 return false; 816 } 817 EXPORT_SYMBOL_GPL(kvm_require_cpl); 818 819 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 820 { 821 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 822 return true; 823 824 kvm_queue_exception(vcpu, UD_VECTOR); 825 return false; 826 } 827 EXPORT_SYMBOL_GPL(kvm_require_dr); 828 829 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 830 { 831 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 832 } 833 834 /* 835 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 836 */ 837 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) 838 { 839 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 840 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 841 gpa_t real_gpa; 842 int i; 843 int ret; 844 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 845 846 /* 847 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 848 * to an L1 GPA. 849 */ 850 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), 851 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 852 if (real_gpa == UNMAPPED_GVA) 853 return 0; 854 855 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 856 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 857 cr3 & GENMASK(11, 5), sizeof(pdpte)); 858 if (ret < 0) 859 return 0; 860 861 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 862 if ((pdpte[i] & PT_PRESENT_MASK) && 863 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 864 return 0; 865 } 866 } 867 868 /* 869 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. 870 * Shadow page roots need to be reconstructed instead. 871 */ 872 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) 873 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT); 874 875 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 876 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 877 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); 878 vcpu->arch.pdptrs_from_userspace = false; 879 880 return 1; 881 } 882 EXPORT_SYMBOL_GPL(load_pdptrs); 883 884 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 885 { 886 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 887 kvm_clear_async_pf_completion_queue(vcpu); 888 kvm_async_pf_hash_reset(vcpu); 889 890 /* 891 * Clearing CR0.PG is defined to flush the TLB from the guest's 892 * perspective. 893 */ 894 if (!(cr0 & X86_CR0_PG)) 895 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 896 } 897 898 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 899 kvm_mmu_reset_context(vcpu); 900 901 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 902 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 903 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 904 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 905 } 906 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 907 908 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 909 { 910 unsigned long old_cr0 = kvm_read_cr0(vcpu); 911 912 cr0 |= X86_CR0_ET; 913 914 #ifdef CONFIG_X86_64 915 if (cr0 & 0xffffffff00000000UL) 916 return 1; 917 #endif 918 919 cr0 &= ~CR0_RESERVED_BITS; 920 921 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 922 return 1; 923 924 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 925 return 1; 926 927 #ifdef CONFIG_X86_64 928 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 929 (cr0 & X86_CR0_PG)) { 930 int cs_db, cs_l; 931 932 if (!is_pae(vcpu)) 933 return 1; 934 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 935 if (cs_l) 936 return 1; 937 } 938 #endif 939 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 940 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && 941 !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 942 return 1; 943 944 if (!(cr0 & X86_CR0_PG) && 945 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))) 946 return 1; 947 948 static_call(kvm_x86_set_cr0)(vcpu, cr0); 949 950 kvm_post_set_cr0(vcpu, old_cr0, cr0); 951 952 return 0; 953 } 954 EXPORT_SYMBOL_GPL(kvm_set_cr0); 955 956 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 957 { 958 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 959 } 960 EXPORT_SYMBOL_GPL(kvm_lmsw); 961 962 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 963 { 964 if (vcpu->arch.guest_state_protected) 965 return; 966 967 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 968 969 if (vcpu->arch.xcr0 != host_xcr0) 970 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 971 972 if (vcpu->arch.xsaves_enabled && 973 vcpu->arch.ia32_xss != host_xss) 974 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 975 } 976 977 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 978 if (static_cpu_has(X86_FEATURE_PKU) && 979 vcpu->arch.pkru != vcpu->arch.host_pkru && 980 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 981 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) 982 write_pkru(vcpu->arch.pkru); 983 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ 984 } 985 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 986 987 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 988 { 989 if (vcpu->arch.guest_state_protected) 990 return; 991 992 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 993 if (static_cpu_has(X86_FEATURE_PKU) && 994 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 995 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) { 996 vcpu->arch.pkru = rdpkru(); 997 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 998 write_pkru(vcpu->arch.host_pkru); 999 } 1000 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ 1001 1002 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 1003 1004 if (vcpu->arch.xcr0 != host_xcr0) 1005 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 1006 1007 if (vcpu->arch.xsaves_enabled && 1008 vcpu->arch.ia32_xss != host_xss) 1009 wrmsrl(MSR_IA32_XSS, host_xss); 1010 } 1011 1012 } 1013 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 1014 1015 static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu) 1016 { 1017 return vcpu->arch.guest_fpu.fpstate->user_xfeatures; 1018 } 1019 1020 #ifdef CONFIG_X86_64 1021 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) 1022 { 1023 return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC; 1024 } 1025 #endif 1026 1027 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 1028 { 1029 u64 xcr0 = xcr; 1030 u64 old_xcr0 = vcpu->arch.xcr0; 1031 u64 valid_bits; 1032 1033 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 1034 if (index != XCR_XFEATURE_ENABLED_MASK) 1035 return 1; 1036 if (!(xcr0 & XFEATURE_MASK_FP)) 1037 return 1; 1038 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 1039 return 1; 1040 1041 /* 1042 * Do not allow the guest to set bits that we do not support 1043 * saving. However, xcr0 bit 0 is always set, even if the 1044 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 1045 */ 1046 valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP; 1047 if (xcr0 & ~valid_bits) 1048 return 1; 1049 1050 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 1051 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1052 return 1; 1053 1054 if (xcr0 & XFEATURE_MASK_AVX512) { 1055 if (!(xcr0 & XFEATURE_MASK_YMM)) 1056 return 1; 1057 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1058 return 1; 1059 } 1060 1061 if ((xcr0 & XFEATURE_MASK_XTILE) && 1062 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) 1063 return 1; 1064 1065 vcpu->arch.xcr0 = xcr0; 1066 1067 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1068 kvm_update_cpuid_runtime(vcpu); 1069 return 0; 1070 } 1071 1072 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1073 { 1074 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1075 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1076 kvm_inject_gp(vcpu, 0); 1077 return 1; 1078 } 1079 1080 return kvm_skip_emulated_instruction(vcpu); 1081 } 1082 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1083 1084 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1085 { 1086 if (cr4 & cr4_reserved_bits) 1087 return false; 1088 1089 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1090 return false; 1091 1092 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1093 } 1094 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1095 1096 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1097 { 1098 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1099 kvm_mmu_reset_context(vcpu); 1100 1101 /* 1102 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1103 * according to the SDM; however, stale prev_roots could be reused 1104 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1105 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST 1106 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed, 1107 * so fall through. 1108 */ 1109 if (!tdp_enabled && 1110 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) 1111 kvm_mmu_unload(vcpu); 1112 1113 /* 1114 * The TLB has to be flushed for all PCIDs if any of the following 1115 * (architecturally required) changes happen: 1116 * - CR4.PCIDE is changed from 1 to 0 1117 * - CR4.PGE is toggled 1118 * 1119 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT. 1120 */ 1121 if (((cr4 ^ old_cr4) & X86_CR4_PGE) || 1122 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1123 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1124 1125 /* 1126 * The TLB has to be flushed for the current PCID if any of the 1127 * following (architecturally required) changes happen: 1128 * - CR4.SMEP is changed from 0 to 1 1129 * - CR4.PAE is toggled 1130 */ 1131 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) || 1132 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP))) 1133 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1134 1135 } 1136 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1137 1138 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1139 { 1140 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1141 1142 if (!kvm_is_valid_cr4(vcpu, cr4)) 1143 return 1; 1144 1145 if (is_long_mode(vcpu)) { 1146 if (!(cr4 & X86_CR4_PAE)) 1147 return 1; 1148 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1149 return 1; 1150 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1151 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) 1152 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 1153 return 1; 1154 1155 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1156 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1157 return 1; 1158 1159 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1160 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1161 return 1; 1162 } 1163 1164 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1165 1166 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1167 1168 return 0; 1169 } 1170 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1171 1172 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1173 { 1174 struct kvm_mmu *mmu = vcpu->arch.mmu; 1175 unsigned long roots_to_free = 0; 1176 int i; 1177 1178 /* 1179 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1180 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1181 * also via the emulator. KVM's TDP page tables are not in the scope of 1182 * the invalidation, but the guest's TLB entries need to be flushed as 1183 * the CPU may have cached entries in its TLB for the target PCID. 1184 */ 1185 if (unlikely(tdp_enabled)) { 1186 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1187 return; 1188 } 1189 1190 /* 1191 * If neither the current CR3 nor any of the prev_roots use the given 1192 * PCID, then nothing needs to be done here because a resync will 1193 * happen anyway before switching to any other CR3. 1194 */ 1195 if (kvm_get_active_pcid(vcpu) == pcid) { 1196 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1197 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1198 } 1199 1200 /* 1201 * If PCID is disabled, there is no need to free prev_roots even if the 1202 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1203 * with PCIDE=0. 1204 */ 1205 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 1206 return; 1207 1208 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1209 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1210 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1211 1212 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); 1213 } 1214 1215 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1216 { 1217 bool skip_tlb_flush = false; 1218 unsigned long pcid = 0; 1219 #ifdef CONFIG_X86_64 1220 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1221 1222 if (pcid_enabled) { 1223 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1224 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1225 pcid = cr3 & X86_CR3_PCID_MASK; 1226 } 1227 #endif 1228 1229 /* PDPTRs are always reloaded for PAE paging. */ 1230 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1231 goto handle_tlb_flush; 1232 1233 /* 1234 * Do not condition the GPA check on long mode, this helper is used to 1235 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1236 * the current vCPU mode is accurate. 1237 */ 1238 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1239 return 1; 1240 1241 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) 1242 return 1; 1243 1244 if (cr3 != kvm_read_cr3(vcpu)) 1245 kvm_mmu_new_pgd(vcpu, cr3); 1246 1247 vcpu->arch.cr3 = cr3; 1248 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 1249 /* Do not call post_set_cr3, we do not get here for confidential guests. */ 1250 1251 handle_tlb_flush: 1252 /* 1253 * A load of CR3 that flushes the TLB flushes only the current PCID, 1254 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1255 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1256 * and it's impossible to use a non-zero PCID when PCID is disabled, 1257 * i.e. only PCID=0 can be relevant. 1258 */ 1259 if (!skip_tlb_flush) 1260 kvm_invalidate_pcid(vcpu, pcid); 1261 1262 return 0; 1263 } 1264 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1265 1266 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1267 { 1268 if (cr8 & CR8_RESERVED_BITS) 1269 return 1; 1270 if (lapic_in_kernel(vcpu)) 1271 kvm_lapic_set_tpr(vcpu, cr8); 1272 else 1273 vcpu->arch.cr8 = cr8; 1274 return 0; 1275 } 1276 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1277 1278 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1279 { 1280 if (lapic_in_kernel(vcpu)) 1281 return kvm_lapic_get_cr8(vcpu); 1282 else 1283 return vcpu->arch.cr8; 1284 } 1285 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1286 1287 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1288 { 1289 int i; 1290 1291 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1292 for (i = 0; i < KVM_NR_DB_REGS; i++) 1293 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1294 } 1295 } 1296 1297 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1298 { 1299 unsigned long dr7; 1300 1301 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1302 dr7 = vcpu->arch.guest_debug_dr7; 1303 else 1304 dr7 = vcpu->arch.dr7; 1305 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1306 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1307 if (dr7 & DR7_BP_EN_MASK) 1308 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1309 } 1310 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1311 1312 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1313 { 1314 u64 fixed = DR6_FIXED_1; 1315 1316 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1317 fixed |= DR6_RTM; 1318 1319 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1320 fixed |= DR6_BUS_LOCK; 1321 return fixed; 1322 } 1323 1324 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1325 { 1326 size_t size = ARRAY_SIZE(vcpu->arch.db); 1327 1328 switch (dr) { 1329 case 0 ... 3: 1330 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1331 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1332 vcpu->arch.eff_db[dr] = val; 1333 break; 1334 case 4: 1335 case 6: 1336 if (!kvm_dr6_valid(val)) 1337 return 1; /* #GP */ 1338 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1339 break; 1340 case 5: 1341 default: /* 7 */ 1342 if (!kvm_dr7_valid(val)) 1343 return 1; /* #GP */ 1344 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1345 kvm_update_dr7(vcpu); 1346 break; 1347 } 1348 1349 return 0; 1350 } 1351 EXPORT_SYMBOL_GPL(kvm_set_dr); 1352 1353 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1354 { 1355 size_t size = ARRAY_SIZE(vcpu->arch.db); 1356 1357 switch (dr) { 1358 case 0 ... 3: 1359 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1360 break; 1361 case 4: 1362 case 6: 1363 *val = vcpu->arch.dr6; 1364 break; 1365 case 5: 1366 default: /* 7 */ 1367 *val = vcpu->arch.dr7; 1368 break; 1369 } 1370 } 1371 EXPORT_SYMBOL_GPL(kvm_get_dr); 1372 1373 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1374 { 1375 u32 ecx = kvm_rcx_read(vcpu); 1376 u64 data; 1377 1378 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1379 kvm_inject_gp(vcpu, 0); 1380 return 1; 1381 } 1382 1383 kvm_rax_write(vcpu, (u32)data); 1384 kvm_rdx_write(vcpu, data >> 32); 1385 return kvm_skip_emulated_instruction(vcpu); 1386 } 1387 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1388 1389 /* 1390 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1391 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1392 * 1393 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1394 * extract the supported MSRs from the related const lists. 1395 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1396 * capabilities of the host cpu. This capabilities test skips MSRs that are 1397 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1398 * may depend on host virtualization features rather than host cpu features. 1399 */ 1400 1401 static const u32 msrs_to_save_all[] = { 1402 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1403 MSR_STAR, 1404 #ifdef CONFIG_X86_64 1405 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1406 #endif 1407 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1408 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1409 MSR_IA32_SPEC_CTRL, 1410 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1411 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1412 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1413 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1414 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1415 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1416 MSR_IA32_UMWAIT_CONTROL, 1417 1418 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1419 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, 1420 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1421 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1422 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1423 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1424 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1425 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1426 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1427 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1428 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1429 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1430 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1431 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1432 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1433 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1434 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1435 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1436 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1437 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1438 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1439 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1440 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, 1441 1442 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1443 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1444 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1445 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1446 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1447 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1448 MSR_IA32_XFD, MSR_IA32_XFD_ERR, 1449 }; 1450 1451 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1452 static unsigned num_msrs_to_save; 1453 1454 static const u32 emulated_msrs_all[] = { 1455 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1456 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1457 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1458 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1459 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1460 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1461 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1462 HV_X64_MSR_RESET, 1463 HV_X64_MSR_VP_INDEX, 1464 HV_X64_MSR_VP_RUNTIME, 1465 HV_X64_MSR_SCONTROL, 1466 HV_X64_MSR_STIMER0_CONFIG, 1467 HV_X64_MSR_VP_ASSIST_PAGE, 1468 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1469 HV_X64_MSR_TSC_EMULATION_STATUS, 1470 HV_X64_MSR_SYNDBG_OPTIONS, 1471 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1472 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1473 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1474 1475 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1476 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1477 1478 MSR_IA32_TSC_ADJUST, 1479 MSR_IA32_TSC_DEADLINE, 1480 MSR_IA32_ARCH_CAPABILITIES, 1481 MSR_IA32_PERF_CAPABILITIES, 1482 MSR_IA32_MISC_ENABLE, 1483 MSR_IA32_MCG_STATUS, 1484 MSR_IA32_MCG_CTL, 1485 MSR_IA32_MCG_EXT_CTL, 1486 MSR_IA32_SMBASE, 1487 MSR_SMI_COUNT, 1488 MSR_PLATFORM_INFO, 1489 MSR_MISC_FEATURES_ENABLES, 1490 MSR_AMD64_VIRT_SPEC_CTRL, 1491 MSR_AMD64_TSC_RATIO, 1492 MSR_IA32_POWER_CTL, 1493 MSR_IA32_UCODE_REV, 1494 1495 /* 1496 * The following list leaves out MSRs whose values are determined 1497 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1498 * We always support the "true" VMX control MSRs, even if the host 1499 * processor does not, so I am putting these registers here rather 1500 * than in msrs_to_save_all. 1501 */ 1502 MSR_IA32_VMX_BASIC, 1503 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1504 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1505 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1506 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1507 MSR_IA32_VMX_MISC, 1508 MSR_IA32_VMX_CR0_FIXED0, 1509 MSR_IA32_VMX_CR4_FIXED0, 1510 MSR_IA32_VMX_VMCS_ENUM, 1511 MSR_IA32_VMX_PROCBASED_CTLS2, 1512 MSR_IA32_VMX_EPT_VPID_CAP, 1513 MSR_IA32_VMX_VMFUNC, 1514 1515 MSR_K7_HWCR, 1516 MSR_KVM_POLL_CONTROL, 1517 }; 1518 1519 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1520 static unsigned num_emulated_msrs; 1521 1522 /* 1523 * List of msr numbers which are used to expose MSR-based features that 1524 * can be used by a hypervisor to validate requested CPU features. 1525 */ 1526 static const u32 msr_based_features_all[] = { 1527 MSR_IA32_VMX_BASIC, 1528 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1529 MSR_IA32_VMX_PINBASED_CTLS, 1530 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1531 MSR_IA32_VMX_PROCBASED_CTLS, 1532 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1533 MSR_IA32_VMX_EXIT_CTLS, 1534 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1535 MSR_IA32_VMX_ENTRY_CTLS, 1536 MSR_IA32_VMX_MISC, 1537 MSR_IA32_VMX_CR0_FIXED0, 1538 MSR_IA32_VMX_CR0_FIXED1, 1539 MSR_IA32_VMX_CR4_FIXED0, 1540 MSR_IA32_VMX_CR4_FIXED1, 1541 MSR_IA32_VMX_VMCS_ENUM, 1542 MSR_IA32_VMX_PROCBASED_CTLS2, 1543 MSR_IA32_VMX_EPT_VPID_CAP, 1544 MSR_IA32_VMX_VMFUNC, 1545 1546 MSR_F10H_DECFG, 1547 MSR_IA32_UCODE_REV, 1548 MSR_IA32_ARCH_CAPABILITIES, 1549 MSR_IA32_PERF_CAPABILITIES, 1550 }; 1551 1552 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1553 static unsigned int num_msr_based_features; 1554 1555 static u64 kvm_get_arch_capabilities(void) 1556 { 1557 u64 data = 0; 1558 1559 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1560 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1561 1562 /* 1563 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1564 * the nested hypervisor runs with NX huge pages. If it is not, 1565 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1566 * L1 guests, so it need not worry about its own (L2) guests. 1567 */ 1568 data |= ARCH_CAP_PSCHANGE_MC_NO; 1569 1570 /* 1571 * If we're doing cache flushes (either "always" or "cond") 1572 * we will do one whenever the guest does a vmlaunch/vmresume. 1573 * If an outer hypervisor is doing the cache flush for us 1574 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1575 * capability to the guest too, and if EPT is disabled we're not 1576 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1577 * require a nested hypervisor to do a flush of its own. 1578 */ 1579 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1580 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1581 1582 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1583 data |= ARCH_CAP_RDCL_NO; 1584 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1585 data |= ARCH_CAP_SSB_NO; 1586 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1587 data |= ARCH_CAP_MDS_NO; 1588 1589 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1590 /* 1591 * If RTM=0 because the kernel has disabled TSX, the host might 1592 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1593 * and therefore knows that there cannot be TAA) but keep 1594 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1595 * and we want to allow migrating those guests to tsx=off hosts. 1596 */ 1597 data &= ~ARCH_CAP_TAA_NO; 1598 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1599 data |= ARCH_CAP_TAA_NO; 1600 } else { 1601 /* 1602 * Nothing to do here; we emulate TSX_CTRL if present on the 1603 * host so the guest can choose between disabling TSX or 1604 * using VERW to clear CPU buffers. 1605 */ 1606 } 1607 1608 return data; 1609 } 1610 1611 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1612 { 1613 switch (msr->index) { 1614 case MSR_IA32_ARCH_CAPABILITIES: 1615 msr->data = kvm_get_arch_capabilities(); 1616 break; 1617 case MSR_IA32_UCODE_REV: 1618 rdmsrl_safe(msr->index, &msr->data); 1619 break; 1620 default: 1621 return static_call(kvm_x86_get_msr_feature)(msr); 1622 } 1623 return 0; 1624 } 1625 1626 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1627 { 1628 struct kvm_msr_entry msr; 1629 int r; 1630 1631 msr.index = index; 1632 r = kvm_get_msr_feature(&msr); 1633 1634 if (r == KVM_MSR_RET_INVALID) { 1635 /* Unconditionally clear the output for simplicity */ 1636 *data = 0; 1637 if (kvm_msr_ignored_check(index, 0, false)) 1638 r = 0; 1639 } 1640 1641 if (r) 1642 return r; 1643 1644 *data = msr.data; 1645 1646 return 0; 1647 } 1648 1649 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1650 { 1651 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1652 return false; 1653 1654 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1655 return false; 1656 1657 if (efer & (EFER_LME | EFER_LMA) && 1658 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1659 return false; 1660 1661 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1662 return false; 1663 1664 return true; 1665 1666 } 1667 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1668 { 1669 if (efer & efer_reserved_bits) 1670 return false; 1671 1672 return __kvm_valid_efer(vcpu, efer); 1673 } 1674 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1675 1676 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1677 { 1678 u64 old_efer = vcpu->arch.efer; 1679 u64 efer = msr_info->data; 1680 int r; 1681 1682 if (efer & efer_reserved_bits) 1683 return 1; 1684 1685 if (!msr_info->host_initiated) { 1686 if (!__kvm_valid_efer(vcpu, efer)) 1687 return 1; 1688 1689 if (is_paging(vcpu) && 1690 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1691 return 1; 1692 } 1693 1694 efer &= ~EFER_LMA; 1695 efer |= vcpu->arch.efer & EFER_LMA; 1696 1697 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1698 if (r) { 1699 WARN_ON(r > 0); 1700 return r; 1701 } 1702 1703 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) 1704 kvm_mmu_reset_context(vcpu); 1705 1706 return 0; 1707 } 1708 1709 void kvm_enable_efer_bits(u64 mask) 1710 { 1711 efer_reserved_bits &= ~mask; 1712 } 1713 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1714 1715 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1716 { 1717 struct kvm_x86_msr_filter *msr_filter; 1718 struct msr_bitmap_range *ranges; 1719 struct kvm *kvm = vcpu->kvm; 1720 bool allowed; 1721 int idx; 1722 u32 i; 1723 1724 /* x2APIC MSRs do not support filtering. */ 1725 if (index >= 0x800 && index <= 0x8ff) 1726 return true; 1727 1728 idx = srcu_read_lock(&kvm->srcu); 1729 1730 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1731 if (!msr_filter) { 1732 allowed = true; 1733 goto out; 1734 } 1735 1736 allowed = msr_filter->default_allow; 1737 ranges = msr_filter->ranges; 1738 1739 for (i = 0; i < msr_filter->count; i++) { 1740 u32 start = ranges[i].base; 1741 u32 end = start + ranges[i].nmsrs; 1742 u32 flags = ranges[i].flags; 1743 unsigned long *bitmap = ranges[i].bitmap; 1744 1745 if ((index >= start) && (index < end) && (flags & type)) { 1746 allowed = !!test_bit(index - start, bitmap); 1747 break; 1748 } 1749 } 1750 1751 out: 1752 srcu_read_unlock(&kvm->srcu, idx); 1753 1754 return allowed; 1755 } 1756 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1757 1758 /* 1759 * Write @data into the MSR specified by @index. Select MSR specific fault 1760 * checks are bypassed if @host_initiated is %true. 1761 * Returns 0 on success, non-0 otherwise. 1762 * Assumes vcpu_load() was already called. 1763 */ 1764 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1765 bool host_initiated) 1766 { 1767 struct msr_data msr; 1768 1769 switch (index) { 1770 case MSR_FS_BASE: 1771 case MSR_GS_BASE: 1772 case MSR_KERNEL_GS_BASE: 1773 case MSR_CSTAR: 1774 case MSR_LSTAR: 1775 if (is_noncanonical_address(data, vcpu)) 1776 return 1; 1777 break; 1778 case MSR_IA32_SYSENTER_EIP: 1779 case MSR_IA32_SYSENTER_ESP: 1780 /* 1781 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1782 * non-canonical address is written on Intel but not on 1783 * AMD (which ignores the top 32-bits, because it does 1784 * not implement 64-bit SYSENTER). 1785 * 1786 * 64-bit code should hence be able to write a non-canonical 1787 * value on AMD. Making the address canonical ensures that 1788 * vmentry does not fail on Intel after writing a non-canonical 1789 * value, and that something deterministic happens if the guest 1790 * invokes 64-bit SYSENTER. 1791 */ 1792 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu)); 1793 break; 1794 case MSR_TSC_AUX: 1795 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1796 return 1; 1797 1798 if (!host_initiated && 1799 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1800 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1801 return 1; 1802 1803 /* 1804 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1805 * incomplete and conflicting architectural behavior. Current 1806 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1807 * reserved and always read as zeros. Enforce Intel's reserved 1808 * bits check if and only if the guest CPU is Intel, and clear 1809 * the bits in all other cases. This ensures cross-vendor 1810 * migration will provide consistent behavior for the guest. 1811 */ 1812 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1813 return 1; 1814 1815 data = (u32)data; 1816 break; 1817 } 1818 1819 msr.data = data; 1820 msr.index = index; 1821 msr.host_initiated = host_initiated; 1822 1823 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1824 } 1825 1826 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1827 u32 index, u64 data, bool host_initiated) 1828 { 1829 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1830 1831 if (ret == KVM_MSR_RET_INVALID) 1832 if (kvm_msr_ignored_check(index, data, true)) 1833 ret = 0; 1834 1835 return ret; 1836 } 1837 1838 /* 1839 * Read the MSR specified by @index into @data. Select MSR specific fault 1840 * checks are bypassed if @host_initiated is %true. 1841 * Returns 0 on success, non-0 otherwise. 1842 * Assumes vcpu_load() was already called. 1843 */ 1844 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1845 bool host_initiated) 1846 { 1847 struct msr_data msr; 1848 int ret; 1849 1850 switch (index) { 1851 case MSR_TSC_AUX: 1852 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1853 return 1; 1854 1855 if (!host_initiated && 1856 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1857 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1858 return 1; 1859 break; 1860 } 1861 1862 msr.index = index; 1863 msr.host_initiated = host_initiated; 1864 1865 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1866 if (!ret) 1867 *data = msr.data; 1868 return ret; 1869 } 1870 1871 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1872 u32 index, u64 *data, bool host_initiated) 1873 { 1874 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1875 1876 if (ret == KVM_MSR_RET_INVALID) { 1877 /* Unconditionally clear *data for simplicity */ 1878 *data = 0; 1879 if (kvm_msr_ignored_check(index, 0, false)) 1880 ret = 0; 1881 } 1882 1883 return ret; 1884 } 1885 1886 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1887 { 1888 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1889 return KVM_MSR_RET_FILTERED; 1890 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1891 } 1892 1893 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data) 1894 { 1895 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1896 return KVM_MSR_RET_FILTERED; 1897 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1898 } 1899 1900 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1901 { 1902 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1903 } 1904 EXPORT_SYMBOL_GPL(kvm_get_msr); 1905 1906 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1907 { 1908 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1909 } 1910 EXPORT_SYMBOL_GPL(kvm_set_msr); 1911 1912 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) 1913 { 1914 if (!vcpu->run->msr.error) { 1915 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1916 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1917 } 1918 } 1919 1920 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) 1921 { 1922 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); 1923 } 1924 1925 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1926 { 1927 complete_userspace_rdmsr(vcpu); 1928 return complete_emulated_msr_access(vcpu); 1929 } 1930 1931 static int complete_fast_msr_access(struct kvm_vcpu *vcpu) 1932 { 1933 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1934 } 1935 1936 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) 1937 { 1938 complete_userspace_rdmsr(vcpu); 1939 return complete_fast_msr_access(vcpu); 1940 } 1941 1942 static u64 kvm_msr_reason(int r) 1943 { 1944 switch (r) { 1945 case KVM_MSR_RET_INVALID: 1946 return KVM_MSR_EXIT_REASON_UNKNOWN; 1947 case KVM_MSR_RET_FILTERED: 1948 return KVM_MSR_EXIT_REASON_FILTER; 1949 default: 1950 return KVM_MSR_EXIT_REASON_INVAL; 1951 } 1952 } 1953 1954 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1955 u32 exit_reason, u64 data, 1956 int (*completion)(struct kvm_vcpu *vcpu), 1957 int r) 1958 { 1959 u64 msr_reason = kvm_msr_reason(r); 1960 1961 /* Check if the user wanted to know about this MSR fault */ 1962 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1963 return 0; 1964 1965 vcpu->run->exit_reason = exit_reason; 1966 vcpu->run->msr.error = 0; 1967 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1968 vcpu->run->msr.reason = msr_reason; 1969 vcpu->run->msr.index = index; 1970 vcpu->run->msr.data = data; 1971 vcpu->arch.complete_userspace_io = completion; 1972 1973 return 1; 1974 } 1975 1976 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1977 { 1978 u32 ecx = kvm_rcx_read(vcpu); 1979 u64 data; 1980 int r; 1981 1982 r = kvm_get_msr_with_filter(vcpu, ecx, &data); 1983 1984 if (!r) { 1985 trace_kvm_msr_read(ecx, data); 1986 1987 kvm_rax_write(vcpu, data & -1u); 1988 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1989 } else { 1990 /* MSR read failed? See if we should ask user space */ 1991 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, 1992 complete_fast_rdmsr, r)) 1993 return 0; 1994 trace_kvm_msr_read_ex(ecx); 1995 } 1996 1997 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1998 } 1999 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 2000 2001 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 2002 { 2003 u32 ecx = kvm_rcx_read(vcpu); 2004 u64 data = kvm_read_edx_eax(vcpu); 2005 int r; 2006 2007 r = kvm_set_msr_with_filter(vcpu, ecx, data); 2008 2009 if (!r) { 2010 trace_kvm_msr_write(ecx, data); 2011 } else { 2012 /* MSR write failed? See if we should ask user space */ 2013 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, 2014 complete_fast_msr_access, r)) 2015 return 0; 2016 /* Signal all other negative errors to userspace */ 2017 if (r < 0) 2018 return r; 2019 trace_kvm_msr_write_ex(ecx, data); 2020 } 2021 2022 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 2023 } 2024 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 2025 2026 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 2027 { 2028 return kvm_skip_emulated_instruction(vcpu); 2029 } 2030 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 2031 2032 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 2033 { 2034 /* Treat an INVD instruction as a NOP and just skip it. */ 2035 return kvm_emulate_as_nop(vcpu); 2036 } 2037 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 2038 2039 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 2040 { 2041 kvm_queue_exception(vcpu, UD_VECTOR); 2042 return 1; 2043 } 2044 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 2045 2046 2047 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn) 2048 { 2049 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_FAULTS) && 2050 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT)) 2051 return kvm_handle_invalid_op(vcpu); 2052 2053 pr_warn_once("kvm: %s instruction emulated as NOP!\n", insn); 2054 return kvm_emulate_as_nop(vcpu); 2055 } 2056 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 2057 { 2058 return kvm_emulate_monitor_mwait(vcpu, "MWAIT"); 2059 } 2060 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 2061 2062 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 2063 { 2064 return kvm_emulate_monitor_mwait(vcpu, "MONITOR"); 2065 } 2066 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 2067 2068 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 2069 { 2070 xfer_to_guest_mode_prepare(); 2071 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 2072 xfer_to_guest_mode_work_pending(); 2073 } 2074 2075 /* 2076 * The fast path for frequent and performance sensitive wrmsr emulation, 2077 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 2078 * the latency of virtual IPI by avoiding the expensive bits of transitioning 2079 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 2080 * other cases which must be called after interrupts are enabled on the host. 2081 */ 2082 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 2083 { 2084 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 2085 return 1; 2086 2087 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 2088 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 2089 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 2090 ((u32)(data >> 32) != X2APIC_BROADCAST)) 2091 return kvm_x2apic_icr_write(vcpu->arch.apic, data); 2092 2093 return 1; 2094 } 2095 2096 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2097 { 2098 if (!kvm_can_use_hv_timer(vcpu)) 2099 return 1; 2100 2101 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2102 return 0; 2103 } 2104 2105 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2106 { 2107 u32 msr = kvm_rcx_read(vcpu); 2108 u64 data; 2109 fastpath_t ret = EXIT_FASTPATH_NONE; 2110 2111 switch (msr) { 2112 case APIC_BASE_MSR + (APIC_ICR >> 4): 2113 data = kvm_read_edx_eax(vcpu); 2114 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2115 kvm_skip_emulated_instruction(vcpu); 2116 ret = EXIT_FASTPATH_EXIT_HANDLED; 2117 } 2118 break; 2119 case MSR_IA32_TSC_DEADLINE: 2120 data = kvm_read_edx_eax(vcpu); 2121 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2122 kvm_skip_emulated_instruction(vcpu); 2123 ret = EXIT_FASTPATH_REENTER_GUEST; 2124 } 2125 break; 2126 default: 2127 break; 2128 } 2129 2130 if (ret != EXIT_FASTPATH_NONE) 2131 trace_kvm_msr_write(msr, data); 2132 2133 return ret; 2134 } 2135 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2136 2137 /* 2138 * Adapt set_msr() to msr_io()'s calling convention 2139 */ 2140 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2141 { 2142 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2143 } 2144 2145 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2146 { 2147 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2148 } 2149 2150 #ifdef CONFIG_X86_64 2151 struct pvclock_clock { 2152 int vclock_mode; 2153 u64 cycle_last; 2154 u64 mask; 2155 u32 mult; 2156 u32 shift; 2157 u64 base_cycles; 2158 u64 offset; 2159 }; 2160 2161 struct pvclock_gtod_data { 2162 seqcount_t seq; 2163 2164 struct pvclock_clock clock; /* extract of a clocksource struct */ 2165 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2166 2167 ktime_t offs_boot; 2168 u64 wall_time_sec; 2169 }; 2170 2171 static struct pvclock_gtod_data pvclock_gtod_data; 2172 2173 static void update_pvclock_gtod(struct timekeeper *tk) 2174 { 2175 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2176 2177 write_seqcount_begin(&vdata->seq); 2178 2179 /* copy pvclock gtod data */ 2180 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2181 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2182 vdata->clock.mask = tk->tkr_mono.mask; 2183 vdata->clock.mult = tk->tkr_mono.mult; 2184 vdata->clock.shift = tk->tkr_mono.shift; 2185 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2186 vdata->clock.offset = tk->tkr_mono.base; 2187 2188 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2189 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2190 vdata->raw_clock.mask = tk->tkr_raw.mask; 2191 vdata->raw_clock.mult = tk->tkr_raw.mult; 2192 vdata->raw_clock.shift = tk->tkr_raw.shift; 2193 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2194 vdata->raw_clock.offset = tk->tkr_raw.base; 2195 2196 vdata->wall_time_sec = tk->xtime_sec; 2197 2198 vdata->offs_boot = tk->offs_boot; 2199 2200 write_seqcount_end(&vdata->seq); 2201 } 2202 2203 static s64 get_kvmclock_base_ns(void) 2204 { 2205 /* Count up from boot time, but with the frequency of the raw clock. */ 2206 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2207 } 2208 #else 2209 static s64 get_kvmclock_base_ns(void) 2210 { 2211 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2212 return ktime_get_boottime_ns(); 2213 } 2214 #endif 2215 2216 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2217 { 2218 int version; 2219 int r; 2220 struct pvclock_wall_clock wc; 2221 u32 wc_sec_hi; 2222 u64 wall_nsec; 2223 2224 if (!wall_clock) 2225 return; 2226 2227 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2228 if (r) 2229 return; 2230 2231 if (version & 1) 2232 ++version; /* first time write, random junk */ 2233 2234 ++version; 2235 2236 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2237 return; 2238 2239 /* 2240 * The guest calculates current wall clock time by adding 2241 * system time (updated by kvm_guest_time_update below) to the 2242 * wall clock specified here. We do the reverse here. 2243 */ 2244 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2245 2246 wc.nsec = do_div(wall_nsec, 1000000000); 2247 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2248 wc.version = version; 2249 2250 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2251 2252 if (sec_hi_ofs) { 2253 wc_sec_hi = wall_nsec >> 32; 2254 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2255 &wc_sec_hi, sizeof(wc_sec_hi)); 2256 } 2257 2258 version++; 2259 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2260 } 2261 2262 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2263 bool old_msr, bool host_initiated) 2264 { 2265 struct kvm_arch *ka = &vcpu->kvm->arch; 2266 2267 if (vcpu->vcpu_id == 0 && !host_initiated) { 2268 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2269 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2270 2271 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2272 } 2273 2274 vcpu->arch.time = system_time; 2275 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2276 2277 /* we verify if the enable bit is set... */ 2278 if (system_time & 1) { 2279 kvm_gfn_to_pfn_cache_init(vcpu->kvm, &vcpu->arch.pv_time, vcpu, 2280 KVM_HOST_USES_PFN, system_time & ~1ULL, 2281 sizeof(struct pvclock_vcpu_time_info)); 2282 } else { 2283 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time); 2284 } 2285 2286 return; 2287 } 2288 2289 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2290 { 2291 do_shl32_div32(dividend, divisor); 2292 return dividend; 2293 } 2294 2295 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2296 s8 *pshift, u32 *pmultiplier) 2297 { 2298 uint64_t scaled64; 2299 int32_t shift = 0; 2300 uint64_t tps64; 2301 uint32_t tps32; 2302 2303 tps64 = base_hz; 2304 scaled64 = scaled_hz; 2305 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2306 tps64 >>= 1; 2307 shift--; 2308 } 2309 2310 tps32 = (uint32_t)tps64; 2311 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2312 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2313 scaled64 >>= 1; 2314 else 2315 tps32 <<= 1; 2316 shift++; 2317 } 2318 2319 *pshift = shift; 2320 *pmultiplier = div_frac(scaled64, tps32); 2321 } 2322 2323 #ifdef CONFIG_X86_64 2324 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2325 #endif 2326 2327 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2328 static unsigned long max_tsc_khz; 2329 2330 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2331 { 2332 u64 v = (u64)khz * (1000000 + ppm); 2333 do_div(v, 1000000); 2334 return v; 2335 } 2336 2337 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2338 2339 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2340 { 2341 u64 ratio; 2342 2343 /* Guest TSC same frequency as host TSC? */ 2344 if (!scale) { 2345 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); 2346 return 0; 2347 } 2348 2349 /* TSC scaling supported? */ 2350 if (!kvm_caps.has_tsc_control) { 2351 if (user_tsc_khz > tsc_khz) { 2352 vcpu->arch.tsc_catchup = 1; 2353 vcpu->arch.tsc_always_catchup = 1; 2354 return 0; 2355 } else { 2356 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2357 return -1; 2358 } 2359 } 2360 2361 /* TSC scaling required - calculate ratio */ 2362 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits, 2363 user_tsc_khz, tsc_khz); 2364 2365 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) { 2366 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2367 user_tsc_khz); 2368 return -1; 2369 } 2370 2371 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2372 return 0; 2373 } 2374 2375 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2376 { 2377 u32 thresh_lo, thresh_hi; 2378 int use_scaling = 0; 2379 2380 /* tsc_khz can be zero if TSC calibration fails */ 2381 if (user_tsc_khz == 0) { 2382 /* set tsc_scaling_ratio to a safe value */ 2383 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); 2384 return -1; 2385 } 2386 2387 /* Compute a scale to convert nanoseconds in TSC cycles */ 2388 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2389 &vcpu->arch.virtual_tsc_shift, 2390 &vcpu->arch.virtual_tsc_mult); 2391 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2392 2393 /* 2394 * Compute the variation in TSC rate which is acceptable 2395 * within the range of tolerance and decide if the 2396 * rate being applied is within that bounds of the hardware 2397 * rate. If so, no scaling or compensation need be done. 2398 */ 2399 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2400 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2401 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2402 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2403 use_scaling = 1; 2404 } 2405 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2406 } 2407 2408 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2409 { 2410 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2411 vcpu->arch.virtual_tsc_mult, 2412 vcpu->arch.virtual_tsc_shift); 2413 tsc += vcpu->arch.this_tsc_write; 2414 return tsc; 2415 } 2416 2417 #ifdef CONFIG_X86_64 2418 static inline int gtod_is_based_on_tsc(int mode) 2419 { 2420 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2421 } 2422 #endif 2423 2424 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2425 { 2426 #ifdef CONFIG_X86_64 2427 bool vcpus_matched; 2428 struct kvm_arch *ka = &vcpu->kvm->arch; 2429 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2430 2431 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2432 atomic_read(&vcpu->kvm->online_vcpus)); 2433 2434 /* 2435 * Once the masterclock is enabled, always perform request in 2436 * order to update it. 2437 * 2438 * In order to enable masterclock, the host clocksource must be TSC 2439 * and the vcpus need to have matched TSCs. When that happens, 2440 * perform request to enable masterclock. 2441 */ 2442 if (ka->use_master_clock || 2443 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2444 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2445 2446 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2447 atomic_read(&vcpu->kvm->online_vcpus), 2448 ka->use_master_clock, gtod->clock.vclock_mode); 2449 #endif 2450 } 2451 2452 /* 2453 * Multiply tsc by a fixed point number represented by ratio. 2454 * 2455 * The most significant 64-N bits (mult) of ratio represent the 2456 * integral part of the fixed point number; the remaining N bits 2457 * (frac) represent the fractional part, ie. ratio represents a fixed 2458 * point number (mult + frac * 2^(-N)). 2459 * 2460 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits. 2461 */ 2462 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2463 { 2464 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits); 2465 } 2466 2467 u64 kvm_scale_tsc(u64 tsc, u64 ratio) 2468 { 2469 u64 _tsc = tsc; 2470 2471 if (ratio != kvm_caps.default_tsc_scaling_ratio) 2472 _tsc = __scale_tsc(ratio, tsc); 2473 2474 return _tsc; 2475 } 2476 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2477 2478 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2479 { 2480 u64 tsc; 2481 2482 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2483 2484 return target_tsc - tsc; 2485 } 2486 2487 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2488 { 2489 return vcpu->arch.l1_tsc_offset + 2490 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2491 } 2492 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2493 2494 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2495 { 2496 u64 nested_offset; 2497 2498 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio) 2499 nested_offset = l1_offset; 2500 else 2501 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2502 kvm_caps.tsc_scaling_ratio_frac_bits); 2503 2504 nested_offset += l2_offset; 2505 return nested_offset; 2506 } 2507 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2508 2509 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2510 { 2511 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio) 2512 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2513 kvm_caps.tsc_scaling_ratio_frac_bits); 2514 2515 return l1_multiplier; 2516 } 2517 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2518 2519 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2520 { 2521 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2522 vcpu->arch.l1_tsc_offset, 2523 l1_offset); 2524 2525 vcpu->arch.l1_tsc_offset = l1_offset; 2526 2527 /* 2528 * If we are here because L1 chose not to trap WRMSR to TSC then 2529 * according to the spec this should set L1's TSC (as opposed to 2530 * setting L1's offset for L2). 2531 */ 2532 if (is_guest_mode(vcpu)) 2533 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2534 l1_offset, 2535 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2536 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2537 else 2538 vcpu->arch.tsc_offset = l1_offset; 2539 2540 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2541 } 2542 2543 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2544 { 2545 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2546 2547 /* Userspace is changing the multiplier while L2 is active */ 2548 if (is_guest_mode(vcpu)) 2549 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2550 l1_multiplier, 2551 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2552 else 2553 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2554 2555 if (kvm_caps.has_tsc_control) 2556 static_call(kvm_x86_write_tsc_multiplier)( 2557 vcpu, vcpu->arch.tsc_scaling_ratio); 2558 } 2559 2560 static inline bool kvm_check_tsc_unstable(void) 2561 { 2562 #ifdef CONFIG_X86_64 2563 /* 2564 * TSC is marked unstable when we're running on Hyper-V, 2565 * 'TSC page' clocksource is good. 2566 */ 2567 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2568 return false; 2569 #endif 2570 return check_tsc_unstable(); 2571 } 2572 2573 /* 2574 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2575 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2576 * participates in. 2577 */ 2578 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2579 u64 ns, bool matched) 2580 { 2581 struct kvm *kvm = vcpu->kvm; 2582 2583 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2584 2585 /* 2586 * We also track th most recent recorded KHZ, write and time to 2587 * allow the matching interval to be extended at each write. 2588 */ 2589 kvm->arch.last_tsc_nsec = ns; 2590 kvm->arch.last_tsc_write = tsc; 2591 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2592 kvm->arch.last_tsc_offset = offset; 2593 2594 vcpu->arch.last_guest_tsc = tsc; 2595 2596 kvm_vcpu_write_tsc_offset(vcpu, offset); 2597 2598 if (!matched) { 2599 /* 2600 * We split periods of matched TSC writes into generations. 2601 * For each generation, we track the original measured 2602 * nanosecond time, offset, and write, so if TSCs are in 2603 * sync, we can match exact offset, and if not, we can match 2604 * exact software computation in compute_guest_tsc() 2605 * 2606 * These values are tracked in kvm->arch.cur_xxx variables. 2607 */ 2608 kvm->arch.cur_tsc_generation++; 2609 kvm->arch.cur_tsc_nsec = ns; 2610 kvm->arch.cur_tsc_write = tsc; 2611 kvm->arch.cur_tsc_offset = offset; 2612 kvm->arch.nr_vcpus_matched_tsc = 0; 2613 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2614 kvm->arch.nr_vcpus_matched_tsc++; 2615 } 2616 2617 /* Keep track of which generation this VCPU has synchronized to */ 2618 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2619 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2620 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2621 2622 kvm_track_tsc_matching(vcpu); 2623 } 2624 2625 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2626 { 2627 struct kvm *kvm = vcpu->kvm; 2628 u64 offset, ns, elapsed; 2629 unsigned long flags; 2630 bool matched = false; 2631 bool synchronizing = false; 2632 2633 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2634 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2635 ns = get_kvmclock_base_ns(); 2636 elapsed = ns - kvm->arch.last_tsc_nsec; 2637 2638 if (vcpu->arch.virtual_tsc_khz) { 2639 if (data == 0) { 2640 /* 2641 * detection of vcpu initialization -- need to sync 2642 * with other vCPUs. This particularly helps to keep 2643 * kvm_clock stable after CPU hotplug 2644 */ 2645 synchronizing = true; 2646 } else { 2647 u64 tsc_exp = kvm->arch.last_tsc_write + 2648 nsec_to_cycles(vcpu, elapsed); 2649 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2650 /* 2651 * Special case: TSC write with a small delta (1 second) 2652 * of virtual cycle time against real time is 2653 * interpreted as an attempt to synchronize the CPU. 2654 */ 2655 synchronizing = data < tsc_exp + tsc_hz && 2656 data + tsc_hz > tsc_exp; 2657 } 2658 } 2659 2660 /* 2661 * For a reliable TSC, we can match TSC offsets, and for an unstable 2662 * TSC, we add elapsed time in this computation. We could let the 2663 * compensation code attempt to catch up if we fall behind, but 2664 * it's better to try to match offsets from the beginning. 2665 */ 2666 if (synchronizing && 2667 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2668 if (!kvm_check_tsc_unstable()) { 2669 offset = kvm->arch.cur_tsc_offset; 2670 } else { 2671 u64 delta = nsec_to_cycles(vcpu, elapsed); 2672 data += delta; 2673 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2674 } 2675 matched = true; 2676 } 2677 2678 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2679 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2680 } 2681 2682 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2683 s64 adjustment) 2684 { 2685 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2686 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2687 } 2688 2689 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2690 { 2691 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio) 2692 WARN_ON(adjustment < 0); 2693 adjustment = kvm_scale_tsc((u64) adjustment, 2694 vcpu->arch.l1_tsc_scaling_ratio); 2695 adjust_tsc_offset_guest(vcpu, adjustment); 2696 } 2697 2698 #ifdef CONFIG_X86_64 2699 2700 static u64 read_tsc(void) 2701 { 2702 u64 ret = (u64)rdtsc_ordered(); 2703 u64 last = pvclock_gtod_data.clock.cycle_last; 2704 2705 if (likely(ret >= last)) 2706 return ret; 2707 2708 /* 2709 * GCC likes to generate cmov here, but this branch is extremely 2710 * predictable (it's just a function of time and the likely is 2711 * very likely) and there's a data dependence, so force GCC 2712 * to generate a branch instead. I don't barrier() because 2713 * we don't actually need a barrier, and if this function 2714 * ever gets inlined it will generate worse code. 2715 */ 2716 asm volatile (""); 2717 return last; 2718 } 2719 2720 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2721 int *mode) 2722 { 2723 long v; 2724 u64 tsc_pg_val; 2725 2726 switch (clock->vclock_mode) { 2727 case VDSO_CLOCKMODE_HVCLOCK: 2728 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2729 tsc_timestamp); 2730 if (tsc_pg_val != U64_MAX) { 2731 /* TSC page valid */ 2732 *mode = VDSO_CLOCKMODE_HVCLOCK; 2733 v = (tsc_pg_val - clock->cycle_last) & 2734 clock->mask; 2735 } else { 2736 /* TSC page invalid */ 2737 *mode = VDSO_CLOCKMODE_NONE; 2738 } 2739 break; 2740 case VDSO_CLOCKMODE_TSC: 2741 *mode = VDSO_CLOCKMODE_TSC; 2742 *tsc_timestamp = read_tsc(); 2743 v = (*tsc_timestamp - clock->cycle_last) & 2744 clock->mask; 2745 break; 2746 default: 2747 *mode = VDSO_CLOCKMODE_NONE; 2748 } 2749 2750 if (*mode == VDSO_CLOCKMODE_NONE) 2751 *tsc_timestamp = v = 0; 2752 2753 return v * clock->mult; 2754 } 2755 2756 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2757 { 2758 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2759 unsigned long seq; 2760 int mode; 2761 u64 ns; 2762 2763 do { 2764 seq = read_seqcount_begin(>od->seq); 2765 ns = gtod->raw_clock.base_cycles; 2766 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2767 ns >>= gtod->raw_clock.shift; 2768 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2769 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2770 *t = ns; 2771 2772 return mode; 2773 } 2774 2775 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2776 { 2777 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2778 unsigned long seq; 2779 int mode; 2780 u64 ns; 2781 2782 do { 2783 seq = read_seqcount_begin(>od->seq); 2784 ts->tv_sec = gtod->wall_time_sec; 2785 ns = gtod->clock.base_cycles; 2786 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2787 ns >>= gtod->clock.shift; 2788 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2789 2790 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2791 ts->tv_nsec = ns; 2792 2793 return mode; 2794 } 2795 2796 /* returns true if host is using TSC based clocksource */ 2797 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2798 { 2799 /* checked again under seqlock below */ 2800 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2801 return false; 2802 2803 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2804 tsc_timestamp)); 2805 } 2806 2807 /* returns true if host is using TSC based clocksource */ 2808 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2809 u64 *tsc_timestamp) 2810 { 2811 /* checked again under seqlock below */ 2812 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2813 return false; 2814 2815 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2816 } 2817 #endif 2818 2819 /* 2820 * 2821 * Assuming a stable TSC across physical CPUS, and a stable TSC 2822 * across virtual CPUs, the following condition is possible. 2823 * Each numbered line represents an event visible to both 2824 * CPUs at the next numbered event. 2825 * 2826 * "timespecX" represents host monotonic time. "tscX" represents 2827 * RDTSC value. 2828 * 2829 * VCPU0 on CPU0 | VCPU1 on CPU1 2830 * 2831 * 1. read timespec0,tsc0 2832 * 2. | timespec1 = timespec0 + N 2833 * | tsc1 = tsc0 + M 2834 * 3. transition to guest | transition to guest 2835 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2836 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2837 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2838 * 2839 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2840 * 2841 * - ret0 < ret1 2842 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2843 * ... 2844 * - 0 < N - M => M < N 2845 * 2846 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2847 * always the case (the difference between two distinct xtime instances 2848 * might be smaller then the difference between corresponding TSC reads, 2849 * when updating guest vcpus pvclock areas). 2850 * 2851 * To avoid that problem, do not allow visibility of distinct 2852 * system_timestamp/tsc_timestamp values simultaneously: use a master 2853 * copy of host monotonic time values. Update that master copy 2854 * in lockstep. 2855 * 2856 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2857 * 2858 */ 2859 2860 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2861 { 2862 #ifdef CONFIG_X86_64 2863 struct kvm_arch *ka = &kvm->arch; 2864 int vclock_mode; 2865 bool host_tsc_clocksource, vcpus_matched; 2866 2867 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2868 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2869 atomic_read(&kvm->online_vcpus)); 2870 2871 /* 2872 * If the host uses TSC clock, then passthrough TSC as stable 2873 * to the guest. 2874 */ 2875 host_tsc_clocksource = kvm_get_time_and_clockread( 2876 &ka->master_kernel_ns, 2877 &ka->master_cycle_now); 2878 2879 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2880 && !ka->backwards_tsc_observed 2881 && !ka->boot_vcpu_runs_old_kvmclock; 2882 2883 if (ka->use_master_clock) 2884 atomic_set(&kvm_guest_has_master_clock, 1); 2885 2886 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2887 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2888 vcpus_matched); 2889 #endif 2890 } 2891 2892 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2893 { 2894 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2895 } 2896 2897 static void __kvm_start_pvclock_update(struct kvm *kvm) 2898 { 2899 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 2900 write_seqcount_begin(&kvm->arch.pvclock_sc); 2901 } 2902 2903 static void kvm_start_pvclock_update(struct kvm *kvm) 2904 { 2905 kvm_make_mclock_inprogress_request(kvm); 2906 2907 /* no guest entries from this point */ 2908 __kvm_start_pvclock_update(kvm); 2909 } 2910 2911 static void kvm_end_pvclock_update(struct kvm *kvm) 2912 { 2913 struct kvm_arch *ka = &kvm->arch; 2914 struct kvm_vcpu *vcpu; 2915 unsigned long i; 2916 2917 write_seqcount_end(&ka->pvclock_sc); 2918 raw_spin_unlock_irq(&ka->tsc_write_lock); 2919 kvm_for_each_vcpu(i, vcpu, kvm) 2920 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2921 2922 /* guest entries allowed */ 2923 kvm_for_each_vcpu(i, vcpu, kvm) 2924 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2925 } 2926 2927 static void kvm_update_masterclock(struct kvm *kvm) 2928 { 2929 kvm_hv_request_tsc_page_update(kvm); 2930 kvm_start_pvclock_update(kvm); 2931 pvclock_update_vm_gtod_copy(kvm); 2932 kvm_end_pvclock_update(kvm); 2933 } 2934 2935 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 2936 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2937 { 2938 struct kvm_arch *ka = &kvm->arch; 2939 struct pvclock_vcpu_time_info hv_clock; 2940 2941 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2942 get_cpu(); 2943 2944 data->flags = 0; 2945 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { 2946 #ifdef CONFIG_X86_64 2947 struct timespec64 ts; 2948 2949 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 2950 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 2951 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 2952 } else 2953 #endif 2954 data->host_tsc = rdtsc(); 2955 2956 data->flags |= KVM_CLOCK_TSC_STABLE; 2957 hv_clock.tsc_timestamp = ka->master_cycle_now; 2958 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2959 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2960 &hv_clock.tsc_shift, 2961 &hv_clock.tsc_to_system_mul); 2962 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 2963 } else { 2964 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 2965 } 2966 2967 put_cpu(); 2968 } 2969 2970 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2971 { 2972 struct kvm_arch *ka = &kvm->arch; 2973 unsigned seq; 2974 2975 do { 2976 seq = read_seqcount_begin(&ka->pvclock_sc); 2977 __get_kvmclock(kvm, data); 2978 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 2979 } 2980 2981 u64 get_kvmclock_ns(struct kvm *kvm) 2982 { 2983 struct kvm_clock_data data; 2984 2985 get_kvmclock(kvm, &data); 2986 return data.clock; 2987 } 2988 2989 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v, 2990 struct gfn_to_pfn_cache *gpc, 2991 unsigned int offset) 2992 { 2993 struct kvm_vcpu_arch *vcpu = &v->arch; 2994 struct pvclock_vcpu_time_info *guest_hv_clock; 2995 unsigned long flags; 2996 2997 read_lock_irqsave(&gpc->lock, flags); 2998 while (!kvm_gfn_to_pfn_cache_check(v->kvm, gpc, gpc->gpa, 2999 offset + sizeof(*guest_hv_clock))) { 3000 read_unlock_irqrestore(&gpc->lock, flags); 3001 3002 if (kvm_gfn_to_pfn_cache_refresh(v->kvm, gpc, gpc->gpa, 3003 offset + sizeof(*guest_hv_clock))) 3004 return; 3005 3006 read_lock_irqsave(&gpc->lock, flags); 3007 } 3008 3009 guest_hv_clock = (void *)(gpc->khva + offset); 3010 3011 /* 3012 * This VCPU is paused, but it's legal for a guest to read another 3013 * VCPU's kvmclock, so we really have to follow the specification where 3014 * it says that version is odd if data is being modified, and even after 3015 * it is consistent. 3016 */ 3017 3018 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1; 3019 smp_wmb(); 3020 3021 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 3022 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED); 3023 3024 if (vcpu->pvclock_set_guest_stopped_request) { 3025 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 3026 vcpu->pvclock_set_guest_stopped_request = false; 3027 } 3028 3029 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock)); 3030 smp_wmb(); 3031 3032 guest_hv_clock->version = ++vcpu->hv_clock.version; 3033 3034 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT); 3035 read_unlock_irqrestore(&gpc->lock, flags); 3036 3037 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 3038 } 3039 3040 static int kvm_guest_time_update(struct kvm_vcpu *v) 3041 { 3042 unsigned long flags, tgt_tsc_khz; 3043 unsigned seq; 3044 struct kvm_vcpu_arch *vcpu = &v->arch; 3045 struct kvm_arch *ka = &v->kvm->arch; 3046 s64 kernel_ns; 3047 u64 tsc_timestamp, host_tsc; 3048 u8 pvclock_flags; 3049 bool use_master_clock; 3050 3051 kernel_ns = 0; 3052 host_tsc = 0; 3053 3054 /* 3055 * If the host uses TSC clock, then passthrough TSC as stable 3056 * to the guest. 3057 */ 3058 do { 3059 seq = read_seqcount_begin(&ka->pvclock_sc); 3060 use_master_clock = ka->use_master_clock; 3061 if (use_master_clock) { 3062 host_tsc = ka->master_cycle_now; 3063 kernel_ns = ka->master_kernel_ns; 3064 } 3065 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3066 3067 /* Keep irq disabled to prevent changes to the clock */ 3068 local_irq_save(flags); 3069 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 3070 if (unlikely(tgt_tsc_khz == 0)) { 3071 local_irq_restore(flags); 3072 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3073 return 1; 3074 } 3075 if (!use_master_clock) { 3076 host_tsc = rdtsc(); 3077 kernel_ns = get_kvmclock_base_ns(); 3078 } 3079 3080 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 3081 3082 /* 3083 * We may have to catch up the TSC to match elapsed wall clock 3084 * time for two reasons, even if kvmclock is used. 3085 * 1) CPU could have been running below the maximum TSC rate 3086 * 2) Broken TSC compensation resets the base at each VCPU 3087 * entry to avoid unknown leaps of TSC even when running 3088 * again on the same CPU. This may cause apparent elapsed 3089 * time to disappear, and the guest to stand still or run 3090 * very slowly. 3091 */ 3092 if (vcpu->tsc_catchup) { 3093 u64 tsc = compute_guest_tsc(v, kernel_ns); 3094 if (tsc > tsc_timestamp) { 3095 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3096 tsc_timestamp = tsc; 3097 } 3098 } 3099 3100 local_irq_restore(flags); 3101 3102 /* With all the info we got, fill in the values */ 3103 3104 if (kvm_caps.has_tsc_control) 3105 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, 3106 v->arch.l1_tsc_scaling_ratio); 3107 3108 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3109 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3110 &vcpu->hv_clock.tsc_shift, 3111 &vcpu->hv_clock.tsc_to_system_mul); 3112 vcpu->hw_tsc_khz = tgt_tsc_khz; 3113 } 3114 3115 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3116 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3117 vcpu->last_guest_tsc = tsc_timestamp; 3118 3119 /* If the host uses TSC clocksource, then it is stable */ 3120 pvclock_flags = 0; 3121 if (use_master_clock) 3122 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3123 3124 vcpu->hv_clock.flags = pvclock_flags; 3125 3126 if (vcpu->pv_time.active) 3127 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0); 3128 if (vcpu->xen.vcpu_info_cache.active) 3129 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache, 3130 offsetof(struct compat_vcpu_info, time)); 3131 if (vcpu->xen.vcpu_time_info_cache.active) 3132 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0); 3133 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3134 return 0; 3135 } 3136 3137 /* 3138 * kvmclock updates which are isolated to a given vcpu, such as 3139 * vcpu->cpu migration, should not allow system_timestamp from 3140 * the rest of the vcpus to remain static. Otherwise ntp frequency 3141 * correction applies to one vcpu's system_timestamp but not 3142 * the others. 3143 * 3144 * So in those cases, request a kvmclock update for all vcpus. 3145 * We need to rate-limit these requests though, as they can 3146 * considerably slow guests that have a large number of vcpus. 3147 * The time for a remote vcpu to update its kvmclock is bound 3148 * by the delay we use to rate-limit the updates. 3149 */ 3150 3151 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3152 3153 static void kvmclock_update_fn(struct work_struct *work) 3154 { 3155 unsigned long i; 3156 struct delayed_work *dwork = to_delayed_work(work); 3157 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3158 kvmclock_update_work); 3159 struct kvm *kvm = container_of(ka, struct kvm, arch); 3160 struct kvm_vcpu *vcpu; 3161 3162 kvm_for_each_vcpu(i, vcpu, kvm) { 3163 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3164 kvm_vcpu_kick(vcpu); 3165 } 3166 } 3167 3168 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3169 { 3170 struct kvm *kvm = v->kvm; 3171 3172 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3173 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3174 KVMCLOCK_UPDATE_DELAY); 3175 } 3176 3177 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3178 3179 static void kvmclock_sync_fn(struct work_struct *work) 3180 { 3181 struct delayed_work *dwork = to_delayed_work(work); 3182 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3183 kvmclock_sync_work); 3184 struct kvm *kvm = container_of(ka, struct kvm, arch); 3185 3186 if (!kvmclock_periodic_sync) 3187 return; 3188 3189 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3190 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3191 KVMCLOCK_SYNC_PERIOD); 3192 } 3193 3194 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */ 3195 static bool is_mci_control_msr(u32 msr) 3196 { 3197 return (msr & 3) == 0; 3198 } 3199 static bool is_mci_status_msr(u32 msr) 3200 { 3201 return (msr & 3) == 1; 3202 } 3203 3204 /* 3205 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3206 */ 3207 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3208 { 3209 /* McStatusWrEn enabled? */ 3210 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3211 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3212 3213 return false; 3214 } 3215 3216 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3217 { 3218 u64 mcg_cap = vcpu->arch.mcg_cap; 3219 unsigned bank_num = mcg_cap & 0xff; 3220 u32 msr = msr_info->index; 3221 u64 data = msr_info->data; 3222 u32 offset, last_msr; 3223 3224 switch (msr) { 3225 case MSR_IA32_MCG_STATUS: 3226 vcpu->arch.mcg_status = data; 3227 break; 3228 case MSR_IA32_MCG_CTL: 3229 if (!(mcg_cap & MCG_CTL_P) && 3230 (data || !msr_info->host_initiated)) 3231 return 1; 3232 if (data != 0 && data != ~(u64)0) 3233 return 1; 3234 vcpu->arch.mcg_ctl = data; 3235 break; 3236 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3237 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; 3238 if (msr > last_msr) 3239 return 1; 3240 3241 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated)) 3242 return 1; 3243 /* An attempt to write a 1 to a reserved bit raises #GP */ 3244 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK)) 3245 return 1; 3246 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, 3247 last_msr + 1 - MSR_IA32_MC0_CTL2); 3248 vcpu->arch.mci_ctl2_banks[offset] = data; 3249 break; 3250 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3251 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; 3252 if (msr > last_msr) 3253 return 1; 3254 3255 /* 3256 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other 3257 * values are architecturally undefined. But, some Linux 3258 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB 3259 * issue on AMD K8s, allow bit 10 to be clear when setting all 3260 * other bits in order to avoid an uncaught #GP in the guest. 3261 * 3262 * UNIXWARE clears bit 0 of MC1_CTL to ignore 3263 * correctable, single-bit ECC data errors. 3264 */ 3265 if (is_mci_control_msr(msr) && 3266 data != 0 && (data | (1 << 10) | 1) != ~(u64)0) 3267 return 1; 3268 3269 /* 3270 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR. 3271 * AMD-based CPUs allow non-zero values, but if and only if 3272 * HWCR[McStatusWrEn] is set. 3273 */ 3274 if (!msr_info->host_initiated && is_mci_status_msr(msr) && 3275 data != 0 && !can_set_mci_status(vcpu)) 3276 return 1; 3277 3278 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, 3279 last_msr + 1 - MSR_IA32_MC0_CTL); 3280 vcpu->arch.mce_banks[offset] = data; 3281 break; 3282 default: 3283 return 1; 3284 } 3285 return 0; 3286 } 3287 3288 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3289 { 3290 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3291 3292 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3293 } 3294 3295 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3296 { 3297 gpa_t gpa = data & ~0x3f; 3298 3299 /* Bits 4:5 are reserved, Should be zero */ 3300 if (data & 0x30) 3301 return 1; 3302 3303 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3304 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3305 return 1; 3306 3307 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3308 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3309 return 1; 3310 3311 if (!lapic_in_kernel(vcpu)) 3312 return data ? 1 : 0; 3313 3314 vcpu->arch.apf.msr_en_val = data; 3315 3316 if (!kvm_pv_async_pf_enabled(vcpu)) { 3317 kvm_clear_async_pf_completion_queue(vcpu); 3318 kvm_async_pf_hash_reset(vcpu); 3319 return 0; 3320 } 3321 3322 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3323 sizeof(u64))) 3324 return 1; 3325 3326 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3327 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3328 3329 kvm_async_pf_wakeup_all(vcpu); 3330 3331 return 0; 3332 } 3333 3334 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3335 { 3336 /* Bits 8-63 are reserved */ 3337 if (data >> 8) 3338 return 1; 3339 3340 if (!lapic_in_kernel(vcpu)) 3341 return 1; 3342 3343 vcpu->arch.apf.msr_int_val = data; 3344 3345 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3346 3347 return 0; 3348 } 3349 3350 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3351 { 3352 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time); 3353 vcpu->arch.time = 0; 3354 } 3355 3356 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3357 { 3358 ++vcpu->stat.tlb_flush; 3359 static_call(kvm_x86_flush_tlb_all)(vcpu); 3360 } 3361 3362 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3363 { 3364 ++vcpu->stat.tlb_flush; 3365 3366 if (!tdp_enabled) { 3367 /* 3368 * A TLB flush on behalf of the guest is equivalent to 3369 * INVPCID(all), toggling CR4.PGE, etc., which requires 3370 * a forced sync of the shadow page tables. Ensure all the 3371 * roots are synced and the guest TLB in hardware is clean. 3372 */ 3373 kvm_mmu_sync_roots(vcpu); 3374 kvm_mmu_sync_prev_roots(vcpu); 3375 } 3376 3377 static_call(kvm_x86_flush_tlb_guest)(vcpu); 3378 } 3379 3380 3381 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 3382 { 3383 ++vcpu->stat.tlb_flush; 3384 static_call(kvm_x86_flush_tlb_current)(vcpu); 3385 } 3386 3387 /* 3388 * Service "local" TLB flush requests, which are specific to the current MMU 3389 * context. In addition to the generic event handling in vcpu_enter_guest(), 3390 * TLB flushes that are targeted at an MMU context also need to be serviced 3391 * prior before nested VM-Enter/VM-Exit. 3392 */ 3393 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) 3394 { 3395 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3396 kvm_vcpu_flush_tlb_current(vcpu); 3397 3398 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 3399 kvm_vcpu_flush_tlb_guest(vcpu); 3400 } 3401 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); 3402 3403 static void record_steal_time(struct kvm_vcpu *vcpu) 3404 { 3405 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3406 struct kvm_steal_time __user *st; 3407 struct kvm_memslots *slots; 3408 u64 steal; 3409 u32 version; 3410 3411 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3412 kvm_xen_runstate_set_running(vcpu); 3413 return; 3414 } 3415 3416 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3417 return; 3418 3419 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3420 return; 3421 3422 slots = kvm_memslots(vcpu->kvm); 3423 3424 if (unlikely(slots->generation != ghc->generation || 3425 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3426 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3427 3428 /* We rely on the fact that it fits in a single page. */ 3429 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3430 3431 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) || 3432 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3433 return; 3434 } 3435 3436 st = (struct kvm_steal_time __user *)ghc->hva; 3437 /* 3438 * Doing a TLB flush here, on the guest's behalf, can avoid 3439 * expensive IPIs. 3440 */ 3441 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3442 u8 st_preempted = 0; 3443 int err = -EFAULT; 3444 3445 if (!user_access_begin(st, sizeof(*st))) 3446 return; 3447 3448 asm volatile("1: xchgb %0, %2\n" 3449 "xor %1, %1\n" 3450 "2:\n" 3451 _ASM_EXTABLE_UA(1b, 2b) 3452 : "+q" (st_preempted), 3453 "+&r" (err), 3454 "+m" (st->preempted)); 3455 if (err) 3456 goto out; 3457 3458 user_access_end(); 3459 3460 vcpu->arch.st.preempted = 0; 3461 3462 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3463 st_preempted & KVM_VCPU_FLUSH_TLB); 3464 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3465 kvm_vcpu_flush_tlb_guest(vcpu); 3466 3467 if (!user_access_begin(st, sizeof(*st))) 3468 goto dirty; 3469 } else { 3470 if (!user_access_begin(st, sizeof(*st))) 3471 return; 3472 3473 unsafe_put_user(0, &st->preempted, out); 3474 vcpu->arch.st.preempted = 0; 3475 } 3476 3477 unsafe_get_user(version, &st->version, out); 3478 if (version & 1) 3479 version += 1; /* first time write, random junk */ 3480 3481 version += 1; 3482 unsafe_put_user(version, &st->version, out); 3483 3484 smp_wmb(); 3485 3486 unsafe_get_user(steal, &st->steal, out); 3487 steal += current->sched_info.run_delay - 3488 vcpu->arch.st.last_steal; 3489 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3490 unsafe_put_user(steal, &st->steal, out); 3491 3492 version += 1; 3493 unsafe_put_user(version, &st->version, out); 3494 3495 out: 3496 user_access_end(); 3497 dirty: 3498 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3499 } 3500 3501 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3502 { 3503 bool pr = false; 3504 u32 msr = msr_info->index; 3505 u64 data = msr_info->data; 3506 3507 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3508 return kvm_xen_write_hypercall_page(vcpu, data); 3509 3510 switch (msr) { 3511 case MSR_AMD64_NB_CFG: 3512 case MSR_IA32_UCODE_WRITE: 3513 case MSR_VM_HSAVE_PA: 3514 case MSR_AMD64_PATCH_LOADER: 3515 case MSR_AMD64_BU_CFG2: 3516 case MSR_AMD64_DC_CFG: 3517 case MSR_F15H_EX_CFG: 3518 break; 3519 3520 case MSR_IA32_UCODE_REV: 3521 if (msr_info->host_initiated) 3522 vcpu->arch.microcode_version = data; 3523 break; 3524 case MSR_IA32_ARCH_CAPABILITIES: 3525 if (!msr_info->host_initiated) 3526 return 1; 3527 vcpu->arch.arch_capabilities = data; 3528 break; 3529 case MSR_IA32_PERF_CAPABILITIES: { 3530 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3531 3532 if (!msr_info->host_initiated) 3533 return 1; 3534 if (kvm_get_msr_feature(&msr_ent)) 3535 return 1; 3536 if (data & ~msr_ent.data) 3537 return 1; 3538 3539 vcpu->arch.perf_capabilities = data; 3540 3541 return 0; 3542 } 3543 case MSR_EFER: 3544 return set_efer(vcpu, msr_info); 3545 case MSR_K7_HWCR: 3546 data &= ~(u64)0x40; /* ignore flush filter disable */ 3547 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3548 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3549 3550 /* Handle McStatusWrEn */ 3551 if (data == BIT_ULL(18)) { 3552 vcpu->arch.msr_hwcr = data; 3553 } else if (data != 0) { 3554 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3555 data); 3556 return 1; 3557 } 3558 break; 3559 case MSR_FAM10H_MMIO_CONF_BASE: 3560 if (data != 0) { 3561 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3562 "0x%llx\n", data); 3563 return 1; 3564 } 3565 break; 3566 case 0x200 ... MSR_IA32_MC0_CTL2 - 1: 3567 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff: 3568 return kvm_mtrr_set_msr(vcpu, msr, data); 3569 case MSR_IA32_APICBASE: 3570 return kvm_set_apic_base(vcpu, msr_info); 3571 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3572 return kvm_x2apic_msr_write(vcpu, msr, data); 3573 case MSR_IA32_TSC_DEADLINE: 3574 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3575 break; 3576 case MSR_IA32_TSC_ADJUST: 3577 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3578 if (!msr_info->host_initiated) { 3579 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3580 adjust_tsc_offset_guest(vcpu, adj); 3581 /* Before back to guest, tsc_timestamp must be adjusted 3582 * as well, otherwise guest's percpu pvclock time could jump. 3583 */ 3584 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3585 } 3586 vcpu->arch.ia32_tsc_adjust_msr = data; 3587 } 3588 break; 3589 case MSR_IA32_MISC_ENABLE: { 3590 u64 old_val = vcpu->arch.ia32_misc_enable_msr; 3591 3592 if (!msr_info->host_initiated) { 3593 /* RO bits */ 3594 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK) 3595 return 1; 3596 3597 /* R bits, i.e. writes are ignored, but don't fault. */ 3598 data = data & ~MSR_IA32_MISC_ENABLE_EMON; 3599 data |= old_val & MSR_IA32_MISC_ENABLE_EMON; 3600 } 3601 3602 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3603 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3604 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3605 return 1; 3606 vcpu->arch.ia32_misc_enable_msr = data; 3607 kvm_update_cpuid_runtime(vcpu); 3608 } else { 3609 vcpu->arch.ia32_misc_enable_msr = data; 3610 } 3611 break; 3612 } 3613 case MSR_IA32_SMBASE: 3614 if (!msr_info->host_initiated) 3615 return 1; 3616 vcpu->arch.smbase = data; 3617 break; 3618 case MSR_IA32_POWER_CTL: 3619 vcpu->arch.msr_ia32_power_ctl = data; 3620 break; 3621 case MSR_IA32_TSC: 3622 if (msr_info->host_initiated) { 3623 kvm_synchronize_tsc(vcpu, data); 3624 } else { 3625 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3626 adjust_tsc_offset_guest(vcpu, adj); 3627 vcpu->arch.ia32_tsc_adjust_msr += adj; 3628 } 3629 break; 3630 case MSR_IA32_XSS: 3631 if (!msr_info->host_initiated && 3632 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3633 return 1; 3634 /* 3635 * KVM supports exposing PT to the guest, but does not support 3636 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3637 * XSAVES/XRSTORS to save/restore PT MSRs. 3638 */ 3639 if (data & ~kvm_caps.supported_xss) 3640 return 1; 3641 vcpu->arch.ia32_xss = data; 3642 kvm_update_cpuid_runtime(vcpu); 3643 break; 3644 case MSR_SMI_COUNT: 3645 if (!msr_info->host_initiated) 3646 return 1; 3647 vcpu->arch.smi_count = data; 3648 break; 3649 case MSR_KVM_WALL_CLOCK_NEW: 3650 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3651 return 1; 3652 3653 vcpu->kvm->arch.wall_clock = data; 3654 kvm_write_wall_clock(vcpu->kvm, data, 0); 3655 break; 3656 case MSR_KVM_WALL_CLOCK: 3657 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3658 return 1; 3659 3660 vcpu->kvm->arch.wall_clock = data; 3661 kvm_write_wall_clock(vcpu->kvm, data, 0); 3662 break; 3663 case MSR_KVM_SYSTEM_TIME_NEW: 3664 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3665 return 1; 3666 3667 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3668 break; 3669 case MSR_KVM_SYSTEM_TIME: 3670 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3671 return 1; 3672 3673 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3674 break; 3675 case MSR_KVM_ASYNC_PF_EN: 3676 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3677 return 1; 3678 3679 if (kvm_pv_enable_async_pf(vcpu, data)) 3680 return 1; 3681 break; 3682 case MSR_KVM_ASYNC_PF_INT: 3683 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3684 return 1; 3685 3686 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3687 return 1; 3688 break; 3689 case MSR_KVM_ASYNC_PF_ACK: 3690 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3691 return 1; 3692 if (data & 0x1) { 3693 vcpu->arch.apf.pageready_pending = false; 3694 kvm_check_async_pf_completion(vcpu); 3695 } 3696 break; 3697 case MSR_KVM_STEAL_TIME: 3698 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3699 return 1; 3700 3701 if (unlikely(!sched_info_on())) 3702 return 1; 3703 3704 if (data & KVM_STEAL_RESERVED_MASK) 3705 return 1; 3706 3707 vcpu->arch.st.msr_val = data; 3708 3709 if (!(data & KVM_MSR_ENABLED)) 3710 break; 3711 3712 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3713 3714 break; 3715 case MSR_KVM_PV_EOI_EN: 3716 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3717 return 1; 3718 3719 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 3720 return 1; 3721 break; 3722 3723 case MSR_KVM_POLL_CONTROL: 3724 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3725 return 1; 3726 3727 /* only enable bit supported */ 3728 if (data & (-1ULL << 1)) 3729 return 1; 3730 3731 vcpu->arch.msr_kvm_poll_control = data; 3732 break; 3733 3734 case MSR_IA32_MCG_CTL: 3735 case MSR_IA32_MCG_STATUS: 3736 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3737 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3738 return set_msr_mce(vcpu, msr_info); 3739 3740 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3741 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3742 pr = true; 3743 fallthrough; 3744 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3745 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3746 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3747 return kvm_pmu_set_msr(vcpu, msr_info); 3748 3749 if (pr || data != 0) 3750 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3751 "0x%x data 0x%llx\n", msr, data); 3752 break; 3753 case MSR_K7_CLK_CTL: 3754 /* 3755 * Ignore all writes to this no longer documented MSR. 3756 * Writes are only relevant for old K7 processors, 3757 * all pre-dating SVM, but a recommended workaround from 3758 * AMD for these chips. It is possible to specify the 3759 * affected processor models on the command line, hence 3760 * the need to ignore the workaround. 3761 */ 3762 break; 3763 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3764 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3765 case HV_X64_MSR_SYNDBG_OPTIONS: 3766 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3767 case HV_X64_MSR_CRASH_CTL: 3768 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3769 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3770 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3771 case HV_X64_MSR_TSC_EMULATION_STATUS: 3772 return kvm_hv_set_msr_common(vcpu, msr, data, 3773 msr_info->host_initiated); 3774 case MSR_IA32_BBL_CR_CTL3: 3775 /* Drop writes to this legacy MSR -- see rdmsr 3776 * counterpart for further detail. 3777 */ 3778 if (report_ignored_msrs) 3779 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3780 msr, data); 3781 break; 3782 case MSR_AMD64_OSVW_ID_LENGTH: 3783 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3784 return 1; 3785 vcpu->arch.osvw.length = data; 3786 break; 3787 case MSR_AMD64_OSVW_STATUS: 3788 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3789 return 1; 3790 vcpu->arch.osvw.status = data; 3791 break; 3792 case MSR_PLATFORM_INFO: 3793 if (!msr_info->host_initiated || 3794 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3795 cpuid_fault_enabled(vcpu))) 3796 return 1; 3797 vcpu->arch.msr_platform_info = data; 3798 break; 3799 case MSR_MISC_FEATURES_ENABLES: 3800 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3801 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3802 !supports_cpuid_fault(vcpu))) 3803 return 1; 3804 vcpu->arch.msr_misc_features_enables = data; 3805 break; 3806 #ifdef CONFIG_X86_64 3807 case MSR_IA32_XFD: 3808 if (!msr_info->host_initiated && 3809 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3810 return 1; 3811 3812 if (data & ~kvm_guest_supported_xfd(vcpu)) 3813 return 1; 3814 3815 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); 3816 break; 3817 case MSR_IA32_XFD_ERR: 3818 if (!msr_info->host_initiated && 3819 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3820 return 1; 3821 3822 if (data & ~kvm_guest_supported_xfd(vcpu)) 3823 return 1; 3824 3825 vcpu->arch.guest_fpu.xfd_err = data; 3826 break; 3827 #endif 3828 case MSR_IA32_PEBS_ENABLE: 3829 case MSR_IA32_DS_AREA: 3830 case MSR_PEBS_DATA_CFG: 3831 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3832 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3833 return kvm_pmu_set_msr(vcpu, msr_info); 3834 /* 3835 * Userspace is allowed to write '0' to MSRs that KVM reports 3836 * as to-be-saved, even if an MSRs isn't fully supported. 3837 */ 3838 return !msr_info->host_initiated || data; 3839 default: 3840 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3841 return kvm_pmu_set_msr(vcpu, msr_info); 3842 return KVM_MSR_RET_INVALID; 3843 } 3844 return 0; 3845 } 3846 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3847 3848 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3849 { 3850 u64 data; 3851 u64 mcg_cap = vcpu->arch.mcg_cap; 3852 unsigned bank_num = mcg_cap & 0xff; 3853 u32 offset, last_msr; 3854 3855 switch (msr) { 3856 case MSR_IA32_P5_MC_ADDR: 3857 case MSR_IA32_P5_MC_TYPE: 3858 data = 0; 3859 break; 3860 case MSR_IA32_MCG_CAP: 3861 data = vcpu->arch.mcg_cap; 3862 break; 3863 case MSR_IA32_MCG_CTL: 3864 if (!(mcg_cap & MCG_CTL_P) && !host) 3865 return 1; 3866 data = vcpu->arch.mcg_ctl; 3867 break; 3868 case MSR_IA32_MCG_STATUS: 3869 data = vcpu->arch.mcg_status; 3870 break; 3871 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3872 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; 3873 if (msr > last_msr) 3874 return 1; 3875 3876 if (!(mcg_cap & MCG_CMCI_P) && !host) 3877 return 1; 3878 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, 3879 last_msr + 1 - MSR_IA32_MC0_CTL2); 3880 data = vcpu->arch.mci_ctl2_banks[offset]; 3881 break; 3882 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3883 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; 3884 if (msr > last_msr) 3885 return 1; 3886 3887 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, 3888 last_msr + 1 - MSR_IA32_MC0_CTL); 3889 data = vcpu->arch.mce_banks[offset]; 3890 break; 3891 default: 3892 return 1; 3893 } 3894 *pdata = data; 3895 return 0; 3896 } 3897 3898 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3899 { 3900 switch (msr_info->index) { 3901 case MSR_IA32_PLATFORM_ID: 3902 case MSR_IA32_EBL_CR_POWERON: 3903 case MSR_IA32_LASTBRANCHFROMIP: 3904 case MSR_IA32_LASTBRANCHTOIP: 3905 case MSR_IA32_LASTINTFROMIP: 3906 case MSR_IA32_LASTINTTOIP: 3907 case MSR_AMD64_SYSCFG: 3908 case MSR_K8_TSEG_ADDR: 3909 case MSR_K8_TSEG_MASK: 3910 case MSR_VM_HSAVE_PA: 3911 case MSR_K8_INT_PENDING_MSG: 3912 case MSR_AMD64_NB_CFG: 3913 case MSR_FAM10H_MMIO_CONF_BASE: 3914 case MSR_AMD64_BU_CFG2: 3915 case MSR_IA32_PERF_CTL: 3916 case MSR_AMD64_DC_CFG: 3917 case MSR_F15H_EX_CFG: 3918 /* 3919 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3920 * limit) MSRs. Just return 0, as we do not want to expose the host 3921 * data here. Do not conditionalize this on CPUID, as KVM does not do 3922 * so for existing CPU-specific MSRs. 3923 */ 3924 case MSR_RAPL_POWER_UNIT: 3925 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3926 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3927 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3928 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3929 msr_info->data = 0; 3930 break; 3931 case MSR_IA32_PEBS_ENABLE: 3932 case MSR_IA32_DS_AREA: 3933 case MSR_PEBS_DATA_CFG: 3934 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3935 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3936 return kvm_pmu_get_msr(vcpu, msr_info); 3937 /* 3938 * Userspace is allowed to read MSRs that KVM reports as 3939 * to-be-saved, even if an MSR isn't fully supported. 3940 */ 3941 if (!msr_info->host_initiated) 3942 return 1; 3943 msr_info->data = 0; 3944 break; 3945 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3946 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3947 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3948 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3949 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3950 return kvm_pmu_get_msr(vcpu, msr_info); 3951 msr_info->data = 0; 3952 break; 3953 case MSR_IA32_UCODE_REV: 3954 msr_info->data = vcpu->arch.microcode_version; 3955 break; 3956 case MSR_IA32_ARCH_CAPABILITIES: 3957 if (!msr_info->host_initiated && 3958 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3959 return 1; 3960 msr_info->data = vcpu->arch.arch_capabilities; 3961 break; 3962 case MSR_IA32_PERF_CAPABILITIES: 3963 if (!msr_info->host_initiated && 3964 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3965 return 1; 3966 msr_info->data = vcpu->arch.perf_capabilities; 3967 break; 3968 case MSR_IA32_POWER_CTL: 3969 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3970 break; 3971 case MSR_IA32_TSC: { 3972 /* 3973 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3974 * even when not intercepted. AMD manual doesn't explicitly 3975 * state this but appears to behave the same. 3976 * 3977 * On userspace reads and writes, however, we unconditionally 3978 * return L1's TSC value to ensure backwards-compatible 3979 * behavior for migration. 3980 */ 3981 u64 offset, ratio; 3982 3983 if (msr_info->host_initiated) { 3984 offset = vcpu->arch.l1_tsc_offset; 3985 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3986 } else { 3987 offset = vcpu->arch.tsc_offset; 3988 ratio = vcpu->arch.tsc_scaling_ratio; 3989 } 3990 3991 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; 3992 break; 3993 } 3994 case MSR_MTRRcap: 3995 case 0x200 ... MSR_IA32_MC0_CTL2 - 1: 3996 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff: 3997 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3998 case 0xcd: /* fsb frequency */ 3999 msr_info->data = 3; 4000 break; 4001 /* 4002 * MSR_EBC_FREQUENCY_ID 4003 * Conservative value valid for even the basic CPU models. 4004 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 4005 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 4006 * and 266MHz for model 3, or 4. Set Core Clock 4007 * Frequency to System Bus Frequency Ratio to 1 (bits 4008 * 31:24) even though these are only valid for CPU 4009 * models > 2, however guests may end up dividing or 4010 * multiplying by zero otherwise. 4011 */ 4012 case MSR_EBC_FREQUENCY_ID: 4013 msr_info->data = 1 << 24; 4014 break; 4015 case MSR_IA32_APICBASE: 4016 msr_info->data = kvm_get_apic_base(vcpu); 4017 break; 4018 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 4019 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 4020 case MSR_IA32_TSC_DEADLINE: 4021 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 4022 break; 4023 case MSR_IA32_TSC_ADJUST: 4024 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 4025 break; 4026 case MSR_IA32_MISC_ENABLE: 4027 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 4028 break; 4029 case MSR_IA32_SMBASE: 4030 if (!msr_info->host_initiated) 4031 return 1; 4032 msr_info->data = vcpu->arch.smbase; 4033 break; 4034 case MSR_SMI_COUNT: 4035 msr_info->data = vcpu->arch.smi_count; 4036 break; 4037 case MSR_IA32_PERF_STATUS: 4038 /* TSC increment by tick */ 4039 msr_info->data = 1000ULL; 4040 /* CPU multiplier */ 4041 msr_info->data |= (((uint64_t)4ULL) << 40); 4042 break; 4043 case MSR_EFER: 4044 msr_info->data = vcpu->arch.efer; 4045 break; 4046 case MSR_KVM_WALL_CLOCK: 4047 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 4048 return 1; 4049 4050 msr_info->data = vcpu->kvm->arch.wall_clock; 4051 break; 4052 case MSR_KVM_WALL_CLOCK_NEW: 4053 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 4054 return 1; 4055 4056 msr_info->data = vcpu->kvm->arch.wall_clock; 4057 break; 4058 case MSR_KVM_SYSTEM_TIME: 4059 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 4060 return 1; 4061 4062 msr_info->data = vcpu->arch.time; 4063 break; 4064 case MSR_KVM_SYSTEM_TIME_NEW: 4065 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 4066 return 1; 4067 4068 msr_info->data = vcpu->arch.time; 4069 break; 4070 case MSR_KVM_ASYNC_PF_EN: 4071 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 4072 return 1; 4073 4074 msr_info->data = vcpu->arch.apf.msr_en_val; 4075 break; 4076 case MSR_KVM_ASYNC_PF_INT: 4077 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4078 return 1; 4079 4080 msr_info->data = vcpu->arch.apf.msr_int_val; 4081 break; 4082 case MSR_KVM_ASYNC_PF_ACK: 4083 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4084 return 1; 4085 4086 msr_info->data = 0; 4087 break; 4088 case MSR_KVM_STEAL_TIME: 4089 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 4090 return 1; 4091 4092 msr_info->data = vcpu->arch.st.msr_val; 4093 break; 4094 case MSR_KVM_PV_EOI_EN: 4095 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 4096 return 1; 4097 4098 msr_info->data = vcpu->arch.pv_eoi.msr_val; 4099 break; 4100 case MSR_KVM_POLL_CONTROL: 4101 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 4102 return 1; 4103 4104 msr_info->data = vcpu->arch.msr_kvm_poll_control; 4105 break; 4106 case MSR_IA32_P5_MC_ADDR: 4107 case MSR_IA32_P5_MC_TYPE: 4108 case MSR_IA32_MCG_CAP: 4109 case MSR_IA32_MCG_CTL: 4110 case MSR_IA32_MCG_STATUS: 4111 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 4112 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 4113 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 4114 msr_info->host_initiated); 4115 case MSR_IA32_XSS: 4116 if (!msr_info->host_initiated && 4117 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 4118 return 1; 4119 msr_info->data = vcpu->arch.ia32_xss; 4120 break; 4121 case MSR_K7_CLK_CTL: 4122 /* 4123 * Provide expected ramp-up count for K7. All other 4124 * are set to zero, indicating minimum divisors for 4125 * every field. 4126 * 4127 * This prevents guest kernels on AMD host with CPU 4128 * type 6, model 8 and higher from exploding due to 4129 * the rdmsr failing. 4130 */ 4131 msr_info->data = 0x20000000; 4132 break; 4133 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 4134 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 4135 case HV_X64_MSR_SYNDBG_OPTIONS: 4136 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4137 case HV_X64_MSR_CRASH_CTL: 4138 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 4139 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4140 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4141 case HV_X64_MSR_TSC_EMULATION_STATUS: 4142 return kvm_hv_get_msr_common(vcpu, 4143 msr_info->index, &msr_info->data, 4144 msr_info->host_initiated); 4145 case MSR_IA32_BBL_CR_CTL3: 4146 /* This legacy MSR exists but isn't fully documented in current 4147 * silicon. It is however accessed by winxp in very narrow 4148 * scenarios where it sets bit #19, itself documented as 4149 * a "reserved" bit. Best effort attempt to source coherent 4150 * read data here should the balance of the register be 4151 * interpreted by the guest: 4152 * 4153 * L2 cache control register 3: 64GB range, 256KB size, 4154 * enabled, latency 0x1, configured 4155 */ 4156 msr_info->data = 0xbe702111; 4157 break; 4158 case MSR_AMD64_OSVW_ID_LENGTH: 4159 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4160 return 1; 4161 msr_info->data = vcpu->arch.osvw.length; 4162 break; 4163 case MSR_AMD64_OSVW_STATUS: 4164 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4165 return 1; 4166 msr_info->data = vcpu->arch.osvw.status; 4167 break; 4168 case MSR_PLATFORM_INFO: 4169 if (!msr_info->host_initiated && 4170 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 4171 return 1; 4172 msr_info->data = vcpu->arch.msr_platform_info; 4173 break; 4174 case MSR_MISC_FEATURES_ENABLES: 4175 msr_info->data = vcpu->arch.msr_misc_features_enables; 4176 break; 4177 case MSR_K7_HWCR: 4178 msr_info->data = vcpu->arch.msr_hwcr; 4179 break; 4180 #ifdef CONFIG_X86_64 4181 case MSR_IA32_XFD: 4182 if (!msr_info->host_initiated && 4183 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4184 return 1; 4185 4186 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; 4187 break; 4188 case MSR_IA32_XFD_ERR: 4189 if (!msr_info->host_initiated && 4190 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4191 return 1; 4192 4193 msr_info->data = vcpu->arch.guest_fpu.xfd_err; 4194 break; 4195 #endif 4196 default: 4197 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4198 return kvm_pmu_get_msr(vcpu, msr_info); 4199 return KVM_MSR_RET_INVALID; 4200 } 4201 return 0; 4202 } 4203 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 4204 4205 /* 4206 * Read or write a bunch of msrs. All parameters are kernel addresses. 4207 * 4208 * @return number of msrs set successfully. 4209 */ 4210 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 4211 struct kvm_msr_entry *entries, 4212 int (*do_msr)(struct kvm_vcpu *vcpu, 4213 unsigned index, u64 *data)) 4214 { 4215 int i; 4216 4217 for (i = 0; i < msrs->nmsrs; ++i) 4218 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 4219 break; 4220 4221 return i; 4222 } 4223 4224 /* 4225 * Read or write a bunch of msrs. Parameters are user addresses. 4226 * 4227 * @return number of msrs set successfully. 4228 */ 4229 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4230 int (*do_msr)(struct kvm_vcpu *vcpu, 4231 unsigned index, u64 *data), 4232 int writeback) 4233 { 4234 struct kvm_msrs msrs; 4235 struct kvm_msr_entry *entries; 4236 int r, n; 4237 unsigned size; 4238 4239 r = -EFAULT; 4240 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4241 goto out; 4242 4243 r = -E2BIG; 4244 if (msrs.nmsrs >= MAX_IO_MSRS) 4245 goto out; 4246 4247 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4248 entries = memdup_user(user_msrs->entries, size); 4249 if (IS_ERR(entries)) { 4250 r = PTR_ERR(entries); 4251 goto out; 4252 } 4253 4254 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 4255 if (r < 0) 4256 goto out_free; 4257 4258 r = -EFAULT; 4259 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4260 goto out_free; 4261 4262 r = n; 4263 4264 out_free: 4265 kfree(entries); 4266 out: 4267 return r; 4268 } 4269 4270 static inline bool kvm_can_mwait_in_guest(void) 4271 { 4272 return boot_cpu_has(X86_FEATURE_MWAIT) && 4273 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4274 boot_cpu_has(X86_FEATURE_ARAT); 4275 } 4276 4277 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4278 struct kvm_cpuid2 __user *cpuid_arg) 4279 { 4280 struct kvm_cpuid2 cpuid; 4281 int r; 4282 4283 r = -EFAULT; 4284 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4285 return r; 4286 4287 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4288 if (r) 4289 return r; 4290 4291 r = -EFAULT; 4292 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4293 return r; 4294 4295 return 0; 4296 } 4297 4298 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4299 { 4300 int r = 0; 4301 4302 switch (ext) { 4303 case KVM_CAP_IRQCHIP: 4304 case KVM_CAP_HLT: 4305 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4306 case KVM_CAP_SET_TSS_ADDR: 4307 case KVM_CAP_EXT_CPUID: 4308 case KVM_CAP_EXT_EMUL_CPUID: 4309 case KVM_CAP_CLOCKSOURCE: 4310 case KVM_CAP_PIT: 4311 case KVM_CAP_NOP_IO_DELAY: 4312 case KVM_CAP_MP_STATE: 4313 case KVM_CAP_SYNC_MMU: 4314 case KVM_CAP_USER_NMI: 4315 case KVM_CAP_REINJECT_CONTROL: 4316 case KVM_CAP_IRQ_INJECT_STATUS: 4317 case KVM_CAP_IOEVENTFD: 4318 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4319 case KVM_CAP_PIT2: 4320 case KVM_CAP_PIT_STATE2: 4321 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4322 case KVM_CAP_VCPU_EVENTS: 4323 case KVM_CAP_HYPERV: 4324 case KVM_CAP_HYPERV_VAPIC: 4325 case KVM_CAP_HYPERV_SPIN: 4326 case KVM_CAP_HYPERV_SYNIC: 4327 case KVM_CAP_HYPERV_SYNIC2: 4328 case KVM_CAP_HYPERV_VP_INDEX: 4329 case KVM_CAP_HYPERV_EVENTFD: 4330 case KVM_CAP_HYPERV_TLBFLUSH: 4331 case KVM_CAP_HYPERV_SEND_IPI: 4332 case KVM_CAP_HYPERV_CPUID: 4333 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4334 case KVM_CAP_SYS_HYPERV_CPUID: 4335 case KVM_CAP_PCI_SEGMENT: 4336 case KVM_CAP_DEBUGREGS: 4337 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4338 case KVM_CAP_XSAVE: 4339 case KVM_CAP_ASYNC_PF: 4340 case KVM_CAP_ASYNC_PF_INT: 4341 case KVM_CAP_GET_TSC_KHZ: 4342 case KVM_CAP_KVMCLOCK_CTRL: 4343 case KVM_CAP_READONLY_MEM: 4344 case KVM_CAP_HYPERV_TIME: 4345 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4346 case KVM_CAP_TSC_DEADLINE_TIMER: 4347 case KVM_CAP_DISABLE_QUIRKS: 4348 case KVM_CAP_SET_BOOT_CPU_ID: 4349 case KVM_CAP_SPLIT_IRQCHIP: 4350 case KVM_CAP_IMMEDIATE_EXIT: 4351 case KVM_CAP_PMU_EVENT_FILTER: 4352 case KVM_CAP_GET_MSR_FEATURES: 4353 case KVM_CAP_MSR_PLATFORM_INFO: 4354 case KVM_CAP_EXCEPTION_PAYLOAD: 4355 case KVM_CAP_X86_TRIPLE_FAULT_EVENT: 4356 case KVM_CAP_SET_GUEST_DEBUG: 4357 case KVM_CAP_LAST_CPU: 4358 case KVM_CAP_X86_USER_SPACE_MSR: 4359 case KVM_CAP_X86_MSR_FILTER: 4360 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4361 #ifdef CONFIG_X86_SGX_KVM 4362 case KVM_CAP_SGX_ATTRIBUTE: 4363 #endif 4364 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4365 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 4366 case KVM_CAP_SREGS2: 4367 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4368 case KVM_CAP_VCPU_ATTRIBUTES: 4369 case KVM_CAP_SYS_ATTRIBUTES: 4370 case KVM_CAP_VAPIC: 4371 case KVM_CAP_ENABLE_CAP: 4372 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: 4373 r = 1; 4374 break; 4375 case KVM_CAP_EXIT_HYPERCALL: 4376 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4377 break; 4378 case KVM_CAP_SET_GUEST_DEBUG2: 4379 return KVM_GUESTDBG_VALID_MASK; 4380 #ifdef CONFIG_KVM_XEN 4381 case KVM_CAP_XEN_HVM: 4382 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4383 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4384 KVM_XEN_HVM_CONFIG_SHARED_INFO | 4385 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL | 4386 KVM_XEN_HVM_CONFIG_EVTCHN_SEND; 4387 if (sched_info_on()) 4388 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4389 break; 4390 #endif 4391 case KVM_CAP_SYNC_REGS: 4392 r = KVM_SYNC_X86_VALID_FIELDS; 4393 break; 4394 case KVM_CAP_ADJUST_CLOCK: 4395 r = KVM_CLOCK_VALID_FLAGS; 4396 break; 4397 case KVM_CAP_X86_DISABLE_EXITS: 4398 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4399 KVM_X86_DISABLE_EXITS_CSTATE; 4400 if(kvm_can_mwait_in_guest()) 4401 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4402 break; 4403 case KVM_CAP_X86_SMM: 4404 /* SMBASE is usually relocated above 1M on modern chipsets, 4405 * and SMM handlers might indeed rely on 4G segment limits, 4406 * so do not report SMM to be available if real mode is 4407 * emulated via vm86 mode. Still, do not go to great lengths 4408 * to avoid userspace's usage of the feature, because it is a 4409 * fringe case that is not enabled except via specific settings 4410 * of the module parameters. 4411 */ 4412 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4413 break; 4414 case KVM_CAP_NR_VCPUS: 4415 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 4416 break; 4417 case KVM_CAP_MAX_VCPUS: 4418 r = KVM_MAX_VCPUS; 4419 break; 4420 case KVM_CAP_MAX_VCPU_ID: 4421 r = KVM_MAX_VCPU_IDS; 4422 break; 4423 case KVM_CAP_PV_MMU: /* obsolete */ 4424 r = 0; 4425 break; 4426 case KVM_CAP_MCE: 4427 r = KVM_MAX_MCE_BANKS; 4428 break; 4429 case KVM_CAP_XCRS: 4430 r = boot_cpu_has(X86_FEATURE_XSAVE); 4431 break; 4432 case KVM_CAP_TSC_CONTROL: 4433 case KVM_CAP_VM_TSC_CONTROL: 4434 r = kvm_caps.has_tsc_control; 4435 break; 4436 case KVM_CAP_X2APIC_API: 4437 r = KVM_X2APIC_API_VALID_FLAGS; 4438 break; 4439 case KVM_CAP_NESTED_STATE: 4440 r = kvm_x86_ops.nested_ops->get_state ? 4441 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4442 break; 4443 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4444 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4445 break; 4446 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4447 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4448 break; 4449 case KVM_CAP_SMALLER_MAXPHYADDR: 4450 r = (int) allow_smaller_maxphyaddr; 4451 break; 4452 case KVM_CAP_STEAL_TIME: 4453 r = sched_info_on(); 4454 break; 4455 case KVM_CAP_X86_BUS_LOCK_EXIT: 4456 if (kvm_caps.has_bus_lock_exit) 4457 r = KVM_BUS_LOCK_DETECTION_OFF | 4458 KVM_BUS_LOCK_DETECTION_EXIT; 4459 else 4460 r = 0; 4461 break; 4462 case KVM_CAP_XSAVE2: { 4463 u64 guest_perm = xstate_get_guest_group_perm(); 4464 4465 r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false); 4466 if (r < sizeof(struct kvm_xsave)) 4467 r = sizeof(struct kvm_xsave); 4468 break; 4469 } 4470 case KVM_CAP_PMU_CAPABILITY: 4471 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; 4472 break; 4473 case KVM_CAP_DISABLE_QUIRKS2: 4474 r = KVM_X86_VALID_QUIRKS; 4475 break; 4476 case KVM_CAP_X86_NOTIFY_VMEXIT: 4477 r = kvm_caps.has_notify_vmexit; 4478 break; 4479 default: 4480 break; 4481 } 4482 return r; 4483 } 4484 4485 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) 4486 { 4487 void __user *uaddr = (void __user*)(unsigned long)attr->addr; 4488 4489 if ((u64)(unsigned long)uaddr != attr->addr) 4490 return ERR_PTR_USR(-EFAULT); 4491 return uaddr; 4492 } 4493 4494 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) 4495 { 4496 u64 __user *uaddr = kvm_get_attr_addr(attr); 4497 4498 if (attr->group) 4499 return -ENXIO; 4500 4501 if (IS_ERR(uaddr)) 4502 return PTR_ERR(uaddr); 4503 4504 switch (attr->attr) { 4505 case KVM_X86_XCOMP_GUEST_SUPP: 4506 if (put_user(kvm_caps.supported_xcr0, uaddr)) 4507 return -EFAULT; 4508 return 0; 4509 default: 4510 return -ENXIO; 4511 break; 4512 } 4513 } 4514 4515 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) 4516 { 4517 if (attr->group) 4518 return -ENXIO; 4519 4520 switch (attr->attr) { 4521 case KVM_X86_XCOMP_GUEST_SUPP: 4522 return 0; 4523 default: 4524 return -ENXIO; 4525 } 4526 } 4527 4528 long kvm_arch_dev_ioctl(struct file *filp, 4529 unsigned int ioctl, unsigned long arg) 4530 { 4531 void __user *argp = (void __user *)arg; 4532 long r; 4533 4534 switch (ioctl) { 4535 case KVM_GET_MSR_INDEX_LIST: { 4536 struct kvm_msr_list __user *user_msr_list = argp; 4537 struct kvm_msr_list msr_list; 4538 unsigned n; 4539 4540 r = -EFAULT; 4541 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4542 goto out; 4543 n = msr_list.nmsrs; 4544 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4545 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4546 goto out; 4547 r = -E2BIG; 4548 if (n < msr_list.nmsrs) 4549 goto out; 4550 r = -EFAULT; 4551 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4552 num_msrs_to_save * sizeof(u32))) 4553 goto out; 4554 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4555 &emulated_msrs, 4556 num_emulated_msrs * sizeof(u32))) 4557 goto out; 4558 r = 0; 4559 break; 4560 } 4561 case KVM_GET_SUPPORTED_CPUID: 4562 case KVM_GET_EMULATED_CPUID: { 4563 struct kvm_cpuid2 __user *cpuid_arg = argp; 4564 struct kvm_cpuid2 cpuid; 4565 4566 r = -EFAULT; 4567 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4568 goto out; 4569 4570 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4571 ioctl); 4572 if (r) 4573 goto out; 4574 4575 r = -EFAULT; 4576 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4577 goto out; 4578 r = 0; 4579 break; 4580 } 4581 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4582 r = -EFAULT; 4583 if (copy_to_user(argp, &kvm_caps.supported_mce_cap, 4584 sizeof(kvm_caps.supported_mce_cap))) 4585 goto out; 4586 r = 0; 4587 break; 4588 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4589 struct kvm_msr_list __user *user_msr_list = argp; 4590 struct kvm_msr_list msr_list; 4591 unsigned int n; 4592 4593 r = -EFAULT; 4594 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4595 goto out; 4596 n = msr_list.nmsrs; 4597 msr_list.nmsrs = num_msr_based_features; 4598 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4599 goto out; 4600 r = -E2BIG; 4601 if (n < msr_list.nmsrs) 4602 goto out; 4603 r = -EFAULT; 4604 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4605 num_msr_based_features * sizeof(u32))) 4606 goto out; 4607 r = 0; 4608 break; 4609 } 4610 case KVM_GET_MSRS: 4611 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4612 break; 4613 case KVM_GET_SUPPORTED_HV_CPUID: 4614 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4615 break; 4616 case KVM_GET_DEVICE_ATTR: { 4617 struct kvm_device_attr attr; 4618 r = -EFAULT; 4619 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4620 break; 4621 r = kvm_x86_dev_get_attr(&attr); 4622 break; 4623 } 4624 case KVM_HAS_DEVICE_ATTR: { 4625 struct kvm_device_attr attr; 4626 r = -EFAULT; 4627 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4628 break; 4629 r = kvm_x86_dev_has_attr(&attr); 4630 break; 4631 } 4632 default: 4633 r = -EINVAL; 4634 break; 4635 } 4636 out: 4637 return r; 4638 } 4639 4640 static void wbinvd_ipi(void *garbage) 4641 { 4642 wbinvd(); 4643 } 4644 4645 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4646 { 4647 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4648 } 4649 4650 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4651 { 4652 /* Address WBINVD may be executed by guest */ 4653 if (need_emulate_wbinvd(vcpu)) { 4654 if (static_call(kvm_x86_has_wbinvd_exit)()) 4655 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4656 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4657 smp_call_function_single(vcpu->cpu, 4658 wbinvd_ipi, NULL, 1); 4659 } 4660 4661 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4662 4663 /* Save host pkru register if supported */ 4664 vcpu->arch.host_pkru = read_pkru(); 4665 4666 /* Apply any externally detected TSC adjustments (due to suspend) */ 4667 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4668 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4669 vcpu->arch.tsc_offset_adjustment = 0; 4670 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4671 } 4672 4673 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4674 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4675 rdtsc() - vcpu->arch.last_host_tsc; 4676 if (tsc_delta < 0) 4677 mark_tsc_unstable("KVM discovered backwards TSC"); 4678 4679 if (kvm_check_tsc_unstable()) { 4680 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4681 vcpu->arch.last_guest_tsc); 4682 kvm_vcpu_write_tsc_offset(vcpu, offset); 4683 vcpu->arch.tsc_catchup = 1; 4684 } 4685 4686 if (kvm_lapic_hv_timer_in_use(vcpu)) 4687 kvm_lapic_restart_hv_timer(vcpu); 4688 4689 /* 4690 * On a host with synchronized TSC, there is no need to update 4691 * kvmclock on vcpu->cpu migration 4692 */ 4693 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4694 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4695 if (vcpu->cpu != cpu) 4696 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4697 vcpu->cpu = cpu; 4698 } 4699 4700 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4701 } 4702 4703 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4704 { 4705 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 4706 struct kvm_steal_time __user *st; 4707 struct kvm_memslots *slots; 4708 static const u8 preempted = KVM_VCPU_PREEMPTED; 4709 4710 /* 4711 * The vCPU can be marked preempted if and only if the VM-Exit was on 4712 * an instruction boundary and will not trigger guest emulation of any 4713 * kind (see vcpu_run). Vendor specific code controls (conservatively) 4714 * when this is true, for example allowing the vCPU to be marked 4715 * preempted if and only if the VM-Exit was due to a host interrupt. 4716 */ 4717 if (!vcpu->arch.at_instruction_boundary) { 4718 vcpu->stat.preemption_other++; 4719 return; 4720 } 4721 4722 vcpu->stat.preemption_reported++; 4723 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4724 return; 4725 4726 if (vcpu->arch.st.preempted) 4727 return; 4728 4729 /* This happens on process exit */ 4730 if (unlikely(current->mm != vcpu->kvm->mm)) 4731 return; 4732 4733 slots = kvm_memslots(vcpu->kvm); 4734 4735 if (unlikely(slots->generation != ghc->generation || 4736 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 4737 return; 4738 4739 st = (struct kvm_steal_time __user *)ghc->hva; 4740 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 4741 4742 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 4743 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4744 4745 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 4746 } 4747 4748 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4749 { 4750 int idx; 4751 4752 if (vcpu->preempted) { 4753 if (!vcpu->arch.guest_state_protected) 4754 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4755 4756 /* 4757 * Take the srcu lock as memslots will be accessed to check the gfn 4758 * cache generation against the memslots generation. 4759 */ 4760 idx = srcu_read_lock(&vcpu->kvm->srcu); 4761 if (kvm_xen_msr_enabled(vcpu->kvm)) 4762 kvm_xen_runstate_set_preempted(vcpu); 4763 else 4764 kvm_steal_time_set_preempted(vcpu); 4765 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4766 } 4767 4768 static_call(kvm_x86_vcpu_put)(vcpu); 4769 vcpu->arch.last_host_tsc = rdtsc(); 4770 } 4771 4772 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4773 struct kvm_lapic_state *s) 4774 { 4775 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 4776 4777 return kvm_apic_get_state(vcpu, s); 4778 } 4779 4780 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4781 struct kvm_lapic_state *s) 4782 { 4783 int r; 4784 4785 r = kvm_apic_set_state(vcpu, s); 4786 if (r) 4787 return r; 4788 update_cr8_intercept(vcpu); 4789 4790 return 0; 4791 } 4792 4793 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4794 { 4795 /* 4796 * We can accept userspace's request for interrupt injection 4797 * as long as we have a place to store the interrupt number. 4798 * The actual injection will happen when the CPU is able to 4799 * deliver the interrupt. 4800 */ 4801 if (kvm_cpu_has_extint(vcpu)) 4802 return false; 4803 4804 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4805 return (!lapic_in_kernel(vcpu) || 4806 kvm_apic_accept_pic_intr(vcpu)); 4807 } 4808 4809 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4810 { 4811 /* 4812 * Do not cause an interrupt window exit if an exception 4813 * is pending or an event needs reinjection; userspace 4814 * might want to inject the interrupt manually using KVM_SET_REGS 4815 * or KVM_SET_SREGS. For that to work, we must be at an 4816 * instruction boundary and with no events half-injected. 4817 */ 4818 return (kvm_arch_interrupt_allowed(vcpu) && 4819 kvm_cpu_accept_dm_intr(vcpu) && 4820 !kvm_event_needs_reinjection(vcpu) && 4821 !vcpu->arch.exception.pending); 4822 } 4823 4824 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4825 struct kvm_interrupt *irq) 4826 { 4827 if (irq->irq >= KVM_NR_INTERRUPTS) 4828 return -EINVAL; 4829 4830 if (!irqchip_in_kernel(vcpu->kvm)) { 4831 kvm_queue_interrupt(vcpu, irq->irq, false); 4832 kvm_make_request(KVM_REQ_EVENT, vcpu); 4833 return 0; 4834 } 4835 4836 /* 4837 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4838 * fail for in-kernel 8259. 4839 */ 4840 if (pic_in_kernel(vcpu->kvm)) 4841 return -ENXIO; 4842 4843 if (vcpu->arch.pending_external_vector != -1) 4844 return -EEXIST; 4845 4846 vcpu->arch.pending_external_vector = irq->irq; 4847 kvm_make_request(KVM_REQ_EVENT, vcpu); 4848 return 0; 4849 } 4850 4851 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4852 { 4853 kvm_inject_nmi(vcpu); 4854 4855 return 0; 4856 } 4857 4858 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4859 { 4860 kvm_make_request(KVM_REQ_SMI, vcpu); 4861 4862 return 0; 4863 } 4864 4865 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4866 struct kvm_tpr_access_ctl *tac) 4867 { 4868 if (tac->flags) 4869 return -EINVAL; 4870 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4871 return 0; 4872 } 4873 4874 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4875 u64 mcg_cap) 4876 { 4877 int r; 4878 unsigned bank_num = mcg_cap & 0xff, bank; 4879 4880 r = -EINVAL; 4881 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4882 goto out; 4883 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000)) 4884 goto out; 4885 r = 0; 4886 vcpu->arch.mcg_cap = mcg_cap; 4887 /* Init IA32_MCG_CTL to all 1s */ 4888 if (mcg_cap & MCG_CTL_P) 4889 vcpu->arch.mcg_ctl = ~(u64)0; 4890 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */ 4891 for (bank = 0; bank < bank_num; bank++) { 4892 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4893 if (mcg_cap & MCG_CMCI_P) 4894 vcpu->arch.mci_ctl2_banks[bank] = 0; 4895 } 4896 vcpu->arch.apic->nr_lvt_entries = 4897 KVM_APIC_MAX_NR_LVT_ENTRIES - !(mcg_cap & MCG_CMCI_P); 4898 4899 static_call(kvm_x86_setup_mce)(vcpu); 4900 out: 4901 return r; 4902 } 4903 4904 /* 4905 * Validate this is an UCNA (uncorrectable no action) error by checking the 4906 * MCG_STATUS and MCi_STATUS registers: 4907 * - none of the bits for Machine Check Exceptions are set 4908 * - both the VAL (valid) and UC (uncorrectable) bits are set 4909 * MCI_STATUS_PCC - Processor Context Corrupted 4910 * MCI_STATUS_S - Signaled as a Machine Check Exception 4911 * MCI_STATUS_AR - Software recoverable Action Required 4912 */ 4913 static bool is_ucna(struct kvm_x86_mce *mce) 4914 { 4915 return !mce->mcg_status && 4916 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) && 4917 (mce->status & MCI_STATUS_VAL) && 4918 (mce->status & MCI_STATUS_UC); 4919 } 4920 4921 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks) 4922 { 4923 u64 mcg_cap = vcpu->arch.mcg_cap; 4924 4925 banks[1] = mce->status; 4926 banks[2] = mce->addr; 4927 banks[3] = mce->misc; 4928 vcpu->arch.mcg_status = mce->mcg_status; 4929 4930 if (!(mcg_cap & MCG_CMCI_P) || 4931 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN)) 4932 return 0; 4933 4934 if (lapic_in_kernel(vcpu)) 4935 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI); 4936 4937 return 0; 4938 } 4939 4940 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4941 struct kvm_x86_mce *mce) 4942 { 4943 u64 mcg_cap = vcpu->arch.mcg_cap; 4944 unsigned bank_num = mcg_cap & 0xff; 4945 u64 *banks = vcpu->arch.mce_banks; 4946 4947 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4948 return -EINVAL; 4949 4950 banks += array_index_nospec(4 * mce->bank, 4 * bank_num); 4951 4952 if (is_ucna(mce)) 4953 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks); 4954 4955 /* 4956 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4957 * reporting is disabled 4958 */ 4959 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4960 vcpu->arch.mcg_ctl != ~(u64)0) 4961 return 0; 4962 /* 4963 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4964 * reporting is disabled for the bank 4965 */ 4966 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4967 return 0; 4968 if (mce->status & MCI_STATUS_UC) { 4969 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4970 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4971 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4972 return 0; 4973 } 4974 if (banks[1] & MCI_STATUS_VAL) 4975 mce->status |= MCI_STATUS_OVER; 4976 banks[2] = mce->addr; 4977 banks[3] = mce->misc; 4978 vcpu->arch.mcg_status = mce->mcg_status; 4979 banks[1] = mce->status; 4980 kvm_queue_exception(vcpu, MC_VECTOR); 4981 } else if (!(banks[1] & MCI_STATUS_VAL) 4982 || !(banks[1] & MCI_STATUS_UC)) { 4983 if (banks[1] & MCI_STATUS_VAL) 4984 mce->status |= MCI_STATUS_OVER; 4985 banks[2] = mce->addr; 4986 banks[3] = mce->misc; 4987 banks[1] = mce->status; 4988 } else 4989 banks[1] |= MCI_STATUS_OVER; 4990 return 0; 4991 } 4992 4993 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4994 struct kvm_vcpu_events *events) 4995 { 4996 process_nmi(vcpu); 4997 4998 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4999 process_smi(vcpu); 5000 5001 /* 5002 * In guest mode, payload delivery should be deferred, 5003 * so that the L1 hypervisor can intercept #PF before 5004 * CR2 is modified (or intercept #DB before DR6 is 5005 * modified under nVMX). Unless the per-VM capability, 5006 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 5007 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 5008 * opportunistically defer the exception payload, deliver it if the 5009 * capability hasn't been requested before processing a 5010 * KVM_GET_VCPU_EVENTS. 5011 */ 5012 if (!vcpu->kvm->arch.exception_payload_enabled && 5013 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 5014 kvm_deliver_exception_payload(vcpu); 5015 5016 /* 5017 * The API doesn't provide the instruction length for software 5018 * exceptions, so don't report them. As long as the guest RIP 5019 * isn't advanced, we should expect to encounter the exception 5020 * again. 5021 */ 5022 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 5023 events->exception.injected = 0; 5024 events->exception.pending = 0; 5025 } else { 5026 events->exception.injected = vcpu->arch.exception.injected; 5027 events->exception.pending = vcpu->arch.exception.pending; 5028 /* 5029 * For ABI compatibility, deliberately conflate 5030 * pending and injected exceptions when 5031 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 5032 */ 5033 if (!vcpu->kvm->arch.exception_payload_enabled) 5034 events->exception.injected |= 5035 vcpu->arch.exception.pending; 5036 } 5037 events->exception.nr = vcpu->arch.exception.nr; 5038 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 5039 events->exception.error_code = vcpu->arch.exception.error_code; 5040 events->exception_has_payload = vcpu->arch.exception.has_payload; 5041 events->exception_payload = vcpu->arch.exception.payload; 5042 5043 events->interrupt.injected = 5044 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 5045 events->interrupt.nr = vcpu->arch.interrupt.nr; 5046 events->interrupt.soft = 0; 5047 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 5048 5049 events->nmi.injected = vcpu->arch.nmi_injected; 5050 events->nmi.pending = vcpu->arch.nmi_pending != 0; 5051 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 5052 events->nmi.pad = 0; 5053 5054 events->sipi_vector = 0; /* never valid when reporting to user space */ 5055 5056 events->smi.smm = is_smm(vcpu); 5057 events->smi.pending = vcpu->arch.smi_pending; 5058 events->smi.smm_inside_nmi = 5059 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 5060 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 5061 5062 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 5063 | KVM_VCPUEVENT_VALID_SHADOW 5064 | KVM_VCPUEVENT_VALID_SMM); 5065 if (vcpu->kvm->arch.exception_payload_enabled) 5066 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 5067 if (vcpu->kvm->arch.triple_fault_event) { 5068 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5069 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; 5070 } 5071 5072 memset(&events->reserved, 0, sizeof(events->reserved)); 5073 } 5074 5075 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 5076 5077 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 5078 struct kvm_vcpu_events *events) 5079 { 5080 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 5081 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 5082 | KVM_VCPUEVENT_VALID_SHADOW 5083 | KVM_VCPUEVENT_VALID_SMM 5084 | KVM_VCPUEVENT_VALID_PAYLOAD 5085 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT)) 5086 return -EINVAL; 5087 5088 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 5089 if (!vcpu->kvm->arch.exception_payload_enabled) 5090 return -EINVAL; 5091 if (events->exception.pending) 5092 events->exception.injected = 0; 5093 else 5094 events->exception_has_payload = 0; 5095 } else { 5096 events->exception.pending = 0; 5097 events->exception_has_payload = 0; 5098 } 5099 5100 if ((events->exception.injected || events->exception.pending) && 5101 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 5102 return -EINVAL; 5103 5104 /* INITs are latched while in SMM */ 5105 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 5106 (events->smi.smm || events->smi.pending) && 5107 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 5108 return -EINVAL; 5109 5110 process_nmi(vcpu); 5111 vcpu->arch.exception.injected = events->exception.injected; 5112 vcpu->arch.exception.pending = events->exception.pending; 5113 vcpu->arch.exception.nr = events->exception.nr; 5114 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 5115 vcpu->arch.exception.error_code = events->exception.error_code; 5116 vcpu->arch.exception.has_payload = events->exception_has_payload; 5117 vcpu->arch.exception.payload = events->exception_payload; 5118 5119 vcpu->arch.interrupt.injected = events->interrupt.injected; 5120 vcpu->arch.interrupt.nr = events->interrupt.nr; 5121 vcpu->arch.interrupt.soft = events->interrupt.soft; 5122 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 5123 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 5124 events->interrupt.shadow); 5125 5126 vcpu->arch.nmi_injected = events->nmi.injected; 5127 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 5128 vcpu->arch.nmi_pending = events->nmi.pending; 5129 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 5130 5131 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 5132 lapic_in_kernel(vcpu)) 5133 vcpu->arch.apic->sipi_vector = events->sipi_vector; 5134 5135 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 5136 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 5137 kvm_x86_ops.nested_ops->leave_nested(vcpu); 5138 kvm_smm_changed(vcpu, events->smi.smm); 5139 } 5140 5141 vcpu->arch.smi_pending = events->smi.pending; 5142 5143 if (events->smi.smm) { 5144 if (events->smi.smm_inside_nmi) 5145 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 5146 else 5147 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 5148 } 5149 5150 if (lapic_in_kernel(vcpu)) { 5151 if (events->smi.latched_init) 5152 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5153 else 5154 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5155 } 5156 } 5157 5158 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { 5159 if (!vcpu->kvm->arch.triple_fault_event) 5160 return -EINVAL; 5161 if (events->triple_fault.pending) 5162 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5163 else 5164 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5165 } 5166 5167 kvm_make_request(KVM_REQ_EVENT, vcpu); 5168 5169 return 0; 5170 } 5171 5172 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 5173 struct kvm_debugregs *dbgregs) 5174 { 5175 unsigned long val; 5176 5177 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 5178 kvm_get_dr(vcpu, 6, &val); 5179 dbgregs->dr6 = val; 5180 dbgregs->dr7 = vcpu->arch.dr7; 5181 dbgregs->flags = 0; 5182 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 5183 } 5184 5185 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 5186 struct kvm_debugregs *dbgregs) 5187 { 5188 if (dbgregs->flags) 5189 return -EINVAL; 5190 5191 if (!kvm_dr6_valid(dbgregs->dr6)) 5192 return -EINVAL; 5193 if (!kvm_dr7_valid(dbgregs->dr7)) 5194 return -EINVAL; 5195 5196 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 5197 kvm_update_dr0123(vcpu); 5198 vcpu->arch.dr6 = dbgregs->dr6; 5199 vcpu->arch.dr7 = dbgregs->dr7; 5200 kvm_update_dr7(vcpu); 5201 5202 return 0; 5203 } 5204 5205 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 5206 struct kvm_xsave *guest_xsave) 5207 { 5208 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5209 return; 5210 5211 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 5212 guest_xsave->region, 5213 sizeof(guest_xsave->region), 5214 vcpu->arch.pkru); 5215 } 5216 5217 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, 5218 u8 *state, unsigned int size) 5219 { 5220 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5221 return; 5222 5223 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 5224 state, size, vcpu->arch.pkru); 5225 } 5226 5227 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 5228 struct kvm_xsave *guest_xsave) 5229 { 5230 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5231 return 0; 5232 5233 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 5234 guest_xsave->region, 5235 kvm_caps.supported_xcr0, 5236 &vcpu->arch.pkru); 5237 } 5238 5239 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 5240 struct kvm_xcrs *guest_xcrs) 5241 { 5242 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 5243 guest_xcrs->nr_xcrs = 0; 5244 return; 5245 } 5246 5247 guest_xcrs->nr_xcrs = 1; 5248 guest_xcrs->flags = 0; 5249 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 5250 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 5251 } 5252 5253 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 5254 struct kvm_xcrs *guest_xcrs) 5255 { 5256 int i, r = 0; 5257 5258 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 5259 return -EINVAL; 5260 5261 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 5262 return -EINVAL; 5263 5264 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 5265 /* Only support XCR0 currently */ 5266 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 5267 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 5268 guest_xcrs->xcrs[i].value); 5269 break; 5270 } 5271 if (r) 5272 r = -EINVAL; 5273 return r; 5274 } 5275 5276 /* 5277 * kvm_set_guest_paused() indicates to the guest kernel that it has been 5278 * stopped by the hypervisor. This function will be called from the host only. 5279 * EINVAL is returned when the host attempts to set the flag for a guest that 5280 * does not support pv clocks. 5281 */ 5282 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 5283 { 5284 if (!vcpu->arch.pv_time.active) 5285 return -EINVAL; 5286 vcpu->arch.pvclock_set_guest_stopped_request = true; 5287 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5288 return 0; 5289 } 5290 5291 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 5292 struct kvm_device_attr *attr) 5293 { 5294 int r; 5295 5296 switch (attr->attr) { 5297 case KVM_VCPU_TSC_OFFSET: 5298 r = 0; 5299 break; 5300 default: 5301 r = -ENXIO; 5302 } 5303 5304 return r; 5305 } 5306 5307 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 5308 struct kvm_device_attr *attr) 5309 { 5310 u64 __user *uaddr = kvm_get_attr_addr(attr); 5311 int r; 5312 5313 if (IS_ERR(uaddr)) 5314 return PTR_ERR(uaddr); 5315 5316 switch (attr->attr) { 5317 case KVM_VCPU_TSC_OFFSET: 5318 r = -EFAULT; 5319 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 5320 break; 5321 r = 0; 5322 break; 5323 default: 5324 r = -ENXIO; 5325 } 5326 5327 return r; 5328 } 5329 5330 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 5331 struct kvm_device_attr *attr) 5332 { 5333 u64 __user *uaddr = kvm_get_attr_addr(attr); 5334 struct kvm *kvm = vcpu->kvm; 5335 int r; 5336 5337 if (IS_ERR(uaddr)) 5338 return PTR_ERR(uaddr); 5339 5340 switch (attr->attr) { 5341 case KVM_VCPU_TSC_OFFSET: { 5342 u64 offset, tsc, ns; 5343 unsigned long flags; 5344 bool matched; 5345 5346 r = -EFAULT; 5347 if (get_user(offset, uaddr)) 5348 break; 5349 5350 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 5351 5352 matched = (vcpu->arch.virtual_tsc_khz && 5353 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 5354 kvm->arch.last_tsc_offset == offset); 5355 5356 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 5357 ns = get_kvmclock_base_ns(); 5358 5359 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 5360 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 5361 5362 r = 0; 5363 break; 5364 } 5365 default: 5366 r = -ENXIO; 5367 } 5368 5369 return r; 5370 } 5371 5372 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 5373 unsigned int ioctl, 5374 void __user *argp) 5375 { 5376 struct kvm_device_attr attr; 5377 int r; 5378 5379 if (copy_from_user(&attr, argp, sizeof(attr))) 5380 return -EFAULT; 5381 5382 if (attr.group != KVM_VCPU_TSC_CTRL) 5383 return -ENXIO; 5384 5385 switch (ioctl) { 5386 case KVM_HAS_DEVICE_ATTR: 5387 r = kvm_arch_tsc_has_attr(vcpu, &attr); 5388 break; 5389 case KVM_GET_DEVICE_ATTR: 5390 r = kvm_arch_tsc_get_attr(vcpu, &attr); 5391 break; 5392 case KVM_SET_DEVICE_ATTR: 5393 r = kvm_arch_tsc_set_attr(vcpu, &attr); 5394 break; 5395 } 5396 5397 return r; 5398 } 5399 5400 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5401 struct kvm_enable_cap *cap) 5402 { 5403 int r; 5404 uint16_t vmcs_version; 5405 void __user *user_ptr; 5406 5407 if (cap->flags) 5408 return -EINVAL; 5409 5410 switch (cap->cap) { 5411 case KVM_CAP_HYPERV_SYNIC2: 5412 if (cap->args[0]) 5413 return -EINVAL; 5414 fallthrough; 5415 5416 case KVM_CAP_HYPERV_SYNIC: 5417 if (!irqchip_in_kernel(vcpu->kvm)) 5418 return -EINVAL; 5419 return kvm_hv_activate_synic(vcpu, cap->cap == 5420 KVM_CAP_HYPERV_SYNIC2); 5421 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5422 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5423 return -ENOTTY; 5424 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5425 if (!r) { 5426 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5427 if (copy_to_user(user_ptr, &vmcs_version, 5428 sizeof(vmcs_version))) 5429 r = -EFAULT; 5430 } 5431 return r; 5432 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5433 if (!kvm_x86_ops.enable_direct_tlbflush) 5434 return -ENOTTY; 5435 5436 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 5437 5438 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5439 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5440 5441 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5442 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5443 if (vcpu->arch.pv_cpuid.enforce) 5444 kvm_update_pv_runtime(vcpu); 5445 5446 return 0; 5447 default: 5448 return -EINVAL; 5449 } 5450 } 5451 5452 long kvm_arch_vcpu_ioctl(struct file *filp, 5453 unsigned int ioctl, unsigned long arg) 5454 { 5455 struct kvm_vcpu *vcpu = filp->private_data; 5456 void __user *argp = (void __user *)arg; 5457 int r; 5458 union { 5459 struct kvm_sregs2 *sregs2; 5460 struct kvm_lapic_state *lapic; 5461 struct kvm_xsave *xsave; 5462 struct kvm_xcrs *xcrs; 5463 void *buffer; 5464 } u; 5465 5466 vcpu_load(vcpu); 5467 5468 u.buffer = NULL; 5469 switch (ioctl) { 5470 case KVM_GET_LAPIC: { 5471 r = -EINVAL; 5472 if (!lapic_in_kernel(vcpu)) 5473 goto out; 5474 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 5475 GFP_KERNEL_ACCOUNT); 5476 5477 r = -ENOMEM; 5478 if (!u.lapic) 5479 goto out; 5480 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5481 if (r) 5482 goto out; 5483 r = -EFAULT; 5484 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5485 goto out; 5486 r = 0; 5487 break; 5488 } 5489 case KVM_SET_LAPIC: { 5490 r = -EINVAL; 5491 if (!lapic_in_kernel(vcpu)) 5492 goto out; 5493 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5494 if (IS_ERR(u.lapic)) { 5495 r = PTR_ERR(u.lapic); 5496 goto out_nofree; 5497 } 5498 5499 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5500 break; 5501 } 5502 case KVM_INTERRUPT: { 5503 struct kvm_interrupt irq; 5504 5505 r = -EFAULT; 5506 if (copy_from_user(&irq, argp, sizeof(irq))) 5507 goto out; 5508 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5509 break; 5510 } 5511 case KVM_NMI: { 5512 r = kvm_vcpu_ioctl_nmi(vcpu); 5513 break; 5514 } 5515 case KVM_SMI: { 5516 r = kvm_vcpu_ioctl_smi(vcpu); 5517 break; 5518 } 5519 case KVM_SET_CPUID: { 5520 struct kvm_cpuid __user *cpuid_arg = argp; 5521 struct kvm_cpuid cpuid; 5522 5523 r = -EFAULT; 5524 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5525 goto out; 5526 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5527 break; 5528 } 5529 case KVM_SET_CPUID2: { 5530 struct kvm_cpuid2 __user *cpuid_arg = argp; 5531 struct kvm_cpuid2 cpuid; 5532 5533 r = -EFAULT; 5534 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5535 goto out; 5536 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5537 cpuid_arg->entries); 5538 break; 5539 } 5540 case KVM_GET_CPUID2: { 5541 struct kvm_cpuid2 __user *cpuid_arg = argp; 5542 struct kvm_cpuid2 cpuid; 5543 5544 r = -EFAULT; 5545 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5546 goto out; 5547 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5548 cpuid_arg->entries); 5549 if (r) 5550 goto out; 5551 r = -EFAULT; 5552 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5553 goto out; 5554 r = 0; 5555 break; 5556 } 5557 case KVM_GET_MSRS: { 5558 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5559 r = msr_io(vcpu, argp, do_get_msr, 1); 5560 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5561 break; 5562 } 5563 case KVM_SET_MSRS: { 5564 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5565 r = msr_io(vcpu, argp, do_set_msr, 0); 5566 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5567 break; 5568 } 5569 case KVM_TPR_ACCESS_REPORTING: { 5570 struct kvm_tpr_access_ctl tac; 5571 5572 r = -EFAULT; 5573 if (copy_from_user(&tac, argp, sizeof(tac))) 5574 goto out; 5575 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5576 if (r) 5577 goto out; 5578 r = -EFAULT; 5579 if (copy_to_user(argp, &tac, sizeof(tac))) 5580 goto out; 5581 r = 0; 5582 break; 5583 }; 5584 case KVM_SET_VAPIC_ADDR: { 5585 struct kvm_vapic_addr va; 5586 int idx; 5587 5588 r = -EINVAL; 5589 if (!lapic_in_kernel(vcpu)) 5590 goto out; 5591 r = -EFAULT; 5592 if (copy_from_user(&va, argp, sizeof(va))) 5593 goto out; 5594 idx = srcu_read_lock(&vcpu->kvm->srcu); 5595 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5596 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5597 break; 5598 } 5599 case KVM_X86_SETUP_MCE: { 5600 u64 mcg_cap; 5601 5602 r = -EFAULT; 5603 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5604 goto out; 5605 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5606 break; 5607 } 5608 case KVM_X86_SET_MCE: { 5609 struct kvm_x86_mce mce; 5610 5611 r = -EFAULT; 5612 if (copy_from_user(&mce, argp, sizeof(mce))) 5613 goto out; 5614 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5615 break; 5616 } 5617 case KVM_GET_VCPU_EVENTS: { 5618 struct kvm_vcpu_events events; 5619 5620 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5621 5622 r = -EFAULT; 5623 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5624 break; 5625 r = 0; 5626 break; 5627 } 5628 case KVM_SET_VCPU_EVENTS: { 5629 struct kvm_vcpu_events events; 5630 5631 r = -EFAULT; 5632 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5633 break; 5634 5635 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5636 break; 5637 } 5638 case KVM_GET_DEBUGREGS: { 5639 struct kvm_debugregs dbgregs; 5640 5641 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5642 5643 r = -EFAULT; 5644 if (copy_to_user(argp, &dbgregs, 5645 sizeof(struct kvm_debugregs))) 5646 break; 5647 r = 0; 5648 break; 5649 } 5650 case KVM_SET_DEBUGREGS: { 5651 struct kvm_debugregs dbgregs; 5652 5653 r = -EFAULT; 5654 if (copy_from_user(&dbgregs, argp, 5655 sizeof(struct kvm_debugregs))) 5656 break; 5657 5658 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5659 break; 5660 } 5661 case KVM_GET_XSAVE: { 5662 r = -EINVAL; 5663 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) 5664 break; 5665 5666 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5667 r = -ENOMEM; 5668 if (!u.xsave) 5669 break; 5670 5671 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5672 5673 r = -EFAULT; 5674 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5675 break; 5676 r = 0; 5677 break; 5678 } 5679 case KVM_SET_XSAVE: { 5680 int size = vcpu->arch.guest_fpu.uabi_size; 5681 5682 u.xsave = memdup_user(argp, size); 5683 if (IS_ERR(u.xsave)) { 5684 r = PTR_ERR(u.xsave); 5685 goto out_nofree; 5686 } 5687 5688 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5689 break; 5690 } 5691 5692 case KVM_GET_XSAVE2: { 5693 int size = vcpu->arch.guest_fpu.uabi_size; 5694 5695 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); 5696 r = -ENOMEM; 5697 if (!u.xsave) 5698 break; 5699 5700 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); 5701 5702 r = -EFAULT; 5703 if (copy_to_user(argp, u.xsave, size)) 5704 break; 5705 5706 r = 0; 5707 break; 5708 } 5709 5710 case KVM_GET_XCRS: { 5711 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5712 r = -ENOMEM; 5713 if (!u.xcrs) 5714 break; 5715 5716 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5717 5718 r = -EFAULT; 5719 if (copy_to_user(argp, u.xcrs, 5720 sizeof(struct kvm_xcrs))) 5721 break; 5722 r = 0; 5723 break; 5724 } 5725 case KVM_SET_XCRS: { 5726 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5727 if (IS_ERR(u.xcrs)) { 5728 r = PTR_ERR(u.xcrs); 5729 goto out_nofree; 5730 } 5731 5732 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5733 break; 5734 } 5735 case KVM_SET_TSC_KHZ: { 5736 u32 user_tsc_khz; 5737 5738 r = -EINVAL; 5739 user_tsc_khz = (u32)arg; 5740 5741 if (kvm_caps.has_tsc_control && 5742 user_tsc_khz >= kvm_caps.max_guest_tsc_khz) 5743 goto out; 5744 5745 if (user_tsc_khz == 0) 5746 user_tsc_khz = tsc_khz; 5747 5748 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5749 r = 0; 5750 5751 goto out; 5752 } 5753 case KVM_GET_TSC_KHZ: { 5754 r = vcpu->arch.virtual_tsc_khz; 5755 goto out; 5756 } 5757 case KVM_KVMCLOCK_CTRL: { 5758 r = kvm_set_guest_paused(vcpu); 5759 goto out; 5760 } 5761 case KVM_ENABLE_CAP: { 5762 struct kvm_enable_cap cap; 5763 5764 r = -EFAULT; 5765 if (copy_from_user(&cap, argp, sizeof(cap))) 5766 goto out; 5767 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5768 break; 5769 } 5770 case KVM_GET_NESTED_STATE: { 5771 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5772 u32 user_data_size; 5773 5774 r = -EINVAL; 5775 if (!kvm_x86_ops.nested_ops->get_state) 5776 break; 5777 5778 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5779 r = -EFAULT; 5780 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5781 break; 5782 5783 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5784 user_data_size); 5785 if (r < 0) 5786 break; 5787 5788 if (r > user_data_size) { 5789 if (put_user(r, &user_kvm_nested_state->size)) 5790 r = -EFAULT; 5791 else 5792 r = -E2BIG; 5793 break; 5794 } 5795 5796 r = 0; 5797 break; 5798 } 5799 case KVM_SET_NESTED_STATE: { 5800 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5801 struct kvm_nested_state kvm_state; 5802 int idx; 5803 5804 r = -EINVAL; 5805 if (!kvm_x86_ops.nested_ops->set_state) 5806 break; 5807 5808 r = -EFAULT; 5809 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5810 break; 5811 5812 r = -EINVAL; 5813 if (kvm_state.size < sizeof(kvm_state)) 5814 break; 5815 5816 if (kvm_state.flags & 5817 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5818 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5819 | KVM_STATE_NESTED_GIF_SET)) 5820 break; 5821 5822 /* nested_run_pending implies guest_mode. */ 5823 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5824 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5825 break; 5826 5827 idx = srcu_read_lock(&vcpu->kvm->srcu); 5828 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5829 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5830 break; 5831 } 5832 case KVM_GET_SUPPORTED_HV_CPUID: 5833 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5834 break; 5835 #ifdef CONFIG_KVM_XEN 5836 case KVM_XEN_VCPU_GET_ATTR: { 5837 struct kvm_xen_vcpu_attr xva; 5838 5839 r = -EFAULT; 5840 if (copy_from_user(&xva, argp, sizeof(xva))) 5841 goto out; 5842 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5843 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5844 r = -EFAULT; 5845 break; 5846 } 5847 case KVM_XEN_VCPU_SET_ATTR: { 5848 struct kvm_xen_vcpu_attr xva; 5849 5850 r = -EFAULT; 5851 if (copy_from_user(&xva, argp, sizeof(xva))) 5852 goto out; 5853 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5854 break; 5855 } 5856 #endif 5857 case KVM_GET_SREGS2: { 5858 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5859 r = -ENOMEM; 5860 if (!u.sregs2) 5861 goto out; 5862 __get_sregs2(vcpu, u.sregs2); 5863 r = -EFAULT; 5864 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5865 goto out; 5866 r = 0; 5867 break; 5868 } 5869 case KVM_SET_SREGS2: { 5870 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5871 if (IS_ERR(u.sregs2)) { 5872 r = PTR_ERR(u.sregs2); 5873 u.sregs2 = NULL; 5874 goto out; 5875 } 5876 r = __set_sregs2(vcpu, u.sregs2); 5877 break; 5878 } 5879 case KVM_HAS_DEVICE_ATTR: 5880 case KVM_GET_DEVICE_ATTR: 5881 case KVM_SET_DEVICE_ATTR: 5882 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 5883 break; 5884 default: 5885 r = -EINVAL; 5886 } 5887 out: 5888 kfree(u.buffer); 5889 out_nofree: 5890 vcpu_put(vcpu); 5891 return r; 5892 } 5893 5894 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5895 { 5896 return VM_FAULT_SIGBUS; 5897 } 5898 5899 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5900 { 5901 int ret; 5902 5903 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5904 return -EINVAL; 5905 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5906 return ret; 5907 } 5908 5909 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5910 u64 ident_addr) 5911 { 5912 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5913 } 5914 5915 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5916 unsigned long kvm_nr_mmu_pages) 5917 { 5918 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5919 return -EINVAL; 5920 5921 mutex_lock(&kvm->slots_lock); 5922 5923 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5924 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5925 5926 mutex_unlock(&kvm->slots_lock); 5927 return 0; 5928 } 5929 5930 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5931 { 5932 return kvm->arch.n_max_mmu_pages; 5933 } 5934 5935 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5936 { 5937 struct kvm_pic *pic = kvm->arch.vpic; 5938 int r; 5939 5940 r = 0; 5941 switch (chip->chip_id) { 5942 case KVM_IRQCHIP_PIC_MASTER: 5943 memcpy(&chip->chip.pic, &pic->pics[0], 5944 sizeof(struct kvm_pic_state)); 5945 break; 5946 case KVM_IRQCHIP_PIC_SLAVE: 5947 memcpy(&chip->chip.pic, &pic->pics[1], 5948 sizeof(struct kvm_pic_state)); 5949 break; 5950 case KVM_IRQCHIP_IOAPIC: 5951 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5952 break; 5953 default: 5954 r = -EINVAL; 5955 break; 5956 } 5957 return r; 5958 } 5959 5960 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5961 { 5962 struct kvm_pic *pic = kvm->arch.vpic; 5963 int r; 5964 5965 r = 0; 5966 switch (chip->chip_id) { 5967 case KVM_IRQCHIP_PIC_MASTER: 5968 spin_lock(&pic->lock); 5969 memcpy(&pic->pics[0], &chip->chip.pic, 5970 sizeof(struct kvm_pic_state)); 5971 spin_unlock(&pic->lock); 5972 break; 5973 case KVM_IRQCHIP_PIC_SLAVE: 5974 spin_lock(&pic->lock); 5975 memcpy(&pic->pics[1], &chip->chip.pic, 5976 sizeof(struct kvm_pic_state)); 5977 spin_unlock(&pic->lock); 5978 break; 5979 case KVM_IRQCHIP_IOAPIC: 5980 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5981 break; 5982 default: 5983 r = -EINVAL; 5984 break; 5985 } 5986 kvm_pic_update_irq(pic); 5987 return r; 5988 } 5989 5990 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5991 { 5992 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5993 5994 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5995 5996 mutex_lock(&kps->lock); 5997 memcpy(ps, &kps->channels, sizeof(*ps)); 5998 mutex_unlock(&kps->lock); 5999 return 0; 6000 } 6001 6002 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 6003 { 6004 int i; 6005 struct kvm_pit *pit = kvm->arch.vpit; 6006 6007 mutex_lock(&pit->pit_state.lock); 6008 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 6009 for (i = 0; i < 3; i++) 6010 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 6011 mutex_unlock(&pit->pit_state.lock); 6012 return 0; 6013 } 6014 6015 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 6016 { 6017 mutex_lock(&kvm->arch.vpit->pit_state.lock); 6018 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 6019 sizeof(ps->channels)); 6020 ps->flags = kvm->arch.vpit->pit_state.flags; 6021 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 6022 memset(&ps->reserved, 0, sizeof(ps->reserved)); 6023 return 0; 6024 } 6025 6026 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 6027 { 6028 int start = 0; 6029 int i; 6030 u32 prev_legacy, cur_legacy; 6031 struct kvm_pit *pit = kvm->arch.vpit; 6032 6033 mutex_lock(&pit->pit_state.lock); 6034 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 6035 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 6036 if (!prev_legacy && cur_legacy) 6037 start = 1; 6038 memcpy(&pit->pit_state.channels, &ps->channels, 6039 sizeof(pit->pit_state.channels)); 6040 pit->pit_state.flags = ps->flags; 6041 for (i = 0; i < 3; i++) 6042 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 6043 start && i == 0); 6044 mutex_unlock(&pit->pit_state.lock); 6045 return 0; 6046 } 6047 6048 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 6049 struct kvm_reinject_control *control) 6050 { 6051 struct kvm_pit *pit = kvm->arch.vpit; 6052 6053 /* pit->pit_state.lock was overloaded to prevent userspace from getting 6054 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 6055 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 6056 */ 6057 mutex_lock(&pit->pit_state.lock); 6058 kvm_pit_set_reinject(pit, control->pit_reinject); 6059 mutex_unlock(&pit->pit_state.lock); 6060 6061 return 0; 6062 } 6063 6064 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 6065 { 6066 6067 /* 6068 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 6069 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 6070 * on all VM-Exits, thus we only need to kick running vCPUs to force a 6071 * VM-Exit. 6072 */ 6073 struct kvm_vcpu *vcpu; 6074 unsigned long i; 6075 6076 kvm_for_each_vcpu(i, vcpu, kvm) 6077 kvm_vcpu_kick(vcpu); 6078 } 6079 6080 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 6081 bool line_status) 6082 { 6083 if (!irqchip_in_kernel(kvm)) 6084 return -ENXIO; 6085 6086 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 6087 irq_event->irq, irq_event->level, 6088 line_status); 6089 return 0; 6090 } 6091 6092 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 6093 struct kvm_enable_cap *cap) 6094 { 6095 int r; 6096 6097 if (cap->flags) 6098 return -EINVAL; 6099 6100 switch (cap->cap) { 6101 case KVM_CAP_DISABLE_QUIRKS2: 6102 r = -EINVAL; 6103 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) 6104 break; 6105 fallthrough; 6106 case KVM_CAP_DISABLE_QUIRKS: 6107 kvm->arch.disabled_quirks = cap->args[0]; 6108 r = 0; 6109 break; 6110 case KVM_CAP_SPLIT_IRQCHIP: { 6111 mutex_lock(&kvm->lock); 6112 r = -EINVAL; 6113 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 6114 goto split_irqchip_unlock; 6115 r = -EEXIST; 6116 if (irqchip_in_kernel(kvm)) 6117 goto split_irqchip_unlock; 6118 if (kvm->created_vcpus) 6119 goto split_irqchip_unlock; 6120 r = kvm_setup_empty_irq_routing(kvm); 6121 if (r) 6122 goto split_irqchip_unlock; 6123 /* Pairs with irqchip_in_kernel. */ 6124 smp_wmb(); 6125 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 6126 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 6127 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 6128 r = 0; 6129 split_irqchip_unlock: 6130 mutex_unlock(&kvm->lock); 6131 break; 6132 } 6133 case KVM_CAP_X2APIC_API: 6134 r = -EINVAL; 6135 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 6136 break; 6137 6138 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 6139 kvm->arch.x2apic_format = true; 6140 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 6141 kvm->arch.x2apic_broadcast_quirk_disabled = true; 6142 6143 r = 0; 6144 break; 6145 case KVM_CAP_X86_DISABLE_EXITS: 6146 r = -EINVAL; 6147 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 6148 break; 6149 6150 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 6151 kvm_can_mwait_in_guest()) 6152 kvm->arch.mwait_in_guest = true; 6153 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 6154 kvm->arch.hlt_in_guest = true; 6155 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 6156 kvm->arch.pause_in_guest = true; 6157 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 6158 kvm->arch.cstate_in_guest = true; 6159 r = 0; 6160 break; 6161 case KVM_CAP_MSR_PLATFORM_INFO: 6162 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 6163 r = 0; 6164 break; 6165 case KVM_CAP_EXCEPTION_PAYLOAD: 6166 kvm->arch.exception_payload_enabled = cap->args[0]; 6167 r = 0; 6168 break; 6169 case KVM_CAP_X86_TRIPLE_FAULT_EVENT: 6170 kvm->arch.triple_fault_event = cap->args[0]; 6171 r = 0; 6172 break; 6173 case KVM_CAP_X86_USER_SPACE_MSR: 6174 kvm->arch.user_space_msr_mask = cap->args[0]; 6175 r = 0; 6176 break; 6177 case KVM_CAP_X86_BUS_LOCK_EXIT: 6178 r = -EINVAL; 6179 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 6180 break; 6181 6182 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 6183 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 6184 break; 6185 6186 if (kvm_caps.has_bus_lock_exit && 6187 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 6188 kvm->arch.bus_lock_detection_enabled = true; 6189 r = 0; 6190 break; 6191 #ifdef CONFIG_X86_SGX_KVM 6192 case KVM_CAP_SGX_ATTRIBUTE: { 6193 unsigned long allowed_attributes = 0; 6194 6195 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 6196 if (r) 6197 break; 6198 6199 /* KVM only supports the PROVISIONKEY privileged attribute. */ 6200 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 6201 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 6202 kvm->arch.sgx_provisioning_allowed = true; 6203 else 6204 r = -EINVAL; 6205 break; 6206 } 6207 #endif 6208 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 6209 r = -EINVAL; 6210 if (!kvm_x86_ops.vm_copy_enc_context_from) 6211 break; 6212 6213 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]); 6214 break; 6215 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 6216 r = -EINVAL; 6217 if (!kvm_x86_ops.vm_move_enc_context_from) 6218 break; 6219 6220 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]); 6221 break; 6222 case KVM_CAP_EXIT_HYPERCALL: 6223 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 6224 r = -EINVAL; 6225 break; 6226 } 6227 kvm->arch.hypercall_exit_enabled = cap->args[0]; 6228 r = 0; 6229 break; 6230 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 6231 r = -EINVAL; 6232 if (cap->args[0] & ~1) 6233 break; 6234 kvm->arch.exit_on_emulation_error = cap->args[0]; 6235 r = 0; 6236 break; 6237 case KVM_CAP_PMU_CAPABILITY: 6238 r = -EINVAL; 6239 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) 6240 break; 6241 6242 mutex_lock(&kvm->lock); 6243 if (!kvm->created_vcpus) { 6244 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); 6245 r = 0; 6246 } 6247 mutex_unlock(&kvm->lock); 6248 break; 6249 case KVM_CAP_MAX_VCPU_ID: 6250 r = -EINVAL; 6251 if (cap->args[0] > KVM_MAX_VCPU_IDS) 6252 break; 6253 6254 mutex_lock(&kvm->lock); 6255 if (kvm->arch.max_vcpu_ids == cap->args[0]) { 6256 r = 0; 6257 } else if (!kvm->arch.max_vcpu_ids) { 6258 kvm->arch.max_vcpu_ids = cap->args[0]; 6259 r = 0; 6260 } 6261 mutex_unlock(&kvm->lock); 6262 break; 6263 case KVM_CAP_X86_NOTIFY_VMEXIT: 6264 r = -EINVAL; 6265 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS) 6266 break; 6267 if (!kvm_caps.has_notify_vmexit) 6268 break; 6269 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED)) 6270 break; 6271 mutex_lock(&kvm->lock); 6272 if (!kvm->created_vcpus) { 6273 kvm->arch.notify_window = cap->args[0] >> 32; 6274 kvm->arch.notify_vmexit_flags = (u32)cap->args[0]; 6275 r = 0; 6276 } 6277 mutex_unlock(&kvm->lock); 6278 break; 6279 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: 6280 r = -EINVAL; 6281 6282 /* 6283 * Since the risk of disabling NX hugepages is a guest crashing 6284 * the system, ensure the userspace process has permission to 6285 * reboot the system. 6286 * 6287 * Note that unlike the reboot() syscall, the process must have 6288 * this capability in the root namespace because exposing 6289 * /dev/kvm into a container does not limit the scope of the 6290 * iTLB multihit bug to that container. In other words, 6291 * this must use capable(), not ns_capable(). 6292 */ 6293 if (!capable(CAP_SYS_BOOT)) { 6294 r = -EPERM; 6295 break; 6296 } 6297 6298 if (cap->args[0]) 6299 break; 6300 6301 mutex_lock(&kvm->lock); 6302 if (!kvm->created_vcpus) { 6303 kvm->arch.disable_nx_huge_pages = true; 6304 r = 0; 6305 } 6306 mutex_unlock(&kvm->lock); 6307 break; 6308 default: 6309 r = -EINVAL; 6310 break; 6311 } 6312 return r; 6313 } 6314 6315 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 6316 { 6317 struct kvm_x86_msr_filter *msr_filter; 6318 6319 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 6320 if (!msr_filter) 6321 return NULL; 6322 6323 msr_filter->default_allow = default_allow; 6324 return msr_filter; 6325 } 6326 6327 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 6328 { 6329 u32 i; 6330 6331 if (!msr_filter) 6332 return; 6333 6334 for (i = 0; i < msr_filter->count; i++) 6335 kfree(msr_filter->ranges[i].bitmap); 6336 6337 kfree(msr_filter); 6338 } 6339 6340 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 6341 struct kvm_msr_filter_range *user_range) 6342 { 6343 unsigned long *bitmap = NULL; 6344 size_t bitmap_size; 6345 6346 if (!user_range->nmsrs) 6347 return 0; 6348 6349 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 6350 return -EINVAL; 6351 6352 if (!user_range->flags) 6353 return -EINVAL; 6354 6355 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 6356 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 6357 return -EINVAL; 6358 6359 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 6360 if (IS_ERR(bitmap)) 6361 return PTR_ERR(bitmap); 6362 6363 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 6364 .flags = user_range->flags, 6365 .base = user_range->base, 6366 .nmsrs = user_range->nmsrs, 6367 .bitmap = bitmap, 6368 }; 6369 6370 msr_filter->count++; 6371 return 0; 6372 } 6373 6374 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 6375 { 6376 struct kvm_msr_filter __user *user_msr_filter = argp; 6377 struct kvm_x86_msr_filter *new_filter, *old_filter; 6378 struct kvm_msr_filter filter; 6379 bool default_allow; 6380 bool empty = true; 6381 int r = 0; 6382 u32 i; 6383 6384 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 6385 return -EFAULT; 6386 6387 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 6388 empty &= !filter.ranges[i].nmsrs; 6389 6390 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 6391 if (empty && !default_allow) 6392 return -EINVAL; 6393 6394 new_filter = kvm_alloc_msr_filter(default_allow); 6395 if (!new_filter) 6396 return -ENOMEM; 6397 6398 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 6399 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 6400 if (r) { 6401 kvm_free_msr_filter(new_filter); 6402 return r; 6403 } 6404 } 6405 6406 mutex_lock(&kvm->lock); 6407 6408 /* The per-VM filter is protected by kvm->lock... */ 6409 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 6410 6411 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 6412 synchronize_srcu(&kvm->srcu); 6413 6414 kvm_free_msr_filter(old_filter); 6415 6416 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 6417 mutex_unlock(&kvm->lock); 6418 6419 return 0; 6420 } 6421 6422 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 6423 static int kvm_arch_suspend_notifier(struct kvm *kvm) 6424 { 6425 struct kvm_vcpu *vcpu; 6426 unsigned long i; 6427 int ret = 0; 6428 6429 mutex_lock(&kvm->lock); 6430 kvm_for_each_vcpu(i, vcpu, kvm) { 6431 if (!vcpu->arch.pv_time.active) 6432 continue; 6433 6434 ret = kvm_set_guest_paused(vcpu); 6435 if (ret) { 6436 kvm_err("Failed to pause guest VCPU%d: %d\n", 6437 vcpu->vcpu_id, ret); 6438 break; 6439 } 6440 } 6441 mutex_unlock(&kvm->lock); 6442 6443 return ret ? NOTIFY_BAD : NOTIFY_DONE; 6444 } 6445 6446 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 6447 { 6448 switch (state) { 6449 case PM_HIBERNATION_PREPARE: 6450 case PM_SUSPEND_PREPARE: 6451 return kvm_arch_suspend_notifier(kvm); 6452 } 6453 6454 return NOTIFY_DONE; 6455 } 6456 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 6457 6458 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 6459 { 6460 struct kvm_clock_data data = { 0 }; 6461 6462 get_kvmclock(kvm, &data); 6463 if (copy_to_user(argp, &data, sizeof(data))) 6464 return -EFAULT; 6465 6466 return 0; 6467 } 6468 6469 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 6470 { 6471 struct kvm_arch *ka = &kvm->arch; 6472 struct kvm_clock_data data; 6473 u64 now_raw_ns; 6474 6475 if (copy_from_user(&data, argp, sizeof(data))) 6476 return -EFAULT; 6477 6478 /* 6479 * Only KVM_CLOCK_REALTIME is used, but allow passing the 6480 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 6481 */ 6482 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 6483 return -EINVAL; 6484 6485 kvm_hv_request_tsc_page_update(kvm); 6486 kvm_start_pvclock_update(kvm); 6487 pvclock_update_vm_gtod_copy(kvm); 6488 6489 /* 6490 * This pairs with kvm_guest_time_update(): when masterclock is 6491 * in use, we use master_kernel_ns + kvmclock_offset to set 6492 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6493 * is slightly ahead) here we risk going negative on unsigned 6494 * 'system_time' when 'data.clock' is very small. 6495 */ 6496 if (data.flags & KVM_CLOCK_REALTIME) { 6497 u64 now_real_ns = ktime_get_real_ns(); 6498 6499 /* 6500 * Avoid stepping the kvmclock backwards. 6501 */ 6502 if (now_real_ns > data.realtime) 6503 data.clock += now_real_ns - data.realtime; 6504 } 6505 6506 if (ka->use_master_clock) 6507 now_raw_ns = ka->master_kernel_ns; 6508 else 6509 now_raw_ns = get_kvmclock_base_ns(); 6510 ka->kvmclock_offset = data.clock - now_raw_ns; 6511 kvm_end_pvclock_update(kvm); 6512 return 0; 6513 } 6514 6515 long kvm_arch_vm_ioctl(struct file *filp, 6516 unsigned int ioctl, unsigned long arg) 6517 { 6518 struct kvm *kvm = filp->private_data; 6519 void __user *argp = (void __user *)arg; 6520 int r = -ENOTTY; 6521 /* 6522 * This union makes it completely explicit to gcc-3.x 6523 * that these two variables' stack usage should be 6524 * combined, not added together. 6525 */ 6526 union { 6527 struct kvm_pit_state ps; 6528 struct kvm_pit_state2 ps2; 6529 struct kvm_pit_config pit_config; 6530 } u; 6531 6532 switch (ioctl) { 6533 case KVM_SET_TSS_ADDR: 6534 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 6535 break; 6536 case KVM_SET_IDENTITY_MAP_ADDR: { 6537 u64 ident_addr; 6538 6539 mutex_lock(&kvm->lock); 6540 r = -EINVAL; 6541 if (kvm->created_vcpus) 6542 goto set_identity_unlock; 6543 r = -EFAULT; 6544 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 6545 goto set_identity_unlock; 6546 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 6547 set_identity_unlock: 6548 mutex_unlock(&kvm->lock); 6549 break; 6550 } 6551 case KVM_SET_NR_MMU_PAGES: 6552 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 6553 break; 6554 case KVM_GET_NR_MMU_PAGES: 6555 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 6556 break; 6557 case KVM_CREATE_IRQCHIP: { 6558 mutex_lock(&kvm->lock); 6559 6560 r = -EEXIST; 6561 if (irqchip_in_kernel(kvm)) 6562 goto create_irqchip_unlock; 6563 6564 r = -EINVAL; 6565 if (kvm->created_vcpus) 6566 goto create_irqchip_unlock; 6567 6568 r = kvm_pic_init(kvm); 6569 if (r) 6570 goto create_irqchip_unlock; 6571 6572 r = kvm_ioapic_init(kvm); 6573 if (r) { 6574 kvm_pic_destroy(kvm); 6575 goto create_irqchip_unlock; 6576 } 6577 6578 r = kvm_setup_default_irq_routing(kvm); 6579 if (r) { 6580 kvm_ioapic_destroy(kvm); 6581 kvm_pic_destroy(kvm); 6582 goto create_irqchip_unlock; 6583 } 6584 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 6585 smp_wmb(); 6586 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 6587 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 6588 create_irqchip_unlock: 6589 mutex_unlock(&kvm->lock); 6590 break; 6591 } 6592 case KVM_CREATE_PIT: 6593 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 6594 goto create_pit; 6595 case KVM_CREATE_PIT2: 6596 r = -EFAULT; 6597 if (copy_from_user(&u.pit_config, argp, 6598 sizeof(struct kvm_pit_config))) 6599 goto out; 6600 create_pit: 6601 mutex_lock(&kvm->lock); 6602 r = -EEXIST; 6603 if (kvm->arch.vpit) 6604 goto create_pit_unlock; 6605 r = -ENOMEM; 6606 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 6607 if (kvm->arch.vpit) 6608 r = 0; 6609 create_pit_unlock: 6610 mutex_unlock(&kvm->lock); 6611 break; 6612 case KVM_GET_IRQCHIP: { 6613 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6614 struct kvm_irqchip *chip; 6615 6616 chip = memdup_user(argp, sizeof(*chip)); 6617 if (IS_ERR(chip)) { 6618 r = PTR_ERR(chip); 6619 goto out; 6620 } 6621 6622 r = -ENXIO; 6623 if (!irqchip_kernel(kvm)) 6624 goto get_irqchip_out; 6625 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 6626 if (r) 6627 goto get_irqchip_out; 6628 r = -EFAULT; 6629 if (copy_to_user(argp, chip, sizeof(*chip))) 6630 goto get_irqchip_out; 6631 r = 0; 6632 get_irqchip_out: 6633 kfree(chip); 6634 break; 6635 } 6636 case KVM_SET_IRQCHIP: { 6637 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6638 struct kvm_irqchip *chip; 6639 6640 chip = memdup_user(argp, sizeof(*chip)); 6641 if (IS_ERR(chip)) { 6642 r = PTR_ERR(chip); 6643 goto out; 6644 } 6645 6646 r = -ENXIO; 6647 if (!irqchip_kernel(kvm)) 6648 goto set_irqchip_out; 6649 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 6650 set_irqchip_out: 6651 kfree(chip); 6652 break; 6653 } 6654 case KVM_GET_PIT: { 6655 r = -EFAULT; 6656 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 6657 goto out; 6658 r = -ENXIO; 6659 if (!kvm->arch.vpit) 6660 goto out; 6661 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 6662 if (r) 6663 goto out; 6664 r = -EFAULT; 6665 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 6666 goto out; 6667 r = 0; 6668 break; 6669 } 6670 case KVM_SET_PIT: { 6671 r = -EFAULT; 6672 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 6673 goto out; 6674 mutex_lock(&kvm->lock); 6675 r = -ENXIO; 6676 if (!kvm->arch.vpit) 6677 goto set_pit_out; 6678 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 6679 set_pit_out: 6680 mutex_unlock(&kvm->lock); 6681 break; 6682 } 6683 case KVM_GET_PIT2: { 6684 r = -ENXIO; 6685 if (!kvm->arch.vpit) 6686 goto out; 6687 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 6688 if (r) 6689 goto out; 6690 r = -EFAULT; 6691 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 6692 goto out; 6693 r = 0; 6694 break; 6695 } 6696 case KVM_SET_PIT2: { 6697 r = -EFAULT; 6698 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 6699 goto out; 6700 mutex_lock(&kvm->lock); 6701 r = -ENXIO; 6702 if (!kvm->arch.vpit) 6703 goto set_pit2_out; 6704 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6705 set_pit2_out: 6706 mutex_unlock(&kvm->lock); 6707 break; 6708 } 6709 case KVM_REINJECT_CONTROL: { 6710 struct kvm_reinject_control control; 6711 r = -EFAULT; 6712 if (copy_from_user(&control, argp, sizeof(control))) 6713 goto out; 6714 r = -ENXIO; 6715 if (!kvm->arch.vpit) 6716 goto out; 6717 r = kvm_vm_ioctl_reinject(kvm, &control); 6718 break; 6719 } 6720 case KVM_SET_BOOT_CPU_ID: 6721 r = 0; 6722 mutex_lock(&kvm->lock); 6723 if (kvm->created_vcpus) 6724 r = -EBUSY; 6725 else 6726 kvm->arch.bsp_vcpu_id = arg; 6727 mutex_unlock(&kvm->lock); 6728 break; 6729 #ifdef CONFIG_KVM_XEN 6730 case KVM_XEN_HVM_CONFIG: { 6731 struct kvm_xen_hvm_config xhc; 6732 r = -EFAULT; 6733 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6734 goto out; 6735 r = kvm_xen_hvm_config(kvm, &xhc); 6736 break; 6737 } 6738 case KVM_XEN_HVM_GET_ATTR: { 6739 struct kvm_xen_hvm_attr xha; 6740 6741 r = -EFAULT; 6742 if (copy_from_user(&xha, argp, sizeof(xha))) 6743 goto out; 6744 r = kvm_xen_hvm_get_attr(kvm, &xha); 6745 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6746 r = -EFAULT; 6747 break; 6748 } 6749 case KVM_XEN_HVM_SET_ATTR: { 6750 struct kvm_xen_hvm_attr xha; 6751 6752 r = -EFAULT; 6753 if (copy_from_user(&xha, argp, sizeof(xha))) 6754 goto out; 6755 r = kvm_xen_hvm_set_attr(kvm, &xha); 6756 break; 6757 } 6758 case KVM_XEN_HVM_EVTCHN_SEND: { 6759 struct kvm_irq_routing_xen_evtchn uxe; 6760 6761 r = -EFAULT; 6762 if (copy_from_user(&uxe, argp, sizeof(uxe))) 6763 goto out; 6764 r = kvm_xen_hvm_evtchn_send(kvm, &uxe); 6765 break; 6766 } 6767 #endif 6768 case KVM_SET_CLOCK: 6769 r = kvm_vm_ioctl_set_clock(kvm, argp); 6770 break; 6771 case KVM_GET_CLOCK: 6772 r = kvm_vm_ioctl_get_clock(kvm, argp); 6773 break; 6774 case KVM_SET_TSC_KHZ: { 6775 u32 user_tsc_khz; 6776 6777 r = -EINVAL; 6778 user_tsc_khz = (u32)arg; 6779 6780 if (kvm_caps.has_tsc_control && 6781 user_tsc_khz >= kvm_caps.max_guest_tsc_khz) 6782 goto out; 6783 6784 if (user_tsc_khz == 0) 6785 user_tsc_khz = tsc_khz; 6786 6787 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz); 6788 r = 0; 6789 6790 goto out; 6791 } 6792 case KVM_GET_TSC_KHZ: { 6793 r = READ_ONCE(kvm->arch.default_tsc_khz); 6794 goto out; 6795 } 6796 case KVM_MEMORY_ENCRYPT_OP: { 6797 r = -ENOTTY; 6798 if (!kvm_x86_ops.mem_enc_ioctl) 6799 goto out; 6800 6801 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp); 6802 break; 6803 } 6804 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6805 struct kvm_enc_region region; 6806 6807 r = -EFAULT; 6808 if (copy_from_user(®ion, argp, sizeof(region))) 6809 goto out; 6810 6811 r = -ENOTTY; 6812 if (!kvm_x86_ops.mem_enc_register_region) 6813 goto out; 6814 6815 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion); 6816 break; 6817 } 6818 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6819 struct kvm_enc_region region; 6820 6821 r = -EFAULT; 6822 if (copy_from_user(®ion, argp, sizeof(region))) 6823 goto out; 6824 6825 r = -ENOTTY; 6826 if (!kvm_x86_ops.mem_enc_unregister_region) 6827 goto out; 6828 6829 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion); 6830 break; 6831 } 6832 case KVM_HYPERV_EVENTFD: { 6833 struct kvm_hyperv_eventfd hvevfd; 6834 6835 r = -EFAULT; 6836 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6837 goto out; 6838 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6839 break; 6840 } 6841 case KVM_SET_PMU_EVENT_FILTER: 6842 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6843 break; 6844 case KVM_X86_SET_MSR_FILTER: 6845 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6846 break; 6847 default: 6848 r = -ENOTTY; 6849 } 6850 out: 6851 return r; 6852 } 6853 6854 static void kvm_init_msr_list(void) 6855 { 6856 u32 dummy[2]; 6857 unsigned i; 6858 6859 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3, 6860 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6861 6862 num_msrs_to_save = 0; 6863 num_emulated_msrs = 0; 6864 num_msr_based_features = 0; 6865 6866 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6867 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6868 continue; 6869 6870 /* 6871 * Even MSRs that are valid in the host may not be exposed 6872 * to the guests in some cases. 6873 */ 6874 switch (msrs_to_save_all[i]) { 6875 case MSR_IA32_BNDCFGS: 6876 if (!kvm_mpx_supported()) 6877 continue; 6878 break; 6879 case MSR_TSC_AUX: 6880 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6881 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6882 continue; 6883 break; 6884 case MSR_IA32_UMWAIT_CONTROL: 6885 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6886 continue; 6887 break; 6888 case MSR_IA32_RTIT_CTL: 6889 case MSR_IA32_RTIT_STATUS: 6890 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6891 continue; 6892 break; 6893 case MSR_IA32_RTIT_CR3_MATCH: 6894 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6895 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6896 continue; 6897 break; 6898 case MSR_IA32_RTIT_OUTPUT_BASE: 6899 case MSR_IA32_RTIT_OUTPUT_MASK: 6900 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6901 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6902 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6903 continue; 6904 break; 6905 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6906 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6907 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6908 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6909 continue; 6910 break; 6911 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6912 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6913 min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) 6914 continue; 6915 break; 6916 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6917 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6918 min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) 6919 continue; 6920 break; 6921 case MSR_IA32_XFD: 6922 case MSR_IA32_XFD_ERR: 6923 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 6924 continue; 6925 break; 6926 default: 6927 break; 6928 } 6929 6930 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6931 } 6932 6933 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6934 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6935 continue; 6936 6937 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6938 } 6939 6940 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6941 struct kvm_msr_entry msr; 6942 6943 msr.index = msr_based_features_all[i]; 6944 if (kvm_get_msr_feature(&msr)) 6945 continue; 6946 6947 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6948 } 6949 } 6950 6951 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6952 const void *v) 6953 { 6954 int handled = 0; 6955 int n; 6956 6957 do { 6958 n = min(len, 8); 6959 if (!(lapic_in_kernel(vcpu) && 6960 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6961 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6962 break; 6963 handled += n; 6964 addr += n; 6965 len -= n; 6966 v += n; 6967 } while (len); 6968 6969 return handled; 6970 } 6971 6972 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6973 { 6974 int handled = 0; 6975 int n; 6976 6977 do { 6978 n = min(len, 8); 6979 if (!(lapic_in_kernel(vcpu) && 6980 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6981 addr, n, v)) 6982 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6983 break; 6984 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6985 handled += n; 6986 addr += n; 6987 len -= n; 6988 v += n; 6989 } while (len); 6990 6991 return handled; 6992 } 6993 6994 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6995 struct kvm_segment *var, int seg) 6996 { 6997 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6998 } 6999 7000 void kvm_get_segment(struct kvm_vcpu *vcpu, 7001 struct kvm_segment *var, int seg) 7002 { 7003 static_call(kvm_x86_get_segment)(vcpu, var, seg); 7004 } 7005 7006 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, 7007 struct x86_exception *exception) 7008 { 7009 struct kvm_mmu *mmu = vcpu->arch.mmu; 7010 gpa_t t_gpa; 7011 7012 BUG_ON(!mmu_is_nested(vcpu)); 7013 7014 /* NPT walks are always user-walks */ 7015 access |= PFERR_USER_MASK; 7016 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); 7017 7018 return t_gpa; 7019 } 7020 7021 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 7022 struct x86_exception *exception) 7023 { 7024 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7025 7026 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7027 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7028 } 7029 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 7030 7031 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 7032 struct x86_exception *exception) 7033 { 7034 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7035 7036 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7037 access |= PFERR_FETCH_MASK; 7038 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7039 } 7040 7041 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 7042 struct x86_exception *exception) 7043 { 7044 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7045 7046 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7047 access |= PFERR_WRITE_MASK; 7048 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7049 } 7050 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 7051 7052 /* uses this to access any guest's mapped memory without checking CPL */ 7053 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 7054 struct x86_exception *exception) 7055 { 7056 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7057 7058 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); 7059 } 7060 7061 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 7062 struct kvm_vcpu *vcpu, u64 access, 7063 struct x86_exception *exception) 7064 { 7065 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7066 void *data = val; 7067 int r = X86EMUL_CONTINUE; 7068 7069 while (bytes) { 7070 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 7071 unsigned offset = addr & (PAGE_SIZE-1); 7072 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 7073 int ret; 7074 7075 if (gpa == UNMAPPED_GVA) 7076 return X86EMUL_PROPAGATE_FAULT; 7077 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 7078 offset, toread); 7079 if (ret < 0) { 7080 r = X86EMUL_IO_NEEDED; 7081 goto out; 7082 } 7083 7084 bytes -= toread; 7085 data += toread; 7086 addr += toread; 7087 } 7088 out: 7089 return r; 7090 } 7091 7092 /* used for instruction fetching */ 7093 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 7094 gva_t addr, void *val, unsigned int bytes, 7095 struct x86_exception *exception) 7096 { 7097 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7098 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7099 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7100 unsigned offset; 7101 int ret; 7102 7103 /* Inline kvm_read_guest_virt_helper for speed. */ 7104 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, 7105 exception); 7106 if (unlikely(gpa == UNMAPPED_GVA)) 7107 return X86EMUL_PROPAGATE_FAULT; 7108 7109 offset = addr & (PAGE_SIZE-1); 7110 if (WARN_ON(offset + bytes > PAGE_SIZE)) 7111 bytes = (unsigned)PAGE_SIZE - offset; 7112 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 7113 offset, bytes); 7114 if (unlikely(ret < 0)) 7115 return X86EMUL_IO_NEEDED; 7116 7117 return X86EMUL_CONTINUE; 7118 } 7119 7120 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 7121 gva_t addr, void *val, unsigned int bytes, 7122 struct x86_exception *exception) 7123 { 7124 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7125 7126 /* 7127 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 7128 * is returned, but our callers are not ready for that and they blindly 7129 * call kvm_inject_page_fault. Ensure that they at least do not leak 7130 * uninitialized kernel stack memory into cr2 and error code. 7131 */ 7132 memset(exception, 0, sizeof(*exception)); 7133 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 7134 exception); 7135 } 7136 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 7137 7138 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 7139 gva_t addr, void *val, unsigned int bytes, 7140 struct x86_exception *exception, bool system) 7141 { 7142 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7143 u64 access = 0; 7144 7145 if (system) 7146 access |= PFERR_IMPLICIT_ACCESS; 7147 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) 7148 access |= PFERR_USER_MASK; 7149 7150 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 7151 } 7152 7153 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 7154 unsigned long addr, void *val, unsigned int bytes) 7155 { 7156 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7157 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 7158 7159 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 7160 } 7161 7162 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 7163 struct kvm_vcpu *vcpu, u64 access, 7164 struct x86_exception *exception) 7165 { 7166 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7167 void *data = val; 7168 int r = X86EMUL_CONTINUE; 7169 7170 while (bytes) { 7171 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 7172 unsigned offset = addr & (PAGE_SIZE-1); 7173 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 7174 int ret; 7175 7176 if (gpa == UNMAPPED_GVA) 7177 return X86EMUL_PROPAGATE_FAULT; 7178 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 7179 if (ret < 0) { 7180 r = X86EMUL_IO_NEEDED; 7181 goto out; 7182 } 7183 7184 bytes -= towrite; 7185 data += towrite; 7186 addr += towrite; 7187 } 7188 out: 7189 return r; 7190 } 7191 7192 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 7193 unsigned int bytes, struct x86_exception *exception, 7194 bool system) 7195 { 7196 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7197 u64 access = PFERR_WRITE_MASK; 7198 7199 if (system) 7200 access |= PFERR_IMPLICIT_ACCESS; 7201 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) 7202 access |= PFERR_USER_MASK; 7203 7204 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7205 access, exception); 7206 } 7207 7208 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 7209 unsigned int bytes, struct x86_exception *exception) 7210 { 7211 /* kvm_write_guest_virt_system can pull in tons of pages. */ 7212 vcpu->arch.l1tf_flush_l1d = true; 7213 7214 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7215 PFERR_WRITE_MASK, exception); 7216 } 7217 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 7218 7219 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, 7220 void *insn, int insn_len) 7221 { 7222 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type, 7223 insn, insn_len); 7224 } 7225 7226 int handle_ud(struct kvm_vcpu *vcpu) 7227 { 7228 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 7229 int emul_type = EMULTYPE_TRAP_UD; 7230 char sig[5]; /* ud2; .ascii "kvm" */ 7231 struct x86_exception e; 7232 7233 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0))) 7234 return 1; 7235 7236 if (force_emulation_prefix && 7237 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 7238 sig, sizeof(sig), &e) == 0 && 7239 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 7240 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 7241 emul_type = EMULTYPE_TRAP_UD_FORCED; 7242 } 7243 7244 return kvm_emulate_instruction(vcpu, emul_type); 7245 } 7246 EXPORT_SYMBOL_GPL(handle_ud); 7247 7248 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7249 gpa_t gpa, bool write) 7250 { 7251 /* For APIC access vmexit */ 7252 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7253 return 1; 7254 7255 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 7256 trace_vcpu_match_mmio(gva, gpa, write, true); 7257 return 1; 7258 } 7259 7260 return 0; 7261 } 7262 7263 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7264 gpa_t *gpa, struct x86_exception *exception, 7265 bool write) 7266 { 7267 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7268 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 7269 | (write ? PFERR_WRITE_MASK : 0); 7270 7271 /* 7272 * currently PKRU is only applied to ept enabled guest so 7273 * there is no pkey in EPT page table for L1 guest or EPT 7274 * shadow page table for L2 guest. 7275 */ 7276 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 7277 !permission_fault(vcpu, vcpu->arch.walk_mmu, 7278 vcpu->arch.mmio_access, 0, access))) { 7279 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 7280 (gva & (PAGE_SIZE - 1)); 7281 trace_vcpu_match_mmio(gva, *gpa, write, false); 7282 return 1; 7283 } 7284 7285 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7286 7287 if (*gpa == UNMAPPED_GVA) 7288 return -1; 7289 7290 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 7291 } 7292 7293 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 7294 const void *val, int bytes) 7295 { 7296 int ret; 7297 7298 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 7299 if (ret < 0) 7300 return 0; 7301 kvm_page_track_write(vcpu, gpa, val, bytes); 7302 return 1; 7303 } 7304 7305 struct read_write_emulator_ops { 7306 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 7307 int bytes); 7308 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 7309 void *val, int bytes); 7310 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7311 int bytes, void *val); 7312 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7313 void *val, int bytes); 7314 bool write; 7315 }; 7316 7317 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 7318 { 7319 if (vcpu->mmio_read_completed) { 7320 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 7321 vcpu->mmio_fragments[0].gpa, val); 7322 vcpu->mmio_read_completed = 0; 7323 return 1; 7324 } 7325 7326 return 0; 7327 } 7328 7329 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7330 void *val, int bytes) 7331 { 7332 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 7333 } 7334 7335 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7336 void *val, int bytes) 7337 { 7338 return emulator_write_phys(vcpu, gpa, val, bytes); 7339 } 7340 7341 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 7342 { 7343 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 7344 return vcpu_mmio_write(vcpu, gpa, bytes, val); 7345 } 7346 7347 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7348 void *val, int bytes) 7349 { 7350 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 7351 return X86EMUL_IO_NEEDED; 7352 } 7353 7354 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7355 void *val, int bytes) 7356 { 7357 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 7358 7359 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 7360 return X86EMUL_CONTINUE; 7361 } 7362 7363 static const struct read_write_emulator_ops read_emultor = { 7364 .read_write_prepare = read_prepare, 7365 .read_write_emulate = read_emulate, 7366 .read_write_mmio = vcpu_mmio_read, 7367 .read_write_exit_mmio = read_exit_mmio, 7368 }; 7369 7370 static const struct read_write_emulator_ops write_emultor = { 7371 .read_write_emulate = write_emulate, 7372 .read_write_mmio = write_mmio, 7373 .read_write_exit_mmio = write_exit_mmio, 7374 .write = true, 7375 }; 7376 7377 static int emulator_read_write_onepage(unsigned long addr, void *val, 7378 unsigned int bytes, 7379 struct x86_exception *exception, 7380 struct kvm_vcpu *vcpu, 7381 const struct read_write_emulator_ops *ops) 7382 { 7383 gpa_t gpa; 7384 int handled, ret; 7385 bool write = ops->write; 7386 struct kvm_mmio_fragment *frag; 7387 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7388 7389 /* 7390 * If the exit was due to a NPF we may already have a GPA. 7391 * If the GPA is present, use it to avoid the GVA to GPA table walk. 7392 * Note, this cannot be used on string operations since string 7393 * operation using rep will only have the initial GPA from the NPF 7394 * occurred. 7395 */ 7396 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 7397 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 7398 gpa = ctxt->gpa_val; 7399 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 7400 } else { 7401 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 7402 if (ret < 0) 7403 return X86EMUL_PROPAGATE_FAULT; 7404 } 7405 7406 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 7407 return X86EMUL_CONTINUE; 7408 7409 /* 7410 * Is this MMIO handled locally? 7411 */ 7412 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 7413 if (handled == bytes) 7414 return X86EMUL_CONTINUE; 7415 7416 gpa += handled; 7417 bytes -= handled; 7418 val += handled; 7419 7420 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 7421 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 7422 frag->gpa = gpa; 7423 frag->data = val; 7424 frag->len = bytes; 7425 return X86EMUL_CONTINUE; 7426 } 7427 7428 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 7429 unsigned long addr, 7430 void *val, unsigned int bytes, 7431 struct x86_exception *exception, 7432 const struct read_write_emulator_ops *ops) 7433 { 7434 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7435 gpa_t gpa; 7436 int rc; 7437 7438 if (ops->read_write_prepare && 7439 ops->read_write_prepare(vcpu, val, bytes)) 7440 return X86EMUL_CONTINUE; 7441 7442 vcpu->mmio_nr_fragments = 0; 7443 7444 /* Crossing a page boundary? */ 7445 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 7446 int now; 7447 7448 now = -addr & ~PAGE_MASK; 7449 rc = emulator_read_write_onepage(addr, val, now, exception, 7450 vcpu, ops); 7451 7452 if (rc != X86EMUL_CONTINUE) 7453 return rc; 7454 addr += now; 7455 if (ctxt->mode != X86EMUL_MODE_PROT64) 7456 addr = (u32)addr; 7457 val += now; 7458 bytes -= now; 7459 } 7460 7461 rc = emulator_read_write_onepage(addr, val, bytes, exception, 7462 vcpu, ops); 7463 if (rc != X86EMUL_CONTINUE) 7464 return rc; 7465 7466 if (!vcpu->mmio_nr_fragments) 7467 return rc; 7468 7469 gpa = vcpu->mmio_fragments[0].gpa; 7470 7471 vcpu->mmio_needed = 1; 7472 vcpu->mmio_cur_fragment = 0; 7473 7474 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 7475 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 7476 vcpu->run->exit_reason = KVM_EXIT_MMIO; 7477 vcpu->run->mmio.phys_addr = gpa; 7478 7479 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 7480 } 7481 7482 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 7483 unsigned long addr, 7484 void *val, 7485 unsigned int bytes, 7486 struct x86_exception *exception) 7487 { 7488 return emulator_read_write(ctxt, addr, val, bytes, 7489 exception, &read_emultor); 7490 } 7491 7492 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 7493 unsigned long addr, 7494 const void *val, 7495 unsigned int bytes, 7496 struct x86_exception *exception) 7497 { 7498 return emulator_read_write(ctxt, addr, (void *)val, bytes, 7499 exception, &write_emultor); 7500 } 7501 7502 #define emulator_try_cmpxchg_user(t, ptr, old, new) \ 7503 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t)) 7504 7505 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 7506 unsigned long addr, 7507 const void *old, 7508 const void *new, 7509 unsigned int bytes, 7510 struct x86_exception *exception) 7511 { 7512 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7513 u64 page_line_mask; 7514 unsigned long hva; 7515 gpa_t gpa; 7516 int r; 7517 7518 /* guests cmpxchg8b have to be emulated atomically */ 7519 if (bytes > 8 || (bytes & (bytes - 1))) 7520 goto emul_write; 7521 7522 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 7523 7524 if (gpa == UNMAPPED_GVA || 7525 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7526 goto emul_write; 7527 7528 /* 7529 * Emulate the atomic as a straight write to avoid #AC if SLD is 7530 * enabled in the host and the access splits a cache line. 7531 */ 7532 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 7533 page_line_mask = ~(cache_line_size() - 1); 7534 else 7535 page_line_mask = PAGE_MASK; 7536 7537 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 7538 goto emul_write; 7539 7540 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa)); 7541 if (kvm_is_error_hva(hva)) 7542 goto emul_write; 7543 7544 hva += offset_in_page(gpa); 7545 7546 switch (bytes) { 7547 case 1: 7548 r = emulator_try_cmpxchg_user(u8, hva, old, new); 7549 break; 7550 case 2: 7551 r = emulator_try_cmpxchg_user(u16, hva, old, new); 7552 break; 7553 case 4: 7554 r = emulator_try_cmpxchg_user(u32, hva, old, new); 7555 break; 7556 case 8: 7557 r = emulator_try_cmpxchg_user(u64, hva, old, new); 7558 break; 7559 default: 7560 BUG(); 7561 } 7562 7563 if (r < 0) 7564 return X86EMUL_UNHANDLEABLE; 7565 if (r) 7566 return X86EMUL_CMPXCHG_FAILED; 7567 7568 kvm_page_track_write(vcpu, gpa, new, bytes); 7569 7570 return X86EMUL_CONTINUE; 7571 7572 emul_write: 7573 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 7574 7575 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 7576 } 7577 7578 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 7579 unsigned short port, 7580 unsigned int count, bool in) 7581 { 7582 void *data = vcpu->arch.pio_data; 7583 unsigned i; 7584 int r; 7585 7586 vcpu->arch.pio.port = port; 7587 vcpu->arch.pio.in = in; 7588 vcpu->arch.pio.count = count; 7589 vcpu->arch.pio.size = size; 7590 7591 for (i = 0; i < count; i++) { 7592 if (in) 7593 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data); 7594 else 7595 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data); 7596 if (r) 7597 goto userspace_io; 7598 data += size; 7599 } 7600 return 1; 7601 7602 userspace_io: 7603 vcpu->run->exit_reason = KVM_EXIT_IO; 7604 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 7605 vcpu->run->io.size = size; 7606 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 7607 vcpu->run->io.count = count; 7608 vcpu->run->io.port = port; 7609 7610 return 0; 7611 } 7612 7613 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7614 unsigned short port, unsigned int count) 7615 { 7616 WARN_ON(vcpu->arch.pio.count); 7617 memset(vcpu->arch.pio_data, 0, size * count); 7618 return emulator_pio_in_out(vcpu, size, port, count, true); 7619 } 7620 7621 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 7622 { 7623 int size = vcpu->arch.pio.size; 7624 unsigned count = vcpu->arch.pio.count; 7625 memcpy(val, vcpu->arch.pio_data, size * count); 7626 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 7627 vcpu->arch.pio.count = 0; 7628 } 7629 7630 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7631 unsigned short port, void *val, unsigned int count) 7632 { 7633 if (vcpu->arch.pio.count) { 7634 /* 7635 * Complete a previous iteration that required userspace I/O. 7636 * Note, @count isn't guaranteed to match pio.count as userspace 7637 * can modify ECX before rerunning the vCPU. Ignore any such 7638 * shenanigans as KVM doesn't support modifying the rep count, 7639 * and the emulator ensures @count doesn't overflow the buffer. 7640 */ 7641 } else { 7642 int r = __emulator_pio_in(vcpu, size, port, count); 7643 if (!r) 7644 return r; 7645 7646 /* Results already available, fall through. */ 7647 } 7648 7649 complete_emulator_pio_in(vcpu, val); 7650 return 1; 7651 } 7652 7653 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 7654 int size, unsigned short port, void *val, 7655 unsigned int count) 7656 { 7657 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 7658 7659 } 7660 7661 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 7662 unsigned short port, const void *val, 7663 unsigned int count) 7664 { 7665 int ret; 7666 7667 memcpy(vcpu->arch.pio_data, val, size * count); 7668 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 7669 ret = emulator_pio_in_out(vcpu, size, port, count, false); 7670 if (ret) 7671 vcpu->arch.pio.count = 0; 7672 7673 return ret; 7674 } 7675 7676 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 7677 int size, unsigned short port, 7678 const void *val, unsigned int count) 7679 { 7680 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 7681 } 7682 7683 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 7684 { 7685 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 7686 } 7687 7688 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 7689 { 7690 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 7691 } 7692 7693 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 7694 { 7695 if (!need_emulate_wbinvd(vcpu)) 7696 return X86EMUL_CONTINUE; 7697 7698 if (static_call(kvm_x86_has_wbinvd_exit)()) { 7699 int cpu = get_cpu(); 7700 7701 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 7702 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 7703 wbinvd_ipi, NULL, 1); 7704 put_cpu(); 7705 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 7706 } else 7707 wbinvd(); 7708 return X86EMUL_CONTINUE; 7709 } 7710 7711 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 7712 { 7713 kvm_emulate_wbinvd_noskip(vcpu); 7714 return kvm_skip_emulated_instruction(vcpu); 7715 } 7716 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 7717 7718 7719 7720 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 7721 { 7722 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 7723 } 7724 7725 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7726 unsigned long *dest) 7727 { 7728 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7729 } 7730 7731 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7732 unsigned long value) 7733 { 7734 7735 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7736 } 7737 7738 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7739 { 7740 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7741 } 7742 7743 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 7744 { 7745 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7746 unsigned long value; 7747 7748 switch (cr) { 7749 case 0: 7750 value = kvm_read_cr0(vcpu); 7751 break; 7752 case 2: 7753 value = vcpu->arch.cr2; 7754 break; 7755 case 3: 7756 value = kvm_read_cr3(vcpu); 7757 break; 7758 case 4: 7759 value = kvm_read_cr4(vcpu); 7760 break; 7761 case 8: 7762 value = kvm_get_cr8(vcpu); 7763 break; 7764 default: 7765 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7766 return 0; 7767 } 7768 7769 return value; 7770 } 7771 7772 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 7773 { 7774 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7775 int res = 0; 7776 7777 switch (cr) { 7778 case 0: 7779 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 7780 break; 7781 case 2: 7782 vcpu->arch.cr2 = val; 7783 break; 7784 case 3: 7785 res = kvm_set_cr3(vcpu, val); 7786 break; 7787 case 4: 7788 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 7789 break; 7790 case 8: 7791 res = kvm_set_cr8(vcpu, val); 7792 break; 7793 default: 7794 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7795 res = -1; 7796 } 7797 7798 return res; 7799 } 7800 7801 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 7802 { 7803 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 7804 } 7805 7806 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7807 { 7808 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7809 } 7810 7811 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7812 { 7813 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7814 } 7815 7816 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7817 { 7818 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7819 } 7820 7821 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7822 { 7823 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7824 } 7825 7826 static unsigned long emulator_get_cached_segment_base( 7827 struct x86_emulate_ctxt *ctxt, int seg) 7828 { 7829 return get_segment_base(emul_to_vcpu(ctxt), seg); 7830 } 7831 7832 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7833 struct desc_struct *desc, u32 *base3, 7834 int seg) 7835 { 7836 struct kvm_segment var; 7837 7838 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7839 *selector = var.selector; 7840 7841 if (var.unusable) { 7842 memset(desc, 0, sizeof(*desc)); 7843 if (base3) 7844 *base3 = 0; 7845 return false; 7846 } 7847 7848 if (var.g) 7849 var.limit >>= 12; 7850 set_desc_limit(desc, var.limit); 7851 set_desc_base(desc, (unsigned long)var.base); 7852 #ifdef CONFIG_X86_64 7853 if (base3) 7854 *base3 = var.base >> 32; 7855 #endif 7856 desc->type = var.type; 7857 desc->s = var.s; 7858 desc->dpl = var.dpl; 7859 desc->p = var.present; 7860 desc->avl = var.avl; 7861 desc->l = var.l; 7862 desc->d = var.db; 7863 desc->g = var.g; 7864 7865 return true; 7866 } 7867 7868 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7869 struct desc_struct *desc, u32 base3, 7870 int seg) 7871 { 7872 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7873 struct kvm_segment var; 7874 7875 var.selector = selector; 7876 var.base = get_desc_base(desc); 7877 #ifdef CONFIG_X86_64 7878 var.base |= ((u64)base3) << 32; 7879 #endif 7880 var.limit = get_desc_limit(desc); 7881 if (desc->g) 7882 var.limit = (var.limit << 12) | 0xfff; 7883 var.type = desc->type; 7884 var.dpl = desc->dpl; 7885 var.db = desc->d; 7886 var.s = desc->s; 7887 var.l = desc->l; 7888 var.g = desc->g; 7889 var.avl = desc->avl; 7890 var.present = desc->p; 7891 var.unusable = !var.present; 7892 var.padding = 0; 7893 7894 kvm_set_segment(vcpu, &var, seg); 7895 return; 7896 } 7897 7898 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt, 7899 u32 msr_index, u64 *pdata) 7900 { 7901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7902 int r; 7903 7904 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata); 7905 7906 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, 7907 complete_emulated_rdmsr, r)) { 7908 /* Bounce to user space */ 7909 return X86EMUL_IO_NEEDED; 7910 } 7911 7912 return r; 7913 } 7914 7915 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt, 7916 u32 msr_index, u64 data) 7917 { 7918 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7919 int r; 7920 7921 r = kvm_set_msr_with_filter(vcpu, msr_index, data); 7922 7923 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, 7924 complete_emulated_msr_access, r)) { 7925 /* Bounce to user space */ 7926 return X86EMUL_IO_NEEDED; 7927 } 7928 7929 return r; 7930 } 7931 7932 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7933 u32 msr_index, u64 *pdata) 7934 { 7935 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 7936 } 7937 7938 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7939 u32 msr_index, u64 data) 7940 { 7941 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); 7942 } 7943 7944 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7945 { 7946 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7947 7948 return vcpu->arch.smbase; 7949 } 7950 7951 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7952 { 7953 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7954 7955 vcpu->arch.smbase = smbase; 7956 } 7957 7958 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7959 u32 pmc) 7960 { 7961 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) 7962 return 0; 7963 return -EINVAL; 7964 } 7965 7966 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7967 u32 pmc, u64 *pdata) 7968 { 7969 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7970 } 7971 7972 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7973 { 7974 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7975 } 7976 7977 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7978 struct x86_instruction_info *info, 7979 enum x86_intercept_stage stage) 7980 { 7981 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7982 &ctxt->exception); 7983 } 7984 7985 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7986 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7987 bool exact_only) 7988 { 7989 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7990 } 7991 7992 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7993 { 7994 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7995 } 7996 7997 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7998 { 7999 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 8000 } 8001 8002 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 8003 { 8004 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 8005 } 8006 8007 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt) 8008 { 8009 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID); 8010 } 8011 8012 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 8013 { 8014 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 8015 } 8016 8017 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 8018 { 8019 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 8020 } 8021 8022 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 8023 { 8024 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 8025 } 8026 8027 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 8028 { 8029 return emul_to_vcpu(ctxt)->arch.hflags; 8030 } 8031 8032 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 8033 { 8034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8035 8036 kvm_smm_changed(vcpu, false); 8037 } 8038 8039 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 8040 const char *smstate) 8041 { 8042 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 8043 } 8044 8045 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 8046 { 8047 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 8048 } 8049 8050 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 8051 { 8052 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 8053 } 8054 8055 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt) 8056 { 8057 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm; 8058 8059 if (!kvm->vm_bugged) 8060 kvm_vm_bugged(kvm); 8061 } 8062 8063 static const struct x86_emulate_ops emulate_ops = { 8064 .vm_bugged = emulator_vm_bugged, 8065 .read_gpr = emulator_read_gpr, 8066 .write_gpr = emulator_write_gpr, 8067 .read_std = emulator_read_std, 8068 .write_std = emulator_write_std, 8069 .read_phys = kvm_read_guest_phys_system, 8070 .fetch = kvm_fetch_guest_virt, 8071 .read_emulated = emulator_read_emulated, 8072 .write_emulated = emulator_write_emulated, 8073 .cmpxchg_emulated = emulator_cmpxchg_emulated, 8074 .invlpg = emulator_invlpg, 8075 .pio_in_emulated = emulator_pio_in_emulated, 8076 .pio_out_emulated = emulator_pio_out_emulated, 8077 .get_segment = emulator_get_segment, 8078 .set_segment = emulator_set_segment, 8079 .get_cached_segment_base = emulator_get_cached_segment_base, 8080 .get_gdt = emulator_get_gdt, 8081 .get_idt = emulator_get_idt, 8082 .set_gdt = emulator_set_gdt, 8083 .set_idt = emulator_set_idt, 8084 .get_cr = emulator_get_cr, 8085 .set_cr = emulator_set_cr, 8086 .cpl = emulator_get_cpl, 8087 .get_dr = emulator_get_dr, 8088 .set_dr = emulator_set_dr, 8089 .get_smbase = emulator_get_smbase, 8090 .set_smbase = emulator_set_smbase, 8091 .set_msr_with_filter = emulator_set_msr_with_filter, 8092 .get_msr_with_filter = emulator_get_msr_with_filter, 8093 .set_msr = emulator_set_msr, 8094 .get_msr = emulator_get_msr, 8095 .check_pmc = emulator_check_pmc, 8096 .read_pmc = emulator_read_pmc, 8097 .halt = emulator_halt, 8098 .wbinvd = emulator_wbinvd, 8099 .fix_hypercall = emulator_fix_hypercall, 8100 .intercept = emulator_intercept, 8101 .get_cpuid = emulator_get_cpuid, 8102 .guest_has_long_mode = emulator_guest_has_long_mode, 8103 .guest_has_movbe = emulator_guest_has_movbe, 8104 .guest_has_fxsr = emulator_guest_has_fxsr, 8105 .guest_has_rdpid = emulator_guest_has_rdpid, 8106 .set_nmi_mask = emulator_set_nmi_mask, 8107 .get_hflags = emulator_get_hflags, 8108 .exiting_smm = emulator_exiting_smm, 8109 .leave_smm = emulator_leave_smm, 8110 .triple_fault = emulator_triple_fault, 8111 .set_xcr = emulator_set_xcr, 8112 }; 8113 8114 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 8115 { 8116 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 8117 /* 8118 * an sti; sti; sequence only disable interrupts for the first 8119 * instruction. So, if the last instruction, be it emulated or 8120 * not, left the system with the INT_STI flag enabled, it 8121 * means that the last instruction is an sti. We should not 8122 * leave the flag on in this case. The same goes for mov ss 8123 */ 8124 if (int_shadow & mask) 8125 mask = 0; 8126 if (unlikely(int_shadow || mask)) { 8127 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 8128 if (!mask) 8129 kvm_make_request(KVM_REQ_EVENT, vcpu); 8130 } 8131 } 8132 8133 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 8134 { 8135 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8136 if (ctxt->exception.vector == PF_VECTOR) 8137 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 8138 8139 if (ctxt->exception.error_code_valid) 8140 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 8141 ctxt->exception.error_code); 8142 else 8143 kvm_queue_exception(vcpu, ctxt->exception.vector); 8144 return false; 8145 } 8146 8147 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 8148 { 8149 struct x86_emulate_ctxt *ctxt; 8150 8151 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 8152 if (!ctxt) { 8153 pr_err("kvm: failed to allocate vcpu's emulator\n"); 8154 return NULL; 8155 } 8156 8157 ctxt->vcpu = vcpu; 8158 ctxt->ops = &emulate_ops; 8159 vcpu->arch.emulate_ctxt = ctxt; 8160 8161 return ctxt; 8162 } 8163 8164 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 8165 { 8166 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8167 int cs_db, cs_l; 8168 8169 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 8170 8171 ctxt->gpa_available = false; 8172 ctxt->eflags = kvm_get_rflags(vcpu); 8173 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 8174 8175 ctxt->eip = kvm_rip_read(vcpu); 8176 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 8177 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 8178 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 8179 cs_db ? X86EMUL_MODE_PROT32 : 8180 X86EMUL_MODE_PROT16; 8181 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 8182 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 8183 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 8184 8185 ctxt->interruptibility = 0; 8186 ctxt->have_exception = false; 8187 ctxt->exception.vector = -1; 8188 ctxt->perm_ok = false; 8189 8190 init_decode_cache(ctxt); 8191 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8192 } 8193 8194 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 8195 { 8196 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8197 int ret; 8198 8199 init_emulate_ctxt(vcpu); 8200 8201 ctxt->op_bytes = 2; 8202 ctxt->ad_bytes = 2; 8203 ctxt->_eip = ctxt->eip + inc_eip; 8204 ret = emulate_int_real(ctxt, irq); 8205 8206 if (ret != X86EMUL_CONTINUE) { 8207 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 8208 } else { 8209 ctxt->eip = ctxt->_eip; 8210 kvm_rip_write(vcpu, ctxt->eip); 8211 kvm_set_rflags(vcpu, ctxt->eflags); 8212 } 8213 } 8214 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 8215 8216 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8217 u8 ndata, u8 *insn_bytes, u8 insn_size) 8218 { 8219 struct kvm_run *run = vcpu->run; 8220 u64 info[5]; 8221 u8 info_start; 8222 8223 /* 8224 * Zero the whole array used to retrieve the exit info, as casting to 8225 * u32 for select entries will leave some chunks uninitialized. 8226 */ 8227 memset(&info, 0, sizeof(info)); 8228 8229 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], 8230 &info[2], (u32 *)&info[3], 8231 (u32 *)&info[4]); 8232 8233 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8234 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 8235 8236 /* 8237 * There's currently space for 13 entries, but 5 are used for the exit 8238 * reason and info. Restrict to 4 to reduce the maintenance burden 8239 * when expanding kvm_run.emulation_failure in the future. 8240 */ 8241 if (WARN_ON_ONCE(ndata > 4)) 8242 ndata = 4; 8243 8244 /* Always include the flags as a 'data' entry. */ 8245 info_start = 1; 8246 run->emulation_failure.flags = 0; 8247 8248 if (insn_size) { 8249 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 8250 sizeof(run->emulation_failure.insn_bytes) != 16)); 8251 info_start += 2; 8252 run->emulation_failure.flags |= 8253 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 8254 run->emulation_failure.insn_size = insn_size; 8255 memset(run->emulation_failure.insn_bytes, 0x90, 8256 sizeof(run->emulation_failure.insn_bytes)); 8257 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 8258 } 8259 8260 memcpy(&run->internal.data[info_start], info, sizeof(info)); 8261 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 8262 ndata * sizeof(data[0])); 8263 8264 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 8265 } 8266 8267 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 8268 { 8269 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8270 8271 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 8272 ctxt->fetch.end - ctxt->fetch.data); 8273 } 8274 8275 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8276 u8 ndata) 8277 { 8278 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 8279 } 8280 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 8281 8282 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 8283 { 8284 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 8285 } 8286 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 8287 8288 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 8289 { 8290 struct kvm *kvm = vcpu->kvm; 8291 8292 ++vcpu->stat.insn_emulation_fail; 8293 trace_kvm_emulate_insn_failed(vcpu); 8294 8295 if (emulation_type & EMULTYPE_VMWARE_GP) { 8296 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8297 return 1; 8298 } 8299 8300 if (kvm->arch.exit_on_emulation_error || 8301 (emulation_type & EMULTYPE_SKIP)) { 8302 prepare_emulation_ctxt_failure_exit(vcpu); 8303 return 0; 8304 } 8305 8306 kvm_queue_exception(vcpu, UD_VECTOR); 8307 8308 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 8309 prepare_emulation_ctxt_failure_exit(vcpu); 8310 return 0; 8311 } 8312 8313 return 1; 8314 } 8315 8316 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8317 bool write_fault_to_shadow_pgtable, 8318 int emulation_type) 8319 { 8320 gpa_t gpa = cr2_or_gpa; 8321 kvm_pfn_t pfn; 8322 8323 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8324 return false; 8325 8326 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8327 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8328 return false; 8329 8330 if (!vcpu->arch.mmu->root_role.direct) { 8331 /* 8332 * Write permission should be allowed since only 8333 * write access need to be emulated. 8334 */ 8335 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8336 8337 /* 8338 * If the mapping is invalid in guest, let cpu retry 8339 * it to generate fault. 8340 */ 8341 if (gpa == UNMAPPED_GVA) 8342 return true; 8343 } 8344 8345 /* 8346 * Do not retry the unhandleable instruction if it faults on the 8347 * readonly host memory, otherwise it will goto a infinite loop: 8348 * retry instruction -> write #PF -> emulation fail -> retry 8349 * instruction -> ... 8350 */ 8351 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 8352 8353 /* 8354 * If the instruction failed on the error pfn, it can not be fixed, 8355 * report the error to userspace. 8356 */ 8357 if (is_error_noslot_pfn(pfn)) 8358 return false; 8359 8360 kvm_release_pfn_clean(pfn); 8361 8362 /* The instructions are well-emulated on direct mmu. */ 8363 if (vcpu->arch.mmu->root_role.direct) { 8364 unsigned int indirect_shadow_pages; 8365 8366 write_lock(&vcpu->kvm->mmu_lock); 8367 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 8368 write_unlock(&vcpu->kvm->mmu_lock); 8369 8370 if (indirect_shadow_pages) 8371 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8372 8373 return true; 8374 } 8375 8376 /* 8377 * if emulation was due to access to shadowed page table 8378 * and it failed try to unshadow page and re-enter the 8379 * guest to let CPU execute the instruction. 8380 */ 8381 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8382 8383 /* 8384 * If the access faults on its page table, it can not 8385 * be fixed by unprotecting shadow page and it should 8386 * be reported to userspace. 8387 */ 8388 return !write_fault_to_shadow_pgtable; 8389 } 8390 8391 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 8392 gpa_t cr2_or_gpa, int emulation_type) 8393 { 8394 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8395 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 8396 8397 last_retry_eip = vcpu->arch.last_retry_eip; 8398 last_retry_addr = vcpu->arch.last_retry_addr; 8399 8400 /* 8401 * If the emulation is caused by #PF and it is non-page_table 8402 * writing instruction, it means the VM-EXIT is caused by shadow 8403 * page protected, we can zap the shadow page and retry this 8404 * instruction directly. 8405 * 8406 * Note: if the guest uses a non-page-table modifying instruction 8407 * on the PDE that points to the instruction, then we will unmap 8408 * the instruction and go to an infinite loop. So, we cache the 8409 * last retried eip and the last fault address, if we meet the eip 8410 * and the address again, we can break out of the potential infinite 8411 * loop. 8412 */ 8413 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 8414 8415 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8416 return false; 8417 8418 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8419 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8420 return false; 8421 8422 if (x86_page_table_writing_insn(ctxt)) 8423 return false; 8424 8425 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 8426 return false; 8427 8428 vcpu->arch.last_retry_eip = ctxt->eip; 8429 vcpu->arch.last_retry_addr = cr2_or_gpa; 8430 8431 if (!vcpu->arch.mmu->root_role.direct) 8432 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8433 8434 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8435 8436 return true; 8437 } 8438 8439 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 8440 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 8441 8442 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 8443 { 8444 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 8445 8446 if (entering_smm) { 8447 vcpu->arch.hflags |= HF_SMM_MASK; 8448 } else { 8449 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 8450 8451 /* Process a latched INIT or SMI, if any. */ 8452 kvm_make_request(KVM_REQ_EVENT, vcpu); 8453 8454 /* 8455 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, 8456 * on SMM exit we still need to reload them from 8457 * guest memory 8458 */ 8459 vcpu->arch.pdptrs_from_userspace = false; 8460 } 8461 8462 kvm_mmu_reset_context(vcpu); 8463 } 8464 8465 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 8466 unsigned long *db) 8467 { 8468 u32 dr6 = 0; 8469 int i; 8470 u32 enable, rwlen; 8471 8472 enable = dr7; 8473 rwlen = dr7 >> 16; 8474 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 8475 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 8476 dr6 |= (1 << i); 8477 return dr6; 8478 } 8479 8480 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 8481 { 8482 struct kvm_run *kvm_run = vcpu->run; 8483 8484 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 8485 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 8486 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 8487 kvm_run->debug.arch.exception = DB_VECTOR; 8488 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8489 return 0; 8490 } 8491 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 8492 return 1; 8493 } 8494 8495 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 8496 { 8497 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8498 int r; 8499 8500 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 8501 if (unlikely(!r)) 8502 return 0; 8503 8504 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8505 8506 /* 8507 * rflags is the old, "raw" value of the flags. The new value has 8508 * not been saved yet. 8509 * 8510 * This is correct even for TF set by the guest, because "the 8511 * processor will not generate this exception after the instruction 8512 * that sets the TF flag". 8513 */ 8514 if (unlikely(rflags & X86_EFLAGS_TF)) 8515 r = kvm_vcpu_do_singlestep(vcpu); 8516 return r; 8517 } 8518 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 8519 8520 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, int *r) 8521 { 8522 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 8523 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 8524 struct kvm_run *kvm_run = vcpu->run; 8525 unsigned long eip = kvm_get_linear_rip(vcpu); 8526 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8527 vcpu->arch.guest_debug_dr7, 8528 vcpu->arch.eff_db); 8529 8530 if (dr6 != 0) { 8531 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 8532 kvm_run->debug.arch.pc = eip; 8533 kvm_run->debug.arch.exception = DB_VECTOR; 8534 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8535 *r = 0; 8536 return true; 8537 } 8538 } 8539 8540 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 8541 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 8542 unsigned long eip = kvm_get_linear_rip(vcpu); 8543 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8544 vcpu->arch.dr7, 8545 vcpu->arch.db); 8546 8547 if (dr6 != 0) { 8548 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 8549 *r = 1; 8550 return true; 8551 } 8552 } 8553 8554 return false; 8555 } 8556 8557 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 8558 { 8559 switch (ctxt->opcode_len) { 8560 case 1: 8561 switch (ctxt->b) { 8562 case 0xe4: /* IN */ 8563 case 0xe5: 8564 case 0xec: 8565 case 0xed: 8566 case 0xe6: /* OUT */ 8567 case 0xe7: 8568 case 0xee: 8569 case 0xef: 8570 case 0x6c: /* INS */ 8571 case 0x6d: 8572 case 0x6e: /* OUTS */ 8573 case 0x6f: 8574 return true; 8575 } 8576 break; 8577 case 2: 8578 switch (ctxt->b) { 8579 case 0x33: /* RDPMC */ 8580 return true; 8581 } 8582 break; 8583 } 8584 8585 return false; 8586 } 8587 8588 /* 8589 * Decode an instruction for emulation. The caller is responsible for handling 8590 * code breakpoints. Note, manually detecting code breakpoints is unnecessary 8591 * (and wrong) when emulating on an intercepted fault-like exception[*], as 8592 * code breakpoints have higher priority and thus have already been done by 8593 * hardware. 8594 * 8595 * [*] Except #MC, which is higher priority, but KVM should never emulate in 8596 * response to a machine check. 8597 */ 8598 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 8599 void *insn, int insn_len) 8600 { 8601 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8602 int r; 8603 8604 init_emulate_ctxt(vcpu); 8605 8606 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 8607 8608 trace_kvm_emulate_insn_start(vcpu); 8609 ++vcpu->stat.insn_emulation; 8610 8611 return r; 8612 } 8613 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 8614 8615 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8616 int emulation_type, void *insn, int insn_len) 8617 { 8618 int r; 8619 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8620 bool writeback = true; 8621 bool write_fault_to_spt; 8622 8623 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len))) 8624 return 1; 8625 8626 vcpu->arch.l1tf_flush_l1d = true; 8627 8628 /* 8629 * Clear write_fault_to_shadow_pgtable here to ensure it is 8630 * never reused. 8631 */ 8632 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 8633 vcpu->arch.write_fault_to_shadow_pgtable = false; 8634 8635 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 8636 kvm_clear_exception_queue(vcpu); 8637 8638 /* 8639 * Return immediately if RIP hits a code breakpoint, such #DBs 8640 * are fault-like and are higher priority than any faults on 8641 * the code fetch itself. 8642 */ 8643 if (!(emulation_type & EMULTYPE_SKIP) && 8644 kvm_vcpu_check_code_breakpoint(vcpu, &r)) 8645 return r; 8646 8647 r = x86_decode_emulated_instruction(vcpu, emulation_type, 8648 insn, insn_len); 8649 if (r != EMULATION_OK) { 8650 if ((emulation_type & EMULTYPE_TRAP_UD) || 8651 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 8652 kvm_queue_exception(vcpu, UD_VECTOR); 8653 return 1; 8654 } 8655 if (reexecute_instruction(vcpu, cr2_or_gpa, 8656 write_fault_to_spt, 8657 emulation_type)) 8658 return 1; 8659 if (ctxt->have_exception) { 8660 /* 8661 * #UD should result in just EMULATION_FAILED, and trap-like 8662 * exception should not be encountered during decode. 8663 */ 8664 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 8665 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 8666 inject_emulated_exception(vcpu); 8667 return 1; 8668 } 8669 return handle_emulation_failure(vcpu, emulation_type); 8670 } 8671 } 8672 8673 if ((emulation_type & EMULTYPE_VMWARE_GP) && 8674 !is_vmware_backdoor_opcode(ctxt)) { 8675 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8676 return 1; 8677 } 8678 8679 /* 8680 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for 8681 * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). 8682 * The caller is responsible for updating interruptibility state and 8683 * injecting single-step #DBs. 8684 */ 8685 if (emulation_type & EMULTYPE_SKIP) { 8686 if (ctxt->mode != X86EMUL_MODE_PROT64) 8687 ctxt->eip = (u32)ctxt->_eip; 8688 else 8689 ctxt->eip = ctxt->_eip; 8690 8691 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { 8692 r = 1; 8693 goto writeback; 8694 } 8695 8696 kvm_rip_write(vcpu, ctxt->eip); 8697 if (ctxt->eflags & X86_EFLAGS_RF) 8698 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 8699 return 1; 8700 } 8701 8702 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 8703 return 1; 8704 8705 /* this is needed for vmware backdoor interface to work since it 8706 changes registers values during IO operation */ 8707 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 8708 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8709 emulator_invalidate_register_cache(ctxt); 8710 } 8711 8712 restart: 8713 if (emulation_type & EMULTYPE_PF) { 8714 /* Save the faulting GPA (cr2) in the address field */ 8715 ctxt->exception.address = cr2_or_gpa; 8716 8717 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 8718 if (vcpu->arch.mmu->root_role.direct) { 8719 ctxt->gpa_available = true; 8720 ctxt->gpa_val = cr2_or_gpa; 8721 } 8722 } else { 8723 /* Sanitize the address out of an abundance of paranoia. */ 8724 ctxt->exception.address = 0; 8725 } 8726 8727 r = x86_emulate_insn(ctxt); 8728 8729 if (r == EMULATION_INTERCEPTED) 8730 return 1; 8731 8732 if (r == EMULATION_FAILED) { 8733 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 8734 emulation_type)) 8735 return 1; 8736 8737 return handle_emulation_failure(vcpu, emulation_type); 8738 } 8739 8740 if (ctxt->have_exception) { 8741 r = 1; 8742 if (inject_emulated_exception(vcpu)) 8743 return r; 8744 } else if (vcpu->arch.pio.count) { 8745 if (!vcpu->arch.pio.in) { 8746 /* FIXME: return into emulator if single-stepping. */ 8747 vcpu->arch.pio.count = 0; 8748 } else { 8749 writeback = false; 8750 vcpu->arch.complete_userspace_io = complete_emulated_pio; 8751 } 8752 r = 0; 8753 } else if (vcpu->mmio_needed) { 8754 ++vcpu->stat.mmio_exits; 8755 8756 if (!vcpu->mmio_is_write) 8757 writeback = false; 8758 r = 0; 8759 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8760 } else if (vcpu->arch.complete_userspace_io) { 8761 writeback = false; 8762 r = 0; 8763 } else if (r == EMULATION_RESTART) 8764 goto restart; 8765 else 8766 r = 1; 8767 8768 writeback: 8769 if (writeback) { 8770 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8771 toggle_interruptibility(vcpu, ctxt->interruptibility); 8772 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8773 if (!ctxt->have_exception || 8774 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 8775 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8776 if (ctxt->is_branch) 8777 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 8778 kvm_rip_write(vcpu, ctxt->eip); 8779 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 8780 r = kvm_vcpu_do_singlestep(vcpu); 8781 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu); 8782 __kvm_set_rflags(vcpu, ctxt->eflags); 8783 } 8784 8785 /* 8786 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 8787 * do nothing, and it will be requested again as soon as 8788 * the shadow expires. But we still need to check here, 8789 * because POPF has no interrupt shadow. 8790 */ 8791 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 8792 kvm_make_request(KVM_REQ_EVENT, vcpu); 8793 } else 8794 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 8795 8796 return r; 8797 } 8798 8799 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 8800 { 8801 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 8802 } 8803 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 8804 8805 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 8806 void *insn, int insn_len) 8807 { 8808 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 8809 } 8810 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 8811 8812 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 8813 { 8814 vcpu->arch.pio.count = 0; 8815 return 1; 8816 } 8817 8818 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 8819 { 8820 vcpu->arch.pio.count = 0; 8821 8822 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 8823 return 1; 8824 8825 return kvm_skip_emulated_instruction(vcpu); 8826 } 8827 8828 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 8829 unsigned short port) 8830 { 8831 unsigned long val = kvm_rax_read(vcpu); 8832 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 8833 8834 if (ret) 8835 return ret; 8836 8837 /* 8838 * Workaround userspace that relies on old KVM behavior of %rip being 8839 * incremented prior to exiting to userspace to handle "OUT 0x7e". 8840 */ 8841 if (port == 0x7e && 8842 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 8843 vcpu->arch.complete_userspace_io = 8844 complete_fast_pio_out_port_0x7e; 8845 kvm_skip_emulated_instruction(vcpu); 8846 } else { 8847 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8848 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 8849 } 8850 return 0; 8851 } 8852 8853 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 8854 { 8855 unsigned long val; 8856 8857 /* We should only ever be called with arch.pio.count equal to 1 */ 8858 BUG_ON(vcpu->arch.pio.count != 1); 8859 8860 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 8861 vcpu->arch.pio.count = 0; 8862 return 1; 8863 } 8864 8865 /* For size less than 4 we merge, else we zero extend */ 8866 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 8867 8868 complete_emulator_pio_in(vcpu, &val); 8869 kvm_rax_write(vcpu, val); 8870 8871 return kvm_skip_emulated_instruction(vcpu); 8872 } 8873 8874 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 8875 unsigned short port) 8876 { 8877 unsigned long val; 8878 int ret; 8879 8880 /* For size less than 4 we merge, else we zero extend */ 8881 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 8882 8883 ret = emulator_pio_in(vcpu, size, port, &val, 1); 8884 if (ret) { 8885 kvm_rax_write(vcpu, val); 8886 return ret; 8887 } 8888 8889 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8890 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 8891 8892 return 0; 8893 } 8894 8895 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 8896 { 8897 int ret; 8898 8899 if (in) 8900 ret = kvm_fast_pio_in(vcpu, size, port); 8901 else 8902 ret = kvm_fast_pio_out(vcpu, size, port); 8903 return ret && kvm_skip_emulated_instruction(vcpu); 8904 } 8905 EXPORT_SYMBOL_GPL(kvm_fast_pio); 8906 8907 static int kvmclock_cpu_down_prep(unsigned int cpu) 8908 { 8909 __this_cpu_write(cpu_tsc_khz, 0); 8910 return 0; 8911 } 8912 8913 static void tsc_khz_changed(void *data) 8914 { 8915 struct cpufreq_freqs *freq = data; 8916 unsigned long khz = 0; 8917 8918 if (data) 8919 khz = freq->new; 8920 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8921 khz = cpufreq_quick_get(raw_smp_processor_id()); 8922 if (!khz) 8923 khz = tsc_khz; 8924 __this_cpu_write(cpu_tsc_khz, khz); 8925 } 8926 8927 #ifdef CONFIG_X86_64 8928 static void kvm_hyperv_tsc_notifier(void) 8929 { 8930 struct kvm *kvm; 8931 int cpu; 8932 8933 mutex_lock(&kvm_lock); 8934 list_for_each_entry(kvm, &vm_list, vm_list) 8935 kvm_make_mclock_inprogress_request(kvm); 8936 8937 /* no guest entries from this point */ 8938 hyperv_stop_tsc_emulation(); 8939 8940 /* TSC frequency always matches when on Hyper-V */ 8941 for_each_present_cpu(cpu) 8942 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8943 kvm_caps.max_guest_tsc_khz = tsc_khz; 8944 8945 list_for_each_entry(kvm, &vm_list, vm_list) { 8946 __kvm_start_pvclock_update(kvm); 8947 pvclock_update_vm_gtod_copy(kvm); 8948 kvm_end_pvclock_update(kvm); 8949 } 8950 8951 mutex_unlock(&kvm_lock); 8952 } 8953 #endif 8954 8955 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8956 { 8957 struct kvm *kvm; 8958 struct kvm_vcpu *vcpu; 8959 int send_ipi = 0; 8960 unsigned long i; 8961 8962 /* 8963 * We allow guests to temporarily run on slowing clocks, 8964 * provided we notify them after, or to run on accelerating 8965 * clocks, provided we notify them before. Thus time never 8966 * goes backwards. 8967 * 8968 * However, we have a problem. We can't atomically update 8969 * the frequency of a given CPU from this function; it is 8970 * merely a notifier, which can be called from any CPU. 8971 * Changing the TSC frequency at arbitrary points in time 8972 * requires a recomputation of local variables related to 8973 * the TSC for each VCPU. We must flag these local variables 8974 * to be updated and be sure the update takes place with the 8975 * new frequency before any guests proceed. 8976 * 8977 * Unfortunately, the combination of hotplug CPU and frequency 8978 * change creates an intractable locking scenario; the order 8979 * of when these callouts happen is undefined with respect to 8980 * CPU hotplug, and they can race with each other. As such, 8981 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 8982 * undefined; you can actually have a CPU frequency change take 8983 * place in between the computation of X and the setting of the 8984 * variable. To protect against this problem, all updates of 8985 * the per_cpu tsc_khz variable are done in an interrupt 8986 * protected IPI, and all callers wishing to update the value 8987 * must wait for a synchronous IPI to complete (which is trivial 8988 * if the caller is on the CPU already). This establishes the 8989 * necessary total order on variable updates. 8990 * 8991 * Note that because a guest time update may take place 8992 * anytime after the setting of the VCPU's request bit, the 8993 * correct TSC value must be set before the request. However, 8994 * to ensure the update actually makes it to any guest which 8995 * starts running in hardware virtualization between the set 8996 * and the acquisition of the spinlock, we must also ping the 8997 * CPU after setting the request bit. 8998 * 8999 */ 9000 9001 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 9002 9003 mutex_lock(&kvm_lock); 9004 list_for_each_entry(kvm, &vm_list, vm_list) { 9005 kvm_for_each_vcpu(i, vcpu, kvm) { 9006 if (vcpu->cpu != cpu) 9007 continue; 9008 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9009 if (vcpu->cpu != raw_smp_processor_id()) 9010 send_ipi = 1; 9011 } 9012 } 9013 mutex_unlock(&kvm_lock); 9014 9015 if (freq->old < freq->new && send_ipi) { 9016 /* 9017 * We upscale the frequency. Must make the guest 9018 * doesn't see old kvmclock values while running with 9019 * the new frequency, otherwise we risk the guest sees 9020 * time go backwards. 9021 * 9022 * In case we update the frequency for another cpu 9023 * (which might be in guest context) send an interrupt 9024 * to kick the cpu out of guest context. Next time 9025 * guest context is entered kvmclock will be updated, 9026 * so the guest will not see stale values. 9027 */ 9028 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 9029 } 9030 } 9031 9032 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 9033 void *data) 9034 { 9035 struct cpufreq_freqs *freq = data; 9036 int cpu; 9037 9038 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 9039 return 0; 9040 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 9041 return 0; 9042 9043 for_each_cpu(cpu, freq->policy->cpus) 9044 __kvmclock_cpufreq_notifier(freq, cpu); 9045 9046 return 0; 9047 } 9048 9049 static struct notifier_block kvmclock_cpufreq_notifier_block = { 9050 .notifier_call = kvmclock_cpufreq_notifier 9051 }; 9052 9053 static int kvmclock_cpu_online(unsigned int cpu) 9054 { 9055 tsc_khz_changed(NULL); 9056 return 0; 9057 } 9058 9059 static void kvm_timer_init(void) 9060 { 9061 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9062 max_tsc_khz = tsc_khz; 9063 9064 if (IS_ENABLED(CONFIG_CPU_FREQ)) { 9065 struct cpufreq_policy *policy; 9066 int cpu; 9067 9068 cpu = get_cpu(); 9069 policy = cpufreq_cpu_get(cpu); 9070 if (policy) { 9071 if (policy->cpuinfo.max_freq) 9072 max_tsc_khz = policy->cpuinfo.max_freq; 9073 cpufreq_cpu_put(policy); 9074 } 9075 put_cpu(); 9076 } 9077 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 9078 CPUFREQ_TRANSITION_NOTIFIER); 9079 } 9080 9081 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 9082 kvmclock_cpu_online, kvmclock_cpu_down_prep); 9083 } 9084 9085 #ifdef CONFIG_X86_64 9086 static void pvclock_gtod_update_fn(struct work_struct *work) 9087 { 9088 struct kvm *kvm; 9089 struct kvm_vcpu *vcpu; 9090 unsigned long i; 9091 9092 mutex_lock(&kvm_lock); 9093 list_for_each_entry(kvm, &vm_list, vm_list) 9094 kvm_for_each_vcpu(i, vcpu, kvm) 9095 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 9096 atomic_set(&kvm_guest_has_master_clock, 0); 9097 mutex_unlock(&kvm_lock); 9098 } 9099 9100 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 9101 9102 /* 9103 * Indirection to move queue_work() out of the tk_core.seq write held 9104 * region to prevent possible deadlocks against time accessors which 9105 * are invoked with work related locks held. 9106 */ 9107 static void pvclock_irq_work_fn(struct irq_work *w) 9108 { 9109 queue_work(system_long_wq, &pvclock_gtod_work); 9110 } 9111 9112 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 9113 9114 /* 9115 * Notification about pvclock gtod data update. 9116 */ 9117 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 9118 void *priv) 9119 { 9120 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 9121 struct timekeeper *tk = priv; 9122 9123 update_pvclock_gtod(tk); 9124 9125 /* 9126 * Disable master clock if host does not trust, or does not use, 9127 * TSC based clocksource. Delegate queue_work() to irq_work as 9128 * this is invoked with tk_core.seq write held. 9129 */ 9130 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 9131 atomic_read(&kvm_guest_has_master_clock) != 0) 9132 irq_work_queue(&pvclock_irq_work); 9133 return 0; 9134 } 9135 9136 static struct notifier_block pvclock_gtod_notifier = { 9137 .notifier_call = pvclock_gtod_notify, 9138 }; 9139 #endif 9140 9141 int kvm_arch_init(void *opaque) 9142 { 9143 struct kvm_x86_init_ops *ops = opaque; 9144 int r; 9145 9146 if (kvm_x86_ops.hardware_enable) { 9147 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); 9148 r = -EEXIST; 9149 goto out; 9150 } 9151 9152 if (!ops->cpu_has_kvm_support()) { 9153 pr_err_ratelimited("kvm: no hardware support for '%s'\n", 9154 ops->runtime_ops->name); 9155 r = -EOPNOTSUPP; 9156 goto out; 9157 } 9158 if (ops->disabled_by_bios()) { 9159 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", 9160 ops->runtime_ops->name); 9161 r = -EOPNOTSUPP; 9162 goto out; 9163 } 9164 9165 /* 9166 * KVM explicitly assumes that the guest has an FPU and 9167 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 9168 * vCPU's FPU state as a fxregs_state struct. 9169 */ 9170 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 9171 printk(KERN_ERR "kvm: inadequate fpu\n"); 9172 r = -EOPNOTSUPP; 9173 goto out; 9174 } 9175 9176 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9177 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n"); 9178 r = -EOPNOTSUPP; 9179 goto out; 9180 } 9181 9182 r = -ENOMEM; 9183 9184 x86_emulator_cache = kvm_alloc_emulator_cache(); 9185 if (!x86_emulator_cache) { 9186 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 9187 goto out; 9188 } 9189 9190 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 9191 if (!user_return_msrs) { 9192 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 9193 goto out_free_x86_emulator_cache; 9194 } 9195 kvm_nr_uret_msrs = 0; 9196 9197 r = kvm_mmu_vendor_module_init(); 9198 if (r) 9199 goto out_free_percpu; 9200 9201 kvm_timer_init(); 9202 9203 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 9204 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 9205 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 9206 } 9207 9208 if (pi_inject_timer == -1) 9209 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER); 9210 #ifdef CONFIG_X86_64 9211 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 9212 9213 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9214 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 9215 #endif 9216 9217 return 0; 9218 9219 out_free_percpu: 9220 free_percpu(user_return_msrs); 9221 out_free_x86_emulator_cache: 9222 kmem_cache_destroy(x86_emulator_cache); 9223 out: 9224 return r; 9225 } 9226 9227 void kvm_arch_exit(void) 9228 { 9229 #ifdef CONFIG_X86_64 9230 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9231 clear_hv_tscchange_cb(); 9232 #endif 9233 kvm_lapic_exit(); 9234 9235 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 9236 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 9237 CPUFREQ_TRANSITION_NOTIFIER); 9238 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 9239 #ifdef CONFIG_X86_64 9240 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 9241 irq_work_sync(&pvclock_irq_work); 9242 cancel_work_sync(&pvclock_gtod_work); 9243 #endif 9244 kvm_x86_ops.hardware_enable = NULL; 9245 kvm_mmu_vendor_module_exit(); 9246 free_percpu(user_return_msrs); 9247 kmem_cache_destroy(x86_emulator_cache); 9248 #ifdef CONFIG_KVM_XEN 9249 static_key_deferred_flush(&kvm_xen_enabled); 9250 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 9251 #endif 9252 } 9253 9254 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) 9255 { 9256 /* 9257 * The vCPU has halted, e.g. executed HLT. Update the run state if the 9258 * local APIC is in-kernel, the run loop will detect the non-runnable 9259 * state and halt the vCPU. Exit to userspace if the local APIC is 9260 * managed by userspace, in which case userspace is responsible for 9261 * handling wake events. 9262 */ 9263 ++vcpu->stat.halt_exits; 9264 if (lapic_in_kernel(vcpu)) { 9265 vcpu->arch.mp_state = state; 9266 return 1; 9267 } else { 9268 vcpu->run->exit_reason = reason; 9269 return 0; 9270 } 9271 } 9272 9273 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) 9274 { 9275 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 9276 } 9277 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); 9278 9279 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 9280 { 9281 int ret = kvm_skip_emulated_instruction(vcpu); 9282 /* 9283 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 9284 * KVM_EXIT_DEBUG here. 9285 */ 9286 return kvm_emulate_halt_noskip(vcpu) && ret; 9287 } 9288 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 9289 9290 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 9291 { 9292 int ret = kvm_skip_emulated_instruction(vcpu); 9293 9294 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, 9295 KVM_EXIT_AP_RESET_HOLD) && ret; 9296 } 9297 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 9298 9299 #ifdef CONFIG_X86_64 9300 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 9301 unsigned long clock_type) 9302 { 9303 struct kvm_clock_pairing clock_pairing; 9304 struct timespec64 ts; 9305 u64 cycle; 9306 int ret; 9307 9308 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 9309 return -KVM_EOPNOTSUPP; 9310 9311 /* 9312 * When tsc is in permanent catchup mode guests won't be able to use 9313 * pvclock_read_retry loop to get consistent view of pvclock 9314 */ 9315 if (vcpu->arch.tsc_always_catchup) 9316 return -KVM_EOPNOTSUPP; 9317 9318 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 9319 return -KVM_EOPNOTSUPP; 9320 9321 clock_pairing.sec = ts.tv_sec; 9322 clock_pairing.nsec = ts.tv_nsec; 9323 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 9324 clock_pairing.flags = 0; 9325 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 9326 9327 ret = 0; 9328 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 9329 sizeof(struct kvm_clock_pairing))) 9330 ret = -KVM_EFAULT; 9331 9332 return ret; 9333 } 9334 #endif 9335 9336 /* 9337 * kvm_pv_kick_cpu_op: Kick a vcpu. 9338 * 9339 * @apicid - apicid of vcpu to be kicked. 9340 */ 9341 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) 9342 { 9343 struct kvm_lapic_irq lapic_irq; 9344 9345 lapic_irq.shorthand = APIC_DEST_NOSHORT; 9346 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 9347 lapic_irq.level = 0; 9348 lapic_irq.dest_id = apicid; 9349 lapic_irq.msi_redir_hint = false; 9350 9351 lapic_irq.delivery_mode = APIC_DM_REMRD; 9352 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 9353 } 9354 9355 bool kvm_apicv_activated(struct kvm *kvm) 9356 { 9357 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 9358 } 9359 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 9360 9361 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu) 9362 { 9363 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons); 9364 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu); 9365 9366 return (vm_reasons | vcpu_reasons) == 0; 9367 } 9368 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated); 9369 9370 static void set_or_clear_apicv_inhibit(unsigned long *inhibits, 9371 enum kvm_apicv_inhibit reason, bool set) 9372 { 9373 if (set) 9374 __set_bit(reason, inhibits); 9375 else 9376 __clear_bit(reason, inhibits); 9377 9378 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits); 9379 } 9380 9381 static void kvm_apicv_init(struct kvm *kvm) 9382 { 9383 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons; 9384 9385 init_rwsem(&kvm->arch.apicv_update_lock); 9386 9387 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true); 9388 9389 if (!enable_apicv) 9390 set_or_clear_apicv_inhibit(inhibits, 9391 APICV_INHIBIT_REASON_DISABLE, true); 9392 } 9393 9394 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 9395 { 9396 struct kvm_vcpu *target = NULL; 9397 struct kvm_apic_map *map; 9398 9399 vcpu->stat.directed_yield_attempted++; 9400 9401 if (single_task_running()) 9402 goto no_yield; 9403 9404 rcu_read_lock(); 9405 map = rcu_dereference(vcpu->kvm->arch.apic_map); 9406 9407 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 9408 target = map->phys_map[dest_id]->vcpu; 9409 9410 rcu_read_unlock(); 9411 9412 if (!target || !READ_ONCE(target->ready)) 9413 goto no_yield; 9414 9415 /* Ignore requests to yield to self */ 9416 if (vcpu == target) 9417 goto no_yield; 9418 9419 if (kvm_vcpu_yield_to(target) <= 0) 9420 goto no_yield; 9421 9422 vcpu->stat.directed_yield_successful++; 9423 9424 no_yield: 9425 return; 9426 } 9427 9428 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 9429 { 9430 u64 ret = vcpu->run->hypercall.ret; 9431 9432 if (!is_64_bit_mode(vcpu)) 9433 ret = (u32)ret; 9434 kvm_rax_write(vcpu, ret); 9435 ++vcpu->stat.hypercalls; 9436 return kvm_skip_emulated_instruction(vcpu); 9437 } 9438 9439 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 9440 { 9441 unsigned long nr, a0, a1, a2, a3, ret; 9442 int op_64_bit; 9443 9444 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 9445 return kvm_xen_hypercall(vcpu); 9446 9447 if (kvm_hv_hypercall_enabled(vcpu)) 9448 return kvm_hv_hypercall(vcpu); 9449 9450 nr = kvm_rax_read(vcpu); 9451 a0 = kvm_rbx_read(vcpu); 9452 a1 = kvm_rcx_read(vcpu); 9453 a2 = kvm_rdx_read(vcpu); 9454 a3 = kvm_rsi_read(vcpu); 9455 9456 trace_kvm_hypercall(nr, a0, a1, a2, a3); 9457 9458 op_64_bit = is_64_bit_hypercall(vcpu); 9459 if (!op_64_bit) { 9460 nr &= 0xFFFFFFFF; 9461 a0 &= 0xFFFFFFFF; 9462 a1 &= 0xFFFFFFFF; 9463 a2 &= 0xFFFFFFFF; 9464 a3 &= 0xFFFFFFFF; 9465 } 9466 9467 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 9468 ret = -KVM_EPERM; 9469 goto out; 9470 } 9471 9472 ret = -KVM_ENOSYS; 9473 9474 switch (nr) { 9475 case KVM_HC_VAPIC_POLL_IRQ: 9476 ret = 0; 9477 break; 9478 case KVM_HC_KICK_CPU: 9479 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 9480 break; 9481 9482 kvm_pv_kick_cpu_op(vcpu->kvm, a1); 9483 kvm_sched_yield(vcpu, a1); 9484 ret = 0; 9485 break; 9486 #ifdef CONFIG_X86_64 9487 case KVM_HC_CLOCK_PAIRING: 9488 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 9489 break; 9490 #endif 9491 case KVM_HC_SEND_IPI: 9492 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 9493 break; 9494 9495 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 9496 break; 9497 case KVM_HC_SCHED_YIELD: 9498 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 9499 break; 9500 9501 kvm_sched_yield(vcpu, a0); 9502 ret = 0; 9503 break; 9504 case KVM_HC_MAP_GPA_RANGE: { 9505 u64 gpa = a0, npages = a1, attrs = a2; 9506 9507 ret = -KVM_ENOSYS; 9508 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 9509 break; 9510 9511 if (!PAGE_ALIGNED(gpa) || !npages || 9512 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 9513 ret = -KVM_EINVAL; 9514 break; 9515 } 9516 9517 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 9518 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 9519 vcpu->run->hypercall.args[0] = gpa; 9520 vcpu->run->hypercall.args[1] = npages; 9521 vcpu->run->hypercall.args[2] = attrs; 9522 vcpu->run->hypercall.longmode = op_64_bit; 9523 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 9524 return 0; 9525 } 9526 default: 9527 ret = -KVM_ENOSYS; 9528 break; 9529 } 9530 out: 9531 if (!op_64_bit) 9532 ret = (u32)ret; 9533 kvm_rax_write(vcpu, ret); 9534 9535 ++vcpu->stat.hypercalls; 9536 return kvm_skip_emulated_instruction(vcpu); 9537 } 9538 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 9539 9540 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 9541 { 9542 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 9543 char instruction[3]; 9544 unsigned long rip = kvm_rip_read(vcpu); 9545 9546 /* 9547 * If the quirk is disabled, synthesize a #UD and let the guest pick up 9548 * the pieces. 9549 */ 9550 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) { 9551 ctxt->exception.error_code_valid = false; 9552 ctxt->exception.vector = UD_VECTOR; 9553 ctxt->have_exception = true; 9554 return X86EMUL_PROPAGATE_FAULT; 9555 } 9556 9557 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 9558 9559 return emulator_write_emulated(ctxt, rip, instruction, 3, 9560 &ctxt->exception); 9561 } 9562 9563 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 9564 { 9565 return vcpu->run->request_interrupt_window && 9566 likely(!pic_in_kernel(vcpu->kvm)); 9567 } 9568 9569 /* Called within kvm->srcu read side. */ 9570 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 9571 { 9572 struct kvm_run *kvm_run = vcpu->run; 9573 9574 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); 9575 kvm_run->cr8 = kvm_get_cr8(vcpu); 9576 kvm_run->apic_base = kvm_get_apic_base(vcpu); 9577 9578 kvm_run->ready_for_interrupt_injection = 9579 pic_in_kernel(vcpu->kvm) || 9580 kvm_vcpu_ready_for_interrupt_injection(vcpu); 9581 9582 if (is_smm(vcpu)) 9583 kvm_run->flags |= KVM_RUN_X86_SMM; 9584 } 9585 9586 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 9587 { 9588 int max_irr, tpr; 9589 9590 if (!kvm_x86_ops.update_cr8_intercept) 9591 return; 9592 9593 if (!lapic_in_kernel(vcpu)) 9594 return; 9595 9596 if (vcpu->arch.apic->apicv_active) 9597 return; 9598 9599 if (!vcpu->arch.apic->vapic_addr) 9600 max_irr = kvm_lapic_find_highest_irr(vcpu); 9601 else 9602 max_irr = -1; 9603 9604 if (max_irr != -1) 9605 max_irr >>= 4; 9606 9607 tpr = kvm_lapic_get_cr8(vcpu); 9608 9609 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 9610 } 9611 9612 9613 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 9614 { 9615 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9616 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9617 return 1; 9618 } 9619 9620 return kvm_x86_ops.nested_ops->check_events(vcpu); 9621 } 9622 9623 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 9624 { 9625 trace_kvm_inj_exception(vcpu->arch.exception.nr, 9626 vcpu->arch.exception.has_error_code, 9627 vcpu->arch.exception.error_code, 9628 vcpu->arch.exception.injected); 9629 9630 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 9631 vcpu->arch.exception.error_code = false; 9632 static_call(kvm_x86_queue_exception)(vcpu); 9633 } 9634 9635 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 9636 { 9637 int r; 9638 bool can_inject = true; 9639 9640 /* try to reinject previous events if any */ 9641 9642 if (vcpu->arch.exception.injected) { 9643 kvm_inject_exception(vcpu); 9644 can_inject = false; 9645 } 9646 /* 9647 * Do not inject an NMI or interrupt if there is a pending 9648 * exception. Exceptions and interrupts are recognized at 9649 * instruction boundaries, i.e. the start of an instruction. 9650 * Trap-like exceptions, e.g. #DB, have higher priority than 9651 * NMIs and interrupts, i.e. traps are recognized before an 9652 * NMI/interrupt that's pending on the same instruction. 9653 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 9654 * priority, but are only generated (pended) during instruction 9655 * execution, i.e. a pending fault-like exception means the 9656 * fault occurred on the *previous* instruction and must be 9657 * serviced prior to recognizing any new events in order to 9658 * fully complete the previous instruction. 9659 */ 9660 else if (!vcpu->arch.exception.pending) { 9661 if (vcpu->arch.nmi_injected) { 9662 static_call(kvm_x86_inject_nmi)(vcpu); 9663 can_inject = false; 9664 } else if (vcpu->arch.interrupt.injected) { 9665 static_call(kvm_x86_inject_irq)(vcpu, true); 9666 can_inject = false; 9667 } 9668 } 9669 9670 WARN_ON_ONCE(vcpu->arch.exception.injected && 9671 vcpu->arch.exception.pending); 9672 9673 /* 9674 * Call check_nested_events() even if we reinjected a previous event 9675 * in order for caller to determine if it should require immediate-exit 9676 * from L2 to L1 due to pending L1 events which require exit 9677 * from L2 to L1. 9678 */ 9679 if (is_guest_mode(vcpu)) { 9680 r = kvm_check_nested_events(vcpu); 9681 if (r < 0) 9682 goto out; 9683 } 9684 9685 /* try to inject new event if pending */ 9686 if (vcpu->arch.exception.pending) { 9687 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 9688 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 9689 X86_EFLAGS_RF); 9690 9691 if (vcpu->arch.exception.nr == DB_VECTOR) { 9692 kvm_deliver_exception_payload(vcpu); 9693 if (vcpu->arch.dr7 & DR7_GD) { 9694 vcpu->arch.dr7 &= ~DR7_GD; 9695 kvm_update_dr7(vcpu); 9696 } 9697 } 9698 9699 kvm_inject_exception(vcpu); 9700 9701 vcpu->arch.exception.pending = false; 9702 vcpu->arch.exception.injected = true; 9703 9704 can_inject = false; 9705 } 9706 9707 /* Don't inject interrupts if the user asked to avoid doing so */ 9708 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 9709 return 0; 9710 9711 /* 9712 * Finally, inject interrupt events. If an event cannot be injected 9713 * due to architectural conditions (e.g. IF=0) a window-open exit 9714 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 9715 * and can architecturally be injected, but we cannot do it right now: 9716 * an interrupt could have arrived just now and we have to inject it 9717 * as a vmexit, or there could already an event in the queue, which is 9718 * indicated by can_inject. In that case we request an immediate exit 9719 * in order to make progress and get back here for another iteration. 9720 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 9721 */ 9722 if (vcpu->arch.smi_pending) { 9723 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 9724 if (r < 0) 9725 goto out; 9726 if (r) { 9727 vcpu->arch.smi_pending = false; 9728 ++vcpu->arch.smi_count; 9729 enter_smm(vcpu); 9730 can_inject = false; 9731 } else 9732 static_call(kvm_x86_enable_smi_window)(vcpu); 9733 } 9734 9735 if (vcpu->arch.nmi_pending) { 9736 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 9737 if (r < 0) 9738 goto out; 9739 if (r) { 9740 --vcpu->arch.nmi_pending; 9741 vcpu->arch.nmi_injected = true; 9742 static_call(kvm_x86_inject_nmi)(vcpu); 9743 can_inject = false; 9744 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 9745 } 9746 if (vcpu->arch.nmi_pending) 9747 static_call(kvm_x86_enable_nmi_window)(vcpu); 9748 } 9749 9750 if (kvm_cpu_has_injectable_intr(vcpu)) { 9751 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 9752 if (r < 0) 9753 goto out; 9754 if (r) { 9755 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 9756 static_call(kvm_x86_inject_irq)(vcpu, false); 9757 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 9758 } 9759 if (kvm_cpu_has_injectable_intr(vcpu)) 9760 static_call(kvm_x86_enable_irq_window)(vcpu); 9761 } 9762 9763 if (is_guest_mode(vcpu) && 9764 kvm_x86_ops.nested_ops->hv_timer_pending && 9765 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 9766 *req_immediate_exit = true; 9767 9768 WARN_ON(vcpu->arch.exception.pending); 9769 return 0; 9770 9771 out: 9772 if (r == -EBUSY) { 9773 *req_immediate_exit = true; 9774 r = 0; 9775 } 9776 return r; 9777 } 9778 9779 static void process_nmi(struct kvm_vcpu *vcpu) 9780 { 9781 unsigned limit = 2; 9782 9783 /* 9784 * x86 is limited to one NMI running, and one NMI pending after it. 9785 * If an NMI is already in progress, limit further NMIs to just one. 9786 * Otherwise, allow two (and we'll inject the first one immediately). 9787 */ 9788 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 9789 limit = 1; 9790 9791 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 9792 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 9793 kvm_make_request(KVM_REQ_EVENT, vcpu); 9794 } 9795 9796 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 9797 { 9798 u32 flags = 0; 9799 flags |= seg->g << 23; 9800 flags |= seg->db << 22; 9801 flags |= seg->l << 21; 9802 flags |= seg->avl << 20; 9803 flags |= seg->present << 15; 9804 flags |= seg->dpl << 13; 9805 flags |= seg->s << 12; 9806 flags |= seg->type << 8; 9807 return flags; 9808 } 9809 9810 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 9811 { 9812 struct kvm_segment seg; 9813 int offset; 9814 9815 kvm_get_segment(vcpu, &seg, n); 9816 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 9817 9818 if (n < 3) 9819 offset = 0x7f84 + n * 12; 9820 else 9821 offset = 0x7f2c + (n - 3) * 12; 9822 9823 put_smstate(u32, buf, offset + 8, seg.base); 9824 put_smstate(u32, buf, offset + 4, seg.limit); 9825 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 9826 } 9827 9828 #ifdef CONFIG_X86_64 9829 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 9830 { 9831 struct kvm_segment seg; 9832 int offset; 9833 u16 flags; 9834 9835 kvm_get_segment(vcpu, &seg, n); 9836 offset = 0x7e00 + n * 16; 9837 9838 flags = enter_smm_get_segment_flags(&seg) >> 8; 9839 put_smstate(u16, buf, offset, seg.selector); 9840 put_smstate(u16, buf, offset + 2, flags); 9841 put_smstate(u32, buf, offset + 4, seg.limit); 9842 put_smstate(u64, buf, offset + 8, seg.base); 9843 } 9844 #endif 9845 9846 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 9847 { 9848 struct desc_ptr dt; 9849 struct kvm_segment seg; 9850 unsigned long val; 9851 int i; 9852 9853 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 9854 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 9855 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 9856 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 9857 9858 for (i = 0; i < 8; i++) 9859 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 9860 9861 kvm_get_dr(vcpu, 6, &val); 9862 put_smstate(u32, buf, 0x7fcc, (u32)val); 9863 kvm_get_dr(vcpu, 7, &val); 9864 put_smstate(u32, buf, 0x7fc8, (u32)val); 9865 9866 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9867 put_smstate(u32, buf, 0x7fc4, seg.selector); 9868 put_smstate(u32, buf, 0x7f64, seg.base); 9869 put_smstate(u32, buf, 0x7f60, seg.limit); 9870 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 9871 9872 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9873 put_smstate(u32, buf, 0x7fc0, seg.selector); 9874 put_smstate(u32, buf, 0x7f80, seg.base); 9875 put_smstate(u32, buf, 0x7f7c, seg.limit); 9876 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 9877 9878 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9879 put_smstate(u32, buf, 0x7f74, dt.address); 9880 put_smstate(u32, buf, 0x7f70, dt.size); 9881 9882 static_call(kvm_x86_get_idt)(vcpu, &dt); 9883 put_smstate(u32, buf, 0x7f58, dt.address); 9884 put_smstate(u32, buf, 0x7f54, dt.size); 9885 9886 for (i = 0; i < 6; i++) 9887 enter_smm_save_seg_32(vcpu, buf, i); 9888 9889 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 9890 9891 /* revision id */ 9892 put_smstate(u32, buf, 0x7efc, 0x00020000); 9893 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 9894 } 9895 9896 #ifdef CONFIG_X86_64 9897 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9898 { 9899 struct desc_ptr dt; 9900 struct kvm_segment seg; 9901 unsigned long val; 9902 int i; 9903 9904 for (i = 0; i < 16; i++) 9905 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9906 9907 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9908 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9909 9910 kvm_get_dr(vcpu, 6, &val); 9911 put_smstate(u64, buf, 0x7f68, val); 9912 kvm_get_dr(vcpu, 7, &val); 9913 put_smstate(u64, buf, 0x7f60, val); 9914 9915 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9916 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9917 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9918 9919 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9920 9921 /* revision id */ 9922 put_smstate(u32, buf, 0x7efc, 0x00020064); 9923 9924 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9925 9926 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9927 put_smstate(u16, buf, 0x7e90, seg.selector); 9928 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9929 put_smstate(u32, buf, 0x7e94, seg.limit); 9930 put_smstate(u64, buf, 0x7e98, seg.base); 9931 9932 static_call(kvm_x86_get_idt)(vcpu, &dt); 9933 put_smstate(u32, buf, 0x7e84, dt.size); 9934 put_smstate(u64, buf, 0x7e88, dt.address); 9935 9936 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9937 put_smstate(u16, buf, 0x7e70, seg.selector); 9938 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9939 put_smstate(u32, buf, 0x7e74, seg.limit); 9940 put_smstate(u64, buf, 0x7e78, seg.base); 9941 9942 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9943 put_smstate(u32, buf, 0x7e64, dt.size); 9944 put_smstate(u64, buf, 0x7e68, dt.address); 9945 9946 for (i = 0; i < 6; i++) 9947 enter_smm_save_seg_64(vcpu, buf, i); 9948 } 9949 #endif 9950 9951 static void enter_smm(struct kvm_vcpu *vcpu) 9952 { 9953 struct kvm_segment cs, ds; 9954 struct desc_ptr dt; 9955 unsigned long cr0; 9956 char buf[512]; 9957 9958 memset(buf, 0, 512); 9959 #ifdef CONFIG_X86_64 9960 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9961 enter_smm_save_state_64(vcpu, buf); 9962 else 9963 #endif 9964 enter_smm_save_state_32(vcpu, buf); 9965 9966 /* 9967 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 9968 * state (e.g. leave guest mode) after we've saved the state into the 9969 * SMM state-save area. 9970 */ 9971 static_call(kvm_x86_enter_smm)(vcpu, buf); 9972 9973 kvm_smm_changed(vcpu, true); 9974 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 9975 9976 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 9977 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 9978 else 9979 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 9980 9981 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 9982 kvm_rip_write(vcpu, 0x8000); 9983 9984 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 9985 static_call(kvm_x86_set_cr0)(vcpu, cr0); 9986 vcpu->arch.cr0 = cr0; 9987 9988 static_call(kvm_x86_set_cr4)(vcpu, 0); 9989 9990 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 9991 dt.address = dt.size = 0; 9992 static_call(kvm_x86_set_idt)(vcpu, &dt); 9993 9994 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 9995 9996 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 9997 cs.base = vcpu->arch.smbase; 9998 9999 ds.selector = 0; 10000 ds.base = 0; 10001 10002 cs.limit = ds.limit = 0xffffffff; 10003 cs.type = ds.type = 0x3; 10004 cs.dpl = ds.dpl = 0; 10005 cs.db = ds.db = 0; 10006 cs.s = ds.s = 1; 10007 cs.l = ds.l = 0; 10008 cs.g = ds.g = 1; 10009 cs.avl = ds.avl = 0; 10010 cs.present = ds.present = 1; 10011 cs.unusable = ds.unusable = 0; 10012 cs.padding = ds.padding = 0; 10013 10014 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10015 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 10016 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 10017 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 10018 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 10019 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 10020 10021 #ifdef CONFIG_X86_64 10022 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 10023 static_call(kvm_x86_set_efer)(vcpu, 0); 10024 #endif 10025 10026 kvm_update_cpuid_runtime(vcpu); 10027 kvm_mmu_reset_context(vcpu); 10028 } 10029 10030 static void process_smi(struct kvm_vcpu *vcpu) 10031 { 10032 vcpu->arch.smi_pending = true; 10033 kvm_make_request(KVM_REQ_EVENT, vcpu); 10034 } 10035 10036 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 10037 unsigned long *vcpu_bitmap) 10038 { 10039 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 10040 } 10041 10042 void kvm_make_scan_ioapic_request(struct kvm *kvm) 10043 { 10044 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 10045 } 10046 10047 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 10048 { 10049 struct kvm_lapic *apic = vcpu->arch.apic; 10050 bool activate; 10051 10052 if (!lapic_in_kernel(vcpu)) 10053 return; 10054 10055 down_read(&vcpu->kvm->arch.apicv_update_lock); 10056 preempt_disable(); 10057 10058 /* Do not activate APICV when APIC is disabled */ 10059 activate = kvm_vcpu_apicv_activated(vcpu) && 10060 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED); 10061 10062 if (apic->apicv_active == activate) 10063 goto out; 10064 10065 apic->apicv_active = activate; 10066 kvm_apic_update_apicv(vcpu); 10067 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 10068 10069 /* 10070 * When APICv gets disabled, we may still have injected interrupts 10071 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 10072 * still active when the interrupt got accepted. Make sure 10073 * inject_pending_event() is called to check for that. 10074 */ 10075 if (!apic->apicv_active) 10076 kvm_make_request(KVM_REQ_EVENT, vcpu); 10077 10078 out: 10079 preempt_enable(); 10080 up_read(&vcpu->kvm->arch.apicv_update_lock); 10081 } 10082 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 10083 10084 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 10085 enum kvm_apicv_inhibit reason, bool set) 10086 { 10087 unsigned long old, new; 10088 10089 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 10090 10091 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason)) 10092 return; 10093 10094 old = new = kvm->arch.apicv_inhibit_reasons; 10095 10096 set_or_clear_apicv_inhibit(&new, reason, set); 10097 10098 if (!!old != !!new) { 10099 /* 10100 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 10101 * false positives in the sanity check WARN in svm_vcpu_run(). 10102 * This task will wait for all vCPUs to ack the kick IRQ before 10103 * updating apicv_inhibit_reasons, and all other vCPUs will 10104 * block on acquiring apicv_update_lock so that vCPUs can't 10105 * redo svm_vcpu_run() without seeing the new inhibit state. 10106 * 10107 * Note, holding apicv_update_lock and taking it in the read 10108 * side (handling the request) also prevents other vCPUs from 10109 * servicing the request with a stale apicv_inhibit_reasons. 10110 */ 10111 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 10112 kvm->arch.apicv_inhibit_reasons = new; 10113 if (new) { 10114 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 10115 kvm_zap_gfn_range(kvm, gfn, gfn+1); 10116 } 10117 } else { 10118 kvm->arch.apicv_inhibit_reasons = new; 10119 } 10120 } 10121 10122 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 10123 enum kvm_apicv_inhibit reason, bool set) 10124 { 10125 if (!enable_apicv) 10126 return; 10127 10128 down_write(&kvm->arch.apicv_update_lock); 10129 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set); 10130 up_write(&kvm->arch.apicv_update_lock); 10131 } 10132 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit); 10133 10134 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 10135 { 10136 if (!kvm_apic_present(vcpu)) 10137 return; 10138 10139 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 10140 10141 if (irqchip_split(vcpu->kvm)) 10142 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 10143 else { 10144 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10145 if (ioapic_in_kernel(vcpu->kvm)) 10146 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 10147 } 10148 10149 if (is_guest_mode(vcpu)) 10150 vcpu->arch.load_eoi_exitmap_pending = true; 10151 else 10152 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 10153 } 10154 10155 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 10156 { 10157 u64 eoi_exit_bitmap[4]; 10158 10159 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 10160 return; 10161 10162 if (to_hv_vcpu(vcpu)) { 10163 bitmap_or((ulong *)eoi_exit_bitmap, 10164 vcpu->arch.ioapic_handled_vectors, 10165 to_hv_synic(vcpu)->vec_bitmap, 256); 10166 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 10167 return; 10168 } 10169 10170 static_call_cond(kvm_x86_load_eoi_exitmap)( 10171 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); 10172 } 10173 10174 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 10175 unsigned long start, unsigned long end) 10176 { 10177 unsigned long apic_address; 10178 10179 /* 10180 * The physical address of apic access page is stored in the VMCS. 10181 * Update it when it becomes invalid. 10182 */ 10183 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 10184 if (start <= apic_address && apic_address < end) 10185 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 10186 } 10187 10188 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm) 10189 { 10190 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm); 10191 } 10192 10193 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 10194 { 10195 if (!lapic_in_kernel(vcpu)) 10196 return; 10197 10198 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu); 10199 } 10200 10201 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 10202 { 10203 smp_send_reschedule(vcpu->cpu); 10204 } 10205 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 10206 10207 /* 10208 * Called within kvm->srcu read side. 10209 * Returns 1 to let vcpu_run() continue the guest execution loop without 10210 * exiting to the userspace. Otherwise, the value will be returned to the 10211 * userspace. 10212 */ 10213 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 10214 { 10215 int r; 10216 bool req_int_win = 10217 dm_request_for_irq_injection(vcpu) && 10218 kvm_cpu_accept_dm_intr(vcpu); 10219 fastpath_t exit_fastpath; 10220 10221 bool req_immediate_exit = false; 10222 10223 /* Forbid vmenter if vcpu dirty ring is soft-full */ 10224 if (unlikely(vcpu->kvm->dirty_ring_size && 10225 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 10226 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 10227 trace_kvm_dirty_ring_exit(vcpu); 10228 r = 0; 10229 goto out; 10230 } 10231 10232 if (kvm_request_pending(vcpu)) { 10233 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 10234 r = -EIO; 10235 goto out; 10236 } 10237 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 10238 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 10239 r = 0; 10240 goto out; 10241 } 10242 } 10243 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) 10244 kvm_mmu_free_obsolete_roots(vcpu); 10245 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 10246 __kvm_migrate_timers(vcpu); 10247 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 10248 kvm_update_masterclock(vcpu->kvm); 10249 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 10250 kvm_gen_kvmclock_update(vcpu); 10251 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 10252 r = kvm_guest_time_update(vcpu); 10253 if (unlikely(r)) 10254 goto out; 10255 } 10256 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 10257 kvm_mmu_sync_roots(vcpu); 10258 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 10259 kvm_mmu_load_pgd(vcpu); 10260 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 10261 kvm_vcpu_flush_tlb_all(vcpu); 10262 10263 /* Flushing all ASIDs flushes the current ASID... */ 10264 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 10265 } 10266 kvm_service_local_tlb_flush_requests(vcpu); 10267 10268 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 10269 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 10270 r = 0; 10271 goto out; 10272 } 10273 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 10274 if (is_guest_mode(vcpu)) { 10275 kvm_x86_ops.nested_ops->triple_fault(vcpu); 10276 } else { 10277 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 10278 vcpu->mmio_needed = 0; 10279 r = 0; 10280 goto out; 10281 } 10282 } 10283 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 10284 /* Page is swapped out. Do synthetic halt */ 10285 vcpu->arch.apf.halted = true; 10286 r = 1; 10287 goto out; 10288 } 10289 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 10290 record_steal_time(vcpu); 10291 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 10292 process_smi(vcpu); 10293 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 10294 process_nmi(vcpu); 10295 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 10296 kvm_pmu_handle_event(vcpu); 10297 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 10298 kvm_pmu_deliver_pmi(vcpu); 10299 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 10300 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 10301 if (test_bit(vcpu->arch.pending_ioapic_eoi, 10302 vcpu->arch.ioapic_handled_vectors)) { 10303 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 10304 vcpu->run->eoi.vector = 10305 vcpu->arch.pending_ioapic_eoi; 10306 r = 0; 10307 goto out; 10308 } 10309 } 10310 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 10311 vcpu_scan_ioapic(vcpu); 10312 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 10313 vcpu_load_eoi_exitmap(vcpu); 10314 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 10315 kvm_vcpu_reload_apic_access_page(vcpu); 10316 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 10317 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10318 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 10319 vcpu->run->system_event.ndata = 0; 10320 r = 0; 10321 goto out; 10322 } 10323 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 10324 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10325 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 10326 vcpu->run->system_event.ndata = 0; 10327 r = 0; 10328 goto out; 10329 } 10330 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 10331 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 10332 10333 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 10334 vcpu->run->hyperv = hv_vcpu->exit; 10335 r = 0; 10336 goto out; 10337 } 10338 10339 /* 10340 * KVM_REQ_HV_STIMER has to be processed after 10341 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 10342 * depend on the guest clock being up-to-date 10343 */ 10344 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 10345 kvm_hv_process_stimers(vcpu); 10346 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 10347 kvm_vcpu_update_apicv(vcpu); 10348 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 10349 kvm_check_async_pf_completion(vcpu); 10350 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 10351 static_call(kvm_x86_msr_filter_changed)(vcpu); 10352 10353 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 10354 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 10355 } 10356 10357 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 10358 kvm_xen_has_interrupt(vcpu)) { 10359 ++vcpu->stat.req_event; 10360 r = kvm_apic_accept_events(vcpu); 10361 if (r < 0) { 10362 r = 0; 10363 goto out; 10364 } 10365 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 10366 r = 1; 10367 goto out; 10368 } 10369 10370 r = inject_pending_event(vcpu, &req_immediate_exit); 10371 if (r < 0) { 10372 r = 0; 10373 goto out; 10374 } 10375 if (req_int_win) 10376 static_call(kvm_x86_enable_irq_window)(vcpu); 10377 10378 if (kvm_lapic_enabled(vcpu)) { 10379 update_cr8_intercept(vcpu); 10380 kvm_lapic_sync_to_vapic(vcpu); 10381 } 10382 } 10383 10384 r = kvm_mmu_reload(vcpu); 10385 if (unlikely(r)) { 10386 goto cancel_injection; 10387 } 10388 10389 preempt_disable(); 10390 10391 static_call(kvm_x86_prepare_switch_to_guest)(vcpu); 10392 10393 /* 10394 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 10395 * IPI are then delayed after guest entry, which ensures that they 10396 * result in virtual interrupt delivery. 10397 */ 10398 local_irq_disable(); 10399 10400 /* Store vcpu->apicv_active before vcpu->mode. */ 10401 smp_store_release(&vcpu->mode, IN_GUEST_MODE); 10402 10403 kvm_vcpu_srcu_read_unlock(vcpu); 10404 10405 /* 10406 * 1) We should set ->mode before checking ->requests. Please see 10407 * the comment in kvm_vcpu_exiting_guest_mode(). 10408 * 10409 * 2) For APICv, we should set ->mode before checking PID.ON. This 10410 * pairs with the memory barrier implicit in pi_test_and_set_on 10411 * (see vmx_deliver_posted_interrupt). 10412 * 10413 * 3) This also orders the write to mode from any reads to the page 10414 * tables done while the VCPU is running. Please see the comment 10415 * in kvm_flush_remote_tlbs. 10416 */ 10417 smp_mb__after_srcu_read_unlock(); 10418 10419 /* 10420 * Process pending posted interrupts to handle the case where the 10421 * notification IRQ arrived in the host, or was never sent (because the 10422 * target vCPU wasn't running). Do this regardless of the vCPU's APICv 10423 * status, KVM doesn't update assigned devices when APICv is inhibited, 10424 * i.e. they can post interrupts even if APICv is temporarily disabled. 10425 */ 10426 if (kvm_lapic_enabled(vcpu)) 10427 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10428 10429 if (kvm_vcpu_exit_request(vcpu)) { 10430 vcpu->mode = OUTSIDE_GUEST_MODE; 10431 smp_wmb(); 10432 local_irq_enable(); 10433 preempt_enable(); 10434 kvm_vcpu_srcu_read_lock(vcpu); 10435 r = 1; 10436 goto cancel_injection; 10437 } 10438 10439 if (req_immediate_exit) { 10440 kvm_make_request(KVM_REQ_EVENT, vcpu); 10441 static_call(kvm_x86_request_immediate_exit)(vcpu); 10442 } 10443 10444 fpregs_assert_state_consistent(); 10445 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 10446 switch_fpu_return(); 10447 10448 if (vcpu->arch.guest_fpu.xfd_err) 10449 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 10450 10451 if (unlikely(vcpu->arch.switch_db_regs)) { 10452 set_debugreg(0, 7); 10453 set_debugreg(vcpu->arch.eff_db[0], 0); 10454 set_debugreg(vcpu->arch.eff_db[1], 1); 10455 set_debugreg(vcpu->arch.eff_db[2], 2); 10456 set_debugreg(vcpu->arch.eff_db[3], 3); 10457 } else if (unlikely(hw_breakpoint_active())) { 10458 set_debugreg(0, 7); 10459 } 10460 10461 guest_timing_enter_irqoff(); 10462 10463 for (;;) { 10464 /* 10465 * Assert that vCPU vs. VM APICv state is consistent. An APICv 10466 * update must kick and wait for all vCPUs before toggling the 10467 * per-VM state, and responsing vCPUs must wait for the update 10468 * to complete before servicing KVM_REQ_APICV_UPDATE. 10469 */ 10470 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) && 10471 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED)); 10472 10473 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu); 10474 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 10475 break; 10476 10477 if (kvm_lapic_enabled(vcpu)) 10478 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10479 10480 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 10481 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 10482 break; 10483 } 10484 } 10485 10486 /* 10487 * Do this here before restoring debug registers on the host. And 10488 * since we do this before handling the vmexit, a DR access vmexit 10489 * can (a) read the correct value of the debug registers, (b) set 10490 * KVM_DEBUGREG_WONT_EXIT again. 10491 */ 10492 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 10493 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 10494 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 10495 kvm_update_dr0123(vcpu); 10496 kvm_update_dr7(vcpu); 10497 } 10498 10499 /* 10500 * If the guest has used debug registers, at least dr7 10501 * will be disabled while returning to the host. 10502 * If we don't have active breakpoints in the host, we don't 10503 * care about the messed up debug address registers. But if 10504 * we have some of them active, restore the old state. 10505 */ 10506 if (hw_breakpoint_active()) 10507 hw_breakpoint_restore(); 10508 10509 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 10510 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 10511 10512 vcpu->mode = OUTSIDE_GUEST_MODE; 10513 smp_wmb(); 10514 10515 /* 10516 * Sync xfd before calling handle_exit_irqoff() which may 10517 * rely on the fact that guest_fpu::xfd is up-to-date (e.g. 10518 * in #NM irqoff handler). 10519 */ 10520 if (vcpu->arch.xfd_no_write_intercept) 10521 fpu_sync_guest_vmexit_xfd_state(); 10522 10523 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 10524 10525 if (vcpu->arch.guest_fpu.xfd_err) 10526 wrmsrl(MSR_IA32_XFD_ERR, 0); 10527 10528 /* 10529 * Consume any pending interrupts, including the possible source of 10530 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 10531 * An instruction is required after local_irq_enable() to fully unblock 10532 * interrupts on processors that implement an interrupt shadow, the 10533 * stat.exits increment will do nicely. 10534 */ 10535 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); 10536 local_irq_enable(); 10537 ++vcpu->stat.exits; 10538 local_irq_disable(); 10539 kvm_after_interrupt(vcpu); 10540 10541 /* 10542 * Wait until after servicing IRQs to account guest time so that any 10543 * ticks that occurred while running the guest are properly accounted 10544 * to the guest. Waiting until IRQs are enabled degrades the accuracy 10545 * of accounting via context tracking, but the loss of accuracy is 10546 * acceptable for all known use cases. 10547 */ 10548 guest_timing_exit_irqoff(); 10549 10550 local_irq_enable(); 10551 preempt_enable(); 10552 10553 kvm_vcpu_srcu_read_lock(vcpu); 10554 10555 /* 10556 * Profile KVM exit RIPs: 10557 */ 10558 if (unlikely(prof_on == KVM_PROFILING)) { 10559 unsigned long rip = kvm_rip_read(vcpu); 10560 profile_hit(KVM_PROFILING, (void *)rip); 10561 } 10562 10563 if (unlikely(vcpu->arch.tsc_always_catchup)) 10564 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10565 10566 if (vcpu->arch.apic_attention) 10567 kvm_lapic_sync_from_vapic(vcpu); 10568 10569 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 10570 return r; 10571 10572 cancel_injection: 10573 if (req_immediate_exit) 10574 kvm_make_request(KVM_REQ_EVENT, vcpu); 10575 static_call(kvm_x86_cancel_injection)(vcpu); 10576 if (unlikely(vcpu->arch.apic_attention)) 10577 kvm_lapic_sync_from_vapic(vcpu); 10578 out: 10579 return r; 10580 } 10581 10582 /* Called within kvm->srcu read side. */ 10583 static inline int vcpu_block(struct kvm_vcpu *vcpu) 10584 { 10585 bool hv_timer; 10586 10587 if (!kvm_arch_vcpu_runnable(vcpu)) { 10588 /* 10589 * Switch to the software timer before halt-polling/blocking as 10590 * the guest's timer may be a break event for the vCPU, and the 10591 * hypervisor timer runs only when the CPU is in guest mode. 10592 * Switch before halt-polling so that KVM recognizes an expired 10593 * timer before blocking. 10594 */ 10595 hv_timer = kvm_lapic_hv_timer_in_use(vcpu); 10596 if (hv_timer) 10597 kvm_lapic_switch_to_sw_timer(vcpu); 10598 10599 kvm_vcpu_srcu_read_unlock(vcpu); 10600 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 10601 kvm_vcpu_halt(vcpu); 10602 else 10603 kvm_vcpu_block(vcpu); 10604 kvm_vcpu_srcu_read_lock(vcpu); 10605 10606 if (hv_timer) 10607 kvm_lapic_switch_to_hv_timer(vcpu); 10608 10609 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 10610 return 1; 10611 } 10612 10613 if (kvm_apic_accept_events(vcpu) < 0) 10614 return 0; 10615 switch(vcpu->arch.mp_state) { 10616 case KVM_MP_STATE_HALTED: 10617 case KVM_MP_STATE_AP_RESET_HOLD: 10618 vcpu->arch.pv.pv_unhalted = false; 10619 vcpu->arch.mp_state = 10620 KVM_MP_STATE_RUNNABLE; 10621 fallthrough; 10622 case KVM_MP_STATE_RUNNABLE: 10623 vcpu->arch.apf.halted = false; 10624 break; 10625 case KVM_MP_STATE_INIT_RECEIVED: 10626 break; 10627 default: 10628 return -EINTR; 10629 } 10630 return 1; 10631 } 10632 10633 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 10634 { 10635 if (is_guest_mode(vcpu)) 10636 kvm_check_nested_events(vcpu); 10637 10638 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 10639 !vcpu->arch.apf.halted); 10640 } 10641 10642 /* Called within kvm->srcu read side. */ 10643 static int vcpu_run(struct kvm_vcpu *vcpu) 10644 { 10645 int r; 10646 10647 vcpu->arch.l1tf_flush_l1d = true; 10648 10649 for (;;) { 10650 /* 10651 * If another guest vCPU requests a PV TLB flush in the middle 10652 * of instruction emulation, the rest of the emulation could 10653 * use a stale page translation. Assume that any code after 10654 * this point can start executing an instruction. 10655 */ 10656 vcpu->arch.at_instruction_boundary = false; 10657 if (kvm_vcpu_running(vcpu)) { 10658 r = vcpu_enter_guest(vcpu); 10659 } else { 10660 r = vcpu_block(vcpu); 10661 } 10662 10663 if (r <= 0) 10664 break; 10665 10666 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 10667 if (kvm_xen_has_pending_events(vcpu)) 10668 kvm_xen_inject_pending_events(vcpu); 10669 10670 if (kvm_cpu_has_pending_timer(vcpu)) 10671 kvm_inject_pending_timer_irqs(vcpu); 10672 10673 if (dm_request_for_irq_injection(vcpu) && 10674 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 10675 r = 0; 10676 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 10677 ++vcpu->stat.request_irq_exits; 10678 break; 10679 } 10680 10681 if (__xfer_to_guest_mode_work_pending()) { 10682 kvm_vcpu_srcu_read_unlock(vcpu); 10683 r = xfer_to_guest_mode_handle_work(vcpu); 10684 kvm_vcpu_srcu_read_lock(vcpu); 10685 if (r) 10686 return r; 10687 } 10688 } 10689 10690 return r; 10691 } 10692 10693 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 10694 { 10695 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 10696 } 10697 10698 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 10699 { 10700 BUG_ON(!vcpu->arch.pio.count); 10701 10702 return complete_emulated_io(vcpu); 10703 } 10704 10705 /* 10706 * Implements the following, as a state machine: 10707 * 10708 * read: 10709 * for each fragment 10710 * for each mmio piece in the fragment 10711 * write gpa, len 10712 * exit 10713 * copy data 10714 * execute insn 10715 * 10716 * write: 10717 * for each fragment 10718 * for each mmio piece in the fragment 10719 * write gpa, len 10720 * copy data 10721 * exit 10722 */ 10723 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 10724 { 10725 struct kvm_run *run = vcpu->run; 10726 struct kvm_mmio_fragment *frag; 10727 unsigned len; 10728 10729 BUG_ON(!vcpu->mmio_needed); 10730 10731 /* Complete previous fragment */ 10732 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 10733 len = min(8u, frag->len); 10734 if (!vcpu->mmio_is_write) 10735 memcpy(frag->data, run->mmio.data, len); 10736 10737 if (frag->len <= 8) { 10738 /* Switch to the next fragment. */ 10739 frag++; 10740 vcpu->mmio_cur_fragment++; 10741 } else { 10742 /* Go forward to the next mmio piece. */ 10743 frag->data += len; 10744 frag->gpa += len; 10745 frag->len -= len; 10746 } 10747 10748 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 10749 vcpu->mmio_needed = 0; 10750 10751 /* FIXME: return into emulator if single-stepping. */ 10752 if (vcpu->mmio_is_write) 10753 return 1; 10754 vcpu->mmio_read_completed = 1; 10755 return complete_emulated_io(vcpu); 10756 } 10757 10758 run->exit_reason = KVM_EXIT_MMIO; 10759 run->mmio.phys_addr = frag->gpa; 10760 if (vcpu->mmio_is_write) 10761 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 10762 run->mmio.len = min(8u, frag->len); 10763 run->mmio.is_write = vcpu->mmio_is_write; 10764 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 10765 return 0; 10766 } 10767 10768 /* Swap (qemu) user FPU context for the guest FPU context. */ 10769 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 10770 { 10771 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ 10772 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 10773 trace_kvm_fpu(1); 10774 } 10775 10776 /* When vcpu_run ends, restore user space FPU context. */ 10777 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 10778 { 10779 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 10780 ++vcpu->stat.fpu_reload; 10781 trace_kvm_fpu(0); 10782 } 10783 10784 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 10785 { 10786 struct kvm_run *kvm_run = vcpu->run; 10787 int r; 10788 10789 vcpu_load(vcpu); 10790 kvm_sigset_activate(vcpu); 10791 kvm_run->flags = 0; 10792 kvm_load_guest_fpu(vcpu); 10793 10794 kvm_vcpu_srcu_read_lock(vcpu); 10795 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 10796 if (kvm_run->immediate_exit) { 10797 r = -EINTR; 10798 goto out; 10799 } 10800 /* 10801 * It should be impossible for the hypervisor timer to be in 10802 * use before KVM has ever run the vCPU. 10803 */ 10804 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu)); 10805 10806 kvm_vcpu_srcu_read_unlock(vcpu); 10807 kvm_vcpu_block(vcpu); 10808 kvm_vcpu_srcu_read_lock(vcpu); 10809 10810 if (kvm_apic_accept_events(vcpu) < 0) { 10811 r = 0; 10812 goto out; 10813 } 10814 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 10815 r = -EAGAIN; 10816 if (signal_pending(current)) { 10817 r = -EINTR; 10818 kvm_run->exit_reason = KVM_EXIT_INTR; 10819 ++vcpu->stat.signal_exits; 10820 } 10821 goto out; 10822 } 10823 10824 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 10825 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 10826 r = -EINVAL; 10827 goto out; 10828 } 10829 10830 if (kvm_run->kvm_dirty_regs) { 10831 r = sync_regs(vcpu); 10832 if (r != 0) 10833 goto out; 10834 } 10835 10836 /* re-sync apic's tpr */ 10837 if (!lapic_in_kernel(vcpu)) { 10838 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 10839 r = -EINVAL; 10840 goto out; 10841 } 10842 } 10843 10844 if (unlikely(vcpu->arch.complete_userspace_io)) { 10845 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 10846 vcpu->arch.complete_userspace_io = NULL; 10847 r = cui(vcpu); 10848 if (r <= 0) 10849 goto out; 10850 } else 10851 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 10852 10853 if (kvm_run->immediate_exit) { 10854 r = -EINTR; 10855 goto out; 10856 } 10857 10858 r = static_call(kvm_x86_vcpu_pre_run)(vcpu); 10859 if (r <= 0) 10860 goto out; 10861 10862 r = vcpu_run(vcpu); 10863 10864 out: 10865 kvm_put_guest_fpu(vcpu); 10866 if (kvm_run->kvm_valid_regs) 10867 store_regs(vcpu); 10868 post_kvm_run_save(vcpu); 10869 kvm_vcpu_srcu_read_unlock(vcpu); 10870 10871 kvm_sigset_deactivate(vcpu); 10872 vcpu_put(vcpu); 10873 return r; 10874 } 10875 10876 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10877 { 10878 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 10879 /* 10880 * We are here if userspace calls get_regs() in the middle of 10881 * instruction emulation. Registers state needs to be copied 10882 * back from emulation context to vcpu. Userspace shouldn't do 10883 * that usually, but some bad designed PV devices (vmware 10884 * backdoor interface) need this to work 10885 */ 10886 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 10887 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10888 } 10889 regs->rax = kvm_rax_read(vcpu); 10890 regs->rbx = kvm_rbx_read(vcpu); 10891 regs->rcx = kvm_rcx_read(vcpu); 10892 regs->rdx = kvm_rdx_read(vcpu); 10893 regs->rsi = kvm_rsi_read(vcpu); 10894 regs->rdi = kvm_rdi_read(vcpu); 10895 regs->rsp = kvm_rsp_read(vcpu); 10896 regs->rbp = kvm_rbp_read(vcpu); 10897 #ifdef CONFIG_X86_64 10898 regs->r8 = kvm_r8_read(vcpu); 10899 regs->r9 = kvm_r9_read(vcpu); 10900 regs->r10 = kvm_r10_read(vcpu); 10901 regs->r11 = kvm_r11_read(vcpu); 10902 regs->r12 = kvm_r12_read(vcpu); 10903 regs->r13 = kvm_r13_read(vcpu); 10904 regs->r14 = kvm_r14_read(vcpu); 10905 regs->r15 = kvm_r15_read(vcpu); 10906 #endif 10907 10908 regs->rip = kvm_rip_read(vcpu); 10909 regs->rflags = kvm_get_rflags(vcpu); 10910 } 10911 10912 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10913 { 10914 vcpu_load(vcpu); 10915 __get_regs(vcpu, regs); 10916 vcpu_put(vcpu); 10917 return 0; 10918 } 10919 10920 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10921 { 10922 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 10923 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10924 10925 kvm_rax_write(vcpu, regs->rax); 10926 kvm_rbx_write(vcpu, regs->rbx); 10927 kvm_rcx_write(vcpu, regs->rcx); 10928 kvm_rdx_write(vcpu, regs->rdx); 10929 kvm_rsi_write(vcpu, regs->rsi); 10930 kvm_rdi_write(vcpu, regs->rdi); 10931 kvm_rsp_write(vcpu, regs->rsp); 10932 kvm_rbp_write(vcpu, regs->rbp); 10933 #ifdef CONFIG_X86_64 10934 kvm_r8_write(vcpu, regs->r8); 10935 kvm_r9_write(vcpu, regs->r9); 10936 kvm_r10_write(vcpu, regs->r10); 10937 kvm_r11_write(vcpu, regs->r11); 10938 kvm_r12_write(vcpu, regs->r12); 10939 kvm_r13_write(vcpu, regs->r13); 10940 kvm_r14_write(vcpu, regs->r14); 10941 kvm_r15_write(vcpu, regs->r15); 10942 #endif 10943 10944 kvm_rip_write(vcpu, regs->rip); 10945 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 10946 10947 vcpu->arch.exception.pending = false; 10948 10949 kvm_make_request(KVM_REQ_EVENT, vcpu); 10950 } 10951 10952 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10953 { 10954 vcpu_load(vcpu); 10955 __set_regs(vcpu, regs); 10956 vcpu_put(vcpu); 10957 return 0; 10958 } 10959 10960 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10961 { 10962 struct desc_ptr dt; 10963 10964 if (vcpu->arch.guest_state_protected) 10965 goto skip_protected_regs; 10966 10967 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10968 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10969 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10970 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10971 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10972 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10973 10974 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10975 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10976 10977 static_call(kvm_x86_get_idt)(vcpu, &dt); 10978 sregs->idt.limit = dt.size; 10979 sregs->idt.base = dt.address; 10980 static_call(kvm_x86_get_gdt)(vcpu, &dt); 10981 sregs->gdt.limit = dt.size; 10982 sregs->gdt.base = dt.address; 10983 10984 sregs->cr2 = vcpu->arch.cr2; 10985 sregs->cr3 = kvm_read_cr3(vcpu); 10986 10987 skip_protected_regs: 10988 sregs->cr0 = kvm_read_cr0(vcpu); 10989 sregs->cr4 = kvm_read_cr4(vcpu); 10990 sregs->cr8 = kvm_get_cr8(vcpu); 10991 sregs->efer = vcpu->arch.efer; 10992 sregs->apic_base = kvm_get_apic_base(vcpu); 10993 } 10994 10995 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10996 { 10997 __get_sregs_common(vcpu, sregs); 10998 10999 if (vcpu->arch.guest_state_protected) 11000 return; 11001 11002 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 11003 set_bit(vcpu->arch.interrupt.nr, 11004 (unsigned long *)sregs->interrupt_bitmap); 11005 } 11006 11007 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11008 { 11009 int i; 11010 11011 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 11012 11013 if (vcpu->arch.guest_state_protected) 11014 return; 11015 11016 if (is_pae_paging(vcpu)) { 11017 for (i = 0 ; i < 4 ; i++) 11018 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 11019 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 11020 } 11021 } 11022 11023 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 11024 struct kvm_sregs *sregs) 11025 { 11026 vcpu_load(vcpu); 11027 __get_sregs(vcpu, sregs); 11028 vcpu_put(vcpu); 11029 return 0; 11030 } 11031 11032 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 11033 struct kvm_mp_state *mp_state) 11034 { 11035 int r; 11036 11037 vcpu_load(vcpu); 11038 if (kvm_mpx_supported()) 11039 kvm_load_guest_fpu(vcpu); 11040 11041 r = kvm_apic_accept_events(vcpu); 11042 if (r < 0) 11043 goto out; 11044 r = 0; 11045 11046 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 11047 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 11048 vcpu->arch.pv.pv_unhalted) 11049 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 11050 else 11051 mp_state->mp_state = vcpu->arch.mp_state; 11052 11053 out: 11054 if (kvm_mpx_supported()) 11055 kvm_put_guest_fpu(vcpu); 11056 vcpu_put(vcpu); 11057 return r; 11058 } 11059 11060 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 11061 struct kvm_mp_state *mp_state) 11062 { 11063 int ret = -EINVAL; 11064 11065 vcpu_load(vcpu); 11066 11067 if (!lapic_in_kernel(vcpu) && 11068 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 11069 goto out; 11070 11071 /* 11072 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 11073 * INIT state; latched init should be reported using 11074 * KVM_SET_VCPU_EVENTS, so reject it here. 11075 */ 11076 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 11077 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 11078 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 11079 goto out; 11080 11081 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 11082 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 11083 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 11084 } else 11085 vcpu->arch.mp_state = mp_state->mp_state; 11086 kvm_make_request(KVM_REQ_EVENT, vcpu); 11087 11088 ret = 0; 11089 out: 11090 vcpu_put(vcpu); 11091 return ret; 11092 } 11093 11094 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 11095 int reason, bool has_error_code, u32 error_code) 11096 { 11097 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 11098 int ret; 11099 11100 init_emulate_ctxt(vcpu); 11101 11102 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 11103 has_error_code, error_code); 11104 if (ret) { 11105 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11106 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11107 vcpu->run->internal.ndata = 0; 11108 return 0; 11109 } 11110 11111 kvm_rip_write(vcpu, ctxt->eip); 11112 kvm_set_rflags(vcpu, ctxt->eflags); 11113 return 1; 11114 } 11115 EXPORT_SYMBOL_GPL(kvm_task_switch); 11116 11117 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11118 { 11119 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 11120 /* 11121 * When EFER.LME and CR0.PG are set, the processor is in 11122 * 64-bit mode (though maybe in a 32-bit code segment). 11123 * CR4.PAE and EFER.LMA must be set. 11124 */ 11125 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 11126 return false; 11127 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 11128 return false; 11129 } else { 11130 /* 11131 * Not in 64-bit mode: EFER.LMA is clear and the code 11132 * segment cannot be 64-bit. 11133 */ 11134 if (sregs->efer & EFER_LMA || sregs->cs.l) 11135 return false; 11136 } 11137 11138 return kvm_is_valid_cr4(vcpu, sregs->cr4); 11139 } 11140 11141 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 11142 int *mmu_reset_needed, bool update_pdptrs) 11143 { 11144 struct msr_data apic_base_msr; 11145 int idx; 11146 struct desc_ptr dt; 11147 11148 if (!kvm_is_valid_sregs(vcpu, sregs)) 11149 return -EINVAL; 11150 11151 apic_base_msr.data = sregs->apic_base; 11152 apic_base_msr.host_initiated = true; 11153 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 11154 return -EINVAL; 11155 11156 if (vcpu->arch.guest_state_protected) 11157 return 0; 11158 11159 dt.size = sregs->idt.limit; 11160 dt.address = sregs->idt.base; 11161 static_call(kvm_x86_set_idt)(vcpu, &dt); 11162 dt.size = sregs->gdt.limit; 11163 dt.address = sregs->gdt.base; 11164 static_call(kvm_x86_set_gdt)(vcpu, &dt); 11165 11166 vcpu->arch.cr2 = sregs->cr2; 11167 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 11168 vcpu->arch.cr3 = sregs->cr3; 11169 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11170 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); 11171 11172 kvm_set_cr8(vcpu, sregs->cr8); 11173 11174 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 11175 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 11176 11177 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 11178 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 11179 vcpu->arch.cr0 = sregs->cr0; 11180 11181 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 11182 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 11183 11184 if (update_pdptrs) { 11185 idx = srcu_read_lock(&vcpu->kvm->srcu); 11186 if (is_pae_paging(vcpu)) { 11187 load_pdptrs(vcpu, kvm_read_cr3(vcpu)); 11188 *mmu_reset_needed = 1; 11189 } 11190 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11191 } 11192 11193 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 11194 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 11195 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 11196 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 11197 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 11198 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 11199 11200 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 11201 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 11202 11203 update_cr8_intercept(vcpu); 11204 11205 /* Older userspace won't unhalt the vcpu on reset. */ 11206 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 11207 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 11208 !is_protmode(vcpu)) 11209 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11210 11211 return 0; 11212 } 11213 11214 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11215 { 11216 int pending_vec, max_bits; 11217 int mmu_reset_needed = 0; 11218 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 11219 11220 if (ret) 11221 return ret; 11222 11223 if (mmu_reset_needed) 11224 kvm_mmu_reset_context(vcpu); 11225 11226 max_bits = KVM_NR_INTERRUPTS; 11227 pending_vec = find_first_bit( 11228 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 11229 11230 if (pending_vec < max_bits) { 11231 kvm_queue_interrupt(vcpu, pending_vec, false); 11232 pr_debug("Set back pending irq %d\n", pending_vec); 11233 kvm_make_request(KVM_REQ_EVENT, vcpu); 11234 } 11235 return 0; 11236 } 11237 11238 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11239 { 11240 int mmu_reset_needed = 0; 11241 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 11242 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 11243 !(sregs2->efer & EFER_LMA); 11244 int i, ret; 11245 11246 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 11247 return -EINVAL; 11248 11249 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 11250 return -EINVAL; 11251 11252 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 11253 &mmu_reset_needed, !valid_pdptrs); 11254 if (ret) 11255 return ret; 11256 11257 if (valid_pdptrs) { 11258 for (i = 0; i < 4 ; i++) 11259 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 11260 11261 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 11262 mmu_reset_needed = 1; 11263 vcpu->arch.pdptrs_from_userspace = true; 11264 } 11265 if (mmu_reset_needed) 11266 kvm_mmu_reset_context(vcpu); 11267 return 0; 11268 } 11269 11270 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 11271 struct kvm_sregs *sregs) 11272 { 11273 int ret; 11274 11275 vcpu_load(vcpu); 11276 ret = __set_sregs(vcpu, sregs); 11277 vcpu_put(vcpu); 11278 return ret; 11279 } 11280 11281 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 11282 { 11283 bool set = false; 11284 struct kvm_vcpu *vcpu; 11285 unsigned long i; 11286 11287 if (!enable_apicv) 11288 return; 11289 11290 down_write(&kvm->arch.apicv_update_lock); 11291 11292 kvm_for_each_vcpu(i, vcpu, kvm) { 11293 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 11294 set = true; 11295 break; 11296 } 11297 } 11298 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set); 11299 up_write(&kvm->arch.apicv_update_lock); 11300 } 11301 11302 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 11303 struct kvm_guest_debug *dbg) 11304 { 11305 unsigned long rflags; 11306 int i, r; 11307 11308 if (vcpu->arch.guest_state_protected) 11309 return -EINVAL; 11310 11311 vcpu_load(vcpu); 11312 11313 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 11314 r = -EBUSY; 11315 if (vcpu->arch.exception.pending) 11316 goto out; 11317 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 11318 kvm_queue_exception(vcpu, DB_VECTOR); 11319 else 11320 kvm_queue_exception(vcpu, BP_VECTOR); 11321 } 11322 11323 /* 11324 * Read rflags as long as potentially injected trace flags are still 11325 * filtered out. 11326 */ 11327 rflags = kvm_get_rflags(vcpu); 11328 11329 vcpu->guest_debug = dbg->control; 11330 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 11331 vcpu->guest_debug = 0; 11332 11333 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 11334 for (i = 0; i < KVM_NR_DB_REGS; ++i) 11335 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 11336 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 11337 } else { 11338 for (i = 0; i < KVM_NR_DB_REGS; i++) 11339 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 11340 } 11341 kvm_update_dr7(vcpu); 11342 11343 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11344 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 11345 11346 /* 11347 * Trigger an rflags update that will inject or remove the trace 11348 * flags. 11349 */ 11350 kvm_set_rflags(vcpu, rflags); 11351 11352 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11353 11354 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 11355 11356 r = 0; 11357 11358 out: 11359 vcpu_put(vcpu); 11360 return r; 11361 } 11362 11363 /* 11364 * Translate a guest virtual address to a guest physical address. 11365 */ 11366 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 11367 struct kvm_translation *tr) 11368 { 11369 unsigned long vaddr = tr->linear_address; 11370 gpa_t gpa; 11371 int idx; 11372 11373 vcpu_load(vcpu); 11374 11375 idx = srcu_read_lock(&vcpu->kvm->srcu); 11376 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 11377 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11378 tr->physical_address = gpa; 11379 tr->valid = gpa != UNMAPPED_GVA; 11380 tr->writeable = 1; 11381 tr->usermode = 0; 11382 11383 vcpu_put(vcpu); 11384 return 0; 11385 } 11386 11387 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11388 { 11389 struct fxregs_state *fxsave; 11390 11391 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11392 return 0; 11393 11394 vcpu_load(vcpu); 11395 11396 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11397 memcpy(fpu->fpr, fxsave->st_space, 128); 11398 fpu->fcw = fxsave->cwd; 11399 fpu->fsw = fxsave->swd; 11400 fpu->ftwx = fxsave->twd; 11401 fpu->last_opcode = fxsave->fop; 11402 fpu->last_ip = fxsave->rip; 11403 fpu->last_dp = fxsave->rdp; 11404 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 11405 11406 vcpu_put(vcpu); 11407 return 0; 11408 } 11409 11410 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11411 { 11412 struct fxregs_state *fxsave; 11413 11414 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11415 return 0; 11416 11417 vcpu_load(vcpu); 11418 11419 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11420 11421 memcpy(fxsave->st_space, fpu->fpr, 128); 11422 fxsave->cwd = fpu->fcw; 11423 fxsave->swd = fpu->fsw; 11424 fxsave->twd = fpu->ftwx; 11425 fxsave->fop = fpu->last_opcode; 11426 fxsave->rip = fpu->last_ip; 11427 fxsave->rdp = fpu->last_dp; 11428 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 11429 11430 vcpu_put(vcpu); 11431 return 0; 11432 } 11433 11434 static void store_regs(struct kvm_vcpu *vcpu) 11435 { 11436 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 11437 11438 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 11439 __get_regs(vcpu, &vcpu->run->s.regs.regs); 11440 11441 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 11442 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 11443 11444 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 11445 kvm_vcpu_ioctl_x86_get_vcpu_events( 11446 vcpu, &vcpu->run->s.regs.events); 11447 } 11448 11449 static int sync_regs(struct kvm_vcpu *vcpu) 11450 { 11451 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 11452 __set_regs(vcpu, &vcpu->run->s.regs.regs); 11453 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 11454 } 11455 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 11456 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 11457 return -EINVAL; 11458 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 11459 } 11460 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 11461 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 11462 vcpu, &vcpu->run->s.regs.events)) 11463 return -EINVAL; 11464 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 11465 } 11466 11467 return 0; 11468 } 11469 11470 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 11471 { 11472 if (kvm_check_tsc_unstable() && kvm->created_vcpus) 11473 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 11474 "guest TSC will not be reliable\n"); 11475 11476 if (!kvm->arch.max_vcpu_ids) 11477 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS; 11478 11479 if (id >= kvm->arch.max_vcpu_ids) 11480 return -EINVAL; 11481 11482 return static_call(kvm_x86_vcpu_precreate)(kvm); 11483 } 11484 11485 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 11486 { 11487 struct page *page; 11488 int r; 11489 11490 vcpu->arch.last_vmentry_cpu = -1; 11491 vcpu->arch.regs_avail = ~0; 11492 vcpu->arch.regs_dirty = ~0; 11493 11494 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 11495 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11496 else 11497 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 11498 11499 r = kvm_mmu_create(vcpu); 11500 if (r < 0) 11501 return r; 11502 11503 if (irqchip_in_kernel(vcpu->kvm)) { 11504 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 11505 if (r < 0) 11506 goto fail_mmu_destroy; 11507 11508 /* 11509 * Defer evaluating inhibits until the vCPU is first run, as 11510 * this vCPU will not get notified of any changes until this 11511 * vCPU is visible to other vCPUs (marked online and added to 11512 * the set of vCPUs). Opportunistically mark APICv active as 11513 * VMX in particularly is highly unlikely to have inhibits. 11514 * Ignore the current per-VM APICv state so that vCPU creation 11515 * is guaranteed to run with a deterministic value, the request 11516 * will ensure the vCPU gets the correct state before VM-Entry. 11517 */ 11518 if (enable_apicv) { 11519 vcpu->arch.apic->apicv_active = true; 11520 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); 11521 } 11522 } else 11523 static_branch_inc(&kvm_has_noapic_vcpu); 11524 11525 r = -ENOMEM; 11526 11527 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 11528 if (!page) 11529 goto fail_free_lapic; 11530 vcpu->arch.pio_data = page_address(page); 11531 11532 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64), 11533 GFP_KERNEL_ACCOUNT); 11534 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64), 11535 GFP_KERNEL_ACCOUNT); 11536 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks) 11537 goto fail_free_pio_data; 11538 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 11539 11540 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 11541 GFP_KERNEL_ACCOUNT)) 11542 goto fail_free_mce_banks; 11543 11544 if (!alloc_emulate_ctxt(vcpu)) 11545 goto free_wbinvd_dirty_mask; 11546 11547 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 11548 pr_err("kvm: failed to allocate vcpu's fpu\n"); 11549 goto free_emulate_ctxt; 11550 } 11551 11552 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 11553 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 11554 11555 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 11556 11557 kvm_async_pf_hash_reset(vcpu); 11558 kvm_pmu_init(vcpu); 11559 11560 vcpu->arch.pending_external_vector = -1; 11561 vcpu->arch.preempted_in_kernel = false; 11562 11563 #if IS_ENABLED(CONFIG_HYPERV) 11564 vcpu->arch.hv_root_tdp = INVALID_PAGE; 11565 #endif 11566 11567 r = static_call(kvm_x86_vcpu_create)(vcpu); 11568 if (r) 11569 goto free_guest_fpu; 11570 11571 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 11572 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 11573 kvm_xen_init_vcpu(vcpu); 11574 kvm_vcpu_mtrr_init(vcpu); 11575 vcpu_load(vcpu); 11576 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz); 11577 kvm_vcpu_reset(vcpu, false); 11578 kvm_init_mmu(vcpu); 11579 vcpu_put(vcpu); 11580 return 0; 11581 11582 free_guest_fpu: 11583 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11584 free_emulate_ctxt: 11585 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11586 free_wbinvd_dirty_mask: 11587 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11588 fail_free_mce_banks: 11589 kfree(vcpu->arch.mce_banks); 11590 kfree(vcpu->arch.mci_ctl2_banks); 11591 fail_free_pio_data: 11592 free_page((unsigned long)vcpu->arch.pio_data); 11593 fail_free_lapic: 11594 kvm_free_lapic(vcpu); 11595 fail_mmu_destroy: 11596 kvm_mmu_destroy(vcpu); 11597 return r; 11598 } 11599 11600 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 11601 { 11602 struct kvm *kvm = vcpu->kvm; 11603 11604 if (mutex_lock_killable(&vcpu->mutex)) 11605 return; 11606 vcpu_load(vcpu); 11607 kvm_synchronize_tsc(vcpu, 0); 11608 vcpu_put(vcpu); 11609 11610 /* poll control enabled by default */ 11611 vcpu->arch.msr_kvm_poll_control = 1; 11612 11613 mutex_unlock(&vcpu->mutex); 11614 11615 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 11616 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 11617 KVMCLOCK_SYNC_PERIOD); 11618 } 11619 11620 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 11621 { 11622 int idx; 11623 11624 kvmclock_reset(vcpu); 11625 11626 static_call(kvm_x86_vcpu_free)(vcpu); 11627 11628 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11629 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11630 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11631 11632 kvm_xen_destroy_vcpu(vcpu); 11633 kvm_hv_vcpu_uninit(vcpu); 11634 kvm_pmu_destroy(vcpu); 11635 kfree(vcpu->arch.mce_banks); 11636 kfree(vcpu->arch.mci_ctl2_banks); 11637 kvm_free_lapic(vcpu); 11638 idx = srcu_read_lock(&vcpu->kvm->srcu); 11639 kvm_mmu_destroy(vcpu); 11640 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11641 free_page((unsigned long)vcpu->arch.pio_data); 11642 kvfree(vcpu->arch.cpuid_entries); 11643 if (!lapic_in_kernel(vcpu)) 11644 static_branch_dec(&kvm_has_noapic_vcpu); 11645 } 11646 11647 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 11648 { 11649 struct kvm_cpuid_entry2 *cpuid_0x1; 11650 unsigned long old_cr0 = kvm_read_cr0(vcpu); 11651 unsigned long new_cr0; 11652 11653 /* 11654 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 11655 * to handle side effects. RESET emulation hits those flows and relies 11656 * on emulated/virtualized registers, including those that are loaded 11657 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 11658 * to detect improper or missing initialization. 11659 */ 11660 WARN_ON_ONCE(!init_event && 11661 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 11662 11663 kvm_lapic_reset(vcpu, init_event); 11664 11665 vcpu->arch.hflags = 0; 11666 11667 vcpu->arch.smi_pending = 0; 11668 vcpu->arch.smi_count = 0; 11669 atomic_set(&vcpu->arch.nmi_queued, 0); 11670 vcpu->arch.nmi_pending = 0; 11671 vcpu->arch.nmi_injected = false; 11672 kvm_clear_interrupt_queue(vcpu); 11673 kvm_clear_exception_queue(vcpu); 11674 11675 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 11676 kvm_update_dr0123(vcpu); 11677 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 11678 vcpu->arch.dr7 = DR7_FIXED_1; 11679 kvm_update_dr7(vcpu); 11680 11681 vcpu->arch.cr2 = 0; 11682 11683 kvm_make_request(KVM_REQ_EVENT, vcpu); 11684 vcpu->arch.apf.msr_en_val = 0; 11685 vcpu->arch.apf.msr_int_val = 0; 11686 vcpu->arch.st.msr_val = 0; 11687 11688 kvmclock_reset(vcpu); 11689 11690 kvm_clear_async_pf_completion_queue(vcpu); 11691 kvm_async_pf_hash_reset(vcpu); 11692 vcpu->arch.apf.halted = false; 11693 11694 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 11695 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 11696 11697 /* 11698 * To avoid have the INIT path from kvm_apic_has_events() that be 11699 * called with loaded FPU and does not let userspace fix the state. 11700 */ 11701 if (init_event) 11702 kvm_put_guest_fpu(vcpu); 11703 11704 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 11705 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 11706 11707 if (init_event) 11708 kvm_load_guest_fpu(vcpu); 11709 } 11710 11711 if (!init_event) { 11712 kvm_pmu_reset(vcpu); 11713 vcpu->arch.smbase = 0x30000; 11714 11715 vcpu->arch.msr_misc_features_enables = 0; 11716 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | 11717 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL; 11718 11719 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); 11720 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); 11721 } 11722 11723 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 11724 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 11725 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 11726 11727 /* 11728 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 11729 * if no CPUID match is found. Note, it's impossible to get a match at 11730 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 11731 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 11732 * on RESET. But, go through the motions in case that's ever remedied. 11733 */ 11734 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0); 11735 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 11736 11737 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 11738 11739 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 11740 kvm_rip_write(vcpu, 0xfff0); 11741 11742 vcpu->arch.cr3 = 0; 11743 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11744 11745 /* 11746 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 11747 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 11748 * (or qualify) that with a footnote stating that CD/NW are preserved. 11749 */ 11750 new_cr0 = X86_CR0_ET; 11751 if (init_event) 11752 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 11753 else 11754 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 11755 11756 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 11757 static_call(kvm_x86_set_cr4)(vcpu, 0); 11758 static_call(kvm_x86_set_efer)(vcpu, 0); 11759 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11760 11761 /* 11762 * On the standard CR0/CR4/EFER modification paths, there are several 11763 * complex conditions determining whether the MMU has to be reset and/or 11764 * which PCIDs have to be flushed. However, CR0.WP and the paging-related 11765 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush 11766 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as 11767 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here. 11768 */ 11769 if (old_cr0 & X86_CR0_PG) { 11770 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11771 kvm_mmu_reset_context(vcpu); 11772 } 11773 11774 /* 11775 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 11776 * APM states the TLBs are untouched by INIT, but it also states that 11777 * the TLBs are flushed on "External initialization of the processor." 11778 * Flush the guest TLB regardless of vendor, there is no meaningful 11779 * benefit in relying on the guest to flush the TLB immediately after 11780 * INIT. A spurious TLB flush is benign and likely negligible from a 11781 * performance perspective. 11782 */ 11783 if (init_event) 11784 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11785 } 11786 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 11787 11788 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 11789 { 11790 struct kvm_segment cs; 11791 11792 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 11793 cs.selector = vector << 8; 11794 cs.base = vector << 12; 11795 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 11796 kvm_rip_write(vcpu, 0); 11797 } 11798 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 11799 11800 int kvm_arch_hardware_enable(void) 11801 { 11802 struct kvm *kvm; 11803 struct kvm_vcpu *vcpu; 11804 unsigned long i; 11805 int ret; 11806 u64 local_tsc; 11807 u64 max_tsc = 0; 11808 bool stable, backwards_tsc = false; 11809 11810 kvm_user_return_msr_cpu_online(); 11811 ret = static_call(kvm_x86_hardware_enable)(); 11812 if (ret != 0) 11813 return ret; 11814 11815 local_tsc = rdtsc(); 11816 stable = !kvm_check_tsc_unstable(); 11817 list_for_each_entry(kvm, &vm_list, vm_list) { 11818 kvm_for_each_vcpu(i, vcpu, kvm) { 11819 if (!stable && vcpu->cpu == smp_processor_id()) 11820 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 11821 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 11822 backwards_tsc = true; 11823 if (vcpu->arch.last_host_tsc > max_tsc) 11824 max_tsc = vcpu->arch.last_host_tsc; 11825 } 11826 } 11827 } 11828 11829 /* 11830 * Sometimes, even reliable TSCs go backwards. This happens on 11831 * platforms that reset TSC during suspend or hibernate actions, but 11832 * maintain synchronization. We must compensate. Fortunately, we can 11833 * detect that condition here, which happens early in CPU bringup, 11834 * before any KVM threads can be running. Unfortunately, we can't 11835 * bring the TSCs fully up to date with real time, as we aren't yet far 11836 * enough into CPU bringup that we know how much real time has actually 11837 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 11838 * variables that haven't been updated yet. 11839 * 11840 * So we simply find the maximum observed TSC above, then record the 11841 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 11842 * the adjustment will be applied. Note that we accumulate 11843 * adjustments, in case multiple suspend cycles happen before some VCPU 11844 * gets a chance to run again. In the event that no KVM threads get a 11845 * chance to run, we will miss the entire elapsed period, as we'll have 11846 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 11847 * loose cycle time. This isn't too big a deal, since the loss will be 11848 * uniform across all VCPUs (not to mention the scenario is extremely 11849 * unlikely). It is possible that a second hibernate recovery happens 11850 * much faster than a first, causing the observed TSC here to be 11851 * smaller; this would require additional padding adjustment, which is 11852 * why we set last_host_tsc to the local tsc observed here. 11853 * 11854 * N.B. - this code below runs only on platforms with reliable TSC, 11855 * as that is the only way backwards_tsc is set above. Also note 11856 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 11857 * have the same delta_cyc adjustment applied if backwards_tsc 11858 * is detected. Note further, this adjustment is only done once, 11859 * as we reset last_host_tsc on all VCPUs to stop this from being 11860 * called multiple times (one for each physical CPU bringup). 11861 * 11862 * Platforms with unreliable TSCs don't have to deal with this, they 11863 * will be compensated by the logic in vcpu_load, which sets the TSC to 11864 * catchup mode. This will catchup all VCPUs to real time, but cannot 11865 * guarantee that they stay in perfect synchronization. 11866 */ 11867 if (backwards_tsc) { 11868 u64 delta_cyc = max_tsc - local_tsc; 11869 list_for_each_entry(kvm, &vm_list, vm_list) { 11870 kvm->arch.backwards_tsc_observed = true; 11871 kvm_for_each_vcpu(i, vcpu, kvm) { 11872 vcpu->arch.tsc_offset_adjustment += delta_cyc; 11873 vcpu->arch.last_host_tsc = local_tsc; 11874 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 11875 } 11876 11877 /* 11878 * We have to disable TSC offset matching.. if you were 11879 * booting a VM while issuing an S4 host suspend.... 11880 * you may have some problem. Solving this issue is 11881 * left as an exercise to the reader. 11882 */ 11883 kvm->arch.last_tsc_nsec = 0; 11884 kvm->arch.last_tsc_write = 0; 11885 } 11886 11887 } 11888 return 0; 11889 } 11890 11891 void kvm_arch_hardware_disable(void) 11892 { 11893 static_call(kvm_x86_hardware_disable)(); 11894 drop_user_return_notifiers(); 11895 } 11896 11897 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops) 11898 { 11899 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 11900 11901 #define __KVM_X86_OP(func) \ 11902 static_call_update(kvm_x86_##func, kvm_x86_ops.func); 11903 #define KVM_X86_OP(func) \ 11904 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func) 11905 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP 11906 #define KVM_X86_OP_OPTIONAL_RET0(func) \ 11907 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \ 11908 (void *)__static_call_return0); 11909 #include <asm/kvm-x86-ops.h> 11910 #undef __KVM_X86_OP 11911 11912 kvm_pmu_ops_update(ops->pmu_ops); 11913 } 11914 11915 int kvm_arch_hardware_setup(void *opaque) 11916 { 11917 struct kvm_x86_init_ops *ops = opaque; 11918 int r; 11919 11920 rdmsrl_safe(MSR_EFER, &host_efer); 11921 11922 if (boot_cpu_has(X86_FEATURE_XSAVES)) 11923 rdmsrl(MSR_IA32_XSS, host_xss); 11924 11925 kvm_init_pmu_capability(); 11926 11927 r = ops->hardware_setup(); 11928 if (r != 0) 11929 return r; 11930 11931 kvm_ops_update(ops); 11932 11933 kvm_register_perf_callbacks(ops->handle_intel_pt_intr); 11934 11935 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 11936 kvm_caps.supported_xss = 0; 11937 11938 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 11939 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 11940 #undef __kvm_cpu_cap_has 11941 11942 if (kvm_caps.has_tsc_control) { 11943 /* 11944 * Make sure the user can only configure tsc_khz values that 11945 * fit into a signed integer. 11946 * A min value is not calculated because it will always 11947 * be 1 on all machines. 11948 */ 11949 u64 max = min(0x7fffffffULL, 11950 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz)); 11951 kvm_caps.max_guest_tsc_khz = max; 11952 } 11953 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits; 11954 kvm_init_msr_list(); 11955 return 0; 11956 } 11957 11958 void kvm_arch_hardware_unsetup(void) 11959 { 11960 kvm_unregister_perf_callbacks(); 11961 11962 static_call(kvm_x86_hardware_unsetup)(); 11963 } 11964 11965 int kvm_arch_check_processor_compat(void *opaque) 11966 { 11967 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 11968 struct kvm_x86_init_ops *ops = opaque; 11969 11970 WARN_ON(!irqs_disabled()); 11971 11972 if (__cr4_reserved_bits(cpu_has, c) != 11973 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 11974 return -EIO; 11975 11976 return ops->check_processor_compatibility(); 11977 } 11978 11979 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 11980 { 11981 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 11982 } 11983 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 11984 11985 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 11986 { 11987 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 11988 } 11989 11990 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 11991 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 11992 11993 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 11994 { 11995 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 11996 11997 vcpu->arch.l1tf_flush_l1d = true; 11998 if (pmu->version && unlikely(pmu->event_count)) { 11999 pmu->need_cleanup = true; 12000 kvm_make_request(KVM_REQ_PMU, vcpu); 12001 } 12002 static_call(kvm_x86_sched_in)(vcpu, cpu); 12003 } 12004 12005 void kvm_arch_free_vm(struct kvm *kvm) 12006 { 12007 kfree(to_kvm_hv(kvm)->hv_pa_pg); 12008 __kvm_arch_free_vm(kvm); 12009 } 12010 12011 12012 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 12013 { 12014 int ret; 12015 unsigned long flags; 12016 12017 if (type) 12018 return -EINVAL; 12019 12020 ret = kvm_page_track_init(kvm); 12021 if (ret) 12022 goto out; 12023 12024 ret = kvm_mmu_init_vm(kvm); 12025 if (ret) 12026 goto out_page_track; 12027 12028 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 12029 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 12030 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 12031 12032 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 12033 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 12034 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 12035 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 12036 &kvm->arch.irq_sources_bitmap); 12037 12038 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 12039 mutex_init(&kvm->arch.apic_map_lock); 12040 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 12041 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 12042 12043 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 12044 pvclock_update_vm_gtod_copy(kvm); 12045 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 12046 12047 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz; 12048 kvm->arch.guest_can_read_msr_platform_info = true; 12049 kvm->arch.enable_pmu = enable_pmu; 12050 12051 #if IS_ENABLED(CONFIG_HYPERV) 12052 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 12053 kvm->arch.hv_root_tdp = INVALID_PAGE; 12054 #endif 12055 12056 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 12057 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 12058 12059 kvm_apicv_init(kvm); 12060 kvm_hv_init_vm(kvm); 12061 kvm_xen_init_vm(kvm); 12062 12063 return static_call(kvm_x86_vm_init)(kvm); 12064 12065 out_page_track: 12066 kvm_page_track_cleanup(kvm); 12067 out: 12068 return ret; 12069 } 12070 12071 int kvm_arch_post_init_vm(struct kvm *kvm) 12072 { 12073 return kvm_mmu_post_init_vm(kvm); 12074 } 12075 12076 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 12077 { 12078 vcpu_load(vcpu); 12079 kvm_mmu_unload(vcpu); 12080 vcpu_put(vcpu); 12081 } 12082 12083 static void kvm_unload_vcpu_mmus(struct kvm *kvm) 12084 { 12085 unsigned long i; 12086 struct kvm_vcpu *vcpu; 12087 12088 kvm_for_each_vcpu(i, vcpu, kvm) { 12089 kvm_clear_async_pf_completion_queue(vcpu); 12090 kvm_unload_vcpu_mmu(vcpu); 12091 } 12092 } 12093 12094 void kvm_arch_sync_events(struct kvm *kvm) 12095 { 12096 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 12097 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 12098 kvm_free_pit(kvm); 12099 } 12100 12101 /** 12102 * __x86_set_memory_region: Setup KVM internal memory slot 12103 * 12104 * @kvm: the kvm pointer to the VM. 12105 * @id: the slot ID to setup. 12106 * @gpa: the GPA to install the slot (unused when @size == 0). 12107 * @size: the size of the slot. Set to zero to uninstall a slot. 12108 * 12109 * This function helps to setup a KVM internal memory slot. Specify 12110 * @size > 0 to install a new slot, while @size == 0 to uninstall a 12111 * slot. The return code can be one of the following: 12112 * 12113 * HVA: on success (uninstall will return a bogus HVA) 12114 * -errno: on error 12115 * 12116 * The caller should always use IS_ERR() to check the return value 12117 * before use. Note, the KVM internal memory slots are guaranteed to 12118 * remain valid and unchanged until the VM is destroyed, i.e., the 12119 * GPA->HVA translation will not change. However, the HVA is a user 12120 * address, i.e. its accessibility is not guaranteed, and must be 12121 * accessed via __copy_{to,from}_user(). 12122 */ 12123 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 12124 u32 size) 12125 { 12126 int i, r; 12127 unsigned long hva, old_npages; 12128 struct kvm_memslots *slots = kvm_memslots(kvm); 12129 struct kvm_memory_slot *slot; 12130 12131 /* Called with kvm->slots_lock held. */ 12132 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 12133 return ERR_PTR_USR(-EINVAL); 12134 12135 slot = id_to_memslot(slots, id); 12136 if (size) { 12137 if (slot && slot->npages) 12138 return ERR_PTR_USR(-EEXIST); 12139 12140 /* 12141 * MAP_SHARED to prevent internal slot pages from being moved 12142 * by fork()/COW. 12143 */ 12144 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 12145 MAP_SHARED | MAP_ANONYMOUS, 0); 12146 if (IS_ERR((void *)hva)) 12147 return (void __user *)hva; 12148 } else { 12149 if (!slot || !slot->npages) 12150 return NULL; 12151 12152 old_npages = slot->npages; 12153 hva = slot->userspace_addr; 12154 } 12155 12156 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 12157 struct kvm_userspace_memory_region m; 12158 12159 m.slot = id | (i << 16); 12160 m.flags = 0; 12161 m.guest_phys_addr = gpa; 12162 m.userspace_addr = hva; 12163 m.memory_size = size; 12164 r = __kvm_set_memory_region(kvm, &m); 12165 if (r < 0) 12166 return ERR_PTR_USR(r); 12167 } 12168 12169 if (!size) 12170 vm_munmap(hva, old_npages * PAGE_SIZE); 12171 12172 return (void __user *)hva; 12173 } 12174 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 12175 12176 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 12177 { 12178 kvm_mmu_pre_destroy_vm(kvm); 12179 } 12180 12181 void kvm_arch_destroy_vm(struct kvm *kvm) 12182 { 12183 if (current->mm == kvm->mm) { 12184 /* 12185 * Free memory regions allocated on behalf of userspace, 12186 * unless the memory map has changed due to process exit 12187 * or fd copying. 12188 */ 12189 mutex_lock(&kvm->slots_lock); 12190 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 12191 0, 0); 12192 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 12193 0, 0); 12194 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 12195 mutex_unlock(&kvm->slots_lock); 12196 } 12197 kvm_unload_vcpu_mmus(kvm); 12198 static_call_cond(kvm_x86_vm_destroy)(kvm); 12199 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 12200 kvm_pic_destroy(kvm); 12201 kvm_ioapic_destroy(kvm); 12202 kvm_destroy_vcpus(kvm); 12203 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 12204 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 12205 kvm_mmu_uninit_vm(kvm); 12206 kvm_page_track_cleanup(kvm); 12207 kvm_xen_destroy_vm(kvm); 12208 kvm_hv_destroy_vm(kvm); 12209 } 12210 12211 static void memslot_rmap_free(struct kvm_memory_slot *slot) 12212 { 12213 int i; 12214 12215 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12216 kvfree(slot->arch.rmap[i]); 12217 slot->arch.rmap[i] = NULL; 12218 } 12219 } 12220 12221 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 12222 { 12223 int i; 12224 12225 memslot_rmap_free(slot); 12226 12227 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12228 kvfree(slot->arch.lpage_info[i - 1]); 12229 slot->arch.lpage_info[i - 1] = NULL; 12230 } 12231 12232 kvm_page_track_free_memslot(slot); 12233 } 12234 12235 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 12236 { 12237 const int sz = sizeof(*slot->arch.rmap[0]); 12238 int i; 12239 12240 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12241 int level = i + 1; 12242 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12243 12244 if (slot->arch.rmap[i]) 12245 continue; 12246 12247 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 12248 if (!slot->arch.rmap[i]) { 12249 memslot_rmap_free(slot); 12250 return -ENOMEM; 12251 } 12252 } 12253 12254 return 0; 12255 } 12256 12257 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 12258 struct kvm_memory_slot *slot) 12259 { 12260 unsigned long npages = slot->npages; 12261 int i, r; 12262 12263 /* 12264 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 12265 * old arrays will be freed by __kvm_set_memory_region() if installing 12266 * the new memslot is successful. 12267 */ 12268 memset(&slot->arch, 0, sizeof(slot->arch)); 12269 12270 if (kvm_memslots_have_rmaps(kvm)) { 12271 r = memslot_rmap_alloc(slot, npages); 12272 if (r) 12273 return r; 12274 } 12275 12276 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12277 struct kvm_lpage_info *linfo; 12278 unsigned long ugfn; 12279 int lpages; 12280 int level = i + 1; 12281 12282 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12283 12284 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 12285 if (!linfo) 12286 goto out_free; 12287 12288 slot->arch.lpage_info[i - 1] = linfo; 12289 12290 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 12291 linfo[0].disallow_lpage = 1; 12292 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 12293 linfo[lpages - 1].disallow_lpage = 1; 12294 ugfn = slot->userspace_addr >> PAGE_SHIFT; 12295 /* 12296 * If the gfn and userspace address are not aligned wrt each 12297 * other, disable large page support for this slot. 12298 */ 12299 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 12300 unsigned long j; 12301 12302 for (j = 0; j < lpages; ++j) 12303 linfo[j].disallow_lpage = 1; 12304 } 12305 } 12306 12307 if (kvm_page_track_create_memslot(kvm, slot, npages)) 12308 goto out_free; 12309 12310 return 0; 12311 12312 out_free: 12313 memslot_rmap_free(slot); 12314 12315 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12316 kvfree(slot->arch.lpage_info[i - 1]); 12317 slot->arch.lpage_info[i - 1] = NULL; 12318 } 12319 return -ENOMEM; 12320 } 12321 12322 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 12323 { 12324 struct kvm_vcpu *vcpu; 12325 unsigned long i; 12326 12327 /* 12328 * memslots->generation has been incremented. 12329 * mmio generation may have reached its maximum value. 12330 */ 12331 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 12332 12333 /* Force re-initialization of steal_time cache */ 12334 kvm_for_each_vcpu(i, vcpu, kvm) 12335 kvm_vcpu_kick(vcpu); 12336 } 12337 12338 int kvm_arch_prepare_memory_region(struct kvm *kvm, 12339 const struct kvm_memory_slot *old, 12340 struct kvm_memory_slot *new, 12341 enum kvm_mr_change change) 12342 { 12343 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) { 12344 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn()) 12345 return -EINVAL; 12346 12347 return kvm_alloc_memslot_metadata(kvm, new); 12348 } 12349 12350 if (change == KVM_MR_FLAGS_ONLY) 12351 memcpy(&new->arch, &old->arch, sizeof(old->arch)); 12352 else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) 12353 return -EIO; 12354 12355 return 0; 12356 } 12357 12358 12359 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 12360 { 12361 struct kvm_arch *ka = &kvm->arch; 12362 12363 if (!kvm_x86_ops.cpu_dirty_log_size) 12364 return; 12365 12366 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 12367 (!enable && --ka->cpu_dirty_logging_count == 0)) 12368 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 12369 12370 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 12371 } 12372 12373 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 12374 struct kvm_memory_slot *old, 12375 const struct kvm_memory_slot *new, 12376 enum kvm_mr_change change) 12377 { 12378 u32 old_flags = old ? old->flags : 0; 12379 u32 new_flags = new ? new->flags : 0; 12380 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; 12381 12382 /* 12383 * Update CPU dirty logging if dirty logging is being toggled. This 12384 * applies to all operations. 12385 */ 12386 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) 12387 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 12388 12389 /* 12390 * Nothing more to do for RO slots (which can't be dirtied and can't be 12391 * made writable) or CREATE/MOVE/DELETE of a slot. 12392 * 12393 * For a memslot with dirty logging disabled: 12394 * CREATE: No dirty mappings will already exist. 12395 * MOVE/DELETE: The old mappings will already have been cleaned up by 12396 * kvm_arch_flush_shadow_memslot() 12397 * 12398 * For a memslot with dirty logging enabled: 12399 * CREATE: No shadow pages exist, thus nothing to write-protect 12400 * and no dirty bits to clear. 12401 * MOVE/DELETE: The old mappings will already have been cleaned up by 12402 * kvm_arch_flush_shadow_memslot(). 12403 */ 12404 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) 12405 return; 12406 12407 /* 12408 * READONLY and non-flags changes were filtered out above, and the only 12409 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 12410 * logging isn't being toggled on or off. 12411 */ 12412 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) 12413 return; 12414 12415 if (!log_dirty_pages) { 12416 /* 12417 * Dirty logging tracks sptes in 4k granularity, meaning that 12418 * large sptes have to be split. If live migration succeeds, 12419 * the guest in the source machine will be destroyed and large 12420 * sptes will be created in the destination. However, if the 12421 * guest continues to run in the source machine (for example if 12422 * live migration fails), small sptes will remain around and 12423 * cause bad performance. 12424 * 12425 * Scan sptes if dirty logging has been stopped, dropping those 12426 * which can be collapsed into a single large-page spte. Later 12427 * page faults will create the large-page sptes. 12428 */ 12429 kvm_mmu_zap_collapsible_sptes(kvm, new); 12430 } else { 12431 /* 12432 * Initially-all-set does not require write protecting any page, 12433 * because they're all assumed to be dirty. 12434 */ 12435 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 12436 return; 12437 12438 if (READ_ONCE(eager_page_split)) 12439 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); 12440 12441 if (kvm_x86_ops.cpu_dirty_log_size) { 12442 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 12443 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 12444 } else { 12445 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 12446 } 12447 } 12448 } 12449 12450 void kvm_arch_commit_memory_region(struct kvm *kvm, 12451 struct kvm_memory_slot *old, 12452 const struct kvm_memory_slot *new, 12453 enum kvm_mr_change change) 12454 { 12455 if (!kvm->arch.n_requested_mmu_pages && 12456 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { 12457 unsigned long nr_mmu_pages; 12458 12459 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; 12460 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); 12461 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 12462 } 12463 12464 kvm_mmu_slot_apply_flags(kvm, old, new, change); 12465 12466 /* Free the arrays associated with the old memslot. */ 12467 if (change == KVM_MR_MOVE) 12468 kvm_arch_free_memslot(kvm, old); 12469 } 12470 12471 void kvm_arch_flush_shadow_all(struct kvm *kvm) 12472 { 12473 kvm_mmu_zap_all(kvm); 12474 } 12475 12476 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 12477 struct kvm_memory_slot *slot) 12478 { 12479 kvm_page_track_flush_slot(kvm, slot); 12480 } 12481 12482 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 12483 { 12484 return (is_guest_mode(vcpu) && 12485 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 12486 } 12487 12488 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 12489 { 12490 if (!list_empty_careful(&vcpu->async_pf.done)) 12491 return true; 12492 12493 if (kvm_apic_has_events(vcpu)) 12494 return true; 12495 12496 if (vcpu->arch.pv.pv_unhalted) 12497 return true; 12498 12499 if (vcpu->arch.exception.pending) 12500 return true; 12501 12502 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12503 (vcpu->arch.nmi_pending && 12504 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 12505 return true; 12506 12507 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 12508 (vcpu->arch.smi_pending && 12509 static_call(kvm_x86_smi_allowed)(vcpu, false))) 12510 return true; 12511 12512 if (kvm_arch_interrupt_allowed(vcpu) && 12513 (kvm_cpu_has_interrupt(vcpu) || 12514 kvm_guest_apic_has_interrupt(vcpu))) 12515 return true; 12516 12517 if (kvm_hv_has_stimer_pending(vcpu)) 12518 return true; 12519 12520 if (is_guest_mode(vcpu) && 12521 kvm_x86_ops.nested_ops->hv_timer_pending && 12522 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 12523 return true; 12524 12525 if (kvm_xen_has_pending_events(vcpu)) 12526 return true; 12527 12528 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) 12529 return true; 12530 12531 return false; 12532 } 12533 12534 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 12535 { 12536 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 12537 } 12538 12539 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 12540 { 12541 if (kvm_vcpu_apicv_active(vcpu) && 12542 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 12543 return true; 12544 12545 return false; 12546 } 12547 12548 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 12549 { 12550 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 12551 return true; 12552 12553 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12554 kvm_test_request(KVM_REQ_SMI, vcpu) || 12555 kvm_test_request(KVM_REQ_EVENT, vcpu)) 12556 return true; 12557 12558 return kvm_arch_dy_has_pending_interrupt(vcpu); 12559 } 12560 12561 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 12562 { 12563 if (vcpu->arch.guest_state_protected) 12564 return true; 12565 12566 return vcpu->arch.preempted_in_kernel; 12567 } 12568 12569 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 12570 { 12571 return kvm_rip_read(vcpu); 12572 } 12573 12574 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 12575 { 12576 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 12577 } 12578 12579 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 12580 { 12581 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 12582 } 12583 12584 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 12585 { 12586 /* Can't read the RIP when guest state is protected, just return 0 */ 12587 if (vcpu->arch.guest_state_protected) 12588 return 0; 12589 12590 if (is_64_bit_mode(vcpu)) 12591 return kvm_rip_read(vcpu); 12592 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 12593 kvm_rip_read(vcpu)); 12594 } 12595 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 12596 12597 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 12598 { 12599 return kvm_get_linear_rip(vcpu) == linear_rip; 12600 } 12601 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 12602 12603 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 12604 { 12605 unsigned long rflags; 12606 12607 rflags = static_call(kvm_x86_get_rflags)(vcpu); 12608 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 12609 rflags &= ~X86_EFLAGS_TF; 12610 return rflags; 12611 } 12612 EXPORT_SYMBOL_GPL(kvm_get_rflags); 12613 12614 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12615 { 12616 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 12617 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 12618 rflags |= X86_EFLAGS_TF; 12619 static_call(kvm_x86_set_rflags)(vcpu, rflags); 12620 } 12621 12622 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12623 { 12624 __kvm_set_rflags(vcpu, rflags); 12625 kvm_make_request(KVM_REQ_EVENT, vcpu); 12626 } 12627 EXPORT_SYMBOL_GPL(kvm_set_rflags); 12628 12629 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 12630 { 12631 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 12632 12633 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 12634 } 12635 12636 static inline u32 kvm_async_pf_next_probe(u32 key) 12637 { 12638 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 12639 } 12640 12641 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12642 { 12643 u32 key = kvm_async_pf_hash_fn(gfn); 12644 12645 while (vcpu->arch.apf.gfns[key] != ~0) 12646 key = kvm_async_pf_next_probe(key); 12647 12648 vcpu->arch.apf.gfns[key] = gfn; 12649 } 12650 12651 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 12652 { 12653 int i; 12654 u32 key = kvm_async_pf_hash_fn(gfn); 12655 12656 for (i = 0; i < ASYNC_PF_PER_VCPU && 12657 (vcpu->arch.apf.gfns[key] != gfn && 12658 vcpu->arch.apf.gfns[key] != ~0); i++) 12659 key = kvm_async_pf_next_probe(key); 12660 12661 return key; 12662 } 12663 12664 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12665 { 12666 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 12667 } 12668 12669 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12670 { 12671 u32 i, j, k; 12672 12673 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 12674 12675 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 12676 return; 12677 12678 while (true) { 12679 vcpu->arch.apf.gfns[i] = ~0; 12680 do { 12681 j = kvm_async_pf_next_probe(j); 12682 if (vcpu->arch.apf.gfns[j] == ~0) 12683 return; 12684 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 12685 /* 12686 * k lies cyclically in ]i,j] 12687 * | i.k.j | 12688 * |....j i.k.| or |.k..j i...| 12689 */ 12690 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 12691 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 12692 i = j; 12693 } 12694 } 12695 12696 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 12697 { 12698 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 12699 12700 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 12701 sizeof(reason)); 12702 } 12703 12704 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 12705 { 12706 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12707 12708 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12709 &token, offset, sizeof(token)); 12710 } 12711 12712 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 12713 { 12714 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12715 u32 val; 12716 12717 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12718 &val, offset, sizeof(val))) 12719 return false; 12720 12721 return !val; 12722 } 12723 12724 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 12725 { 12726 12727 if (!kvm_pv_async_pf_enabled(vcpu)) 12728 return false; 12729 12730 if (vcpu->arch.apf.send_user_only && 12731 static_call(kvm_x86_get_cpl)(vcpu) == 0) 12732 return false; 12733 12734 if (is_guest_mode(vcpu)) { 12735 /* 12736 * L1 needs to opt into the special #PF vmexits that are 12737 * used to deliver async page faults. 12738 */ 12739 return vcpu->arch.apf.delivery_as_pf_vmexit; 12740 } else { 12741 /* 12742 * Play it safe in case the guest temporarily disables paging. 12743 * The real mode IDT in particular is unlikely to have a #PF 12744 * exception setup. 12745 */ 12746 return is_paging(vcpu); 12747 } 12748 } 12749 12750 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 12751 { 12752 if (unlikely(!lapic_in_kernel(vcpu) || 12753 kvm_event_needs_reinjection(vcpu) || 12754 vcpu->arch.exception.pending)) 12755 return false; 12756 12757 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 12758 return false; 12759 12760 /* 12761 * If interrupts are off we cannot even use an artificial 12762 * halt state. 12763 */ 12764 return kvm_arch_interrupt_allowed(vcpu); 12765 } 12766 12767 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 12768 struct kvm_async_pf *work) 12769 { 12770 struct x86_exception fault; 12771 12772 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 12773 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 12774 12775 if (kvm_can_deliver_async_pf(vcpu) && 12776 !apf_put_user_notpresent(vcpu)) { 12777 fault.vector = PF_VECTOR; 12778 fault.error_code_valid = true; 12779 fault.error_code = 0; 12780 fault.nested_page_fault = false; 12781 fault.address = work->arch.token; 12782 fault.async_page_fault = true; 12783 kvm_inject_page_fault(vcpu, &fault); 12784 return true; 12785 } else { 12786 /* 12787 * It is not possible to deliver a paravirtualized asynchronous 12788 * page fault, but putting the guest in an artificial halt state 12789 * can be beneficial nevertheless: if an interrupt arrives, we 12790 * can deliver it timely and perhaps the guest will schedule 12791 * another process. When the instruction that triggered a page 12792 * fault is retried, hopefully the page will be ready in the host. 12793 */ 12794 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 12795 return false; 12796 } 12797 } 12798 12799 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 12800 struct kvm_async_pf *work) 12801 { 12802 struct kvm_lapic_irq irq = { 12803 .delivery_mode = APIC_DM_FIXED, 12804 .vector = vcpu->arch.apf.vec 12805 }; 12806 12807 if (work->wakeup_all) 12808 work->arch.token = ~0; /* broadcast wakeup */ 12809 else 12810 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 12811 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 12812 12813 if ((work->wakeup_all || work->notpresent_injected) && 12814 kvm_pv_async_pf_enabled(vcpu) && 12815 !apf_put_user_ready(vcpu, work->arch.token)) { 12816 vcpu->arch.apf.pageready_pending = true; 12817 kvm_apic_set_irq(vcpu, &irq, NULL); 12818 } 12819 12820 vcpu->arch.apf.halted = false; 12821 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 12822 } 12823 12824 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 12825 { 12826 kvm_make_request(KVM_REQ_APF_READY, vcpu); 12827 if (!vcpu->arch.apf.pageready_pending) 12828 kvm_vcpu_kick(vcpu); 12829 } 12830 12831 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 12832 { 12833 if (!kvm_pv_async_pf_enabled(vcpu)) 12834 return true; 12835 else 12836 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 12837 } 12838 12839 void kvm_arch_start_assignment(struct kvm *kvm) 12840 { 12841 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 12842 static_call_cond(kvm_x86_pi_start_assignment)(kvm); 12843 } 12844 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 12845 12846 void kvm_arch_end_assignment(struct kvm *kvm) 12847 { 12848 atomic_dec(&kvm->arch.assigned_device_count); 12849 } 12850 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 12851 12852 bool kvm_arch_has_assigned_device(struct kvm *kvm) 12853 { 12854 return atomic_read(&kvm->arch.assigned_device_count); 12855 } 12856 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 12857 12858 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 12859 { 12860 atomic_inc(&kvm->arch.noncoherent_dma_count); 12861 } 12862 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 12863 12864 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 12865 { 12866 atomic_dec(&kvm->arch.noncoherent_dma_count); 12867 } 12868 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 12869 12870 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 12871 { 12872 return atomic_read(&kvm->arch.noncoherent_dma_count); 12873 } 12874 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 12875 12876 bool kvm_arch_has_irq_bypass(void) 12877 { 12878 return true; 12879 } 12880 12881 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 12882 struct irq_bypass_producer *prod) 12883 { 12884 struct kvm_kernel_irqfd *irqfd = 12885 container_of(cons, struct kvm_kernel_irqfd, consumer); 12886 int ret; 12887 12888 irqfd->producer = prod; 12889 kvm_arch_start_assignment(irqfd->kvm); 12890 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, 12891 prod->irq, irqfd->gsi, 1); 12892 12893 if (ret) 12894 kvm_arch_end_assignment(irqfd->kvm); 12895 12896 return ret; 12897 } 12898 12899 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 12900 struct irq_bypass_producer *prod) 12901 { 12902 int ret; 12903 struct kvm_kernel_irqfd *irqfd = 12904 container_of(cons, struct kvm_kernel_irqfd, consumer); 12905 12906 WARN_ON(irqfd->producer != prod); 12907 irqfd->producer = NULL; 12908 12909 /* 12910 * When producer of consumer is unregistered, we change back to 12911 * remapped mode, so we can re-use the current implementation 12912 * when the irq is masked/disabled or the consumer side (KVM 12913 * int this case doesn't want to receive the interrupts. 12914 */ 12915 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 12916 if (ret) 12917 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 12918 " fails: %d\n", irqfd->consumer.token, ret); 12919 12920 kvm_arch_end_assignment(irqfd->kvm); 12921 } 12922 12923 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 12924 uint32_t guest_irq, bool set) 12925 { 12926 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set); 12927 } 12928 12929 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 12930 struct kvm_kernel_irq_routing_entry *new) 12931 { 12932 if (new->type != KVM_IRQ_ROUTING_MSI) 12933 return true; 12934 12935 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 12936 } 12937 12938 bool kvm_vector_hashing_enabled(void) 12939 { 12940 return vector_hashing; 12941 } 12942 12943 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 12944 { 12945 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 12946 } 12947 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 12948 12949 12950 int kvm_spec_ctrl_test_value(u64 value) 12951 { 12952 /* 12953 * test that setting IA32_SPEC_CTRL to given value 12954 * is allowed by the host processor 12955 */ 12956 12957 u64 saved_value; 12958 unsigned long flags; 12959 int ret = 0; 12960 12961 local_irq_save(flags); 12962 12963 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 12964 ret = 1; 12965 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 12966 ret = 1; 12967 else 12968 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 12969 12970 local_irq_restore(flags); 12971 12972 return ret; 12973 } 12974 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 12975 12976 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 12977 { 12978 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 12979 struct x86_exception fault; 12980 u64 access = error_code & 12981 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 12982 12983 if (!(error_code & PFERR_PRESENT_MASK) || 12984 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) { 12985 /* 12986 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 12987 * tables probably do not match the TLB. Just proceed 12988 * with the error code that the processor gave. 12989 */ 12990 fault.vector = PF_VECTOR; 12991 fault.error_code_valid = true; 12992 fault.error_code = error_code; 12993 fault.nested_page_fault = false; 12994 fault.address = gva; 12995 } 12996 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 12997 } 12998 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 12999 13000 /* 13001 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 13002 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 13003 * indicates whether exit to userspace is needed. 13004 */ 13005 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 13006 struct x86_exception *e) 13007 { 13008 if (r == X86EMUL_PROPAGATE_FAULT) { 13009 kvm_inject_emulated_page_fault(vcpu, e); 13010 return 1; 13011 } 13012 13013 /* 13014 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 13015 * while handling a VMX instruction KVM could've handled the request 13016 * correctly by exiting to userspace and performing I/O but there 13017 * doesn't seem to be a real use-case behind such requests, just return 13018 * KVM_EXIT_INTERNAL_ERROR for now. 13019 */ 13020 kvm_prepare_emulation_failure_exit(vcpu); 13021 13022 return 0; 13023 } 13024 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 13025 13026 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 13027 { 13028 bool pcid_enabled; 13029 struct x86_exception e; 13030 struct { 13031 u64 pcid; 13032 u64 gla; 13033 } operand; 13034 int r; 13035 13036 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 13037 if (r != X86EMUL_CONTINUE) 13038 return kvm_handle_memory_failure(vcpu, r, &e); 13039 13040 if (operand.pcid >> 12 != 0) { 13041 kvm_inject_gp(vcpu, 0); 13042 return 1; 13043 } 13044 13045 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 13046 13047 switch (type) { 13048 case INVPCID_TYPE_INDIV_ADDR: 13049 if ((!pcid_enabled && (operand.pcid != 0)) || 13050 is_noncanonical_address(operand.gla, vcpu)) { 13051 kvm_inject_gp(vcpu, 0); 13052 return 1; 13053 } 13054 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 13055 return kvm_skip_emulated_instruction(vcpu); 13056 13057 case INVPCID_TYPE_SINGLE_CTXT: 13058 if (!pcid_enabled && (operand.pcid != 0)) { 13059 kvm_inject_gp(vcpu, 0); 13060 return 1; 13061 } 13062 13063 kvm_invalidate_pcid(vcpu, operand.pcid); 13064 return kvm_skip_emulated_instruction(vcpu); 13065 13066 case INVPCID_TYPE_ALL_NON_GLOBAL: 13067 /* 13068 * Currently, KVM doesn't mark global entries in the shadow 13069 * page tables, so a non-global flush just degenerates to a 13070 * global flush. If needed, we could optimize this later by 13071 * keeping track of global entries in shadow page tables. 13072 */ 13073 13074 fallthrough; 13075 case INVPCID_TYPE_ALL_INCL_GLOBAL: 13076 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 13077 return kvm_skip_emulated_instruction(vcpu); 13078 13079 default: 13080 kvm_inject_gp(vcpu, 0); 13081 return 1; 13082 } 13083 } 13084 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 13085 13086 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 13087 { 13088 struct kvm_run *run = vcpu->run; 13089 struct kvm_mmio_fragment *frag; 13090 unsigned int len; 13091 13092 BUG_ON(!vcpu->mmio_needed); 13093 13094 /* Complete previous fragment */ 13095 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 13096 len = min(8u, frag->len); 13097 if (!vcpu->mmio_is_write) 13098 memcpy(frag->data, run->mmio.data, len); 13099 13100 if (frag->len <= 8) { 13101 /* Switch to the next fragment. */ 13102 frag++; 13103 vcpu->mmio_cur_fragment++; 13104 } else { 13105 /* Go forward to the next mmio piece. */ 13106 frag->data += len; 13107 frag->gpa += len; 13108 frag->len -= len; 13109 } 13110 13111 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 13112 vcpu->mmio_needed = 0; 13113 13114 // VMG change, at this point, we're always done 13115 // RIP has already been advanced 13116 return 1; 13117 } 13118 13119 // More MMIO is needed 13120 run->mmio.phys_addr = frag->gpa; 13121 run->mmio.len = min(8u, frag->len); 13122 run->mmio.is_write = vcpu->mmio_is_write; 13123 if (run->mmio.is_write) 13124 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 13125 run->exit_reason = KVM_EXIT_MMIO; 13126 13127 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13128 13129 return 0; 13130 } 13131 13132 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 13133 void *data) 13134 { 13135 int handled; 13136 struct kvm_mmio_fragment *frag; 13137 13138 if (!data) 13139 return -EINVAL; 13140 13141 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 13142 if (handled == bytes) 13143 return 1; 13144 13145 bytes -= handled; 13146 gpa += handled; 13147 data += handled; 13148 13149 /*TODO: Check if need to increment number of frags */ 13150 frag = vcpu->mmio_fragments; 13151 vcpu->mmio_nr_fragments = 1; 13152 frag->len = bytes; 13153 frag->gpa = gpa; 13154 frag->data = data; 13155 13156 vcpu->mmio_needed = 1; 13157 vcpu->mmio_cur_fragment = 0; 13158 13159 vcpu->run->mmio.phys_addr = gpa; 13160 vcpu->run->mmio.len = min(8u, frag->len); 13161 vcpu->run->mmio.is_write = 1; 13162 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 13163 vcpu->run->exit_reason = KVM_EXIT_MMIO; 13164 13165 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13166 13167 return 0; 13168 } 13169 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 13170 13171 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 13172 void *data) 13173 { 13174 int handled; 13175 struct kvm_mmio_fragment *frag; 13176 13177 if (!data) 13178 return -EINVAL; 13179 13180 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 13181 if (handled == bytes) 13182 return 1; 13183 13184 bytes -= handled; 13185 gpa += handled; 13186 data += handled; 13187 13188 /*TODO: Check if need to increment number of frags */ 13189 frag = vcpu->mmio_fragments; 13190 vcpu->mmio_nr_fragments = 1; 13191 frag->len = bytes; 13192 frag->gpa = gpa; 13193 frag->data = data; 13194 13195 vcpu->mmio_needed = 1; 13196 vcpu->mmio_cur_fragment = 0; 13197 13198 vcpu->run->mmio.phys_addr = gpa; 13199 vcpu->run->mmio.len = min(8u, frag->len); 13200 vcpu->run->mmio.is_write = 0; 13201 vcpu->run->exit_reason = KVM_EXIT_MMIO; 13202 13203 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13204 13205 return 0; 13206 } 13207 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 13208 13209 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13210 unsigned int port); 13211 13212 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 13213 { 13214 int size = vcpu->arch.pio.size; 13215 int port = vcpu->arch.pio.port; 13216 13217 vcpu->arch.pio.count = 0; 13218 if (vcpu->arch.sev_pio_count) 13219 return kvm_sev_es_outs(vcpu, size, port); 13220 return 1; 13221 } 13222 13223 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13224 unsigned int port) 13225 { 13226 for (;;) { 13227 unsigned int count = 13228 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13229 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 13230 13231 /* memcpy done already by emulator_pio_out. */ 13232 vcpu->arch.sev_pio_count -= count; 13233 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 13234 if (!ret) 13235 break; 13236 13237 /* Emulation done by the kernel. */ 13238 if (!vcpu->arch.sev_pio_count) 13239 return 1; 13240 } 13241 13242 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 13243 return 0; 13244 } 13245 13246 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13247 unsigned int port); 13248 13249 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 13250 { 13251 unsigned count = vcpu->arch.pio.count; 13252 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 13253 vcpu->arch.sev_pio_count -= count; 13254 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 13255 } 13256 13257 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 13258 { 13259 int size = vcpu->arch.pio.size; 13260 int port = vcpu->arch.pio.port; 13261 13262 advance_sev_es_emulated_ins(vcpu); 13263 if (vcpu->arch.sev_pio_count) 13264 return kvm_sev_es_ins(vcpu, size, port); 13265 return 1; 13266 } 13267 13268 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13269 unsigned int port) 13270 { 13271 for (;;) { 13272 unsigned int count = 13273 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13274 if (!__emulator_pio_in(vcpu, size, port, count)) 13275 break; 13276 13277 /* Emulation done by the kernel. */ 13278 advance_sev_es_emulated_ins(vcpu); 13279 if (!vcpu->arch.sev_pio_count) 13280 return 1; 13281 } 13282 13283 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 13284 return 0; 13285 } 13286 13287 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 13288 unsigned int port, void *data, unsigned int count, 13289 int in) 13290 { 13291 vcpu->arch.sev_pio_data = data; 13292 vcpu->arch.sev_pio_count = count; 13293 return in ? kvm_sev_es_ins(vcpu, size, port) 13294 : kvm_sev_es_outs(vcpu, size, port); 13295 } 13296 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 13297 13298 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 13299 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 13300 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 13301 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 13302 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 13303 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 13304 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 13305 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 13306 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 13307 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 13308 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 13309 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 13310 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 13311 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 13312 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 13313 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 13314 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 13315 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 13316 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 13317 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 13318 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 13319 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 13320 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath); 13321 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell); 13322 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); 13323 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 13324 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 13325 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 13326 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 13327 13328 static int __init kvm_x86_init(void) 13329 { 13330 kvm_mmu_x86_module_init(); 13331 return 0; 13332 } 13333 module_init(kvm_x86_init); 13334 13335 static void __exit kvm_x86_exit(void) 13336 { 13337 /* 13338 * If module_init() is implemented, module_exit() must also be 13339 * implemented to allow module unload. 13340 */ 13341 } 13342 module_exit(kvm_x86_exit); 13343