1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "mmu.h" 22 #include "i8254.h" 23 #include "tss.h" 24 #include "kvm_cache_regs.h" 25 #include "x86.h" 26 #include "cpuid.h" 27 #include "pmu.h" 28 #include "hyperv.h" 29 #include "lapic.h" 30 31 #include <linux/clocksource.h> 32 #include <linux/interrupt.h> 33 #include <linux/kvm.h> 34 #include <linux/fs.h> 35 #include <linux/vmalloc.h> 36 #include <linux/export.h> 37 #include <linux/moduleparam.h> 38 #include <linux/mman.h> 39 #include <linux/highmem.h> 40 #include <linux/iommu.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/cpufreq.h> 43 #include <linux/user-return-notifier.h> 44 #include <linux/srcu.h> 45 #include <linux/slab.h> 46 #include <linux/perf_event.h> 47 #include <linux/uaccess.h> 48 #include <linux/hash.h> 49 #include <linux/pci.h> 50 #include <linux/timekeeper_internal.h> 51 #include <linux/pvclock_gtod.h> 52 #include <linux/kvm_irqfd.h> 53 #include <linux/irqbypass.h> 54 #include <linux/sched/stat.h> 55 #include <linux/sched/isolation.h> 56 #include <linux/mem_encrypt.h> 57 58 #include <trace/events/kvm.h> 59 60 #include <asm/debugreg.h> 61 #include <asm/msr.h> 62 #include <asm/desc.h> 63 #include <asm/mce.h> 64 #include <linux/kernel_stat.h> 65 #include <asm/fpu/internal.h> /* Ugh! */ 66 #include <asm/pvclock.h> 67 #include <asm/div64.h> 68 #include <asm/irq_remapping.h> 69 #include <asm/mshyperv.h> 70 #include <asm/hypervisor.h> 71 #include <asm/intel_pt.h> 72 #include <asm/emulate_prefix.h> 73 #include <clocksource/hyperv_timer.h> 74 75 #define CREATE_TRACE_POINTS 76 #include "trace.h" 77 78 #define MAX_IO_MSRS 256 79 #define KVM_MAX_MCE_BANKS 32 80 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 81 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 82 83 #define emul_to_vcpu(ctxt) \ 84 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 85 86 /* EFER defaults: 87 * - enable syscall per default because its emulated by KVM 88 * - enable LME and LMA per default on 64 bit KVM 89 */ 90 #ifdef CONFIG_X86_64 91 static 92 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 93 #else 94 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 95 #endif 96 97 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 98 99 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__ 100 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__ 101 102 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 103 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 104 105 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 106 static void process_nmi(struct kvm_vcpu *vcpu); 107 static void enter_smm(struct kvm_vcpu *vcpu); 108 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 109 static void store_regs(struct kvm_vcpu *vcpu); 110 static int sync_regs(struct kvm_vcpu *vcpu); 111 112 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 113 EXPORT_SYMBOL_GPL(kvm_x86_ops); 114 115 static bool __read_mostly ignore_msrs = 0; 116 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 117 118 static bool __read_mostly report_ignored_msrs = true; 119 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 120 121 unsigned int min_timer_period_us = 200; 122 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 123 124 static bool __read_mostly kvmclock_periodic_sync = true; 125 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 126 127 bool __read_mostly kvm_has_tsc_control; 128 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 129 u32 __read_mostly kvm_max_guest_tsc_khz; 130 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 131 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 132 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 133 u64 __read_mostly kvm_max_tsc_scaling_ratio; 134 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 135 u64 __read_mostly kvm_default_tsc_scaling_ratio; 136 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 137 138 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 139 static u32 __read_mostly tsc_tolerance_ppm = 250; 140 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 141 142 /* 143 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 144 * adaptive tuning starting from default advancment of 1000ns. '0' disables 145 * advancement entirely. Any other value is used as-is and disables adaptive 146 * tuning, i.e. allows priveleged userspace to set an exact advancement time. 147 */ 148 static int __read_mostly lapic_timer_advance_ns = -1; 149 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 150 151 static bool __read_mostly vector_hashing = true; 152 module_param(vector_hashing, bool, S_IRUGO); 153 154 bool __read_mostly enable_vmware_backdoor = false; 155 module_param(enable_vmware_backdoor, bool, S_IRUGO); 156 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 157 158 static bool __read_mostly force_emulation_prefix = false; 159 module_param(force_emulation_prefix, bool, S_IRUGO); 160 161 int __read_mostly pi_inject_timer = -1; 162 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 163 164 #define KVM_NR_SHARED_MSRS 16 165 166 struct kvm_shared_msrs_global { 167 int nr; 168 u32 msrs[KVM_NR_SHARED_MSRS]; 169 }; 170 171 struct kvm_shared_msrs { 172 struct user_return_notifier urn; 173 bool registered; 174 struct kvm_shared_msr_values { 175 u64 host; 176 u64 curr; 177 } values[KVM_NR_SHARED_MSRS]; 178 }; 179 180 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 181 static struct kvm_shared_msrs __percpu *shared_msrs; 182 183 static u64 __read_mostly host_xss; 184 185 struct kvm_stats_debugfs_item debugfs_entries[] = { 186 { "pf_fixed", VCPU_STAT(pf_fixed) }, 187 { "pf_guest", VCPU_STAT(pf_guest) }, 188 { "tlb_flush", VCPU_STAT(tlb_flush) }, 189 { "invlpg", VCPU_STAT(invlpg) }, 190 { "exits", VCPU_STAT(exits) }, 191 { "io_exits", VCPU_STAT(io_exits) }, 192 { "mmio_exits", VCPU_STAT(mmio_exits) }, 193 { "signal_exits", VCPU_STAT(signal_exits) }, 194 { "irq_window", VCPU_STAT(irq_window_exits) }, 195 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 196 { "halt_exits", VCPU_STAT(halt_exits) }, 197 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 198 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 199 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 200 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 201 { "hypercalls", VCPU_STAT(hypercalls) }, 202 { "request_irq", VCPU_STAT(request_irq_exits) }, 203 { "irq_exits", VCPU_STAT(irq_exits) }, 204 { "host_state_reload", VCPU_STAT(host_state_reload) }, 205 { "fpu_reload", VCPU_STAT(fpu_reload) }, 206 { "insn_emulation", VCPU_STAT(insn_emulation) }, 207 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 208 { "irq_injections", VCPU_STAT(irq_injections) }, 209 { "nmi_injections", VCPU_STAT(nmi_injections) }, 210 { "req_event", VCPU_STAT(req_event) }, 211 { "l1d_flush", VCPU_STAT(l1d_flush) }, 212 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 213 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 214 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 215 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 216 { "mmu_flooded", VM_STAT(mmu_flooded) }, 217 { "mmu_recycled", VM_STAT(mmu_recycled) }, 218 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 219 { "mmu_unsync", VM_STAT(mmu_unsync) }, 220 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 221 { "largepages", VM_STAT(lpages, .mode = 0444) }, 222 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) }, 223 { "max_mmu_page_hash_collisions", 224 VM_STAT(max_mmu_page_hash_collisions) }, 225 { NULL } 226 }; 227 228 u64 __read_mostly host_xcr0; 229 230 struct kmem_cache *x86_fpu_cache; 231 EXPORT_SYMBOL_GPL(x86_fpu_cache); 232 233 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 234 235 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 236 { 237 int i; 238 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 239 vcpu->arch.apf.gfns[i] = ~0; 240 } 241 242 static void kvm_on_user_return(struct user_return_notifier *urn) 243 { 244 unsigned slot; 245 struct kvm_shared_msrs *locals 246 = container_of(urn, struct kvm_shared_msrs, urn); 247 struct kvm_shared_msr_values *values; 248 unsigned long flags; 249 250 /* 251 * Disabling irqs at this point since the following code could be 252 * interrupted and executed through kvm_arch_hardware_disable() 253 */ 254 local_irq_save(flags); 255 if (locals->registered) { 256 locals->registered = false; 257 user_return_notifier_unregister(urn); 258 } 259 local_irq_restore(flags); 260 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 261 values = &locals->values[slot]; 262 if (values->host != values->curr) { 263 wrmsrl(shared_msrs_global.msrs[slot], values->host); 264 values->curr = values->host; 265 } 266 } 267 } 268 269 void kvm_define_shared_msr(unsigned slot, u32 msr) 270 { 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 272 shared_msrs_global.msrs[slot] = msr; 273 if (slot >= shared_msrs_global.nr) 274 shared_msrs_global.nr = slot + 1; 275 } 276 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 277 278 static void kvm_shared_msr_cpu_online(void) 279 { 280 unsigned int cpu = smp_processor_id(); 281 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 282 u64 value; 283 int i; 284 285 for (i = 0; i < shared_msrs_global.nr; ++i) { 286 rdmsrl_safe(shared_msrs_global.msrs[i], &value); 287 smsr->values[i].host = value; 288 smsr->values[i].curr = value; 289 } 290 } 291 292 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 293 { 294 unsigned int cpu = smp_processor_id(); 295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 296 int err; 297 298 value = (value & mask) | (smsr->values[slot].host & ~mask); 299 if (value == smsr->values[slot].curr) 300 return 0; 301 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 302 if (err) 303 return 1; 304 305 smsr->values[slot].curr = value; 306 if (!smsr->registered) { 307 smsr->urn.on_user_return = kvm_on_user_return; 308 user_return_notifier_register(&smsr->urn); 309 smsr->registered = true; 310 } 311 return 0; 312 } 313 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 314 315 static void drop_user_return_notifiers(void) 316 { 317 unsigned int cpu = smp_processor_id(); 318 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 319 320 if (smsr->registered) 321 kvm_on_user_return(&smsr->urn); 322 } 323 324 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 325 { 326 return vcpu->arch.apic_base; 327 } 328 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 329 330 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 331 { 332 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 333 } 334 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 335 336 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 337 { 338 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 339 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 340 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 341 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 342 343 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 344 return 1; 345 if (!msr_info->host_initiated) { 346 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 347 return 1; 348 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 349 return 1; 350 } 351 352 kvm_lapic_set_base(vcpu, msr_info->data); 353 return 0; 354 } 355 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 356 357 asmlinkage __visible void kvm_spurious_fault(void) 358 { 359 /* Fault while not rebooting. We want the trace. */ 360 BUG_ON(!kvm_rebooting); 361 } 362 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 363 364 #define EXCPT_BENIGN 0 365 #define EXCPT_CONTRIBUTORY 1 366 #define EXCPT_PF 2 367 368 static int exception_class(int vector) 369 { 370 switch (vector) { 371 case PF_VECTOR: 372 return EXCPT_PF; 373 case DE_VECTOR: 374 case TS_VECTOR: 375 case NP_VECTOR: 376 case SS_VECTOR: 377 case GP_VECTOR: 378 return EXCPT_CONTRIBUTORY; 379 default: 380 break; 381 } 382 return EXCPT_BENIGN; 383 } 384 385 #define EXCPT_FAULT 0 386 #define EXCPT_TRAP 1 387 #define EXCPT_ABORT 2 388 #define EXCPT_INTERRUPT 3 389 390 static int exception_type(int vector) 391 { 392 unsigned int mask; 393 394 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 395 return EXCPT_INTERRUPT; 396 397 mask = 1 << vector; 398 399 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 400 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 401 return EXCPT_TRAP; 402 403 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 404 return EXCPT_ABORT; 405 406 /* Reserved exceptions will result in fault */ 407 return EXCPT_FAULT; 408 } 409 410 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 411 { 412 unsigned nr = vcpu->arch.exception.nr; 413 bool has_payload = vcpu->arch.exception.has_payload; 414 unsigned long payload = vcpu->arch.exception.payload; 415 416 if (!has_payload) 417 return; 418 419 switch (nr) { 420 case DB_VECTOR: 421 /* 422 * "Certain debug exceptions may clear bit 0-3. The 423 * remaining contents of the DR6 register are never 424 * cleared by the processor". 425 */ 426 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 427 /* 428 * DR6.RTM is set by all #DB exceptions that don't clear it. 429 */ 430 vcpu->arch.dr6 |= DR6_RTM; 431 vcpu->arch.dr6 |= payload; 432 /* 433 * Bit 16 should be set in the payload whenever the #DB 434 * exception should clear DR6.RTM. This makes the payload 435 * compatible with the pending debug exceptions under VMX. 436 * Though not currently documented in the SDM, this also 437 * makes the payload compatible with the exit qualification 438 * for #DB exceptions under VMX. 439 */ 440 vcpu->arch.dr6 ^= payload & DR6_RTM; 441 break; 442 case PF_VECTOR: 443 vcpu->arch.cr2 = payload; 444 break; 445 } 446 447 vcpu->arch.exception.has_payload = false; 448 vcpu->arch.exception.payload = 0; 449 } 450 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 451 452 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 453 unsigned nr, bool has_error, u32 error_code, 454 bool has_payload, unsigned long payload, bool reinject) 455 { 456 u32 prev_nr; 457 int class1, class2; 458 459 kvm_make_request(KVM_REQ_EVENT, vcpu); 460 461 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 462 queue: 463 if (has_error && !is_protmode(vcpu)) 464 has_error = false; 465 if (reinject) { 466 /* 467 * On vmentry, vcpu->arch.exception.pending is only 468 * true if an event injection was blocked by 469 * nested_run_pending. In that case, however, 470 * vcpu_enter_guest requests an immediate exit, 471 * and the guest shouldn't proceed far enough to 472 * need reinjection. 473 */ 474 WARN_ON_ONCE(vcpu->arch.exception.pending); 475 vcpu->arch.exception.injected = true; 476 if (WARN_ON_ONCE(has_payload)) { 477 /* 478 * A reinjected event has already 479 * delivered its payload. 480 */ 481 has_payload = false; 482 payload = 0; 483 } 484 } else { 485 vcpu->arch.exception.pending = true; 486 vcpu->arch.exception.injected = false; 487 } 488 vcpu->arch.exception.has_error_code = has_error; 489 vcpu->arch.exception.nr = nr; 490 vcpu->arch.exception.error_code = error_code; 491 vcpu->arch.exception.has_payload = has_payload; 492 vcpu->arch.exception.payload = payload; 493 /* 494 * In guest mode, payload delivery should be deferred, 495 * so that the L1 hypervisor can intercept #PF before 496 * CR2 is modified (or intercept #DB before DR6 is 497 * modified under nVMX). However, for ABI 498 * compatibility with KVM_GET_VCPU_EVENTS and 499 * KVM_SET_VCPU_EVENTS, we can't delay payload 500 * delivery unless userspace has enabled this 501 * functionality via the per-VM capability, 502 * KVM_CAP_EXCEPTION_PAYLOAD. 503 */ 504 if (!vcpu->kvm->arch.exception_payload_enabled || 505 !is_guest_mode(vcpu)) 506 kvm_deliver_exception_payload(vcpu); 507 return; 508 } 509 510 /* to check exception */ 511 prev_nr = vcpu->arch.exception.nr; 512 if (prev_nr == DF_VECTOR) { 513 /* triple fault -> shutdown */ 514 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 515 return; 516 } 517 class1 = exception_class(prev_nr); 518 class2 = exception_class(nr); 519 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 520 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 521 /* 522 * Generate double fault per SDM Table 5-5. Set 523 * exception.pending = true so that the double fault 524 * can trigger a nested vmexit. 525 */ 526 vcpu->arch.exception.pending = true; 527 vcpu->arch.exception.injected = false; 528 vcpu->arch.exception.has_error_code = true; 529 vcpu->arch.exception.nr = DF_VECTOR; 530 vcpu->arch.exception.error_code = 0; 531 vcpu->arch.exception.has_payload = false; 532 vcpu->arch.exception.payload = 0; 533 } else 534 /* replace previous exception with a new one in a hope 535 that instruction re-execution will regenerate lost 536 exception */ 537 goto queue; 538 } 539 540 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 541 { 542 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 543 } 544 EXPORT_SYMBOL_GPL(kvm_queue_exception); 545 546 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 547 { 548 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 549 } 550 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 551 552 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 553 unsigned long payload) 554 { 555 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 556 } 557 558 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 559 u32 error_code, unsigned long payload) 560 { 561 kvm_multiple_exception(vcpu, nr, true, error_code, 562 true, payload, false); 563 } 564 565 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 566 { 567 if (err) 568 kvm_inject_gp(vcpu, 0); 569 else 570 return kvm_skip_emulated_instruction(vcpu); 571 572 return 1; 573 } 574 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 575 576 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 577 { 578 ++vcpu->stat.pf_guest; 579 vcpu->arch.exception.nested_apf = 580 is_guest_mode(vcpu) && fault->async_page_fault; 581 if (vcpu->arch.exception.nested_apf) { 582 vcpu->arch.apf.nested_apf_token = fault->address; 583 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 584 } else { 585 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 586 fault->address); 587 } 588 } 589 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 590 591 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 592 { 593 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 594 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 595 else 596 vcpu->arch.mmu->inject_page_fault(vcpu, fault); 597 598 return fault->nested_page_fault; 599 } 600 601 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 602 { 603 atomic_inc(&vcpu->arch.nmi_queued); 604 kvm_make_request(KVM_REQ_NMI, vcpu); 605 } 606 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 607 608 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 609 { 610 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 611 } 612 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 613 614 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 615 { 616 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 617 } 618 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 619 620 /* 621 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 622 * a #GP and return false. 623 */ 624 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 625 { 626 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 627 return true; 628 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 629 return false; 630 } 631 EXPORT_SYMBOL_GPL(kvm_require_cpl); 632 633 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 634 { 635 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 636 return true; 637 638 kvm_queue_exception(vcpu, UD_VECTOR); 639 return false; 640 } 641 EXPORT_SYMBOL_GPL(kvm_require_dr); 642 643 /* 644 * This function will be used to read from the physical memory of the currently 645 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 646 * can read from guest physical or from the guest's guest physical memory. 647 */ 648 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 649 gfn_t ngfn, void *data, int offset, int len, 650 u32 access) 651 { 652 struct x86_exception exception; 653 gfn_t real_gfn; 654 gpa_t ngpa; 655 656 ngpa = gfn_to_gpa(ngfn); 657 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 658 if (real_gfn == UNMAPPED_GVA) 659 return -EFAULT; 660 661 real_gfn = gpa_to_gfn(real_gfn); 662 663 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 664 } 665 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 666 667 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 668 void *data, int offset, int len, u32 access) 669 { 670 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 671 data, offset, len, access); 672 } 673 674 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 675 { 676 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | 677 rsvd_bits(1, 2); 678 } 679 680 /* 681 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 682 */ 683 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 684 { 685 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 686 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 687 int i; 688 int ret; 689 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 690 691 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 692 offset * sizeof(u64), sizeof(pdpte), 693 PFERR_USER_MASK|PFERR_WRITE_MASK); 694 if (ret < 0) { 695 ret = 0; 696 goto out; 697 } 698 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 699 if ((pdpte[i] & PT_PRESENT_MASK) && 700 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 701 ret = 0; 702 goto out; 703 } 704 } 705 ret = 1; 706 707 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 708 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 709 710 out: 711 712 return ret; 713 } 714 EXPORT_SYMBOL_GPL(load_pdptrs); 715 716 bool pdptrs_changed(struct kvm_vcpu *vcpu) 717 { 718 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 719 int offset; 720 gfn_t gfn; 721 int r; 722 723 if (!is_pae_paging(vcpu)) 724 return false; 725 726 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) 727 return true; 728 729 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 730 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 731 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 732 PFERR_USER_MASK | PFERR_WRITE_MASK); 733 if (r < 0) 734 return true; 735 736 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 737 } 738 EXPORT_SYMBOL_GPL(pdptrs_changed); 739 740 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 741 { 742 unsigned long old_cr0 = kvm_read_cr0(vcpu); 743 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 744 745 cr0 |= X86_CR0_ET; 746 747 #ifdef CONFIG_X86_64 748 if (cr0 & 0xffffffff00000000UL) 749 return 1; 750 #endif 751 752 cr0 &= ~CR0_RESERVED_BITS; 753 754 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 755 return 1; 756 757 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 758 return 1; 759 760 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 761 #ifdef CONFIG_X86_64 762 if ((vcpu->arch.efer & EFER_LME)) { 763 int cs_db, cs_l; 764 765 if (!is_pae(vcpu)) 766 return 1; 767 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 768 if (cs_l) 769 return 1; 770 } else 771 #endif 772 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 773 kvm_read_cr3(vcpu))) 774 return 1; 775 } 776 777 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 778 return 1; 779 780 kvm_x86_ops->set_cr0(vcpu, cr0); 781 782 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 783 kvm_clear_async_pf_completion_queue(vcpu); 784 kvm_async_pf_hash_reset(vcpu); 785 } 786 787 if ((cr0 ^ old_cr0) & update_bits) 788 kvm_mmu_reset_context(vcpu); 789 790 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 791 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 792 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 793 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 794 795 return 0; 796 } 797 EXPORT_SYMBOL_GPL(kvm_set_cr0); 798 799 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 800 { 801 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 802 } 803 EXPORT_SYMBOL_GPL(kvm_lmsw); 804 805 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 806 { 807 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 808 809 if (vcpu->arch.xcr0 != host_xcr0) 810 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 811 812 if (vcpu->arch.xsaves_enabled && 813 vcpu->arch.ia32_xss != host_xss) 814 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 815 } 816 } 817 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 818 819 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 820 { 821 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 822 823 if (vcpu->arch.xcr0 != host_xcr0) 824 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 825 826 if (vcpu->arch.xsaves_enabled && 827 vcpu->arch.ia32_xss != host_xss) 828 wrmsrl(MSR_IA32_XSS, host_xss); 829 } 830 831 } 832 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 833 834 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 835 { 836 u64 xcr0 = xcr; 837 u64 old_xcr0 = vcpu->arch.xcr0; 838 u64 valid_bits; 839 840 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 841 if (index != XCR_XFEATURE_ENABLED_MASK) 842 return 1; 843 if (!(xcr0 & XFEATURE_MASK_FP)) 844 return 1; 845 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 846 return 1; 847 848 /* 849 * Do not allow the guest to set bits that we do not support 850 * saving. However, xcr0 bit 0 is always set, even if the 851 * emulated CPU does not support XSAVE (see fx_init). 852 */ 853 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 854 if (xcr0 & ~valid_bits) 855 return 1; 856 857 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 858 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 859 return 1; 860 861 if (xcr0 & XFEATURE_MASK_AVX512) { 862 if (!(xcr0 & XFEATURE_MASK_YMM)) 863 return 1; 864 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 865 return 1; 866 } 867 vcpu->arch.xcr0 = xcr0; 868 869 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 870 kvm_update_cpuid(vcpu); 871 return 0; 872 } 873 874 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 875 { 876 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 877 __kvm_set_xcr(vcpu, index, xcr)) { 878 kvm_inject_gp(vcpu, 0); 879 return 1; 880 } 881 return 0; 882 } 883 EXPORT_SYMBOL_GPL(kvm_set_xcr); 884 885 #define __cr4_reserved_bits(__cpu_has, __c) \ 886 ({ \ 887 u64 __reserved_bits = CR4_RESERVED_BITS; \ 888 \ 889 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ 890 __reserved_bits |= X86_CR4_OSXSAVE; \ 891 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ 892 __reserved_bits |= X86_CR4_SMEP; \ 893 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ 894 __reserved_bits |= X86_CR4_SMAP; \ 895 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ 896 __reserved_bits |= X86_CR4_FSGSBASE; \ 897 if (!__cpu_has(__c, X86_FEATURE_PKU)) \ 898 __reserved_bits |= X86_CR4_PKE; \ 899 if (!__cpu_has(__c, X86_FEATURE_LA57)) \ 900 __reserved_bits |= X86_CR4_LA57; \ 901 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \ 902 __reserved_bits |= X86_CR4_UMIP; \ 903 __reserved_bits; \ 904 }) 905 906 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c) 907 { 908 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c); 909 910 if (cpuid_ecx(0x7) & feature_bit(LA57)) 911 reserved_bits &= ~X86_CR4_LA57; 912 913 if (kvm_x86_ops->umip_emulated()) 914 reserved_bits &= ~X86_CR4_UMIP; 915 916 return reserved_bits; 917 } 918 919 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 920 { 921 if (cr4 & cr4_reserved_bits) 922 return -EINVAL; 923 924 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu)) 925 return -EINVAL; 926 927 return 0; 928 } 929 930 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 931 { 932 unsigned long old_cr4 = kvm_read_cr4(vcpu); 933 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 934 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 935 936 if (kvm_valid_cr4(vcpu, cr4)) 937 return 1; 938 939 if (is_long_mode(vcpu)) { 940 if (!(cr4 & X86_CR4_PAE)) 941 return 1; 942 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 943 && ((cr4 ^ old_cr4) & pdptr_bits) 944 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 945 kvm_read_cr3(vcpu))) 946 return 1; 947 948 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 949 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 950 return 1; 951 952 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 953 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 954 return 1; 955 } 956 957 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 958 return 1; 959 960 if (((cr4 ^ old_cr4) & pdptr_bits) || 961 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 962 kvm_mmu_reset_context(vcpu); 963 964 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 965 kvm_update_cpuid(vcpu); 966 967 return 0; 968 } 969 EXPORT_SYMBOL_GPL(kvm_set_cr4); 970 971 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 972 { 973 bool skip_tlb_flush = false; 974 #ifdef CONFIG_X86_64 975 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 976 977 if (pcid_enabled) { 978 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 979 cr3 &= ~X86_CR3_PCID_NOFLUSH; 980 } 981 #endif 982 983 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 984 if (!skip_tlb_flush) { 985 kvm_mmu_sync_roots(vcpu); 986 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 987 } 988 return 0; 989 } 990 991 if (is_long_mode(vcpu) && 992 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) 993 return 1; 994 else if (is_pae_paging(vcpu) && 995 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 996 return 1; 997 998 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); 999 vcpu->arch.cr3 = cr3; 1000 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1001 1002 return 0; 1003 } 1004 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1005 1006 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1007 { 1008 if (cr8 & CR8_RESERVED_BITS) 1009 return 1; 1010 if (lapic_in_kernel(vcpu)) 1011 kvm_lapic_set_tpr(vcpu, cr8); 1012 else 1013 vcpu->arch.cr8 = cr8; 1014 return 0; 1015 } 1016 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1017 1018 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1019 { 1020 if (lapic_in_kernel(vcpu)) 1021 return kvm_lapic_get_cr8(vcpu); 1022 else 1023 return vcpu->arch.cr8; 1024 } 1025 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1026 1027 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1028 { 1029 int i; 1030 1031 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1032 for (i = 0; i < KVM_NR_DB_REGS; i++) 1033 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1034 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1035 } 1036 } 1037 1038 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 1039 { 1040 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1041 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 1042 } 1043 1044 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 1045 { 1046 unsigned long dr7; 1047 1048 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1049 dr7 = vcpu->arch.guest_debug_dr7; 1050 else 1051 dr7 = vcpu->arch.dr7; 1052 kvm_x86_ops->set_dr7(vcpu, dr7); 1053 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1054 if (dr7 & DR7_BP_EN_MASK) 1055 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1056 } 1057 1058 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1059 { 1060 u64 fixed = DR6_FIXED_1; 1061 1062 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1063 fixed |= DR6_RTM; 1064 return fixed; 1065 } 1066 1067 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1068 { 1069 size_t size = ARRAY_SIZE(vcpu->arch.db); 1070 1071 switch (dr) { 1072 case 0 ... 3: 1073 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1074 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1075 vcpu->arch.eff_db[dr] = val; 1076 break; 1077 case 4: 1078 /* fall through */ 1079 case 6: 1080 if (val & 0xffffffff00000000ULL) 1081 return -1; /* #GP */ 1082 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1083 kvm_update_dr6(vcpu); 1084 break; 1085 case 5: 1086 /* fall through */ 1087 default: /* 7 */ 1088 if (!kvm_dr7_valid(val)) 1089 return -1; /* #GP */ 1090 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1091 kvm_update_dr7(vcpu); 1092 break; 1093 } 1094 1095 return 0; 1096 } 1097 1098 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1099 { 1100 if (__kvm_set_dr(vcpu, dr, val)) { 1101 kvm_inject_gp(vcpu, 0); 1102 return 1; 1103 } 1104 return 0; 1105 } 1106 EXPORT_SYMBOL_GPL(kvm_set_dr); 1107 1108 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1109 { 1110 size_t size = ARRAY_SIZE(vcpu->arch.db); 1111 1112 switch (dr) { 1113 case 0 ... 3: 1114 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1115 break; 1116 case 4: 1117 /* fall through */ 1118 case 6: 1119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1120 *val = vcpu->arch.dr6; 1121 else 1122 *val = kvm_x86_ops->get_dr6(vcpu); 1123 break; 1124 case 5: 1125 /* fall through */ 1126 default: /* 7 */ 1127 *val = vcpu->arch.dr7; 1128 break; 1129 } 1130 return 0; 1131 } 1132 EXPORT_SYMBOL_GPL(kvm_get_dr); 1133 1134 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1135 { 1136 u32 ecx = kvm_rcx_read(vcpu); 1137 u64 data; 1138 int err; 1139 1140 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1141 if (err) 1142 return err; 1143 kvm_rax_write(vcpu, (u32)data); 1144 kvm_rdx_write(vcpu, data >> 32); 1145 return err; 1146 } 1147 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1148 1149 /* 1150 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1151 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1152 * 1153 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1154 * extract the supported MSRs from the related const lists. 1155 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1156 * capabilities of the host cpu. This capabilities test skips MSRs that are 1157 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1158 * may depend on host virtualization features rather than host cpu features. 1159 */ 1160 1161 static const u32 msrs_to_save_all[] = { 1162 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1163 MSR_STAR, 1164 #ifdef CONFIG_X86_64 1165 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1166 #endif 1167 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1168 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1169 MSR_IA32_SPEC_CTRL, 1170 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1171 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1172 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1173 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1174 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1175 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1176 MSR_IA32_UMWAIT_CONTROL, 1177 1178 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1179 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1180 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1181 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1182 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1183 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1184 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1185 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1186 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1187 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1188 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1189 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1190 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1191 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1192 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1193 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1194 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1195 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1196 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1197 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1198 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1199 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1200 }; 1201 1202 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1203 static unsigned num_msrs_to_save; 1204 1205 static const u32 emulated_msrs_all[] = { 1206 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1207 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1208 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1209 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1210 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1211 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1212 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1213 HV_X64_MSR_RESET, 1214 HV_X64_MSR_VP_INDEX, 1215 HV_X64_MSR_VP_RUNTIME, 1216 HV_X64_MSR_SCONTROL, 1217 HV_X64_MSR_STIMER0_CONFIG, 1218 HV_X64_MSR_VP_ASSIST_PAGE, 1219 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1220 HV_X64_MSR_TSC_EMULATION_STATUS, 1221 1222 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1223 MSR_KVM_PV_EOI_EN, 1224 1225 MSR_IA32_TSC_ADJUST, 1226 MSR_IA32_TSCDEADLINE, 1227 MSR_IA32_ARCH_CAPABILITIES, 1228 MSR_IA32_MISC_ENABLE, 1229 MSR_IA32_MCG_STATUS, 1230 MSR_IA32_MCG_CTL, 1231 MSR_IA32_MCG_EXT_CTL, 1232 MSR_IA32_SMBASE, 1233 MSR_SMI_COUNT, 1234 MSR_PLATFORM_INFO, 1235 MSR_MISC_FEATURES_ENABLES, 1236 MSR_AMD64_VIRT_SPEC_CTRL, 1237 MSR_IA32_POWER_CTL, 1238 MSR_IA32_UCODE_REV, 1239 1240 /* 1241 * The following list leaves out MSRs whose values are determined 1242 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1243 * We always support the "true" VMX control MSRs, even if the host 1244 * processor does not, so I am putting these registers here rather 1245 * than in msrs_to_save_all. 1246 */ 1247 MSR_IA32_VMX_BASIC, 1248 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1249 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1250 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1251 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1252 MSR_IA32_VMX_MISC, 1253 MSR_IA32_VMX_CR0_FIXED0, 1254 MSR_IA32_VMX_CR4_FIXED0, 1255 MSR_IA32_VMX_VMCS_ENUM, 1256 MSR_IA32_VMX_PROCBASED_CTLS2, 1257 MSR_IA32_VMX_EPT_VPID_CAP, 1258 MSR_IA32_VMX_VMFUNC, 1259 1260 MSR_K7_HWCR, 1261 MSR_KVM_POLL_CONTROL, 1262 }; 1263 1264 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1265 static unsigned num_emulated_msrs; 1266 1267 /* 1268 * List of msr numbers which are used to expose MSR-based features that 1269 * can be used by a hypervisor to validate requested CPU features. 1270 */ 1271 static const u32 msr_based_features_all[] = { 1272 MSR_IA32_VMX_BASIC, 1273 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1274 MSR_IA32_VMX_PINBASED_CTLS, 1275 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1276 MSR_IA32_VMX_PROCBASED_CTLS, 1277 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1278 MSR_IA32_VMX_EXIT_CTLS, 1279 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1280 MSR_IA32_VMX_ENTRY_CTLS, 1281 MSR_IA32_VMX_MISC, 1282 MSR_IA32_VMX_CR0_FIXED0, 1283 MSR_IA32_VMX_CR0_FIXED1, 1284 MSR_IA32_VMX_CR4_FIXED0, 1285 MSR_IA32_VMX_CR4_FIXED1, 1286 MSR_IA32_VMX_VMCS_ENUM, 1287 MSR_IA32_VMX_PROCBASED_CTLS2, 1288 MSR_IA32_VMX_EPT_VPID_CAP, 1289 MSR_IA32_VMX_VMFUNC, 1290 1291 MSR_F10H_DECFG, 1292 MSR_IA32_UCODE_REV, 1293 MSR_IA32_ARCH_CAPABILITIES, 1294 }; 1295 1296 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1297 static unsigned int num_msr_based_features; 1298 1299 static u64 kvm_get_arch_capabilities(void) 1300 { 1301 u64 data = 0; 1302 1303 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1304 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1305 1306 /* 1307 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1308 * the nested hypervisor runs with NX huge pages. If it is not, 1309 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other 1310 * L1 guests, so it need not worry about its own (L2) guests. 1311 */ 1312 data |= ARCH_CAP_PSCHANGE_MC_NO; 1313 1314 /* 1315 * If we're doing cache flushes (either "always" or "cond") 1316 * we will do one whenever the guest does a vmlaunch/vmresume. 1317 * If an outer hypervisor is doing the cache flush for us 1318 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1319 * capability to the guest too, and if EPT is disabled we're not 1320 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1321 * require a nested hypervisor to do a flush of its own. 1322 */ 1323 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1324 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1325 1326 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1327 data |= ARCH_CAP_RDCL_NO; 1328 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1329 data |= ARCH_CAP_SSB_NO; 1330 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1331 data |= ARCH_CAP_MDS_NO; 1332 1333 /* 1334 * On TAA affected systems: 1335 * - nothing to do if TSX is disabled on the host. 1336 * - we emulate TSX_CTRL if present on the host. 1337 * This lets the guest use VERW to clear CPU buffers. 1338 */ 1339 if (!boot_cpu_has(X86_FEATURE_RTM)) 1340 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); 1341 else if (!boot_cpu_has_bug(X86_BUG_TAA)) 1342 data |= ARCH_CAP_TAA_NO; 1343 1344 return data; 1345 } 1346 1347 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1348 { 1349 switch (msr->index) { 1350 case MSR_IA32_ARCH_CAPABILITIES: 1351 msr->data = kvm_get_arch_capabilities(); 1352 break; 1353 case MSR_IA32_UCODE_REV: 1354 rdmsrl_safe(msr->index, &msr->data); 1355 break; 1356 default: 1357 if (kvm_x86_ops->get_msr_feature(msr)) 1358 return 1; 1359 } 1360 return 0; 1361 } 1362 1363 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1364 { 1365 struct kvm_msr_entry msr; 1366 int r; 1367 1368 msr.index = index; 1369 r = kvm_get_msr_feature(&msr); 1370 if (r) 1371 return r; 1372 1373 *data = msr.data; 1374 1375 return 0; 1376 } 1377 1378 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1379 { 1380 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1381 return false; 1382 1383 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1384 return false; 1385 1386 if (efer & (EFER_LME | EFER_LMA) && 1387 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1388 return false; 1389 1390 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1391 return false; 1392 1393 return true; 1394 1395 } 1396 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1397 { 1398 if (efer & efer_reserved_bits) 1399 return false; 1400 1401 return __kvm_valid_efer(vcpu, efer); 1402 } 1403 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1404 1405 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1406 { 1407 u64 old_efer = vcpu->arch.efer; 1408 u64 efer = msr_info->data; 1409 1410 if (efer & efer_reserved_bits) 1411 return 1; 1412 1413 if (!msr_info->host_initiated) { 1414 if (!__kvm_valid_efer(vcpu, efer)) 1415 return 1; 1416 1417 if (is_paging(vcpu) && 1418 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1419 return 1; 1420 } 1421 1422 efer &= ~EFER_LMA; 1423 efer |= vcpu->arch.efer & EFER_LMA; 1424 1425 kvm_x86_ops->set_efer(vcpu, efer); 1426 1427 /* Update reserved bits */ 1428 if ((efer ^ old_efer) & EFER_NX) 1429 kvm_mmu_reset_context(vcpu); 1430 1431 return 0; 1432 } 1433 1434 void kvm_enable_efer_bits(u64 mask) 1435 { 1436 efer_reserved_bits &= ~mask; 1437 } 1438 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1439 1440 /* 1441 * Write @data into the MSR specified by @index. Select MSR specific fault 1442 * checks are bypassed if @host_initiated is %true. 1443 * Returns 0 on success, non-0 otherwise. 1444 * Assumes vcpu_load() was already called. 1445 */ 1446 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1447 bool host_initiated) 1448 { 1449 struct msr_data msr; 1450 1451 switch (index) { 1452 case MSR_FS_BASE: 1453 case MSR_GS_BASE: 1454 case MSR_KERNEL_GS_BASE: 1455 case MSR_CSTAR: 1456 case MSR_LSTAR: 1457 if (is_noncanonical_address(data, vcpu)) 1458 return 1; 1459 break; 1460 case MSR_IA32_SYSENTER_EIP: 1461 case MSR_IA32_SYSENTER_ESP: 1462 /* 1463 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1464 * non-canonical address is written on Intel but not on 1465 * AMD (which ignores the top 32-bits, because it does 1466 * not implement 64-bit SYSENTER). 1467 * 1468 * 64-bit code should hence be able to write a non-canonical 1469 * value on AMD. Making the address canonical ensures that 1470 * vmentry does not fail on Intel after writing a non-canonical 1471 * value, and that something deterministic happens if the guest 1472 * invokes 64-bit SYSENTER. 1473 */ 1474 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1475 } 1476 1477 msr.data = data; 1478 msr.index = index; 1479 msr.host_initiated = host_initiated; 1480 1481 return kvm_x86_ops->set_msr(vcpu, &msr); 1482 } 1483 1484 /* 1485 * Read the MSR specified by @index into @data. Select MSR specific fault 1486 * checks are bypassed if @host_initiated is %true. 1487 * Returns 0 on success, non-0 otherwise. 1488 * Assumes vcpu_load() was already called. 1489 */ 1490 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1491 bool host_initiated) 1492 { 1493 struct msr_data msr; 1494 int ret; 1495 1496 msr.index = index; 1497 msr.host_initiated = host_initiated; 1498 1499 ret = kvm_x86_ops->get_msr(vcpu, &msr); 1500 if (!ret) 1501 *data = msr.data; 1502 return ret; 1503 } 1504 1505 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1506 { 1507 return __kvm_get_msr(vcpu, index, data, false); 1508 } 1509 EXPORT_SYMBOL_GPL(kvm_get_msr); 1510 1511 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1512 { 1513 return __kvm_set_msr(vcpu, index, data, false); 1514 } 1515 EXPORT_SYMBOL_GPL(kvm_set_msr); 1516 1517 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1518 { 1519 u32 ecx = kvm_rcx_read(vcpu); 1520 u64 data; 1521 1522 if (kvm_get_msr(vcpu, ecx, &data)) { 1523 trace_kvm_msr_read_ex(ecx); 1524 kvm_inject_gp(vcpu, 0); 1525 return 1; 1526 } 1527 1528 trace_kvm_msr_read(ecx, data); 1529 1530 kvm_rax_write(vcpu, data & -1u); 1531 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1532 return kvm_skip_emulated_instruction(vcpu); 1533 } 1534 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1535 1536 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1537 { 1538 u32 ecx = kvm_rcx_read(vcpu); 1539 u64 data = kvm_read_edx_eax(vcpu); 1540 1541 if (kvm_set_msr(vcpu, ecx, data)) { 1542 trace_kvm_msr_write_ex(ecx, data); 1543 kvm_inject_gp(vcpu, 0); 1544 return 1; 1545 } 1546 1547 trace_kvm_msr_write(ecx, data); 1548 return kvm_skip_emulated_instruction(vcpu); 1549 } 1550 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1551 1552 /* 1553 * The fast path for frequent and performance sensitive wrmsr emulation, 1554 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1555 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1556 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1557 * other cases which must be called after interrupts are enabled on the host. 1558 */ 1559 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1560 { 1561 if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) && 1562 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1563 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) { 1564 1565 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1566 return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data); 1567 } 1568 1569 return 1; 1570 } 1571 1572 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1573 { 1574 u32 msr = kvm_rcx_read(vcpu); 1575 u64 data = kvm_read_edx_eax(vcpu); 1576 int ret = 0; 1577 1578 switch (msr) { 1579 case APIC_BASE_MSR + (APIC_ICR >> 4): 1580 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data); 1581 break; 1582 default: 1583 return EXIT_FASTPATH_NONE; 1584 } 1585 1586 if (!ret) { 1587 trace_kvm_msr_write(msr, data); 1588 return EXIT_FASTPATH_SKIP_EMUL_INS; 1589 } 1590 1591 return EXIT_FASTPATH_NONE; 1592 } 1593 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 1594 1595 /* 1596 * Adapt set_msr() to msr_io()'s calling convention 1597 */ 1598 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1599 { 1600 return __kvm_get_msr(vcpu, index, data, true); 1601 } 1602 1603 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1604 { 1605 return __kvm_set_msr(vcpu, index, *data, true); 1606 } 1607 1608 #ifdef CONFIG_X86_64 1609 struct pvclock_clock { 1610 int vclock_mode; 1611 u64 cycle_last; 1612 u64 mask; 1613 u32 mult; 1614 u32 shift; 1615 u64 base_cycles; 1616 u64 offset; 1617 }; 1618 1619 struct pvclock_gtod_data { 1620 seqcount_t seq; 1621 1622 struct pvclock_clock clock; /* extract of a clocksource struct */ 1623 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 1624 1625 ktime_t offs_boot; 1626 u64 wall_time_sec; 1627 }; 1628 1629 static struct pvclock_gtod_data pvclock_gtod_data; 1630 1631 static void update_pvclock_gtod(struct timekeeper *tk) 1632 { 1633 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1634 1635 write_seqcount_begin(&vdata->seq); 1636 1637 /* copy pvclock gtod data */ 1638 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1639 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1640 vdata->clock.mask = tk->tkr_mono.mask; 1641 vdata->clock.mult = tk->tkr_mono.mult; 1642 vdata->clock.shift = tk->tkr_mono.shift; 1643 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 1644 vdata->clock.offset = tk->tkr_mono.base; 1645 1646 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode; 1647 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 1648 vdata->raw_clock.mask = tk->tkr_raw.mask; 1649 vdata->raw_clock.mult = tk->tkr_raw.mult; 1650 vdata->raw_clock.shift = tk->tkr_raw.shift; 1651 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 1652 vdata->raw_clock.offset = tk->tkr_raw.base; 1653 1654 vdata->wall_time_sec = tk->xtime_sec; 1655 1656 vdata->offs_boot = tk->offs_boot; 1657 1658 write_seqcount_end(&vdata->seq); 1659 } 1660 1661 static s64 get_kvmclock_base_ns(void) 1662 { 1663 /* Count up from boot time, but with the frequency of the raw clock. */ 1664 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 1665 } 1666 #else 1667 static s64 get_kvmclock_base_ns(void) 1668 { 1669 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 1670 return ktime_get_boottime_ns(); 1671 } 1672 #endif 1673 1674 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1675 { 1676 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1677 kvm_vcpu_kick(vcpu); 1678 } 1679 1680 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1681 { 1682 int version; 1683 int r; 1684 struct pvclock_wall_clock wc; 1685 u64 wall_nsec; 1686 1687 if (!wall_clock) 1688 return; 1689 1690 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1691 if (r) 1692 return; 1693 1694 if (version & 1) 1695 ++version; /* first time write, random junk */ 1696 1697 ++version; 1698 1699 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1700 return; 1701 1702 /* 1703 * The guest calculates current wall clock time by adding 1704 * system time (updated by kvm_guest_time_update below) to the 1705 * wall clock specified here. We do the reverse here. 1706 */ 1707 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 1708 1709 wc.nsec = do_div(wall_nsec, 1000000000); 1710 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 1711 wc.version = version; 1712 1713 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1714 1715 version++; 1716 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1717 } 1718 1719 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1720 { 1721 do_shl32_div32(dividend, divisor); 1722 return dividend; 1723 } 1724 1725 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1726 s8 *pshift, u32 *pmultiplier) 1727 { 1728 uint64_t scaled64; 1729 int32_t shift = 0; 1730 uint64_t tps64; 1731 uint32_t tps32; 1732 1733 tps64 = base_hz; 1734 scaled64 = scaled_hz; 1735 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1736 tps64 >>= 1; 1737 shift--; 1738 } 1739 1740 tps32 = (uint32_t)tps64; 1741 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1742 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1743 scaled64 >>= 1; 1744 else 1745 tps32 <<= 1; 1746 shift++; 1747 } 1748 1749 *pshift = shift; 1750 *pmultiplier = div_frac(scaled64, tps32); 1751 } 1752 1753 #ifdef CONFIG_X86_64 1754 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1755 #endif 1756 1757 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1758 static unsigned long max_tsc_khz; 1759 1760 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1761 { 1762 u64 v = (u64)khz * (1000000 + ppm); 1763 do_div(v, 1000000); 1764 return v; 1765 } 1766 1767 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1768 { 1769 u64 ratio; 1770 1771 /* Guest TSC same frequency as host TSC? */ 1772 if (!scale) { 1773 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1774 return 0; 1775 } 1776 1777 /* TSC scaling supported? */ 1778 if (!kvm_has_tsc_control) { 1779 if (user_tsc_khz > tsc_khz) { 1780 vcpu->arch.tsc_catchup = 1; 1781 vcpu->arch.tsc_always_catchup = 1; 1782 return 0; 1783 } else { 1784 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 1785 return -1; 1786 } 1787 } 1788 1789 /* TSC scaling required - calculate ratio */ 1790 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1791 user_tsc_khz, tsc_khz); 1792 1793 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1794 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1795 user_tsc_khz); 1796 return -1; 1797 } 1798 1799 vcpu->arch.tsc_scaling_ratio = ratio; 1800 return 0; 1801 } 1802 1803 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1804 { 1805 u32 thresh_lo, thresh_hi; 1806 int use_scaling = 0; 1807 1808 /* tsc_khz can be zero if TSC calibration fails */ 1809 if (user_tsc_khz == 0) { 1810 /* set tsc_scaling_ratio to a safe value */ 1811 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1812 return -1; 1813 } 1814 1815 /* Compute a scale to convert nanoseconds in TSC cycles */ 1816 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1817 &vcpu->arch.virtual_tsc_shift, 1818 &vcpu->arch.virtual_tsc_mult); 1819 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1820 1821 /* 1822 * Compute the variation in TSC rate which is acceptable 1823 * within the range of tolerance and decide if the 1824 * rate being applied is within that bounds of the hardware 1825 * rate. If so, no scaling or compensation need be done. 1826 */ 1827 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1828 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1829 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1830 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1831 use_scaling = 1; 1832 } 1833 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1834 } 1835 1836 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1837 { 1838 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1839 vcpu->arch.virtual_tsc_mult, 1840 vcpu->arch.virtual_tsc_shift); 1841 tsc += vcpu->arch.this_tsc_write; 1842 return tsc; 1843 } 1844 1845 static inline int gtod_is_based_on_tsc(int mode) 1846 { 1847 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; 1848 } 1849 1850 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1851 { 1852 #ifdef CONFIG_X86_64 1853 bool vcpus_matched; 1854 struct kvm_arch *ka = &vcpu->kvm->arch; 1855 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1856 1857 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1858 atomic_read(&vcpu->kvm->online_vcpus)); 1859 1860 /* 1861 * Once the masterclock is enabled, always perform request in 1862 * order to update it. 1863 * 1864 * In order to enable masterclock, the host clocksource must be TSC 1865 * and the vcpus need to have matched TSCs. When that happens, 1866 * perform request to enable masterclock. 1867 */ 1868 if (ka->use_master_clock || 1869 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1870 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1871 1872 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1873 atomic_read(&vcpu->kvm->online_vcpus), 1874 ka->use_master_clock, gtod->clock.vclock_mode); 1875 #endif 1876 } 1877 1878 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1879 { 1880 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1881 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1882 } 1883 1884 /* 1885 * Multiply tsc by a fixed point number represented by ratio. 1886 * 1887 * The most significant 64-N bits (mult) of ratio represent the 1888 * integral part of the fixed point number; the remaining N bits 1889 * (frac) represent the fractional part, ie. ratio represents a fixed 1890 * point number (mult + frac * 2^(-N)). 1891 * 1892 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1893 */ 1894 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1895 { 1896 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1897 } 1898 1899 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1900 { 1901 u64 _tsc = tsc; 1902 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1903 1904 if (ratio != kvm_default_tsc_scaling_ratio) 1905 _tsc = __scale_tsc(ratio, tsc); 1906 1907 return _tsc; 1908 } 1909 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1910 1911 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1912 { 1913 u64 tsc; 1914 1915 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1916 1917 return target_tsc - tsc; 1918 } 1919 1920 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1921 { 1922 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1923 1924 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1925 } 1926 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1927 1928 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1929 { 1930 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset); 1931 } 1932 1933 static inline bool kvm_check_tsc_unstable(void) 1934 { 1935 #ifdef CONFIG_X86_64 1936 /* 1937 * TSC is marked unstable when we're running on Hyper-V, 1938 * 'TSC page' clocksource is good. 1939 */ 1940 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) 1941 return false; 1942 #endif 1943 return check_tsc_unstable(); 1944 } 1945 1946 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1947 { 1948 struct kvm *kvm = vcpu->kvm; 1949 u64 offset, ns, elapsed; 1950 unsigned long flags; 1951 bool matched; 1952 bool already_matched; 1953 u64 data = msr->data; 1954 bool synchronizing = false; 1955 1956 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1957 offset = kvm_compute_tsc_offset(vcpu, data); 1958 ns = get_kvmclock_base_ns(); 1959 elapsed = ns - kvm->arch.last_tsc_nsec; 1960 1961 if (vcpu->arch.virtual_tsc_khz) { 1962 if (data == 0 && msr->host_initiated) { 1963 /* 1964 * detection of vcpu initialization -- need to sync 1965 * with other vCPUs. This particularly helps to keep 1966 * kvm_clock stable after CPU hotplug 1967 */ 1968 synchronizing = true; 1969 } else { 1970 u64 tsc_exp = kvm->arch.last_tsc_write + 1971 nsec_to_cycles(vcpu, elapsed); 1972 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1973 /* 1974 * Special case: TSC write with a small delta (1 second) 1975 * of virtual cycle time against real time is 1976 * interpreted as an attempt to synchronize the CPU. 1977 */ 1978 synchronizing = data < tsc_exp + tsc_hz && 1979 data + tsc_hz > tsc_exp; 1980 } 1981 } 1982 1983 /* 1984 * For a reliable TSC, we can match TSC offsets, and for an unstable 1985 * TSC, we add elapsed time in this computation. We could let the 1986 * compensation code attempt to catch up if we fall behind, but 1987 * it's better to try to match offsets from the beginning. 1988 */ 1989 if (synchronizing && 1990 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1991 if (!kvm_check_tsc_unstable()) { 1992 offset = kvm->arch.cur_tsc_offset; 1993 } else { 1994 u64 delta = nsec_to_cycles(vcpu, elapsed); 1995 data += delta; 1996 offset = kvm_compute_tsc_offset(vcpu, data); 1997 } 1998 matched = true; 1999 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2000 } else { 2001 /* 2002 * We split periods of matched TSC writes into generations. 2003 * For each generation, we track the original measured 2004 * nanosecond time, offset, and write, so if TSCs are in 2005 * sync, we can match exact offset, and if not, we can match 2006 * exact software computation in compute_guest_tsc() 2007 * 2008 * These values are tracked in kvm->arch.cur_xxx variables. 2009 */ 2010 kvm->arch.cur_tsc_generation++; 2011 kvm->arch.cur_tsc_nsec = ns; 2012 kvm->arch.cur_tsc_write = data; 2013 kvm->arch.cur_tsc_offset = offset; 2014 matched = false; 2015 } 2016 2017 /* 2018 * We also track th most recent recorded KHZ, write and time to 2019 * allow the matching interval to be extended at each write. 2020 */ 2021 kvm->arch.last_tsc_nsec = ns; 2022 kvm->arch.last_tsc_write = data; 2023 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2024 2025 vcpu->arch.last_guest_tsc = data; 2026 2027 /* Keep track of which generation this VCPU has synchronized to */ 2028 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2029 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2030 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2031 2032 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 2033 update_ia32_tsc_adjust_msr(vcpu, offset); 2034 2035 kvm_vcpu_write_tsc_offset(vcpu, offset); 2036 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2037 2038 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 2039 if (!matched) { 2040 kvm->arch.nr_vcpus_matched_tsc = 0; 2041 } else if (!already_matched) { 2042 kvm->arch.nr_vcpus_matched_tsc++; 2043 } 2044 2045 kvm_track_tsc_matching(vcpu); 2046 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 2047 } 2048 2049 EXPORT_SYMBOL_GPL(kvm_write_tsc); 2050 2051 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2052 s64 adjustment) 2053 { 2054 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 2055 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2056 } 2057 2058 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2059 { 2060 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2061 WARN_ON(adjustment < 0); 2062 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 2063 adjust_tsc_offset_guest(vcpu, adjustment); 2064 } 2065 2066 #ifdef CONFIG_X86_64 2067 2068 static u64 read_tsc(void) 2069 { 2070 u64 ret = (u64)rdtsc_ordered(); 2071 u64 last = pvclock_gtod_data.clock.cycle_last; 2072 2073 if (likely(ret >= last)) 2074 return ret; 2075 2076 /* 2077 * GCC likes to generate cmov here, but this branch is extremely 2078 * predictable (it's just a function of time and the likely is 2079 * very likely) and there's a data dependence, so force GCC 2080 * to generate a branch instead. I don't barrier() because 2081 * we don't actually need a barrier, and if this function 2082 * ever gets inlined it will generate worse code. 2083 */ 2084 asm volatile (""); 2085 return last; 2086 } 2087 2088 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2089 int *mode) 2090 { 2091 long v; 2092 u64 tsc_pg_val; 2093 2094 switch (clock->vclock_mode) { 2095 case VCLOCK_HVCLOCK: 2096 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2097 tsc_timestamp); 2098 if (tsc_pg_val != U64_MAX) { 2099 /* TSC page valid */ 2100 *mode = VCLOCK_HVCLOCK; 2101 v = (tsc_pg_val - clock->cycle_last) & 2102 clock->mask; 2103 } else { 2104 /* TSC page invalid */ 2105 *mode = VCLOCK_NONE; 2106 } 2107 break; 2108 case VCLOCK_TSC: 2109 *mode = VCLOCK_TSC; 2110 *tsc_timestamp = read_tsc(); 2111 v = (*tsc_timestamp - clock->cycle_last) & 2112 clock->mask; 2113 break; 2114 default: 2115 *mode = VCLOCK_NONE; 2116 } 2117 2118 if (*mode == VCLOCK_NONE) 2119 *tsc_timestamp = v = 0; 2120 2121 return v * clock->mult; 2122 } 2123 2124 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2125 { 2126 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2127 unsigned long seq; 2128 int mode; 2129 u64 ns; 2130 2131 do { 2132 seq = read_seqcount_begin(>od->seq); 2133 ns = gtod->raw_clock.base_cycles; 2134 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2135 ns >>= gtod->raw_clock.shift; 2136 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2137 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2138 *t = ns; 2139 2140 return mode; 2141 } 2142 2143 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2144 { 2145 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2146 unsigned long seq; 2147 int mode; 2148 u64 ns; 2149 2150 do { 2151 seq = read_seqcount_begin(>od->seq); 2152 ts->tv_sec = gtod->wall_time_sec; 2153 ns = gtod->clock.base_cycles; 2154 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2155 ns >>= gtod->clock.shift; 2156 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2157 2158 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2159 ts->tv_nsec = ns; 2160 2161 return mode; 2162 } 2163 2164 /* returns true if host is using TSC based clocksource */ 2165 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2166 { 2167 /* checked again under seqlock below */ 2168 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2169 return false; 2170 2171 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2172 tsc_timestamp)); 2173 } 2174 2175 /* returns true if host is using TSC based clocksource */ 2176 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2177 u64 *tsc_timestamp) 2178 { 2179 /* checked again under seqlock below */ 2180 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2181 return false; 2182 2183 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2184 } 2185 #endif 2186 2187 /* 2188 * 2189 * Assuming a stable TSC across physical CPUS, and a stable TSC 2190 * across virtual CPUs, the following condition is possible. 2191 * Each numbered line represents an event visible to both 2192 * CPUs at the next numbered event. 2193 * 2194 * "timespecX" represents host monotonic time. "tscX" represents 2195 * RDTSC value. 2196 * 2197 * VCPU0 on CPU0 | VCPU1 on CPU1 2198 * 2199 * 1. read timespec0,tsc0 2200 * 2. | timespec1 = timespec0 + N 2201 * | tsc1 = tsc0 + M 2202 * 3. transition to guest | transition to guest 2203 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2204 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2205 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2206 * 2207 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2208 * 2209 * - ret0 < ret1 2210 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2211 * ... 2212 * - 0 < N - M => M < N 2213 * 2214 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2215 * always the case (the difference between two distinct xtime instances 2216 * might be smaller then the difference between corresponding TSC reads, 2217 * when updating guest vcpus pvclock areas). 2218 * 2219 * To avoid that problem, do not allow visibility of distinct 2220 * system_timestamp/tsc_timestamp values simultaneously: use a master 2221 * copy of host monotonic time values. Update that master copy 2222 * in lockstep. 2223 * 2224 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2225 * 2226 */ 2227 2228 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2229 { 2230 #ifdef CONFIG_X86_64 2231 struct kvm_arch *ka = &kvm->arch; 2232 int vclock_mode; 2233 bool host_tsc_clocksource, vcpus_matched; 2234 2235 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2236 atomic_read(&kvm->online_vcpus)); 2237 2238 /* 2239 * If the host uses TSC clock, then passthrough TSC as stable 2240 * to the guest. 2241 */ 2242 host_tsc_clocksource = kvm_get_time_and_clockread( 2243 &ka->master_kernel_ns, 2244 &ka->master_cycle_now); 2245 2246 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2247 && !ka->backwards_tsc_observed 2248 && !ka->boot_vcpu_runs_old_kvmclock; 2249 2250 if (ka->use_master_clock) 2251 atomic_set(&kvm_guest_has_master_clock, 1); 2252 2253 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2254 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2255 vcpus_matched); 2256 #endif 2257 } 2258 2259 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2260 { 2261 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2262 } 2263 2264 static void kvm_gen_update_masterclock(struct kvm *kvm) 2265 { 2266 #ifdef CONFIG_X86_64 2267 int i; 2268 struct kvm_vcpu *vcpu; 2269 struct kvm_arch *ka = &kvm->arch; 2270 2271 spin_lock(&ka->pvclock_gtod_sync_lock); 2272 kvm_make_mclock_inprogress_request(kvm); 2273 /* no guest entries from this point */ 2274 pvclock_update_vm_gtod_copy(kvm); 2275 2276 kvm_for_each_vcpu(i, vcpu, kvm) 2277 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2278 2279 /* guest entries allowed */ 2280 kvm_for_each_vcpu(i, vcpu, kvm) 2281 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2282 2283 spin_unlock(&ka->pvclock_gtod_sync_lock); 2284 #endif 2285 } 2286 2287 u64 get_kvmclock_ns(struct kvm *kvm) 2288 { 2289 struct kvm_arch *ka = &kvm->arch; 2290 struct pvclock_vcpu_time_info hv_clock; 2291 u64 ret; 2292 2293 spin_lock(&ka->pvclock_gtod_sync_lock); 2294 if (!ka->use_master_clock) { 2295 spin_unlock(&ka->pvclock_gtod_sync_lock); 2296 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2297 } 2298 2299 hv_clock.tsc_timestamp = ka->master_cycle_now; 2300 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2301 spin_unlock(&ka->pvclock_gtod_sync_lock); 2302 2303 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2304 get_cpu(); 2305 2306 if (__this_cpu_read(cpu_tsc_khz)) { 2307 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2308 &hv_clock.tsc_shift, 2309 &hv_clock.tsc_to_system_mul); 2310 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2311 } else 2312 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2313 2314 put_cpu(); 2315 2316 return ret; 2317 } 2318 2319 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 2320 { 2321 struct kvm_vcpu_arch *vcpu = &v->arch; 2322 struct pvclock_vcpu_time_info guest_hv_clock; 2323 2324 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 2325 &guest_hv_clock, sizeof(guest_hv_clock)))) 2326 return; 2327 2328 /* This VCPU is paused, but it's legal for a guest to read another 2329 * VCPU's kvmclock, so we really have to follow the specification where 2330 * it says that version is odd if data is being modified, and even after 2331 * it is consistent. 2332 * 2333 * Version field updates must be kept separate. This is because 2334 * kvm_write_guest_cached might use a "rep movs" instruction, and 2335 * writes within a string instruction are weakly ordered. So there 2336 * are three writes overall. 2337 * 2338 * As a small optimization, only write the version field in the first 2339 * and third write. The vcpu->pv_time cache is still valid, because the 2340 * version field is the first in the struct. 2341 */ 2342 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2343 2344 if (guest_hv_clock.version & 1) 2345 ++guest_hv_clock.version; /* first time write, random junk */ 2346 2347 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2348 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2349 &vcpu->hv_clock, 2350 sizeof(vcpu->hv_clock.version)); 2351 2352 smp_wmb(); 2353 2354 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2355 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2356 2357 if (vcpu->pvclock_set_guest_stopped_request) { 2358 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2359 vcpu->pvclock_set_guest_stopped_request = false; 2360 } 2361 2362 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2363 2364 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2365 &vcpu->hv_clock, 2366 sizeof(vcpu->hv_clock)); 2367 2368 smp_wmb(); 2369 2370 vcpu->hv_clock.version++; 2371 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2372 &vcpu->hv_clock, 2373 sizeof(vcpu->hv_clock.version)); 2374 } 2375 2376 static int kvm_guest_time_update(struct kvm_vcpu *v) 2377 { 2378 unsigned long flags, tgt_tsc_khz; 2379 struct kvm_vcpu_arch *vcpu = &v->arch; 2380 struct kvm_arch *ka = &v->kvm->arch; 2381 s64 kernel_ns; 2382 u64 tsc_timestamp, host_tsc; 2383 u8 pvclock_flags; 2384 bool use_master_clock; 2385 2386 kernel_ns = 0; 2387 host_tsc = 0; 2388 2389 /* 2390 * If the host uses TSC clock, then passthrough TSC as stable 2391 * to the guest. 2392 */ 2393 spin_lock(&ka->pvclock_gtod_sync_lock); 2394 use_master_clock = ka->use_master_clock; 2395 if (use_master_clock) { 2396 host_tsc = ka->master_cycle_now; 2397 kernel_ns = ka->master_kernel_ns; 2398 } 2399 spin_unlock(&ka->pvclock_gtod_sync_lock); 2400 2401 /* Keep irq disabled to prevent changes to the clock */ 2402 local_irq_save(flags); 2403 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2404 if (unlikely(tgt_tsc_khz == 0)) { 2405 local_irq_restore(flags); 2406 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2407 return 1; 2408 } 2409 if (!use_master_clock) { 2410 host_tsc = rdtsc(); 2411 kernel_ns = get_kvmclock_base_ns(); 2412 } 2413 2414 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2415 2416 /* 2417 * We may have to catch up the TSC to match elapsed wall clock 2418 * time for two reasons, even if kvmclock is used. 2419 * 1) CPU could have been running below the maximum TSC rate 2420 * 2) Broken TSC compensation resets the base at each VCPU 2421 * entry to avoid unknown leaps of TSC even when running 2422 * again on the same CPU. This may cause apparent elapsed 2423 * time to disappear, and the guest to stand still or run 2424 * very slowly. 2425 */ 2426 if (vcpu->tsc_catchup) { 2427 u64 tsc = compute_guest_tsc(v, kernel_ns); 2428 if (tsc > tsc_timestamp) { 2429 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2430 tsc_timestamp = tsc; 2431 } 2432 } 2433 2434 local_irq_restore(flags); 2435 2436 /* With all the info we got, fill in the values */ 2437 2438 if (kvm_has_tsc_control) 2439 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2440 2441 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2442 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2443 &vcpu->hv_clock.tsc_shift, 2444 &vcpu->hv_clock.tsc_to_system_mul); 2445 vcpu->hw_tsc_khz = tgt_tsc_khz; 2446 } 2447 2448 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2449 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2450 vcpu->last_guest_tsc = tsc_timestamp; 2451 WARN_ON(vcpu->hv_clock.system_time < 0); 2452 2453 /* If the host uses TSC clocksource, then it is stable */ 2454 pvclock_flags = 0; 2455 if (use_master_clock) 2456 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2457 2458 vcpu->hv_clock.flags = pvclock_flags; 2459 2460 if (vcpu->pv_time_enabled) 2461 kvm_setup_pvclock_page(v); 2462 if (v == kvm_get_vcpu(v->kvm, 0)) 2463 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2464 return 0; 2465 } 2466 2467 /* 2468 * kvmclock updates which are isolated to a given vcpu, such as 2469 * vcpu->cpu migration, should not allow system_timestamp from 2470 * the rest of the vcpus to remain static. Otherwise ntp frequency 2471 * correction applies to one vcpu's system_timestamp but not 2472 * the others. 2473 * 2474 * So in those cases, request a kvmclock update for all vcpus. 2475 * We need to rate-limit these requests though, as they can 2476 * considerably slow guests that have a large number of vcpus. 2477 * The time for a remote vcpu to update its kvmclock is bound 2478 * by the delay we use to rate-limit the updates. 2479 */ 2480 2481 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2482 2483 static void kvmclock_update_fn(struct work_struct *work) 2484 { 2485 int i; 2486 struct delayed_work *dwork = to_delayed_work(work); 2487 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2488 kvmclock_update_work); 2489 struct kvm *kvm = container_of(ka, struct kvm, arch); 2490 struct kvm_vcpu *vcpu; 2491 2492 kvm_for_each_vcpu(i, vcpu, kvm) { 2493 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2494 kvm_vcpu_kick(vcpu); 2495 } 2496 } 2497 2498 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2499 { 2500 struct kvm *kvm = v->kvm; 2501 2502 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2503 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2504 KVMCLOCK_UPDATE_DELAY); 2505 } 2506 2507 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2508 2509 static void kvmclock_sync_fn(struct work_struct *work) 2510 { 2511 struct delayed_work *dwork = to_delayed_work(work); 2512 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2513 kvmclock_sync_work); 2514 struct kvm *kvm = container_of(ka, struct kvm, arch); 2515 2516 if (!kvmclock_periodic_sync) 2517 return; 2518 2519 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2520 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2521 KVMCLOCK_SYNC_PERIOD); 2522 } 2523 2524 /* 2525 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2526 */ 2527 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2528 { 2529 /* McStatusWrEn enabled? */ 2530 if (guest_cpuid_is_amd(vcpu)) 2531 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2532 2533 return false; 2534 } 2535 2536 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2537 { 2538 u64 mcg_cap = vcpu->arch.mcg_cap; 2539 unsigned bank_num = mcg_cap & 0xff; 2540 u32 msr = msr_info->index; 2541 u64 data = msr_info->data; 2542 2543 switch (msr) { 2544 case MSR_IA32_MCG_STATUS: 2545 vcpu->arch.mcg_status = data; 2546 break; 2547 case MSR_IA32_MCG_CTL: 2548 if (!(mcg_cap & MCG_CTL_P) && 2549 (data || !msr_info->host_initiated)) 2550 return 1; 2551 if (data != 0 && data != ~(u64)0) 2552 return 1; 2553 vcpu->arch.mcg_ctl = data; 2554 break; 2555 default: 2556 if (msr >= MSR_IA32_MC0_CTL && 2557 msr < MSR_IA32_MCx_CTL(bank_num)) { 2558 u32 offset = array_index_nospec( 2559 msr - MSR_IA32_MC0_CTL, 2560 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 2561 2562 /* only 0 or all 1s can be written to IA32_MCi_CTL 2563 * some Linux kernels though clear bit 10 in bank 4 to 2564 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2565 * this to avoid an uncatched #GP in the guest 2566 */ 2567 if ((offset & 0x3) == 0 && 2568 data != 0 && (data | (1 << 10)) != ~(u64)0) 2569 return -1; 2570 2571 /* MCi_STATUS */ 2572 if (!msr_info->host_initiated && 2573 (offset & 0x3) == 1 && data != 0) { 2574 if (!can_set_mci_status(vcpu)) 2575 return -1; 2576 } 2577 2578 vcpu->arch.mce_banks[offset] = data; 2579 break; 2580 } 2581 return 1; 2582 } 2583 return 0; 2584 } 2585 2586 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2587 { 2588 struct kvm *kvm = vcpu->kvm; 2589 int lm = is_long_mode(vcpu); 2590 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2591 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2592 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2593 : kvm->arch.xen_hvm_config.blob_size_32; 2594 u32 page_num = data & ~PAGE_MASK; 2595 u64 page_addr = data & PAGE_MASK; 2596 u8 *page; 2597 int r; 2598 2599 r = -E2BIG; 2600 if (page_num >= blob_size) 2601 goto out; 2602 r = -ENOMEM; 2603 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2604 if (IS_ERR(page)) { 2605 r = PTR_ERR(page); 2606 goto out; 2607 } 2608 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2609 goto out_free; 2610 r = 0; 2611 out_free: 2612 kfree(page); 2613 out: 2614 return r; 2615 } 2616 2617 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2618 { 2619 gpa_t gpa = data & ~0x3f; 2620 2621 /* Bits 3:5 are reserved, Should be zero */ 2622 if (data & 0x38) 2623 return 1; 2624 2625 vcpu->arch.apf.msr_val = data; 2626 2627 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2628 kvm_clear_async_pf_completion_queue(vcpu); 2629 kvm_async_pf_hash_reset(vcpu); 2630 return 0; 2631 } 2632 2633 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2634 sizeof(u32))) 2635 return 1; 2636 2637 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2638 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2639 kvm_async_pf_wakeup_all(vcpu); 2640 return 0; 2641 } 2642 2643 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2644 { 2645 vcpu->arch.pv_time_enabled = false; 2646 vcpu->arch.time = 0; 2647 } 2648 2649 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2650 { 2651 ++vcpu->stat.tlb_flush; 2652 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); 2653 } 2654 2655 static void record_steal_time(struct kvm_vcpu *vcpu) 2656 { 2657 struct kvm_host_map map; 2658 struct kvm_steal_time *st; 2659 2660 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2661 return; 2662 2663 /* -EAGAIN is returned in atomic context so we can just return. */ 2664 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 2665 &map, &vcpu->arch.st.cache, false)) 2666 return; 2667 2668 st = map.hva + 2669 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 2670 2671 /* 2672 * Doing a TLB flush here, on the guest's behalf, can avoid 2673 * expensive IPIs. 2674 */ 2675 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 2676 st->preempted & KVM_VCPU_FLUSH_TLB); 2677 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) 2678 kvm_vcpu_flush_tlb(vcpu, false); 2679 2680 vcpu->arch.st.preempted = 0; 2681 2682 if (st->version & 1) 2683 st->version += 1; /* first time write, random junk */ 2684 2685 st->version += 1; 2686 2687 smp_wmb(); 2688 2689 st->steal += current->sched_info.run_delay - 2690 vcpu->arch.st.last_steal; 2691 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2692 2693 smp_wmb(); 2694 2695 st->version += 1; 2696 2697 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 2698 } 2699 2700 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2701 { 2702 bool pr = false; 2703 u32 msr = msr_info->index; 2704 u64 data = msr_info->data; 2705 2706 switch (msr) { 2707 case MSR_AMD64_NB_CFG: 2708 case MSR_IA32_UCODE_WRITE: 2709 case MSR_VM_HSAVE_PA: 2710 case MSR_AMD64_PATCH_LOADER: 2711 case MSR_AMD64_BU_CFG2: 2712 case MSR_AMD64_DC_CFG: 2713 case MSR_F15H_EX_CFG: 2714 break; 2715 2716 case MSR_IA32_UCODE_REV: 2717 if (msr_info->host_initiated) 2718 vcpu->arch.microcode_version = data; 2719 break; 2720 case MSR_IA32_ARCH_CAPABILITIES: 2721 if (!msr_info->host_initiated) 2722 return 1; 2723 vcpu->arch.arch_capabilities = data; 2724 break; 2725 case MSR_EFER: 2726 return set_efer(vcpu, msr_info); 2727 case MSR_K7_HWCR: 2728 data &= ~(u64)0x40; /* ignore flush filter disable */ 2729 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2730 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2731 2732 /* Handle McStatusWrEn */ 2733 if (data == BIT_ULL(18)) { 2734 vcpu->arch.msr_hwcr = data; 2735 } else if (data != 0) { 2736 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2737 data); 2738 return 1; 2739 } 2740 break; 2741 case MSR_FAM10H_MMIO_CONF_BASE: 2742 if (data != 0) { 2743 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2744 "0x%llx\n", data); 2745 return 1; 2746 } 2747 break; 2748 case MSR_IA32_DEBUGCTLMSR: 2749 if (!data) { 2750 /* We support the non-activated case already */ 2751 break; 2752 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2753 /* Values other than LBR and BTF are vendor-specific, 2754 thus reserved and should throw a #GP */ 2755 return 1; 2756 } 2757 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2758 __func__, data); 2759 break; 2760 case 0x200 ... 0x2ff: 2761 return kvm_mtrr_set_msr(vcpu, msr, data); 2762 case MSR_IA32_APICBASE: 2763 return kvm_set_apic_base(vcpu, msr_info); 2764 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2765 return kvm_x2apic_msr_write(vcpu, msr, data); 2766 case MSR_IA32_TSCDEADLINE: 2767 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2768 break; 2769 case MSR_IA32_TSC_ADJUST: 2770 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2771 if (!msr_info->host_initiated) { 2772 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2773 adjust_tsc_offset_guest(vcpu, adj); 2774 } 2775 vcpu->arch.ia32_tsc_adjust_msr = data; 2776 } 2777 break; 2778 case MSR_IA32_MISC_ENABLE: 2779 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 2780 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 2781 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 2782 return 1; 2783 vcpu->arch.ia32_misc_enable_msr = data; 2784 kvm_update_cpuid(vcpu); 2785 } else { 2786 vcpu->arch.ia32_misc_enable_msr = data; 2787 } 2788 break; 2789 case MSR_IA32_SMBASE: 2790 if (!msr_info->host_initiated) 2791 return 1; 2792 vcpu->arch.smbase = data; 2793 break; 2794 case MSR_IA32_POWER_CTL: 2795 vcpu->arch.msr_ia32_power_ctl = data; 2796 break; 2797 case MSR_IA32_TSC: 2798 kvm_write_tsc(vcpu, msr_info); 2799 break; 2800 case MSR_IA32_XSS: 2801 if (!msr_info->host_initiated && 2802 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 2803 return 1; 2804 /* 2805 * We do support PT if kvm_x86_ops->pt_supported(), but we do 2806 * not support IA32_XSS[bit 8]. Guests will have to use 2807 * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT 2808 * MSRs. 2809 */ 2810 if (data != 0) 2811 return 1; 2812 vcpu->arch.ia32_xss = data; 2813 break; 2814 case MSR_SMI_COUNT: 2815 if (!msr_info->host_initiated) 2816 return 1; 2817 vcpu->arch.smi_count = data; 2818 break; 2819 case MSR_KVM_WALL_CLOCK_NEW: 2820 case MSR_KVM_WALL_CLOCK: 2821 vcpu->kvm->arch.wall_clock = data; 2822 kvm_write_wall_clock(vcpu->kvm, data); 2823 break; 2824 case MSR_KVM_SYSTEM_TIME_NEW: 2825 case MSR_KVM_SYSTEM_TIME: { 2826 struct kvm_arch *ka = &vcpu->kvm->arch; 2827 2828 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2829 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2830 2831 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2832 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2833 2834 ka->boot_vcpu_runs_old_kvmclock = tmp; 2835 } 2836 2837 vcpu->arch.time = data; 2838 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2839 2840 /* we verify if the enable bit is set... */ 2841 vcpu->arch.pv_time_enabled = false; 2842 if (!(data & 1)) 2843 break; 2844 2845 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2846 &vcpu->arch.pv_time, data & ~1ULL, 2847 sizeof(struct pvclock_vcpu_time_info))) 2848 vcpu->arch.pv_time_enabled = true; 2849 2850 break; 2851 } 2852 case MSR_KVM_ASYNC_PF_EN: 2853 if (kvm_pv_enable_async_pf(vcpu, data)) 2854 return 1; 2855 break; 2856 case MSR_KVM_STEAL_TIME: 2857 2858 if (unlikely(!sched_info_on())) 2859 return 1; 2860 2861 if (data & KVM_STEAL_RESERVED_MASK) 2862 return 1; 2863 2864 vcpu->arch.st.msr_val = data; 2865 2866 if (!(data & KVM_MSR_ENABLED)) 2867 break; 2868 2869 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2870 2871 break; 2872 case MSR_KVM_PV_EOI_EN: 2873 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 2874 return 1; 2875 break; 2876 2877 case MSR_KVM_POLL_CONTROL: 2878 /* only enable bit supported */ 2879 if (data & (-1ULL << 1)) 2880 return 1; 2881 2882 vcpu->arch.msr_kvm_poll_control = data; 2883 break; 2884 2885 case MSR_IA32_MCG_CTL: 2886 case MSR_IA32_MCG_STATUS: 2887 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2888 return set_msr_mce(vcpu, msr_info); 2889 2890 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2891 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2892 pr = true; /* fall through */ 2893 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2894 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2895 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2896 return kvm_pmu_set_msr(vcpu, msr_info); 2897 2898 if (pr || data != 0) 2899 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2900 "0x%x data 0x%llx\n", msr, data); 2901 break; 2902 case MSR_K7_CLK_CTL: 2903 /* 2904 * Ignore all writes to this no longer documented MSR. 2905 * Writes are only relevant for old K7 processors, 2906 * all pre-dating SVM, but a recommended workaround from 2907 * AMD for these chips. It is possible to specify the 2908 * affected processor models on the command line, hence 2909 * the need to ignore the workaround. 2910 */ 2911 break; 2912 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2913 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2914 case HV_X64_MSR_CRASH_CTL: 2915 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2916 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2917 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2918 case HV_X64_MSR_TSC_EMULATION_STATUS: 2919 return kvm_hv_set_msr_common(vcpu, msr, data, 2920 msr_info->host_initiated); 2921 case MSR_IA32_BBL_CR_CTL3: 2922 /* Drop writes to this legacy MSR -- see rdmsr 2923 * counterpart for further detail. 2924 */ 2925 if (report_ignored_msrs) 2926 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2927 msr, data); 2928 break; 2929 case MSR_AMD64_OSVW_ID_LENGTH: 2930 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2931 return 1; 2932 vcpu->arch.osvw.length = data; 2933 break; 2934 case MSR_AMD64_OSVW_STATUS: 2935 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2936 return 1; 2937 vcpu->arch.osvw.status = data; 2938 break; 2939 case MSR_PLATFORM_INFO: 2940 if (!msr_info->host_initiated || 2941 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2942 cpuid_fault_enabled(vcpu))) 2943 return 1; 2944 vcpu->arch.msr_platform_info = data; 2945 break; 2946 case MSR_MISC_FEATURES_ENABLES: 2947 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2948 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2949 !supports_cpuid_fault(vcpu))) 2950 return 1; 2951 vcpu->arch.msr_misc_features_enables = data; 2952 break; 2953 default: 2954 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2955 return xen_hvm_config(vcpu, data); 2956 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2957 return kvm_pmu_set_msr(vcpu, msr_info); 2958 if (!ignore_msrs) { 2959 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2960 msr, data); 2961 return 1; 2962 } else { 2963 if (report_ignored_msrs) 2964 vcpu_unimpl(vcpu, 2965 "ignored wrmsr: 0x%x data 0x%llx\n", 2966 msr, data); 2967 break; 2968 } 2969 } 2970 return 0; 2971 } 2972 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2973 2974 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 2975 { 2976 u64 data; 2977 u64 mcg_cap = vcpu->arch.mcg_cap; 2978 unsigned bank_num = mcg_cap & 0xff; 2979 2980 switch (msr) { 2981 case MSR_IA32_P5_MC_ADDR: 2982 case MSR_IA32_P5_MC_TYPE: 2983 data = 0; 2984 break; 2985 case MSR_IA32_MCG_CAP: 2986 data = vcpu->arch.mcg_cap; 2987 break; 2988 case MSR_IA32_MCG_CTL: 2989 if (!(mcg_cap & MCG_CTL_P) && !host) 2990 return 1; 2991 data = vcpu->arch.mcg_ctl; 2992 break; 2993 case MSR_IA32_MCG_STATUS: 2994 data = vcpu->arch.mcg_status; 2995 break; 2996 default: 2997 if (msr >= MSR_IA32_MC0_CTL && 2998 msr < MSR_IA32_MCx_CTL(bank_num)) { 2999 u32 offset = array_index_nospec( 3000 msr - MSR_IA32_MC0_CTL, 3001 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3002 3003 data = vcpu->arch.mce_banks[offset]; 3004 break; 3005 } 3006 return 1; 3007 } 3008 *pdata = data; 3009 return 0; 3010 } 3011 3012 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3013 { 3014 switch (msr_info->index) { 3015 case MSR_IA32_PLATFORM_ID: 3016 case MSR_IA32_EBL_CR_POWERON: 3017 case MSR_IA32_DEBUGCTLMSR: 3018 case MSR_IA32_LASTBRANCHFROMIP: 3019 case MSR_IA32_LASTBRANCHTOIP: 3020 case MSR_IA32_LASTINTFROMIP: 3021 case MSR_IA32_LASTINTTOIP: 3022 case MSR_K8_SYSCFG: 3023 case MSR_K8_TSEG_ADDR: 3024 case MSR_K8_TSEG_MASK: 3025 case MSR_VM_HSAVE_PA: 3026 case MSR_K8_INT_PENDING_MSG: 3027 case MSR_AMD64_NB_CFG: 3028 case MSR_FAM10H_MMIO_CONF_BASE: 3029 case MSR_AMD64_BU_CFG2: 3030 case MSR_IA32_PERF_CTL: 3031 case MSR_AMD64_DC_CFG: 3032 case MSR_F15H_EX_CFG: 3033 msr_info->data = 0; 3034 break; 3035 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3036 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3037 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3038 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3039 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3040 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3041 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 3042 msr_info->data = 0; 3043 break; 3044 case MSR_IA32_UCODE_REV: 3045 msr_info->data = vcpu->arch.microcode_version; 3046 break; 3047 case MSR_IA32_ARCH_CAPABILITIES: 3048 if (!msr_info->host_initiated && 3049 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3050 return 1; 3051 msr_info->data = vcpu->arch.arch_capabilities; 3052 break; 3053 case MSR_IA32_POWER_CTL: 3054 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3055 break; 3056 case MSR_IA32_TSC: 3057 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; 3058 break; 3059 case MSR_MTRRcap: 3060 case 0x200 ... 0x2ff: 3061 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3062 case 0xcd: /* fsb frequency */ 3063 msr_info->data = 3; 3064 break; 3065 /* 3066 * MSR_EBC_FREQUENCY_ID 3067 * Conservative value valid for even the basic CPU models. 3068 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3069 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3070 * and 266MHz for model 3, or 4. Set Core Clock 3071 * Frequency to System Bus Frequency Ratio to 1 (bits 3072 * 31:24) even though these are only valid for CPU 3073 * models > 2, however guests may end up dividing or 3074 * multiplying by zero otherwise. 3075 */ 3076 case MSR_EBC_FREQUENCY_ID: 3077 msr_info->data = 1 << 24; 3078 break; 3079 case MSR_IA32_APICBASE: 3080 msr_info->data = kvm_get_apic_base(vcpu); 3081 break; 3082 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 3083 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3084 break; 3085 case MSR_IA32_TSCDEADLINE: 3086 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3087 break; 3088 case MSR_IA32_TSC_ADJUST: 3089 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3090 break; 3091 case MSR_IA32_MISC_ENABLE: 3092 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3093 break; 3094 case MSR_IA32_SMBASE: 3095 if (!msr_info->host_initiated) 3096 return 1; 3097 msr_info->data = vcpu->arch.smbase; 3098 break; 3099 case MSR_SMI_COUNT: 3100 msr_info->data = vcpu->arch.smi_count; 3101 break; 3102 case MSR_IA32_PERF_STATUS: 3103 /* TSC increment by tick */ 3104 msr_info->data = 1000ULL; 3105 /* CPU multiplier */ 3106 msr_info->data |= (((uint64_t)4ULL) << 40); 3107 break; 3108 case MSR_EFER: 3109 msr_info->data = vcpu->arch.efer; 3110 break; 3111 case MSR_KVM_WALL_CLOCK: 3112 case MSR_KVM_WALL_CLOCK_NEW: 3113 msr_info->data = vcpu->kvm->arch.wall_clock; 3114 break; 3115 case MSR_KVM_SYSTEM_TIME: 3116 case MSR_KVM_SYSTEM_TIME_NEW: 3117 msr_info->data = vcpu->arch.time; 3118 break; 3119 case MSR_KVM_ASYNC_PF_EN: 3120 msr_info->data = vcpu->arch.apf.msr_val; 3121 break; 3122 case MSR_KVM_STEAL_TIME: 3123 msr_info->data = vcpu->arch.st.msr_val; 3124 break; 3125 case MSR_KVM_PV_EOI_EN: 3126 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3127 break; 3128 case MSR_KVM_POLL_CONTROL: 3129 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3130 break; 3131 case MSR_IA32_P5_MC_ADDR: 3132 case MSR_IA32_P5_MC_TYPE: 3133 case MSR_IA32_MCG_CAP: 3134 case MSR_IA32_MCG_CTL: 3135 case MSR_IA32_MCG_STATUS: 3136 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3137 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3138 msr_info->host_initiated); 3139 case MSR_IA32_XSS: 3140 if (!msr_info->host_initiated && 3141 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3142 return 1; 3143 msr_info->data = vcpu->arch.ia32_xss; 3144 break; 3145 case MSR_K7_CLK_CTL: 3146 /* 3147 * Provide expected ramp-up count for K7. All other 3148 * are set to zero, indicating minimum divisors for 3149 * every field. 3150 * 3151 * This prevents guest kernels on AMD host with CPU 3152 * type 6, model 8 and higher from exploding due to 3153 * the rdmsr failing. 3154 */ 3155 msr_info->data = 0x20000000; 3156 break; 3157 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3158 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3159 case HV_X64_MSR_CRASH_CTL: 3160 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3161 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3162 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3163 case HV_X64_MSR_TSC_EMULATION_STATUS: 3164 return kvm_hv_get_msr_common(vcpu, 3165 msr_info->index, &msr_info->data, 3166 msr_info->host_initiated); 3167 break; 3168 case MSR_IA32_BBL_CR_CTL3: 3169 /* This legacy MSR exists but isn't fully documented in current 3170 * silicon. It is however accessed by winxp in very narrow 3171 * scenarios where it sets bit #19, itself documented as 3172 * a "reserved" bit. Best effort attempt to source coherent 3173 * read data here should the balance of the register be 3174 * interpreted by the guest: 3175 * 3176 * L2 cache control register 3: 64GB range, 256KB size, 3177 * enabled, latency 0x1, configured 3178 */ 3179 msr_info->data = 0xbe702111; 3180 break; 3181 case MSR_AMD64_OSVW_ID_LENGTH: 3182 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3183 return 1; 3184 msr_info->data = vcpu->arch.osvw.length; 3185 break; 3186 case MSR_AMD64_OSVW_STATUS: 3187 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3188 return 1; 3189 msr_info->data = vcpu->arch.osvw.status; 3190 break; 3191 case MSR_PLATFORM_INFO: 3192 if (!msr_info->host_initiated && 3193 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3194 return 1; 3195 msr_info->data = vcpu->arch.msr_platform_info; 3196 break; 3197 case MSR_MISC_FEATURES_ENABLES: 3198 msr_info->data = vcpu->arch.msr_misc_features_enables; 3199 break; 3200 case MSR_K7_HWCR: 3201 msr_info->data = vcpu->arch.msr_hwcr; 3202 break; 3203 default: 3204 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3205 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 3206 if (!ignore_msrs) { 3207 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 3208 msr_info->index); 3209 return 1; 3210 } else { 3211 if (report_ignored_msrs) 3212 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 3213 msr_info->index); 3214 msr_info->data = 0; 3215 } 3216 break; 3217 } 3218 return 0; 3219 } 3220 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3221 3222 /* 3223 * Read or write a bunch of msrs. All parameters are kernel addresses. 3224 * 3225 * @return number of msrs set successfully. 3226 */ 3227 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3228 struct kvm_msr_entry *entries, 3229 int (*do_msr)(struct kvm_vcpu *vcpu, 3230 unsigned index, u64 *data)) 3231 { 3232 int i; 3233 3234 for (i = 0; i < msrs->nmsrs; ++i) 3235 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3236 break; 3237 3238 return i; 3239 } 3240 3241 /* 3242 * Read or write a bunch of msrs. Parameters are user addresses. 3243 * 3244 * @return number of msrs set successfully. 3245 */ 3246 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3247 int (*do_msr)(struct kvm_vcpu *vcpu, 3248 unsigned index, u64 *data), 3249 int writeback) 3250 { 3251 struct kvm_msrs msrs; 3252 struct kvm_msr_entry *entries; 3253 int r, n; 3254 unsigned size; 3255 3256 r = -EFAULT; 3257 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3258 goto out; 3259 3260 r = -E2BIG; 3261 if (msrs.nmsrs >= MAX_IO_MSRS) 3262 goto out; 3263 3264 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3265 entries = memdup_user(user_msrs->entries, size); 3266 if (IS_ERR(entries)) { 3267 r = PTR_ERR(entries); 3268 goto out; 3269 } 3270 3271 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3272 if (r < 0) 3273 goto out_free; 3274 3275 r = -EFAULT; 3276 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3277 goto out_free; 3278 3279 r = n; 3280 3281 out_free: 3282 kfree(entries); 3283 out: 3284 return r; 3285 } 3286 3287 static inline bool kvm_can_mwait_in_guest(void) 3288 { 3289 return boot_cpu_has(X86_FEATURE_MWAIT) && 3290 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3291 boot_cpu_has(X86_FEATURE_ARAT); 3292 } 3293 3294 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3295 { 3296 int r = 0; 3297 3298 switch (ext) { 3299 case KVM_CAP_IRQCHIP: 3300 case KVM_CAP_HLT: 3301 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3302 case KVM_CAP_SET_TSS_ADDR: 3303 case KVM_CAP_EXT_CPUID: 3304 case KVM_CAP_EXT_EMUL_CPUID: 3305 case KVM_CAP_CLOCKSOURCE: 3306 case KVM_CAP_PIT: 3307 case KVM_CAP_NOP_IO_DELAY: 3308 case KVM_CAP_MP_STATE: 3309 case KVM_CAP_SYNC_MMU: 3310 case KVM_CAP_USER_NMI: 3311 case KVM_CAP_REINJECT_CONTROL: 3312 case KVM_CAP_IRQ_INJECT_STATUS: 3313 case KVM_CAP_IOEVENTFD: 3314 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3315 case KVM_CAP_PIT2: 3316 case KVM_CAP_PIT_STATE2: 3317 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3318 case KVM_CAP_XEN_HVM: 3319 case KVM_CAP_VCPU_EVENTS: 3320 case KVM_CAP_HYPERV: 3321 case KVM_CAP_HYPERV_VAPIC: 3322 case KVM_CAP_HYPERV_SPIN: 3323 case KVM_CAP_HYPERV_SYNIC: 3324 case KVM_CAP_HYPERV_SYNIC2: 3325 case KVM_CAP_HYPERV_VP_INDEX: 3326 case KVM_CAP_HYPERV_EVENTFD: 3327 case KVM_CAP_HYPERV_TLBFLUSH: 3328 case KVM_CAP_HYPERV_SEND_IPI: 3329 case KVM_CAP_HYPERV_CPUID: 3330 case KVM_CAP_PCI_SEGMENT: 3331 case KVM_CAP_DEBUGREGS: 3332 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3333 case KVM_CAP_XSAVE: 3334 case KVM_CAP_ASYNC_PF: 3335 case KVM_CAP_GET_TSC_KHZ: 3336 case KVM_CAP_KVMCLOCK_CTRL: 3337 case KVM_CAP_READONLY_MEM: 3338 case KVM_CAP_HYPERV_TIME: 3339 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3340 case KVM_CAP_TSC_DEADLINE_TIMER: 3341 case KVM_CAP_DISABLE_QUIRKS: 3342 case KVM_CAP_SET_BOOT_CPU_ID: 3343 case KVM_CAP_SPLIT_IRQCHIP: 3344 case KVM_CAP_IMMEDIATE_EXIT: 3345 case KVM_CAP_PMU_EVENT_FILTER: 3346 case KVM_CAP_GET_MSR_FEATURES: 3347 case KVM_CAP_MSR_PLATFORM_INFO: 3348 case KVM_CAP_EXCEPTION_PAYLOAD: 3349 r = 1; 3350 break; 3351 case KVM_CAP_SYNC_REGS: 3352 r = KVM_SYNC_X86_VALID_FIELDS; 3353 break; 3354 case KVM_CAP_ADJUST_CLOCK: 3355 r = KVM_CLOCK_TSC_STABLE; 3356 break; 3357 case KVM_CAP_X86_DISABLE_EXITS: 3358 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 3359 KVM_X86_DISABLE_EXITS_CSTATE; 3360 if(kvm_can_mwait_in_guest()) 3361 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3362 break; 3363 case KVM_CAP_X86_SMM: 3364 /* SMBASE is usually relocated above 1M on modern chipsets, 3365 * and SMM handlers might indeed rely on 4G segment limits, 3366 * so do not report SMM to be available if real mode is 3367 * emulated via vm86 mode. Still, do not go to great lengths 3368 * to avoid userspace's usage of the feature, because it is a 3369 * fringe case that is not enabled except via specific settings 3370 * of the module parameters. 3371 */ 3372 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE); 3373 break; 3374 case KVM_CAP_VAPIC: 3375 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 3376 break; 3377 case KVM_CAP_NR_VCPUS: 3378 r = KVM_SOFT_MAX_VCPUS; 3379 break; 3380 case KVM_CAP_MAX_VCPUS: 3381 r = KVM_MAX_VCPUS; 3382 break; 3383 case KVM_CAP_MAX_VCPU_ID: 3384 r = KVM_MAX_VCPU_ID; 3385 break; 3386 case KVM_CAP_PV_MMU: /* obsolete */ 3387 r = 0; 3388 break; 3389 case KVM_CAP_MCE: 3390 r = KVM_MAX_MCE_BANKS; 3391 break; 3392 case KVM_CAP_XCRS: 3393 r = boot_cpu_has(X86_FEATURE_XSAVE); 3394 break; 3395 case KVM_CAP_TSC_CONTROL: 3396 r = kvm_has_tsc_control; 3397 break; 3398 case KVM_CAP_X2APIC_API: 3399 r = KVM_X2APIC_API_VALID_FLAGS; 3400 break; 3401 case KVM_CAP_NESTED_STATE: 3402 r = kvm_x86_ops->get_nested_state ? 3403 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0; 3404 break; 3405 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 3406 r = kvm_x86_ops->enable_direct_tlbflush != NULL; 3407 break; 3408 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3409 r = kvm_x86_ops->nested_enable_evmcs != NULL; 3410 break; 3411 default: 3412 break; 3413 } 3414 return r; 3415 3416 } 3417 3418 long kvm_arch_dev_ioctl(struct file *filp, 3419 unsigned int ioctl, unsigned long arg) 3420 { 3421 void __user *argp = (void __user *)arg; 3422 long r; 3423 3424 switch (ioctl) { 3425 case KVM_GET_MSR_INDEX_LIST: { 3426 struct kvm_msr_list __user *user_msr_list = argp; 3427 struct kvm_msr_list msr_list; 3428 unsigned n; 3429 3430 r = -EFAULT; 3431 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3432 goto out; 3433 n = msr_list.nmsrs; 3434 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3435 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3436 goto out; 3437 r = -E2BIG; 3438 if (n < msr_list.nmsrs) 3439 goto out; 3440 r = -EFAULT; 3441 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3442 num_msrs_to_save * sizeof(u32))) 3443 goto out; 3444 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3445 &emulated_msrs, 3446 num_emulated_msrs * sizeof(u32))) 3447 goto out; 3448 r = 0; 3449 break; 3450 } 3451 case KVM_GET_SUPPORTED_CPUID: 3452 case KVM_GET_EMULATED_CPUID: { 3453 struct kvm_cpuid2 __user *cpuid_arg = argp; 3454 struct kvm_cpuid2 cpuid; 3455 3456 r = -EFAULT; 3457 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3458 goto out; 3459 3460 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3461 ioctl); 3462 if (r) 3463 goto out; 3464 3465 r = -EFAULT; 3466 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3467 goto out; 3468 r = 0; 3469 break; 3470 } 3471 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 3472 r = -EFAULT; 3473 if (copy_to_user(argp, &kvm_mce_cap_supported, 3474 sizeof(kvm_mce_cap_supported))) 3475 goto out; 3476 r = 0; 3477 break; 3478 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3479 struct kvm_msr_list __user *user_msr_list = argp; 3480 struct kvm_msr_list msr_list; 3481 unsigned int n; 3482 3483 r = -EFAULT; 3484 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3485 goto out; 3486 n = msr_list.nmsrs; 3487 msr_list.nmsrs = num_msr_based_features; 3488 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3489 goto out; 3490 r = -E2BIG; 3491 if (n < msr_list.nmsrs) 3492 goto out; 3493 r = -EFAULT; 3494 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3495 num_msr_based_features * sizeof(u32))) 3496 goto out; 3497 r = 0; 3498 break; 3499 } 3500 case KVM_GET_MSRS: 3501 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3502 break; 3503 } 3504 default: 3505 r = -EINVAL; 3506 } 3507 out: 3508 return r; 3509 } 3510 3511 static void wbinvd_ipi(void *garbage) 3512 { 3513 wbinvd(); 3514 } 3515 3516 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3517 { 3518 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3519 } 3520 3521 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3522 { 3523 /* Address WBINVD may be executed by guest */ 3524 if (need_emulate_wbinvd(vcpu)) { 3525 if (kvm_x86_ops->has_wbinvd_exit()) 3526 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3527 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3528 smp_call_function_single(vcpu->cpu, 3529 wbinvd_ipi, NULL, 1); 3530 } 3531 3532 kvm_x86_ops->vcpu_load(vcpu, cpu); 3533 3534 /* Apply any externally detected TSC adjustments (due to suspend) */ 3535 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3536 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3537 vcpu->arch.tsc_offset_adjustment = 0; 3538 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3539 } 3540 3541 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3542 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3543 rdtsc() - vcpu->arch.last_host_tsc; 3544 if (tsc_delta < 0) 3545 mark_tsc_unstable("KVM discovered backwards TSC"); 3546 3547 if (kvm_check_tsc_unstable()) { 3548 u64 offset = kvm_compute_tsc_offset(vcpu, 3549 vcpu->arch.last_guest_tsc); 3550 kvm_vcpu_write_tsc_offset(vcpu, offset); 3551 vcpu->arch.tsc_catchup = 1; 3552 } 3553 3554 if (kvm_lapic_hv_timer_in_use(vcpu)) 3555 kvm_lapic_restart_hv_timer(vcpu); 3556 3557 /* 3558 * On a host with synchronized TSC, there is no need to update 3559 * kvmclock on vcpu->cpu migration 3560 */ 3561 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3562 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3563 if (vcpu->cpu != cpu) 3564 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3565 vcpu->cpu = cpu; 3566 } 3567 3568 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3569 } 3570 3571 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3572 { 3573 struct kvm_host_map map; 3574 struct kvm_steal_time *st; 3575 3576 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3577 return; 3578 3579 if (vcpu->arch.st.preempted) 3580 return; 3581 3582 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 3583 &vcpu->arch.st.cache, true)) 3584 return; 3585 3586 st = map.hva + 3587 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 3588 3589 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 3590 3591 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 3592 } 3593 3594 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3595 { 3596 int idx; 3597 3598 if (vcpu->preempted) 3599 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 3600 3601 /* 3602 * Disable page faults because we're in atomic context here. 3603 * kvm_write_guest_offset_cached() would call might_fault() 3604 * that relies on pagefault_disable() to tell if there's a 3605 * bug. NOTE: the write to guest memory may not go through if 3606 * during postcopy live migration or if there's heavy guest 3607 * paging. 3608 */ 3609 pagefault_disable(); 3610 /* 3611 * kvm_memslots() will be called by 3612 * kvm_write_guest_offset_cached() so take the srcu lock. 3613 */ 3614 idx = srcu_read_lock(&vcpu->kvm->srcu); 3615 kvm_steal_time_set_preempted(vcpu); 3616 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3617 pagefault_enable(); 3618 kvm_x86_ops->vcpu_put(vcpu); 3619 vcpu->arch.last_host_tsc = rdtsc(); 3620 /* 3621 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3622 * on every vmexit, but if not, we might have a stale dr6 from the 3623 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3624 */ 3625 set_debugreg(0, 6); 3626 } 3627 3628 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3629 struct kvm_lapic_state *s) 3630 { 3631 if (vcpu->arch.apicv_active) 3632 kvm_x86_ops->sync_pir_to_irr(vcpu); 3633 3634 return kvm_apic_get_state(vcpu, s); 3635 } 3636 3637 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3638 struct kvm_lapic_state *s) 3639 { 3640 int r; 3641 3642 r = kvm_apic_set_state(vcpu, s); 3643 if (r) 3644 return r; 3645 update_cr8_intercept(vcpu); 3646 3647 return 0; 3648 } 3649 3650 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3651 { 3652 return (!lapic_in_kernel(vcpu) || 3653 kvm_apic_accept_pic_intr(vcpu)); 3654 } 3655 3656 /* 3657 * if userspace requested an interrupt window, check that the 3658 * interrupt window is open. 3659 * 3660 * No need to exit to userspace if we already have an interrupt queued. 3661 */ 3662 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3663 { 3664 return kvm_arch_interrupt_allowed(vcpu) && 3665 !kvm_cpu_has_interrupt(vcpu) && 3666 !kvm_event_needs_reinjection(vcpu) && 3667 kvm_cpu_accept_dm_intr(vcpu); 3668 } 3669 3670 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3671 struct kvm_interrupt *irq) 3672 { 3673 if (irq->irq >= KVM_NR_INTERRUPTS) 3674 return -EINVAL; 3675 3676 if (!irqchip_in_kernel(vcpu->kvm)) { 3677 kvm_queue_interrupt(vcpu, irq->irq, false); 3678 kvm_make_request(KVM_REQ_EVENT, vcpu); 3679 return 0; 3680 } 3681 3682 /* 3683 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3684 * fail for in-kernel 8259. 3685 */ 3686 if (pic_in_kernel(vcpu->kvm)) 3687 return -ENXIO; 3688 3689 if (vcpu->arch.pending_external_vector != -1) 3690 return -EEXIST; 3691 3692 vcpu->arch.pending_external_vector = irq->irq; 3693 kvm_make_request(KVM_REQ_EVENT, vcpu); 3694 return 0; 3695 } 3696 3697 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3698 { 3699 kvm_inject_nmi(vcpu); 3700 3701 return 0; 3702 } 3703 3704 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3705 { 3706 kvm_make_request(KVM_REQ_SMI, vcpu); 3707 3708 return 0; 3709 } 3710 3711 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3712 struct kvm_tpr_access_ctl *tac) 3713 { 3714 if (tac->flags) 3715 return -EINVAL; 3716 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3717 return 0; 3718 } 3719 3720 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3721 u64 mcg_cap) 3722 { 3723 int r; 3724 unsigned bank_num = mcg_cap & 0xff, bank; 3725 3726 r = -EINVAL; 3727 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3728 goto out; 3729 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3730 goto out; 3731 r = 0; 3732 vcpu->arch.mcg_cap = mcg_cap; 3733 /* Init IA32_MCG_CTL to all 1s */ 3734 if (mcg_cap & MCG_CTL_P) 3735 vcpu->arch.mcg_ctl = ~(u64)0; 3736 /* Init IA32_MCi_CTL to all 1s */ 3737 for (bank = 0; bank < bank_num; bank++) 3738 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3739 3740 kvm_x86_ops->setup_mce(vcpu); 3741 out: 3742 return r; 3743 } 3744 3745 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3746 struct kvm_x86_mce *mce) 3747 { 3748 u64 mcg_cap = vcpu->arch.mcg_cap; 3749 unsigned bank_num = mcg_cap & 0xff; 3750 u64 *banks = vcpu->arch.mce_banks; 3751 3752 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3753 return -EINVAL; 3754 /* 3755 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3756 * reporting is disabled 3757 */ 3758 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3759 vcpu->arch.mcg_ctl != ~(u64)0) 3760 return 0; 3761 banks += 4 * mce->bank; 3762 /* 3763 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3764 * reporting is disabled for the bank 3765 */ 3766 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3767 return 0; 3768 if (mce->status & MCI_STATUS_UC) { 3769 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3770 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3771 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3772 return 0; 3773 } 3774 if (banks[1] & MCI_STATUS_VAL) 3775 mce->status |= MCI_STATUS_OVER; 3776 banks[2] = mce->addr; 3777 banks[3] = mce->misc; 3778 vcpu->arch.mcg_status = mce->mcg_status; 3779 banks[1] = mce->status; 3780 kvm_queue_exception(vcpu, MC_VECTOR); 3781 } else if (!(banks[1] & MCI_STATUS_VAL) 3782 || !(banks[1] & MCI_STATUS_UC)) { 3783 if (banks[1] & MCI_STATUS_VAL) 3784 mce->status |= MCI_STATUS_OVER; 3785 banks[2] = mce->addr; 3786 banks[3] = mce->misc; 3787 banks[1] = mce->status; 3788 } else 3789 banks[1] |= MCI_STATUS_OVER; 3790 return 0; 3791 } 3792 3793 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3794 struct kvm_vcpu_events *events) 3795 { 3796 process_nmi(vcpu); 3797 3798 /* 3799 * The API doesn't provide the instruction length for software 3800 * exceptions, so don't report them. As long as the guest RIP 3801 * isn't advanced, we should expect to encounter the exception 3802 * again. 3803 */ 3804 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 3805 events->exception.injected = 0; 3806 events->exception.pending = 0; 3807 } else { 3808 events->exception.injected = vcpu->arch.exception.injected; 3809 events->exception.pending = vcpu->arch.exception.pending; 3810 /* 3811 * For ABI compatibility, deliberately conflate 3812 * pending and injected exceptions when 3813 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 3814 */ 3815 if (!vcpu->kvm->arch.exception_payload_enabled) 3816 events->exception.injected |= 3817 vcpu->arch.exception.pending; 3818 } 3819 events->exception.nr = vcpu->arch.exception.nr; 3820 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3821 events->exception.error_code = vcpu->arch.exception.error_code; 3822 events->exception_has_payload = vcpu->arch.exception.has_payload; 3823 events->exception_payload = vcpu->arch.exception.payload; 3824 3825 events->interrupt.injected = 3826 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3827 events->interrupt.nr = vcpu->arch.interrupt.nr; 3828 events->interrupt.soft = 0; 3829 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3830 3831 events->nmi.injected = vcpu->arch.nmi_injected; 3832 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3833 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3834 events->nmi.pad = 0; 3835 3836 events->sipi_vector = 0; /* never valid when reporting to user space */ 3837 3838 events->smi.smm = is_smm(vcpu); 3839 events->smi.pending = vcpu->arch.smi_pending; 3840 events->smi.smm_inside_nmi = 3841 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3842 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3843 3844 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3845 | KVM_VCPUEVENT_VALID_SHADOW 3846 | KVM_VCPUEVENT_VALID_SMM); 3847 if (vcpu->kvm->arch.exception_payload_enabled) 3848 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 3849 3850 memset(&events->reserved, 0, sizeof(events->reserved)); 3851 } 3852 3853 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 3854 3855 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3856 struct kvm_vcpu_events *events) 3857 { 3858 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3859 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3860 | KVM_VCPUEVENT_VALID_SHADOW 3861 | KVM_VCPUEVENT_VALID_SMM 3862 | KVM_VCPUEVENT_VALID_PAYLOAD)) 3863 return -EINVAL; 3864 3865 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 3866 if (!vcpu->kvm->arch.exception_payload_enabled) 3867 return -EINVAL; 3868 if (events->exception.pending) 3869 events->exception.injected = 0; 3870 else 3871 events->exception_has_payload = 0; 3872 } else { 3873 events->exception.pending = 0; 3874 events->exception_has_payload = 0; 3875 } 3876 3877 if ((events->exception.injected || events->exception.pending) && 3878 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 3879 return -EINVAL; 3880 3881 /* INITs are latched while in SMM */ 3882 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3883 (events->smi.smm || events->smi.pending) && 3884 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3885 return -EINVAL; 3886 3887 process_nmi(vcpu); 3888 vcpu->arch.exception.injected = events->exception.injected; 3889 vcpu->arch.exception.pending = events->exception.pending; 3890 vcpu->arch.exception.nr = events->exception.nr; 3891 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3892 vcpu->arch.exception.error_code = events->exception.error_code; 3893 vcpu->arch.exception.has_payload = events->exception_has_payload; 3894 vcpu->arch.exception.payload = events->exception_payload; 3895 3896 vcpu->arch.interrupt.injected = events->interrupt.injected; 3897 vcpu->arch.interrupt.nr = events->interrupt.nr; 3898 vcpu->arch.interrupt.soft = events->interrupt.soft; 3899 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3900 kvm_x86_ops->set_interrupt_shadow(vcpu, 3901 events->interrupt.shadow); 3902 3903 vcpu->arch.nmi_injected = events->nmi.injected; 3904 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3905 vcpu->arch.nmi_pending = events->nmi.pending; 3906 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3907 3908 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3909 lapic_in_kernel(vcpu)) 3910 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3911 3912 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3913 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 3914 if (events->smi.smm) 3915 vcpu->arch.hflags |= HF_SMM_MASK; 3916 else 3917 vcpu->arch.hflags &= ~HF_SMM_MASK; 3918 kvm_smm_changed(vcpu); 3919 } 3920 3921 vcpu->arch.smi_pending = events->smi.pending; 3922 3923 if (events->smi.smm) { 3924 if (events->smi.smm_inside_nmi) 3925 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3926 else 3927 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3928 } 3929 3930 if (lapic_in_kernel(vcpu)) { 3931 if (events->smi.latched_init) 3932 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3933 else 3934 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3935 } 3936 } 3937 3938 kvm_make_request(KVM_REQ_EVENT, vcpu); 3939 3940 return 0; 3941 } 3942 3943 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3944 struct kvm_debugregs *dbgregs) 3945 { 3946 unsigned long val; 3947 3948 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3949 kvm_get_dr(vcpu, 6, &val); 3950 dbgregs->dr6 = val; 3951 dbgregs->dr7 = vcpu->arch.dr7; 3952 dbgregs->flags = 0; 3953 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3954 } 3955 3956 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3957 struct kvm_debugregs *dbgregs) 3958 { 3959 if (dbgregs->flags) 3960 return -EINVAL; 3961 3962 if (dbgregs->dr6 & ~0xffffffffull) 3963 return -EINVAL; 3964 if (dbgregs->dr7 & ~0xffffffffull) 3965 return -EINVAL; 3966 3967 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3968 kvm_update_dr0123(vcpu); 3969 vcpu->arch.dr6 = dbgregs->dr6; 3970 kvm_update_dr6(vcpu); 3971 vcpu->arch.dr7 = dbgregs->dr7; 3972 kvm_update_dr7(vcpu); 3973 3974 return 0; 3975 } 3976 3977 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3978 3979 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3980 { 3981 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 3982 u64 xstate_bv = xsave->header.xfeatures; 3983 u64 valid; 3984 3985 /* 3986 * Copy legacy XSAVE area, to avoid complications with CPUID 3987 * leaves 0 and 1 in the loop below. 3988 */ 3989 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3990 3991 /* Set XSTATE_BV */ 3992 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3993 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3994 3995 /* 3996 * Copy each region from the possibly compacted offset to the 3997 * non-compacted offset. 3998 */ 3999 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4000 while (valid) { 4001 u64 xfeature_mask = valid & -valid; 4002 int xfeature_nr = fls64(xfeature_mask) - 1; 4003 void *src = get_xsave_addr(xsave, xfeature_nr); 4004 4005 if (src) { 4006 u32 size, offset, ecx, edx; 4007 cpuid_count(XSTATE_CPUID, xfeature_nr, 4008 &size, &offset, &ecx, &edx); 4009 if (xfeature_nr == XFEATURE_PKRU) 4010 memcpy(dest + offset, &vcpu->arch.pkru, 4011 sizeof(vcpu->arch.pkru)); 4012 else 4013 memcpy(dest + offset, src, size); 4014 4015 } 4016 4017 valid -= xfeature_mask; 4018 } 4019 } 4020 4021 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4022 { 4023 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4024 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4025 u64 valid; 4026 4027 /* 4028 * Copy legacy XSAVE area, to avoid complications with CPUID 4029 * leaves 0 and 1 in the loop below. 4030 */ 4031 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4032 4033 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4034 xsave->header.xfeatures = xstate_bv; 4035 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4036 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4037 4038 /* 4039 * Copy each region from the non-compacted offset to the 4040 * possibly compacted offset. 4041 */ 4042 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4043 while (valid) { 4044 u64 xfeature_mask = valid & -valid; 4045 int xfeature_nr = fls64(xfeature_mask) - 1; 4046 void *dest = get_xsave_addr(xsave, xfeature_nr); 4047 4048 if (dest) { 4049 u32 size, offset, ecx, edx; 4050 cpuid_count(XSTATE_CPUID, xfeature_nr, 4051 &size, &offset, &ecx, &edx); 4052 if (xfeature_nr == XFEATURE_PKRU) 4053 memcpy(&vcpu->arch.pkru, src + offset, 4054 sizeof(vcpu->arch.pkru)); 4055 else 4056 memcpy(dest, src + offset, size); 4057 } 4058 4059 valid -= xfeature_mask; 4060 } 4061 } 4062 4063 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4064 struct kvm_xsave *guest_xsave) 4065 { 4066 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4067 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4068 fill_xsave((u8 *) guest_xsave->region, vcpu); 4069 } else { 4070 memcpy(guest_xsave->region, 4071 &vcpu->arch.guest_fpu->state.fxsave, 4072 sizeof(struct fxregs_state)); 4073 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4074 XFEATURE_MASK_FPSSE; 4075 } 4076 } 4077 4078 #define XSAVE_MXCSR_OFFSET 24 4079 4080 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4081 struct kvm_xsave *guest_xsave) 4082 { 4083 u64 xstate_bv = 4084 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4085 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4086 4087 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4088 /* 4089 * Here we allow setting states that are not present in 4090 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4091 * with old userspace. 4092 */ 4093 if (xstate_bv & ~kvm_supported_xcr0() || 4094 mxcsr & ~mxcsr_feature_mask) 4095 return -EINVAL; 4096 load_xsave(vcpu, (u8 *)guest_xsave->region); 4097 } else { 4098 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4099 mxcsr & ~mxcsr_feature_mask) 4100 return -EINVAL; 4101 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4102 guest_xsave->region, sizeof(struct fxregs_state)); 4103 } 4104 return 0; 4105 } 4106 4107 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4108 struct kvm_xcrs *guest_xcrs) 4109 { 4110 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4111 guest_xcrs->nr_xcrs = 0; 4112 return; 4113 } 4114 4115 guest_xcrs->nr_xcrs = 1; 4116 guest_xcrs->flags = 0; 4117 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4118 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4119 } 4120 4121 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4122 struct kvm_xcrs *guest_xcrs) 4123 { 4124 int i, r = 0; 4125 4126 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4127 return -EINVAL; 4128 4129 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4130 return -EINVAL; 4131 4132 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4133 /* Only support XCR0 currently */ 4134 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4135 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4136 guest_xcrs->xcrs[i].value); 4137 break; 4138 } 4139 if (r) 4140 r = -EINVAL; 4141 return r; 4142 } 4143 4144 /* 4145 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4146 * stopped by the hypervisor. This function will be called from the host only. 4147 * EINVAL is returned when the host attempts to set the flag for a guest that 4148 * does not support pv clocks. 4149 */ 4150 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4151 { 4152 if (!vcpu->arch.pv_time_enabled) 4153 return -EINVAL; 4154 vcpu->arch.pvclock_set_guest_stopped_request = true; 4155 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4156 return 0; 4157 } 4158 4159 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4160 struct kvm_enable_cap *cap) 4161 { 4162 int r; 4163 uint16_t vmcs_version; 4164 void __user *user_ptr; 4165 4166 if (cap->flags) 4167 return -EINVAL; 4168 4169 switch (cap->cap) { 4170 case KVM_CAP_HYPERV_SYNIC2: 4171 if (cap->args[0]) 4172 return -EINVAL; 4173 /* fall through */ 4174 4175 case KVM_CAP_HYPERV_SYNIC: 4176 if (!irqchip_in_kernel(vcpu->kvm)) 4177 return -EINVAL; 4178 return kvm_hv_activate_synic(vcpu, cap->cap == 4179 KVM_CAP_HYPERV_SYNIC2); 4180 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4181 if (!kvm_x86_ops->nested_enable_evmcs) 4182 return -ENOTTY; 4183 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version); 4184 if (!r) { 4185 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4186 if (copy_to_user(user_ptr, &vmcs_version, 4187 sizeof(vmcs_version))) 4188 r = -EFAULT; 4189 } 4190 return r; 4191 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4192 if (!kvm_x86_ops->enable_direct_tlbflush) 4193 return -ENOTTY; 4194 4195 return kvm_x86_ops->enable_direct_tlbflush(vcpu); 4196 4197 default: 4198 return -EINVAL; 4199 } 4200 } 4201 4202 long kvm_arch_vcpu_ioctl(struct file *filp, 4203 unsigned int ioctl, unsigned long arg) 4204 { 4205 struct kvm_vcpu *vcpu = filp->private_data; 4206 void __user *argp = (void __user *)arg; 4207 int r; 4208 union { 4209 struct kvm_lapic_state *lapic; 4210 struct kvm_xsave *xsave; 4211 struct kvm_xcrs *xcrs; 4212 void *buffer; 4213 } u; 4214 4215 vcpu_load(vcpu); 4216 4217 u.buffer = NULL; 4218 switch (ioctl) { 4219 case KVM_GET_LAPIC: { 4220 r = -EINVAL; 4221 if (!lapic_in_kernel(vcpu)) 4222 goto out; 4223 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4224 GFP_KERNEL_ACCOUNT); 4225 4226 r = -ENOMEM; 4227 if (!u.lapic) 4228 goto out; 4229 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4230 if (r) 4231 goto out; 4232 r = -EFAULT; 4233 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4234 goto out; 4235 r = 0; 4236 break; 4237 } 4238 case KVM_SET_LAPIC: { 4239 r = -EINVAL; 4240 if (!lapic_in_kernel(vcpu)) 4241 goto out; 4242 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4243 if (IS_ERR(u.lapic)) { 4244 r = PTR_ERR(u.lapic); 4245 goto out_nofree; 4246 } 4247 4248 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4249 break; 4250 } 4251 case KVM_INTERRUPT: { 4252 struct kvm_interrupt irq; 4253 4254 r = -EFAULT; 4255 if (copy_from_user(&irq, argp, sizeof(irq))) 4256 goto out; 4257 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4258 break; 4259 } 4260 case KVM_NMI: { 4261 r = kvm_vcpu_ioctl_nmi(vcpu); 4262 break; 4263 } 4264 case KVM_SMI: { 4265 r = kvm_vcpu_ioctl_smi(vcpu); 4266 break; 4267 } 4268 case KVM_SET_CPUID: { 4269 struct kvm_cpuid __user *cpuid_arg = argp; 4270 struct kvm_cpuid cpuid; 4271 4272 r = -EFAULT; 4273 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4274 goto out; 4275 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4276 break; 4277 } 4278 case KVM_SET_CPUID2: { 4279 struct kvm_cpuid2 __user *cpuid_arg = argp; 4280 struct kvm_cpuid2 cpuid; 4281 4282 r = -EFAULT; 4283 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4284 goto out; 4285 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4286 cpuid_arg->entries); 4287 break; 4288 } 4289 case KVM_GET_CPUID2: { 4290 struct kvm_cpuid2 __user *cpuid_arg = argp; 4291 struct kvm_cpuid2 cpuid; 4292 4293 r = -EFAULT; 4294 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4295 goto out; 4296 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4297 cpuid_arg->entries); 4298 if (r) 4299 goto out; 4300 r = -EFAULT; 4301 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4302 goto out; 4303 r = 0; 4304 break; 4305 } 4306 case KVM_GET_MSRS: { 4307 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4308 r = msr_io(vcpu, argp, do_get_msr, 1); 4309 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4310 break; 4311 } 4312 case KVM_SET_MSRS: { 4313 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4314 r = msr_io(vcpu, argp, do_set_msr, 0); 4315 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4316 break; 4317 } 4318 case KVM_TPR_ACCESS_REPORTING: { 4319 struct kvm_tpr_access_ctl tac; 4320 4321 r = -EFAULT; 4322 if (copy_from_user(&tac, argp, sizeof(tac))) 4323 goto out; 4324 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4325 if (r) 4326 goto out; 4327 r = -EFAULT; 4328 if (copy_to_user(argp, &tac, sizeof(tac))) 4329 goto out; 4330 r = 0; 4331 break; 4332 }; 4333 case KVM_SET_VAPIC_ADDR: { 4334 struct kvm_vapic_addr va; 4335 int idx; 4336 4337 r = -EINVAL; 4338 if (!lapic_in_kernel(vcpu)) 4339 goto out; 4340 r = -EFAULT; 4341 if (copy_from_user(&va, argp, sizeof(va))) 4342 goto out; 4343 idx = srcu_read_lock(&vcpu->kvm->srcu); 4344 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4345 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4346 break; 4347 } 4348 case KVM_X86_SETUP_MCE: { 4349 u64 mcg_cap; 4350 4351 r = -EFAULT; 4352 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4353 goto out; 4354 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4355 break; 4356 } 4357 case KVM_X86_SET_MCE: { 4358 struct kvm_x86_mce mce; 4359 4360 r = -EFAULT; 4361 if (copy_from_user(&mce, argp, sizeof(mce))) 4362 goto out; 4363 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4364 break; 4365 } 4366 case KVM_GET_VCPU_EVENTS: { 4367 struct kvm_vcpu_events events; 4368 4369 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4370 4371 r = -EFAULT; 4372 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4373 break; 4374 r = 0; 4375 break; 4376 } 4377 case KVM_SET_VCPU_EVENTS: { 4378 struct kvm_vcpu_events events; 4379 4380 r = -EFAULT; 4381 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4382 break; 4383 4384 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4385 break; 4386 } 4387 case KVM_GET_DEBUGREGS: { 4388 struct kvm_debugregs dbgregs; 4389 4390 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4391 4392 r = -EFAULT; 4393 if (copy_to_user(argp, &dbgregs, 4394 sizeof(struct kvm_debugregs))) 4395 break; 4396 r = 0; 4397 break; 4398 } 4399 case KVM_SET_DEBUGREGS: { 4400 struct kvm_debugregs dbgregs; 4401 4402 r = -EFAULT; 4403 if (copy_from_user(&dbgregs, argp, 4404 sizeof(struct kvm_debugregs))) 4405 break; 4406 4407 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4408 break; 4409 } 4410 case KVM_GET_XSAVE: { 4411 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4412 r = -ENOMEM; 4413 if (!u.xsave) 4414 break; 4415 4416 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4417 4418 r = -EFAULT; 4419 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4420 break; 4421 r = 0; 4422 break; 4423 } 4424 case KVM_SET_XSAVE: { 4425 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4426 if (IS_ERR(u.xsave)) { 4427 r = PTR_ERR(u.xsave); 4428 goto out_nofree; 4429 } 4430 4431 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4432 break; 4433 } 4434 case KVM_GET_XCRS: { 4435 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4436 r = -ENOMEM; 4437 if (!u.xcrs) 4438 break; 4439 4440 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4441 4442 r = -EFAULT; 4443 if (copy_to_user(argp, u.xcrs, 4444 sizeof(struct kvm_xcrs))) 4445 break; 4446 r = 0; 4447 break; 4448 } 4449 case KVM_SET_XCRS: { 4450 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4451 if (IS_ERR(u.xcrs)) { 4452 r = PTR_ERR(u.xcrs); 4453 goto out_nofree; 4454 } 4455 4456 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4457 break; 4458 } 4459 case KVM_SET_TSC_KHZ: { 4460 u32 user_tsc_khz; 4461 4462 r = -EINVAL; 4463 user_tsc_khz = (u32)arg; 4464 4465 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 4466 goto out; 4467 4468 if (user_tsc_khz == 0) 4469 user_tsc_khz = tsc_khz; 4470 4471 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4472 r = 0; 4473 4474 goto out; 4475 } 4476 case KVM_GET_TSC_KHZ: { 4477 r = vcpu->arch.virtual_tsc_khz; 4478 goto out; 4479 } 4480 case KVM_KVMCLOCK_CTRL: { 4481 r = kvm_set_guest_paused(vcpu); 4482 goto out; 4483 } 4484 case KVM_ENABLE_CAP: { 4485 struct kvm_enable_cap cap; 4486 4487 r = -EFAULT; 4488 if (copy_from_user(&cap, argp, sizeof(cap))) 4489 goto out; 4490 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4491 break; 4492 } 4493 case KVM_GET_NESTED_STATE: { 4494 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4495 u32 user_data_size; 4496 4497 r = -EINVAL; 4498 if (!kvm_x86_ops->get_nested_state) 4499 break; 4500 4501 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4502 r = -EFAULT; 4503 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4504 break; 4505 4506 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state, 4507 user_data_size); 4508 if (r < 0) 4509 break; 4510 4511 if (r > user_data_size) { 4512 if (put_user(r, &user_kvm_nested_state->size)) 4513 r = -EFAULT; 4514 else 4515 r = -E2BIG; 4516 break; 4517 } 4518 4519 r = 0; 4520 break; 4521 } 4522 case KVM_SET_NESTED_STATE: { 4523 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4524 struct kvm_nested_state kvm_state; 4525 int idx; 4526 4527 r = -EINVAL; 4528 if (!kvm_x86_ops->set_nested_state) 4529 break; 4530 4531 r = -EFAULT; 4532 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 4533 break; 4534 4535 r = -EINVAL; 4536 if (kvm_state.size < sizeof(kvm_state)) 4537 break; 4538 4539 if (kvm_state.flags & 4540 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 4541 | KVM_STATE_NESTED_EVMCS)) 4542 break; 4543 4544 /* nested_run_pending implies guest_mode. */ 4545 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 4546 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 4547 break; 4548 4549 idx = srcu_read_lock(&vcpu->kvm->srcu); 4550 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); 4551 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4552 break; 4553 } 4554 case KVM_GET_SUPPORTED_HV_CPUID: { 4555 struct kvm_cpuid2 __user *cpuid_arg = argp; 4556 struct kvm_cpuid2 cpuid; 4557 4558 r = -EFAULT; 4559 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4560 goto out; 4561 4562 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, 4563 cpuid_arg->entries); 4564 if (r) 4565 goto out; 4566 4567 r = -EFAULT; 4568 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4569 goto out; 4570 r = 0; 4571 break; 4572 } 4573 default: 4574 r = -EINVAL; 4575 } 4576 out: 4577 kfree(u.buffer); 4578 out_nofree: 4579 vcpu_put(vcpu); 4580 return r; 4581 } 4582 4583 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 4584 { 4585 return VM_FAULT_SIGBUS; 4586 } 4587 4588 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 4589 { 4590 int ret; 4591 4592 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 4593 return -EINVAL; 4594 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 4595 return ret; 4596 } 4597 4598 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 4599 u64 ident_addr) 4600 { 4601 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); 4602 } 4603 4604 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 4605 unsigned long kvm_nr_mmu_pages) 4606 { 4607 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 4608 return -EINVAL; 4609 4610 mutex_lock(&kvm->slots_lock); 4611 4612 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 4613 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 4614 4615 mutex_unlock(&kvm->slots_lock); 4616 return 0; 4617 } 4618 4619 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 4620 { 4621 return kvm->arch.n_max_mmu_pages; 4622 } 4623 4624 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4625 { 4626 struct kvm_pic *pic = kvm->arch.vpic; 4627 int r; 4628 4629 r = 0; 4630 switch (chip->chip_id) { 4631 case KVM_IRQCHIP_PIC_MASTER: 4632 memcpy(&chip->chip.pic, &pic->pics[0], 4633 sizeof(struct kvm_pic_state)); 4634 break; 4635 case KVM_IRQCHIP_PIC_SLAVE: 4636 memcpy(&chip->chip.pic, &pic->pics[1], 4637 sizeof(struct kvm_pic_state)); 4638 break; 4639 case KVM_IRQCHIP_IOAPIC: 4640 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4641 break; 4642 default: 4643 r = -EINVAL; 4644 break; 4645 } 4646 return r; 4647 } 4648 4649 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4650 { 4651 struct kvm_pic *pic = kvm->arch.vpic; 4652 int r; 4653 4654 r = 0; 4655 switch (chip->chip_id) { 4656 case KVM_IRQCHIP_PIC_MASTER: 4657 spin_lock(&pic->lock); 4658 memcpy(&pic->pics[0], &chip->chip.pic, 4659 sizeof(struct kvm_pic_state)); 4660 spin_unlock(&pic->lock); 4661 break; 4662 case KVM_IRQCHIP_PIC_SLAVE: 4663 spin_lock(&pic->lock); 4664 memcpy(&pic->pics[1], &chip->chip.pic, 4665 sizeof(struct kvm_pic_state)); 4666 spin_unlock(&pic->lock); 4667 break; 4668 case KVM_IRQCHIP_IOAPIC: 4669 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4670 break; 4671 default: 4672 r = -EINVAL; 4673 break; 4674 } 4675 kvm_pic_update_irq(pic); 4676 return r; 4677 } 4678 4679 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4680 { 4681 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4682 4683 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4684 4685 mutex_lock(&kps->lock); 4686 memcpy(ps, &kps->channels, sizeof(*ps)); 4687 mutex_unlock(&kps->lock); 4688 return 0; 4689 } 4690 4691 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4692 { 4693 int i; 4694 struct kvm_pit *pit = kvm->arch.vpit; 4695 4696 mutex_lock(&pit->pit_state.lock); 4697 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4698 for (i = 0; i < 3; i++) 4699 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4700 mutex_unlock(&pit->pit_state.lock); 4701 return 0; 4702 } 4703 4704 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4705 { 4706 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4707 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4708 sizeof(ps->channels)); 4709 ps->flags = kvm->arch.vpit->pit_state.flags; 4710 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4711 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4712 return 0; 4713 } 4714 4715 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4716 { 4717 int start = 0; 4718 int i; 4719 u32 prev_legacy, cur_legacy; 4720 struct kvm_pit *pit = kvm->arch.vpit; 4721 4722 mutex_lock(&pit->pit_state.lock); 4723 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4724 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4725 if (!prev_legacy && cur_legacy) 4726 start = 1; 4727 memcpy(&pit->pit_state.channels, &ps->channels, 4728 sizeof(pit->pit_state.channels)); 4729 pit->pit_state.flags = ps->flags; 4730 for (i = 0; i < 3; i++) 4731 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4732 start && i == 0); 4733 mutex_unlock(&pit->pit_state.lock); 4734 return 0; 4735 } 4736 4737 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4738 struct kvm_reinject_control *control) 4739 { 4740 struct kvm_pit *pit = kvm->arch.vpit; 4741 4742 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4743 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4744 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4745 */ 4746 mutex_lock(&pit->pit_state.lock); 4747 kvm_pit_set_reinject(pit, control->pit_reinject); 4748 mutex_unlock(&pit->pit_state.lock); 4749 4750 return 0; 4751 } 4752 4753 /** 4754 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 4755 * @kvm: kvm instance 4756 * @log: slot id and address to which we copy the log 4757 * 4758 * Steps 1-4 below provide general overview of dirty page logging. See 4759 * kvm_get_dirty_log_protect() function description for additional details. 4760 * 4761 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 4762 * always flush the TLB (step 4) even if previous step failed and the dirty 4763 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 4764 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 4765 * writes will be marked dirty for next log read. 4766 * 4767 * 1. Take a snapshot of the bit and clear it if needed. 4768 * 2. Write protect the corresponding page. 4769 * 3. Copy the snapshot to the userspace. 4770 * 4. Flush TLB's if needed. 4771 */ 4772 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 4773 { 4774 bool flush = false; 4775 int r; 4776 4777 mutex_lock(&kvm->slots_lock); 4778 4779 /* 4780 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4781 */ 4782 if (kvm_x86_ops->flush_log_dirty) 4783 kvm_x86_ops->flush_log_dirty(kvm); 4784 4785 r = kvm_get_dirty_log_protect(kvm, log, &flush); 4786 4787 /* 4788 * All the TLBs can be flushed out of mmu lock, see the comments in 4789 * kvm_mmu_slot_remove_write_access(). 4790 */ 4791 lockdep_assert_held(&kvm->slots_lock); 4792 if (flush) 4793 kvm_flush_remote_tlbs(kvm); 4794 4795 mutex_unlock(&kvm->slots_lock); 4796 return r; 4797 } 4798 4799 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) 4800 { 4801 bool flush = false; 4802 int r; 4803 4804 mutex_lock(&kvm->slots_lock); 4805 4806 /* 4807 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4808 */ 4809 if (kvm_x86_ops->flush_log_dirty) 4810 kvm_x86_ops->flush_log_dirty(kvm); 4811 4812 r = kvm_clear_dirty_log_protect(kvm, log, &flush); 4813 4814 /* 4815 * All the TLBs can be flushed out of mmu lock, see the comments in 4816 * kvm_mmu_slot_remove_write_access(). 4817 */ 4818 lockdep_assert_held(&kvm->slots_lock); 4819 if (flush) 4820 kvm_flush_remote_tlbs(kvm); 4821 4822 mutex_unlock(&kvm->slots_lock); 4823 return r; 4824 } 4825 4826 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4827 bool line_status) 4828 { 4829 if (!irqchip_in_kernel(kvm)) 4830 return -ENXIO; 4831 4832 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4833 irq_event->irq, irq_event->level, 4834 line_status); 4835 return 0; 4836 } 4837 4838 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4839 struct kvm_enable_cap *cap) 4840 { 4841 int r; 4842 4843 if (cap->flags) 4844 return -EINVAL; 4845 4846 switch (cap->cap) { 4847 case KVM_CAP_DISABLE_QUIRKS: 4848 kvm->arch.disabled_quirks = cap->args[0]; 4849 r = 0; 4850 break; 4851 case KVM_CAP_SPLIT_IRQCHIP: { 4852 mutex_lock(&kvm->lock); 4853 r = -EINVAL; 4854 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4855 goto split_irqchip_unlock; 4856 r = -EEXIST; 4857 if (irqchip_in_kernel(kvm)) 4858 goto split_irqchip_unlock; 4859 if (kvm->created_vcpus) 4860 goto split_irqchip_unlock; 4861 r = kvm_setup_empty_irq_routing(kvm); 4862 if (r) 4863 goto split_irqchip_unlock; 4864 /* Pairs with irqchip_in_kernel. */ 4865 smp_wmb(); 4866 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4867 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4868 r = 0; 4869 split_irqchip_unlock: 4870 mutex_unlock(&kvm->lock); 4871 break; 4872 } 4873 case KVM_CAP_X2APIC_API: 4874 r = -EINVAL; 4875 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4876 break; 4877 4878 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4879 kvm->arch.x2apic_format = true; 4880 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4881 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4882 4883 r = 0; 4884 break; 4885 case KVM_CAP_X86_DISABLE_EXITS: 4886 r = -EINVAL; 4887 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4888 break; 4889 4890 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4891 kvm_can_mwait_in_guest()) 4892 kvm->arch.mwait_in_guest = true; 4893 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 4894 kvm->arch.hlt_in_guest = true; 4895 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4896 kvm->arch.pause_in_guest = true; 4897 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 4898 kvm->arch.cstate_in_guest = true; 4899 r = 0; 4900 break; 4901 case KVM_CAP_MSR_PLATFORM_INFO: 4902 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 4903 r = 0; 4904 break; 4905 case KVM_CAP_EXCEPTION_PAYLOAD: 4906 kvm->arch.exception_payload_enabled = cap->args[0]; 4907 r = 0; 4908 break; 4909 default: 4910 r = -EINVAL; 4911 break; 4912 } 4913 return r; 4914 } 4915 4916 long kvm_arch_vm_ioctl(struct file *filp, 4917 unsigned int ioctl, unsigned long arg) 4918 { 4919 struct kvm *kvm = filp->private_data; 4920 void __user *argp = (void __user *)arg; 4921 int r = -ENOTTY; 4922 /* 4923 * This union makes it completely explicit to gcc-3.x 4924 * that these two variables' stack usage should be 4925 * combined, not added together. 4926 */ 4927 union { 4928 struct kvm_pit_state ps; 4929 struct kvm_pit_state2 ps2; 4930 struct kvm_pit_config pit_config; 4931 } u; 4932 4933 switch (ioctl) { 4934 case KVM_SET_TSS_ADDR: 4935 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4936 break; 4937 case KVM_SET_IDENTITY_MAP_ADDR: { 4938 u64 ident_addr; 4939 4940 mutex_lock(&kvm->lock); 4941 r = -EINVAL; 4942 if (kvm->created_vcpus) 4943 goto set_identity_unlock; 4944 r = -EFAULT; 4945 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 4946 goto set_identity_unlock; 4947 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4948 set_identity_unlock: 4949 mutex_unlock(&kvm->lock); 4950 break; 4951 } 4952 case KVM_SET_NR_MMU_PAGES: 4953 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4954 break; 4955 case KVM_GET_NR_MMU_PAGES: 4956 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4957 break; 4958 case KVM_CREATE_IRQCHIP: { 4959 mutex_lock(&kvm->lock); 4960 4961 r = -EEXIST; 4962 if (irqchip_in_kernel(kvm)) 4963 goto create_irqchip_unlock; 4964 4965 r = -EINVAL; 4966 if (kvm->created_vcpus) 4967 goto create_irqchip_unlock; 4968 4969 r = kvm_pic_init(kvm); 4970 if (r) 4971 goto create_irqchip_unlock; 4972 4973 r = kvm_ioapic_init(kvm); 4974 if (r) { 4975 kvm_pic_destroy(kvm); 4976 goto create_irqchip_unlock; 4977 } 4978 4979 r = kvm_setup_default_irq_routing(kvm); 4980 if (r) { 4981 kvm_ioapic_destroy(kvm); 4982 kvm_pic_destroy(kvm); 4983 goto create_irqchip_unlock; 4984 } 4985 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4986 smp_wmb(); 4987 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4988 create_irqchip_unlock: 4989 mutex_unlock(&kvm->lock); 4990 break; 4991 } 4992 case KVM_CREATE_PIT: 4993 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4994 goto create_pit; 4995 case KVM_CREATE_PIT2: 4996 r = -EFAULT; 4997 if (copy_from_user(&u.pit_config, argp, 4998 sizeof(struct kvm_pit_config))) 4999 goto out; 5000 create_pit: 5001 mutex_lock(&kvm->lock); 5002 r = -EEXIST; 5003 if (kvm->arch.vpit) 5004 goto create_pit_unlock; 5005 r = -ENOMEM; 5006 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 5007 if (kvm->arch.vpit) 5008 r = 0; 5009 create_pit_unlock: 5010 mutex_unlock(&kvm->lock); 5011 break; 5012 case KVM_GET_IRQCHIP: { 5013 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5014 struct kvm_irqchip *chip; 5015 5016 chip = memdup_user(argp, sizeof(*chip)); 5017 if (IS_ERR(chip)) { 5018 r = PTR_ERR(chip); 5019 goto out; 5020 } 5021 5022 r = -ENXIO; 5023 if (!irqchip_kernel(kvm)) 5024 goto get_irqchip_out; 5025 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5026 if (r) 5027 goto get_irqchip_out; 5028 r = -EFAULT; 5029 if (copy_to_user(argp, chip, sizeof(*chip))) 5030 goto get_irqchip_out; 5031 r = 0; 5032 get_irqchip_out: 5033 kfree(chip); 5034 break; 5035 } 5036 case KVM_SET_IRQCHIP: { 5037 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5038 struct kvm_irqchip *chip; 5039 5040 chip = memdup_user(argp, sizeof(*chip)); 5041 if (IS_ERR(chip)) { 5042 r = PTR_ERR(chip); 5043 goto out; 5044 } 5045 5046 r = -ENXIO; 5047 if (!irqchip_kernel(kvm)) 5048 goto set_irqchip_out; 5049 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5050 set_irqchip_out: 5051 kfree(chip); 5052 break; 5053 } 5054 case KVM_GET_PIT: { 5055 r = -EFAULT; 5056 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5057 goto out; 5058 r = -ENXIO; 5059 if (!kvm->arch.vpit) 5060 goto out; 5061 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5062 if (r) 5063 goto out; 5064 r = -EFAULT; 5065 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5066 goto out; 5067 r = 0; 5068 break; 5069 } 5070 case KVM_SET_PIT: { 5071 r = -EFAULT; 5072 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5073 goto out; 5074 r = -ENXIO; 5075 if (!kvm->arch.vpit) 5076 goto out; 5077 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5078 break; 5079 } 5080 case KVM_GET_PIT2: { 5081 r = -ENXIO; 5082 if (!kvm->arch.vpit) 5083 goto out; 5084 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5085 if (r) 5086 goto out; 5087 r = -EFAULT; 5088 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5089 goto out; 5090 r = 0; 5091 break; 5092 } 5093 case KVM_SET_PIT2: { 5094 r = -EFAULT; 5095 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5096 goto out; 5097 r = -ENXIO; 5098 if (!kvm->arch.vpit) 5099 goto out; 5100 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5101 break; 5102 } 5103 case KVM_REINJECT_CONTROL: { 5104 struct kvm_reinject_control control; 5105 r = -EFAULT; 5106 if (copy_from_user(&control, argp, sizeof(control))) 5107 goto out; 5108 r = -ENXIO; 5109 if (!kvm->arch.vpit) 5110 goto out; 5111 r = kvm_vm_ioctl_reinject(kvm, &control); 5112 break; 5113 } 5114 case KVM_SET_BOOT_CPU_ID: 5115 r = 0; 5116 mutex_lock(&kvm->lock); 5117 if (kvm->created_vcpus) 5118 r = -EBUSY; 5119 else 5120 kvm->arch.bsp_vcpu_id = arg; 5121 mutex_unlock(&kvm->lock); 5122 break; 5123 case KVM_XEN_HVM_CONFIG: { 5124 struct kvm_xen_hvm_config xhc; 5125 r = -EFAULT; 5126 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5127 goto out; 5128 r = -EINVAL; 5129 if (xhc.flags) 5130 goto out; 5131 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 5132 r = 0; 5133 break; 5134 } 5135 case KVM_SET_CLOCK: { 5136 struct kvm_clock_data user_ns; 5137 u64 now_ns; 5138 5139 r = -EFAULT; 5140 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5141 goto out; 5142 5143 r = -EINVAL; 5144 if (user_ns.flags) 5145 goto out; 5146 5147 r = 0; 5148 /* 5149 * TODO: userspace has to take care of races with VCPU_RUN, so 5150 * kvm_gen_update_masterclock() can be cut down to locked 5151 * pvclock_update_vm_gtod_copy(). 5152 */ 5153 kvm_gen_update_masterclock(kvm); 5154 now_ns = get_kvmclock_ns(kvm); 5155 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 5156 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5157 break; 5158 } 5159 case KVM_GET_CLOCK: { 5160 struct kvm_clock_data user_ns; 5161 u64 now_ns; 5162 5163 now_ns = get_kvmclock_ns(kvm); 5164 user_ns.clock = now_ns; 5165 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 5166 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 5167 5168 r = -EFAULT; 5169 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 5170 goto out; 5171 r = 0; 5172 break; 5173 } 5174 case KVM_MEMORY_ENCRYPT_OP: { 5175 r = -ENOTTY; 5176 if (kvm_x86_ops->mem_enc_op) 5177 r = kvm_x86_ops->mem_enc_op(kvm, argp); 5178 break; 5179 } 5180 case KVM_MEMORY_ENCRYPT_REG_REGION: { 5181 struct kvm_enc_region region; 5182 5183 r = -EFAULT; 5184 if (copy_from_user(®ion, argp, sizeof(region))) 5185 goto out; 5186 5187 r = -ENOTTY; 5188 if (kvm_x86_ops->mem_enc_reg_region) 5189 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); 5190 break; 5191 } 5192 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 5193 struct kvm_enc_region region; 5194 5195 r = -EFAULT; 5196 if (copy_from_user(®ion, argp, sizeof(region))) 5197 goto out; 5198 5199 r = -ENOTTY; 5200 if (kvm_x86_ops->mem_enc_unreg_region) 5201 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); 5202 break; 5203 } 5204 case KVM_HYPERV_EVENTFD: { 5205 struct kvm_hyperv_eventfd hvevfd; 5206 5207 r = -EFAULT; 5208 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 5209 goto out; 5210 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 5211 break; 5212 } 5213 case KVM_SET_PMU_EVENT_FILTER: 5214 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 5215 break; 5216 default: 5217 r = -ENOTTY; 5218 } 5219 out: 5220 return r; 5221 } 5222 5223 static void kvm_init_msr_list(void) 5224 { 5225 struct x86_pmu_capability x86_pmu; 5226 u32 dummy[2]; 5227 unsigned i; 5228 5229 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 5230 "Please update the fixed PMCs in msrs_to_saved_all[]"); 5231 5232 perf_get_x86_pmu_capability(&x86_pmu); 5233 5234 num_msrs_to_save = 0; 5235 num_emulated_msrs = 0; 5236 num_msr_based_features = 0; 5237 5238 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 5239 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 5240 continue; 5241 5242 /* 5243 * Even MSRs that are valid in the host may not be exposed 5244 * to the guests in some cases. 5245 */ 5246 switch (msrs_to_save_all[i]) { 5247 case MSR_IA32_BNDCFGS: 5248 if (!kvm_mpx_supported()) 5249 continue; 5250 break; 5251 case MSR_TSC_AUX: 5252 if (!kvm_x86_ops->rdtscp_supported()) 5253 continue; 5254 break; 5255 case MSR_IA32_RTIT_CTL: 5256 case MSR_IA32_RTIT_STATUS: 5257 if (!kvm_x86_ops->pt_supported()) 5258 continue; 5259 break; 5260 case MSR_IA32_RTIT_CR3_MATCH: 5261 if (!kvm_x86_ops->pt_supported() || 5262 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 5263 continue; 5264 break; 5265 case MSR_IA32_RTIT_OUTPUT_BASE: 5266 case MSR_IA32_RTIT_OUTPUT_MASK: 5267 if (!kvm_x86_ops->pt_supported() || 5268 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 5269 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 5270 continue; 5271 break; 5272 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { 5273 if (!kvm_x86_ops->pt_supported() || 5274 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 5275 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 5276 continue; 5277 break; 5278 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 5279 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 5280 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5281 continue; 5282 break; 5283 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 5284 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 5285 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5286 continue; 5287 } 5288 default: 5289 break; 5290 } 5291 5292 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 5293 } 5294 5295 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 5296 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i])) 5297 continue; 5298 5299 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 5300 } 5301 5302 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 5303 struct kvm_msr_entry msr; 5304 5305 msr.index = msr_based_features_all[i]; 5306 if (kvm_get_msr_feature(&msr)) 5307 continue; 5308 5309 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 5310 } 5311 } 5312 5313 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 5314 const void *v) 5315 { 5316 int handled = 0; 5317 int n; 5318 5319 do { 5320 n = min(len, 8); 5321 if (!(lapic_in_kernel(vcpu) && 5322 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 5323 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 5324 break; 5325 handled += n; 5326 addr += n; 5327 len -= n; 5328 v += n; 5329 } while (len); 5330 5331 return handled; 5332 } 5333 5334 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 5335 { 5336 int handled = 0; 5337 int n; 5338 5339 do { 5340 n = min(len, 8); 5341 if (!(lapic_in_kernel(vcpu) && 5342 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5343 addr, n, v)) 5344 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5345 break; 5346 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5347 handled += n; 5348 addr += n; 5349 len -= n; 5350 v += n; 5351 } while (len); 5352 5353 return handled; 5354 } 5355 5356 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5357 struct kvm_segment *var, int seg) 5358 { 5359 kvm_x86_ops->set_segment(vcpu, var, seg); 5360 } 5361 5362 void kvm_get_segment(struct kvm_vcpu *vcpu, 5363 struct kvm_segment *var, int seg) 5364 { 5365 kvm_x86_ops->get_segment(vcpu, var, seg); 5366 } 5367 5368 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5369 struct x86_exception *exception) 5370 { 5371 gpa_t t_gpa; 5372 5373 BUG_ON(!mmu_is_nested(vcpu)); 5374 5375 /* NPT walks are always user-walks */ 5376 access |= PFERR_USER_MASK; 5377 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5378 5379 return t_gpa; 5380 } 5381 5382 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5383 struct x86_exception *exception) 5384 { 5385 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5386 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5387 } 5388 5389 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 5390 struct x86_exception *exception) 5391 { 5392 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5393 access |= PFERR_FETCH_MASK; 5394 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5395 } 5396 5397 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 5398 struct x86_exception *exception) 5399 { 5400 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5401 access |= PFERR_WRITE_MASK; 5402 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5403 } 5404 5405 /* uses this to access any guest's mapped memory without checking CPL */ 5406 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 5407 struct x86_exception *exception) 5408 { 5409 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 5410 } 5411 5412 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5413 struct kvm_vcpu *vcpu, u32 access, 5414 struct x86_exception *exception) 5415 { 5416 void *data = val; 5417 int r = X86EMUL_CONTINUE; 5418 5419 while (bytes) { 5420 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 5421 exception); 5422 unsigned offset = addr & (PAGE_SIZE-1); 5423 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 5424 int ret; 5425 5426 if (gpa == UNMAPPED_GVA) 5427 return X86EMUL_PROPAGATE_FAULT; 5428 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 5429 offset, toread); 5430 if (ret < 0) { 5431 r = X86EMUL_IO_NEEDED; 5432 goto out; 5433 } 5434 5435 bytes -= toread; 5436 data += toread; 5437 addr += toread; 5438 } 5439 out: 5440 return r; 5441 } 5442 5443 /* used for instruction fetching */ 5444 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 5445 gva_t addr, void *val, unsigned int bytes, 5446 struct x86_exception *exception) 5447 { 5448 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5449 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5450 unsigned offset; 5451 int ret; 5452 5453 /* Inline kvm_read_guest_virt_helper for speed. */ 5454 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 5455 exception); 5456 if (unlikely(gpa == UNMAPPED_GVA)) 5457 return X86EMUL_PROPAGATE_FAULT; 5458 5459 offset = addr & (PAGE_SIZE-1); 5460 if (WARN_ON(offset + bytes > PAGE_SIZE)) 5461 bytes = (unsigned)PAGE_SIZE - offset; 5462 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 5463 offset, bytes); 5464 if (unlikely(ret < 0)) 5465 return X86EMUL_IO_NEEDED; 5466 5467 return X86EMUL_CONTINUE; 5468 } 5469 5470 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 5471 gva_t addr, void *val, unsigned int bytes, 5472 struct x86_exception *exception) 5473 { 5474 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5475 5476 /* 5477 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5478 * is returned, but our callers are not ready for that and they blindly 5479 * call kvm_inject_page_fault. Ensure that they at least do not leak 5480 * uninitialized kernel stack memory into cr2 and error code. 5481 */ 5482 memset(exception, 0, sizeof(*exception)); 5483 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 5484 exception); 5485 } 5486 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 5487 5488 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 5489 gva_t addr, void *val, unsigned int bytes, 5490 struct x86_exception *exception, bool system) 5491 { 5492 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5493 u32 access = 0; 5494 5495 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) 5496 access |= PFERR_USER_MASK; 5497 5498 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 5499 } 5500 5501 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 5502 unsigned long addr, void *val, unsigned int bytes) 5503 { 5504 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5505 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 5506 5507 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 5508 } 5509 5510 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5511 struct kvm_vcpu *vcpu, u32 access, 5512 struct x86_exception *exception) 5513 { 5514 void *data = val; 5515 int r = X86EMUL_CONTINUE; 5516 5517 while (bytes) { 5518 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 5519 access, 5520 exception); 5521 unsigned offset = addr & (PAGE_SIZE-1); 5522 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 5523 int ret; 5524 5525 if (gpa == UNMAPPED_GVA) 5526 return X86EMUL_PROPAGATE_FAULT; 5527 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 5528 if (ret < 0) { 5529 r = X86EMUL_IO_NEEDED; 5530 goto out; 5531 } 5532 5533 bytes -= towrite; 5534 data += towrite; 5535 addr += towrite; 5536 } 5537 out: 5538 return r; 5539 } 5540 5541 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 5542 unsigned int bytes, struct x86_exception *exception, 5543 bool system) 5544 { 5545 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5546 u32 access = PFERR_WRITE_MASK; 5547 5548 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) 5549 access |= PFERR_USER_MASK; 5550 5551 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5552 access, exception); 5553 } 5554 5555 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 5556 unsigned int bytes, struct x86_exception *exception) 5557 { 5558 /* kvm_write_guest_virt_system can pull in tons of pages. */ 5559 vcpu->arch.l1tf_flush_l1d = true; 5560 5561 /* 5562 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5563 * is returned, but our callers are not ready for that and they blindly 5564 * call kvm_inject_page_fault. Ensure that they at least do not leak 5565 * uninitialized kernel stack memory into cr2 and error code. 5566 */ 5567 memset(exception, 0, sizeof(*exception)); 5568 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5569 PFERR_WRITE_MASK, exception); 5570 } 5571 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 5572 5573 int handle_ud(struct kvm_vcpu *vcpu) 5574 { 5575 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 5576 int emul_type = EMULTYPE_TRAP_UD; 5577 char sig[5]; /* ud2; .ascii "kvm" */ 5578 struct x86_exception e; 5579 5580 if (force_emulation_prefix && 5581 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 5582 sig, sizeof(sig), &e) == 0 && 5583 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 5584 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 5585 emul_type = EMULTYPE_TRAP_UD_FORCED; 5586 } 5587 5588 return kvm_emulate_instruction(vcpu, emul_type); 5589 } 5590 EXPORT_SYMBOL_GPL(handle_ud); 5591 5592 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5593 gpa_t gpa, bool write) 5594 { 5595 /* For APIC access vmexit */ 5596 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5597 return 1; 5598 5599 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 5600 trace_vcpu_match_mmio(gva, gpa, write, true); 5601 return 1; 5602 } 5603 5604 return 0; 5605 } 5606 5607 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5608 gpa_t *gpa, struct x86_exception *exception, 5609 bool write) 5610 { 5611 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 5612 | (write ? PFERR_WRITE_MASK : 0); 5613 5614 /* 5615 * currently PKRU is only applied to ept enabled guest so 5616 * there is no pkey in EPT page table for L1 guest or EPT 5617 * shadow page table for L2 guest. 5618 */ 5619 if (vcpu_match_mmio_gva(vcpu, gva) 5620 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 5621 vcpu->arch.mmio_access, 0, access)) { 5622 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 5623 (gva & (PAGE_SIZE - 1)); 5624 trace_vcpu_match_mmio(gva, *gpa, write, false); 5625 return 1; 5626 } 5627 5628 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5629 5630 if (*gpa == UNMAPPED_GVA) 5631 return -1; 5632 5633 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 5634 } 5635 5636 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 5637 const void *val, int bytes) 5638 { 5639 int ret; 5640 5641 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 5642 if (ret < 0) 5643 return 0; 5644 kvm_page_track_write(vcpu, gpa, val, bytes); 5645 return 1; 5646 } 5647 5648 struct read_write_emulator_ops { 5649 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 5650 int bytes); 5651 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 5652 void *val, int bytes); 5653 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5654 int bytes, void *val); 5655 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5656 void *val, int bytes); 5657 bool write; 5658 }; 5659 5660 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 5661 { 5662 if (vcpu->mmio_read_completed) { 5663 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 5664 vcpu->mmio_fragments[0].gpa, val); 5665 vcpu->mmio_read_completed = 0; 5666 return 1; 5667 } 5668 5669 return 0; 5670 } 5671 5672 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5673 void *val, int bytes) 5674 { 5675 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 5676 } 5677 5678 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5679 void *val, int bytes) 5680 { 5681 return emulator_write_phys(vcpu, gpa, val, bytes); 5682 } 5683 5684 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 5685 { 5686 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 5687 return vcpu_mmio_write(vcpu, gpa, bytes, val); 5688 } 5689 5690 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5691 void *val, int bytes) 5692 { 5693 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 5694 return X86EMUL_IO_NEEDED; 5695 } 5696 5697 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5698 void *val, int bytes) 5699 { 5700 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 5701 5702 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 5703 return X86EMUL_CONTINUE; 5704 } 5705 5706 static const struct read_write_emulator_ops read_emultor = { 5707 .read_write_prepare = read_prepare, 5708 .read_write_emulate = read_emulate, 5709 .read_write_mmio = vcpu_mmio_read, 5710 .read_write_exit_mmio = read_exit_mmio, 5711 }; 5712 5713 static const struct read_write_emulator_ops write_emultor = { 5714 .read_write_emulate = write_emulate, 5715 .read_write_mmio = write_mmio, 5716 .read_write_exit_mmio = write_exit_mmio, 5717 .write = true, 5718 }; 5719 5720 static int emulator_read_write_onepage(unsigned long addr, void *val, 5721 unsigned int bytes, 5722 struct x86_exception *exception, 5723 struct kvm_vcpu *vcpu, 5724 const struct read_write_emulator_ops *ops) 5725 { 5726 gpa_t gpa; 5727 int handled, ret; 5728 bool write = ops->write; 5729 struct kvm_mmio_fragment *frag; 5730 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5731 5732 /* 5733 * If the exit was due to a NPF we may already have a GPA. 5734 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5735 * Note, this cannot be used on string operations since string 5736 * operation using rep will only have the initial GPA from the NPF 5737 * occurred. 5738 */ 5739 if (vcpu->arch.gpa_available && 5740 emulator_can_use_gpa(ctxt) && 5741 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 5742 gpa = vcpu->arch.gpa_val; 5743 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5744 } else { 5745 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5746 if (ret < 0) 5747 return X86EMUL_PROPAGATE_FAULT; 5748 } 5749 5750 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5751 return X86EMUL_CONTINUE; 5752 5753 /* 5754 * Is this MMIO handled locally? 5755 */ 5756 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5757 if (handled == bytes) 5758 return X86EMUL_CONTINUE; 5759 5760 gpa += handled; 5761 bytes -= handled; 5762 val += handled; 5763 5764 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5765 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5766 frag->gpa = gpa; 5767 frag->data = val; 5768 frag->len = bytes; 5769 return X86EMUL_CONTINUE; 5770 } 5771 5772 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5773 unsigned long addr, 5774 void *val, unsigned int bytes, 5775 struct x86_exception *exception, 5776 const struct read_write_emulator_ops *ops) 5777 { 5778 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5779 gpa_t gpa; 5780 int rc; 5781 5782 if (ops->read_write_prepare && 5783 ops->read_write_prepare(vcpu, val, bytes)) 5784 return X86EMUL_CONTINUE; 5785 5786 vcpu->mmio_nr_fragments = 0; 5787 5788 /* Crossing a page boundary? */ 5789 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5790 int now; 5791 5792 now = -addr & ~PAGE_MASK; 5793 rc = emulator_read_write_onepage(addr, val, now, exception, 5794 vcpu, ops); 5795 5796 if (rc != X86EMUL_CONTINUE) 5797 return rc; 5798 addr += now; 5799 if (ctxt->mode != X86EMUL_MODE_PROT64) 5800 addr = (u32)addr; 5801 val += now; 5802 bytes -= now; 5803 } 5804 5805 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5806 vcpu, ops); 5807 if (rc != X86EMUL_CONTINUE) 5808 return rc; 5809 5810 if (!vcpu->mmio_nr_fragments) 5811 return rc; 5812 5813 gpa = vcpu->mmio_fragments[0].gpa; 5814 5815 vcpu->mmio_needed = 1; 5816 vcpu->mmio_cur_fragment = 0; 5817 5818 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5819 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5820 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5821 vcpu->run->mmio.phys_addr = gpa; 5822 5823 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5824 } 5825 5826 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5827 unsigned long addr, 5828 void *val, 5829 unsigned int bytes, 5830 struct x86_exception *exception) 5831 { 5832 return emulator_read_write(ctxt, addr, val, bytes, 5833 exception, &read_emultor); 5834 } 5835 5836 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5837 unsigned long addr, 5838 const void *val, 5839 unsigned int bytes, 5840 struct x86_exception *exception) 5841 { 5842 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5843 exception, &write_emultor); 5844 } 5845 5846 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5847 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5848 5849 #ifdef CONFIG_X86_64 5850 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5851 #else 5852 # define CMPXCHG64(ptr, old, new) \ 5853 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5854 #endif 5855 5856 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5857 unsigned long addr, 5858 const void *old, 5859 const void *new, 5860 unsigned int bytes, 5861 struct x86_exception *exception) 5862 { 5863 struct kvm_host_map map; 5864 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5865 gpa_t gpa; 5866 char *kaddr; 5867 bool exchanged; 5868 5869 /* guests cmpxchg8b have to be emulated atomically */ 5870 if (bytes > 8 || (bytes & (bytes - 1))) 5871 goto emul_write; 5872 5873 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5874 5875 if (gpa == UNMAPPED_GVA || 5876 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5877 goto emul_write; 5878 5879 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 5880 goto emul_write; 5881 5882 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 5883 goto emul_write; 5884 5885 kaddr = map.hva + offset_in_page(gpa); 5886 5887 switch (bytes) { 5888 case 1: 5889 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5890 break; 5891 case 2: 5892 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5893 break; 5894 case 4: 5895 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5896 break; 5897 case 8: 5898 exchanged = CMPXCHG64(kaddr, old, new); 5899 break; 5900 default: 5901 BUG(); 5902 } 5903 5904 kvm_vcpu_unmap(vcpu, &map, true); 5905 5906 if (!exchanged) 5907 return X86EMUL_CMPXCHG_FAILED; 5908 5909 kvm_page_track_write(vcpu, gpa, new, bytes); 5910 5911 return X86EMUL_CONTINUE; 5912 5913 emul_write: 5914 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5915 5916 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5917 } 5918 5919 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5920 { 5921 int r = 0, i; 5922 5923 for (i = 0; i < vcpu->arch.pio.count; i++) { 5924 if (vcpu->arch.pio.in) 5925 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5926 vcpu->arch.pio.size, pd); 5927 else 5928 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5929 vcpu->arch.pio.port, vcpu->arch.pio.size, 5930 pd); 5931 if (r) 5932 break; 5933 pd += vcpu->arch.pio.size; 5934 } 5935 return r; 5936 } 5937 5938 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5939 unsigned short port, void *val, 5940 unsigned int count, bool in) 5941 { 5942 vcpu->arch.pio.port = port; 5943 vcpu->arch.pio.in = in; 5944 vcpu->arch.pio.count = count; 5945 vcpu->arch.pio.size = size; 5946 5947 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5948 vcpu->arch.pio.count = 0; 5949 return 1; 5950 } 5951 5952 vcpu->run->exit_reason = KVM_EXIT_IO; 5953 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5954 vcpu->run->io.size = size; 5955 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5956 vcpu->run->io.count = count; 5957 vcpu->run->io.port = port; 5958 5959 return 0; 5960 } 5961 5962 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5963 int size, unsigned short port, void *val, 5964 unsigned int count) 5965 { 5966 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5967 int ret; 5968 5969 if (vcpu->arch.pio.count) 5970 goto data_avail; 5971 5972 memset(vcpu->arch.pio_data, 0, size * count); 5973 5974 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5975 if (ret) { 5976 data_avail: 5977 memcpy(val, vcpu->arch.pio_data, size * count); 5978 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5979 vcpu->arch.pio.count = 0; 5980 return 1; 5981 } 5982 5983 return 0; 5984 } 5985 5986 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5987 int size, unsigned short port, 5988 const void *val, unsigned int count) 5989 { 5990 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5991 5992 memcpy(vcpu->arch.pio_data, val, size * count); 5993 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5994 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5995 } 5996 5997 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5998 { 5999 return kvm_x86_ops->get_segment_base(vcpu, seg); 6000 } 6001 6002 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6003 { 6004 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6005 } 6006 6007 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6008 { 6009 if (!need_emulate_wbinvd(vcpu)) 6010 return X86EMUL_CONTINUE; 6011 6012 if (kvm_x86_ops->has_wbinvd_exit()) { 6013 int cpu = get_cpu(); 6014 6015 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6016 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 6017 wbinvd_ipi, NULL, 1); 6018 put_cpu(); 6019 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6020 } else 6021 wbinvd(); 6022 return X86EMUL_CONTINUE; 6023 } 6024 6025 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6026 { 6027 kvm_emulate_wbinvd_noskip(vcpu); 6028 return kvm_skip_emulated_instruction(vcpu); 6029 } 6030 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6031 6032 6033 6034 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6035 { 6036 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6037 } 6038 6039 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6040 unsigned long *dest) 6041 { 6042 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6043 } 6044 6045 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6046 unsigned long value) 6047 { 6048 6049 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6050 } 6051 6052 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6053 { 6054 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6055 } 6056 6057 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6058 { 6059 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6060 unsigned long value; 6061 6062 switch (cr) { 6063 case 0: 6064 value = kvm_read_cr0(vcpu); 6065 break; 6066 case 2: 6067 value = vcpu->arch.cr2; 6068 break; 6069 case 3: 6070 value = kvm_read_cr3(vcpu); 6071 break; 6072 case 4: 6073 value = kvm_read_cr4(vcpu); 6074 break; 6075 case 8: 6076 value = kvm_get_cr8(vcpu); 6077 break; 6078 default: 6079 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6080 return 0; 6081 } 6082 6083 return value; 6084 } 6085 6086 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6087 { 6088 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6089 int res = 0; 6090 6091 switch (cr) { 6092 case 0: 6093 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6094 break; 6095 case 2: 6096 vcpu->arch.cr2 = val; 6097 break; 6098 case 3: 6099 res = kvm_set_cr3(vcpu, val); 6100 break; 6101 case 4: 6102 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6103 break; 6104 case 8: 6105 res = kvm_set_cr8(vcpu, val); 6106 break; 6107 default: 6108 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6109 res = -1; 6110 } 6111 6112 return res; 6113 } 6114 6115 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6116 { 6117 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 6118 } 6119 6120 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6121 { 6122 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 6123 } 6124 6125 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6126 { 6127 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 6128 } 6129 6130 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6131 { 6132 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 6133 } 6134 6135 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6136 { 6137 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 6138 } 6139 6140 static unsigned long emulator_get_cached_segment_base( 6141 struct x86_emulate_ctxt *ctxt, int seg) 6142 { 6143 return get_segment_base(emul_to_vcpu(ctxt), seg); 6144 } 6145 6146 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 6147 struct desc_struct *desc, u32 *base3, 6148 int seg) 6149 { 6150 struct kvm_segment var; 6151 6152 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 6153 *selector = var.selector; 6154 6155 if (var.unusable) { 6156 memset(desc, 0, sizeof(*desc)); 6157 if (base3) 6158 *base3 = 0; 6159 return false; 6160 } 6161 6162 if (var.g) 6163 var.limit >>= 12; 6164 set_desc_limit(desc, var.limit); 6165 set_desc_base(desc, (unsigned long)var.base); 6166 #ifdef CONFIG_X86_64 6167 if (base3) 6168 *base3 = var.base >> 32; 6169 #endif 6170 desc->type = var.type; 6171 desc->s = var.s; 6172 desc->dpl = var.dpl; 6173 desc->p = var.present; 6174 desc->avl = var.avl; 6175 desc->l = var.l; 6176 desc->d = var.db; 6177 desc->g = var.g; 6178 6179 return true; 6180 } 6181 6182 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 6183 struct desc_struct *desc, u32 base3, 6184 int seg) 6185 { 6186 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6187 struct kvm_segment var; 6188 6189 var.selector = selector; 6190 var.base = get_desc_base(desc); 6191 #ifdef CONFIG_X86_64 6192 var.base |= ((u64)base3) << 32; 6193 #endif 6194 var.limit = get_desc_limit(desc); 6195 if (desc->g) 6196 var.limit = (var.limit << 12) | 0xfff; 6197 var.type = desc->type; 6198 var.dpl = desc->dpl; 6199 var.db = desc->d; 6200 var.s = desc->s; 6201 var.l = desc->l; 6202 var.g = desc->g; 6203 var.avl = desc->avl; 6204 var.present = desc->p; 6205 var.unusable = !var.present; 6206 var.padding = 0; 6207 6208 kvm_set_segment(vcpu, &var, seg); 6209 return; 6210 } 6211 6212 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 6213 u32 msr_index, u64 *pdata) 6214 { 6215 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 6216 } 6217 6218 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 6219 u32 msr_index, u64 data) 6220 { 6221 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); 6222 } 6223 6224 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 6225 { 6226 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6227 6228 return vcpu->arch.smbase; 6229 } 6230 6231 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 6232 { 6233 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6234 6235 vcpu->arch.smbase = smbase; 6236 } 6237 6238 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 6239 u32 pmc) 6240 { 6241 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 6242 } 6243 6244 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 6245 u32 pmc, u64 *pdata) 6246 { 6247 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 6248 } 6249 6250 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 6251 { 6252 emul_to_vcpu(ctxt)->arch.halt_request = 1; 6253 } 6254 6255 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 6256 struct x86_instruction_info *info, 6257 enum x86_intercept_stage stage) 6258 { 6259 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 6260 } 6261 6262 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 6263 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 6264 { 6265 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 6266 } 6267 6268 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 6269 { 6270 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 6271 } 6272 6273 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 6274 { 6275 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 6276 } 6277 6278 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 6279 { 6280 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 6281 } 6282 6283 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 6284 { 6285 return kvm_register_read(emul_to_vcpu(ctxt), reg); 6286 } 6287 6288 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 6289 { 6290 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 6291 } 6292 6293 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 6294 { 6295 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 6296 } 6297 6298 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 6299 { 6300 return emul_to_vcpu(ctxt)->arch.hflags; 6301 } 6302 6303 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 6304 { 6305 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 6306 } 6307 6308 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 6309 const char *smstate) 6310 { 6311 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate); 6312 } 6313 6314 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 6315 { 6316 kvm_smm_changed(emul_to_vcpu(ctxt)); 6317 } 6318 6319 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 6320 { 6321 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 6322 } 6323 6324 static const struct x86_emulate_ops emulate_ops = { 6325 .read_gpr = emulator_read_gpr, 6326 .write_gpr = emulator_write_gpr, 6327 .read_std = emulator_read_std, 6328 .write_std = emulator_write_std, 6329 .read_phys = kvm_read_guest_phys_system, 6330 .fetch = kvm_fetch_guest_virt, 6331 .read_emulated = emulator_read_emulated, 6332 .write_emulated = emulator_write_emulated, 6333 .cmpxchg_emulated = emulator_cmpxchg_emulated, 6334 .invlpg = emulator_invlpg, 6335 .pio_in_emulated = emulator_pio_in_emulated, 6336 .pio_out_emulated = emulator_pio_out_emulated, 6337 .get_segment = emulator_get_segment, 6338 .set_segment = emulator_set_segment, 6339 .get_cached_segment_base = emulator_get_cached_segment_base, 6340 .get_gdt = emulator_get_gdt, 6341 .get_idt = emulator_get_idt, 6342 .set_gdt = emulator_set_gdt, 6343 .set_idt = emulator_set_idt, 6344 .get_cr = emulator_get_cr, 6345 .set_cr = emulator_set_cr, 6346 .cpl = emulator_get_cpl, 6347 .get_dr = emulator_get_dr, 6348 .set_dr = emulator_set_dr, 6349 .get_smbase = emulator_get_smbase, 6350 .set_smbase = emulator_set_smbase, 6351 .set_msr = emulator_set_msr, 6352 .get_msr = emulator_get_msr, 6353 .check_pmc = emulator_check_pmc, 6354 .read_pmc = emulator_read_pmc, 6355 .halt = emulator_halt, 6356 .wbinvd = emulator_wbinvd, 6357 .fix_hypercall = emulator_fix_hypercall, 6358 .intercept = emulator_intercept, 6359 .get_cpuid = emulator_get_cpuid, 6360 .guest_has_long_mode = emulator_guest_has_long_mode, 6361 .guest_has_movbe = emulator_guest_has_movbe, 6362 .guest_has_fxsr = emulator_guest_has_fxsr, 6363 .set_nmi_mask = emulator_set_nmi_mask, 6364 .get_hflags = emulator_get_hflags, 6365 .set_hflags = emulator_set_hflags, 6366 .pre_leave_smm = emulator_pre_leave_smm, 6367 .post_leave_smm = emulator_post_leave_smm, 6368 .set_xcr = emulator_set_xcr, 6369 }; 6370 6371 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 6372 { 6373 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 6374 /* 6375 * an sti; sti; sequence only disable interrupts for the first 6376 * instruction. So, if the last instruction, be it emulated or 6377 * not, left the system with the INT_STI flag enabled, it 6378 * means that the last instruction is an sti. We should not 6379 * leave the flag on in this case. The same goes for mov ss 6380 */ 6381 if (int_shadow & mask) 6382 mask = 0; 6383 if (unlikely(int_shadow || mask)) { 6384 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 6385 if (!mask) 6386 kvm_make_request(KVM_REQ_EVENT, vcpu); 6387 } 6388 } 6389 6390 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 6391 { 6392 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6393 if (ctxt->exception.vector == PF_VECTOR) 6394 return kvm_propagate_fault(vcpu, &ctxt->exception); 6395 6396 if (ctxt->exception.error_code_valid) 6397 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 6398 ctxt->exception.error_code); 6399 else 6400 kvm_queue_exception(vcpu, ctxt->exception.vector); 6401 return false; 6402 } 6403 6404 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 6405 { 6406 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6407 int cs_db, cs_l; 6408 6409 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 6410 6411 ctxt->eflags = kvm_get_rflags(vcpu); 6412 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 6413 6414 ctxt->eip = kvm_rip_read(vcpu); 6415 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 6416 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 6417 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 6418 cs_db ? X86EMUL_MODE_PROT32 : 6419 X86EMUL_MODE_PROT16; 6420 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 6421 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 6422 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 6423 6424 init_decode_cache(ctxt); 6425 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6426 } 6427 6428 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 6429 { 6430 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6431 int ret; 6432 6433 init_emulate_ctxt(vcpu); 6434 6435 ctxt->op_bytes = 2; 6436 ctxt->ad_bytes = 2; 6437 ctxt->_eip = ctxt->eip + inc_eip; 6438 ret = emulate_int_real(ctxt, irq); 6439 6440 if (ret != X86EMUL_CONTINUE) { 6441 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 6442 } else { 6443 ctxt->eip = ctxt->_eip; 6444 kvm_rip_write(vcpu, ctxt->eip); 6445 kvm_set_rflags(vcpu, ctxt->eflags); 6446 } 6447 } 6448 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 6449 6450 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 6451 { 6452 ++vcpu->stat.insn_emulation_fail; 6453 trace_kvm_emulate_insn_failed(vcpu); 6454 6455 if (emulation_type & EMULTYPE_VMWARE_GP) { 6456 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 6457 return 1; 6458 } 6459 6460 if (emulation_type & EMULTYPE_SKIP) { 6461 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6462 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6463 vcpu->run->internal.ndata = 0; 6464 return 0; 6465 } 6466 6467 kvm_queue_exception(vcpu, UD_VECTOR); 6468 6469 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 6470 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6471 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6472 vcpu->run->internal.ndata = 0; 6473 return 0; 6474 } 6475 6476 return 1; 6477 } 6478 6479 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 6480 bool write_fault_to_shadow_pgtable, 6481 int emulation_type) 6482 { 6483 gpa_t gpa = cr2_or_gpa; 6484 kvm_pfn_t pfn; 6485 6486 if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) 6487 return false; 6488 6489 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 6490 return false; 6491 6492 if (!vcpu->arch.mmu->direct_map) { 6493 /* 6494 * Write permission should be allowed since only 6495 * write access need to be emulated. 6496 */ 6497 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 6498 6499 /* 6500 * If the mapping is invalid in guest, let cpu retry 6501 * it to generate fault. 6502 */ 6503 if (gpa == UNMAPPED_GVA) 6504 return true; 6505 } 6506 6507 /* 6508 * Do not retry the unhandleable instruction if it faults on the 6509 * readonly host memory, otherwise it will goto a infinite loop: 6510 * retry instruction -> write #PF -> emulation fail -> retry 6511 * instruction -> ... 6512 */ 6513 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 6514 6515 /* 6516 * If the instruction failed on the error pfn, it can not be fixed, 6517 * report the error to userspace. 6518 */ 6519 if (is_error_noslot_pfn(pfn)) 6520 return false; 6521 6522 kvm_release_pfn_clean(pfn); 6523 6524 /* The instructions are well-emulated on direct mmu. */ 6525 if (vcpu->arch.mmu->direct_map) { 6526 unsigned int indirect_shadow_pages; 6527 6528 spin_lock(&vcpu->kvm->mmu_lock); 6529 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 6530 spin_unlock(&vcpu->kvm->mmu_lock); 6531 6532 if (indirect_shadow_pages) 6533 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6534 6535 return true; 6536 } 6537 6538 /* 6539 * if emulation was due to access to shadowed page table 6540 * and it failed try to unshadow page and re-enter the 6541 * guest to let CPU execute the instruction. 6542 */ 6543 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6544 6545 /* 6546 * If the access faults on its page table, it can not 6547 * be fixed by unprotecting shadow page and it should 6548 * be reported to userspace. 6549 */ 6550 return !write_fault_to_shadow_pgtable; 6551 } 6552 6553 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 6554 gpa_t cr2_or_gpa, int emulation_type) 6555 { 6556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6557 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 6558 6559 last_retry_eip = vcpu->arch.last_retry_eip; 6560 last_retry_addr = vcpu->arch.last_retry_addr; 6561 6562 /* 6563 * If the emulation is caused by #PF and it is non-page_table 6564 * writing instruction, it means the VM-EXIT is caused by shadow 6565 * page protected, we can zap the shadow page and retry this 6566 * instruction directly. 6567 * 6568 * Note: if the guest uses a non-page-table modifying instruction 6569 * on the PDE that points to the instruction, then we will unmap 6570 * the instruction and go to an infinite loop. So, we cache the 6571 * last retried eip and the last fault address, if we meet the eip 6572 * and the address again, we can break out of the potential infinite 6573 * loop. 6574 */ 6575 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 6576 6577 if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) 6578 return false; 6579 6580 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 6581 return false; 6582 6583 if (x86_page_table_writing_insn(ctxt)) 6584 return false; 6585 6586 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 6587 return false; 6588 6589 vcpu->arch.last_retry_eip = ctxt->eip; 6590 vcpu->arch.last_retry_addr = cr2_or_gpa; 6591 6592 if (!vcpu->arch.mmu->direct_map) 6593 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 6594 6595 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6596 6597 return true; 6598 } 6599 6600 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 6601 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 6602 6603 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 6604 { 6605 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 6606 /* This is a good place to trace that we are exiting SMM. */ 6607 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 6608 6609 /* Process a latched INIT or SMI, if any. */ 6610 kvm_make_request(KVM_REQ_EVENT, vcpu); 6611 } 6612 6613 kvm_mmu_reset_context(vcpu); 6614 } 6615 6616 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 6617 unsigned long *db) 6618 { 6619 u32 dr6 = 0; 6620 int i; 6621 u32 enable, rwlen; 6622 6623 enable = dr7; 6624 rwlen = dr7 >> 16; 6625 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 6626 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 6627 dr6 |= (1 << i); 6628 return dr6; 6629 } 6630 6631 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 6632 { 6633 struct kvm_run *kvm_run = vcpu->run; 6634 6635 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 6636 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 6637 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 6638 kvm_run->debug.arch.exception = DB_VECTOR; 6639 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6640 return 0; 6641 } 6642 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 6643 return 1; 6644 } 6645 6646 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 6647 { 6648 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6649 int r; 6650 6651 r = kvm_x86_ops->skip_emulated_instruction(vcpu); 6652 if (unlikely(!r)) 6653 return 0; 6654 6655 /* 6656 * rflags is the old, "raw" value of the flags. The new value has 6657 * not been saved yet. 6658 * 6659 * This is correct even for TF set by the guest, because "the 6660 * processor will not generate this exception after the instruction 6661 * that sets the TF flag". 6662 */ 6663 if (unlikely(rflags & X86_EFLAGS_TF)) 6664 r = kvm_vcpu_do_singlestep(vcpu); 6665 return r; 6666 } 6667 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 6668 6669 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 6670 { 6671 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 6672 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 6673 struct kvm_run *kvm_run = vcpu->run; 6674 unsigned long eip = kvm_get_linear_rip(vcpu); 6675 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6676 vcpu->arch.guest_debug_dr7, 6677 vcpu->arch.eff_db); 6678 6679 if (dr6 != 0) { 6680 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 6681 kvm_run->debug.arch.pc = eip; 6682 kvm_run->debug.arch.exception = DB_VECTOR; 6683 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6684 *r = 0; 6685 return true; 6686 } 6687 } 6688 6689 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 6690 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 6691 unsigned long eip = kvm_get_linear_rip(vcpu); 6692 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6693 vcpu->arch.dr7, 6694 vcpu->arch.db); 6695 6696 if (dr6 != 0) { 6697 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 6698 vcpu->arch.dr6 |= dr6 | DR6_RTM; 6699 kvm_queue_exception(vcpu, DB_VECTOR); 6700 *r = 1; 6701 return true; 6702 } 6703 } 6704 6705 return false; 6706 } 6707 6708 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 6709 { 6710 switch (ctxt->opcode_len) { 6711 case 1: 6712 switch (ctxt->b) { 6713 case 0xe4: /* IN */ 6714 case 0xe5: 6715 case 0xec: 6716 case 0xed: 6717 case 0xe6: /* OUT */ 6718 case 0xe7: 6719 case 0xee: 6720 case 0xef: 6721 case 0x6c: /* INS */ 6722 case 0x6d: 6723 case 0x6e: /* OUTS */ 6724 case 0x6f: 6725 return true; 6726 } 6727 break; 6728 case 2: 6729 switch (ctxt->b) { 6730 case 0x33: /* RDPMC */ 6731 return true; 6732 } 6733 break; 6734 } 6735 6736 return false; 6737 } 6738 6739 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 6740 int emulation_type, void *insn, int insn_len) 6741 { 6742 int r; 6743 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6744 bool writeback = true; 6745 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6746 6747 vcpu->arch.l1tf_flush_l1d = true; 6748 6749 /* 6750 * Clear write_fault_to_shadow_pgtable here to ensure it is 6751 * never reused. 6752 */ 6753 vcpu->arch.write_fault_to_shadow_pgtable = false; 6754 kvm_clear_exception_queue(vcpu); 6755 6756 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6757 init_emulate_ctxt(vcpu); 6758 6759 /* 6760 * We will reenter on the same instruction since 6761 * we do not set complete_userspace_io. This does not 6762 * handle watchpoints yet, those would be handled in 6763 * the emulate_ops. 6764 */ 6765 if (!(emulation_type & EMULTYPE_SKIP) && 6766 kvm_vcpu_check_breakpoint(vcpu, &r)) 6767 return r; 6768 6769 ctxt->interruptibility = 0; 6770 ctxt->have_exception = false; 6771 ctxt->exception.vector = -1; 6772 ctxt->perm_ok = false; 6773 6774 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6775 6776 r = x86_decode_insn(ctxt, insn, insn_len); 6777 6778 trace_kvm_emulate_insn_start(vcpu); 6779 ++vcpu->stat.insn_emulation; 6780 if (r != EMULATION_OK) { 6781 if ((emulation_type & EMULTYPE_TRAP_UD) || 6782 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 6783 kvm_queue_exception(vcpu, UD_VECTOR); 6784 return 1; 6785 } 6786 if (reexecute_instruction(vcpu, cr2_or_gpa, 6787 write_fault_to_spt, 6788 emulation_type)) 6789 return 1; 6790 if (ctxt->have_exception) { 6791 /* 6792 * #UD should result in just EMULATION_FAILED, and trap-like 6793 * exception should not be encountered during decode. 6794 */ 6795 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 6796 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 6797 inject_emulated_exception(vcpu); 6798 return 1; 6799 } 6800 return handle_emulation_failure(vcpu, emulation_type); 6801 } 6802 } 6803 6804 if ((emulation_type & EMULTYPE_VMWARE_GP) && 6805 !is_vmware_backdoor_opcode(ctxt)) { 6806 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 6807 return 1; 6808 } 6809 6810 /* 6811 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 6812 * for kvm_skip_emulated_instruction(). The caller is responsible for 6813 * updating interruptibility state and injecting single-step #DBs. 6814 */ 6815 if (emulation_type & EMULTYPE_SKIP) { 6816 kvm_rip_write(vcpu, ctxt->_eip); 6817 if (ctxt->eflags & X86_EFLAGS_RF) 6818 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6819 return 1; 6820 } 6821 6822 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 6823 return 1; 6824 6825 /* this is needed for vmware backdoor interface to work since it 6826 changes registers values during IO operation */ 6827 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6828 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6829 emulator_invalidate_register_cache(ctxt); 6830 } 6831 6832 restart: 6833 /* Save the faulting GPA (cr2) in the address field */ 6834 ctxt->exception.address = cr2_or_gpa; 6835 6836 r = x86_emulate_insn(ctxt); 6837 6838 if (r == EMULATION_INTERCEPTED) 6839 return 1; 6840 6841 if (r == EMULATION_FAILED) { 6842 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 6843 emulation_type)) 6844 return 1; 6845 6846 return handle_emulation_failure(vcpu, emulation_type); 6847 } 6848 6849 if (ctxt->have_exception) { 6850 r = 1; 6851 if (inject_emulated_exception(vcpu)) 6852 return r; 6853 } else if (vcpu->arch.pio.count) { 6854 if (!vcpu->arch.pio.in) { 6855 /* FIXME: return into emulator if single-stepping. */ 6856 vcpu->arch.pio.count = 0; 6857 } else { 6858 writeback = false; 6859 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6860 } 6861 r = 0; 6862 } else if (vcpu->mmio_needed) { 6863 ++vcpu->stat.mmio_exits; 6864 6865 if (!vcpu->mmio_is_write) 6866 writeback = false; 6867 r = 0; 6868 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6869 } else if (r == EMULATION_RESTART) 6870 goto restart; 6871 else 6872 r = 1; 6873 6874 if (writeback) { 6875 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6876 toggle_interruptibility(vcpu, ctxt->interruptibility); 6877 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6878 if (!ctxt->have_exception || 6879 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 6880 kvm_rip_write(vcpu, ctxt->eip); 6881 if (r && ctxt->tf) 6882 r = kvm_vcpu_do_singlestep(vcpu); 6883 __kvm_set_rflags(vcpu, ctxt->eflags); 6884 } 6885 6886 /* 6887 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6888 * do nothing, and it will be requested again as soon as 6889 * the shadow expires. But we still need to check here, 6890 * because POPF has no interrupt shadow. 6891 */ 6892 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6893 kvm_make_request(KVM_REQ_EVENT, vcpu); 6894 } else 6895 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6896 6897 return r; 6898 } 6899 6900 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 6901 { 6902 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 6903 } 6904 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 6905 6906 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 6907 void *insn, int insn_len) 6908 { 6909 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 6910 } 6911 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 6912 6913 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 6914 { 6915 vcpu->arch.pio.count = 0; 6916 return 1; 6917 } 6918 6919 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 6920 { 6921 vcpu->arch.pio.count = 0; 6922 6923 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 6924 return 1; 6925 6926 return kvm_skip_emulated_instruction(vcpu); 6927 } 6928 6929 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6930 unsigned short port) 6931 { 6932 unsigned long val = kvm_rax_read(vcpu); 6933 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 6934 size, port, &val, 1); 6935 if (ret) 6936 return ret; 6937 6938 /* 6939 * Workaround userspace that relies on old KVM behavior of %rip being 6940 * incremented prior to exiting to userspace to handle "OUT 0x7e". 6941 */ 6942 if (port == 0x7e && 6943 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 6944 vcpu->arch.complete_userspace_io = 6945 complete_fast_pio_out_port_0x7e; 6946 kvm_skip_emulated_instruction(vcpu); 6947 } else { 6948 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6949 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 6950 } 6951 return 0; 6952 } 6953 6954 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6955 { 6956 unsigned long val; 6957 6958 /* We should only ever be called with arch.pio.count equal to 1 */ 6959 BUG_ON(vcpu->arch.pio.count != 1); 6960 6961 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 6962 vcpu->arch.pio.count = 0; 6963 return 1; 6964 } 6965 6966 /* For size less than 4 we merge, else we zero extend */ 6967 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 6968 6969 /* 6970 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 6971 * the copy and tracing 6972 */ 6973 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 6974 vcpu->arch.pio.port, &val, 1); 6975 kvm_rax_write(vcpu, val); 6976 6977 return kvm_skip_emulated_instruction(vcpu); 6978 } 6979 6980 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 6981 unsigned short port) 6982 { 6983 unsigned long val; 6984 int ret; 6985 6986 /* For size less than 4 we merge, else we zero extend */ 6987 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 6988 6989 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 6990 &val, 1); 6991 if (ret) { 6992 kvm_rax_write(vcpu, val); 6993 return ret; 6994 } 6995 6996 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6997 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 6998 6999 return 0; 7000 } 7001 7002 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7003 { 7004 int ret; 7005 7006 if (in) 7007 ret = kvm_fast_pio_in(vcpu, size, port); 7008 else 7009 ret = kvm_fast_pio_out(vcpu, size, port); 7010 return ret && kvm_skip_emulated_instruction(vcpu); 7011 } 7012 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7013 7014 static int kvmclock_cpu_down_prep(unsigned int cpu) 7015 { 7016 __this_cpu_write(cpu_tsc_khz, 0); 7017 return 0; 7018 } 7019 7020 static void tsc_khz_changed(void *data) 7021 { 7022 struct cpufreq_freqs *freq = data; 7023 unsigned long khz = 0; 7024 7025 if (data) 7026 khz = freq->new; 7027 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7028 khz = cpufreq_quick_get(raw_smp_processor_id()); 7029 if (!khz) 7030 khz = tsc_khz; 7031 __this_cpu_write(cpu_tsc_khz, khz); 7032 } 7033 7034 #ifdef CONFIG_X86_64 7035 static void kvm_hyperv_tsc_notifier(void) 7036 { 7037 struct kvm *kvm; 7038 struct kvm_vcpu *vcpu; 7039 int cpu; 7040 7041 mutex_lock(&kvm_lock); 7042 list_for_each_entry(kvm, &vm_list, vm_list) 7043 kvm_make_mclock_inprogress_request(kvm); 7044 7045 hyperv_stop_tsc_emulation(); 7046 7047 /* TSC frequency always matches when on Hyper-V */ 7048 for_each_present_cpu(cpu) 7049 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 7050 kvm_max_guest_tsc_khz = tsc_khz; 7051 7052 list_for_each_entry(kvm, &vm_list, vm_list) { 7053 struct kvm_arch *ka = &kvm->arch; 7054 7055 spin_lock(&ka->pvclock_gtod_sync_lock); 7056 7057 pvclock_update_vm_gtod_copy(kvm); 7058 7059 kvm_for_each_vcpu(cpu, vcpu, kvm) 7060 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7061 7062 kvm_for_each_vcpu(cpu, vcpu, kvm) 7063 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 7064 7065 spin_unlock(&ka->pvclock_gtod_sync_lock); 7066 } 7067 mutex_unlock(&kvm_lock); 7068 } 7069 #endif 7070 7071 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 7072 { 7073 struct kvm *kvm; 7074 struct kvm_vcpu *vcpu; 7075 int i, send_ipi = 0; 7076 7077 /* 7078 * We allow guests to temporarily run on slowing clocks, 7079 * provided we notify them after, or to run on accelerating 7080 * clocks, provided we notify them before. Thus time never 7081 * goes backwards. 7082 * 7083 * However, we have a problem. We can't atomically update 7084 * the frequency of a given CPU from this function; it is 7085 * merely a notifier, which can be called from any CPU. 7086 * Changing the TSC frequency at arbitrary points in time 7087 * requires a recomputation of local variables related to 7088 * the TSC for each VCPU. We must flag these local variables 7089 * to be updated and be sure the update takes place with the 7090 * new frequency before any guests proceed. 7091 * 7092 * Unfortunately, the combination of hotplug CPU and frequency 7093 * change creates an intractable locking scenario; the order 7094 * of when these callouts happen is undefined with respect to 7095 * CPU hotplug, and they can race with each other. As such, 7096 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 7097 * undefined; you can actually have a CPU frequency change take 7098 * place in between the computation of X and the setting of the 7099 * variable. To protect against this problem, all updates of 7100 * the per_cpu tsc_khz variable are done in an interrupt 7101 * protected IPI, and all callers wishing to update the value 7102 * must wait for a synchronous IPI to complete (which is trivial 7103 * if the caller is on the CPU already). This establishes the 7104 * necessary total order on variable updates. 7105 * 7106 * Note that because a guest time update may take place 7107 * anytime after the setting of the VCPU's request bit, the 7108 * correct TSC value must be set before the request. However, 7109 * to ensure the update actually makes it to any guest which 7110 * starts running in hardware virtualization between the set 7111 * and the acquisition of the spinlock, we must also ping the 7112 * CPU after setting the request bit. 7113 * 7114 */ 7115 7116 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7117 7118 mutex_lock(&kvm_lock); 7119 list_for_each_entry(kvm, &vm_list, vm_list) { 7120 kvm_for_each_vcpu(i, vcpu, kvm) { 7121 if (vcpu->cpu != cpu) 7122 continue; 7123 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7124 if (vcpu->cpu != raw_smp_processor_id()) 7125 send_ipi = 1; 7126 } 7127 } 7128 mutex_unlock(&kvm_lock); 7129 7130 if (freq->old < freq->new && send_ipi) { 7131 /* 7132 * We upscale the frequency. Must make the guest 7133 * doesn't see old kvmclock values while running with 7134 * the new frequency, otherwise we risk the guest sees 7135 * time go backwards. 7136 * 7137 * In case we update the frequency for another cpu 7138 * (which might be in guest context) send an interrupt 7139 * to kick the cpu out of guest context. Next time 7140 * guest context is entered kvmclock will be updated, 7141 * so the guest will not see stale values. 7142 */ 7143 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7144 } 7145 } 7146 7147 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 7148 void *data) 7149 { 7150 struct cpufreq_freqs *freq = data; 7151 int cpu; 7152 7153 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 7154 return 0; 7155 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 7156 return 0; 7157 7158 for_each_cpu(cpu, freq->policy->cpus) 7159 __kvmclock_cpufreq_notifier(freq, cpu); 7160 7161 return 0; 7162 } 7163 7164 static struct notifier_block kvmclock_cpufreq_notifier_block = { 7165 .notifier_call = kvmclock_cpufreq_notifier 7166 }; 7167 7168 static int kvmclock_cpu_online(unsigned int cpu) 7169 { 7170 tsc_khz_changed(NULL); 7171 return 0; 7172 } 7173 7174 static void kvm_timer_init(void) 7175 { 7176 max_tsc_khz = tsc_khz; 7177 7178 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 7179 #ifdef CONFIG_CPU_FREQ 7180 struct cpufreq_policy policy; 7181 int cpu; 7182 7183 memset(&policy, 0, sizeof(policy)); 7184 cpu = get_cpu(); 7185 cpufreq_get_policy(&policy, cpu); 7186 if (policy.cpuinfo.max_freq) 7187 max_tsc_khz = policy.cpuinfo.max_freq; 7188 put_cpu(); 7189 #endif 7190 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 7191 CPUFREQ_TRANSITION_NOTIFIER); 7192 } 7193 7194 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 7195 kvmclock_cpu_online, kvmclock_cpu_down_prep); 7196 } 7197 7198 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 7199 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 7200 7201 int kvm_is_in_guest(void) 7202 { 7203 return __this_cpu_read(current_vcpu) != NULL; 7204 } 7205 7206 static int kvm_is_user_mode(void) 7207 { 7208 int user_mode = 3; 7209 7210 if (__this_cpu_read(current_vcpu)) 7211 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 7212 7213 return user_mode != 0; 7214 } 7215 7216 static unsigned long kvm_get_guest_ip(void) 7217 { 7218 unsigned long ip = 0; 7219 7220 if (__this_cpu_read(current_vcpu)) 7221 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 7222 7223 return ip; 7224 } 7225 7226 static void kvm_handle_intel_pt_intr(void) 7227 { 7228 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 7229 7230 kvm_make_request(KVM_REQ_PMI, vcpu); 7231 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 7232 (unsigned long *)&vcpu->arch.pmu.global_status); 7233 } 7234 7235 static struct perf_guest_info_callbacks kvm_guest_cbs = { 7236 .is_in_guest = kvm_is_in_guest, 7237 .is_user_mode = kvm_is_user_mode, 7238 .get_guest_ip = kvm_get_guest_ip, 7239 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 7240 }; 7241 7242 #ifdef CONFIG_X86_64 7243 static void pvclock_gtod_update_fn(struct work_struct *work) 7244 { 7245 struct kvm *kvm; 7246 7247 struct kvm_vcpu *vcpu; 7248 int i; 7249 7250 mutex_lock(&kvm_lock); 7251 list_for_each_entry(kvm, &vm_list, vm_list) 7252 kvm_for_each_vcpu(i, vcpu, kvm) 7253 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7254 atomic_set(&kvm_guest_has_master_clock, 0); 7255 mutex_unlock(&kvm_lock); 7256 } 7257 7258 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 7259 7260 /* 7261 * Notification about pvclock gtod data update. 7262 */ 7263 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 7264 void *priv) 7265 { 7266 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 7267 struct timekeeper *tk = priv; 7268 7269 update_pvclock_gtod(tk); 7270 7271 /* disable master clock if host does not trust, or does not 7272 * use, TSC based clocksource. 7273 */ 7274 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 7275 atomic_read(&kvm_guest_has_master_clock) != 0) 7276 queue_work(system_long_wq, &pvclock_gtod_work); 7277 7278 return 0; 7279 } 7280 7281 static struct notifier_block pvclock_gtod_notifier = { 7282 .notifier_call = pvclock_gtod_notify, 7283 }; 7284 #endif 7285 7286 int kvm_arch_init(void *opaque) 7287 { 7288 int r; 7289 struct kvm_x86_ops *ops = opaque; 7290 7291 if (kvm_x86_ops) { 7292 printk(KERN_ERR "kvm: already loaded the other module\n"); 7293 r = -EEXIST; 7294 goto out; 7295 } 7296 7297 if (!ops->cpu_has_kvm_support()) { 7298 printk(KERN_ERR "kvm: no hardware support\n"); 7299 r = -EOPNOTSUPP; 7300 goto out; 7301 } 7302 if (ops->disabled_by_bios()) { 7303 printk(KERN_ERR "kvm: disabled by bios\n"); 7304 r = -EOPNOTSUPP; 7305 goto out; 7306 } 7307 7308 /* 7309 * KVM explicitly assumes that the guest has an FPU and 7310 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 7311 * vCPU's FPU state as a fxregs_state struct. 7312 */ 7313 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 7314 printk(KERN_ERR "kvm: inadequate fpu\n"); 7315 r = -EOPNOTSUPP; 7316 goto out; 7317 } 7318 7319 r = -ENOMEM; 7320 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 7321 __alignof__(struct fpu), SLAB_ACCOUNT, 7322 NULL); 7323 if (!x86_fpu_cache) { 7324 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 7325 goto out; 7326 } 7327 7328 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 7329 if (!shared_msrs) { 7330 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 7331 goto out_free_x86_fpu_cache; 7332 } 7333 7334 r = kvm_mmu_module_init(); 7335 if (r) 7336 goto out_free_percpu; 7337 7338 kvm_x86_ops = ops; 7339 7340 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 7341 PT_DIRTY_MASK, PT64_NX_MASK, 0, 7342 PT_PRESENT_MASK, 0, sme_me_mask); 7343 kvm_timer_init(); 7344 7345 perf_register_guest_info_callbacks(&kvm_guest_cbs); 7346 7347 if (boot_cpu_has(X86_FEATURE_XSAVE)) 7348 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 7349 7350 kvm_lapic_init(); 7351 if (pi_inject_timer == -1) 7352 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 7353 #ifdef CONFIG_X86_64 7354 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 7355 7356 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7357 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 7358 #endif 7359 7360 return 0; 7361 7362 out_free_percpu: 7363 free_percpu(shared_msrs); 7364 out_free_x86_fpu_cache: 7365 kmem_cache_destroy(x86_fpu_cache); 7366 out: 7367 return r; 7368 } 7369 7370 void kvm_arch_exit(void) 7371 { 7372 #ifdef CONFIG_X86_64 7373 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7374 clear_hv_tscchange_cb(); 7375 #endif 7376 kvm_lapic_exit(); 7377 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 7378 7379 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7380 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 7381 CPUFREQ_TRANSITION_NOTIFIER); 7382 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 7383 #ifdef CONFIG_X86_64 7384 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 7385 #endif 7386 kvm_x86_ops = NULL; 7387 kvm_mmu_module_exit(); 7388 free_percpu(shared_msrs); 7389 kmem_cache_destroy(x86_fpu_cache); 7390 } 7391 7392 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 7393 { 7394 ++vcpu->stat.halt_exits; 7395 if (lapic_in_kernel(vcpu)) { 7396 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 7397 return 1; 7398 } else { 7399 vcpu->run->exit_reason = KVM_EXIT_HLT; 7400 return 0; 7401 } 7402 } 7403 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 7404 7405 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 7406 { 7407 int ret = kvm_skip_emulated_instruction(vcpu); 7408 /* 7409 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 7410 * KVM_EXIT_DEBUG here. 7411 */ 7412 return kvm_vcpu_halt(vcpu) && ret; 7413 } 7414 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 7415 7416 #ifdef CONFIG_X86_64 7417 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 7418 unsigned long clock_type) 7419 { 7420 struct kvm_clock_pairing clock_pairing; 7421 struct timespec64 ts; 7422 u64 cycle; 7423 int ret; 7424 7425 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 7426 return -KVM_EOPNOTSUPP; 7427 7428 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 7429 return -KVM_EOPNOTSUPP; 7430 7431 clock_pairing.sec = ts.tv_sec; 7432 clock_pairing.nsec = ts.tv_nsec; 7433 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 7434 clock_pairing.flags = 0; 7435 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 7436 7437 ret = 0; 7438 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 7439 sizeof(struct kvm_clock_pairing))) 7440 ret = -KVM_EFAULT; 7441 7442 return ret; 7443 } 7444 #endif 7445 7446 /* 7447 * kvm_pv_kick_cpu_op: Kick a vcpu. 7448 * 7449 * @apicid - apicid of vcpu to be kicked. 7450 */ 7451 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 7452 { 7453 struct kvm_lapic_irq lapic_irq; 7454 7455 lapic_irq.shorthand = APIC_DEST_NOSHORT; 7456 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 7457 lapic_irq.level = 0; 7458 lapic_irq.dest_id = apicid; 7459 lapic_irq.msi_redir_hint = false; 7460 7461 lapic_irq.delivery_mode = APIC_DM_REMRD; 7462 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 7463 } 7464 7465 bool kvm_apicv_activated(struct kvm *kvm) 7466 { 7467 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 7468 } 7469 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 7470 7471 void kvm_apicv_init(struct kvm *kvm, bool enable) 7472 { 7473 if (enable) 7474 clear_bit(APICV_INHIBIT_REASON_DISABLE, 7475 &kvm->arch.apicv_inhibit_reasons); 7476 else 7477 set_bit(APICV_INHIBIT_REASON_DISABLE, 7478 &kvm->arch.apicv_inhibit_reasons); 7479 } 7480 EXPORT_SYMBOL_GPL(kvm_apicv_init); 7481 7482 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) 7483 { 7484 struct kvm_vcpu *target = NULL; 7485 struct kvm_apic_map *map; 7486 7487 rcu_read_lock(); 7488 map = rcu_dereference(kvm->arch.apic_map); 7489 7490 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 7491 target = map->phys_map[dest_id]->vcpu; 7492 7493 rcu_read_unlock(); 7494 7495 if (target && READ_ONCE(target->ready)) 7496 kvm_vcpu_yield_to(target); 7497 } 7498 7499 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 7500 { 7501 unsigned long nr, a0, a1, a2, a3, ret; 7502 int op_64_bit; 7503 7504 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 7505 return kvm_hv_hypercall(vcpu); 7506 7507 nr = kvm_rax_read(vcpu); 7508 a0 = kvm_rbx_read(vcpu); 7509 a1 = kvm_rcx_read(vcpu); 7510 a2 = kvm_rdx_read(vcpu); 7511 a3 = kvm_rsi_read(vcpu); 7512 7513 trace_kvm_hypercall(nr, a0, a1, a2, a3); 7514 7515 op_64_bit = is_64_bit_mode(vcpu); 7516 if (!op_64_bit) { 7517 nr &= 0xFFFFFFFF; 7518 a0 &= 0xFFFFFFFF; 7519 a1 &= 0xFFFFFFFF; 7520 a2 &= 0xFFFFFFFF; 7521 a3 &= 0xFFFFFFFF; 7522 } 7523 7524 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 7525 ret = -KVM_EPERM; 7526 goto out; 7527 } 7528 7529 switch (nr) { 7530 case KVM_HC_VAPIC_POLL_IRQ: 7531 ret = 0; 7532 break; 7533 case KVM_HC_KICK_CPU: 7534 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 7535 kvm_sched_yield(vcpu->kvm, a1); 7536 ret = 0; 7537 break; 7538 #ifdef CONFIG_X86_64 7539 case KVM_HC_CLOCK_PAIRING: 7540 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 7541 break; 7542 #endif 7543 case KVM_HC_SEND_IPI: 7544 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 7545 break; 7546 case KVM_HC_SCHED_YIELD: 7547 kvm_sched_yield(vcpu->kvm, a0); 7548 ret = 0; 7549 break; 7550 default: 7551 ret = -KVM_ENOSYS; 7552 break; 7553 } 7554 out: 7555 if (!op_64_bit) 7556 ret = (u32)ret; 7557 kvm_rax_write(vcpu, ret); 7558 7559 ++vcpu->stat.hypercalls; 7560 return kvm_skip_emulated_instruction(vcpu); 7561 } 7562 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 7563 7564 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 7565 { 7566 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7567 char instruction[3]; 7568 unsigned long rip = kvm_rip_read(vcpu); 7569 7570 kvm_x86_ops->patch_hypercall(vcpu, instruction); 7571 7572 return emulator_write_emulated(ctxt, rip, instruction, 3, 7573 &ctxt->exception); 7574 } 7575 7576 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 7577 { 7578 return vcpu->run->request_interrupt_window && 7579 likely(!pic_in_kernel(vcpu->kvm)); 7580 } 7581 7582 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 7583 { 7584 struct kvm_run *kvm_run = vcpu->run; 7585 7586 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 7587 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 7588 kvm_run->cr8 = kvm_get_cr8(vcpu); 7589 kvm_run->apic_base = kvm_get_apic_base(vcpu); 7590 kvm_run->ready_for_interrupt_injection = 7591 pic_in_kernel(vcpu->kvm) || 7592 kvm_vcpu_ready_for_interrupt_injection(vcpu); 7593 } 7594 7595 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 7596 { 7597 int max_irr, tpr; 7598 7599 if (!kvm_x86_ops->update_cr8_intercept) 7600 return; 7601 7602 if (!lapic_in_kernel(vcpu)) 7603 return; 7604 7605 if (vcpu->arch.apicv_active) 7606 return; 7607 7608 if (!vcpu->arch.apic->vapic_addr) 7609 max_irr = kvm_lapic_find_highest_irr(vcpu); 7610 else 7611 max_irr = -1; 7612 7613 if (max_irr != -1) 7614 max_irr >>= 4; 7615 7616 tpr = kvm_lapic_get_cr8(vcpu); 7617 7618 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 7619 } 7620 7621 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 7622 { 7623 int r; 7624 7625 /* try to reinject previous events if any */ 7626 7627 if (vcpu->arch.exception.injected) 7628 kvm_x86_ops->queue_exception(vcpu); 7629 /* 7630 * Do not inject an NMI or interrupt if there is a pending 7631 * exception. Exceptions and interrupts are recognized at 7632 * instruction boundaries, i.e. the start of an instruction. 7633 * Trap-like exceptions, e.g. #DB, have higher priority than 7634 * NMIs and interrupts, i.e. traps are recognized before an 7635 * NMI/interrupt that's pending on the same instruction. 7636 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 7637 * priority, but are only generated (pended) during instruction 7638 * execution, i.e. a pending fault-like exception means the 7639 * fault occurred on the *previous* instruction and must be 7640 * serviced prior to recognizing any new events in order to 7641 * fully complete the previous instruction. 7642 */ 7643 else if (!vcpu->arch.exception.pending) { 7644 if (vcpu->arch.nmi_injected) 7645 kvm_x86_ops->set_nmi(vcpu); 7646 else if (vcpu->arch.interrupt.injected) 7647 kvm_x86_ops->set_irq(vcpu); 7648 } 7649 7650 /* 7651 * Call check_nested_events() even if we reinjected a previous event 7652 * in order for caller to determine if it should require immediate-exit 7653 * from L2 to L1 due to pending L1 events which require exit 7654 * from L2 to L1. 7655 */ 7656 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 7657 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 7658 if (r != 0) 7659 return r; 7660 } 7661 7662 /* try to inject new event if pending */ 7663 if (vcpu->arch.exception.pending) { 7664 trace_kvm_inj_exception(vcpu->arch.exception.nr, 7665 vcpu->arch.exception.has_error_code, 7666 vcpu->arch.exception.error_code); 7667 7668 WARN_ON_ONCE(vcpu->arch.exception.injected); 7669 vcpu->arch.exception.pending = false; 7670 vcpu->arch.exception.injected = true; 7671 7672 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 7673 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 7674 X86_EFLAGS_RF); 7675 7676 if (vcpu->arch.exception.nr == DB_VECTOR) { 7677 /* 7678 * This code assumes that nSVM doesn't use 7679 * check_nested_events(). If it does, the 7680 * DR6/DR7 changes should happen before L1 7681 * gets a #VMEXIT for an intercepted #DB in 7682 * L2. (Under VMX, on the other hand, the 7683 * DR6/DR7 changes should not happen in the 7684 * event of a VM-exit to L1 for an intercepted 7685 * #DB in L2.) 7686 */ 7687 kvm_deliver_exception_payload(vcpu); 7688 if (vcpu->arch.dr7 & DR7_GD) { 7689 vcpu->arch.dr7 &= ~DR7_GD; 7690 kvm_update_dr7(vcpu); 7691 } 7692 } 7693 7694 kvm_x86_ops->queue_exception(vcpu); 7695 } 7696 7697 /* Don't consider new event if we re-injected an event */ 7698 if (kvm_event_needs_reinjection(vcpu)) 7699 return 0; 7700 7701 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 7702 kvm_x86_ops->smi_allowed(vcpu)) { 7703 vcpu->arch.smi_pending = false; 7704 ++vcpu->arch.smi_count; 7705 enter_smm(vcpu); 7706 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 7707 --vcpu->arch.nmi_pending; 7708 vcpu->arch.nmi_injected = true; 7709 kvm_x86_ops->set_nmi(vcpu); 7710 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 7711 /* 7712 * Because interrupts can be injected asynchronously, we are 7713 * calling check_nested_events again here to avoid a race condition. 7714 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 7715 * proposal and current concerns. Perhaps we should be setting 7716 * KVM_REQ_EVENT only on certain events and not unconditionally? 7717 */ 7718 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 7719 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 7720 if (r != 0) 7721 return r; 7722 } 7723 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 7724 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 7725 false); 7726 kvm_x86_ops->set_irq(vcpu); 7727 } 7728 } 7729 7730 return 0; 7731 } 7732 7733 static void process_nmi(struct kvm_vcpu *vcpu) 7734 { 7735 unsigned limit = 2; 7736 7737 /* 7738 * x86 is limited to one NMI running, and one NMI pending after it. 7739 * If an NMI is already in progress, limit further NMIs to just one. 7740 * Otherwise, allow two (and we'll inject the first one immediately). 7741 */ 7742 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 7743 limit = 1; 7744 7745 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 7746 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 7747 kvm_make_request(KVM_REQ_EVENT, vcpu); 7748 } 7749 7750 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 7751 { 7752 u32 flags = 0; 7753 flags |= seg->g << 23; 7754 flags |= seg->db << 22; 7755 flags |= seg->l << 21; 7756 flags |= seg->avl << 20; 7757 flags |= seg->present << 15; 7758 flags |= seg->dpl << 13; 7759 flags |= seg->s << 12; 7760 flags |= seg->type << 8; 7761 return flags; 7762 } 7763 7764 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 7765 { 7766 struct kvm_segment seg; 7767 int offset; 7768 7769 kvm_get_segment(vcpu, &seg, n); 7770 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 7771 7772 if (n < 3) 7773 offset = 0x7f84 + n * 12; 7774 else 7775 offset = 0x7f2c + (n - 3) * 12; 7776 7777 put_smstate(u32, buf, offset + 8, seg.base); 7778 put_smstate(u32, buf, offset + 4, seg.limit); 7779 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 7780 } 7781 7782 #ifdef CONFIG_X86_64 7783 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 7784 { 7785 struct kvm_segment seg; 7786 int offset; 7787 u16 flags; 7788 7789 kvm_get_segment(vcpu, &seg, n); 7790 offset = 0x7e00 + n * 16; 7791 7792 flags = enter_smm_get_segment_flags(&seg) >> 8; 7793 put_smstate(u16, buf, offset, seg.selector); 7794 put_smstate(u16, buf, offset + 2, flags); 7795 put_smstate(u32, buf, offset + 4, seg.limit); 7796 put_smstate(u64, buf, offset + 8, seg.base); 7797 } 7798 #endif 7799 7800 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 7801 { 7802 struct desc_ptr dt; 7803 struct kvm_segment seg; 7804 unsigned long val; 7805 int i; 7806 7807 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 7808 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 7809 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 7810 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 7811 7812 for (i = 0; i < 8; i++) 7813 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 7814 7815 kvm_get_dr(vcpu, 6, &val); 7816 put_smstate(u32, buf, 0x7fcc, (u32)val); 7817 kvm_get_dr(vcpu, 7, &val); 7818 put_smstate(u32, buf, 0x7fc8, (u32)val); 7819 7820 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7821 put_smstate(u32, buf, 0x7fc4, seg.selector); 7822 put_smstate(u32, buf, 0x7f64, seg.base); 7823 put_smstate(u32, buf, 0x7f60, seg.limit); 7824 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 7825 7826 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7827 put_smstate(u32, buf, 0x7fc0, seg.selector); 7828 put_smstate(u32, buf, 0x7f80, seg.base); 7829 put_smstate(u32, buf, 0x7f7c, seg.limit); 7830 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 7831 7832 kvm_x86_ops->get_gdt(vcpu, &dt); 7833 put_smstate(u32, buf, 0x7f74, dt.address); 7834 put_smstate(u32, buf, 0x7f70, dt.size); 7835 7836 kvm_x86_ops->get_idt(vcpu, &dt); 7837 put_smstate(u32, buf, 0x7f58, dt.address); 7838 put_smstate(u32, buf, 0x7f54, dt.size); 7839 7840 for (i = 0; i < 6; i++) 7841 enter_smm_save_seg_32(vcpu, buf, i); 7842 7843 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 7844 7845 /* revision id */ 7846 put_smstate(u32, buf, 0x7efc, 0x00020000); 7847 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 7848 } 7849 7850 #ifdef CONFIG_X86_64 7851 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 7852 { 7853 struct desc_ptr dt; 7854 struct kvm_segment seg; 7855 unsigned long val; 7856 int i; 7857 7858 for (i = 0; i < 16; i++) 7859 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7860 7861 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7862 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7863 7864 kvm_get_dr(vcpu, 6, &val); 7865 put_smstate(u64, buf, 0x7f68, val); 7866 kvm_get_dr(vcpu, 7, &val); 7867 put_smstate(u64, buf, 0x7f60, val); 7868 7869 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7870 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7871 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7872 7873 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7874 7875 /* revision id */ 7876 put_smstate(u32, buf, 0x7efc, 0x00020064); 7877 7878 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7879 7880 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7881 put_smstate(u16, buf, 0x7e90, seg.selector); 7882 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7883 put_smstate(u32, buf, 0x7e94, seg.limit); 7884 put_smstate(u64, buf, 0x7e98, seg.base); 7885 7886 kvm_x86_ops->get_idt(vcpu, &dt); 7887 put_smstate(u32, buf, 0x7e84, dt.size); 7888 put_smstate(u64, buf, 0x7e88, dt.address); 7889 7890 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7891 put_smstate(u16, buf, 0x7e70, seg.selector); 7892 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7893 put_smstate(u32, buf, 0x7e74, seg.limit); 7894 put_smstate(u64, buf, 0x7e78, seg.base); 7895 7896 kvm_x86_ops->get_gdt(vcpu, &dt); 7897 put_smstate(u32, buf, 0x7e64, dt.size); 7898 put_smstate(u64, buf, 0x7e68, dt.address); 7899 7900 for (i = 0; i < 6; i++) 7901 enter_smm_save_seg_64(vcpu, buf, i); 7902 } 7903 #endif 7904 7905 static void enter_smm(struct kvm_vcpu *vcpu) 7906 { 7907 struct kvm_segment cs, ds; 7908 struct desc_ptr dt; 7909 char buf[512]; 7910 u32 cr0; 7911 7912 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7913 memset(buf, 0, 512); 7914 #ifdef CONFIG_X86_64 7915 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7916 enter_smm_save_state_64(vcpu, buf); 7917 else 7918 #endif 7919 enter_smm_save_state_32(vcpu, buf); 7920 7921 /* 7922 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7923 * vCPU state (e.g. leave guest mode) after we've saved the state into 7924 * the SMM state-save area. 7925 */ 7926 kvm_x86_ops->pre_enter_smm(vcpu, buf); 7927 7928 vcpu->arch.hflags |= HF_SMM_MASK; 7929 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7930 7931 if (kvm_x86_ops->get_nmi_mask(vcpu)) 7932 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7933 else 7934 kvm_x86_ops->set_nmi_mask(vcpu, true); 7935 7936 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7937 kvm_rip_write(vcpu, 0x8000); 7938 7939 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7940 kvm_x86_ops->set_cr0(vcpu, cr0); 7941 vcpu->arch.cr0 = cr0; 7942 7943 kvm_x86_ops->set_cr4(vcpu, 0); 7944 7945 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7946 dt.address = dt.size = 0; 7947 kvm_x86_ops->set_idt(vcpu, &dt); 7948 7949 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7950 7951 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7952 cs.base = vcpu->arch.smbase; 7953 7954 ds.selector = 0; 7955 ds.base = 0; 7956 7957 cs.limit = ds.limit = 0xffffffff; 7958 cs.type = ds.type = 0x3; 7959 cs.dpl = ds.dpl = 0; 7960 cs.db = ds.db = 0; 7961 cs.s = ds.s = 1; 7962 cs.l = ds.l = 0; 7963 cs.g = ds.g = 1; 7964 cs.avl = ds.avl = 0; 7965 cs.present = ds.present = 1; 7966 cs.unusable = ds.unusable = 0; 7967 cs.padding = ds.padding = 0; 7968 7969 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7970 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 7971 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 7972 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 7973 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 7974 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 7975 7976 #ifdef CONFIG_X86_64 7977 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7978 kvm_x86_ops->set_efer(vcpu, 0); 7979 #endif 7980 7981 kvm_update_cpuid(vcpu); 7982 kvm_mmu_reset_context(vcpu); 7983 } 7984 7985 static void process_smi(struct kvm_vcpu *vcpu) 7986 { 7987 vcpu->arch.smi_pending = true; 7988 kvm_make_request(KVM_REQ_EVENT, vcpu); 7989 } 7990 7991 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 7992 unsigned long *vcpu_bitmap) 7993 { 7994 cpumask_var_t cpus; 7995 7996 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 7997 7998 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 7999 vcpu_bitmap, cpus); 8000 8001 free_cpumask_var(cpus); 8002 } 8003 8004 void kvm_make_scan_ioapic_request(struct kvm *kvm) 8005 { 8006 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 8007 } 8008 8009 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 8010 { 8011 if (!lapic_in_kernel(vcpu)) 8012 return; 8013 8014 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 8015 kvm_apic_update_apicv(vcpu); 8016 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 8017 } 8018 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 8019 8020 /* 8021 * NOTE: Do not hold any lock prior to calling this. 8022 * 8023 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 8024 * locked, because it calls __x86_set_memory_region() which does 8025 * synchronize_srcu(&kvm->srcu). 8026 */ 8027 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 8028 { 8029 if (!kvm_x86_ops->check_apicv_inhibit_reasons || 8030 !kvm_x86_ops->check_apicv_inhibit_reasons(bit)) 8031 return; 8032 8033 if (activate) { 8034 if (!test_and_clear_bit(bit, &kvm->arch.apicv_inhibit_reasons) || 8035 !kvm_apicv_activated(kvm)) 8036 return; 8037 } else { 8038 if (test_and_set_bit(bit, &kvm->arch.apicv_inhibit_reasons) || 8039 kvm_apicv_activated(kvm)) 8040 return; 8041 } 8042 8043 trace_kvm_apicv_update_request(activate, bit); 8044 if (kvm_x86_ops->pre_update_apicv_exec_ctrl) 8045 kvm_x86_ops->pre_update_apicv_exec_ctrl(kvm, activate); 8046 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 8047 } 8048 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 8049 8050 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 8051 { 8052 if (!kvm_apic_present(vcpu)) 8053 return; 8054 8055 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 8056 8057 if (irqchip_split(vcpu->kvm)) 8058 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 8059 else { 8060 if (vcpu->arch.apicv_active) 8061 kvm_x86_ops->sync_pir_to_irr(vcpu); 8062 if (ioapic_in_kernel(vcpu->kvm)) 8063 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 8064 } 8065 8066 if (is_guest_mode(vcpu)) 8067 vcpu->arch.load_eoi_exitmap_pending = true; 8068 else 8069 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 8070 } 8071 8072 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 8073 { 8074 u64 eoi_exit_bitmap[4]; 8075 8076 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 8077 return; 8078 8079 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 8080 vcpu_to_synic(vcpu)->vec_bitmap, 256); 8081 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 8082 } 8083 8084 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 8085 unsigned long start, unsigned long end, 8086 bool blockable) 8087 { 8088 unsigned long apic_address; 8089 8090 /* 8091 * The physical address of apic access page is stored in the VMCS. 8092 * Update it when it becomes invalid. 8093 */ 8094 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8095 if (start <= apic_address && apic_address < end) 8096 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 8097 8098 return 0; 8099 } 8100 8101 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 8102 { 8103 struct page *page = NULL; 8104 8105 if (!lapic_in_kernel(vcpu)) 8106 return; 8107 8108 if (!kvm_x86_ops->set_apic_access_page_addr) 8109 return; 8110 8111 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8112 if (is_error_page(page)) 8113 return; 8114 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 8115 8116 /* 8117 * Do not pin apic access page in memory, the MMU notifier 8118 * will call us again if it is migrated or swapped out. 8119 */ 8120 put_page(page); 8121 } 8122 8123 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 8124 { 8125 smp_send_reschedule(vcpu->cpu); 8126 } 8127 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 8128 8129 /* 8130 * Returns 1 to let vcpu_run() continue the guest execution loop without 8131 * exiting to the userspace. Otherwise, the value will be returned to the 8132 * userspace. 8133 */ 8134 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 8135 { 8136 int r; 8137 bool req_int_win = 8138 dm_request_for_irq_injection(vcpu) && 8139 kvm_cpu_accept_dm_intr(vcpu); 8140 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE; 8141 8142 bool req_immediate_exit = false; 8143 8144 if (kvm_request_pending(vcpu)) { 8145 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) { 8146 if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) { 8147 r = 0; 8148 goto out; 8149 } 8150 } 8151 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 8152 kvm_mmu_unload(vcpu); 8153 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 8154 __kvm_migrate_timers(vcpu); 8155 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 8156 kvm_gen_update_masterclock(vcpu->kvm); 8157 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 8158 kvm_gen_kvmclock_update(vcpu); 8159 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 8160 r = kvm_guest_time_update(vcpu); 8161 if (unlikely(r)) 8162 goto out; 8163 } 8164 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 8165 kvm_mmu_sync_roots(vcpu); 8166 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu)) 8167 kvm_mmu_load_cr3(vcpu); 8168 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 8169 kvm_vcpu_flush_tlb(vcpu, true); 8170 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 8171 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 8172 r = 0; 8173 goto out; 8174 } 8175 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8176 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 8177 vcpu->mmio_needed = 0; 8178 r = 0; 8179 goto out; 8180 } 8181 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 8182 /* Page is swapped out. Do synthetic halt */ 8183 vcpu->arch.apf.halted = true; 8184 r = 1; 8185 goto out; 8186 } 8187 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 8188 record_steal_time(vcpu); 8189 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 8190 process_smi(vcpu); 8191 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 8192 process_nmi(vcpu); 8193 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 8194 kvm_pmu_handle_event(vcpu); 8195 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 8196 kvm_pmu_deliver_pmi(vcpu); 8197 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 8198 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 8199 if (test_bit(vcpu->arch.pending_ioapic_eoi, 8200 vcpu->arch.ioapic_handled_vectors)) { 8201 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 8202 vcpu->run->eoi.vector = 8203 vcpu->arch.pending_ioapic_eoi; 8204 r = 0; 8205 goto out; 8206 } 8207 } 8208 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 8209 vcpu_scan_ioapic(vcpu); 8210 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 8211 vcpu_load_eoi_exitmap(vcpu); 8212 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 8213 kvm_vcpu_reload_apic_access_page(vcpu); 8214 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 8215 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8216 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 8217 r = 0; 8218 goto out; 8219 } 8220 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 8221 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8222 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 8223 r = 0; 8224 goto out; 8225 } 8226 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 8227 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 8228 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 8229 r = 0; 8230 goto out; 8231 } 8232 8233 /* 8234 * KVM_REQ_HV_STIMER has to be processed after 8235 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 8236 * depend on the guest clock being up-to-date 8237 */ 8238 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 8239 kvm_hv_process_stimers(vcpu); 8240 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 8241 kvm_vcpu_update_apicv(vcpu); 8242 } 8243 8244 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 8245 ++vcpu->stat.req_event; 8246 kvm_apic_accept_events(vcpu); 8247 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 8248 r = 1; 8249 goto out; 8250 } 8251 8252 if (inject_pending_event(vcpu, req_int_win) != 0) 8253 req_immediate_exit = true; 8254 else { 8255 /* Enable SMI/NMI/IRQ window open exits if needed. 8256 * 8257 * SMIs have three cases: 8258 * 1) They can be nested, and then there is nothing to 8259 * do here because RSM will cause a vmexit anyway. 8260 * 2) There is an ISA-specific reason why SMI cannot be 8261 * injected, and the moment when this changes can be 8262 * intercepted. 8263 * 3) Or the SMI can be pending because 8264 * inject_pending_event has completed the injection 8265 * of an IRQ or NMI from the previous vmexit, and 8266 * then we request an immediate exit to inject the 8267 * SMI. 8268 */ 8269 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 8270 if (!kvm_x86_ops->enable_smi_window(vcpu)) 8271 req_immediate_exit = true; 8272 if (vcpu->arch.nmi_pending) 8273 kvm_x86_ops->enable_nmi_window(vcpu); 8274 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 8275 kvm_x86_ops->enable_irq_window(vcpu); 8276 WARN_ON(vcpu->arch.exception.pending); 8277 } 8278 8279 if (kvm_lapic_enabled(vcpu)) { 8280 update_cr8_intercept(vcpu); 8281 kvm_lapic_sync_to_vapic(vcpu); 8282 } 8283 } 8284 8285 r = kvm_mmu_reload(vcpu); 8286 if (unlikely(r)) { 8287 goto cancel_injection; 8288 } 8289 8290 preempt_disable(); 8291 8292 kvm_x86_ops->prepare_guest_switch(vcpu); 8293 8294 /* 8295 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 8296 * IPI are then delayed after guest entry, which ensures that they 8297 * result in virtual interrupt delivery. 8298 */ 8299 local_irq_disable(); 8300 vcpu->mode = IN_GUEST_MODE; 8301 8302 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8303 8304 /* 8305 * 1) We should set ->mode before checking ->requests. Please see 8306 * the comment in kvm_vcpu_exiting_guest_mode(). 8307 * 8308 * 2) For APICv, we should set ->mode before checking PID.ON. This 8309 * pairs with the memory barrier implicit in pi_test_and_set_on 8310 * (see vmx_deliver_posted_interrupt). 8311 * 8312 * 3) This also orders the write to mode from any reads to the page 8313 * tables done while the VCPU is running. Please see the comment 8314 * in kvm_flush_remote_tlbs. 8315 */ 8316 smp_mb__after_srcu_read_unlock(); 8317 8318 /* 8319 * This handles the case where a posted interrupt was 8320 * notified with kvm_vcpu_kick. 8321 */ 8322 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 8323 kvm_x86_ops->sync_pir_to_irr(vcpu); 8324 8325 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 8326 || need_resched() || signal_pending(current)) { 8327 vcpu->mode = OUTSIDE_GUEST_MODE; 8328 smp_wmb(); 8329 local_irq_enable(); 8330 preempt_enable(); 8331 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8332 r = 1; 8333 goto cancel_injection; 8334 } 8335 8336 if (req_immediate_exit) { 8337 kvm_make_request(KVM_REQ_EVENT, vcpu); 8338 kvm_x86_ops->request_immediate_exit(vcpu); 8339 } 8340 8341 trace_kvm_entry(vcpu->vcpu_id); 8342 guest_enter_irqoff(); 8343 8344 fpregs_assert_state_consistent(); 8345 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 8346 switch_fpu_return(); 8347 8348 if (unlikely(vcpu->arch.switch_db_regs)) { 8349 set_debugreg(0, 7); 8350 set_debugreg(vcpu->arch.eff_db[0], 0); 8351 set_debugreg(vcpu->arch.eff_db[1], 1); 8352 set_debugreg(vcpu->arch.eff_db[2], 2); 8353 set_debugreg(vcpu->arch.eff_db[3], 3); 8354 set_debugreg(vcpu->arch.dr6, 6); 8355 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 8356 } 8357 8358 kvm_x86_ops->run(vcpu); 8359 8360 /* 8361 * Do this here before restoring debug registers on the host. And 8362 * since we do this before handling the vmexit, a DR access vmexit 8363 * can (a) read the correct value of the debug registers, (b) set 8364 * KVM_DEBUGREG_WONT_EXIT again. 8365 */ 8366 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 8367 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 8368 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 8369 kvm_update_dr0123(vcpu); 8370 kvm_update_dr6(vcpu); 8371 kvm_update_dr7(vcpu); 8372 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 8373 } 8374 8375 /* 8376 * If the guest has used debug registers, at least dr7 8377 * will be disabled while returning to the host. 8378 * If we don't have active breakpoints in the host, we don't 8379 * care about the messed up debug address registers. But if 8380 * we have some of them active, restore the old state. 8381 */ 8382 if (hw_breakpoint_active()) 8383 hw_breakpoint_restore(); 8384 8385 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 8386 8387 vcpu->mode = OUTSIDE_GUEST_MODE; 8388 smp_wmb(); 8389 8390 kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath); 8391 8392 /* 8393 * Consume any pending interrupts, including the possible source of 8394 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 8395 * An instruction is required after local_irq_enable() to fully unblock 8396 * interrupts on processors that implement an interrupt shadow, the 8397 * stat.exits increment will do nicely. 8398 */ 8399 kvm_before_interrupt(vcpu); 8400 local_irq_enable(); 8401 ++vcpu->stat.exits; 8402 local_irq_disable(); 8403 kvm_after_interrupt(vcpu); 8404 8405 guest_exit_irqoff(); 8406 if (lapic_in_kernel(vcpu)) { 8407 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 8408 if (delta != S64_MIN) { 8409 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 8410 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 8411 } 8412 } 8413 8414 local_irq_enable(); 8415 preempt_enable(); 8416 8417 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8418 8419 /* 8420 * Profile KVM exit RIPs: 8421 */ 8422 if (unlikely(prof_on == KVM_PROFILING)) { 8423 unsigned long rip = kvm_rip_read(vcpu); 8424 profile_hit(KVM_PROFILING, (void *)rip); 8425 } 8426 8427 if (unlikely(vcpu->arch.tsc_always_catchup)) 8428 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8429 8430 if (vcpu->arch.apic_attention) 8431 kvm_lapic_sync_from_vapic(vcpu); 8432 8433 vcpu->arch.gpa_available = false; 8434 r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath); 8435 return r; 8436 8437 cancel_injection: 8438 kvm_x86_ops->cancel_injection(vcpu); 8439 if (unlikely(vcpu->arch.apic_attention)) 8440 kvm_lapic_sync_from_vapic(vcpu); 8441 out: 8442 return r; 8443 } 8444 8445 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 8446 { 8447 if (!kvm_arch_vcpu_runnable(vcpu) && 8448 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 8449 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8450 kvm_vcpu_block(vcpu); 8451 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8452 8453 if (kvm_x86_ops->post_block) 8454 kvm_x86_ops->post_block(vcpu); 8455 8456 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 8457 return 1; 8458 } 8459 8460 kvm_apic_accept_events(vcpu); 8461 switch(vcpu->arch.mp_state) { 8462 case KVM_MP_STATE_HALTED: 8463 vcpu->arch.pv.pv_unhalted = false; 8464 vcpu->arch.mp_state = 8465 KVM_MP_STATE_RUNNABLE; 8466 /* fall through */ 8467 case KVM_MP_STATE_RUNNABLE: 8468 vcpu->arch.apf.halted = false; 8469 break; 8470 case KVM_MP_STATE_INIT_RECEIVED: 8471 break; 8472 default: 8473 return -EINTR; 8474 break; 8475 } 8476 return 1; 8477 } 8478 8479 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 8480 { 8481 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8482 kvm_x86_ops->check_nested_events(vcpu, false); 8483 8484 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 8485 !vcpu->arch.apf.halted); 8486 } 8487 8488 static int vcpu_run(struct kvm_vcpu *vcpu) 8489 { 8490 int r; 8491 struct kvm *kvm = vcpu->kvm; 8492 8493 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8494 vcpu->arch.l1tf_flush_l1d = true; 8495 8496 for (;;) { 8497 if (kvm_vcpu_running(vcpu)) { 8498 r = vcpu_enter_guest(vcpu); 8499 } else { 8500 r = vcpu_block(kvm, vcpu); 8501 } 8502 8503 if (r <= 0) 8504 break; 8505 8506 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 8507 if (kvm_cpu_has_pending_timer(vcpu)) 8508 kvm_inject_pending_timer_irqs(vcpu); 8509 8510 if (dm_request_for_irq_injection(vcpu) && 8511 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 8512 r = 0; 8513 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 8514 ++vcpu->stat.request_irq_exits; 8515 break; 8516 } 8517 8518 kvm_check_async_pf_completion(vcpu); 8519 8520 if (signal_pending(current)) { 8521 r = -EINTR; 8522 vcpu->run->exit_reason = KVM_EXIT_INTR; 8523 ++vcpu->stat.signal_exits; 8524 break; 8525 } 8526 if (need_resched()) { 8527 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8528 cond_resched(); 8529 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8530 } 8531 } 8532 8533 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8534 8535 return r; 8536 } 8537 8538 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 8539 { 8540 int r; 8541 8542 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8543 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 8544 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8545 return r; 8546 } 8547 8548 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 8549 { 8550 BUG_ON(!vcpu->arch.pio.count); 8551 8552 return complete_emulated_io(vcpu); 8553 } 8554 8555 /* 8556 * Implements the following, as a state machine: 8557 * 8558 * read: 8559 * for each fragment 8560 * for each mmio piece in the fragment 8561 * write gpa, len 8562 * exit 8563 * copy data 8564 * execute insn 8565 * 8566 * write: 8567 * for each fragment 8568 * for each mmio piece in the fragment 8569 * write gpa, len 8570 * copy data 8571 * exit 8572 */ 8573 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 8574 { 8575 struct kvm_run *run = vcpu->run; 8576 struct kvm_mmio_fragment *frag; 8577 unsigned len; 8578 8579 BUG_ON(!vcpu->mmio_needed); 8580 8581 /* Complete previous fragment */ 8582 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 8583 len = min(8u, frag->len); 8584 if (!vcpu->mmio_is_write) 8585 memcpy(frag->data, run->mmio.data, len); 8586 8587 if (frag->len <= 8) { 8588 /* Switch to the next fragment. */ 8589 frag++; 8590 vcpu->mmio_cur_fragment++; 8591 } else { 8592 /* Go forward to the next mmio piece. */ 8593 frag->data += len; 8594 frag->gpa += len; 8595 frag->len -= len; 8596 } 8597 8598 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 8599 vcpu->mmio_needed = 0; 8600 8601 /* FIXME: return into emulator if single-stepping. */ 8602 if (vcpu->mmio_is_write) 8603 return 1; 8604 vcpu->mmio_read_completed = 1; 8605 return complete_emulated_io(vcpu); 8606 } 8607 8608 run->exit_reason = KVM_EXIT_MMIO; 8609 run->mmio.phys_addr = frag->gpa; 8610 if (vcpu->mmio_is_write) 8611 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 8612 run->mmio.len = min(8u, frag->len); 8613 run->mmio.is_write = vcpu->mmio_is_write; 8614 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8615 return 0; 8616 } 8617 8618 static void kvm_save_current_fpu(struct fpu *fpu) 8619 { 8620 /* 8621 * If the target FPU state is not resident in the CPU registers, just 8622 * memcpy() from current, else save CPU state directly to the target. 8623 */ 8624 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 8625 memcpy(&fpu->state, ¤t->thread.fpu.state, 8626 fpu_kernel_xstate_size); 8627 else 8628 copy_fpregs_to_fpstate(fpu); 8629 } 8630 8631 /* Swap (qemu) user FPU context for the guest FPU context. */ 8632 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8633 { 8634 fpregs_lock(); 8635 8636 kvm_save_current_fpu(vcpu->arch.user_fpu); 8637 8638 /* PKRU is separately restored in kvm_x86_ops->run. */ 8639 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 8640 ~XFEATURE_MASK_PKRU); 8641 8642 fpregs_mark_activate(); 8643 fpregs_unlock(); 8644 8645 trace_kvm_fpu(1); 8646 } 8647 8648 /* When vcpu_run ends, restore user space FPU context. */ 8649 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8650 { 8651 fpregs_lock(); 8652 8653 kvm_save_current_fpu(vcpu->arch.guest_fpu); 8654 8655 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); 8656 8657 fpregs_mark_activate(); 8658 fpregs_unlock(); 8659 8660 ++vcpu->stat.fpu_reload; 8661 trace_kvm_fpu(0); 8662 } 8663 8664 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 8665 { 8666 int r; 8667 8668 vcpu_load(vcpu); 8669 kvm_sigset_activate(vcpu); 8670 kvm_load_guest_fpu(vcpu); 8671 8672 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 8673 if (kvm_run->immediate_exit) { 8674 r = -EINTR; 8675 goto out; 8676 } 8677 kvm_vcpu_block(vcpu); 8678 kvm_apic_accept_events(vcpu); 8679 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 8680 r = -EAGAIN; 8681 if (signal_pending(current)) { 8682 r = -EINTR; 8683 vcpu->run->exit_reason = KVM_EXIT_INTR; 8684 ++vcpu->stat.signal_exits; 8685 } 8686 goto out; 8687 } 8688 8689 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 8690 r = -EINVAL; 8691 goto out; 8692 } 8693 8694 if (vcpu->run->kvm_dirty_regs) { 8695 r = sync_regs(vcpu); 8696 if (r != 0) 8697 goto out; 8698 } 8699 8700 /* re-sync apic's tpr */ 8701 if (!lapic_in_kernel(vcpu)) { 8702 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 8703 r = -EINVAL; 8704 goto out; 8705 } 8706 } 8707 8708 if (unlikely(vcpu->arch.complete_userspace_io)) { 8709 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 8710 vcpu->arch.complete_userspace_io = NULL; 8711 r = cui(vcpu); 8712 if (r <= 0) 8713 goto out; 8714 } else 8715 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 8716 8717 if (kvm_run->immediate_exit) 8718 r = -EINTR; 8719 else 8720 r = vcpu_run(vcpu); 8721 8722 out: 8723 kvm_put_guest_fpu(vcpu); 8724 if (vcpu->run->kvm_valid_regs) 8725 store_regs(vcpu); 8726 post_kvm_run_save(vcpu); 8727 kvm_sigset_deactivate(vcpu); 8728 8729 vcpu_put(vcpu); 8730 return r; 8731 } 8732 8733 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8734 { 8735 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 8736 /* 8737 * We are here if userspace calls get_regs() in the middle of 8738 * instruction emulation. Registers state needs to be copied 8739 * back from emulation context to vcpu. Userspace shouldn't do 8740 * that usually, but some bad designed PV devices (vmware 8741 * backdoor interface) need this to work 8742 */ 8743 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 8744 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8745 } 8746 regs->rax = kvm_rax_read(vcpu); 8747 regs->rbx = kvm_rbx_read(vcpu); 8748 regs->rcx = kvm_rcx_read(vcpu); 8749 regs->rdx = kvm_rdx_read(vcpu); 8750 regs->rsi = kvm_rsi_read(vcpu); 8751 regs->rdi = kvm_rdi_read(vcpu); 8752 regs->rsp = kvm_rsp_read(vcpu); 8753 regs->rbp = kvm_rbp_read(vcpu); 8754 #ifdef CONFIG_X86_64 8755 regs->r8 = kvm_r8_read(vcpu); 8756 regs->r9 = kvm_r9_read(vcpu); 8757 regs->r10 = kvm_r10_read(vcpu); 8758 regs->r11 = kvm_r11_read(vcpu); 8759 regs->r12 = kvm_r12_read(vcpu); 8760 regs->r13 = kvm_r13_read(vcpu); 8761 regs->r14 = kvm_r14_read(vcpu); 8762 regs->r15 = kvm_r15_read(vcpu); 8763 #endif 8764 8765 regs->rip = kvm_rip_read(vcpu); 8766 regs->rflags = kvm_get_rflags(vcpu); 8767 } 8768 8769 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8770 { 8771 vcpu_load(vcpu); 8772 __get_regs(vcpu, regs); 8773 vcpu_put(vcpu); 8774 return 0; 8775 } 8776 8777 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8778 { 8779 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 8780 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8781 8782 kvm_rax_write(vcpu, regs->rax); 8783 kvm_rbx_write(vcpu, regs->rbx); 8784 kvm_rcx_write(vcpu, regs->rcx); 8785 kvm_rdx_write(vcpu, regs->rdx); 8786 kvm_rsi_write(vcpu, regs->rsi); 8787 kvm_rdi_write(vcpu, regs->rdi); 8788 kvm_rsp_write(vcpu, regs->rsp); 8789 kvm_rbp_write(vcpu, regs->rbp); 8790 #ifdef CONFIG_X86_64 8791 kvm_r8_write(vcpu, regs->r8); 8792 kvm_r9_write(vcpu, regs->r9); 8793 kvm_r10_write(vcpu, regs->r10); 8794 kvm_r11_write(vcpu, regs->r11); 8795 kvm_r12_write(vcpu, regs->r12); 8796 kvm_r13_write(vcpu, regs->r13); 8797 kvm_r14_write(vcpu, regs->r14); 8798 kvm_r15_write(vcpu, regs->r15); 8799 #endif 8800 8801 kvm_rip_write(vcpu, regs->rip); 8802 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 8803 8804 vcpu->arch.exception.pending = false; 8805 8806 kvm_make_request(KVM_REQ_EVENT, vcpu); 8807 } 8808 8809 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8810 { 8811 vcpu_load(vcpu); 8812 __set_regs(vcpu, regs); 8813 vcpu_put(vcpu); 8814 return 0; 8815 } 8816 8817 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 8818 { 8819 struct kvm_segment cs; 8820 8821 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8822 *db = cs.db; 8823 *l = cs.l; 8824 } 8825 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 8826 8827 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8828 { 8829 struct desc_ptr dt; 8830 8831 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8832 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8833 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8834 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8835 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8836 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8837 8838 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8839 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8840 8841 kvm_x86_ops->get_idt(vcpu, &dt); 8842 sregs->idt.limit = dt.size; 8843 sregs->idt.base = dt.address; 8844 kvm_x86_ops->get_gdt(vcpu, &dt); 8845 sregs->gdt.limit = dt.size; 8846 sregs->gdt.base = dt.address; 8847 8848 sregs->cr0 = kvm_read_cr0(vcpu); 8849 sregs->cr2 = vcpu->arch.cr2; 8850 sregs->cr3 = kvm_read_cr3(vcpu); 8851 sregs->cr4 = kvm_read_cr4(vcpu); 8852 sregs->cr8 = kvm_get_cr8(vcpu); 8853 sregs->efer = vcpu->arch.efer; 8854 sregs->apic_base = kvm_get_apic_base(vcpu); 8855 8856 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 8857 8858 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 8859 set_bit(vcpu->arch.interrupt.nr, 8860 (unsigned long *)sregs->interrupt_bitmap); 8861 } 8862 8863 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 8864 struct kvm_sregs *sregs) 8865 { 8866 vcpu_load(vcpu); 8867 __get_sregs(vcpu, sregs); 8868 vcpu_put(vcpu); 8869 return 0; 8870 } 8871 8872 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 8873 struct kvm_mp_state *mp_state) 8874 { 8875 vcpu_load(vcpu); 8876 if (kvm_mpx_supported()) 8877 kvm_load_guest_fpu(vcpu); 8878 8879 kvm_apic_accept_events(vcpu); 8880 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 8881 vcpu->arch.pv.pv_unhalted) 8882 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 8883 else 8884 mp_state->mp_state = vcpu->arch.mp_state; 8885 8886 if (kvm_mpx_supported()) 8887 kvm_put_guest_fpu(vcpu); 8888 vcpu_put(vcpu); 8889 return 0; 8890 } 8891 8892 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 8893 struct kvm_mp_state *mp_state) 8894 { 8895 int ret = -EINVAL; 8896 8897 vcpu_load(vcpu); 8898 8899 if (!lapic_in_kernel(vcpu) && 8900 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 8901 goto out; 8902 8903 /* 8904 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 8905 * INIT state; latched init should be reported using 8906 * KVM_SET_VCPU_EVENTS, so reject it here. 8907 */ 8908 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 8909 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 8910 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 8911 goto out; 8912 8913 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 8914 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 8915 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 8916 } else 8917 vcpu->arch.mp_state = mp_state->mp_state; 8918 kvm_make_request(KVM_REQ_EVENT, vcpu); 8919 8920 ret = 0; 8921 out: 8922 vcpu_put(vcpu); 8923 return ret; 8924 } 8925 8926 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 8927 int reason, bool has_error_code, u32 error_code) 8928 { 8929 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 8930 int ret; 8931 8932 init_emulate_ctxt(vcpu); 8933 8934 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 8935 has_error_code, error_code); 8936 if (ret) { 8937 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8938 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 8939 vcpu->run->internal.ndata = 0; 8940 return 0; 8941 } 8942 8943 kvm_rip_write(vcpu, ctxt->eip); 8944 kvm_set_rflags(vcpu, ctxt->eflags); 8945 kvm_make_request(KVM_REQ_EVENT, vcpu); 8946 return 1; 8947 } 8948 EXPORT_SYMBOL_GPL(kvm_task_switch); 8949 8950 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8951 { 8952 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 8953 /* 8954 * When EFER.LME and CR0.PG are set, the processor is in 8955 * 64-bit mode (though maybe in a 32-bit code segment). 8956 * CR4.PAE and EFER.LMA must be set. 8957 */ 8958 if (!(sregs->cr4 & X86_CR4_PAE) 8959 || !(sregs->efer & EFER_LMA)) 8960 return -EINVAL; 8961 } else { 8962 /* 8963 * Not in 64-bit mode: EFER.LMA is clear and the code 8964 * segment cannot be 64-bit. 8965 */ 8966 if (sregs->efer & EFER_LMA || sregs->cs.l) 8967 return -EINVAL; 8968 } 8969 8970 return kvm_valid_cr4(vcpu, sregs->cr4); 8971 } 8972 8973 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8974 { 8975 struct msr_data apic_base_msr; 8976 int mmu_reset_needed = 0; 8977 int cpuid_update_needed = 0; 8978 int pending_vec, max_bits, idx; 8979 struct desc_ptr dt; 8980 int ret = -EINVAL; 8981 8982 if (kvm_valid_sregs(vcpu, sregs)) 8983 goto out; 8984 8985 apic_base_msr.data = sregs->apic_base; 8986 apic_base_msr.host_initiated = true; 8987 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 8988 goto out; 8989 8990 dt.size = sregs->idt.limit; 8991 dt.address = sregs->idt.base; 8992 kvm_x86_ops->set_idt(vcpu, &dt); 8993 dt.size = sregs->gdt.limit; 8994 dt.address = sregs->gdt.base; 8995 kvm_x86_ops->set_gdt(vcpu, &dt); 8996 8997 vcpu->arch.cr2 = sregs->cr2; 8998 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 8999 vcpu->arch.cr3 = sregs->cr3; 9000 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 9001 9002 kvm_set_cr8(vcpu, sregs->cr8); 9003 9004 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 9005 kvm_x86_ops->set_efer(vcpu, sregs->efer); 9006 9007 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 9008 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 9009 vcpu->arch.cr0 = sregs->cr0; 9010 9011 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 9012 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & 9013 (X86_CR4_OSXSAVE | X86_CR4_PKE)); 9014 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 9015 if (cpuid_update_needed) 9016 kvm_update_cpuid(vcpu); 9017 9018 idx = srcu_read_lock(&vcpu->kvm->srcu); 9019 if (is_pae_paging(vcpu)) { 9020 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 9021 mmu_reset_needed = 1; 9022 } 9023 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9024 9025 if (mmu_reset_needed) 9026 kvm_mmu_reset_context(vcpu); 9027 9028 max_bits = KVM_NR_INTERRUPTS; 9029 pending_vec = find_first_bit( 9030 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 9031 if (pending_vec < max_bits) { 9032 kvm_queue_interrupt(vcpu, pending_vec, false); 9033 pr_debug("Set back pending irq %d\n", pending_vec); 9034 } 9035 9036 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9037 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9038 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9039 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9040 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9041 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9042 9043 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9044 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9045 9046 update_cr8_intercept(vcpu); 9047 9048 /* Older userspace won't unhalt the vcpu on reset. */ 9049 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 9050 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 9051 !is_protmode(vcpu)) 9052 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9053 9054 kvm_make_request(KVM_REQ_EVENT, vcpu); 9055 9056 ret = 0; 9057 out: 9058 return ret; 9059 } 9060 9061 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 9062 struct kvm_sregs *sregs) 9063 { 9064 int ret; 9065 9066 vcpu_load(vcpu); 9067 ret = __set_sregs(vcpu, sregs); 9068 vcpu_put(vcpu); 9069 return ret; 9070 } 9071 9072 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 9073 struct kvm_guest_debug *dbg) 9074 { 9075 unsigned long rflags; 9076 int i, r; 9077 9078 vcpu_load(vcpu); 9079 9080 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 9081 r = -EBUSY; 9082 if (vcpu->arch.exception.pending) 9083 goto out; 9084 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 9085 kvm_queue_exception(vcpu, DB_VECTOR); 9086 else 9087 kvm_queue_exception(vcpu, BP_VECTOR); 9088 } 9089 9090 /* 9091 * Read rflags as long as potentially injected trace flags are still 9092 * filtered out. 9093 */ 9094 rflags = kvm_get_rflags(vcpu); 9095 9096 vcpu->guest_debug = dbg->control; 9097 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 9098 vcpu->guest_debug = 0; 9099 9100 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 9101 for (i = 0; i < KVM_NR_DB_REGS; ++i) 9102 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 9103 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 9104 } else { 9105 for (i = 0; i < KVM_NR_DB_REGS; i++) 9106 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 9107 } 9108 kvm_update_dr7(vcpu); 9109 9110 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9111 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 9112 get_segment_base(vcpu, VCPU_SREG_CS); 9113 9114 /* 9115 * Trigger an rflags update that will inject or remove the trace 9116 * flags. 9117 */ 9118 kvm_set_rflags(vcpu, rflags); 9119 9120 kvm_x86_ops->update_bp_intercept(vcpu); 9121 9122 r = 0; 9123 9124 out: 9125 vcpu_put(vcpu); 9126 return r; 9127 } 9128 9129 /* 9130 * Translate a guest virtual address to a guest physical address. 9131 */ 9132 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 9133 struct kvm_translation *tr) 9134 { 9135 unsigned long vaddr = tr->linear_address; 9136 gpa_t gpa; 9137 int idx; 9138 9139 vcpu_load(vcpu); 9140 9141 idx = srcu_read_lock(&vcpu->kvm->srcu); 9142 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 9143 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9144 tr->physical_address = gpa; 9145 tr->valid = gpa != UNMAPPED_GVA; 9146 tr->writeable = 1; 9147 tr->usermode = 0; 9148 9149 vcpu_put(vcpu); 9150 return 0; 9151 } 9152 9153 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9154 { 9155 struct fxregs_state *fxsave; 9156 9157 vcpu_load(vcpu); 9158 9159 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9160 memcpy(fpu->fpr, fxsave->st_space, 128); 9161 fpu->fcw = fxsave->cwd; 9162 fpu->fsw = fxsave->swd; 9163 fpu->ftwx = fxsave->twd; 9164 fpu->last_opcode = fxsave->fop; 9165 fpu->last_ip = fxsave->rip; 9166 fpu->last_dp = fxsave->rdp; 9167 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 9168 9169 vcpu_put(vcpu); 9170 return 0; 9171 } 9172 9173 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9174 { 9175 struct fxregs_state *fxsave; 9176 9177 vcpu_load(vcpu); 9178 9179 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9180 9181 memcpy(fxsave->st_space, fpu->fpr, 128); 9182 fxsave->cwd = fpu->fcw; 9183 fxsave->swd = fpu->fsw; 9184 fxsave->twd = fpu->ftwx; 9185 fxsave->fop = fpu->last_opcode; 9186 fxsave->rip = fpu->last_ip; 9187 fxsave->rdp = fpu->last_dp; 9188 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 9189 9190 vcpu_put(vcpu); 9191 return 0; 9192 } 9193 9194 static void store_regs(struct kvm_vcpu *vcpu) 9195 { 9196 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 9197 9198 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 9199 __get_regs(vcpu, &vcpu->run->s.regs.regs); 9200 9201 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 9202 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 9203 9204 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 9205 kvm_vcpu_ioctl_x86_get_vcpu_events( 9206 vcpu, &vcpu->run->s.regs.events); 9207 } 9208 9209 static int sync_regs(struct kvm_vcpu *vcpu) 9210 { 9211 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 9212 return -EINVAL; 9213 9214 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 9215 __set_regs(vcpu, &vcpu->run->s.regs.regs); 9216 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 9217 } 9218 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 9219 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 9220 return -EINVAL; 9221 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 9222 } 9223 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 9224 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 9225 vcpu, &vcpu->run->s.regs.events)) 9226 return -EINVAL; 9227 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 9228 } 9229 9230 return 0; 9231 } 9232 9233 static void fx_init(struct kvm_vcpu *vcpu) 9234 { 9235 fpstate_init(&vcpu->arch.guest_fpu->state); 9236 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9237 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 9238 host_xcr0 | XSTATE_COMPACTION_ENABLED; 9239 9240 /* 9241 * Ensure guest xcr0 is valid for loading 9242 */ 9243 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 9244 9245 vcpu->arch.cr0 |= X86_CR0_ET; 9246 } 9247 9248 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 9249 { 9250 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 9251 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 9252 "guest TSC will not be reliable\n"); 9253 9254 return 0; 9255 } 9256 9257 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 9258 { 9259 struct page *page; 9260 int r; 9261 9262 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 9263 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 9264 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9265 else 9266 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 9267 9268 kvm_set_tsc_khz(vcpu, max_tsc_khz); 9269 9270 r = kvm_mmu_create(vcpu); 9271 if (r < 0) 9272 return r; 9273 9274 if (irqchip_in_kernel(vcpu->kvm)) { 9275 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 9276 if (r < 0) 9277 goto fail_mmu_destroy; 9278 if (kvm_apicv_activated(vcpu->kvm)) 9279 vcpu->arch.apicv_active = true; 9280 } else 9281 static_key_slow_inc(&kvm_no_apic_vcpu); 9282 9283 r = -ENOMEM; 9284 9285 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 9286 if (!page) 9287 goto fail_free_lapic; 9288 vcpu->arch.pio_data = page_address(page); 9289 9290 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 9291 GFP_KERNEL_ACCOUNT); 9292 if (!vcpu->arch.mce_banks) 9293 goto fail_free_pio_data; 9294 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 9295 9296 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 9297 GFP_KERNEL_ACCOUNT)) 9298 goto fail_free_mce_banks; 9299 9300 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 9301 GFP_KERNEL_ACCOUNT); 9302 if (!vcpu->arch.user_fpu) { 9303 pr_err("kvm: failed to allocate userspace's fpu\n"); 9304 goto free_wbinvd_dirty_mask; 9305 } 9306 9307 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 9308 GFP_KERNEL_ACCOUNT); 9309 if (!vcpu->arch.guest_fpu) { 9310 pr_err("kvm: failed to allocate vcpu's fpu\n"); 9311 goto free_user_fpu; 9312 } 9313 fx_init(vcpu); 9314 9315 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 9316 9317 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 9318 9319 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 9320 9321 kvm_async_pf_hash_reset(vcpu); 9322 kvm_pmu_init(vcpu); 9323 9324 vcpu->arch.pending_external_vector = -1; 9325 vcpu->arch.preempted_in_kernel = false; 9326 9327 kvm_hv_vcpu_init(vcpu); 9328 9329 r = kvm_x86_ops->vcpu_create(vcpu); 9330 if (r) 9331 goto free_guest_fpu; 9332 9333 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 9334 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 9335 kvm_vcpu_mtrr_init(vcpu); 9336 vcpu_load(vcpu); 9337 kvm_vcpu_reset(vcpu, false); 9338 kvm_init_mmu(vcpu, false); 9339 vcpu_put(vcpu); 9340 return 0; 9341 9342 free_guest_fpu: 9343 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 9344 free_user_fpu: 9345 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 9346 free_wbinvd_dirty_mask: 9347 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 9348 fail_free_mce_banks: 9349 kfree(vcpu->arch.mce_banks); 9350 fail_free_pio_data: 9351 free_page((unsigned long)vcpu->arch.pio_data); 9352 fail_free_lapic: 9353 kvm_free_lapic(vcpu); 9354 fail_mmu_destroy: 9355 kvm_mmu_destroy(vcpu); 9356 return r; 9357 } 9358 9359 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 9360 { 9361 struct msr_data msr; 9362 struct kvm *kvm = vcpu->kvm; 9363 9364 kvm_hv_vcpu_postcreate(vcpu); 9365 9366 if (mutex_lock_killable(&vcpu->mutex)) 9367 return; 9368 vcpu_load(vcpu); 9369 msr.data = 0x0; 9370 msr.index = MSR_IA32_TSC; 9371 msr.host_initiated = true; 9372 kvm_write_tsc(vcpu, &msr); 9373 vcpu_put(vcpu); 9374 9375 /* poll control enabled by default */ 9376 vcpu->arch.msr_kvm_poll_control = 1; 9377 9378 mutex_unlock(&vcpu->mutex); 9379 9380 if (!kvmclock_periodic_sync) 9381 return; 9382 9383 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 9384 KVMCLOCK_SYNC_PERIOD); 9385 } 9386 9387 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 9388 { 9389 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 9390 int idx; 9391 9392 kvm_release_pfn(cache->pfn, cache->dirty, cache); 9393 9394 kvmclock_reset(vcpu); 9395 9396 kvm_x86_ops->vcpu_free(vcpu); 9397 9398 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 9399 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 9400 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 9401 9402 kvm_hv_vcpu_uninit(vcpu); 9403 kvm_pmu_destroy(vcpu); 9404 kfree(vcpu->arch.mce_banks); 9405 kvm_free_lapic(vcpu); 9406 idx = srcu_read_lock(&vcpu->kvm->srcu); 9407 kvm_mmu_destroy(vcpu); 9408 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9409 free_page((unsigned long)vcpu->arch.pio_data); 9410 if (!lapic_in_kernel(vcpu)) 9411 static_key_slow_dec(&kvm_no_apic_vcpu); 9412 } 9413 9414 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 9415 { 9416 kvm_lapic_reset(vcpu, init_event); 9417 9418 vcpu->arch.hflags = 0; 9419 9420 vcpu->arch.smi_pending = 0; 9421 vcpu->arch.smi_count = 0; 9422 atomic_set(&vcpu->arch.nmi_queued, 0); 9423 vcpu->arch.nmi_pending = 0; 9424 vcpu->arch.nmi_injected = false; 9425 kvm_clear_interrupt_queue(vcpu); 9426 kvm_clear_exception_queue(vcpu); 9427 9428 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 9429 kvm_update_dr0123(vcpu); 9430 vcpu->arch.dr6 = DR6_INIT; 9431 kvm_update_dr6(vcpu); 9432 vcpu->arch.dr7 = DR7_FIXED_1; 9433 kvm_update_dr7(vcpu); 9434 9435 vcpu->arch.cr2 = 0; 9436 9437 kvm_make_request(KVM_REQ_EVENT, vcpu); 9438 vcpu->arch.apf.msr_val = 0; 9439 vcpu->arch.st.msr_val = 0; 9440 9441 kvmclock_reset(vcpu); 9442 9443 kvm_clear_async_pf_completion_queue(vcpu); 9444 kvm_async_pf_hash_reset(vcpu); 9445 vcpu->arch.apf.halted = false; 9446 9447 if (kvm_mpx_supported()) { 9448 void *mpx_state_buffer; 9449 9450 /* 9451 * To avoid have the INIT path from kvm_apic_has_events() that be 9452 * called with loaded FPU and does not let userspace fix the state. 9453 */ 9454 if (init_event) 9455 kvm_put_guest_fpu(vcpu); 9456 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 9457 XFEATURE_BNDREGS); 9458 if (mpx_state_buffer) 9459 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 9460 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 9461 XFEATURE_BNDCSR); 9462 if (mpx_state_buffer) 9463 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 9464 if (init_event) 9465 kvm_load_guest_fpu(vcpu); 9466 } 9467 9468 if (!init_event) { 9469 kvm_pmu_reset(vcpu); 9470 vcpu->arch.smbase = 0x30000; 9471 9472 vcpu->arch.msr_misc_features_enables = 0; 9473 9474 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 9475 } 9476 9477 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 9478 vcpu->arch.regs_avail = ~0; 9479 vcpu->arch.regs_dirty = ~0; 9480 9481 vcpu->arch.ia32_xss = 0; 9482 9483 kvm_x86_ops->vcpu_reset(vcpu, init_event); 9484 } 9485 9486 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 9487 { 9488 struct kvm_segment cs; 9489 9490 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9491 cs.selector = vector << 8; 9492 cs.base = vector << 12; 9493 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9494 kvm_rip_write(vcpu, 0); 9495 } 9496 9497 int kvm_arch_hardware_enable(void) 9498 { 9499 struct kvm *kvm; 9500 struct kvm_vcpu *vcpu; 9501 int i; 9502 int ret; 9503 u64 local_tsc; 9504 u64 max_tsc = 0; 9505 bool stable, backwards_tsc = false; 9506 9507 kvm_shared_msr_cpu_online(); 9508 ret = kvm_x86_ops->hardware_enable(); 9509 if (ret != 0) 9510 return ret; 9511 9512 local_tsc = rdtsc(); 9513 stable = !kvm_check_tsc_unstable(); 9514 list_for_each_entry(kvm, &vm_list, vm_list) { 9515 kvm_for_each_vcpu(i, vcpu, kvm) { 9516 if (!stable && vcpu->cpu == smp_processor_id()) 9517 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9518 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 9519 backwards_tsc = true; 9520 if (vcpu->arch.last_host_tsc > max_tsc) 9521 max_tsc = vcpu->arch.last_host_tsc; 9522 } 9523 } 9524 } 9525 9526 /* 9527 * Sometimes, even reliable TSCs go backwards. This happens on 9528 * platforms that reset TSC during suspend or hibernate actions, but 9529 * maintain synchronization. We must compensate. Fortunately, we can 9530 * detect that condition here, which happens early in CPU bringup, 9531 * before any KVM threads can be running. Unfortunately, we can't 9532 * bring the TSCs fully up to date with real time, as we aren't yet far 9533 * enough into CPU bringup that we know how much real time has actually 9534 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 9535 * variables that haven't been updated yet. 9536 * 9537 * So we simply find the maximum observed TSC above, then record the 9538 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 9539 * the adjustment will be applied. Note that we accumulate 9540 * adjustments, in case multiple suspend cycles happen before some VCPU 9541 * gets a chance to run again. In the event that no KVM threads get a 9542 * chance to run, we will miss the entire elapsed period, as we'll have 9543 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 9544 * loose cycle time. This isn't too big a deal, since the loss will be 9545 * uniform across all VCPUs (not to mention the scenario is extremely 9546 * unlikely). It is possible that a second hibernate recovery happens 9547 * much faster than a first, causing the observed TSC here to be 9548 * smaller; this would require additional padding adjustment, which is 9549 * why we set last_host_tsc to the local tsc observed here. 9550 * 9551 * N.B. - this code below runs only on platforms with reliable TSC, 9552 * as that is the only way backwards_tsc is set above. Also note 9553 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 9554 * have the same delta_cyc adjustment applied if backwards_tsc 9555 * is detected. Note further, this adjustment is only done once, 9556 * as we reset last_host_tsc on all VCPUs to stop this from being 9557 * called multiple times (one for each physical CPU bringup). 9558 * 9559 * Platforms with unreliable TSCs don't have to deal with this, they 9560 * will be compensated by the logic in vcpu_load, which sets the TSC to 9561 * catchup mode. This will catchup all VCPUs to real time, but cannot 9562 * guarantee that they stay in perfect synchronization. 9563 */ 9564 if (backwards_tsc) { 9565 u64 delta_cyc = max_tsc - local_tsc; 9566 list_for_each_entry(kvm, &vm_list, vm_list) { 9567 kvm->arch.backwards_tsc_observed = true; 9568 kvm_for_each_vcpu(i, vcpu, kvm) { 9569 vcpu->arch.tsc_offset_adjustment += delta_cyc; 9570 vcpu->arch.last_host_tsc = local_tsc; 9571 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 9572 } 9573 9574 /* 9575 * We have to disable TSC offset matching.. if you were 9576 * booting a VM while issuing an S4 host suspend.... 9577 * you may have some problem. Solving this issue is 9578 * left as an exercise to the reader. 9579 */ 9580 kvm->arch.last_tsc_nsec = 0; 9581 kvm->arch.last_tsc_write = 0; 9582 } 9583 9584 } 9585 return 0; 9586 } 9587 9588 void kvm_arch_hardware_disable(void) 9589 { 9590 kvm_x86_ops->hardware_disable(); 9591 drop_user_return_notifiers(); 9592 } 9593 9594 int kvm_arch_hardware_setup(void) 9595 { 9596 int r; 9597 9598 r = kvm_x86_ops->hardware_setup(); 9599 if (r != 0) 9600 return r; 9601 9602 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data); 9603 9604 if (kvm_has_tsc_control) { 9605 /* 9606 * Make sure the user can only configure tsc_khz values that 9607 * fit into a signed integer. 9608 * A min value is not calculated because it will always 9609 * be 1 on all machines. 9610 */ 9611 u64 max = min(0x7fffffffULL, 9612 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 9613 kvm_max_guest_tsc_khz = max; 9614 9615 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 9616 } 9617 9618 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9619 rdmsrl(MSR_IA32_XSS, host_xss); 9620 9621 kvm_init_msr_list(); 9622 return 0; 9623 } 9624 9625 void kvm_arch_hardware_unsetup(void) 9626 { 9627 kvm_x86_ops->hardware_unsetup(); 9628 } 9629 9630 int kvm_arch_check_processor_compat(void) 9631 { 9632 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 9633 9634 WARN_ON(!irqs_disabled()); 9635 9636 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits) 9637 return -EIO; 9638 9639 return kvm_x86_ops->check_processor_compatibility(); 9640 } 9641 9642 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 9643 { 9644 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 9645 } 9646 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 9647 9648 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 9649 { 9650 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 9651 } 9652 9653 struct static_key kvm_no_apic_vcpu __read_mostly; 9654 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 9655 9656 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 9657 { 9658 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 9659 9660 vcpu->arch.l1tf_flush_l1d = true; 9661 if (pmu->version && unlikely(pmu->event_count)) { 9662 pmu->need_cleanup = true; 9663 kvm_make_request(KVM_REQ_PMU, vcpu); 9664 } 9665 kvm_x86_ops->sched_in(vcpu, cpu); 9666 } 9667 9668 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 9669 { 9670 if (type) 9671 return -EINVAL; 9672 9673 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 9674 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 9675 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 9676 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 9677 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 9678 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 9679 9680 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 9681 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 9682 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 9683 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 9684 &kvm->arch.irq_sources_bitmap); 9685 9686 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 9687 mutex_init(&kvm->arch.apic_map_lock); 9688 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 9689 9690 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 9691 pvclock_update_vm_gtod_copy(kvm); 9692 9693 kvm->arch.guest_can_read_msr_platform_info = true; 9694 9695 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 9696 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 9697 9698 kvm_hv_init_vm(kvm); 9699 kvm_page_track_init(kvm); 9700 kvm_mmu_init_vm(kvm); 9701 9702 return kvm_x86_ops->vm_init(kvm); 9703 } 9704 9705 int kvm_arch_post_init_vm(struct kvm *kvm) 9706 { 9707 return kvm_mmu_post_init_vm(kvm); 9708 } 9709 9710 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 9711 { 9712 vcpu_load(vcpu); 9713 kvm_mmu_unload(vcpu); 9714 vcpu_put(vcpu); 9715 } 9716 9717 static void kvm_free_vcpus(struct kvm *kvm) 9718 { 9719 unsigned int i; 9720 struct kvm_vcpu *vcpu; 9721 9722 /* 9723 * Unpin any mmu pages first. 9724 */ 9725 kvm_for_each_vcpu(i, vcpu, kvm) { 9726 kvm_clear_async_pf_completion_queue(vcpu); 9727 kvm_unload_vcpu_mmu(vcpu); 9728 } 9729 kvm_for_each_vcpu(i, vcpu, kvm) 9730 kvm_vcpu_destroy(vcpu); 9731 9732 mutex_lock(&kvm->lock); 9733 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 9734 kvm->vcpus[i] = NULL; 9735 9736 atomic_set(&kvm->online_vcpus, 0); 9737 mutex_unlock(&kvm->lock); 9738 } 9739 9740 void kvm_arch_sync_events(struct kvm *kvm) 9741 { 9742 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 9743 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 9744 kvm_free_pit(kvm); 9745 } 9746 9747 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9748 { 9749 int i, r; 9750 unsigned long hva; 9751 struct kvm_memslots *slots = kvm_memslots(kvm); 9752 struct kvm_memory_slot *slot, old; 9753 9754 /* Called with kvm->slots_lock held. */ 9755 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 9756 return -EINVAL; 9757 9758 slot = id_to_memslot(slots, id); 9759 if (size) { 9760 if (slot->npages) 9761 return -EEXIST; 9762 9763 /* 9764 * MAP_SHARED to prevent internal slot pages from being moved 9765 * by fork()/COW. 9766 */ 9767 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 9768 MAP_SHARED | MAP_ANONYMOUS, 0); 9769 if (IS_ERR((void *)hva)) 9770 return PTR_ERR((void *)hva); 9771 } else { 9772 if (!slot->npages) 9773 return 0; 9774 9775 hva = 0; 9776 } 9777 9778 old = *slot; 9779 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 9780 struct kvm_userspace_memory_region m; 9781 9782 m.slot = id | (i << 16); 9783 m.flags = 0; 9784 m.guest_phys_addr = gpa; 9785 m.userspace_addr = hva; 9786 m.memory_size = size; 9787 r = __kvm_set_memory_region(kvm, &m); 9788 if (r < 0) 9789 return r; 9790 } 9791 9792 if (!size) 9793 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 9794 9795 return 0; 9796 } 9797 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 9798 9799 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 9800 { 9801 kvm_mmu_pre_destroy_vm(kvm); 9802 } 9803 9804 void kvm_arch_destroy_vm(struct kvm *kvm) 9805 { 9806 if (current->mm == kvm->mm) { 9807 /* 9808 * Free memory regions allocated on behalf of userspace, 9809 * unless the the memory map has changed due to process exit 9810 * or fd copying. 9811 */ 9812 mutex_lock(&kvm->slots_lock); 9813 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 9814 0, 0); 9815 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 9816 0, 0); 9817 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 9818 mutex_unlock(&kvm->slots_lock); 9819 } 9820 if (kvm_x86_ops->vm_destroy) 9821 kvm_x86_ops->vm_destroy(kvm); 9822 kvm_pic_destroy(kvm); 9823 kvm_ioapic_destroy(kvm); 9824 kvm_free_vcpus(kvm); 9825 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 9826 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 9827 kvm_mmu_uninit_vm(kvm); 9828 kvm_page_track_cleanup(kvm); 9829 kvm_hv_destroy_vm(kvm); 9830 } 9831 9832 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 9833 struct kvm_memory_slot *dont) 9834 { 9835 int i; 9836 9837 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9838 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 9839 kvfree(free->arch.rmap[i]); 9840 free->arch.rmap[i] = NULL; 9841 } 9842 if (i == 0) 9843 continue; 9844 9845 if (!dont || free->arch.lpage_info[i - 1] != 9846 dont->arch.lpage_info[i - 1]) { 9847 kvfree(free->arch.lpage_info[i - 1]); 9848 free->arch.lpage_info[i - 1] = NULL; 9849 } 9850 } 9851 9852 kvm_page_track_free_memslot(free, dont); 9853 } 9854 9855 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 9856 unsigned long npages) 9857 { 9858 int i; 9859 9860 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9861 struct kvm_lpage_info *linfo; 9862 unsigned long ugfn; 9863 int lpages; 9864 int level = i + 1; 9865 9866 lpages = gfn_to_index(slot->base_gfn + npages - 1, 9867 slot->base_gfn, level) + 1; 9868 9869 slot->arch.rmap[i] = 9870 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 9871 GFP_KERNEL_ACCOUNT); 9872 if (!slot->arch.rmap[i]) 9873 goto out_free; 9874 if (i == 0) 9875 continue; 9876 9877 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 9878 if (!linfo) 9879 goto out_free; 9880 9881 slot->arch.lpage_info[i - 1] = linfo; 9882 9883 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 9884 linfo[0].disallow_lpage = 1; 9885 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 9886 linfo[lpages - 1].disallow_lpage = 1; 9887 ugfn = slot->userspace_addr >> PAGE_SHIFT; 9888 /* 9889 * If the gfn and userspace address are not aligned wrt each 9890 * other, or if explicitly asked to, disable large page 9891 * support for this slot 9892 */ 9893 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 9894 !kvm_largepages_enabled()) { 9895 unsigned long j; 9896 9897 for (j = 0; j < lpages; ++j) 9898 linfo[j].disallow_lpage = 1; 9899 } 9900 } 9901 9902 if (kvm_page_track_create_memslot(slot, npages)) 9903 goto out_free; 9904 9905 return 0; 9906 9907 out_free: 9908 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9909 kvfree(slot->arch.rmap[i]); 9910 slot->arch.rmap[i] = NULL; 9911 if (i == 0) 9912 continue; 9913 9914 kvfree(slot->arch.lpage_info[i - 1]); 9915 slot->arch.lpage_info[i - 1] = NULL; 9916 } 9917 return -ENOMEM; 9918 } 9919 9920 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 9921 { 9922 struct kvm_vcpu *vcpu; 9923 int i; 9924 9925 /* 9926 * memslots->generation has been incremented. 9927 * mmio generation may have reached its maximum value. 9928 */ 9929 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 9930 9931 /* Force re-initialization of steal_time cache */ 9932 kvm_for_each_vcpu(i, vcpu, kvm) 9933 kvm_vcpu_kick(vcpu); 9934 } 9935 9936 int kvm_arch_prepare_memory_region(struct kvm *kvm, 9937 struct kvm_memory_slot *memslot, 9938 const struct kvm_userspace_memory_region *mem, 9939 enum kvm_mr_change change) 9940 { 9941 return 0; 9942 } 9943 9944 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 9945 struct kvm_memory_slot *new) 9946 { 9947 /* Still write protect RO slot */ 9948 if (new->flags & KVM_MEM_READONLY) { 9949 kvm_mmu_slot_remove_write_access(kvm, new); 9950 return; 9951 } 9952 9953 /* 9954 * Call kvm_x86_ops dirty logging hooks when they are valid. 9955 * 9956 * kvm_x86_ops->slot_disable_log_dirty is called when: 9957 * 9958 * - KVM_MR_CREATE with dirty logging is disabled 9959 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 9960 * 9961 * The reason is, in case of PML, we need to set D-bit for any slots 9962 * with dirty logging disabled in order to eliminate unnecessary GPA 9963 * logging in PML buffer (and potential PML buffer full VMEXIT). This 9964 * guarantees leaving PML enabled during guest's lifetime won't have 9965 * any additional overhead from PML when guest is running with dirty 9966 * logging disabled for memory slots. 9967 * 9968 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 9969 * to dirty logging mode. 9970 * 9971 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 9972 * 9973 * In case of write protect: 9974 * 9975 * Write protect all pages for dirty logging. 9976 * 9977 * All the sptes including the large sptes which point to this 9978 * slot are set to readonly. We can not create any new large 9979 * spte on this slot until the end of the logging. 9980 * 9981 * See the comments in fast_page_fault(). 9982 */ 9983 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 9984 if (kvm_x86_ops->slot_enable_log_dirty) 9985 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 9986 else 9987 kvm_mmu_slot_remove_write_access(kvm, new); 9988 } else { 9989 if (kvm_x86_ops->slot_disable_log_dirty) 9990 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 9991 } 9992 } 9993 9994 void kvm_arch_commit_memory_region(struct kvm *kvm, 9995 const struct kvm_userspace_memory_region *mem, 9996 const struct kvm_memory_slot *old, 9997 const struct kvm_memory_slot *new, 9998 enum kvm_mr_change change) 9999 { 10000 if (!kvm->arch.n_requested_mmu_pages) 10001 kvm_mmu_change_mmu_pages(kvm, 10002 kvm_mmu_calculate_default_mmu_pages(kvm)); 10003 10004 /* 10005 * Dirty logging tracks sptes in 4k granularity, meaning that large 10006 * sptes have to be split. If live migration is successful, the guest 10007 * in the source machine will be destroyed and large sptes will be 10008 * created in the destination. However, if the guest continues to run 10009 * in the source machine (for example if live migration fails), small 10010 * sptes will remain around and cause bad performance. 10011 * 10012 * Scan sptes if dirty logging has been stopped, dropping those 10013 * which can be collapsed into a single large-page spte. Later 10014 * page faults will create the large-page sptes. 10015 * 10016 * There is no need to do this in any of the following cases: 10017 * CREATE: No dirty mappings will already exist. 10018 * MOVE/DELETE: The old mappings will already have been cleaned up by 10019 * kvm_arch_flush_shadow_memslot() 10020 */ 10021 if (change == KVM_MR_FLAGS_ONLY && 10022 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 10023 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 10024 kvm_mmu_zap_collapsible_sptes(kvm, new); 10025 10026 /* 10027 * Set up write protection and/or dirty logging for the new slot. 10028 * 10029 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 10030 * been zapped so no dirty logging staff is needed for old slot. For 10031 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 10032 * new and it's also covered when dealing with the new slot. 10033 * 10034 * FIXME: const-ify all uses of struct kvm_memory_slot. 10035 */ 10036 if (change != KVM_MR_DELETE) 10037 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 10038 } 10039 10040 void kvm_arch_flush_shadow_all(struct kvm *kvm) 10041 { 10042 kvm_mmu_zap_all(kvm); 10043 } 10044 10045 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 10046 struct kvm_memory_slot *slot) 10047 { 10048 kvm_page_track_flush_slot(kvm, slot); 10049 } 10050 10051 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 10052 { 10053 return (is_guest_mode(vcpu) && 10054 kvm_x86_ops->guest_apic_has_interrupt && 10055 kvm_x86_ops->guest_apic_has_interrupt(vcpu)); 10056 } 10057 10058 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 10059 { 10060 if (!list_empty_careful(&vcpu->async_pf.done)) 10061 return true; 10062 10063 if (kvm_apic_has_events(vcpu)) 10064 return true; 10065 10066 if (vcpu->arch.pv.pv_unhalted) 10067 return true; 10068 10069 if (vcpu->arch.exception.pending) 10070 return true; 10071 10072 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10073 (vcpu->arch.nmi_pending && 10074 kvm_x86_ops->nmi_allowed(vcpu))) 10075 return true; 10076 10077 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 10078 (vcpu->arch.smi_pending && !is_smm(vcpu))) 10079 return true; 10080 10081 if (kvm_arch_interrupt_allowed(vcpu) && 10082 (kvm_cpu_has_interrupt(vcpu) || 10083 kvm_guest_apic_has_interrupt(vcpu))) 10084 return true; 10085 10086 if (kvm_hv_has_stimer_pending(vcpu)) 10087 return true; 10088 10089 return false; 10090 } 10091 10092 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 10093 { 10094 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 10095 } 10096 10097 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 10098 { 10099 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 10100 return true; 10101 10102 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10103 kvm_test_request(KVM_REQ_SMI, vcpu) || 10104 kvm_test_request(KVM_REQ_EVENT, vcpu)) 10105 return true; 10106 10107 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu)) 10108 return true; 10109 10110 return false; 10111 } 10112 10113 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 10114 { 10115 return vcpu->arch.preempted_in_kernel; 10116 } 10117 10118 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 10119 { 10120 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 10121 } 10122 10123 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 10124 { 10125 return kvm_x86_ops->interrupt_allowed(vcpu); 10126 } 10127 10128 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 10129 { 10130 if (is_64_bit_mode(vcpu)) 10131 return kvm_rip_read(vcpu); 10132 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 10133 kvm_rip_read(vcpu)); 10134 } 10135 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 10136 10137 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 10138 { 10139 return kvm_get_linear_rip(vcpu) == linear_rip; 10140 } 10141 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 10142 10143 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 10144 { 10145 unsigned long rflags; 10146 10147 rflags = kvm_x86_ops->get_rflags(vcpu); 10148 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10149 rflags &= ~X86_EFLAGS_TF; 10150 return rflags; 10151 } 10152 EXPORT_SYMBOL_GPL(kvm_get_rflags); 10153 10154 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 10155 { 10156 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 10157 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 10158 rflags |= X86_EFLAGS_TF; 10159 kvm_x86_ops->set_rflags(vcpu, rflags); 10160 } 10161 10162 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 10163 { 10164 __kvm_set_rflags(vcpu, rflags); 10165 kvm_make_request(KVM_REQ_EVENT, vcpu); 10166 } 10167 EXPORT_SYMBOL_GPL(kvm_set_rflags); 10168 10169 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 10170 { 10171 int r; 10172 10173 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 10174 work->wakeup_all) 10175 return; 10176 10177 r = kvm_mmu_reload(vcpu); 10178 if (unlikely(r)) 10179 return; 10180 10181 if (!vcpu->arch.mmu->direct_map && 10182 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu)) 10183 return; 10184 10185 vcpu->arch.mmu->page_fault(vcpu, work->cr2_or_gpa, 0, true); 10186 } 10187 10188 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 10189 { 10190 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 10191 } 10192 10193 static inline u32 kvm_async_pf_next_probe(u32 key) 10194 { 10195 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 10196 } 10197 10198 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10199 { 10200 u32 key = kvm_async_pf_hash_fn(gfn); 10201 10202 while (vcpu->arch.apf.gfns[key] != ~0) 10203 key = kvm_async_pf_next_probe(key); 10204 10205 vcpu->arch.apf.gfns[key] = gfn; 10206 } 10207 10208 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 10209 { 10210 int i; 10211 u32 key = kvm_async_pf_hash_fn(gfn); 10212 10213 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 10214 (vcpu->arch.apf.gfns[key] != gfn && 10215 vcpu->arch.apf.gfns[key] != ~0); i++) 10216 key = kvm_async_pf_next_probe(key); 10217 10218 return key; 10219 } 10220 10221 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10222 { 10223 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 10224 } 10225 10226 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10227 { 10228 u32 i, j, k; 10229 10230 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 10231 while (true) { 10232 vcpu->arch.apf.gfns[i] = ~0; 10233 do { 10234 j = kvm_async_pf_next_probe(j); 10235 if (vcpu->arch.apf.gfns[j] == ~0) 10236 return; 10237 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 10238 /* 10239 * k lies cyclically in ]i,j] 10240 * | i.k.j | 10241 * |....j i.k.| or |.k..j i...| 10242 */ 10243 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 10244 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 10245 i = j; 10246 } 10247 } 10248 10249 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 10250 { 10251 10252 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 10253 sizeof(val)); 10254 } 10255 10256 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 10257 { 10258 10259 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 10260 sizeof(u32)); 10261 } 10262 10263 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 10264 { 10265 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 10266 return false; 10267 10268 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 10269 (vcpu->arch.apf.send_user_only && 10270 kvm_x86_ops->get_cpl(vcpu) == 0)) 10271 return false; 10272 10273 return true; 10274 } 10275 10276 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 10277 { 10278 if (unlikely(!lapic_in_kernel(vcpu) || 10279 kvm_event_needs_reinjection(vcpu) || 10280 vcpu->arch.exception.pending)) 10281 return false; 10282 10283 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 10284 return false; 10285 10286 /* 10287 * If interrupts are off we cannot even use an artificial 10288 * halt state. 10289 */ 10290 return kvm_x86_ops->interrupt_allowed(vcpu); 10291 } 10292 10293 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 10294 struct kvm_async_pf *work) 10295 { 10296 struct x86_exception fault; 10297 10298 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 10299 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 10300 10301 if (kvm_can_deliver_async_pf(vcpu) && 10302 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 10303 fault.vector = PF_VECTOR; 10304 fault.error_code_valid = true; 10305 fault.error_code = 0; 10306 fault.nested_page_fault = false; 10307 fault.address = work->arch.token; 10308 fault.async_page_fault = true; 10309 kvm_inject_page_fault(vcpu, &fault); 10310 } else { 10311 /* 10312 * It is not possible to deliver a paravirtualized asynchronous 10313 * page fault, but putting the guest in an artificial halt state 10314 * can be beneficial nevertheless: if an interrupt arrives, we 10315 * can deliver it timely and perhaps the guest will schedule 10316 * another process. When the instruction that triggered a page 10317 * fault is retried, hopefully the page will be ready in the host. 10318 */ 10319 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 10320 } 10321 } 10322 10323 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 10324 struct kvm_async_pf *work) 10325 { 10326 struct x86_exception fault; 10327 u32 val; 10328 10329 if (work->wakeup_all) 10330 work->arch.token = ~0; /* broadcast wakeup */ 10331 else 10332 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 10333 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 10334 10335 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 10336 !apf_get_user(vcpu, &val)) { 10337 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 10338 vcpu->arch.exception.pending && 10339 vcpu->arch.exception.nr == PF_VECTOR && 10340 !apf_put_user(vcpu, 0)) { 10341 vcpu->arch.exception.injected = false; 10342 vcpu->arch.exception.pending = false; 10343 vcpu->arch.exception.nr = 0; 10344 vcpu->arch.exception.has_error_code = false; 10345 vcpu->arch.exception.error_code = 0; 10346 vcpu->arch.exception.has_payload = false; 10347 vcpu->arch.exception.payload = 0; 10348 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 10349 fault.vector = PF_VECTOR; 10350 fault.error_code_valid = true; 10351 fault.error_code = 0; 10352 fault.nested_page_fault = false; 10353 fault.address = work->arch.token; 10354 fault.async_page_fault = true; 10355 kvm_inject_page_fault(vcpu, &fault); 10356 } 10357 } 10358 vcpu->arch.apf.halted = false; 10359 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10360 } 10361 10362 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 10363 { 10364 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 10365 return true; 10366 else 10367 return kvm_can_do_async_pf(vcpu); 10368 } 10369 10370 void kvm_arch_start_assignment(struct kvm *kvm) 10371 { 10372 atomic_inc(&kvm->arch.assigned_device_count); 10373 } 10374 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 10375 10376 void kvm_arch_end_assignment(struct kvm *kvm) 10377 { 10378 atomic_dec(&kvm->arch.assigned_device_count); 10379 } 10380 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 10381 10382 bool kvm_arch_has_assigned_device(struct kvm *kvm) 10383 { 10384 return atomic_read(&kvm->arch.assigned_device_count); 10385 } 10386 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 10387 10388 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 10389 { 10390 atomic_inc(&kvm->arch.noncoherent_dma_count); 10391 } 10392 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 10393 10394 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 10395 { 10396 atomic_dec(&kvm->arch.noncoherent_dma_count); 10397 } 10398 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 10399 10400 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 10401 { 10402 return atomic_read(&kvm->arch.noncoherent_dma_count); 10403 } 10404 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 10405 10406 bool kvm_arch_has_irq_bypass(void) 10407 { 10408 return true; 10409 } 10410 10411 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 10412 struct irq_bypass_producer *prod) 10413 { 10414 struct kvm_kernel_irqfd *irqfd = 10415 container_of(cons, struct kvm_kernel_irqfd, consumer); 10416 10417 irqfd->producer = prod; 10418 10419 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 10420 prod->irq, irqfd->gsi, 1); 10421 } 10422 10423 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 10424 struct irq_bypass_producer *prod) 10425 { 10426 int ret; 10427 struct kvm_kernel_irqfd *irqfd = 10428 container_of(cons, struct kvm_kernel_irqfd, consumer); 10429 10430 WARN_ON(irqfd->producer != prod); 10431 irqfd->producer = NULL; 10432 10433 /* 10434 * When producer of consumer is unregistered, we change back to 10435 * remapped mode, so we can re-use the current implementation 10436 * when the irq is masked/disabled or the consumer side (KVM 10437 * int this case doesn't want to receive the interrupts. 10438 */ 10439 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 10440 if (ret) 10441 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 10442 " fails: %d\n", irqfd->consumer.token, ret); 10443 } 10444 10445 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 10446 uint32_t guest_irq, bool set) 10447 { 10448 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 10449 } 10450 10451 bool kvm_vector_hashing_enabled(void) 10452 { 10453 return vector_hashing; 10454 } 10455 10456 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 10457 { 10458 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 10459 } 10460 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 10461 10462 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu) 10463 { 10464 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD; 10465 10466 /* The STIBP bit doesn't fault even if it's not advertised */ 10467 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) && 10468 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS)) 10469 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP); 10470 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) && 10471 !boot_cpu_has(X86_FEATURE_AMD_IBRS)) 10472 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP); 10473 10474 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) && 10475 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) 10476 bits &= ~SPEC_CTRL_SSBD; 10477 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && 10478 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 10479 bits &= ~SPEC_CTRL_SSBD; 10480 10481 return bits; 10482 } 10483 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits); 10484 10485 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 10486 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 10487 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 10488 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 10489 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 10490 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 10491 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 10492 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 10493 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 10494 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 10495 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 10496 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 10497 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 10498 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 10499 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 10500 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 10501 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 10502 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 10503 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 10504 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 10505 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 10506