1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 10 #include "capabilities.h" 11 #include "ops.h" 12 #include "vmcs.h" 13 14 extern const u32 vmx_msr_index[]; 15 extern u64 host_efer; 16 17 #define MSR_TYPE_R 1 18 #define MSR_TYPE_W 2 19 #define MSR_TYPE_RW 3 20 21 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 22 23 #define NR_AUTOLOAD_MSRS 8 24 25 struct vmx_msrs { 26 unsigned int nr; 27 struct vmx_msr_entry val[NR_AUTOLOAD_MSRS]; 28 }; 29 30 struct shared_msr_entry { 31 unsigned index; 32 u64 data; 33 u64 mask; 34 }; 35 36 enum segment_cache_field { 37 SEG_FIELD_SEL = 0, 38 SEG_FIELD_BASE = 1, 39 SEG_FIELD_LIMIT = 2, 40 SEG_FIELD_AR = 3, 41 42 SEG_FIELD_NR = 4 43 }; 44 45 /* Posted-Interrupt Descriptor */ 46 struct pi_desc { 47 u32 pir[8]; /* Posted interrupt requested */ 48 union { 49 struct { 50 /* bit 256 - Outstanding Notification */ 51 u16 on : 1, 52 /* bit 257 - Suppress Notification */ 53 sn : 1, 54 /* bit 271:258 - Reserved */ 55 rsvd_1 : 14; 56 /* bit 279:272 - Notification Vector */ 57 u8 nv; 58 /* bit 287:280 - Reserved */ 59 u8 rsvd_2; 60 /* bit 319:288 - Notification Destination */ 61 u32 ndst; 62 }; 63 u64 control; 64 }; 65 u32 rsvd[6]; 66 } __aligned(64); 67 68 #define RTIT_ADDR_RANGE 4 69 70 struct pt_ctx { 71 u64 ctl; 72 u64 status; 73 u64 output_base; 74 u64 output_mask; 75 u64 cr3_match; 76 u64 addr_a[RTIT_ADDR_RANGE]; 77 u64 addr_b[RTIT_ADDR_RANGE]; 78 }; 79 80 struct pt_desc { 81 u64 ctl_bitmask; 82 u32 addr_range; 83 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 84 struct pt_ctx host; 85 struct pt_ctx guest; 86 }; 87 88 /* 89 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 90 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 91 */ 92 struct nested_vmx { 93 /* Has the level1 guest done vmxon? */ 94 bool vmxon; 95 gpa_t vmxon_ptr; 96 bool pml_full; 97 98 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 99 gpa_t current_vmptr; 100 /* 101 * Cache of the guest's VMCS, existing outside of guest memory. 102 * Loaded from guest memory during VMPTRLD. Flushed to guest 103 * memory during VMCLEAR and VMPTRLD. 104 */ 105 struct vmcs12 *cached_vmcs12; 106 /* 107 * Cache of the guest's shadow VMCS, existing outside of guest 108 * memory. Loaded from guest memory during VM entry. Flushed 109 * to guest memory during VM exit. 110 */ 111 struct vmcs12 *cached_shadow_vmcs12; 112 113 /* 114 * Indicates if the shadow vmcs or enlightened vmcs must be updated 115 * with the data held by struct vmcs12. 116 */ 117 bool need_vmcs12_to_shadow_sync; 118 bool dirty_vmcs12; 119 120 /* 121 * Indicates lazily loaded guest state has not yet been decached from 122 * vmcs02. 123 */ 124 bool need_sync_vmcs02_to_vmcs12_rare; 125 126 /* 127 * vmcs02 has been initialized, i.e. state that is constant for 128 * vmcs02 has been written to the backing VMCS. Initialization 129 * is delayed until L1 actually attempts to run a nested VM. 130 */ 131 bool vmcs02_initialized; 132 133 bool change_vmcs01_virtual_apic_mode; 134 135 /* 136 * Enlightened VMCS has been enabled. It does not mean that L1 has to 137 * use it. However, VMX features available to L1 will be limited based 138 * on what the enlightened VMCS supports. 139 */ 140 bool enlightened_vmcs_enabled; 141 142 /* L2 must run next, and mustn't decide to exit to L1. */ 143 bool nested_run_pending; 144 145 struct loaded_vmcs vmcs02; 146 147 /* 148 * Guest pages referred to in the vmcs02 with host-physical 149 * pointers, so we must keep them pinned while L2 runs. 150 */ 151 struct page *apic_access_page; 152 struct kvm_host_map virtual_apic_map; 153 struct kvm_host_map pi_desc_map; 154 155 struct kvm_host_map msr_bitmap_map; 156 157 struct pi_desc *pi_desc; 158 bool pi_pending; 159 u16 posted_intr_nv; 160 161 struct hrtimer preemption_timer; 162 bool preemption_timer_expired; 163 164 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ 165 u64 vmcs01_debugctl; 166 u64 vmcs01_guest_bndcfgs; 167 168 u16 vpid02; 169 u16 last_vpid; 170 171 struct nested_vmx_msrs msrs; 172 173 /* SMM related state */ 174 struct { 175 /* in VMX operation on SMM entry? */ 176 bool vmxon; 177 /* in guest mode on SMM entry? */ 178 bool guest_mode; 179 } smm; 180 181 gpa_t hv_evmcs_vmptr; 182 struct kvm_host_map hv_evmcs_map; 183 struct hv_enlightened_vmcs *hv_evmcs; 184 }; 185 186 struct vcpu_vmx { 187 struct kvm_vcpu vcpu; 188 u8 fail; 189 u8 msr_bitmap_mode; 190 191 /* 192 * If true, host state has been stored in vmx->loaded_vmcs for 193 * the CPU registers that only need to be switched when transitioning 194 * to/from the kernel, and the registers have been loaded with guest 195 * values. If false, host state is loaded in the CPU registers 196 * and vmx->loaded_vmcs->host_state is invalid. 197 */ 198 bool guest_state_loaded; 199 200 u32 exit_intr_info; 201 u32 idt_vectoring_info; 202 ulong rflags; 203 204 struct shared_msr_entry *guest_msrs; 205 int nmsrs; 206 int save_nmsrs; 207 bool guest_msrs_ready; 208 #ifdef CONFIG_X86_64 209 u64 msr_host_kernel_gs_base; 210 u64 msr_guest_kernel_gs_base; 211 #endif 212 213 u64 spec_ctrl; 214 215 u32 secondary_exec_control; 216 217 /* 218 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 219 * non-nested (L1) guest, it always points to vmcs01. For a nested 220 * guest (L2), it points to a different VMCS. 221 */ 222 struct loaded_vmcs vmcs01; 223 struct loaded_vmcs *loaded_vmcs; 224 225 struct msr_autoload { 226 struct vmx_msrs guest; 227 struct vmx_msrs host; 228 } msr_autoload; 229 230 struct { 231 int vm86_active; 232 ulong save_rflags; 233 struct kvm_segment segs[8]; 234 } rmode; 235 struct { 236 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 237 struct kvm_save_segment { 238 u16 selector; 239 unsigned long base; 240 u32 limit; 241 u32 ar; 242 } seg[8]; 243 } segment_cache; 244 int vpid; 245 bool emulation_required; 246 247 u32 exit_reason; 248 249 /* Posted interrupt descriptor */ 250 struct pi_desc pi_desc; 251 252 /* Support for a guest hypervisor (nested VMX) */ 253 struct nested_vmx nested; 254 255 /* Dynamic PLE window. */ 256 int ple_window; 257 bool ple_window_dirty; 258 259 bool req_immediate_exit; 260 261 /* Support for PML */ 262 #define PML_ENTITY_NUM 512 263 struct page *pml_pg; 264 265 /* apic deadline value in host tsc */ 266 u64 hv_deadline_tsc; 267 268 u64 current_tsc_ratio; 269 270 u32 host_pkru; 271 272 unsigned long host_debugctlmsr; 273 274 /* 275 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 276 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included 277 * in msr_ia32_feature_control_valid_bits. 278 */ 279 u64 msr_ia32_feature_control; 280 u64 msr_ia32_feature_control_valid_bits; 281 u64 ept_pointer; 282 283 struct pt_desc pt_desc; 284 }; 285 286 enum ept_pointers_status { 287 EPT_POINTERS_CHECK = 0, 288 EPT_POINTERS_MATCH = 1, 289 EPT_POINTERS_MISMATCH = 2 290 }; 291 292 struct kvm_vmx { 293 struct kvm kvm; 294 295 unsigned int tss_addr; 296 bool ept_identity_pagetable_done; 297 gpa_t ept_identity_map_addr; 298 299 enum ept_pointers_status ept_pointers_match; 300 spinlock_t ept_pointer_lock; 301 }; 302 303 bool nested_vmx_allowed(struct kvm_vcpu *vcpu); 304 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu); 305 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 306 int allocate_vpid(void); 307 void free_vpid(int vpid); 308 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 309 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 310 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 311 unsigned long fs_base, unsigned long gs_base); 312 int vmx_get_cpl(struct kvm_vcpu *vcpu); 313 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 314 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 315 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 316 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 317 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 318 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 319 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); 320 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 321 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 322 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 323 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 324 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 325 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); 326 void update_exception_bitmap(struct kvm_vcpu *vcpu); 327 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); 328 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 329 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 330 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 331 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr); 332 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx); 333 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 334 335 #define POSTED_INTR_ON 0 336 #define POSTED_INTR_SN 1 337 338 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc) 339 { 340 return test_and_set_bit(POSTED_INTR_ON, 341 (unsigned long *)&pi_desc->control); 342 } 343 344 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc) 345 { 346 return test_and_clear_bit(POSTED_INTR_ON, 347 (unsigned long *)&pi_desc->control); 348 } 349 350 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) 351 { 352 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); 353 } 354 355 static inline void pi_set_sn(struct pi_desc *pi_desc) 356 { 357 set_bit(POSTED_INTR_SN, 358 (unsigned long *)&pi_desc->control); 359 } 360 361 static inline void pi_set_on(struct pi_desc *pi_desc) 362 { 363 set_bit(POSTED_INTR_ON, 364 (unsigned long *)&pi_desc->control); 365 } 366 367 static inline void pi_clear_on(struct pi_desc *pi_desc) 368 { 369 clear_bit(POSTED_INTR_ON, 370 (unsigned long *)&pi_desc->control); 371 } 372 373 static inline int pi_test_on(struct pi_desc *pi_desc) 374 { 375 return test_bit(POSTED_INTR_ON, 376 (unsigned long *)&pi_desc->control); 377 } 378 379 static inline int pi_test_sn(struct pi_desc *pi_desc) 380 { 381 return test_bit(POSTED_INTR_SN, 382 (unsigned long *)&pi_desc->control); 383 } 384 385 static inline u8 vmx_get_rvi(void) 386 { 387 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 388 } 389 390 #define BUILD_CONTROLS_SHADOW(lname, uname) \ 391 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \ 392 { \ 393 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 394 vmcs_write32(uname, val); \ 395 vmx->loaded_vmcs->controls_shadow.lname = val; \ 396 } \ 397 } \ 398 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \ 399 { \ 400 return vmx->loaded_vmcs->controls_shadow.lname; \ 401 } \ 402 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \ 403 { \ 404 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 405 } \ 406 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \ 407 { \ 408 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 409 } 410 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS) 411 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS) 412 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL) 413 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL) 414 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL) 415 416 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 417 { 418 vmx->segment_cache.bitmask = 0; 419 } 420 421 static inline u32 vmx_vmentry_ctrl(void) 422 { 423 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl; 424 if (pt_mode == PT_MODE_SYSTEM) 425 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP | 426 VM_ENTRY_LOAD_IA32_RTIT_CTL); 427 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 428 return vmentry_ctrl & 429 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER); 430 } 431 432 static inline u32 vmx_vmexit_ctrl(void) 433 { 434 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl; 435 if (pt_mode == PT_MODE_SYSTEM) 436 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP | 437 VM_EXIT_CLEAR_IA32_RTIT_CTL); 438 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 439 return vmexit_ctrl & 440 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER); 441 } 442 443 u32 vmx_exec_control(struct vcpu_vmx *vmx); 444 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx); 445 446 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 447 { 448 return container_of(kvm, struct kvm_vmx, kvm); 449 } 450 451 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 452 { 453 return container_of(vcpu, struct vcpu_vmx, vcpu); 454 } 455 456 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) 457 { 458 return &(to_vmx(vcpu)->pi_desc); 459 } 460 461 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 462 void free_vmcs(struct vmcs *vmcs); 463 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 464 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 465 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs); 466 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs); 467 468 static inline struct vmcs *alloc_vmcs(bool shadow) 469 { 470 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 471 GFP_KERNEL_ACCOUNT); 472 } 473 474 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); 475 476 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid, 477 bool invalidate_gpa) 478 { 479 if (enable_ept && (invalidate_gpa || !enable_vpid)) { 480 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) 481 return; 482 ept_sync_context(construct_eptp(vcpu, 483 vcpu->arch.mmu->root_hpa)); 484 } else { 485 vpid_sync_context(vpid); 486 } 487 } 488 489 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 490 { 491 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa); 492 } 493 494 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx) 495 { 496 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; 497 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); 498 } 499 500 void dump_vmcs(void); 501 502 #endif /* __KVM_X86_VMX_H */ 503