1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 10 #include "capabilities.h" 11 #include "kvm_cache_regs.h" 12 #include "posted_intr.h" 13 #include "vmcs.h" 14 #include "vmx_ops.h" 15 #include "cpuid.h" 16 17 extern const u32 vmx_msr_index[]; 18 19 #define MSR_TYPE_R 1 20 #define MSR_TYPE_W 2 21 #define MSR_TYPE_RW 3 22 23 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 24 25 #ifdef CONFIG_X86_64 26 #define MAX_NR_USER_RETURN_MSRS 7 27 #else 28 #define MAX_NR_USER_RETURN_MSRS 4 29 #endif 30 31 #define MAX_NR_LOADSTORE_MSRS 8 32 33 struct vmx_msrs { 34 unsigned int nr; 35 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS]; 36 }; 37 38 struct vmx_uret_msr { 39 bool load_into_hardware; 40 u64 data; 41 u64 mask; 42 }; 43 44 enum segment_cache_field { 45 SEG_FIELD_SEL = 0, 46 SEG_FIELD_BASE = 1, 47 SEG_FIELD_LIMIT = 2, 48 SEG_FIELD_AR = 3, 49 50 SEG_FIELD_NR = 4 51 }; 52 53 #define RTIT_ADDR_RANGE 4 54 55 struct pt_ctx { 56 u64 ctl; 57 u64 status; 58 u64 output_base; 59 u64 output_mask; 60 u64 cr3_match; 61 u64 addr_a[RTIT_ADDR_RANGE]; 62 u64 addr_b[RTIT_ADDR_RANGE]; 63 }; 64 65 struct pt_desc { 66 u64 ctl_bitmask; 67 u32 addr_range; 68 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 69 struct pt_ctx host; 70 struct pt_ctx guest; 71 }; 72 73 union vmx_exit_reason { 74 struct { 75 u32 basic : 16; 76 u32 reserved16 : 1; 77 u32 reserved17 : 1; 78 u32 reserved18 : 1; 79 u32 reserved19 : 1; 80 u32 reserved20 : 1; 81 u32 reserved21 : 1; 82 u32 reserved22 : 1; 83 u32 reserved23 : 1; 84 u32 reserved24 : 1; 85 u32 reserved25 : 1; 86 u32 bus_lock_detected : 1; 87 u32 enclave_mode : 1; 88 u32 smi_pending_mtf : 1; 89 u32 smi_from_vmx_root : 1; 90 u32 reserved30 : 1; 91 u32 failed_vmentry : 1; 92 }; 93 u32 full; 94 }; 95 96 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc) 97 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records) 98 99 bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu); 100 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu); 101 102 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 103 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu); 104 105 struct lbr_desc { 106 /* Basic info about guest LBR records. */ 107 struct x86_pmu_lbr records; 108 109 /* 110 * Emulate LBR feature via passthrough LBR registers when the 111 * per-vcpu guest LBR event is scheduled on the current pcpu. 112 * 113 * The records may be inaccurate if the host reclaims the LBR. 114 */ 115 struct perf_event *event; 116 117 /* True if LBRs are marked as not intercepted in the MSR bitmap */ 118 bool msr_passthrough; 119 }; 120 121 /* 122 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 123 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 124 */ 125 struct nested_vmx { 126 /* Has the level1 guest done vmxon? */ 127 bool vmxon; 128 gpa_t vmxon_ptr; 129 bool pml_full; 130 131 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 132 gpa_t current_vmptr; 133 /* 134 * Cache of the guest's VMCS, existing outside of guest memory. 135 * Loaded from guest memory during VMPTRLD. Flushed to guest 136 * memory during VMCLEAR and VMPTRLD. 137 */ 138 struct vmcs12 *cached_vmcs12; 139 /* 140 * Cache of the guest's shadow VMCS, existing outside of guest 141 * memory. Loaded from guest memory during VM entry. Flushed 142 * to guest memory during VM exit. 143 */ 144 struct vmcs12 *cached_shadow_vmcs12; 145 146 /* 147 * Indicates if the shadow vmcs or enlightened vmcs must be updated 148 * with the data held by struct vmcs12. 149 */ 150 bool need_vmcs12_to_shadow_sync; 151 bool dirty_vmcs12; 152 153 /* 154 * Indicates lazily loaded guest state has not yet been decached from 155 * vmcs02. 156 */ 157 bool need_sync_vmcs02_to_vmcs12_rare; 158 159 /* 160 * vmcs02 has been initialized, i.e. state that is constant for 161 * vmcs02 has been written to the backing VMCS. Initialization 162 * is delayed until L1 actually attempts to run a nested VM. 163 */ 164 bool vmcs02_initialized; 165 166 bool change_vmcs01_virtual_apic_mode; 167 bool reload_vmcs01_apic_access_page; 168 bool update_vmcs01_cpu_dirty_logging; 169 170 /* 171 * Enlightened VMCS has been enabled. It does not mean that L1 has to 172 * use it. However, VMX features available to L1 will be limited based 173 * on what the enlightened VMCS supports. 174 */ 175 bool enlightened_vmcs_enabled; 176 177 /* L2 must run next, and mustn't decide to exit to L1. */ 178 bool nested_run_pending; 179 180 /* Pending MTF VM-exit into L1. */ 181 bool mtf_pending; 182 183 struct loaded_vmcs vmcs02; 184 185 /* 186 * Guest pages referred to in the vmcs02 with host-physical 187 * pointers, so we must keep them pinned while L2 runs. 188 */ 189 struct page *apic_access_page; 190 struct kvm_host_map virtual_apic_map; 191 struct kvm_host_map pi_desc_map; 192 193 struct kvm_host_map msr_bitmap_map; 194 195 struct pi_desc *pi_desc; 196 bool pi_pending; 197 u16 posted_intr_nv; 198 199 struct hrtimer preemption_timer; 200 u64 preemption_timer_deadline; 201 bool has_preemption_timer_deadline; 202 bool preemption_timer_expired; 203 204 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ 205 u64 vmcs01_debugctl; 206 u64 vmcs01_guest_bndcfgs; 207 208 /* to migrate it to L1 if L2 writes to L1's CR8 directly */ 209 int l1_tpr_threshold; 210 211 u16 vpid02; 212 u16 last_vpid; 213 214 struct nested_vmx_msrs msrs; 215 216 /* SMM related state */ 217 struct { 218 /* in VMX operation on SMM entry? */ 219 bool vmxon; 220 /* in guest mode on SMM entry? */ 221 bool guest_mode; 222 } smm; 223 224 gpa_t hv_evmcs_vmptr; 225 struct kvm_host_map hv_evmcs_map; 226 struct hv_enlightened_vmcs *hv_evmcs; 227 }; 228 229 struct vcpu_vmx { 230 struct kvm_vcpu vcpu; 231 u8 fail; 232 u8 msr_bitmap_mode; 233 234 /* 235 * If true, host state has been stored in vmx->loaded_vmcs for 236 * the CPU registers that only need to be switched when transitioning 237 * to/from the kernel, and the registers have been loaded with guest 238 * values. If false, host state is loaded in the CPU registers 239 * and vmx->loaded_vmcs->host_state is invalid. 240 */ 241 bool guest_state_loaded; 242 243 unsigned long exit_qualification; 244 u32 exit_intr_info; 245 u32 idt_vectoring_info; 246 ulong rflags; 247 248 /* 249 * User return MSRs are always emulated when enabled in the guest, but 250 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside 251 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to 252 * be loaded into hardware if those conditions aren't met. 253 * nr_active_uret_msrs tracks the number of MSRs that need to be loaded 254 * into hardware when running the guest. guest_uret_msrs[] is resorted 255 * whenever the number of "active" uret MSRs is modified. 256 */ 257 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS]; 258 int nr_active_uret_msrs; 259 bool guest_uret_msrs_loaded; 260 #ifdef CONFIG_X86_64 261 u64 msr_host_kernel_gs_base; 262 u64 msr_guest_kernel_gs_base; 263 #endif 264 265 u64 spec_ctrl; 266 u32 msr_ia32_umwait_control; 267 268 u32 secondary_exec_control; 269 270 /* 271 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 272 * non-nested (L1) guest, it always points to vmcs01. For a nested 273 * guest (L2), it points to a different VMCS. 274 */ 275 struct loaded_vmcs vmcs01; 276 struct loaded_vmcs *loaded_vmcs; 277 278 struct msr_autoload { 279 struct vmx_msrs guest; 280 struct vmx_msrs host; 281 } msr_autoload; 282 283 struct msr_autostore { 284 struct vmx_msrs guest; 285 } msr_autostore; 286 287 struct { 288 int vm86_active; 289 ulong save_rflags; 290 struct kvm_segment segs[8]; 291 } rmode; 292 struct { 293 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 294 struct kvm_save_segment { 295 u16 selector; 296 unsigned long base; 297 u32 limit; 298 u32 ar; 299 } seg[8]; 300 } segment_cache; 301 int vpid; 302 bool emulation_required; 303 304 union vmx_exit_reason exit_reason; 305 306 /* Posted interrupt descriptor */ 307 struct pi_desc pi_desc; 308 309 /* Support for a guest hypervisor (nested VMX) */ 310 struct nested_vmx nested; 311 312 /* Dynamic PLE window. */ 313 unsigned int ple_window; 314 bool ple_window_dirty; 315 316 bool req_immediate_exit; 317 318 /* Support for PML */ 319 #define PML_ENTITY_NUM 512 320 struct page *pml_pg; 321 322 /* apic deadline value in host tsc */ 323 u64 hv_deadline_tsc; 324 325 u64 current_tsc_ratio; 326 327 unsigned long host_debugctlmsr; 328 329 /* 330 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 331 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 332 * in msr_ia32_feature_control_valid_bits. 333 */ 334 u64 msr_ia32_feature_control; 335 u64 msr_ia32_feature_control_valid_bits; 336 /* SGX Launch Control public key hash */ 337 u64 msr_ia32_sgxlepubkeyhash[4]; 338 339 #if IS_ENABLED(CONFIG_HYPERV) 340 u64 hv_root_ept; 341 #endif 342 343 struct pt_desc pt_desc; 344 struct lbr_desc lbr_desc; 345 346 /* Save desired MSR intercept (read: pass-through) state */ 347 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 13 348 struct { 349 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS); 350 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS); 351 } shadow_msr_intercept; 352 }; 353 354 struct kvm_vmx { 355 struct kvm kvm; 356 357 unsigned int tss_addr; 358 bool ept_identity_pagetable_done; 359 gpa_t ept_identity_map_addr; 360 361 #if IS_ENABLED(CONFIG_HYPERV) 362 hpa_t hv_root_ept; 363 spinlock_t hv_root_ept_lock; 364 #endif 365 }; 366 367 bool nested_vmx_allowed(struct kvm_vcpu *vcpu); 368 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, 369 struct loaded_vmcs *buddy); 370 int allocate_vpid(void); 371 void free_vpid(int vpid); 372 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 373 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 374 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 375 unsigned long fs_base, unsigned long gs_base); 376 int vmx_get_cpl(struct kvm_vcpu *vcpu); 377 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 378 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 379 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 380 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 381 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 382 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 383 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 384 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 385 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 386 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 387 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 388 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level); 389 390 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); 391 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); 392 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu); 393 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 394 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 395 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 396 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 397 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr); 398 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu); 399 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 400 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 401 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr); 402 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu); 403 404 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type); 405 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type); 406 407 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, 408 int type, bool value) 409 { 410 if (value) 411 vmx_enable_intercept_for_msr(vcpu, msr, type); 412 else 413 vmx_disable_intercept_for_msr(vcpu, msr, type); 414 } 415 416 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu); 417 418 static inline u8 vmx_get_rvi(void) 419 { 420 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 421 } 422 423 #define BUILD_CONTROLS_SHADOW(lname, uname) \ 424 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \ 425 { \ 426 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 427 vmcs_write32(uname, val); \ 428 vmx->loaded_vmcs->controls_shadow.lname = val; \ 429 } \ 430 } \ 431 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \ 432 { \ 433 return vmx->loaded_vmcs->controls_shadow.lname; \ 434 } \ 435 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \ 436 { \ 437 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 438 } \ 439 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \ 440 { \ 441 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 442 } 443 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS) 444 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS) 445 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL) 446 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL) 447 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL) 448 449 static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu) 450 { 451 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 452 | (1 << VCPU_EXREG_RFLAGS) 453 | (1 << VCPU_EXREG_PDPTR) 454 | (1 << VCPU_EXREG_SEGMENTS) 455 | (1 << VCPU_EXREG_CR0) 456 | (1 << VCPU_EXREG_CR3) 457 | (1 << VCPU_EXREG_CR4) 458 | (1 << VCPU_EXREG_EXIT_INFO_1) 459 | (1 << VCPU_EXREG_EXIT_INFO_2)); 460 vcpu->arch.regs_dirty = 0; 461 } 462 463 static inline u32 vmx_vmentry_ctrl(void) 464 { 465 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl; 466 if (vmx_pt_mode_is_system()) 467 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP | 468 VM_ENTRY_LOAD_IA32_RTIT_CTL); 469 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 470 return vmentry_ctrl & 471 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER); 472 } 473 474 static inline u32 vmx_vmexit_ctrl(void) 475 { 476 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl; 477 if (vmx_pt_mode_is_system()) 478 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP | 479 VM_EXIT_CLEAR_IA32_RTIT_CTL); 480 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */ 481 return vmexit_ctrl & 482 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER); 483 } 484 485 u32 vmx_exec_control(struct vcpu_vmx *vmx); 486 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx); 487 488 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 489 { 490 return container_of(kvm, struct kvm_vmx, kvm); 491 } 492 493 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 494 { 495 return container_of(vcpu, struct vcpu_vmx, vcpu); 496 } 497 498 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu) 499 { 500 struct vcpu_vmx *vmx = to_vmx(vcpu); 501 502 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) { 503 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1); 504 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 505 } 506 return vmx->exit_qualification; 507 } 508 509 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) 510 { 511 struct vcpu_vmx *vmx = to_vmx(vcpu); 512 513 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) { 514 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2); 515 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 516 } 517 return vmx->exit_intr_info; 518 } 519 520 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 521 void free_vmcs(struct vmcs *vmcs); 522 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 523 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 524 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs); 525 526 static inline struct vmcs *alloc_vmcs(bool shadow) 527 { 528 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 529 GFP_KERNEL_ACCOUNT); 530 } 531 532 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx) 533 { 534 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; 535 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); 536 } 537 538 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 539 { 540 return vmx->secondary_exec_control & 541 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 542 } 543 544 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu) 545 { 546 if (!enable_ept) 547 return true; 548 549 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits; 550 } 551 552 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) 553 { 554 return enable_unrestricted_guest && (!is_guest_mode(vcpu) || 555 (secondary_exec_controls_get(to_vmx(vcpu)) & 556 SECONDARY_EXEC_UNRESTRICTED_GUEST)); 557 } 558 559 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu); 560 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu) 561 { 562 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu); 563 } 564 565 void dump_vmcs(struct kvm_vcpu *vcpu); 566 567 #endif /* __KVM_X86_VMX_H */ 568