1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/debugreg.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/io.h> 38 #include <asm/irq_remapping.h> 39 #include <asm/kexec.h> 40 #include <asm/perf_event.h> 41 #include <asm/mce.h> 42 #include <asm/mmu_context.h> 43 #include <asm/mshyperv.h> 44 #include <asm/spec-ctrl.h> 45 #include <asm/virtext.h> 46 #include <asm/vmx.h> 47 48 #include "capabilities.h" 49 #include "cpuid.h" 50 #include "evmcs.h" 51 #include "irq.h" 52 #include "kvm_cache_regs.h" 53 #include "lapic.h" 54 #include "mmu.h" 55 #include "nested.h" 56 #include "ops.h" 57 #include "pmu.h" 58 #include "trace.h" 59 #include "vmcs.h" 60 #include "vmcs12.h" 61 #include "vmx.h" 62 #include "x86.h" 63 64 MODULE_AUTHOR("Qumranet"); 65 MODULE_LICENSE("GPL"); 66 67 static const struct x86_cpu_id vmx_cpu_id[] = { 68 X86_FEATURE_MATCH(X86_FEATURE_VMX), 69 {} 70 }; 71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 72 73 bool __read_mostly enable_vpid = 1; 74 module_param_named(vpid, enable_vpid, bool, 0444); 75 76 static bool __read_mostly enable_vnmi = 1; 77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 78 79 bool __read_mostly flexpriority_enabled = 1; 80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 81 82 bool __read_mostly enable_ept = 1; 83 module_param_named(ept, enable_ept, bool, S_IRUGO); 84 85 bool __read_mostly enable_unrestricted_guest = 1; 86 module_param_named(unrestricted_guest, 87 enable_unrestricted_guest, bool, S_IRUGO); 88 89 bool __read_mostly enable_ept_ad_bits = 1; 90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 91 92 static bool __read_mostly emulate_invalid_guest_state = true; 93 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 94 95 static bool __read_mostly fasteoi = 1; 96 module_param(fasteoi, bool, S_IRUGO); 97 98 static bool __read_mostly enable_apicv = 1; 99 module_param(enable_apicv, bool, S_IRUGO); 100 101 /* 102 * If nested=1, nested virtualization is supported, i.e., guests may use 103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 104 * use VMX instructions. 105 */ 106 static bool __read_mostly nested = 1; 107 module_param(nested, bool, S_IRUGO); 108 109 static u64 __read_mostly host_xss; 110 111 bool __read_mostly enable_pml = 1; 112 module_param_named(pml, enable_pml, bool, S_IRUGO); 113 114 static bool __read_mostly dump_invalid_vmcs = 0; 115 module_param(dump_invalid_vmcs, bool, 0644); 116 117 #define MSR_BITMAP_MODE_X2APIC 1 118 #define MSR_BITMAP_MODE_X2APIC_APICV 2 119 120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 121 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 123 static int __read_mostly cpu_preemption_timer_multi; 124 static bool __read_mostly enable_preemption_timer = 1; 125 #ifdef CONFIG_X86_64 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 127 #endif 128 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 131 #define KVM_VM_CR0_ALWAYS_ON \ 132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 134 #define KVM_CR4_GUEST_OWNED_BITS \ 135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 137 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 141 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 143 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 147 RTIT_STATUS_BYTECNT)) 148 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 151 152 /* 153 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 154 * ple_gap: upper bound on the amount of time between two successive 155 * executions of PAUSE in a loop. Also indicate if ple enabled. 156 * According to test, this time is usually smaller than 128 cycles. 157 * ple_window: upper bound on the amount of time a guest is allowed to execute 158 * in a PAUSE loop. Tests indicate that most spinlocks are held for 159 * less than 2^12 cycles 160 * Time is measured based on a counter that runs at the same rate as the TSC, 161 * refer SDM volume 3b section 21.6.13 & 22.1.3. 162 */ 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 164 module_param(ple_gap, uint, 0444); 165 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 167 module_param(ple_window, uint, 0444); 168 169 /* Default doubles per-vcpu window every exit. */ 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 171 module_param(ple_window_grow, uint, 0444); 172 173 /* Default resets per-vcpu window every exit to ple_window. */ 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 175 module_param(ple_window_shrink, uint, 0444); 176 177 /* Default is to compute the maximum so we can never overflow. */ 178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 179 module_param(ple_window_max, uint, 0444); 180 181 /* Default is SYSTEM mode, 1 for host-guest mode */ 182 int __read_mostly pt_mode = PT_MODE_SYSTEM; 183 module_param(pt_mode, int, S_IRUGO); 184 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 188 189 /* Storage for pre module init parameter parsing */ 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 191 192 static const struct { 193 const char *option; 194 bool for_parse; 195 } vmentry_l1d_param[] = { 196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 198 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 202 }; 203 204 #define L1D_CACHE_ORDER 4 205 static void *vmx_l1d_flush_pages; 206 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 208 { 209 struct page *page; 210 unsigned int i; 211 212 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 214 return 0; 215 } 216 217 if (!enable_ept) { 218 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 219 return 0; 220 } 221 222 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 223 u64 msr; 224 225 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 226 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 228 return 0; 229 } 230 } 231 232 /* If set to auto use the default l1tf mitigation method */ 233 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 234 switch (l1tf_mitigation) { 235 case L1TF_MITIGATION_OFF: 236 l1tf = VMENTER_L1D_FLUSH_NEVER; 237 break; 238 case L1TF_MITIGATION_FLUSH_NOWARN: 239 case L1TF_MITIGATION_FLUSH: 240 case L1TF_MITIGATION_FLUSH_NOSMT: 241 l1tf = VMENTER_L1D_FLUSH_COND; 242 break; 243 case L1TF_MITIGATION_FULL: 244 case L1TF_MITIGATION_FULL_FORCE: 245 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 246 break; 247 } 248 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 249 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 250 } 251 252 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 253 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 254 /* 255 * This allocation for vmx_l1d_flush_pages is not tied to a VM 256 * lifetime and so should not be charged to a memcg. 257 */ 258 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 259 if (!page) 260 return -ENOMEM; 261 vmx_l1d_flush_pages = page_address(page); 262 263 /* 264 * Initialize each page with a different pattern in 265 * order to protect against KSM in the nested 266 * virtualization case. 267 */ 268 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 269 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 270 PAGE_SIZE); 271 } 272 } 273 274 l1tf_vmx_mitigation = l1tf; 275 276 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 277 static_branch_enable(&vmx_l1d_should_flush); 278 else 279 static_branch_disable(&vmx_l1d_should_flush); 280 281 if (l1tf == VMENTER_L1D_FLUSH_COND) 282 static_branch_enable(&vmx_l1d_flush_cond); 283 else 284 static_branch_disable(&vmx_l1d_flush_cond); 285 return 0; 286 } 287 288 static int vmentry_l1d_flush_parse(const char *s) 289 { 290 unsigned int i; 291 292 if (s) { 293 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 294 if (vmentry_l1d_param[i].for_parse && 295 sysfs_streq(s, vmentry_l1d_param[i].option)) 296 return i; 297 } 298 } 299 return -EINVAL; 300 } 301 302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 303 { 304 int l1tf, ret; 305 306 l1tf = vmentry_l1d_flush_parse(s); 307 if (l1tf < 0) 308 return l1tf; 309 310 if (!boot_cpu_has(X86_BUG_L1TF)) 311 return 0; 312 313 /* 314 * Has vmx_init() run already? If not then this is the pre init 315 * parameter parsing. In that case just store the value and let 316 * vmx_init() do the proper setup after enable_ept has been 317 * established. 318 */ 319 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 320 vmentry_l1d_flush_param = l1tf; 321 return 0; 322 } 323 324 mutex_lock(&vmx_l1d_flush_mutex); 325 ret = vmx_setup_l1d_flush(l1tf); 326 mutex_unlock(&vmx_l1d_flush_mutex); 327 return ret; 328 } 329 330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 331 { 332 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 333 return sprintf(s, "???\n"); 334 335 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 336 } 337 338 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 339 .set = vmentry_l1d_flush_set, 340 .get = vmentry_l1d_flush_get, 341 }; 342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 343 344 static bool guest_state_valid(struct kvm_vcpu *vcpu); 345 static u32 vmx_segment_access_rights(struct kvm_segment *var); 346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 347 u32 msr, int type); 348 349 void vmx_vmexit(void); 350 351 #define vmx_insn_failed(fmt...) \ 352 do { \ 353 WARN_ONCE(1, fmt); \ 354 pr_warn_ratelimited(fmt); \ 355 } while (0) 356 357 asmlinkage void vmread_error(unsigned long field, bool fault) 358 { 359 if (fault) 360 kvm_spurious_fault(); 361 else 362 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 363 } 364 365 noinline void vmwrite_error(unsigned long field, unsigned long value) 366 { 367 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 368 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 369 } 370 371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 372 { 373 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 374 } 375 376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 377 { 378 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 379 } 380 381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 382 { 383 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 384 ext, vpid, gva); 385 } 386 387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 388 { 389 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 390 ext, eptp, gpa); 391 } 392 393 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 394 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 395 /* 396 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 397 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 398 */ 399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 400 401 /* 402 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 403 * can find which vCPU should be waken up. 404 */ 405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 407 408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 409 static DEFINE_SPINLOCK(vmx_vpid_lock); 410 411 struct vmcs_config vmcs_config; 412 struct vmx_capability vmx_capability; 413 414 #define VMX_SEGMENT_FIELD(seg) \ 415 [VCPU_SREG_##seg] = { \ 416 .selector = GUEST_##seg##_SELECTOR, \ 417 .base = GUEST_##seg##_BASE, \ 418 .limit = GUEST_##seg##_LIMIT, \ 419 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 420 } 421 422 static const struct kvm_vmx_segment_field { 423 unsigned selector; 424 unsigned base; 425 unsigned limit; 426 unsigned ar_bytes; 427 } kvm_vmx_segment_fields[] = { 428 VMX_SEGMENT_FIELD(CS), 429 VMX_SEGMENT_FIELD(DS), 430 VMX_SEGMENT_FIELD(ES), 431 VMX_SEGMENT_FIELD(FS), 432 VMX_SEGMENT_FIELD(GS), 433 VMX_SEGMENT_FIELD(SS), 434 VMX_SEGMENT_FIELD(TR), 435 VMX_SEGMENT_FIELD(LDTR), 436 }; 437 438 u64 host_efer; 439 static unsigned long host_idt_base; 440 441 /* 442 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 443 * will emulate SYSCALL in legacy mode if the vendor string in guest 444 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 445 * support this emulation, IA32_STAR must always be included in 446 * vmx_msr_index[], even in i386 builds. 447 */ 448 const u32 vmx_msr_index[] = { 449 #ifdef CONFIG_X86_64 450 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 451 #endif 452 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 453 }; 454 455 #if IS_ENABLED(CONFIG_HYPERV) 456 static bool __read_mostly enlightened_vmcs = true; 457 module_param(enlightened_vmcs, bool, 0444); 458 459 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 460 static void check_ept_pointer_match(struct kvm *kvm) 461 { 462 struct kvm_vcpu *vcpu; 463 u64 tmp_eptp = INVALID_PAGE; 464 int i; 465 466 kvm_for_each_vcpu(i, vcpu, kvm) { 467 if (!VALID_PAGE(tmp_eptp)) { 468 tmp_eptp = to_vmx(vcpu)->ept_pointer; 469 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 470 to_kvm_vmx(kvm)->ept_pointers_match 471 = EPT_POINTERS_MISMATCH; 472 return; 473 } 474 } 475 476 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 477 } 478 479 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 480 void *data) 481 { 482 struct kvm_tlb_range *range = data; 483 484 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 485 range->pages); 486 } 487 488 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 489 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 490 { 491 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 492 493 /* 494 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 495 * of the base of EPT PML4 table, strip off EPT configuration 496 * information. 497 */ 498 if (range) 499 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 500 kvm_fill_hv_flush_list_func, (void *)range); 501 else 502 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 503 } 504 505 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 506 struct kvm_tlb_range *range) 507 { 508 struct kvm_vcpu *vcpu; 509 int ret = 0, i; 510 511 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 512 513 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 514 check_ept_pointer_match(kvm); 515 516 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 517 kvm_for_each_vcpu(i, vcpu, kvm) { 518 /* If ept_pointer is invalid pointer, bypass flush request. */ 519 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 520 ret |= __hv_remote_flush_tlb_with_range( 521 kvm, vcpu, range); 522 } 523 } else { 524 ret = __hv_remote_flush_tlb_with_range(kvm, 525 kvm_get_vcpu(kvm, 0), range); 526 } 527 528 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 529 return ret; 530 } 531 static int hv_remote_flush_tlb(struct kvm *kvm) 532 { 533 return hv_remote_flush_tlb_with_range(kvm, NULL); 534 } 535 536 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 537 { 538 struct hv_enlightened_vmcs *evmcs; 539 struct hv_partition_assist_pg **p_hv_pa_pg = 540 &vcpu->kvm->arch.hyperv.hv_pa_pg; 541 /* 542 * Synthetic VM-Exit is not enabled in current code and so All 543 * evmcs in singe VM shares same assist page. 544 */ 545 if (!*p_hv_pa_pg) 546 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 547 548 if (!*p_hv_pa_pg) 549 return -ENOMEM; 550 551 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 552 553 evmcs->partition_assist_page = 554 __pa(*p_hv_pa_pg); 555 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 556 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 557 558 return 0; 559 } 560 561 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 562 563 /* 564 * Comment's format: document - errata name - stepping - processor name. 565 * Refer from 566 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 567 */ 568 static u32 vmx_preemption_cpu_tfms[] = { 569 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 570 0x000206E6, 571 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 572 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 573 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 574 0x00020652, 575 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 576 0x00020655, 577 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 578 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 579 /* 580 * 320767.pdf - AAP86 - B1 - 581 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 582 */ 583 0x000106E5, 584 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 585 0x000106A0, 586 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 587 0x000106A1, 588 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 589 0x000106A4, 590 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 591 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 592 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 593 0x000106A5, 594 /* Xeon E3-1220 V2 */ 595 0x000306A8, 596 }; 597 598 static inline bool cpu_has_broken_vmx_preemption_timer(void) 599 { 600 u32 eax = cpuid_eax(0x00000001), i; 601 602 /* Clear the reserved bits */ 603 eax &= ~(0x3U << 14 | 0xfU << 28); 604 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 605 if (eax == vmx_preemption_cpu_tfms[i]) 606 return true; 607 608 return false; 609 } 610 611 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 612 { 613 return flexpriority_enabled && lapic_in_kernel(vcpu); 614 } 615 616 static inline bool report_flexpriority(void) 617 { 618 return flexpriority_enabled; 619 } 620 621 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 622 { 623 int i; 624 625 for (i = 0; i < vmx->nmsrs; ++i) 626 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 627 return i; 628 return -1; 629 } 630 631 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 632 { 633 int i; 634 635 i = __find_msr_index(vmx, msr); 636 if (i >= 0) 637 return &vmx->guest_msrs[i]; 638 return NULL; 639 } 640 641 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 642 { 643 vmcs_clear(loaded_vmcs->vmcs); 644 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 645 vmcs_clear(loaded_vmcs->shadow_vmcs); 646 loaded_vmcs->cpu = -1; 647 loaded_vmcs->launched = 0; 648 } 649 650 #ifdef CONFIG_KEXEC_CORE 651 /* 652 * This bitmap is used to indicate whether the vmclear 653 * operation is enabled on all cpus. All disabled by 654 * default. 655 */ 656 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 657 658 static inline void crash_enable_local_vmclear(int cpu) 659 { 660 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 661 } 662 663 static inline void crash_disable_local_vmclear(int cpu) 664 { 665 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 666 } 667 668 static inline int crash_local_vmclear_enabled(int cpu) 669 { 670 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 671 } 672 673 static void crash_vmclear_local_loaded_vmcss(void) 674 { 675 int cpu = raw_smp_processor_id(); 676 struct loaded_vmcs *v; 677 678 if (!crash_local_vmclear_enabled(cpu)) 679 return; 680 681 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 682 loaded_vmcss_on_cpu_link) 683 vmcs_clear(v->vmcs); 684 } 685 #else 686 static inline void crash_enable_local_vmclear(int cpu) { } 687 static inline void crash_disable_local_vmclear(int cpu) { } 688 #endif /* CONFIG_KEXEC_CORE */ 689 690 static void __loaded_vmcs_clear(void *arg) 691 { 692 struct loaded_vmcs *loaded_vmcs = arg; 693 int cpu = raw_smp_processor_id(); 694 695 if (loaded_vmcs->cpu != cpu) 696 return; /* vcpu migration can race with cpu offline */ 697 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 698 per_cpu(current_vmcs, cpu) = NULL; 699 crash_disable_local_vmclear(cpu); 700 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 701 702 /* 703 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 704 * is before setting loaded_vmcs->vcpu to -1 which is done in 705 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 706 * then adds the vmcs into percpu list before it is deleted. 707 */ 708 smp_wmb(); 709 710 loaded_vmcs_init(loaded_vmcs); 711 crash_enable_local_vmclear(cpu); 712 } 713 714 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 715 { 716 int cpu = loaded_vmcs->cpu; 717 718 if (cpu != -1) 719 smp_call_function_single(cpu, 720 __loaded_vmcs_clear, loaded_vmcs, 1); 721 } 722 723 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 724 unsigned field) 725 { 726 bool ret; 727 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 728 729 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { 730 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); 731 vmx->segment_cache.bitmask = 0; 732 } 733 ret = vmx->segment_cache.bitmask & mask; 734 vmx->segment_cache.bitmask |= mask; 735 return ret; 736 } 737 738 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 739 { 740 u16 *p = &vmx->segment_cache.seg[seg].selector; 741 742 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 743 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 744 return *p; 745 } 746 747 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 748 { 749 ulong *p = &vmx->segment_cache.seg[seg].base; 750 751 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 752 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 753 return *p; 754 } 755 756 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 757 { 758 u32 *p = &vmx->segment_cache.seg[seg].limit; 759 760 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 761 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 762 return *p; 763 } 764 765 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 766 { 767 u32 *p = &vmx->segment_cache.seg[seg].ar; 768 769 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 770 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 771 return *p; 772 } 773 774 void update_exception_bitmap(struct kvm_vcpu *vcpu) 775 { 776 u32 eb; 777 778 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 779 (1u << DB_VECTOR) | (1u << AC_VECTOR); 780 /* 781 * Guest access to VMware backdoor ports could legitimately 782 * trigger #GP because of TSS I/O permission bitmap. 783 * We intercept those #GP and allow access to them anyway 784 * as VMware does. 785 */ 786 if (enable_vmware_backdoor) 787 eb |= (1u << GP_VECTOR); 788 if ((vcpu->guest_debug & 789 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 790 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 791 eb |= 1u << BP_VECTOR; 792 if (to_vmx(vcpu)->rmode.vm86_active) 793 eb = ~0; 794 if (enable_ept) 795 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 796 797 /* When we are running a nested L2 guest and L1 specified for it a 798 * certain exception bitmap, we must trap the same exceptions and pass 799 * them to L1. When running L2, we will only handle the exceptions 800 * specified above if L1 did not want them. 801 */ 802 if (is_guest_mode(vcpu)) 803 eb |= get_vmcs12(vcpu)->exception_bitmap; 804 805 vmcs_write32(EXCEPTION_BITMAP, eb); 806 } 807 808 /* 809 * Check if MSR is intercepted for currently loaded MSR bitmap. 810 */ 811 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 812 { 813 unsigned long *msr_bitmap; 814 int f = sizeof(unsigned long); 815 816 if (!cpu_has_vmx_msr_bitmap()) 817 return true; 818 819 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 820 821 if (msr <= 0x1fff) { 822 return !!test_bit(msr, msr_bitmap + 0x800 / f); 823 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 824 msr &= 0x1fff; 825 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 826 } 827 828 return true; 829 } 830 831 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 832 unsigned long entry, unsigned long exit) 833 { 834 vm_entry_controls_clearbit(vmx, entry); 835 vm_exit_controls_clearbit(vmx, exit); 836 } 837 838 static int find_msr(struct vmx_msrs *m, unsigned int msr) 839 { 840 unsigned int i; 841 842 for (i = 0; i < m->nr; ++i) { 843 if (m->val[i].index == msr) 844 return i; 845 } 846 return -ENOENT; 847 } 848 849 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 850 { 851 int i; 852 struct msr_autoload *m = &vmx->msr_autoload; 853 854 switch (msr) { 855 case MSR_EFER: 856 if (cpu_has_load_ia32_efer()) { 857 clear_atomic_switch_msr_special(vmx, 858 VM_ENTRY_LOAD_IA32_EFER, 859 VM_EXIT_LOAD_IA32_EFER); 860 return; 861 } 862 break; 863 case MSR_CORE_PERF_GLOBAL_CTRL: 864 if (cpu_has_load_perf_global_ctrl()) { 865 clear_atomic_switch_msr_special(vmx, 866 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 867 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 868 return; 869 } 870 break; 871 } 872 i = find_msr(&m->guest, msr); 873 if (i < 0) 874 goto skip_guest; 875 --m->guest.nr; 876 m->guest.val[i] = m->guest.val[m->guest.nr]; 877 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 878 879 skip_guest: 880 i = find_msr(&m->host, msr); 881 if (i < 0) 882 return; 883 884 --m->host.nr; 885 m->host.val[i] = m->host.val[m->host.nr]; 886 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 887 } 888 889 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 890 unsigned long entry, unsigned long exit, 891 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 892 u64 guest_val, u64 host_val) 893 { 894 vmcs_write64(guest_val_vmcs, guest_val); 895 if (host_val_vmcs != HOST_IA32_EFER) 896 vmcs_write64(host_val_vmcs, host_val); 897 vm_entry_controls_setbit(vmx, entry); 898 vm_exit_controls_setbit(vmx, exit); 899 } 900 901 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 902 u64 guest_val, u64 host_val, bool entry_only) 903 { 904 int i, j = 0; 905 struct msr_autoload *m = &vmx->msr_autoload; 906 907 switch (msr) { 908 case MSR_EFER: 909 if (cpu_has_load_ia32_efer()) { 910 add_atomic_switch_msr_special(vmx, 911 VM_ENTRY_LOAD_IA32_EFER, 912 VM_EXIT_LOAD_IA32_EFER, 913 GUEST_IA32_EFER, 914 HOST_IA32_EFER, 915 guest_val, host_val); 916 return; 917 } 918 break; 919 case MSR_CORE_PERF_GLOBAL_CTRL: 920 if (cpu_has_load_perf_global_ctrl()) { 921 add_atomic_switch_msr_special(vmx, 922 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 923 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 924 GUEST_IA32_PERF_GLOBAL_CTRL, 925 HOST_IA32_PERF_GLOBAL_CTRL, 926 guest_val, host_val); 927 return; 928 } 929 break; 930 case MSR_IA32_PEBS_ENABLE: 931 /* PEBS needs a quiescent period after being disabled (to write 932 * a record). Disabling PEBS through VMX MSR swapping doesn't 933 * provide that period, so a CPU could write host's record into 934 * guest's memory. 935 */ 936 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 937 } 938 939 i = find_msr(&m->guest, msr); 940 if (!entry_only) 941 j = find_msr(&m->host, msr); 942 943 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) || 944 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) { 945 printk_once(KERN_WARNING "Not enough msr switch entries. " 946 "Can't add msr %x\n", msr); 947 return; 948 } 949 if (i < 0) { 950 i = m->guest.nr++; 951 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 952 } 953 m->guest.val[i].index = msr; 954 m->guest.val[i].value = guest_val; 955 956 if (entry_only) 957 return; 958 959 if (j < 0) { 960 j = m->host.nr++; 961 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 962 } 963 m->host.val[j].index = msr; 964 m->host.val[j].value = host_val; 965 } 966 967 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 968 { 969 u64 guest_efer = vmx->vcpu.arch.efer; 970 u64 ignore_bits = 0; 971 972 /* Shadow paging assumes NX to be available. */ 973 if (!enable_ept) 974 guest_efer |= EFER_NX; 975 976 /* 977 * LMA and LME handled by hardware; SCE meaningless outside long mode. 978 */ 979 ignore_bits |= EFER_SCE; 980 #ifdef CONFIG_X86_64 981 ignore_bits |= EFER_LMA | EFER_LME; 982 /* SCE is meaningful only in long mode on Intel */ 983 if (guest_efer & EFER_LMA) 984 ignore_bits &= ~(u64)EFER_SCE; 985 #endif 986 987 /* 988 * On EPT, we can't emulate NX, so we must switch EFER atomically. 989 * On CPUs that support "load IA32_EFER", always switch EFER 990 * atomically, since it's faster than switching it manually. 991 */ 992 if (cpu_has_load_ia32_efer() || 993 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 994 if (!(guest_efer & EFER_LMA)) 995 guest_efer &= ~EFER_LME; 996 if (guest_efer != host_efer) 997 add_atomic_switch_msr(vmx, MSR_EFER, 998 guest_efer, host_efer, false); 999 else 1000 clear_atomic_switch_msr(vmx, MSR_EFER); 1001 return false; 1002 } else { 1003 clear_atomic_switch_msr(vmx, MSR_EFER); 1004 1005 guest_efer &= ~ignore_bits; 1006 guest_efer |= host_efer & ignore_bits; 1007 1008 vmx->guest_msrs[efer_offset].data = guest_efer; 1009 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1010 1011 return true; 1012 } 1013 } 1014 1015 #ifdef CONFIG_X86_32 1016 /* 1017 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1018 * VMCS rather than the segment table. KVM uses this helper to figure 1019 * out the current bases to poke them into the VMCS before entry. 1020 */ 1021 static unsigned long segment_base(u16 selector) 1022 { 1023 struct desc_struct *table; 1024 unsigned long v; 1025 1026 if (!(selector & ~SEGMENT_RPL_MASK)) 1027 return 0; 1028 1029 table = get_current_gdt_ro(); 1030 1031 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1032 u16 ldt_selector = kvm_read_ldt(); 1033 1034 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1035 return 0; 1036 1037 table = (struct desc_struct *)segment_base(ldt_selector); 1038 } 1039 v = get_desc_base(&table[selector >> 3]); 1040 return v; 1041 } 1042 #endif 1043 1044 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1045 { 1046 u32 i; 1047 1048 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1049 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1050 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1051 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1052 for (i = 0; i < addr_range; i++) { 1053 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1054 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1055 } 1056 } 1057 1058 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1059 { 1060 u32 i; 1061 1062 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1063 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1064 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1065 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1066 for (i = 0; i < addr_range; i++) { 1067 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1068 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1069 } 1070 } 1071 1072 static void pt_guest_enter(struct vcpu_vmx *vmx) 1073 { 1074 if (pt_mode == PT_MODE_SYSTEM) 1075 return; 1076 1077 /* 1078 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1079 * Save host state before VM entry. 1080 */ 1081 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1082 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1083 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1084 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1085 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1086 } 1087 } 1088 1089 static void pt_guest_exit(struct vcpu_vmx *vmx) 1090 { 1091 if (pt_mode == PT_MODE_SYSTEM) 1092 return; 1093 1094 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1095 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1096 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1097 } 1098 1099 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1100 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1101 } 1102 1103 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1104 unsigned long fs_base, unsigned long gs_base) 1105 { 1106 if (unlikely(fs_sel != host->fs_sel)) { 1107 if (!(fs_sel & 7)) 1108 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1109 else 1110 vmcs_write16(HOST_FS_SELECTOR, 0); 1111 host->fs_sel = fs_sel; 1112 } 1113 if (unlikely(gs_sel != host->gs_sel)) { 1114 if (!(gs_sel & 7)) 1115 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1116 else 1117 vmcs_write16(HOST_GS_SELECTOR, 0); 1118 host->gs_sel = gs_sel; 1119 } 1120 if (unlikely(fs_base != host->fs_base)) { 1121 vmcs_writel(HOST_FS_BASE, fs_base); 1122 host->fs_base = fs_base; 1123 } 1124 if (unlikely(gs_base != host->gs_base)) { 1125 vmcs_writel(HOST_GS_BASE, gs_base); 1126 host->gs_base = gs_base; 1127 } 1128 } 1129 1130 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1131 { 1132 struct vcpu_vmx *vmx = to_vmx(vcpu); 1133 struct vmcs_host_state *host_state; 1134 #ifdef CONFIG_X86_64 1135 int cpu = raw_smp_processor_id(); 1136 #endif 1137 unsigned long fs_base, gs_base; 1138 u16 fs_sel, gs_sel; 1139 int i; 1140 1141 vmx->req_immediate_exit = false; 1142 1143 /* 1144 * Note that guest MSRs to be saved/restored can also be changed 1145 * when guest state is loaded. This happens when guest transitions 1146 * to/from long-mode by setting MSR_EFER.LMA. 1147 */ 1148 if (!vmx->guest_msrs_ready) { 1149 vmx->guest_msrs_ready = true; 1150 for (i = 0; i < vmx->save_nmsrs; ++i) 1151 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1152 vmx->guest_msrs[i].data, 1153 vmx->guest_msrs[i].mask); 1154 1155 } 1156 if (vmx->guest_state_loaded) 1157 return; 1158 1159 host_state = &vmx->loaded_vmcs->host_state; 1160 1161 /* 1162 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1163 * allow segment selectors with cpl > 0 or ti == 1. 1164 */ 1165 host_state->ldt_sel = kvm_read_ldt(); 1166 1167 #ifdef CONFIG_X86_64 1168 savesegment(ds, host_state->ds_sel); 1169 savesegment(es, host_state->es_sel); 1170 1171 gs_base = cpu_kernelmode_gs_base(cpu); 1172 if (likely(is_64bit_mm(current->mm))) { 1173 save_fsgs_for_kvm(); 1174 fs_sel = current->thread.fsindex; 1175 gs_sel = current->thread.gsindex; 1176 fs_base = current->thread.fsbase; 1177 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1178 } else { 1179 savesegment(fs, fs_sel); 1180 savesegment(gs, gs_sel); 1181 fs_base = read_msr(MSR_FS_BASE); 1182 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1183 } 1184 1185 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1186 #else 1187 savesegment(fs, fs_sel); 1188 savesegment(gs, gs_sel); 1189 fs_base = segment_base(fs_sel); 1190 gs_base = segment_base(gs_sel); 1191 #endif 1192 1193 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1194 vmx->guest_state_loaded = true; 1195 } 1196 1197 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1198 { 1199 struct vmcs_host_state *host_state; 1200 1201 if (!vmx->guest_state_loaded) 1202 return; 1203 1204 host_state = &vmx->loaded_vmcs->host_state; 1205 1206 ++vmx->vcpu.stat.host_state_reload; 1207 1208 #ifdef CONFIG_X86_64 1209 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1210 #endif 1211 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1212 kvm_load_ldt(host_state->ldt_sel); 1213 #ifdef CONFIG_X86_64 1214 load_gs_index(host_state->gs_sel); 1215 #else 1216 loadsegment(gs, host_state->gs_sel); 1217 #endif 1218 } 1219 if (host_state->fs_sel & 7) 1220 loadsegment(fs, host_state->fs_sel); 1221 #ifdef CONFIG_X86_64 1222 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1223 loadsegment(ds, host_state->ds_sel); 1224 loadsegment(es, host_state->es_sel); 1225 } 1226 #endif 1227 invalidate_tss_limit(); 1228 #ifdef CONFIG_X86_64 1229 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1230 #endif 1231 load_fixmap_gdt(raw_smp_processor_id()); 1232 vmx->guest_state_loaded = false; 1233 vmx->guest_msrs_ready = false; 1234 } 1235 1236 #ifdef CONFIG_X86_64 1237 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1238 { 1239 preempt_disable(); 1240 if (vmx->guest_state_loaded) 1241 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1242 preempt_enable(); 1243 return vmx->msr_guest_kernel_gs_base; 1244 } 1245 1246 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1247 { 1248 preempt_disable(); 1249 if (vmx->guest_state_loaded) 1250 wrmsrl(MSR_KERNEL_GS_BASE, data); 1251 preempt_enable(); 1252 vmx->msr_guest_kernel_gs_base = data; 1253 } 1254 #endif 1255 1256 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1257 { 1258 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1259 struct pi_desc old, new; 1260 unsigned int dest; 1261 1262 /* 1263 * In case of hot-plug or hot-unplug, we may have to undo 1264 * vmx_vcpu_pi_put even if there is no assigned device. And we 1265 * always keep PI.NDST up to date for simplicity: it makes the 1266 * code easier, and CPU migration is not a fast path. 1267 */ 1268 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1269 return; 1270 1271 /* The full case. */ 1272 do { 1273 old.control = new.control = pi_desc->control; 1274 1275 dest = cpu_physical_id(cpu); 1276 1277 if (x2apic_enabled()) 1278 new.ndst = dest; 1279 else 1280 new.ndst = (dest << 8) & 0xFF00; 1281 1282 new.sn = 0; 1283 } while (cmpxchg64(&pi_desc->control, old.control, 1284 new.control) != old.control); 1285 1286 /* 1287 * Clear SN before reading the bitmap. The VT-d firmware 1288 * writes the bitmap and reads SN atomically (5.2.3 in the 1289 * spec), so it doesn't really have a memory barrier that 1290 * pairs with this, but we cannot do that and we need one. 1291 */ 1292 smp_mb__after_atomic(); 1293 1294 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS)) 1295 pi_set_on(pi_desc); 1296 } 1297 1298 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1299 { 1300 struct vcpu_vmx *vmx = to_vmx(vcpu); 1301 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1302 1303 if (!already_loaded) { 1304 loaded_vmcs_clear(vmx->loaded_vmcs); 1305 local_irq_disable(); 1306 crash_disable_local_vmclear(cpu); 1307 1308 /* 1309 * Read loaded_vmcs->cpu should be before fetching 1310 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1311 * See the comments in __loaded_vmcs_clear(). 1312 */ 1313 smp_rmb(); 1314 1315 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1316 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1317 crash_enable_local_vmclear(cpu); 1318 local_irq_enable(); 1319 } 1320 1321 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1322 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1323 vmcs_load(vmx->loaded_vmcs->vmcs); 1324 indirect_branch_prediction_barrier(); 1325 } 1326 1327 if (!already_loaded) { 1328 void *gdt = get_current_gdt_ro(); 1329 unsigned long sysenter_esp; 1330 1331 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1332 1333 /* 1334 * Linux uses per-cpu TSS and GDT, so set these when switching 1335 * processors. See 22.2.4. 1336 */ 1337 vmcs_writel(HOST_TR_BASE, 1338 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1339 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1340 1341 /* 1342 * VM exits change the host TR limit to 0x67 after a VM 1343 * exit. This is okay, since 0x67 covers everything except 1344 * the IO bitmap and have have code to handle the IO bitmap 1345 * being lost after a VM exit. 1346 */ 1347 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); 1348 1349 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1350 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1351 1352 vmx->loaded_vmcs->cpu = cpu; 1353 } 1354 1355 /* Setup TSC multiplier */ 1356 if (kvm_has_tsc_control && 1357 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1358 decache_tsc_multiplier(vmx); 1359 } 1360 1361 /* 1362 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1363 * vcpu mutex is already taken. 1364 */ 1365 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1366 { 1367 struct vcpu_vmx *vmx = to_vmx(vcpu); 1368 1369 vmx_vcpu_load_vmcs(vcpu, cpu); 1370 1371 vmx_vcpu_pi_load(vcpu, cpu); 1372 1373 vmx->host_pkru = read_pkru(); 1374 vmx->host_debugctlmsr = get_debugctlmsr(); 1375 } 1376 1377 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1378 { 1379 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1380 1381 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1382 !irq_remapping_cap(IRQ_POSTING_CAP) || 1383 !kvm_vcpu_apicv_active(vcpu)) 1384 return; 1385 1386 /* Set SN when the vCPU is preempted */ 1387 if (vcpu->preempted) 1388 pi_set_sn(pi_desc); 1389 } 1390 1391 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1392 { 1393 vmx_vcpu_pi_put(vcpu); 1394 1395 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1396 } 1397 1398 static bool emulation_required(struct kvm_vcpu *vcpu) 1399 { 1400 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1401 } 1402 1403 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); 1404 1405 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1406 { 1407 unsigned long rflags, save_rflags; 1408 1409 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { 1410 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); 1411 rflags = vmcs_readl(GUEST_RFLAGS); 1412 if (to_vmx(vcpu)->rmode.vm86_active) { 1413 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1414 save_rflags = to_vmx(vcpu)->rmode.save_rflags; 1415 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1416 } 1417 to_vmx(vcpu)->rflags = rflags; 1418 } 1419 return to_vmx(vcpu)->rflags; 1420 } 1421 1422 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1423 { 1424 unsigned long old_rflags = vmx_get_rflags(vcpu); 1425 1426 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); 1427 to_vmx(vcpu)->rflags = rflags; 1428 if (to_vmx(vcpu)->rmode.vm86_active) { 1429 to_vmx(vcpu)->rmode.save_rflags = rflags; 1430 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1431 } 1432 vmcs_writel(GUEST_RFLAGS, rflags); 1433 1434 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM) 1435 to_vmx(vcpu)->emulation_required = emulation_required(vcpu); 1436 } 1437 1438 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1439 { 1440 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1441 int ret = 0; 1442 1443 if (interruptibility & GUEST_INTR_STATE_STI) 1444 ret |= KVM_X86_SHADOW_INT_STI; 1445 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1446 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1447 1448 return ret; 1449 } 1450 1451 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1452 { 1453 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1454 u32 interruptibility = interruptibility_old; 1455 1456 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1457 1458 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1459 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1460 else if (mask & KVM_X86_SHADOW_INT_STI) 1461 interruptibility |= GUEST_INTR_STATE_STI; 1462 1463 if ((interruptibility != interruptibility_old)) 1464 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1465 } 1466 1467 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1468 { 1469 struct vcpu_vmx *vmx = to_vmx(vcpu); 1470 unsigned long value; 1471 1472 /* 1473 * Any MSR write that attempts to change bits marked reserved will 1474 * case a #GP fault. 1475 */ 1476 if (data & vmx->pt_desc.ctl_bitmask) 1477 return 1; 1478 1479 /* 1480 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1481 * result in a #GP unless the same write also clears TraceEn. 1482 */ 1483 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1484 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1485 return 1; 1486 1487 /* 1488 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1489 * and FabricEn would cause #GP, if 1490 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1491 */ 1492 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1493 !(data & RTIT_CTL_FABRIC_EN) && 1494 !intel_pt_validate_cap(vmx->pt_desc.caps, 1495 PT_CAP_single_range_output)) 1496 return 1; 1497 1498 /* 1499 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1500 * utilize encodings marked reserved will casue a #GP fault. 1501 */ 1502 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1503 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1504 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1505 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1506 return 1; 1507 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1508 PT_CAP_cycle_thresholds); 1509 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1510 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1511 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1512 return 1; 1513 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1514 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1515 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1516 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1517 return 1; 1518 1519 /* 1520 * If ADDRx_CFG is reserved or the encodings is >2 will 1521 * cause a #GP fault. 1522 */ 1523 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1524 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1525 return 1; 1526 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1527 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1528 return 1; 1529 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1530 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1531 return 1; 1532 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1533 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1534 return 1; 1535 1536 return 0; 1537 } 1538 1539 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1540 { 1541 unsigned long rip; 1542 1543 /* 1544 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1545 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1546 * set when EPT misconfig occurs. In practice, real hardware updates 1547 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1548 * (namely Hyper-V) don't set it due to it being undefined behavior, 1549 * i.e. we end up advancing IP with some random value. 1550 */ 1551 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1552 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1553 rip = kvm_rip_read(vcpu); 1554 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1555 kvm_rip_write(vcpu, rip); 1556 } else { 1557 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1558 return 0; 1559 } 1560 1561 /* skipping an emulated instruction also counts */ 1562 vmx_set_interrupt_shadow(vcpu, 0); 1563 1564 return 1; 1565 } 1566 1567 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1568 { 1569 /* 1570 * Ensure that we clear the HLT state in the VMCS. We don't need to 1571 * explicitly skip the instruction because if the HLT state is set, 1572 * then the instruction is already executing and RIP has already been 1573 * advanced. 1574 */ 1575 if (kvm_hlt_in_guest(vcpu->kvm) && 1576 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1577 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1578 } 1579 1580 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1581 { 1582 struct vcpu_vmx *vmx = to_vmx(vcpu); 1583 unsigned nr = vcpu->arch.exception.nr; 1584 bool has_error_code = vcpu->arch.exception.has_error_code; 1585 u32 error_code = vcpu->arch.exception.error_code; 1586 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1587 1588 kvm_deliver_exception_payload(vcpu); 1589 1590 if (has_error_code) { 1591 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1592 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1593 } 1594 1595 if (vmx->rmode.vm86_active) { 1596 int inc_eip = 0; 1597 if (kvm_exception_is_soft(nr)) 1598 inc_eip = vcpu->arch.event_exit_inst_len; 1599 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1600 return; 1601 } 1602 1603 WARN_ON_ONCE(vmx->emulation_required); 1604 1605 if (kvm_exception_is_soft(nr)) { 1606 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1607 vmx->vcpu.arch.event_exit_inst_len); 1608 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1609 } else 1610 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1611 1612 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1613 1614 vmx_clear_hlt(vcpu); 1615 } 1616 1617 static bool vmx_rdtscp_supported(void) 1618 { 1619 return cpu_has_vmx_rdtscp(); 1620 } 1621 1622 static bool vmx_invpcid_supported(void) 1623 { 1624 return cpu_has_vmx_invpcid(); 1625 } 1626 1627 /* 1628 * Swap MSR entry in host/guest MSR entry array. 1629 */ 1630 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1631 { 1632 struct shared_msr_entry tmp; 1633 1634 tmp = vmx->guest_msrs[to]; 1635 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1636 vmx->guest_msrs[from] = tmp; 1637 } 1638 1639 /* 1640 * Set up the vmcs to automatically save and restore system 1641 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1642 * mode, as fiddling with msrs is very expensive. 1643 */ 1644 static void setup_msrs(struct vcpu_vmx *vmx) 1645 { 1646 int save_nmsrs, index; 1647 1648 save_nmsrs = 0; 1649 #ifdef CONFIG_X86_64 1650 /* 1651 * The SYSCALL MSRs are only needed on long mode guests, and only 1652 * when EFER.SCE is set. 1653 */ 1654 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1655 index = __find_msr_index(vmx, MSR_STAR); 1656 if (index >= 0) 1657 move_msr_up(vmx, index, save_nmsrs++); 1658 index = __find_msr_index(vmx, MSR_LSTAR); 1659 if (index >= 0) 1660 move_msr_up(vmx, index, save_nmsrs++); 1661 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1662 if (index >= 0) 1663 move_msr_up(vmx, index, save_nmsrs++); 1664 } 1665 #endif 1666 index = __find_msr_index(vmx, MSR_EFER); 1667 if (index >= 0 && update_transition_efer(vmx, index)) 1668 move_msr_up(vmx, index, save_nmsrs++); 1669 index = __find_msr_index(vmx, MSR_TSC_AUX); 1670 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1671 move_msr_up(vmx, index, save_nmsrs++); 1672 1673 vmx->save_nmsrs = save_nmsrs; 1674 vmx->guest_msrs_ready = false; 1675 1676 if (cpu_has_vmx_msr_bitmap()) 1677 vmx_update_msr_bitmap(&vmx->vcpu); 1678 } 1679 1680 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1681 { 1682 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1683 1684 if (is_guest_mode(vcpu) && 1685 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) 1686 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1687 1688 return vcpu->arch.tsc_offset; 1689 } 1690 1691 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1692 { 1693 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1694 u64 g_tsc_offset = 0; 1695 1696 /* 1697 * We're here if L1 chose not to trap WRMSR to TSC. According 1698 * to the spec, this should set L1's TSC; The offset that L1 1699 * set for L2 remains unchanged, and still needs to be added 1700 * to the newly set TSC to get L2's TSC. 1701 */ 1702 if (is_guest_mode(vcpu) && 1703 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) 1704 g_tsc_offset = vmcs12->tsc_offset; 1705 1706 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1707 vcpu->arch.tsc_offset - g_tsc_offset, 1708 offset); 1709 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1710 return offset + g_tsc_offset; 1711 } 1712 1713 /* 1714 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1715 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1716 * all guests if the "nested" module option is off, and can also be disabled 1717 * for a single guest by disabling its VMX cpuid bit. 1718 */ 1719 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1720 { 1721 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1722 } 1723 1724 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1725 uint64_t val) 1726 { 1727 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1728 1729 return !(val & ~valid_bits); 1730 } 1731 1732 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1733 { 1734 switch (msr->index) { 1735 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1736 if (!nested) 1737 return 1; 1738 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1739 default: 1740 return 1; 1741 } 1742 1743 return 0; 1744 } 1745 1746 /* 1747 * Reads an msr value (of 'msr_index') into 'pdata'. 1748 * Returns 0 on success, non-0 otherwise. 1749 * Assumes vcpu_load() was already called. 1750 */ 1751 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1752 { 1753 struct vcpu_vmx *vmx = to_vmx(vcpu); 1754 struct shared_msr_entry *msr; 1755 u32 index; 1756 1757 switch (msr_info->index) { 1758 #ifdef CONFIG_X86_64 1759 case MSR_FS_BASE: 1760 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1761 break; 1762 case MSR_GS_BASE: 1763 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1764 break; 1765 case MSR_KERNEL_GS_BASE: 1766 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1767 break; 1768 #endif 1769 case MSR_EFER: 1770 return kvm_get_msr_common(vcpu, msr_info); 1771 case MSR_IA32_UMWAIT_CONTROL: 1772 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1773 return 1; 1774 1775 msr_info->data = vmx->msr_ia32_umwait_control; 1776 break; 1777 case MSR_IA32_SPEC_CTRL: 1778 if (!msr_info->host_initiated && 1779 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1780 return 1; 1781 1782 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1783 break; 1784 case MSR_IA32_SYSENTER_CS: 1785 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1786 break; 1787 case MSR_IA32_SYSENTER_EIP: 1788 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1789 break; 1790 case MSR_IA32_SYSENTER_ESP: 1791 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1792 break; 1793 case MSR_IA32_BNDCFGS: 1794 if (!kvm_mpx_supported() || 1795 (!msr_info->host_initiated && 1796 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1797 return 1; 1798 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1799 break; 1800 case MSR_IA32_MCG_EXT_CTL: 1801 if (!msr_info->host_initiated && 1802 !(vmx->msr_ia32_feature_control & 1803 FEATURE_CONTROL_LMCE)) 1804 return 1; 1805 msr_info->data = vcpu->arch.mcg_ext_ctl; 1806 break; 1807 case MSR_IA32_FEATURE_CONTROL: 1808 msr_info->data = vmx->msr_ia32_feature_control; 1809 break; 1810 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1811 if (!nested_vmx_allowed(vcpu)) 1812 return 1; 1813 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1814 &msr_info->data); 1815 case MSR_IA32_XSS: 1816 if (!vmx_xsaves_supported() || 1817 (!msr_info->host_initiated && 1818 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 1819 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)))) 1820 return 1; 1821 msr_info->data = vcpu->arch.ia32_xss; 1822 break; 1823 case MSR_IA32_RTIT_CTL: 1824 if (pt_mode != PT_MODE_HOST_GUEST) 1825 return 1; 1826 msr_info->data = vmx->pt_desc.guest.ctl; 1827 break; 1828 case MSR_IA32_RTIT_STATUS: 1829 if (pt_mode != PT_MODE_HOST_GUEST) 1830 return 1; 1831 msr_info->data = vmx->pt_desc.guest.status; 1832 break; 1833 case MSR_IA32_RTIT_CR3_MATCH: 1834 if ((pt_mode != PT_MODE_HOST_GUEST) || 1835 !intel_pt_validate_cap(vmx->pt_desc.caps, 1836 PT_CAP_cr3_filtering)) 1837 return 1; 1838 msr_info->data = vmx->pt_desc.guest.cr3_match; 1839 break; 1840 case MSR_IA32_RTIT_OUTPUT_BASE: 1841 if ((pt_mode != PT_MODE_HOST_GUEST) || 1842 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1843 PT_CAP_topa_output) && 1844 !intel_pt_validate_cap(vmx->pt_desc.caps, 1845 PT_CAP_single_range_output))) 1846 return 1; 1847 msr_info->data = vmx->pt_desc.guest.output_base; 1848 break; 1849 case MSR_IA32_RTIT_OUTPUT_MASK: 1850 if ((pt_mode != PT_MODE_HOST_GUEST) || 1851 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1852 PT_CAP_topa_output) && 1853 !intel_pt_validate_cap(vmx->pt_desc.caps, 1854 PT_CAP_single_range_output))) 1855 return 1; 1856 msr_info->data = vmx->pt_desc.guest.output_mask; 1857 break; 1858 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1859 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1860 if ((pt_mode != PT_MODE_HOST_GUEST) || 1861 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1862 PT_CAP_num_address_ranges))) 1863 return 1; 1864 if (index % 2) 1865 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1866 else 1867 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1868 break; 1869 case MSR_TSC_AUX: 1870 if (!msr_info->host_initiated && 1871 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1872 return 1; 1873 /* Else, falls through */ 1874 default: 1875 msr = find_msr_entry(vmx, msr_info->index); 1876 if (msr) { 1877 msr_info->data = msr->data; 1878 break; 1879 } 1880 return kvm_get_msr_common(vcpu, msr_info); 1881 } 1882 1883 return 0; 1884 } 1885 1886 /* 1887 * Writes msr value into into the appropriate "register". 1888 * Returns 0 on success, non-0 otherwise. 1889 * Assumes vcpu_load() was already called. 1890 */ 1891 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1892 { 1893 struct vcpu_vmx *vmx = to_vmx(vcpu); 1894 struct shared_msr_entry *msr; 1895 int ret = 0; 1896 u32 msr_index = msr_info->index; 1897 u64 data = msr_info->data; 1898 u32 index; 1899 1900 switch (msr_index) { 1901 case MSR_EFER: 1902 ret = kvm_set_msr_common(vcpu, msr_info); 1903 break; 1904 #ifdef CONFIG_X86_64 1905 case MSR_FS_BASE: 1906 vmx_segment_cache_clear(vmx); 1907 vmcs_writel(GUEST_FS_BASE, data); 1908 break; 1909 case MSR_GS_BASE: 1910 vmx_segment_cache_clear(vmx); 1911 vmcs_writel(GUEST_GS_BASE, data); 1912 break; 1913 case MSR_KERNEL_GS_BASE: 1914 vmx_write_guest_kernel_gs_base(vmx, data); 1915 break; 1916 #endif 1917 case MSR_IA32_SYSENTER_CS: 1918 if (is_guest_mode(vcpu)) 1919 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1920 vmcs_write32(GUEST_SYSENTER_CS, data); 1921 break; 1922 case MSR_IA32_SYSENTER_EIP: 1923 if (is_guest_mode(vcpu)) 1924 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1925 vmcs_writel(GUEST_SYSENTER_EIP, data); 1926 break; 1927 case MSR_IA32_SYSENTER_ESP: 1928 if (is_guest_mode(vcpu)) 1929 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1930 vmcs_writel(GUEST_SYSENTER_ESP, data); 1931 break; 1932 case MSR_IA32_DEBUGCTLMSR: 1933 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1934 VM_EXIT_SAVE_DEBUG_CONTROLS) 1935 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1936 1937 ret = kvm_set_msr_common(vcpu, msr_info); 1938 break; 1939 1940 case MSR_IA32_BNDCFGS: 1941 if (!kvm_mpx_supported() || 1942 (!msr_info->host_initiated && 1943 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1944 return 1; 1945 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1946 (data & MSR_IA32_BNDCFGS_RSVD)) 1947 return 1; 1948 vmcs_write64(GUEST_BNDCFGS, data); 1949 break; 1950 case MSR_IA32_UMWAIT_CONTROL: 1951 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1952 return 1; 1953 1954 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 1955 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 1956 return 1; 1957 1958 vmx->msr_ia32_umwait_control = data; 1959 break; 1960 case MSR_IA32_SPEC_CTRL: 1961 if (!msr_info->host_initiated && 1962 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1963 return 1; 1964 1965 /* The STIBP bit doesn't fault even if it's not advertised */ 1966 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) 1967 return 1; 1968 1969 vmx->spec_ctrl = data; 1970 1971 if (!data) 1972 break; 1973 1974 /* 1975 * For non-nested: 1976 * When it's written (to non-zero) for the first time, pass 1977 * it through. 1978 * 1979 * For nested: 1980 * The handling of the MSR bitmap for L2 guests is done in 1981 * nested_vmx_merge_msr_bitmap. We should not touch the 1982 * vmcs02.msr_bitmap here since it gets completely overwritten 1983 * in the merging. We update the vmcs01 here for L1 as well 1984 * since it will end up touching the MSR anyway now. 1985 */ 1986 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 1987 MSR_IA32_SPEC_CTRL, 1988 MSR_TYPE_RW); 1989 break; 1990 case MSR_IA32_PRED_CMD: 1991 if (!msr_info->host_initiated && 1992 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1993 return 1; 1994 1995 if (data & ~PRED_CMD_IBPB) 1996 return 1; 1997 1998 if (!data) 1999 break; 2000 2001 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2002 2003 /* 2004 * For non-nested: 2005 * When it's written (to non-zero) for the first time, pass 2006 * it through. 2007 * 2008 * For nested: 2009 * The handling of the MSR bitmap for L2 guests is done in 2010 * nested_vmx_merge_msr_bitmap. We should not touch the 2011 * vmcs02.msr_bitmap here since it gets completely overwritten 2012 * in the merging. 2013 */ 2014 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2015 MSR_TYPE_W); 2016 break; 2017 case MSR_IA32_CR_PAT: 2018 if (!kvm_pat_valid(data)) 2019 return 1; 2020 2021 if (is_guest_mode(vcpu) && 2022 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2023 get_vmcs12(vcpu)->guest_ia32_pat = data; 2024 2025 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2026 vmcs_write64(GUEST_IA32_PAT, data); 2027 vcpu->arch.pat = data; 2028 break; 2029 } 2030 ret = kvm_set_msr_common(vcpu, msr_info); 2031 break; 2032 case MSR_IA32_TSC_ADJUST: 2033 ret = kvm_set_msr_common(vcpu, msr_info); 2034 break; 2035 case MSR_IA32_MCG_EXT_CTL: 2036 if ((!msr_info->host_initiated && 2037 !(to_vmx(vcpu)->msr_ia32_feature_control & 2038 FEATURE_CONTROL_LMCE)) || 2039 (data & ~MCG_EXT_CTL_LMCE_EN)) 2040 return 1; 2041 vcpu->arch.mcg_ext_ctl = data; 2042 break; 2043 case MSR_IA32_FEATURE_CONTROL: 2044 if (!vmx_feature_control_msr_valid(vcpu, data) || 2045 (to_vmx(vcpu)->msr_ia32_feature_control & 2046 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) 2047 return 1; 2048 vmx->msr_ia32_feature_control = data; 2049 if (msr_info->host_initiated && data == 0) 2050 vmx_leave_nested(vcpu); 2051 break; 2052 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2053 if (!msr_info->host_initiated) 2054 return 1; /* they are read-only */ 2055 if (!nested_vmx_allowed(vcpu)) 2056 return 1; 2057 return vmx_set_vmx_msr(vcpu, msr_index, data); 2058 case MSR_IA32_XSS: 2059 if (!vmx_xsaves_supported() || 2060 (!msr_info->host_initiated && 2061 !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 2062 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)))) 2063 return 1; 2064 /* 2065 * The only supported bit as of Skylake is bit 8, but 2066 * it is not supported on KVM. 2067 */ 2068 if (data != 0) 2069 return 1; 2070 vcpu->arch.ia32_xss = data; 2071 if (vcpu->arch.ia32_xss != host_xss) 2072 add_atomic_switch_msr(vmx, MSR_IA32_XSS, 2073 vcpu->arch.ia32_xss, host_xss, false); 2074 else 2075 clear_atomic_switch_msr(vmx, MSR_IA32_XSS); 2076 break; 2077 case MSR_IA32_RTIT_CTL: 2078 if ((pt_mode != PT_MODE_HOST_GUEST) || 2079 vmx_rtit_ctl_check(vcpu, data) || 2080 vmx->nested.vmxon) 2081 return 1; 2082 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2083 vmx->pt_desc.guest.ctl = data; 2084 pt_update_intercept_for_msr(vmx); 2085 break; 2086 case MSR_IA32_RTIT_STATUS: 2087 if ((pt_mode != PT_MODE_HOST_GUEST) || 2088 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2089 (data & MSR_IA32_RTIT_STATUS_MASK)) 2090 return 1; 2091 vmx->pt_desc.guest.status = data; 2092 break; 2093 case MSR_IA32_RTIT_CR3_MATCH: 2094 if ((pt_mode != PT_MODE_HOST_GUEST) || 2095 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2096 !intel_pt_validate_cap(vmx->pt_desc.caps, 2097 PT_CAP_cr3_filtering)) 2098 return 1; 2099 vmx->pt_desc.guest.cr3_match = data; 2100 break; 2101 case MSR_IA32_RTIT_OUTPUT_BASE: 2102 if ((pt_mode != PT_MODE_HOST_GUEST) || 2103 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2104 (!intel_pt_validate_cap(vmx->pt_desc.caps, 2105 PT_CAP_topa_output) && 2106 !intel_pt_validate_cap(vmx->pt_desc.caps, 2107 PT_CAP_single_range_output)) || 2108 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)) 2109 return 1; 2110 vmx->pt_desc.guest.output_base = data; 2111 break; 2112 case MSR_IA32_RTIT_OUTPUT_MASK: 2113 if ((pt_mode != PT_MODE_HOST_GUEST) || 2114 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2115 (!intel_pt_validate_cap(vmx->pt_desc.caps, 2116 PT_CAP_topa_output) && 2117 !intel_pt_validate_cap(vmx->pt_desc.caps, 2118 PT_CAP_single_range_output))) 2119 return 1; 2120 vmx->pt_desc.guest.output_mask = data; 2121 break; 2122 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2123 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2124 if ((pt_mode != PT_MODE_HOST_GUEST) || 2125 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2126 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2127 PT_CAP_num_address_ranges))) 2128 return 1; 2129 if (index % 2) 2130 vmx->pt_desc.guest.addr_b[index / 2] = data; 2131 else 2132 vmx->pt_desc.guest.addr_a[index / 2] = data; 2133 break; 2134 case MSR_TSC_AUX: 2135 if (!msr_info->host_initiated && 2136 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2137 return 1; 2138 /* Check reserved bit, higher 32 bits should be zero */ 2139 if ((data >> 32) != 0) 2140 return 1; 2141 /* Else, falls through */ 2142 default: 2143 msr = find_msr_entry(vmx, msr_index); 2144 if (msr) { 2145 u64 old_msr_data = msr->data; 2146 msr->data = data; 2147 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 2148 preempt_disable(); 2149 ret = kvm_set_shared_msr(msr->index, msr->data, 2150 msr->mask); 2151 preempt_enable(); 2152 if (ret) 2153 msr->data = old_msr_data; 2154 } 2155 break; 2156 } 2157 ret = kvm_set_msr_common(vcpu, msr_info); 2158 } 2159 2160 return ret; 2161 } 2162 2163 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2164 { 2165 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); 2166 switch (reg) { 2167 case VCPU_REGS_RSP: 2168 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2169 break; 2170 case VCPU_REGS_RIP: 2171 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2172 break; 2173 case VCPU_EXREG_PDPTR: 2174 if (enable_ept) 2175 ept_save_pdptrs(vcpu); 2176 break; 2177 default: 2178 break; 2179 } 2180 } 2181 2182 static __init int cpu_has_kvm_support(void) 2183 { 2184 return cpu_has_vmx(); 2185 } 2186 2187 static __init int vmx_disabled_by_bios(void) 2188 { 2189 u64 msr; 2190 2191 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); 2192 if (msr & FEATURE_CONTROL_LOCKED) { 2193 /* launched w/ TXT and VMX disabled */ 2194 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) 2195 && tboot_enabled()) 2196 return 1; 2197 /* launched w/o TXT and VMX only enabled w/ TXT */ 2198 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) 2199 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) 2200 && !tboot_enabled()) { 2201 printk(KERN_WARNING "kvm: disable TXT in the BIOS or " 2202 "activate TXT before enabling KVM\n"); 2203 return 1; 2204 } 2205 /* launched w/o TXT and VMX disabled */ 2206 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) 2207 && !tboot_enabled()) 2208 return 1; 2209 } 2210 2211 return 0; 2212 } 2213 2214 static void kvm_cpu_vmxon(u64 addr) 2215 { 2216 cr4_set_bits(X86_CR4_VMXE); 2217 intel_pt_handle_vmx(1); 2218 2219 asm volatile ("vmxon %0" : : "m"(addr)); 2220 } 2221 2222 static int hardware_enable(void) 2223 { 2224 int cpu = raw_smp_processor_id(); 2225 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2226 u64 old, test_bits; 2227 2228 if (cr4_read_shadow() & X86_CR4_VMXE) 2229 return -EBUSY; 2230 2231 /* 2232 * This can happen if we hot-added a CPU but failed to allocate 2233 * VP assist page for it. 2234 */ 2235 if (static_branch_unlikely(&enable_evmcs) && 2236 !hv_get_vp_assist_page(cpu)) 2237 return -EFAULT; 2238 2239 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2240 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2241 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2242 2243 /* 2244 * Now we can enable the vmclear operation in kdump 2245 * since the loaded_vmcss_on_cpu list on this cpu 2246 * has been initialized. 2247 * 2248 * Though the cpu is not in VMX operation now, there 2249 * is no problem to enable the vmclear operation 2250 * for the loaded_vmcss_on_cpu list is empty! 2251 */ 2252 crash_enable_local_vmclear(cpu); 2253 2254 rdmsrl(MSR_IA32_FEATURE_CONTROL, old); 2255 2256 test_bits = FEATURE_CONTROL_LOCKED; 2257 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 2258 if (tboot_enabled()) 2259 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; 2260 2261 if ((old & test_bits) != test_bits) { 2262 /* enable and lock */ 2263 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); 2264 } 2265 kvm_cpu_vmxon(phys_addr); 2266 if (enable_ept) 2267 ept_sync_global(); 2268 2269 return 0; 2270 } 2271 2272 static void vmclear_local_loaded_vmcss(void) 2273 { 2274 int cpu = raw_smp_processor_id(); 2275 struct loaded_vmcs *v, *n; 2276 2277 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2278 loaded_vmcss_on_cpu_link) 2279 __loaded_vmcs_clear(v); 2280 } 2281 2282 2283 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2284 * tricks. 2285 */ 2286 static void kvm_cpu_vmxoff(void) 2287 { 2288 asm volatile (__ex("vmxoff")); 2289 2290 intel_pt_handle_vmx(0); 2291 cr4_clear_bits(X86_CR4_VMXE); 2292 } 2293 2294 static void hardware_disable(void) 2295 { 2296 vmclear_local_loaded_vmcss(); 2297 kvm_cpu_vmxoff(); 2298 } 2299 2300 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2301 u32 msr, u32 *result) 2302 { 2303 u32 vmx_msr_low, vmx_msr_high; 2304 u32 ctl = ctl_min | ctl_opt; 2305 2306 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2307 2308 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2309 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2310 2311 /* Ensure minimum (required) set of control bits are supported. */ 2312 if (ctl_min & ~ctl) 2313 return -EIO; 2314 2315 *result = ctl; 2316 return 0; 2317 } 2318 2319 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2320 struct vmx_capability *vmx_cap) 2321 { 2322 u32 vmx_msr_low, vmx_msr_high; 2323 u32 min, opt, min2, opt2; 2324 u32 _pin_based_exec_control = 0; 2325 u32 _cpu_based_exec_control = 0; 2326 u32 _cpu_based_2nd_exec_control = 0; 2327 u32 _vmexit_control = 0; 2328 u32 _vmentry_control = 0; 2329 2330 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2331 min = CPU_BASED_HLT_EXITING | 2332 #ifdef CONFIG_X86_64 2333 CPU_BASED_CR8_LOAD_EXITING | 2334 CPU_BASED_CR8_STORE_EXITING | 2335 #endif 2336 CPU_BASED_CR3_LOAD_EXITING | 2337 CPU_BASED_CR3_STORE_EXITING | 2338 CPU_BASED_UNCOND_IO_EXITING | 2339 CPU_BASED_MOV_DR_EXITING | 2340 CPU_BASED_USE_TSC_OFFSETING | 2341 CPU_BASED_MWAIT_EXITING | 2342 CPU_BASED_MONITOR_EXITING | 2343 CPU_BASED_INVLPG_EXITING | 2344 CPU_BASED_RDPMC_EXITING; 2345 2346 opt = CPU_BASED_TPR_SHADOW | 2347 CPU_BASED_USE_MSR_BITMAPS | 2348 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2349 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2350 &_cpu_based_exec_control) < 0) 2351 return -EIO; 2352 #ifdef CONFIG_X86_64 2353 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2354 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2355 ~CPU_BASED_CR8_STORE_EXITING; 2356 #endif 2357 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2358 min2 = 0; 2359 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2360 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2361 SECONDARY_EXEC_WBINVD_EXITING | 2362 SECONDARY_EXEC_ENABLE_VPID | 2363 SECONDARY_EXEC_ENABLE_EPT | 2364 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2365 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2366 SECONDARY_EXEC_DESC | 2367 SECONDARY_EXEC_RDTSCP | 2368 SECONDARY_EXEC_ENABLE_INVPCID | 2369 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2370 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2371 SECONDARY_EXEC_SHADOW_VMCS | 2372 SECONDARY_EXEC_XSAVES | 2373 SECONDARY_EXEC_RDSEED_EXITING | 2374 SECONDARY_EXEC_RDRAND_EXITING | 2375 SECONDARY_EXEC_ENABLE_PML | 2376 SECONDARY_EXEC_TSC_SCALING | 2377 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2378 SECONDARY_EXEC_PT_USE_GPA | 2379 SECONDARY_EXEC_PT_CONCEAL_VMX | 2380 SECONDARY_EXEC_ENABLE_VMFUNC | 2381 SECONDARY_EXEC_ENCLS_EXITING; 2382 if (adjust_vmx_controls(min2, opt2, 2383 MSR_IA32_VMX_PROCBASED_CTLS2, 2384 &_cpu_based_2nd_exec_control) < 0) 2385 return -EIO; 2386 } 2387 #ifndef CONFIG_X86_64 2388 if (!(_cpu_based_2nd_exec_control & 2389 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2390 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2391 #endif 2392 2393 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2394 _cpu_based_2nd_exec_control &= ~( 2395 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2396 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2397 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2398 2399 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2400 &vmx_cap->ept, &vmx_cap->vpid); 2401 2402 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2403 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2404 enabled */ 2405 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2406 CPU_BASED_CR3_STORE_EXITING | 2407 CPU_BASED_INVLPG_EXITING); 2408 } else if (vmx_cap->ept) { 2409 vmx_cap->ept = 0; 2410 pr_warn_once("EPT CAP should not exist if not support " 2411 "1-setting enable EPT VM-execution control\n"); 2412 } 2413 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2414 vmx_cap->vpid) { 2415 vmx_cap->vpid = 0; 2416 pr_warn_once("VPID CAP should not exist if not support " 2417 "1-setting enable VPID VM-execution control\n"); 2418 } 2419 2420 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2421 #ifdef CONFIG_X86_64 2422 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2423 #endif 2424 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2425 VM_EXIT_LOAD_IA32_PAT | 2426 VM_EXIT_LOAD_IA32_EFER | 2427 VM_EXIT_CLEAR_BNDCFGS | 2428 VM_EXIT_PT_CONCEAL_PIP | 2429 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2430 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2431 &_vmexit_control) < 0) 2432 return -EIO; 2433 2434 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2435 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2436 PIN_BASED_VMX_PREEMPTION_TIMER; 2437 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2438 &_pin_based_exec_control) < 0) 2439 return -EIO; 2440 2441 if (cpu_has_broken_vmx_preemption_timer()) 2442 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2443 if (!(_cpu_based_2nd_exec_control & 2444 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2445 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2446 2447 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2448 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2449 VM_ENTRY_LOAD_IA32_PAT | 2450 VM_ENTRY_LOAD_IA32_EFER | 2451 VM_ENTRY_LOAD_BNDCFGS | 2452 VM_ENTRY_PT_CONCEAL_PIP | 2453 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2454 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2455 &_vmentry_control) < 0) 2456 return -EIO; 2457 2458 /* 2459 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2460 * can't be used due to an errata where VM Exit may incorrectly clear 2461 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2462 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2463 */ 2464 if (boot_cpu_data.x86 == 0x6) { 2465 switch (boot_cpu_data.x86_model) { 2466 case 26: /* AAK155 */ 2467 case 30: /* AAP115 */ 2468 case 37: /* AAT100 */ 2469 case 44: /* BC86,AAY89,BD102 */ 2470 case 46: /* BA97 */ 2471 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2472 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2473 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2474 "does not work properly. Using workaround\n"); 2475 break; 2476 default: 2477 break; 2478 } 2479 } 2480 2481 2482 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2483 2484 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2485 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2486 return -EIO; 2487 2488 #ifdef CONFIG_X86_64 2489 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2490 if (vmx_msr_high & (1u<<16)) 2491 return -EIO; 2492 #endif 2493 2494 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2495 if (((vmx_msr_high >> 18) & 15) != 6) 2496 return -EIO; 2497 2498 vmcs_conf->size = vmx_msr_high & 0x1fff; 2499 vmcs_conf->order = get_order(vmcs_conf->size); 2500 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2501 2502 vmcs_conf->revision_id = vmx_msr_low; 2503 2504 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2505 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2506 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2507 vmcs_conf->vmexit_ctrl = _vmexit_control; 2508 vmcs_conf->vmentry_ctrl = _vmentry_control; 2509 2510 if (static_branch_unlikely(&enable_evmcs)) 2511 evmcs_sanitize_exec_ctrls(vmcs_conf); 2512 2513 return 0; 2514 } 2515 2516 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2517 { 2518 int node = cpu_to_node(cpu); 2519 struct page *pages; 2520 struct vmcs *vmcs; 2521 2522 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2523 if (!pages) 2524 return NULL; 2525 vmcs = page_address(pages); 2526 memset(vmcs, 0, vmcs_config.size); 2527 2528 /* KVM supports Enlightened VMCS v1 only */ 2529 if (static_branch_unlikely(&enable_evmcs)) 2530 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2531 else 2532 vmcs->hdr.revision_id = vmcs_config.revision_id; 2533 2534 if (shadow) 2535 vmcs->hdr.shadow_vmcs = 1; 2536 return vmcs; 2537 } 2538 2539 void free_vmcs(struct vmcs *vmcs) 2540 { 2541 free_pages((unsigned long)vmcs, vmcs_config.order); 2542 } 2543 2544 /* 2545 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2546 */ 2547 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2548 { 2549 if (!loaded_vmcs->vmcs) 2550 return; 2551 loaded_vmcs_clear(loaded_vmcs); 2552 free_vmcs(loaded_vmcs->vmcs); 2553 loaded_vmcs->vmcs = NULL; 2554 if (loaded_vmcs->msr_bitmap) 2555 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2556 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2557 } 2558 2559 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2560 { 2561 loaded_vmcs->vmcs = alloc_vmcs(false); 2562 if (!loaded_vmcs->vmcs) 2563 return -ENOMEM; 2564 2565 loaded_vmcs->shadow_vmcs = NULL; 2566 loaded_vmcs->hv_timer_soft_disabled = false; 2567 loaded_vmcs_init(loaded_vmcs); 2568 2569 if (cpu_has_vmx_msr_bitmap()) { 2570 loaded_vmcs->msr_bitmap = (unsigned long *) 2571 __get_free_page(GFP_KERNEL_ACCOUNT); 2572 if (!loaded_vmcs->msr_bitmap) 2573 goto out_vmcs; 2574 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2575 2576 if (IS_ENABLED(CONFIG_HYPERV) && 2577 static_branch_unlikely(&enable_evmcs) && 2578 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2579 struct hv_enlightened_vmcs *evmcs = 2580 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2581 2582 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2583 } 2584 } 2585 2586 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2587 memset(&loaded_vmcs->controls_shadow, 0, 2588 sizeof(struct vmcs_controls_shadow)); 2589 2590 return 0; 2591 2592 out_vmcs: 2593 free_loaded_vmcs(loaded_vmcs); 2594 return -ENOMEM; 2595 } 2596 2597 static void free_kvm_area(void) 2598 { 2599 int cpu; 2600 2601 for_each_possible_cpu(cpu) { 2602 free_vmcs(per_cpu(vmxarea, cpu)); 2603 per_cpu(vmxarea, cpu) = NULL; 2604 } 2605 } 2606 2607 static __init int alloc_kvm_area(void) 2608 { 2609 int cpu; 2610 2611 for_each_possible_cpu(cpu) { 2612 struct vmcs *vmcs; 2613 2614 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2615 if (!vmcs) { 2616 free_kvm_area(); 2617 return -ENOMEM; 2618 } 2619 2620 /* 2621 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2622 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2623 * revision_id reported by MSR_IA32_VMX_BASIC. 2624 * 2625 * However, even though not explicitly documented by 2626 * TLFS, VMXArea passed as VMXON argument should 2627 * still be marked with revision_id reported by 2628 * physical CPU. 2629 */ 2630 if (static_branch_unlikely(&enable_evmcs)) 2631 vmcs->hdr.revision_id = vmcs_config.revision_id; 2632 2633 per_cpu(vmxarea, cpu) = vmcs; 2634 } 2635 return 0; 2636 } 2637 2638 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2639 struct kvm_segment *save) 2640 { 2641 if (!emulate_invalid_guest_state) { 2642 /* 2643 * CS and SS RPL should be equal during guest entry according 2644 * to VMX spec, but in reality it is not always so. Since vcpu 2645 * is in the middle of the transition from real mode to 2646 * protected mode it is safe to assume that RPL 0 is a good 2647 * default value. 2648 */ 2649 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2650 save->selector &= ~SEGMENT_RPL_MASK; 2651 save->dpl = save->selector & SEGMENT_RPL_MASK; 2652 save->s = 1; 2653 } 2654 vmx_set_segment(vcpu, save, seg); 2655 } 2656 2657 static void enter_pmode(struct kvm_vcpu *vcpu) 2658 { 2659 unsigned long flags; 2660 struct vcpu_vmx *vmx = to_vmx(vcpu); 2661 2662 /* 2663 * Update real mode segment cache. It may be not up-to-date if sement 2664 * register was written while vcpu was in a guest mode. 2665 */ 2666 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2667 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2668 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2669 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2670 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2671 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2672 2673 vmx->rmode.vm86_active = 0; 2674 2675 vmx_segment_cache_clear(vmx); 2676 2677 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2678 2679 flags = vmcs_readl(GUEST_RFLAGS); 2680 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2681 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2682 vmcs_writel(GUEST_RFLAGS, flags); 2683 2684 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2685 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2686 2687 update_exception_bitmap(vcpu); 2688 2689 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2690 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2691 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2692 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2693 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2694 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2695 } 2696 2697 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2698 { 2699 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2700 struct kvm_segment var = *save; 2701 2702 var.dpl = 0x3; 2703 if (seg == VCPU_SREG_CS) 2704 var.type = 0x3; 2705 2706 if (!emulate_invalid_guest_state) { 2707 var.selector = var.base >> 4; 2708 var.base = var.base & 0xffff0; 2709 var.limit = 0xffff; 2710 var.g = 0; 2711 var.db = 0; 2712 var.present = 1; 2713 var.s = 1; 2714 var.l = 0; 2715 var.unusable = 0; 2716 var.type = 0x3; 2717 var.avl = 0; 2718 if (save->base & 0xf) 2719 printk_once(KERN_WARNING "kvm: segment base is not " 2720 "paragraph aligned when entering " 2721 "protected mode (seg=%d)", seg); 2722 } 2723 2724 vmcs_write16(sf->selector, var.selector); 2725 vmcs_writel(sf->base, var.base); 2726 vmcs_write32(sf->limit, var.limit); 2727 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2728 } 2729 2730 static void enter_rmode(struct kvm_vcpu *vcpu) 2731 { 2732 unsigned long flags; 2733 struct vcpu_vmx *vmx = to_vmx(vcpu); 2734 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2735 2736 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2737 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2738 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2739 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2740 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2741 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2742 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2743 2744 vmx->rmode.vm86_active = 1; 2745 2746 /* 2747 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2748 * vcpu. Warn the user that an update is overdue. 2749 */ 2750 if (!kvm_vmx->tss_addr) 2751 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2752 "called before entering vcpu\n"); 2753 2754 vmx_segment_cache_clear(vmx); 2755 2756 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2757 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2758 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2759 2760 flags = vmcs_readl(GUEST_RFLAGS); 2761 vmx->rmode.save_rflags = flags; 2762 2763 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2764 2765 vmcs_writel(GUEST_RFLAGS, flags); 2766 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2767 update_exception_bitmap(vcpu); 2768 2769 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2770 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2771 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2772 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2773 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2774 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2775 2776 kvm_mmu_reset_context(vcpu); 2777 } 2778 2779 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2780 { 2781 struct vcpu_vmx *vmx = to_vmx(vcpu); 2782 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2783 2784 if (!msr) 2785 return; 2786 2787 vcpu->arch.efer = efer; 2788 if (efer & EFER_LMA) { 2789 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2790 msr->data = efer; 2791 } else { 2792 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2793 2794 msr->data = efer & ~EFER_LME; 2795 } 2796 setup_msrs(vmx); 2797 } 2798 2799 #ifdef CONFIG_X86_64 2800 2801 static void enter_lmode(struct kvm_vcpu *vcpu) 2802 { 2803 u32 guest_tr_ar; 2804 2805 vmx_segment_cache_clear(to_vmx(vcpu)); 2806 2807 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2808 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2809 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2810 __func__); 2811 vmcs_write32(GUEST_TR_AR_BYTES, 2812 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2813 | VMX_AR_TYPE_BUSY_64_TSS); 2814 } 2815 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2816 } 2817 2818 static void exit_lmode(struct kvm_vcpu *vcpu) 2819 { 2820 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2821 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2822 } 2823 2824 #endif 2825 2826 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2827 { 2828 int vpid = to_vmx(vcpu)->vpid; 2829 2830 if (!vpid_sync_vcpu_addr(vpid, addr)) 2831 vpid_sync_context(vpid); 2832 2833 /* 2834 * If VPIDs are not supported or enabled, then the above is a no-op. 2835 * But we don't really need a TLB flush in that case anyway, because 2836 * each VM entry/exit includes an implicit flush when VPID is 0. 2837 */ 2838 } 2839 2840 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2841 { 2842 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2843 2844 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2845 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2846 } 2847 2848 static void vmx_decache_cr3(struct kvm_vcpu *vcpu) 2849 { 2850 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2851 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2852 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 2853 } 2854 2855 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2856 { 2857 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2858 2859 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2860 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2861 } 2862 2863 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2864 { 2865 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2866 2867 if (!test_bit(VCPU_EXREG_PDPTR, 2868 (unsigned long *)&vcpu->arch.regs_dirty)) 2869 return; 2870 2871 if (is_pae_paging(vcpu)) { 2872 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2873 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2874 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2875 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2876 } 2877 } 2878 2879 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2880 { 2881 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2882 2883 if (is_pae_paging(vcpu)) { 2884 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2885 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2886 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2887 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2888 } 2889 2890 __set_bit(VCPU_EXREG_PDPTR, 2891 (unsigned long *)&vcpu->arch.regs_avail); 2892 __set_bit(VCPU_EXREG_PDPTR, 2893 (unsigned long *)&vcpu->arch.regs_dirty); 2894 } 2895 2896 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2897 unsigned long cr0, 2898 struct kvm_vcpu *vcpu) 2899 { 2900 struct vcpu_vmx *vmx = to_vmx(vcpu); 2901 2902 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 2903 vmx_decache_cr3(vcpu); 2904 if (!(cr0 & X86_CR0_PG)) { 2905 /* From paging/starting to nonpaging */ 2906 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2907 CPU_BASED_CR3_STORE_EXITING); 2908 vcpu->arch.cr0 = cr0; 2909 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2910 } else if (!is_paging(vcpu)) { 2911 /* From nonpaging to paging */ 2912 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2913 CPU_BASED_CR3_STORE_EXITING); 2914 vcpu->arch.cr0 = cr0; 2915 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2916 } 2917 2918 if (!(cr0 & X86_CR0_WP)) 2919 *hw_cr0 &= ~X86_CR0_WP; 2920 } 2921 2922 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2923 { 2924 struct vcpu_vmx *vmx = to_vmx(vcpu); 2925 unsigned long hw_cr0; 2926 2927 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2928 if (enable_unrestricted_guest) 2929 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2930 else { 2931 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2932 2933 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2934 enter_pmode(vcpu); 2935 2936 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2937 enter_rmode(vcpu); 2938 } 2939 2940 #ifdef CONFIG_X86_64 2941 if (vcpu->arch.efer & EFER_LME) { 2942 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2943 enter_lmode(vcpu); 2944 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2945 exit_lmode(vcpu); 2946 } 2947 #endif 2948 2949 if (enable_ept && !enable_unrestricted_guest) 2950 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2951 2952 vmcs_writel(CR0_READ_SHADOW, cr0); 2953 vmcs_writel(GUEST_CR0, hw_cr0); 2954 vcpu->arch.cr0 = cr0; 2955 2956 /* depends on vcpu->arch.cr0 to be set to a new value */ 2957 vmx->emulation_required = emulation_required(vcpu); 2958 } 2959 2960 static int get_ept_level(struct kvm_vcpu *vcpu) 2961 { 2962 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2963 return 5; 2964 return 4; 2965 } 2966 2967 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2968 { 2969 u64 eptp = VMX_EPTP_MT_WB; 2970 2971 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2972 2973 if (enable_ept_ad_bits && 2974 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2975 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2976 eptp |= (root_hpa & PAGE_MASK); 2977 2978 return eptp; 2979 } 2980 2981 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 2982 { 2983 struct kvm *kvm = vcpu->kvm; 2984 unsigned long guest_cr3; 2985 u64 eptp; 2986 2987 guest_cr3 = cr3; 2988 if (enable_ept) { 2989 eptp = construct_eptp(vcpu, cr3); 2990 vmcs_write64(EPT_POINTER, eptp); 2991 2992 if (kvm_x86_ops->tlb_remote_flush) { 2993 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2994 to_vmx(vcpu)->ept_pointer = eptp; 2995 to_kvm_vmx(kvm)->ept_pointers_match 2996 = EPT_POINTERS_CHECK; 2997 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2998 } 2999 3000 if (enable_unrestricted_guest || is_paging(vcpu) || 3001 is_guest_mode(vcpu)) 3002 guest_cr3 = kvm_read_cr3(vcpu); 3003 else 3004 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3005 ept_load_pdptrs(vcpu); 3006 } 3007 3008 vmcs_writel(GUEST_CR3, guest_cr3); 3009 } 3010 3011 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3012 { 3013 struct vcpu_vmx *vmx = to_vmx(vcpu); 3014 /* 3015 * Pass through host's Machine Check Enable value to hw_cr4, which 3016 * is in force while we are in guest mode. Do not let guests control 3017 * this bit, even if host CR4.MCE == 0. 3018 */ 3019 unsigned long hw_cr4; 3020 3021 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3022 if (enable_unrestricted_guest) 3023 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3024 else if (vmx->rmode.vm86_active) 3025 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3026 else 3027 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3028 3029 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3030 if (cr4 & X86_CR4_UMIP) { 3031 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3032 hw_cr4 &= ~X86_CR4_UMIP; 3033 } else if (!is_guest_mode(vcpu) || 3034 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3035 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3036 } 3037 } 3038 3039 if (cr4 & X86_CR4_VMXE) { 3040 /* 3041 * To use VMXON (and later other VMX instructions), a guest 3042 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3043 * So basically the check on whether to allow nested VMX 3044 * is here. We operate under the default treatment of SMM, 3045 * so VMX cannot be enabled under SMM. 3046 */ 3047 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3048 return 1; 3049 } 3050 3051 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3052 return 1; 3053 3054 vcpu->arch.cr4 = cr4; 3055 3056 if (!enable_unrestricted_guest) { 3057 if (enable_ept) { 3058 if (!is_paging(vcpu)) { 3059 hw_cr4 &= ~X86_CR4_PAE; 3060 hw_cr4 |= X86_CR4_PSE; 3061 } else if (!(cr4 & X86_CR4_PAE)) { 3062 hw_cr4 &= ~X86_CR4_PAE; 3063 } 3064 } 3065 3066 /* 3067 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3068 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3069 * to be manually disabled when guest switches to non-paging 3070 * mode. 3071 * 3072 * If !enable_unrestricted_guest, the CPU is always running 3073 * with CR0.PG=1 and CR4 needs to be modified. 3074 * If enable_unrestricted_guest, the CPU automatically 3075 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3076 */ 3077 if (!is_paging(vcpu)) 3078 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3079 } 3080 3081 vmcs_writel(CR4_READ_SHADOW, cr4); 3082 vmcs_writel(GUEST_CR4, hw_cr4); 3083 return 0; 3084 } 3085 3086 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3087 { 3088 struct vcpu_vmx *vmx = to_vmx(vcpu); 3089 u32 ar; 3090 3091 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3092 *var = vmx->rmode.segs[seg]; 3093 if (seg == VCPU_SREG_TR 3094 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3095 return; 3096 var->base = vmx_read_guest_seg_base(vmx, seg); 3097 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3098 return; 3099 } 3100 var->base = vmx_read_guest_seg_base(vmx, seg); 3101 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3102 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3103 ar = vmx_read_guest_seg_ar(vmx, seg); 3104 var->unusable = (ar >> 16) & 1; 3105 var->type = ar & 15; 3106 var->s = (ar >> 4) & 1; 3107 var->dpl = (ar >> 5) & 3; 3108 /* 3109 * Some userspaces do not preserve unusable property. Since usable 3110 * segment has to be present according to VMX spec we can use present 3111 * property to amend userspace bug by making unusable segment always 3112 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3113 * segment as unusable. 3114 */ 3115 var->present = !var->unusable; 3116 var->avl = (ar >> 12) & 1; 3117 var->l = (ar >> 13) & 1; 3118 var->db = (ar >> 14) & 1; 3119 var->g = (ar >> 15) & 1; 3120 } 3121 3122 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3123 { 3124 struct kvm_segment s; 3125 3126 if (to_vmx(vcpu)->rmode.vm86_active) { 3127 vmx_get_segment(vcpu, &s, seg); 3128 return s.base; 3129 } 3130 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3131 } 3132 3133 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3134 { 3135 struct vcpu_vmx *vmx = to_vmx(vcpu); 3136 3137 if (unlikely(vmx->rmode.vm86_active)) 3138 return 0; 3139 else { 3140 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3141 return VMX_AR_DPL(ar); 3142 } 3143 } 3144 3145 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3146 { 3147 u32 ar; 3148 3149 if (var->unusable || !var->present) 3150 ar = 1 << 16; 3151 else { 3152 ar = var->type & 15; 3153 ar |= (var->s & 1) << 4; 3154 ar |= (var->dpl & 3) << 5; 3155 ar |= (var->present & 1) << 7; 3156 ar |= (var->avl & 1) << 12; 3157 ar |= (var->l & 1) << 13; 3158 ar |= (var->db & 1) << 14; 3159 ar |= (var->g & 1) << 15; 3160 } 3161 3162 return ar; 3163 } 3164 3165 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3166 { 3167 struct vcpu_vmx *vmx = to_vmx(vcpu); 3168 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3169 3170 vmx_segment_cache_clear(vmx); 3171 3172 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3173 vmx->rmode.segs[seg] = *var; 3174 if (seg == VCPU_SREG_TR) 3175 vmcs_write16(sf->selector, var->selector); 3176 else if (var->s) 3177 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3178 goto out; 3179 } 3180 3181 vmcs_writel(sf->base, var->base); 3182 vmcs_write32(sf->limit, var->limit); 3183 vmcs_write16(sf->selector, var->selector); 3184 3185 /* 3186 * Fix the "Accessed" bit in AR field of segment registers for older 3187 * qemu binaries. 3188 * IA32 arch specifies that at the time of processor reset the 3189 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3190 * is setting it to 0 in the userland code. This causes invalid guest 3191 * state vmexit when "unrestricted guest" mode is turned on. 3192 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3193 * tree. Newer qemu binaries with that qemu fix would not need this 3194 * kvm hack. 3195 */ 3196 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3197 var->type |= 0x1; /* Accessed */ 3198 3199 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3200 3201 out: 3202 vmx->emulation_required = emulation_required(vcpu); 3203 } 3204 3205 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3206 { 3207 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3208 3209 *db = (ar >> 14) & 1; 3210 *l = (ar >> 13) & 1; 3211 } 3212 3213 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3214 { 3215 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3216 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3217 } 3218 3219 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3220 { 3221 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3222 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3223 } 3224 3225 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3226 { 3227 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3228 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3229 } 3230 3231 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3232 { 3233 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3234 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3235 } 3236 3237 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3238 { 3239 struct kvm_segment var; 3240 u32 ar; 3241 3242 vmx_get_segment(vcpu, &var, seg); 3243 var.dpl = 0x3; 3244 if (seg == VCPU_SREG_CS) 3245 var.type = 0x3; 3246 ar = vmx_segment_access_rights(&var); 3247 3248 if (var.base != (var.selector << 4)) 3249 return false; 3250 if (var.limit != 0xffff) 3251 return false; 3252 if (ar != 0xf3) 3253 return false; 3254 3255 return true; 3256 } 3257 3258 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3259 { 3260 struct kvm_segment cs; 3261 unsigned int cs_rpl; 3262 3263 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3264 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3265 3266 if (cs.unusable) 3267 return false; 3268 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3269 return false; 3270 if (!cs.s) 3271 return false; 3272 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3273 if (cs.dpl > cs_rpl) 3274 return false; 3275 } else { 3276 if (cs.dpl != cs_rpl) 3277 return false; 3278 } 3279 if (!cs.present) 3280 return false; 3281 3282 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3283 return true; 3284 } 3285 3286 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3287 { 3288 struct kvm_segment ss; 3289 unsigned int ss_rpl; 3290 3291 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3292 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3293 3294 if (ss.unusable) 3295 return true; 3296 if (ss.type != 3 && ss.type != 7) 3297 return false; 3298 if (!ss.s) 3299 return false; 3300 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3301 return false; 3302 if (!ss.present) 3303 return false; 3304 3305 return true; 3306 } 3307 3308 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3309 { 3310 struct kvm_segment var; 3311 unsigned int rpl; 3312 3313 vmx_get_segment(vcpu, &var, seg); 3314 rpl = var.selector & SEGMENT_RPL_MASK; 3315 3316 if (var.unusable) 3317 return true; 3318 if (!var.s) 3319 return false; 3320 if (!var.present) 3321 return false; 3322 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3323 if (var.dpl < rpl) /* DPL < RPL */ 3324 return false; 3325 } 3326 3327 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3328 * rights flags 3329 */ 3330 return true; 3331 } 3332 3333 static bool tr_valid(struct kvm_vcpu *vcpu) 3334 { 3335 struct kvm_segment tr; 3336 3337 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3338 3339 if (tr.unusable) 3340 return false; 3341 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3342 return false; 3343 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3344 return false; 3345 if (!tr.present) 3346 return false; 3347 3348 return true; 3349 } 3350 3351 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3352 { 3353 struct kvm_segment ldtr; 3354 3355 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3356 3357 if (ldtr.unusable) 3358 return true; 3359 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3360 return false; 3361 if (ldtr.type != 2) 3362 return false; 3363 if (!ldtr.present) 3364 return false; 3365 3366 return true; 3367 } 3368 3369 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3370 { 3371 struct kvm_segment cs, ss; 3372 3373 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3374 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3375 3376 return ((cs.selector & SEGMENT_RPL_MASK) == 3377 (ss.selector & SEGMENT_RPL_MASK)); 3378 } 3379 3380 /* 3381 * Check if guest state is valid. Returns true if valid, false if 3382 * not. 3383 * We assume that registers are always usable 3384 */ 3385 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3386 { 3387 if (enable_unrestricted_guest) 3388 return true; 3389 3390 /* real mode guest state checks */ 3391 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3392 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3393 return false; 3394 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3395 return false; 3396 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3397 return false; 3398 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3399 return false; 3400 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3401 return false; 3402 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3403 return false; 3404 } else { 3405 /* protected mode guest state checks */ 3406 if (!cs_ss_rpl_check(vcpu)) 3407 return false; 3408 if (!code_segment_valid(vcpu)) 3409 return false; 3410 if (!stack_segment_valid(vcpu)) 3411 return false; 3412 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3413 return false; 3414 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3415 return false; 3416 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3417 return false; 3418 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3419 return false; 3420 if (!tr_valid(vcpu)) 3421 return false; 3422 if (!ldtr_valid(vcpu)) 3423 return false; 3424 } 3425 /* TODO: 3426 * - Add checks on RIP 3427 * - Add checks on RFLAGS 3428 */ 3429 3430 return true; 3431 } 3432 3433 static int init_rmode_tss(struct kvm *kvm) 3434 { 3435 gfn_t fn; 3436 u16 data = 0; 3437 int idx, r; 3438 3439 idx = srcu_read_lock(&kvm->srcu); 3440 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3441 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3442 if (r < 0) 3443 goto out; 3444 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3445 r = kvm_write_guest_page(kvm, fn++, &data, 3446 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3447 if (r < 0) 3448 goto out; 3449 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3450 if (r < 0) 3451 goto out; 3452 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3453 if (r < 0) 3454 goto out; 3455 data = ~0; 3456 r = kvm_write_guest_page(kvm, fn, &data, 3457 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3458 sizeof(u8)); 3459 out: 3460 srcu_read_unlock(&kvm->srcu, idx); 3461 return r; 3462 } 3463 3464 static int init_rmode_identity_map(struct kvm *kvm) 3465 { 3466 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3467 int i, idx, r = 0; 3468 kvm_pfn_t identity_map_pfn; 3469 u32 tmp; 3470 3471 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3472 mutex_lock(&kvm->slots_lock); 3473 3474 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3475 goto out2; 3476 3477 if (!kvm_vmx->ept_identity_map_addr) 3478 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3479 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3480 3481 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3482 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3483 if (r < 0) 3484 goto out2; 3485 3486 idx = srcu_read_lock(&kvm->srcu); 3487 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3488 if (r < 0) 3489 goto out; 3490 /* Set up identity-mapping pagetable for EPT in real mode */ 3491 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3492 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3493 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3494 r = kvm_write_guest_page(kvm, identity_map_pfn, 3495 &tmp, i * sizeof(tmp), sizeof(tmp)); 3496 if (r < 0) 3497 goto out; 3498 } 3499 kvm_vmx->ept_identity_pagetable_done = true; 3500 3501 out: 3502 srcu_read_unlock(&kvm->srcu, idx); 3503 3504 out2: 3505 mutex_unlock(&kvm->slots_lock); 3506 return r; 3507 } 3508 3509 static void seg_setup(int seg) 3510 { 3511 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3512 unsigned int ar; 3513 3514 vmcs_write16(sf->selector, 0); 3515 vmcs_writel(sf->base, 0); 3516 vmcs_write32(sf->limit, 0xffff); 3517 ar = 0x93; 3518 if (seg == VCPU_SREG_CS) 3519 ar |= 0x08; /* code segment */ 3520 3521 vmcs_write32(sf->ar_bytes, ar); 3522 } 3523 3524 static int alloc_apic_access_page(struct kvm *kvm) 3525 { 3526 struct page *page; 3527 int r = 0; 3528 3529 mutex_lock(&kvm->slots_lock); 3530 if (kvm->arch.apic_access_page_done) 3531 goto out; 3532 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3533 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3534 if (r) 3535 goto out; 3536 3537 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3538 if (is_error_page(page)) { 3539 r = -EFAULT; 3540 goto out; 3541 } 3542 3543 /* 3544 * Do not pin the page in memory, so that memory hot-unplug 3545 * is able to migrate it. 3546 */ 3547 put_page(page); 3548 kvm->arch.apic_access_page_done = true; 3549 out: 3550 mutex_unlock(&kvm->slots_lock); 3551 return r; 3552 } 3553 3554 int allocate_vpid(void) 3555 { 3556 int vpid; 3557 3558 if (!enable_vpid) 3559 return 0; 3560 spin_lock(&vmx_vpid_lock); 3561 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3562 if (vpid < VMX_NR_VPIDS) 3563 __set_bit(vpid, vmx_vpid_bitmap); 3564 else 3565 vpid = 0; 3566 spin_unlock(&vmx_vpid_lock); 3567 return vpid; 3568 } 3569 3570 void free_vpid(int vpid) 3571 { 3572 if (!enable_vpid || vpid == 0) 3573 return; 3574 spin_lock(&vmx_vpid_lock); 3575 __clear_bit(vpid, vmx_vpid_bitmap); 3576 spin_unlock(&vmx_vpid_lock); 3577 } 3578 3579 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3580 u32 msr, int type) 3581 { 3582 int f = sizeof(unsigned long); 3583 3584 if (!cpu_has_vmx_msr_bitmap()) 3585 return; 3586 3587 if (static_branch_unlikely(&enable_evmcs)) 3588 evmcs_touch_msr_bitmap(); 3589 3590 /* 3591 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3592 * have the write-low and read-high bitmap offsets the wrong way round. 3593 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3594 */ 3595 if (msr <= 0x1fff) { 3596 if (type & MSR_TYPE_R) 3597 /* read-low */ 3598 __clear_bit(msr, msr_bitmap + 0x000 / f); 3599 3600 if (type & MSR_TYPE_W) 3601 /* write-low */ 3602 __clear_bit(msr, msr_bitmap + 0x800 / f); 3603 3604 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3605 msr &= 0x1fff; 3606 if (type & MSR_TYPE_R) 3607 /* read-high */ 3608 __clear_bit(msr, msr_bitmap + 0x400 / f); 3609 3610 if (type & MSR_TYPE_W) 3611 /* write-high */ 3612 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3613 3614 } 3615 } 3616 3617 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3618 u32 msr, int type) 3619 { 3620 int f = sizeof(unsigned long); 3621 3622 if (!cpu_has_vmx_msr_bitmap()) 3623 return; 3624 3625 if (static_branch_unlikely(&enable_evmcs)) 3626 evmcs_touch_msr_bitmap(); 3627 3628 /* 3629 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3630 * have the write-low and read-high bitmap offsets the wrong way round. 3631 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3632 */ 3633 if (msr <= 0x1fff) { 3634 if (type & MSR_TYPE_R) 3635 /* read-low */ 3636 __set_bit(msr, msr_bitmap + 0x000 / f); 3637 3638 if (type & MSR_TYPE_W) 3639 /* write-low */ 3640 __set_bit(msr, msr_bitmap + 0x800 / f); 3641 3642 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3643 msr &= 0x1fff; 3644 if (type & MSR_TYPE_R) 3645 /* read-high */ 3646 __set_bit(msr, msr_bitmap + 0x400 / f); 3647 3648 if (type & MSR_TYPE_W) 3649 /* write-high */ 3650 __set_bit(msr, msr_bitmap + 0xc00 / f); 3651 3652 } 3653 } 3654 3655 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3656 u32 msr, int type, bool value) 3657 { 3658 if (value) 3659 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3660 else 3661 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3662 } 3663 3664 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3665 { 3666 u8 mode = 0; 3667 3668 if (cpu_has_secondary_exec_ctrls() && 3669 (secondary_exec_controls_get(to_vmx(vcpu)) & 3670 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3671 mode |= MSR_BITMAP_MODE_X2APIC; 3672 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3673 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3674 } 3675 3676 return mode; 3677 } 3678 3679 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3680 u8 mode) 3681 { 3682 int msr; 3683 3684 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3685 unsigned word = msr / BITS_PER_LONG; 3686 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3687 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3688 } 3689 3690 if (mode & MSR_BITMAP_MODE_X2APIC) { 3691 /* 3692 * TPR reads and writes can be virtualized even if virtual interrupt 3693 * delivery is not in use. 3694 */ 3695 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3696 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3697 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3698 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3699 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3700 } 3701 } 3702 } 3703 3704 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3705 { 3706 struct vcpu_vmx *vmx = to_vmx(vcpu); 3707 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3708 u8 mode = vmx_msr_bitmap_mode(vcpu); 3709 u8 changed = mode ^ vmx->msr_bitmap_mode; 3710 3711 if (!changed) 3712 return; 3713 3714 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3715 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3716 3717 vmx->msr_bitmap_mode = mode; 3718 } 3719 3720 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3721 { 3722 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3723 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3724 u32 i; 3725 3726 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3727 MSR_TYPE_RW, flag); 3728 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3729 MSR_TYPE_RW, flag); 3730 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3731 MSR_TYPE_RW, flag); 3732 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3733 MSR_TYPE_RW, flag); 3734 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3735 vmx_set_intercept_for_msr(msr_bitmap, 3736 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3737 vmx_set_intercept_for_msr(msr_bitmap, 3738 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3739 } 3740 } 3741 3742 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) 3743 { 3744 return enable_apicv; 3745 } 3746 3747 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3748 { 3749 struct vcpu_vmx *vmx = to_vmx(vcpu); 3750 void *vapic_page; 3751 u32 vppr; 3752 int rvi; 3753 3754 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3755 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3756 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3757 return false; 3758 3759 rvi = vmx_get_rvi(); 3760 3761 vapic_page = vmx->nested.virtual_apic_map.hva; 3762 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3763 3764 return ((rvi & 0xf0) > (vppr & 0xf0)); 3765 } 3766 3767 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3768 bool nested) 3769 { 3770 #ifdef CONFIG_SMP 3771 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3772 3773 if (vcpu->mode == IN_GUEST_MODE) { 3774 /* 3775 * The vector of interrupt to be delivered to vcpu had 3776 * been set in PIR before this function. 3777 * 3778 * Following cases will be reached in this block, and 3779 * we always send a notification event in all cases as 3780 * explained below. 3781 * 3782 * Case 1: vcpu keeps in non-root mode. Sending a 3783 * notification event posts the interrupt to vcpu. 3784 * 3785 * Case 2: vcpu exits to root mode and is still 3786 * runnable. PIR will be synced to vIRR before the 3787 * next vcpu entry. Sending a notification event in 3788 * this case has no effect, as vcpu is not in root 3789 * mode. 3790 * 3791 * Case 3: vcpu exits to root mode and is blocked. 3792 * vcpu_block() has already synced PIR to vIRR and 3793 * never blocks vcpu if vIRR is not cleared. Therefore, 3794 * a blocked vcpu here does not wait for any requested 3795 * interrupts in PIR, and sending a notification event 3796 * which has no effect is safe here. 3797 */ 3798 3799 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3800 return true; 3801 } 3802 #endif 3803 return false; 3804 } 3805 3806 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3807 int vector) 3808 { 3809 struct vcpu_vmx *vmx = to_vmx(vcpu); 3810 3811 if (is_guest_mode(vcpu) && 3812 vector == vmx->nested.posted_intr_nv) { 3813 /* 3814 * If a posted intr is not recognized by hardware, 3815 * we will accomplish it in the next vmentry. 3816 */ 3817 vmx->nested.pi_pending = true; 3818 kvm_make_request(KVM_REQ_EVENT, vcpu); 3819 /* the PIR and ON have been set by L1. */ 3820 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3821 kvm_vcpu_kick(vcpu); 3822 return 0; 3823 } 3824 return -1; 3825 } 3826 /* 3827 * Send interrupt to vcpu via posted interrupt way. 3828 * 1. If target vcpu is running(non-root mode), send posted interrupt 3829 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3830 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3831 * interrupt from PIR in next vmentry. 3832 */ 3833 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3834 { 3835 struct vcpu_vmx *vmx = to_vmx(vcpu); 3836 int r; 3837 3838 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3839 if (!r) 3840 return; 3841 3842 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3843 return; 3844 3845 /* If a previous notification has sent the IPI, nothing to do. */ 3846 if (pi_test_and_set_on(&vmx->pi_desc)) 3847 return; 3848 3849 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3850 kvm_vcpu_kick(vcpu); 3851 } 3852 3853 /* 3854 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3855 * will not change in the lifetime of the guest. 3856 * Note that host-state that does change is set elsewhere. E.g., host-state 3857 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3858 */ 3859 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3860 { 3861 u32 low32, high32; 3862 unsigned long tmpl; 3863 unsigned long cr0, cr3, cr4; 3864 3865 cr0 = read_cr0(); 3866 WARN_ON(cr0 & X86_CR0_TS); 3867 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3868 3869 /* 3870 * Save the most likely value for this task's CR3 in the VMCS. 3871 * We can't use __get_current_cr3_fast() because we're not atomic. 3872 */ 3873 cr3 = __read_cr3(); 3874 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3875 vmx->loaded_vmcs->host_state.cr3 = cr3; 3876 3877 /* Save the most likely value for this task's CR4 in the VMCS. */ 3878 cr4 = cr4_read_shadow(); 3879 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3880 vmx->loaded_vmcs->host_state.cr4 = cr4; 3881 3882 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3883 #ifdef CONFIG_X86_64 3884 /* 3885 * Load null selectors, so we can avoid reloading them in 3886 * vmx_prepare_switch_to_host(), in case userspace uses 3887 * the null selectors too (the expected case). 3888 */ 3889 vmcs_write16(HOST_DS_SELECTOR, 0); 3890 vmcs_write16(HOST_ES_SELECTOR, 0); 3891 #else 3892 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3893 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3894 #endif 3895 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3896 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3897 3898 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3899 3900 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3901 3902 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3903 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3904 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3905 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3906 3907 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3908 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3909 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3910 } 3911 3912 if (cpu_has_load_ia32_efer()) 3913 vmcs_write64(HOST_IA32_EFER, host_efer); 3914 } 3915 3916 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3917 { 3918 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3919 if (enable_ept) 3920 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3921 if (is_guest_mode(&vmx->vcpu)) 3922 vmx->vcpu.arch.cr4_guest_owned_bits &= 3923 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3924 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3925 } 3926 3927 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3928 { 3929 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3930 3931 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3932 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3933 3934 if (!enable_vnmi) 3935 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3936 3937 if (!enable_preemption_timer) 3938 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3939 3940 return pin_based_exec_ctrl; 3941 } 3942 3943 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3944 { 3945 struct vcpu_vmx *vmx = to_vmx(vcpu); 3946 3947 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3948 if (cpu_has_secondary_exec_ctrls()) { 3949 if (kvm_vcpu_apicv_active(vcpu)) 3950 secondary_exec_controls_setbit(vmx, 3951 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3952 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3953 else 3954 secondary_exec_controls_clearbit(vmx, 3955 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3956 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3957 } 3958 3959 if (cpu_has_vmx_msr_bitmap()) 3960 vmx_update_msr_bitmap(vcpu); 3961 } 3962 3963 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3964 { 3965 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3966 3967 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3968 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3969 3970 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3971 exec_control &= ~CPU_BASED_TPR_SHADOW; 3972 #ifdef CONFIG_X86_64 3973 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3974 CPU_BASED_CR8_LOAD_EXITING; 3975 #endif 3976 } 3977 if (!enable_ept) 3978 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3979 CPU_BASED_CR3_LOAD_EXITING | 3980 CPU_BASED_INVLPG_EXITING; 3981 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3982 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3983 CPU_BASED_MONITOR_EXITING); 3984 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3985 exec_control &= ~CPU_BASED_HLT_EXITING; 3986 return exec_control; 3987 } 3988 3989 3990 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 3991 { 3992 struct kvm_vcpu *vcpu = &vmx->vcpu; 3993 3994 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 3995 3996 if (pt_mode == PT_MODE_SYSTEM) 3997 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 3998 if (!cpu_need_virtualize_apic_accesses(vcpu)) 3999 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4000 if (vmx->vpid == 0) 4001 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4002 if (!enable_ept) { 4003 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4004 enable_unrestricted_guest = 0; 4005 } 4006 if (!enable_unrestricted_guest) 4007 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4008 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4009 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4010 if (!kvm_vcpu_apicv_active(vcpu)) 4011 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4012 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4013 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4014 4015 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4016 * in vmx_set_cr4. */ 4017 exec_control &= ~SECONDARY_EXEC_DESC; 4018 4019 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4020 (handle_vmptrld). 4021 We can NOT enable shadow_vmcs here because we don't have yet 4022 a current VMCS12 4023 */ 4024 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4025 4026 if (!enable_pml) 4027 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4028 4029 if (vmx_xsaves_supported()) { 4030 /* Exposing XSAVES only when XSAVE is exposed */ 4031 bool xsaves_enabled = 4032 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4033 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4034 4035 if (!xsaves_enabled) 4036 exec_control &= ~SECONDARY_EXEC_XSAVES; 4037 4038 if (nested) { 4039 if (xsaves_enabled) 4040 vmx->nested.msrs.secondary_ctls_high |= 4041 SECONDARY_EXEC_XSAVES; 4042 else 4043 vmx->nested.msrs.secondary_ctls_high &= 4044 ~SECONDARY_EXEC_XSAVES; 4045 } 4046 } 4047 4048 if (vmx_rdtscp_supported()) { 4049 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4050 if (!rdtscp_enabled) 4051 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4052 4053 if (nested) { 4054 if (rdtscp_enabled) 4055 vmx->nested.msrs.secondary_ctls_high |= 4056 SECONDARY_EXEC_RDTSCP; 4057 else 4058 vmx->nested.msrs.secondary_ctls_high &= 4059 ~SECONDARY_EXEC_RDTSCP; 4060 } 4061 } 4062 4063 if (vmx_invpcid_supported()) { 4064 /* Exposing INVPCID only when PCID is exposed */ 4065 bool invpcid_enabled = 4066 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4067 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4068 4069 if (!invpcid_enabled) { 4070 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4071 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4072 } 4073 4074 if (nested) { 4075 if (invpcid_enabled) 4076 vmx->nested.msrs.secondary_ctls_high |= 4077 SECONDARY_EXEC_ENABLE_INVPCID; 4078 else 4079 vmx->nested.msrs.secondary_ctls_high &= 4080 ~SECONDARY_EXEC_ENABLE_INVPCID; 4081 } 4082 } 4083 4084 if (vmx_rdrand_supported()) { 4085 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4086 if (rdrand_enabled) 4087 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4088 4089 if (nested) { 4090 if (rdrand_enabled) 4091 vmx->nested.msrs.secondary_ctls_high |= 4092 SECONDARY_EXEC_RDRAND_EXITING; 4093 else 4094 vmx->nested.msrs.secondary_ctls_high &= 4095 ~SECONDARY_EXEC_RDRAND_EXITING; 4096 } 4097 } 4098 4099 if (vmx_rdseed_supported()) { 4100 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4101 if (rdseed_enabled) 4102 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4103 4104 if (nested) { 4105 if (rdseed_enabled) 4106 vmx->nested.msrs.secondary_ctls_high |= 4107 SECONDARY_EXEC_RDSEED_EXITING; 4108 else 4109 vmx->nested.msrs.secondary_ctls_high &= 4110 ~SECONDARY_EXEC_RDSEED_EXITING; 4111 } 4112 } 4113 4114 if (vmx_waitpkg_supported()) { 4115 bool waitpkg_enabled = 4116 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4117 4118 if (!waitpkg_enabled) 4119 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4120 4121 if (nested) { 4122 if (waitpkg_enabled) 4123 vmx->nested.msrs.secondary_ctls_high |= 4124 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4125 else 4126 vmx->nested.msrs.secondary_ctls_high &= 4127 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4128 } 4129 } 4130 4131 vmx->secondary_exec_control = exec_control; 4132 } 4133 4134 static void ept_set_mmio_spte_mask(void) 4135 { 4136 /* 4137 * EPT Misconfigurations can be generated if the value of bits 2:0 4138 * of an EPT paging-structure entry is 110b (write/execute). 4139 */ 4140 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4141 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4142 } 4143 4144 #define VMX_XSS_EXIT_BITMAP 0 4145 4146 /* 4147 * Sets up the vmcs for emulated real mode. 4148 */ 4149 static void vmx_vcpu_setup(struct vcpu_vmx *vmx) 4150 { 4151 int i; 4152 4153 if (nested) 4154 nested_vmx_vcpu_setup(); 4155 4156 if (cpu_has_vmx_msr_bitmap()) 4157 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4158 4159 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4160 4161 /* Control */ 4162 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4163 vmx->hv_deadline_tsc = -1; 4164 4165 exec_controls_set(vmx, vmx_exec_control(vmx)); 4166 4167 if (cpu_has_secondary_exec_ctrls()) { 4168 vmx_compute_secondary_exec_control(vmx); 4169 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4170 } 4171 4172 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4173 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4174 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4175 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4176 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4177 4178 vmcs_write16(GUEST_INTR_STATUS, 0); 4179 4180 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4181 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4182 } 4183 4184 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4185 vmcs_write32(PLE_GAP, ple_gap); 4186 vmx->ple_window = ple_window; 4187 vmx->ple_window_dirty = true; 4188 } 4189 4190 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4191 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4192 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4193 4194 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4195 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4196 vmx_set_constant_host_state(vmx); 4197 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4198 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4199 4200 if (cpu_has_vmx_vmfunc()) 4201 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4202 4203 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4204 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4205 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4206 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4207 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4208 4209 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4210 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4211 4212 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 4213 u32 index = vmx_msr_index[i]; 4214 u32 data_low, data_high; 4215 int j = vmx->nmsrs; 4216 4217 if (rdmsr_safe(index, &data_low, &data_high) < 0) 4218 continue; 4219 if (wrmsr_safe(index, data_low, data_high) < 0) 4220 continue; 4221 vmx->guest_msrs[j].index = i; 4222 vmx->guest_msrs[j].data = 0; 4223 vmx->guest_msrs[j].mask = -1ull; 4224 ++vmx->nmsrs; 4225 } 4226 4227 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4228 4229 /* 22.2.1, 20.8.1 */ 4230 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4231 4232 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4233 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4234 4235 set_cr4_guest_host_mask(vmx); 4236 4237 if (vmx_xsaves_supported()) 4238 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4239 4240 if (enable_pml) { 4241 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4242 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4243 } 4244 4245 if (cpu_has_vmx_encls_vmexit()) 4246 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4247 4248 if (pt_mode == PT_MODE_HOST_GUEST) { 4249 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4250 /* Bit[6~0] are forced to 1, writes are ignored. */ 4251 vmx->pt_desc.guest.output_mask = 0x7F; 4252 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4253 } 4254 } 4255 4256 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4257 { 4258 struct vcpu_vmx *vmx = to_vmx(vcpu); 4259 struct msr_data apic_base_msr; 4260 u64 cr0; 4261 4262 vmx->rmode.vm86_active = 0; 4263 vmx->spec_ctrl = 0; 4264 4265 vmx->msr_ia32_umwait_control = 0; 4266 4267 vcpu->arch.microcode_version = 0x100000000ULL; 4268 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4269 vmx->hv_deadline_tsc = -1; 4270 kvm_set_cr8(vcpu, 0); 4271 4272 if (!init_event) { 4273 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4274 MSR_IA32_APICBASE_ENABLE; 4275 if (kvm_vcpu_is_reset_bsp(vcpu)) 4276 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4277 apic_base_msr.host_initiated = true; 4278 kvm_set_apic_base(vcpu, &apic_base_msr); 4279 } 4280 4281 vmx_segment_cache_clear(vmx); 4282 4283 seg_setup(VCPU_SREG_CS); 4284 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4285 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4286 4287 seg_setup(VCPU_SREG_DS); 4288 seg_setup(VCPU_SREG_ES); 4289 seg_setup(VCPU_SREG_FS); 4290 seg_setup(VCPU_SREG_GS); 4291 seg_setup(VCPU_SREG_SS); 4292 4293 vmcs_write16(GUEST_TR_SELECTOR, 0); 4294 vmcs_writel(GUEST_TR_BASE, 0); 4295 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4296 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4297 4298 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4299 vmcs_writel(GUEST_LDTR_BASE, 0); 4300 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4301 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4302 4303 if (!init_event) { 4304 vmcs_write32(GUEST_SYSENTER_CS, 0); 4305 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4306 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4307 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4308 } 4309 4310 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4311 kvm_rip_write(vcpu, 0xfff0); 4312 4313 vmcs_writel(GUEST_GDTR_BASE, 0); 4314 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4315 4316 vmcs_writel(GUEST_IDTR_BASE, 0); 4317 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4318 4319 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4320 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4321 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4322 if (kvm_mpx_supported()) 4323 vmcs_write64(GUEST_BNDCFGS, 0); 4324 4325 setup_msrs(vmx); 4326 4327 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4328 4329 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4330 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4331 if (cpu_need_tpr_shadow(vcpu)) 4332 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4333 __pa(vcpu->arch.apic->regs)); 4334 vmcs_write32(TPR_THRESHOLD, 0); 4335 } 4336 4337 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4338 4339 if (vmx->vpid != 0) 4340 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4341 4342 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4343 vmx->vcpu.arch.cr0 = cr0; 4344 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4345 vmx_set_cr4(vcpu, 0); 4346 vmx_set_efer(vcpu, 0); 4347 4348 update_exception_bitmap(vcpu); 4349 4350 vpid_sync_context(vmx->vpid); 4351 if (init_event) 4352 vmx_clear_hlt(vcpu); 4353 } 4354 4355 static void enable_irq_window(struct kvm_vcpu *vcpu) 4356 { 4357 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING); 4358 } 4359 4360 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4361 { 4362 if (!enable_vnmi || 4363 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4364 enable_irq_window(vcpu); 4365 return; 4366 } 4367 4368 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING); 4369 } 4370 4371 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4372 { 4373 struct vcpu_vmx *vmx = to_vmx(vcpu); 4374 uint32_t intr; 4375 int irq = vcpu->arch.interrupt.nr; 4376 4377 trace_kvm_inj_virq(irq); 4378 4379 ++vcpu->stat.irq_injections; 4380 if (vmx->rmode.vm86_active) { 4381 int inc_eip = 0; 4382 if (vcpu->arch.interrupt.soft) 4383 inc_eip = vcpu->arch.event_exit_inst_len; 4384 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4385 return; 4386 } 4387 intr = irq | INTR_INFO_VALID_MASK; 4388 if (vcpu->arch.interrupt.soft) { 4389 intr |= INTR_TYPE_SOFT_INTR; 4390 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4391 vmx->vcpu.arch.event_exit_inst_len); 4392 } else 4393 intr |= INTR_TYPE_EXT_INTR; 4394 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4395 4396 vmx_clear_hlt(vcpu); 4397 } 4398 4399 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4400 { 4401 struct vcpu_vmx *vmx = to_vmx(vcpu); 4402 4403 if (!enable_vnmi) { 4404 /* 4405 * Tracking the NMI-blocked state in software is built upon 4406 * finding the next open IRQ window. This, in turn, depends on 4407 * well-behaving guests: They have to keep IRQs disabled at 4408 * least as long as the NMI handler runs. Otherwise we may 4409 * cause NMI nesting, maybe breaking the guest. But as this is 4410 * highly unlikely, we can live with the residual risk. 4411 */ 4412 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4413 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4414 } 4415 4416 ++vcpu->stat.nmi_injections; 4417 vmx->loaded_vmcs->nmi_known_unmasked = false; 4418 4419 if (vmx->rmode.vm86_active) { 4420 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4421 return; 4422 } 4423 4424 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4425 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4426 4427 vmx_clear_hlt(vcpu); 4428 } 4429 4430 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4431 { 4432 struct vcpu_vmx *vmx = to_vmx(vcpu); 4433 bool masked; 4434 4435 if (!enable_vnmi) 4436 return vmx->loaded_vmcs->soft_vnmi_blocked; 4437 if (vmx->loaded_vmcs->nmi_known_unmasked) 4438 return false; 4439 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4440 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4441 return masked; 4442 } 4443 4444 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4445 { 4446 struct vcpu_vmx *vmx = to_vmx(vcpu); 4447 4448 if (!enable_vnmi) { 4449 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4450 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4451 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4452 } 4453 } else { 4454 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4455 if (masked) 4456 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4457 GUEST_INTR_STATE_NMI); 4458 else 4459 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4460 GUEST_INTR_STATE_NMI); 4461 } 4462 } 4463 4464 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4465 { 4466 if (to_vmx(vcpu)->nested.nested_run_pending) 4467 return 0; 4468 4469 if (!enable_vnmi && 4470 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4471 return 0; 4472 4473 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4474 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4475 | GUEST_INTR_STATE_NMI)); 4476 } 4477 4478 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4479 { 4480 return (!to_vmx(vcpu)->nested.nested_run_pending && 4481 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4482 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4483 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4484 } 4485 4486 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4487 { 4488 int ret; 4489 4490 if (enable_unrestricted_guest) 4491 return 0; 4492 4493 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4494 PAGE_SIZE * 3); 4495 if (ret) 4496 return ret; 4497 to_kvm_vmx(kvm)->tss_addr = addr; 4498 return init_rmode_tss(kvm); 4499 } 4500 4501 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4502 { 4503 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4504 return 0; 4505 } 4506 4507 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4508 { 4509 switch (vec) { 4510 case BP_VECTOR: 4511 /* 4512 * Update instruction length as we may reinject the exception 4513 * from user space while in guest debugging mode. 4514 */ 4515 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4516 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4517 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4518 return false; 4519 /* fall through */ 4520 case DB_VECTOR: 4521 if (vcpu->guest_debug & 4522 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4523 return false; 4524 /* fall through */ 4525 case DE_VECTOR: 4526 case OF_VECTOR: 4527 case BR_VECTOR: 4528 case UD_VECTOR: 4529 case DF_VECTOR: 4530 case SS_VECTOR: 4531 case GP_VECTOR: 4532 case MF_VECTOR: 4533 return true; 4534 break; 4535 } 4536 return false; 4537 } 4538 4539 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4540 int vec, u32 err_code) 4541 { 4542 /* 4543 * Instruction with address size override prefix opcode 0x67 4544 * Cause the #SS fault with 0 error code in VM86 mode. 4545 */ 4546 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4547 if (kvm_emulate_instruction(vcpu, 0)) { 4548 if (vcpu->arch.halt_request) { 4549 vcpu->arch.halt_request = 0; 4550 return kvm_vcpu_halt(vcpu); 4551 } 4552 return 1; 4553 } 4554 return 0; 4555 } 4556 4557 /* 4558 * Forward all other exceptions that are valid in real mode. 4559 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4560 * the required debugging infrastructure rework. 4561 */ 4562 kvm_queue_exception(vcpu, vec); 4563 return 1; 4564 } 4565 4566 /* 4567 * Trigger machine check on the host. We assume all the MSRs are already set up 4568 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4569 * We pass a fake environment to the machine check handler because we want 4570 * the guest to be always treated like user space, no matter what context 4571 * it used internally. 4572 */ 4573 static void kvm_machine_check(void) 4574 { 4575 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4576 struct pt_regs regs = { 4577 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4578 .flags = X86_EFLAGS_IF, 4579 }; 4580 4581 do_machine_check(®s, 0); 4582 #endif 4583 } 4584 4585 static int handle_machine_check(struct kvm_vcpu *vcpu) 4586 { 4587 /* handled by vmx_vcpu_run() */ 4588 return 1; 4589 } 4590 4591 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4592 { 4593 struct vcpu_vmx *vmx = to_vmx(vcpu); 4594 struct kvm_run *kvm_run = vcpu->run; 4595 u32 intr_info, ex_no, error_code; 4596 unsigned long cr2, rip, dr6; 4597 u32 vect_info; 4598 4599 vect_info = vmx->idt_vectoring_info; 4600 intr_info = vmx->exit_intr_info; 4601 4602 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4603 return 1; /* handled by handle_exception_nmi_irqoff() */ 4604 4605 if (is_invalid_opcode(intr_info)) 4606 return handle_ud(vcpu); 4607 4608 error_code = 0; 4609 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4610 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4611 4612 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4613 WARN_ON_ONCE(!enable_vmware_backdoor); 4614 4615 /* 4616 * VMware backdoor emulation on #GP interception only handles 4617 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4618 * error code on #GP. 4619 */ 4620 if (error_code) { 4621 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4622 return 1; 4623 } 4624 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4625 } 4626 4627 /* 4628 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4629 * MMIO, it is better to report an internal error. 4630 * See the comments in vmx_handle_exit. 4631 */ 4632 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4633 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4634 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4635 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4636 vcpu->run->internal.ndata = 3; 4637 vcpu->run->internal.data[0] = vect_info; 4638 vcpu->run->internal.data[1] = intr_info; 4639 vcpu->run->internal.data[2] = error_code; 4640 return 0; 4641 } 4642 4643 if (is_page_fault(intr_info)) { 4644 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4645 /* EPT won't cause page fault directly */ 4646 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4647 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4648 } 4649 4650 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4651 4652 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4653 return handle_rmode_exception(vcpu, ex_no, error_code); 4654 4655 switch (ex_no) { 4656 case AC_VECTOR: 4657 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4658 return 1; 4659 case DB_VECTOR: 4660 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4661 if (!(vcpu->guest_debug & 4662 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4663 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4664 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4665 if (is_icebp(intr_info)) 4666 WARN_ON(!skip_emulated_instruction(vcpu)); 4667 4668 kvm_queue_exception(vcpu, DB_VECTOR); 4669 return 1; 4670 } 4671 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4672 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4673 /* fall through */ 4674 case BP_VECTOR: 4675 /* 4676 * Update instruction length as we may reinject #BP from 4677 * user space while in guest debugging mode. Reading it for 4678 * #DB as well causes no harm, it is not used in that case. 4679 */ 4680 vmx->vcpu.arch.event_exit_inst_len = 4681 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4682 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4683 rip = kvm_rip_read(vcpu); 4684 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4685 kvm_run->debug.arch.exception = ex_no; 4686 break; 4687 default: 4688 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4689 kvm_run->ex.exception = ex_no; 4690 kvm_run->ex.error_code = error_code; 4691 break; 4692 } 4693 return 0; 4694 } 4695 4696 static int handle_external_interrupt(struct kvm_vcpu *vcpu) 4697 { 4698 ++vcpu->stat.irq_exits; 4699 return 1; 4700 } 4701 4702 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4703 { 4704 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4705 vcpu->mmio_needed = 0; 4706 return 0; 4707 } 4708 4709 static int handle_io(struct kvm_vcpu *vcpu) 4710 { 4711 unsigned long exit_qualification; 4712 int size, in, string; 4713 unsigned port; 4714 4715 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4716 string = (exit_qualification & 16) != 0; 4717 4718 ++vcpu->stat.io_exits; 4719 4720 if (string) 4721 return kvm_emulate_instruction(vcpu, 0); 4722 4723 port = exit_qualification >> 16; 4724 size = (exit_qualification & 7) + 1; 4725 in = (exit_qualification & 8) != 0; 4726 4727 return kvm_fast_pio(vcpu, size, port, in); 4728 } 4729 4730 static void 4731 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4732 { 4733 /* 4734 * Patch in the VMCALL instruction: 4735 */ 4736 hypercall[0] = 0x0f; 4737 hypercall[1] = 0x01; 4738 hypercall[2] = 0xc1; 4739 } 4740 4741 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4742 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4743 { 4744 if (is_guest_mode(vcpu)) { 4745 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4746 unsigned long orig_val = val; 4747 4748 /* 4749 * We get here when L2 changed cr0 in a way that did not change 4750 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4751 * but did change L0 shadowed bits. So we first calculate the 4752 * effective cr0 value that L1 would like to write into the 4753 * hardware. It consists of the L2-owned bits from the new 4754 * value combined with the L1-owned bits from L1's guest_cr0. 4755 */ 4756 val = (val & ~vmcs12->cr0_guest_host_mask) | 4757 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4758 4759 if (!nested_guest_cr0_valid(vcpu, val)) 4760 return 1; 4761 4762 if (kvm_set_cr0(vcpu, val)) 4763 return 1; 4764 vmcs_writel(CR0_READ_SHADOW, orig_val); 4765 return 0; 4766 } else { 4767 if (to_vmx(vcpu)->nested.vmxon && 4768 !nested_host_cr0_valid(vcpu, val)) 4769 return 1; 4770 4771 return kvm_set_cr0(vcpu, val); 4772 } 4773 } 4774 4775 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4776 { 4777 if (is_guest_mode(vcpu)) { 4778 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4779 unsigned long orig_val = val; 4780 4781 /* analogously to handle_set_cr0 */ 4782 val = (val & ~vmcs12->cr4_guest_host_mask) | 4783 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4784 if (kvm_set_cr4(vcpu, val)) 4785 return 1; 4786 vmcs_writel(CR4_READ_SHADOW, orig_val); 4787 return 0; 4788 } else 4789 return kvm_set_cr4(vcpu, val); 4790 } 4791 4792 static int handle_desc(struct kvm_vcpu *vcpu) 4793 { 4794 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4795 return kvm_emulate_instruction(vcpu, 0); 4796 } 4797 4798 static int handle_cr(struct kvm_vcpu *vcpu) 4799 { 4800 unsigned long exit_qualification, val; 4801 int cr; 4802 int reg; 4803 int err; 4804 int ret; 4805 4806 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4807 cr = exit_qualification & 15; 4808 reg = (exit_qualification >> 8) & 15; 4809 switch ((exit_qualification >> 4) & 3) { 4810 case 0: /* mov to cr */ 4811 val = kvm_register_readl(vcpu, reg); 4812 trace_kvm_cr_write(cr, val); 4813 switch (cr) { 4814 case 0: 4815 err = handle_set_cr0(vcpu, val); 4816 return kvm_complete_insn_gp(vcpu, err); 4817 case 3: 4818 WARN_ON_ONCE(enable_unrestricted_guest); 4819 err = kvm_set_cr3(vcpu, val); 4820 return kvm_complete_insn_gp(vcpu, err); 4821 case 4: 4822 err = handle_set_cr4(vcpu, val); 4823 return kvm_complete_insn_gp(vcpu, err); 4824 case 8: { 4825 u8 cr8_prev = kvm_get_cr8(vcpu); 4826 u8 cr8 = (u8)val; 4827 err = kvm_set_cr8(vcpu, cr8); 4828 ret = kvm_complete_insn_gp(vcpu, err); 4829 if (lapic_in_kernel(vcpu)) 4830 return ret; 4831 if (cr8_prev <= cr8) 4832 return ret; 4833 /* 4834 * TODO: we might be squashing a 4835 * KVM_GUESTDBG_SINGLESTEP-triggered 4836 * KVM_EXIT_DEBUG here. 4837 */ 4838 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4839 return 0; 4840 } 4841 } 4842 break; 4843 case 2: /* clts */ 4844 WARN_ONCE(1, "Guest should always own CR0.TS"); 4845 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4846 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4847 return kvm_skip_emulated_instruction(vcpu); 4848 case 1: /*mov from cr*/ 4849 switch (cr) { 4850 case 3: 4851 WARN_ON_ONCE(enable_unrestricted_guest); 4852 val = kvm_read_cr3(vcpu); 4853 kvm_register_write(vcpu, reg, val); 4854 trace_kvm_cr_read(cr, val); 4855 return kvm_skip_emulated_instruction(vcpu); 4856 case 8: 4857 val = kvm_get_cr8(vcpu); 4858 kvm_register_write(vcpu, reg, val); 4859 trace_kvm_cr_read(cr, val); 4860 return kvm_skip_emulated_instruction(vcpu); 4861 } 4862 break; 4863 case 3: /* lmsw */ 4864 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4865 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4866 kvm_lmsw(vcpu, val); 4867 4868 return kvm_skip_emulated_instruction(vcpu); 4869 default: 4870 break; 4871 } 4872 vcpu->run->exit_reason = 0; 4873 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4874 (int)(exit_qualification >> 4) & 3, cr); 4875 return 0; 4876 } 4877 4878 static int handle_dr(struct kvm_vcpu *vcpu) 4879 { 4880 unsigned long exit_qualification; 4881 int dr, dr7, reg; 4882 4883 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4884 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4885 4886 /* First, if DR does not exist, trigger UD */ 4887 if (!kvm_require_dr(vcpu, dr)) 4888 return 1; 4889 4890 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4891 if (!kvm_require_cpl(vcpu, 0)) 4892 return 1; 4893 dr7 = vmcs_readl(GUEST_DR7); 4894 if (dr7 & DR7_GD) { 4895 /* 4896 * As the vm-exit takes precedence over the debug trap, we 4897 * need to emulate the latter, either for the host or the 4898 * guest debugging itself. 4899 */ 4900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4901 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4902 vcpu->run->debug.arch.dr7 = dr7; 4903 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4904 vcpu->run->debug.arch.exception = DB_VECTOR; 4905 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4906 return 0; 4907 } else { 4908 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4909 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4910 kvm_queue_exception(vcpu, DB_VECTOR); 4911 return 1; 4912 } 4913 } 4914 4915 if (vcpu->guest_debug == 0) { 4916 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4917 4918 /* 4919 * No more DR vmexits; force a reload of the debug registers 4920 * and reenter on this instruction. The next vmexit will 4921 * retrieve the full state of the debug registers. 4922 */ 4923 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4924 return 1; 4925 } 4926 4927 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4928 if (exit_qualification & TYPE_MOV_FROM_DR) { 4929 unsigned long val; 4930 4931 if (kvm_get_dr(vcpu, dr, &val)) 4932 return 1; 4933 kvm_register_write(vcpu, reg, val); 4934 } else 4935 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4936 return 1; 4937 4938 return kvm_skip_emulated_instruction(vcpu); 4939 } 4940 4941 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4942 { 4943 return vcpu->arch.dr6; 4944 } 4945 4946 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4947 { 4948 } 4949 4950 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4951 { 4952 get_debugreg(vcpu->arch.db[0], 0); 4953 get_debugreg(vcpu->arch.db[1], 1); 4954 get_debugreg(vcpu->arch.db[2], 2); 4955 get_debugreg(vcpu->arch.db[3], 3); 4956 get_debugreg(vcpu->arch.dr6, 6); 4957 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4958 4959 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4960 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4961 } 4962 4963 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4964 { 4965 vmcs_writel(GUEST_DR7, val); 4966 } 4967 4968 static int handle_cpuid(struct kvm_vcpu *vcpu) 4969 { 4970 return kvm_emulate_cpuid(vcpu); 4971 } 4972 4973 static int handle_rdmsr(struct kvm_vcpu *vcpu) 4974 { 4975 return kvm_emulate_rdmsr(vcpu); 4976 } 4977 4978 static int handle_wrmsr(struct kvm_vcpu *vcpu) 4979 { 4980 return kvm_emulate_wrmsr(vcpu); 4981 } 4982 4983 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4984 { 4985 kvm_apic_update_ppr(vcpu); 4986 return 1; 4987 } 4988 4989 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4990 { 4991 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING); 4992 4993 kvm_make_request(KVM_REQ_EVENT, vcpu); 4994 4995 ++vcpu->stat.irq_window_exits; 4996 return 1; 4997 } 4998 4999 static int handle_halt(struct kvm_vcpu *vcpu) 5000 { 5001 return kvm_emulate_halt(vcpu); 5002 } 5003 5004 static int handle_vmcall(struct kvm_vcpu *vcpu) 5005 { 5006 return kvm_emulate_hypercall(vcpu); 5007 } 5008 5009 static int handle_invd(struct kvm_vcpu *vcpu) 5010 { 5011 return kvm_emulate_instruction(vcpu, 0); 5012 } 5013 5014 static int handle_invlpg(struct kvm_vcpu *vcpu) 5015 { 5016 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5017 5018 kvm_mmu_invlpg(vcpu, exit_qualification); 5019 return kvm_skip_emulated_instruction(vcpu); 5020 } 5021 5022 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5023 { 5024 int err; 5025 5026 err = kvm_rdpmc(vcpu); 5027 return kvm_complete_insn_gp(vcpu, err); 5028 } 5029 5030 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5031 { 5032 return kvm_emulate_wbinvd(vcpu); 5033 } 5034 5035 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5036 { 5037 u64 new_bv = kvm_read_edx_eax(vcpu); 5038 u32 index = kvm_rcx_read(vcpu); 5039 5040 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5041 return kvm_skip_emulated_instruction(vcpu); 5042 return 1; 5043 } 5044 5045 static int handle_apic_access(struct kvm_vcpu *vcpu) 5046 { 5047 if (likely(fasteoi)) { 5048 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5049 int access_type, offset; 5050 5051 access_type = exit_qualification & APIC_ACCESS_TYPE; 5052 offset = exit_qualification & APIC_ACCESS_OFFSET; 5053 /* 5054 * Sane guest uses MOV to write EOI, with written value 5055 * not cared. So make a short-circuit here by avoiding 5056 * heavy instruction emulation. 5057 */ 5058 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5059 (offset == APIC_EOI)) { 5060 kvm_lapic_set_eoi(vcpu); 5061 return kvm_skip_emulated_instruction(vcpu); 5062 } 5063 } 5064 return kvm_emulate_instruction(vcpu, 0); 5065 } 5066 5067 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5068 { 5069 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5070 int vector = exit_qualification & 0xff; 5071 5072 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5073 kvm_apic_set_eoi_accelerated(vcpu, vector); 5074 return 1; 5075 } 5076 5077 static int handle_apic_write(struct kvm_vcpu *vcpu) 5078 { 5079 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5080 u32 offset = exit_qualification & 0xfff; 5081 5082 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5083 kvm_apic_write_nodecode(vcpu, offset); 5084 return 1; 5085 } 5086 5087 static int handle_task_switch(struct kvm_vcpu *vcpu) 5088 { 5089 struct vcpu_vmx *vmx = to_vmx(vcpu); 5090 unsigned long exit_qualification; 5091 bool has_error_code = false; 5092 u32 error_code = 0; 5093 u16 tss_selector; 5094 int reason, type, idt_v, idt_index; 5095 5096 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5097 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5098 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5099 5100 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5101 5102 reason = (u32)exit_qualification >> 30; 5103 if (reason == TASK_SWITCH_GATE && idt_v) { 5104 switch (type) { 5105 case INTR_TYPE_NMI_INTR: 5106 vcpu->arch.nmi_injected = false; 5107 vmx_set_nmi_mask(vcpu, true); 5108 break; 5109 case INTR_TYPE_EXT_INTR: 5110 case INTR_TYPE_SOFT_INTR: 5111 kvm_clear_interrupt_queue(vcpu); 5112 break; 5113 case INTR_TYPE_HARD_EXCEPTION: 5114 if (vmx->idt_vectoring_info & 5115 VECTORING_INFO_DELIVER_CODE_MASK) { 5116 has_error_code = true; 5117 error_code = 5118 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5119 } 5120 /* fall through */ 5121 case INTR_TYPE_SOFT_EXCEPTION: 5122 kvm_clear_exception_queue(vcpu); 5123 break; 5124 default: 5125 break; 5126 } 5127 } 5128 tss_selector = exit_qualification; 5129 5130 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5131 type != INTR_TYPE_EXT_INTR && 5132 type != INTR_TYPE_NMI_INTR)) 5133 WARN_ON(!skip_emulated_instruction(vcpu)); 5134 5135 /* 5136 * TODO: What about debug traps on tss switch? 5137 * Are we supposed to inject them and update dr6? 5138 */ 5139 return kvm_task_switch(vcpu, tss_selector, 5140 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5141 reason, has_error_code, error_code); 5142 } 5143 5144 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5145 { 5146 unsigned long exit_qualification; 5147 gpa_t gpa; 5148 u64 error_code; 5149 5150 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5151 5152 /* 5153 * EPT violation happened while executing iret from NMI, 5154 * "blocked by NMI" bit has to be set before next VM entry. 5155 * There are errata that may cause this bit to not be set: 5156 * AAK134, BY25. 5157 */ 5158 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5159 enable_vnmi && 5160 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5161 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5162 5163 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5164 trace_kvm_page_fault(gpa, exit_qualification); 5165 5166 /* Is it a read fault? */ 5167 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5168 ? PFERR_USER_MASK : 0; 5169 /* Is it a write fault? */ 5170 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5171 ? PFERR_WRITE_MASK : 0; 5172 /* Is it a fetch fault? */ 5173 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5174 ? PFERR_FETCH_MASK : 0; 5175 /* ept page table entry is present? */ 5176 error_code |= (exit_qualification & 5177 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5178 EPT_VIOLATION_EXECUTABLE)) 5179 ? PFERR_PRESENT_MASK : 0; 5180 5181 error_code |= (exit_qualification & 0x100) != 0 ? 5182 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5183 5184 vcpu->arch.exit_qualification = exit_qualification; 5185 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5186 } 5187 5188 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5189 { 5190 gpa_t gpa; 5191 5192 /* 5193 * A nested guest cannot optimize MMIO vmexits, because we have an 5194 * nGPA here instead of the required GPA. 5195 */ 5196 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5197 if (!is_guest_mode(vcpu) && 5198 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5199 trace_kvm_fast_mmio(gpa); 5200 return kvm_skip_emulated_instruction(vcpu); 5201 } 5202 5203 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5204 } 5205 5206 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5207 { 5208 WARN_ON_ONCE(!enable_vnmi); 5209 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING); 5210 ++vcpu->stat.nmi_window_exits; 5211 kvm_make_request(KVM_REQ_EVENT, vcpu); 5212 5213 return 1; 5214 } 5215 5216 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5217 { 5218 struct vcpu_vmx *vmx = to_vmx(vcpu); 5219 bool intr_window_requested; 5220 unsigned count = 130; 5221 5222 /* 5223 * We should never reach the point where we are emulating L2 5224 * due to invalid guest state as that means we incorrectly 5225 * allowed a nested VMEntry with an invalid vmcs12. 5226 */ 5227 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5228 5229 intr_window_requested = exec_controls_get(vmx) & 5230 CPU_BASED_VIRTUAL_INTR_PENDING; 5231 5232 while (vmx->emulation_required && count-- != 0) { 5233 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5234 return handle_interrupt_window(&vmx->vcpu); 5235 5236 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5237 return 1; 5238 5239 if (!kvm_emulate_instruction(vcpu, 0)) 5240 return 0; 5241 5242 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5243 vcpu->arch.exception.pending) { 5244 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5245 vcpu->run->internal.suberror = 5246 KVM_INTERNAL_ERROR_EMULATION; 5247 vcpu->run->internal.ndata = 0; 5248 return 0; 5249 } 5250 5251 if (vcpu->arch.halt_request) { 5252 vcpu->arch.halt_request = 0; 5253 return kvm_vcpu_halt(vcpu); 5254 } 5255 5256 /* 5257 * Note, return 1 and not 0, vcpu_run() is responsible for 5258 * morphing the pending signal into the proper return code. 5259 */ 5260 if (signal_pending(current)) 5261 return 1; 5262 5263 if (need_resched()) 5264 schedule(); 5265 } 5266 5267 return 1; 5268 } 5269 5270 static void grow_ple_window(struct kvm_vcpu *vcpu) 5271 { 5272 struct vcpu_vmx *vmx = to_vmx(vcpu); 5273 unsigned int old = vmx->ple_window; 5274 5275 vmx->ple_window = __grow_ple_window(old, ple_window, 5276 ple_window_grow, 5277 ple_window_max); 5278 5279 if (vmx->ple_window != old) { 5280 vmx->ple_window_dirty = true; 5281 trace_kvm_ple_window_update(vcpu->vcpu_id, 5282 vmx->ple_window, old); 5283 } 5284 } 5285 5286 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5287 { 5288 struct vcpu_vmx *vmx = to_vmx(vcpu); 5289 unsigned int old = vmx->ple_window; 5290 5291 vmx->ple_window = __shrink_ple_window(old, ple_window, 5292 ple_window_shrink, 5293 ple_window); 5294 5295 if (vmx->ple_window != old) { 5296 vmx->ple_window_dirty = true; 5297 trace_kvm_ple_window_update(vcpu->vcpu_id, 5298 vmx->ple_window, old); 5299 } 5300 } 5301 5302 /* 5303 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5304 */ 5305 static void wakeup_handler(void) 5306 { 5307 struct kvm_vcpu *vcpu; 5308 int cpu = smp_processor_id(); 5309 5310 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5311 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5312 blocked_vcpu_list) { 5313 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5314 5315 if (pi_test_on(pi_desc) == 1) 5316 kvm_vcpu_kick(vcpu); 5317 } 5318 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5319 } 5320 5321 static void vmx_enable_tdp(void) 5322 { 5323 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5324 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5325 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5326 0ull, VMX_EPT_EXECUTABLE_MASK, 5327 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5328 VMX_EPT_RWX_MASK, 0ull); 5329 5330 ept_set_mmio_spte_mask(); 5331 kvm_enable_tdp(); 5332 } 5333 5334 /* 5335 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5336 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5337 */ 5338 static int handle_pause(struct kvm_vcpu *vcpu) 5339 { 5340 if (!kvm_pause_in_guest(vcpu->kvm)) 5341 grow_ple_window(vcpu); 5342 5343 /* 5344 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5345 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5346 * never set PAUSE_EXITING and just set PLE if supported, 5347 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5348 */ 5349 kvm_vcpu_on_spin(vcpu, true); 5350 return kvm_skip_emulated_instruction(vcpu); 5351 } 5352 5353 static int handle_nop(struct kvm_vcpu *vcpu) 5354 { 5355 return kvm_skip_emulated_instruction(vcpu); 5356 } 5357 5358 static int handle_mwait(struct kvm_vcpu *vcpu) 5359 { 5360 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5361 return handle_nop(vcpu); 5362 } 5363 5364 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5365 { 5366 kvm_queue_exception(vcpu, UD_VECTOR); 5367 return 1; 5368 } 5369 5370 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5371 { 5372 return 1; 5373 } 5374 5375 static int handle_monitor(struct kvm_vcpu *vcpu) 5376 { 5377 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5378 return handle_nop(vcpu); 5379 } 5380 5381 static int handle_invpcid(struct kvm_vcpu *vcpu) 5382 { 5383 u32 vmx_instruction_info; 5384 unsigned long type; 5385 bool pcid_enabled; 5386 gva_t gva; 5387 struct x86_exception e; 5388 unsigned i; 5389 unsigned long roots_to_free = 0; 5390 struct { 5391 u64 pcid; 5392 u64 gla; 5393 } operand; 5394 5395 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5396 kvm_queue_exception(vcpu, UD_VECTOR); 5397 return 1; 5398 } 5399 5400 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5401 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5402 5403 if (type > 3) { 5404 kvm_inject_gp(vcpu, 0); 5405 return 1; 5406 } 5407 5408 /* According to the Intel instruction reference, the memory operand 5409 * is read even if it isn't needed (e.g., for type==all) 5410 */ 5411 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5412 vmx_instruction_info, false, 5413 sizeof(operand), &gva)) 5414 return 1; 5415 5416 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5417 kvm_inject_page_fault(vcpu, &e); 5418 return 1; 5419 } 5420 5421 if (operand.pcid >> 12 != 0) { 5422 kvm_inject_gp(vcpu, 0); 5423 return 1; 5424 } 5425 5426 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5427 5428 switch (type) { 5429 case INVPCID_TYPE_INDIV_ADDR: 5430 if ((!pcid_enabled && (operand.pcid != 0)) || 5431 is_noncanonical_address(operand.gla, vcpu)) { 5432 kvm_inject_gp(vcpu, 0); 5433 return 1; 5434 } 5435 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5436 return kvm_skip_emulated_instruction(vcpu); 5437 5438 case INVPCID_TYPE_SINGLE_CTXT: 5439 if (!pcid_enabled && (operand.pcid != 0)) { 5440 kvm_inject_gp(vcpu, 0); 5441 return 1; 5442 } 5443 5444 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5445 kvm_mmu_sync_roots(vcpu); 5446 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5447 } 5448 5449 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5450 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5451 == operand.pcid) 5452 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5453 5454 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5455 /* 5456 * If neither the current cr3 nor any of the prev_roots use the 5457 * given PCID, then nothing needs to be done here because a 5458 * resync will happen anyway before switching to any other CR3. 5459 */ 5460 5461 return kvm_skip_emulated_instruction(vcpu); 5462 5463 case INVPCID_TYPE_ALL_NON_GLOBAL: 5464 /* 5465 * Currently, KVM doesn't mark global entries in the shadow 5466 * page tables, so a non-global flush just degenerates to a 5467 * global flush. If needed, we could optimize this later by 5468 * keeping track of global entries in shadow page tables. 5469 */ 5470 5471 /* fall-through */ 5472 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5473 kvm_mmu_unload(vcpu); 5474 return kvm_skip_emulated_instruction(vcpu); 5475 5476 default: 5477 BUG(); /* We have already checked above that type <= 3 */ 5478 } 5479 } 5480 5481 static int handle_pml_full(struct kvm_vcpu *vcpu) 5482 { 5483 unsigned long exit_qualification; 5484 5485 trace_kvm_pml_full(vcpu->vcpu_id); 5486 5487 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5488 5489 /* 5490 * PML buffer FULL happened while executing iret from NMI, 5491 * "blocked by NMI" bit has to be set before next VM entry. 5492 */ 5493 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5494 enable_vnmi && 5495 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5496 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5497 GUEST_INTR_STATE_NMI); 5498 5499 /* 5500 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5501 * here.., and there's no userspace involvement needed for PML. 5502 */ 5503 return 1; 5504 } 5505 5506 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5507 { 5508 struct vcpu_vmx *vmx = to_vmx(vcpu); 5509 5510 if (!vmx->req_immediate_exit && 5511 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5512 kvm_lapic_expired_hv_timer(vcpu); 5513 5514 return 1; 5515 } 5516 5517 /* 5518 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5519 * are overwritten by nested_vmx_setup() when nested=1. 5520 */ 5521 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5522 { 5523 kvm_queue_exception(vcpu, UD_VECTOR); 5524 return 1; 5525 } 5526 5527 static int handle_encls(struct kvm_vcpu *vcpu) 5528 { 5529 /* 5530 * SGX virtualization is not yet supported. There is no software 5531 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5532 * to prevent the guest from executing ENCLS. 5533 */ 5534 kvm_queue_exception(vcpu, UD_VECTOR); 5535 return 1; 5536 } 5537 5538 /* 5539 * The exit handlers return 1 if the exit was handled fully and guest execution 5540 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5541 * to be done to userspace and return 0. 5542 */ 5543 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5544 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5545 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5546 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5547 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5548 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5549 [EXIT_REASON_CR_ACCESS] = handle_cr, 5550 [EXIT_REASON_DR_ACCESS] = handle_dr, 5551 [EXIT_REASON_CPUID] = handle_cpuid, 5552 [EXIT_REASON_MSR_READ] = handle_rdmsr, 5553 [EXIT_REASON_MSR_WRITE] = handle_wrmsr, 5554 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, 5555 [EXIT_REASON_HLT] = handle_halt, 5556 [EXIT_REASON_INVD] = handle_invd, 5557 [EXIT_REASON_INVLPG] = handle_invlpg, 5558 [EXIT_REASON_RDPMC] = handle_rdpmc, 5559 [EXIT_REASON_VMCALL] = handle_vmcall, 5560 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5561 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5562 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5563 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5564 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5565 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5566 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5567 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5568 [EXIT_REASON_VMON] = handle_vmx_instruction, 5569 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5570 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5571 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5572 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5573 [EXIT_REASON_WBINVD] = handle_wbinvd, 5574 [EXIT_REASON_XSETBV] = handle_xsetbv, 5575 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5576 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5577 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5578 [EXIT_REASON_LDTR_TR] = handle_desc, 5579 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5580 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5581 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5582 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5583 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5584 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5585 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5586 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5587 [EXIT_REASON_RDRAND] = handle_invalid_op, 5588 [EXIT_REASON_RDSEED] = handle_invalid_op, 5589 [EXIT_REASON_PML_FULL] = handle_pml_full, 5590 [EXIT_REASON_INVPCID] = handle_invpcid, 5591 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5592 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5593 [EXIT_REASON_ENCLS] = handle_encls, 5594 }; 5595 5596 static const int kvm_vmx_max_exit_handlers = 5597 ARRAY_SIZE(kvm_vmx_exit_handlers); 5598 5599 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5600 { 5601 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5602 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5603 } 5604 5605 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5606 { 5607 if (vmx->pml_pg) { 5608 __free_page(vmx->pml_pg); 5609 vmx->pml_pg = NULL; 5610 } 5611 } 5612 5613 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5614 { 5615 struct vcpu_vmx *vmx = to_vmx(vcpu); 5616 u64 *pml_buf; 5617 u16 pml_idx; 5618 5619 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5620 5621 /* Do nothing if PML buffer is empty */ 5622 if (pml_idx == (PML_ENTITY_NUM - 1)) 5623 return; 5624 5625 /* PML index always points to next available PML buffer entity */ 5626 if (pml_idx >= PML_ENTITY_NUM) 5627 pml_idx = 0; 5628 else 5629 pml_idx++; 5630 5631 pml_buf = page_address(vmx->pml_pg); 5632 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5633 u64 gpa; 5634 5635 gpa = pml_buf[pml_idx]; 5636 WARN_ON(gpa & (PAGE_SIZE - 1)); 5637 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5638 } 5639 5640 /* reset PML index */ 5641 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5642 } 5643 5644 /* 5645 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5646 * Called before reporting dirty_bitmap to userspace. 5647 */ 5648 static void kvm_flush_pml_buffers(struct kvm *kvm) 5649 { 5650 int i; 5651 struct kvm_vcpu *vcpu; 5652 /* 5653 * We only need to kick vcpu out of guest mode here, as PML buffer 5654 * is flushed at beginning of all VMEXITs, and it's obvious that only 5655 * vcpus running in guest are possible to have unflushed GPAs in PML 5656 * buffer. 5657 */ 5658 kvm_for_each_vcpu(i, vcpu, kvm) 5659 kvm_vcpu_kick(vcpu); 5660 } 5661 5662 static void vmx_dump_sel(char *name, uint32_t sel) 5663 { 5664 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5665 name, vmcs_read16(sel), 5666 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5667 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5668 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5669 } 5670 5671 static void vmx_dump_dtsel(char *name, uint32_t limit) 5672 { 5673 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5674 name, vmcs_read32(limit), 5675 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5676 } 5677 5678 void dump_vmcs(void) 5679 { 5680 u32 vmentry_ctl, vmexit_ctl; 5681 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5682 unsigned long cr4; 5683 u64 efer; 5684 int i, n; 5685 5686 if (!dump_invalid_vmcs) { 5687 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5688 return; 5689 } 5690 5691 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5692 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5693 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5694 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5695 cr4 = vmcs_readl(GUEST_CR4); 5696 efer = vmcs_read64(GUEST_IA32_EFER); 5697 secondary_exec_control = 0; 5698 if (cpu_has_secondary_exec_ctrls()) 5699 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5700 5701 pr_err("*** Guest State ***\n"); 5702 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5703 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5704 vmcs_readl(CR0_GUEST_HOST_MASK)); 5705 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5706 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5707 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5708 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5709 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5710 { 5711 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5712 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5713 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5714 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5715 } 5716 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5717 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5718 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5719 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5720 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5721 vmcs_readl(GUEST_SYSENTER_ESP), 5722 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5723 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5724 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5725 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5726 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5727 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5728 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5729 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5730 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5731 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5732 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5733 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5734 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5735 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5736 efer, vmcs_read64(GUEST_IA32_PAT)); 5737 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5738 vmcs_read64(GUEST_IA32_DEBUGCTL), 5739 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5740 if (cpu_has_load_perf_global_ctrl() && 5741 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5742 pr_err("PerfGlobCtl = 0x%016llx\n", 5743 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5744 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5745 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5746 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5747 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5748 vmcs_read32(GUEST_ACTIVITY_STATE)); 5749 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5750 pr_err("InterruptStatus = %04x\n", 5751 vmcs_read16(GUEST_INTR_STATUS)); 5752 5753 pr_err("*** Host State ***\n"); 5754 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5755 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5756 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5757 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5758 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5759 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5760 vmcs_read16(HOST_TR_SELECTOR)); 5761 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5762 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5763 vmcs_readl(HOST_TR_BASE)); 5764 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5765 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5766 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5767 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5768 vmcs_readl(HOST_CR4)); 5769 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5770 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5771 vmcs_read32(HOST_IA32_SYSENTER_CS), 5772 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5773 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5774 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5775 vmcs_read64(HOST_IA32_EFER), 5776 vmcs_read64(HOST_IA32_PAT)); 5777 if (cpu_has_load_perf_global_ctrl() && 5778 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5779 pr_err("PerfGlobCtl = 0x%016llx\n", 5780 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5781 5782 pr_err("*** Control State ***\n"); 5783 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5784 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5785 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5786 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5787 vmcs_read32(EXCEPTION_BITMAP), 5788 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5789 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5790 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5791 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5792 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5793 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5794 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5795 vmcs_read32(VM_EXIT_INTR_INFO), 5796 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5797 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5798 pr_err(" reason=%08x qualification=%016lx\n", 5799 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5800 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5801 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5802 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5803 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5804 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5805 pr_err("TSC Multiplier = 0x%016llx\n", 5806 vmcs_read64(TSC_MULTIPLIER)); 5807 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5808 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5809 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5810 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5811 } 5812 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5813 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5814 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5815 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5816 } 5817 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5818 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5819 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5820 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5821 n = vmcs_read32(CR3_TARGET_COUNT); 5822 for (i = 0; i + 1 < n; i += 4) 5823 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5824 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5825 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5826 if (i < n) 5827 pr_err("CR3 target%u=%016lx\n", 5828 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5829 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5830 pr_err("PLE Gap=%08x Window=%08x\n", 5831 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5832 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5833 pr_err("Virtual processor ID = 0x%04x\n", 5834 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5835 } 5836 5837 /* 5838 * The guest has exited. See if we can fix it or if we need userspace 5839 * assistance. 5840 */ 5841 static int vmx_handle_exit(struct kvm_vcpu *vcpu) 5842 { 5843 struct vcpu_vmx *vmx = to_vmx(vcpu); 5844 u32 exit_reason = vmx->exit_reason; 5845 u32 vectoring_info = vmx->idt_vectoring_info; 5846 5847 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5848 5849 /* 5850 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5851 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5852 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5853 * mode as if vcpus is in root mode, the PML buffer must has been 5854 * flushed already. 5855 */ 5856 if (enable_pml) 5857 vmx_flush_pml_buffer(vcpu); 5858 5859 /* If guest state is invalid, start emulating */ 5860 if (vmx->emulation_required) 5861 return handle_invalid_guest_state(vcpu); 5862 5863 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5864 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5865 5866 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5867 dump_vmcs(); 5868 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5869 vcpu->run->fail_entry.hardware_entry_failure_reason 5870 = exit_reason; 5871 return 0; 5872 } 5873 5874 if (unlikely(vmx->fail)) { 5875 dump_vmcs(); 5876 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5877 vcpu->run->fail_entry.hardware_entry_failure_reason 5878 = vmcs_read32(VM_INSTRUCTION_ERROR); 5879 return 0; 5880 } 5881 5882 /* 5883 * Note: 5884 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5885 * delivery event since it indicates guest is accessing MMIO. 5886 * The vm-exit can be triggered again after return to guest that 5887 * will cause infinite loop. 5888 */ 5889 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5890 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5891 exit_reason != EXIT_REASON_EPT_VIOLATION && 5892 exit_reason != EXIT_REASON_PML_FULL && 5893 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5894 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5895 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5896 vcpu->run->internal.ndata = 3; 5897 vcpu->run->internal.data[0] = vectoring_info; 5898 vcpu->run->internal.data[1] = exit_reason; 5899 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5900 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5901 vcpu->run->internal.ndata++; 5902 vcpu->run->internal.data[3] = 5903 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5904 } 5905 return 0; 5906 } 5907 5908 if (unlikely(!enable_vnmi && 5909 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5910 if (vmx_interrupt_allowed(vcpu)) { 5911 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5912 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5913 vcpu->arch.nmi_pending) { 5914 /* 5915 * This CPU don't support us in finding the end of an 5916 * NMI-blocked window if the guest runs with IRQs 5917 * disabled. So we pull the trigger after 1 s of 5918 * futile waiting, but inform the user about this. 5919 */ 5920 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5921 "state on VCPU %d after 1 s timeout\n", 5922 __func__, vcpu->vcpu_id); 5923 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5924 } 5925 } 5926 5927 if (exit_reason < kvm_vmx_max_exit_handlers 5928 && kvm_vmx_exit_handlers[exit_reason]) 5929 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5930 else { 5931 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", 5932 exit_reason); 5933 dump_vmcs(); 5934 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5935 vcpu->run->internal.suberror = 5936 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5937 vcpu->run->internal.ndata = 1; 5938 vcpu->run->internal.data[0] = exit_reason; 5939 return 0; 5940 } 5941 } 5942 5943 /* 5944 * Software based L1D cache flush which is used when microcode providing 5945 * the cache control MSR is not loaded. 5946 * 5947 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5948 * flush it is required to read in 64 KiB because the replacement algorithm 5949 * is not exactly LRU. This could be sized at runtime via topology 5950 * information but as all relevant affected CPUs have 32KiB L1D cache size 5951 * there is no point in doing so. 5952 */ 5953 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5954 { 5955 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5956 5957 /* 5958 * This code is only executed when the the flush mode is 'cond' or 5959 * 'always' 5960 */ 5961 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5962 bool flush_l1d; 5963 5964 /* 5965 * Clear the per-vcpu flush bit, it gets set again 5966 * either from vcpu_run() or from one of the unsafe 5967 * VMEXIT handlers. 5968 */ 5969 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5970 vcpu->arch.l1tf_flush_l1d = false; 5971 5972 /* 5973 * Clear the per-cpu flush bit, it gets set again from 5974 * the interrupt handlers. 5975 */ 5976 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 5977 kvm_clear_cpu_l1tf_flush_l1d(); 5978 5979 if (!flush_l1d) 5980 return; 5981 } 5982 5983 vcpu->stat.l1d_flush++; 5984 5985 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 5986 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 5987 return; 5988 } 5989 5990 asm volatile( 5991 /* First ensure the pages are in the TLB */ 5992 "xorl %%eax, %%eax\n" 5993 ".Lpopulate_tlb:\n\t" 5994 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5995 "addl $4096, %%eax\n\t" 5996 "cmpl %%eax, %[size]\n\t" 5997 "jne .Lpopulate_tlb\n\t" 5998 "xorl %%eax, %%eax\n\t" 5999 "cpuid\n\t" 6000 /* Now fill the cache */ 6001 "xorl %%eax, %%eax\n" 6002 ".Lfill_cache:\n" 6003 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6004 "addl $64, %%eax\n\t" 6005 "cmpl %%eax, %[size]\n\t" 6006 "jne .Lfill_cache\n\t" 6007 "lfence\n" 6008 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6009 [size] "r" (size) 6010 : "eax", "ebx", "ecx", "edx"); 6011 } 6012 6013 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6014 { 6015 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6016 6017 if (is_guest_mode(vcpu) && 6018 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6019 return; 6020 6021 if (irr == -1 || tpr < irr) { 6022 vmcs_write32(TPR_THRESHOLD, 0); 6023 return; 6024 } 6025 6026 vmcs_write32(TPR_THRESHOLD, irr); 6027 } 6028 6029 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6030 { 6031 struct vcpu_vmx *vmx = to_vmx(vcpu); 6032 u32 sec_exec_control; 6033 6034 if (!lapic_in_kernel(vcpu)) 6035 return; 6036 6037 if (!flexpriority_enabled && 6038 !cpu_has_vmx_virtualize_x2apic_mode()) 6039 return; 6040 6041 /* Postpone execution until vmcs01 is the current VMCS. */ 6042 if (is_guest_mode(vcpu)) { 6043 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6044 return; 6045 } 6046 6047 sec_exec_control = secondary_exec_controls_get(vmx); 6048 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6049 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6050 6051 switch (kvm_get_apic_mode(vcpu)) { 6052 case LAPIC_MODE_INVALID: 6053 WARN_ONCE(true, "Invalid local APIC state"); 6054 case LAPIC_MODE_DISABLED: 6055 break; 6056 case LAPIC_MODE_XAPIC: 6057 if (flexpriority_enabled) { 6058 sec_exec_control |= 6059 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6060 vmx_flush_tlb(vcpu, true); 6061 } 6062 break; 6063 case LAPIC_MODE_X2APIC: 6064 if (cpu_has_vmx_virtualize_x2apic_mode()) 6065 sec_exec_control |= 6066 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6067 break; 6068 } 6069 secondary_exec_controls_set(vmx, sec_exec_control); 6070 6071 vmx_update_msr_bitmap(vcpu); 6072 } 6073 6074 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6075 { 6076 if (!is_guest_mode(vcpu)) { 6077 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6078 vmx_flush_tlb(vcpu, true); 6079 } 6080 } 6081 6082 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6083 { 6084 u16 status; 6085 u8 old; 6086 6087 if (max_isr == -1) 6088 max_isr = 0; 6089 6090 status = vmcs_read16(GUEST_INTR_STATUS); 6091 old = status >> 8; 6092 if (max_isr != old) { 6093 status &= 0xff; 6094 status |= max_isr << 8; 6095 vmcs_write16(GUEST_INTR_STATUS, status); 6096 } 6097 } 6098 6099 static void vmx_set_rvi(int vector) 6100 { 6101 u16 status; 6102 u8 old; 6103 6104 if (vector == -1) 6105 vector = 0; 6106 6107 status = vmcs_read16(GUEST_INTR_STATUS); 6108 old = (u8)status & 0xff; 6109 if ((u8)vector != old) { 6110 status &= ~0xff; 6111 status |= (u8)vector; 6112 vmcs_write16(GUEST_INTR_STATUS, status); 6113 } 6114 } 6115 6116 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6117 { 6118 /* 6119 * When running L2, updating RVI is only relevant when 6120 * vmcs12 virtual-interrupt-delivery enabled. 6121 * However, it can be enabled only when L1 also 6122 * intercepts external-interrupts and in that case 6123 * we should not update vmcs02 RVI but instead intercept 6124 * interrupt. Therefore, do nothing when running L2. 6125 */ 6126 if (!is_guest_mode(vcpu)) 6127 vmx_set_rvi(max_irr); 6128 } 6129 6130 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6131 { 6132 struct vcpu_vmx *vmx = to_vmx(vcpu); 6133 int max_irr; 6134 bool max_irr_updated; 6135 6136 WARN_ON(!vcpu->arch.apicv_active); 6137 if (pi_test_on(&vmx->pi_desc)) { 6138 pi_clear_on(&vmx->pi_desc); 6139 /* 6140 * IOMMU can write to PIR.ON, so the barrier matters even on UP. 6141 * But on x86 this is just a compiler barrier anyway. 6142 */ 6143 smp_mb__after_atomic(); 6144 max_irr_updated = 6145 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6146 6147 /* 6148 * If we are running L2 and L1 has a new pending interrupt 6149 * which can be injected, we should re-evaluate 6150 * what should be done with this new L1 interrupt. 6151 * If L1 intercepts external-interrupts, we should 6152 * exit from L2 to L1. Otherwise, interrupt should be 6153 * delivered directly to L2. 6154 */ 6155 if (is_guest_mode(vcpu) && max_irr_updated) { 6156 if (nested_exit_on_intr(vcpu)) 6157 kvm_vcpu_exiting_guest_mode(vcpu); 6158 else 6159 kvm_make_request(KVM_REQ_EVENT, vcpu); 6160 } 6161 } else { 6162 max_irr = kvm_lapic_find_highest_irr(vcpu); 6163 } 6164 vmx_hwapic_irr_update(vcpu, max_irr); 6165 return max_irr; 6166 } 6167 6168 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6169 { 6170 return pi_test_on(vcpu_to_pi_desc(vcpu)); 6171 } 6172 6173 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6174 { 6175 if (!kvm_vcpu_apicv_active(vcpu)) 6176 return; 6177 6178 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6179 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6180 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6181 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6182 } 6183 6184 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6185 { 6186 struct vcpu_vmx *vmx = to_vmx(vcpu); 6187 6188 pi_clear_on(&vmx->pi_desc); 6189 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6190 } 6191 6192 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6193 { 6194 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6195 6196 /* if exit due to PF check for async PF */ 6197 if (is_page_fault(vmx->exit_intr_info)) 6198 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6199 6200 /* Handle machine checks before interrupts are enabled */ 6201 if (is_machine_check(vmx->exit_intr_info)) 6202 kvm_machine_check(); 6203 6204 /* We need to handle NMIs before interrupts are enabled */ 6205 if (is_nmi(vmx->exit_intr_info)) { 6206 kvm_before_interrupt(&vmx->vcpu); 6207 asm("int $2"); 6208 kvm_after_interrupt(&vmx->vcpu); 6209 } 6210 } 6211 6212 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6213 { 6214 unsigned int vector; 6215 unsigned long entry; 6216 #ifdef CONFIG_X86_64 6217 unsigned long tmp; 6218 #endif 6219 gate_desc *desc; 6220 u32 intr_info; 6221 6222 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6223 if (WARN_ONCE(!is_external_intr(intr_info), 6224 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6225 return; 6226 6227 vector = intr_info & INTR_INFO_VECTOR_MASK; 6228 desc = (gate_desc *)host_idt_base + vector; 6229 entry = gate_offset(desc); 6230 6231 kvm_before_interrupt(vcpu); 6232 6233 asm volatile( 6234 #ifdef CONFIG_X86_64 6235 "mov %%" _ASM_SP ", %[sp]\n\t" 6236 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6237 "push $%c[ss]\n\t" 6238 "push %[sp]\n\t" 6239 #endif 6240 "pushf\n\t" 6241 __ASM_SIZE(push) " $%c[cs]\n\t" 6242 CALL_NOSPEC 6243 : 6244 #ifdef CONFIG_X86_64 6245 [sp]"=&r"(tmp), 6246 #endif 6247 ASM_CALL_CONSTRAINT 6248 : 6249 THUNK_TARGET(entry), 6250 [ss]"i"(__KERNEL_DS), 6251 [cs]"i"(__KERNEL_CS) 6252 ); 6253 6254 kvm_after_interrupt(vcpu); 6255 } 6256 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6257 6258 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu) 6259 { 6260 struct vcpu_vmx *vmx = to_vmx(vcpu); 6261 6262 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6263 handle_external_interrupt_irqoff(vcpu); 6264 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6265 handle_exception_nmi_irqoff(vmx); 6266 } 6267 6268 static bool vmx_has_emulated_msr(int index) 6269 { 6270 switch (index) { 6271 case MSR_IA32_SMBASE: 6272 /* 6273 * We cannot do SMM unless we can run the guest in big 6274 * real mode. 6275 */ 6276 return enable_unrestricted_guest || emulate_invalid_guest_state; 6277 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6278 return nested; 6279 case MSR_AMD64_VIRT_SPEC_CTRL: 6280 /* This is AMD only. */ 6281 return false; 6282 default: 6283 return true; 6284 } 6285 } 6286 6287 static bool vmx_pt_supported(void) 6288 { 6289 return pt_mode == PT_MODE_HOST_GUEST; 6290 } 6291 6292 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6293 { 6294 u32 exit_intr_info; 6295 bool unblock_nmi; 6296 u8 vector; 6297 bool idtv_info_valid; 6298 6299 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6300 6301 if (enable_vnmi) { 6302 if (vmx->loaded_vmcs->nmi_known_unmasked) 6303 return; 6304 /* 6305 * Can't use vmx->exit_intr_info since we're not sure what 6306 * the exit reason is. 6307 */ 6308 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6309 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6310 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6311 /* 6312 * SDM 3: 27.7.1.2 (September 2008) 6313 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6314 * a guest IRET fault. 6315 * SDM 3: 23.2.2 (September 2008) 6316 * Bit 12 is undefined in any of the following cases: 6317 * If the VM exit sets the valid bit in the IDT-vectoring 6318 * information field. 6319 * If the VM exit is due to a double fault. 6320 */ 6321 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6322 vector != DF_VECTOR && !idtv_info_valid) 6323 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6324 GUEST_INTR_STATE_NMI); 6325 else 6326 vmx->loaded_vmcs->nmi_known_unmasked = 6327 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6328 & GUEST_INTR_STATE_NMI); 6329 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6330 vmx->loaded_vmcs->vnmi_blocked_time += 6331 ktime_to_ns(ktime_sub(ktime_get(), 6332 vmx->loaded_vmcs->entry_time)); 6333 } 6334 6335 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6336 u32 idt_vectoring_info, 6337 int instr_len_field, 6338 int error_code_field) 6339 { 6340 u8 vector; 6341 int type; 6342 bool idtv_info_valid; 6343 6344 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6345 6346 vcpu->arch.nmi_injected = false; 6347 kvm_clear_exception_queue(vcpu); 6348 kvm_clear_interrupt_queue(vcpu); 6349 6350 if (!idtv_info_valid) 6351 return; 6352 6353 kvm_make_request(KVM_REQ_EVENT, vcpu); 6354 6355 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6356 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6357 6358 switch (type) { 6359 case INTR_TYPE_NMI_INTR: 6360 vcpu->arch.nmi_injected = true; 6361 /* 6362 * SDM 3: 27.7.1.2 (September 2008) 6363 * Clear bit "block by NMI" before VM entry if a NMI 6364 * delivery faulted. 6365 */ 6366 vmx_set_nmi_mask(vcpu, false); 6367 break; 6368 case INTR_TYPE_SOFT_EXCEPTION: 6369 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6370 /* fall through */ 6371 case INTR_TYPE_HARD_EXCEPTION: 6372 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6373 u32 err = vmcs_read32(error_code_field); 6374 kvm_requeue_exception_e(vcpu, vector, err); 6375 } else 6376 kvm_requeue_exception(vcpu, vector); 6377 break; 6378 case INTR_TYPE_SOFT_INTR: 6379 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6380 /* fall through */ 6381 case INTR_TYPE_EXT_INTR: 6382 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6383 break; 6384 default: 6385 break; 6386 } 6387 } 6388 6389 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6390 { 6391 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6392 VM_EXIT_INSTRUCTION_LEN, 6393 IDT_VECTORING_ERROR_CODE); 6394 } 6395 6396 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6397 { 6398 __vmx_complete_interrupts(vcpu, 6399 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6400 VM_ENTRY_INSTRUCTION_LEN, 6401 VM_ENTRY_EXCEPTION_ERROR_CODE); 6402 6403 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6404 } 6405 6406 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6407 { 6408 int i, nr_msrs; 6409 struct perf_guest_switch_msr *msrs; 6410 6411 msrs = perf_guest_get_msrs(&nr_msrs); 6412 6413 if (!msrs) 6414 return; 6415 6416 for (i = 0; i < nr_msrs; i++) 6417 if (msrs[i].host == msrs[i].guest) 6418 clear_atomic_switch_msr(vmx, msrs[i].msr); 6419 else 6420 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6421 msrs[i].host, false); 6422 } 6423 6424 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6425 { 6426 u32 host_umwait_control; 6427 6428 if (!vmx_has_waitpkg(vmx)) 6429 return; 6430 6431 host_umwait_control = get_umwait_control_msr(); 6432 6433 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6434 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6435 vmx->msr_ia32_umwait_control, 6436 host_umwait_control, false); 6437 else 6438 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6439 } 6440 6441 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6442 { 6443 struct vcpu_vmx *vmx = to_vmx(vcpu); 6444 u64 tscl; 6445 u32 delta_tsc; 6446 6447 if (vmx->req_immediate_exit) { 6448 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6449 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6450 } else if (vmx->hv_deadline_tsc != -1) { 6451 tscl = rdtsc(); 6452 if (vmx->hv_deadline_tsc > tscl) 6453 /* set_hv_timer ensures the delta fits in 32-bits */ 6454 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6455 cpu_preemption_timer_multi); 6456 else 6457 delta_tsc = 0; 6458 6459 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6460 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6461 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6462 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6463 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6464 } 6465 } 6466 6467 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6468 { 6469 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6470 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6471 vmcs_writel(HOST_RSP, host_rsp); 6472 } 6473 } 6474 6475 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6476 6477 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6478 { 6479 struct vcpu_vmx *vmx = to_vmx(vcpu); 6480 unsigned long cr3, cr4; 6481 6482 /* Record the guest's net vcpu time for enforced NMI injections. */ 6483 if (unlikely(!enable_vnmi && 6484 vmx->loaded_vmcs->soft_vnmi_blocked)) 6485 vmx->loaded_vmcs->entry_time = ktime_get(); 6486 6487 /* Don't enter VMX if guest state is invalid, let the exit handler 6488 start emulation until we arrive back to a valid state */ 6489 if (vmx->emulation_required) 6490 return; 6491 6492 if (vmx->ple_window_dirty) { 6493 vmx->ple_window_dirty = false; 6494 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6495 } 6496 6497 if (vmx->nested.need_vmcs12_to_shadow_sync) 6498 nested_sync_vmcs12_to_shadow(vcpu); 6499 6500 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) 6501 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6502 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) 6503 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6504 6505 cr3 = __get_current_cr3_fast(); 6506 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6507 vmcs_writel(HOST_CR3, cr3); 6508 vmx->loaded_vmcs->host_state.cr3 = cr3; 6509 } 6510 6511 cr4 = cr4_read_shadow(); 6512 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6513 vmcs_writel(HOST_CR4, cr4); 6514 vmx->loaded_vmcs->host_state.cr4 = cr4; 6515 } 6516 6517 /* When single-stepping over STI and MOV SS, we must clear the 6518 * corresponding interruptibility bits in the guest state. Otherwise 6519 * vmentry fails as it then expects bit 14 (BS) in pending debug 6520 * exceptions being set, but that's not correct for the guest debugging 6521 * case. */ 6522 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6523 vmx_set_interrupt_shadow(vcpu, 0); 6524 6525 kvm_load_guest_xcr0(vcpu); 6526 6527 if (static_cpu_has(X86_FEATURE_PKU) && 6528 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6529 vcpu->arch.pkru != vmx->host_pkru) 6530 __write_pkru(vcpu->arch.pkru); 6531 6532 pt_guest_enter(vmx); 6533 6534 atomic_switch_perf_msrs(vmx); 6535 atomic_switch_umwait_control_msr(vmx); 6536 6537 if (enable_preemption_timer) 6538 vmx_update_hv_timer(vcpu); 6539 6540 if (lapic_in_kernel(vcpu) && 6541 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6542 kvm_wait_lapic_expire(vcpu); 6543 6544 /* 6545 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6546 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6547 * is no need to worry about the conditional branch over the wrmsr 6548 * being speculatively taken. 6549 */ 6550 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6551 6552 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6553 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6554 vmx_l1d_flush(vcpu); 6555 else if (static_branch_unlikely(&mds_user_clear)) 6556 mds_clear_cpu_buffers(); 6557 6558 if (vcpu->arch.cr2 != read_cr2()) 6559 write_cr2(vcpu->arch.cr2); 6560 6561 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6562 vmx->loaded_vmcs->launched); 6563 6564 vcpu->arch.cr2 = read_cr2(); 6565 6566 /* 6567 * We do not use IBRS in the kernel. If this vCPU has used the 6568 * SPEC_CTRL MSR it may have left it on; save the value and 6569 * turn it off. This is much more efficient than blindly adding 6570 * it to the atomic save/restore list. Especially as the former 6571 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6572 * 6573 * For non-nested case: 6574 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6575 * save it. 6576 * 6577 * For nested case: 6578 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6579 * save it. 6580 */ 6581 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6582 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6583 6584 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6585 6586 /* All fields are clean at this point */ 6587 if (static_branch_unlikely(&enable_evmcs)) 6588 current_evmcs->hv_clean_fields |= 6589 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6590 6591 if (static_branch_unlikely(&enable_evmcs)) 6592 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6593 6594 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6595 if (vmx->host_debugctlmsr) 6596 update_debugctlmsr(vmx->host_debugctlmsr); 6597 6598 #ifndef CONFIG_X86_64 6599 /* 6600 * The sysexit path does not restore ds/es, so we must set them to 6601 * a reasonable value ourselves. 6602 * 6603 * We can't defer this to vmx_prepare_switch_to_host() since that 6604 * function may be executed in interrupt context, which saves and 6605 * restore segments around it, nullifying its effect. 6606 */ 6607 loadsegment(ds, __USER_DS); 6608 loadsegment(es, __USER_DS); 6609 #endif 6610 6611 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6612 | (1 << VCPU_EXREG_RFLAGS) 6613 | (1 << VCPU_EXREG_PDPTR) 6614 | (1 << VCPU_EXREG_SEGMENTS) 6615 | (1 << VCPU_EXREG_CR3)); 6616 vcpu->arch.regs_dirty = 0; 6617 6618 pt_guest_exit(vmx); 6619 6620 /* 6621 * eager fpu is enabled if PKEY is supported and CR4 is switched 6622 * back on host, so it is safe to read guest PKRU from current 6623 * XSAVE. 6624 */ 6625 if (static_cpu_has(X86_FEATURE_PKU) && 6626 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6627 vcpu->arch.pkru = rdpkru(); 6628 if (vcpu->arch.pkru != vmx->host_pkru) 6629 __write_pkru(vmx->host_pkru); 6630 } 6631 6632 kvm_put_guest_xcr0(vcpu); 6633 6634 vmx->nested.nested_run_pending = 0; 6635 vmx->idt_vectoring_info = 0; 6636 6637 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6638 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6639 kvm_machine_check(); 6640 6641 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6642 return; 6643 6644 vmx->loaded_vmcs->launched = 1; 6645 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6646 6647 vmx_recover_nmi_blocking(vmx); 6648 vmx_complete_interrupts(vmx); 6649 } 6650 6651 static struct kvm *vmx_vm_alloc(void) 6652 { 6653 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6654 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6655 PAGE_KERNEL); 6656 return &kvm_vmx->kvm; 6657 } 6658 6659 static void vmx_vm_free(struct kvm *kvm) 6660 { 6661 kfree(kvm->arch.hyperv.hv_pa_pg); 6662 vfree(to_kvm_vmx(kvm)); 6663 } 6664 6665 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6666 { 6667 struct vcpu_vmx *vmx = to_vmx(vcpu); 6668 6669 if (enable_pml) 6670 vmx_destroy_pml_buffer(vmx); 6671 free_vpid(vmx->vpid); 6672 nested_vmx_free_vcpu(vcpu); 6673 free_loaded_vmcs(vmx->loaded_vmcs); 6674 kfree(vmx->guest_msrs); 6675 kvm_vcpu_uninit(vcpu); 6676 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); 6677 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); 6678 kmem_cache_free(kvm_vcpu_cache, vmx); 6679 } 6680 6681 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) 6682 { 6683 int err; 6684 struct vcpu_vmx *vmx; 6685 unsigned long *msr_bitmap; 6686 int cpu; 6687 6688 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0, 6689 "struct kvm_vcpu must be at offset 0 for arch usercopy region"); 6690 6691 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT); 6692 if (!vmx) 6693 return ERR_PTR(-ENOMEM); 6694 6695 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 6696 GFP_KERNEL_ACCOUNT); 6697 if (!vmx->vcpu.arch.user_fpu) { 6698 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n"); 6699 err = -ENOMEM; 6700 goto free_partial_vcpu; 6701 } 6702 6703 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 6704 GFP_KERNEL_ACCOUNT); 6705 if (!vmx->vcpu.arch.guest_fpu) { 6706 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); 6707 err = -ENOMEM; 6708 goto free_user_fpu; 6709 } 6710 6711 vmx->vpid = allocate_vpid(); 6712 6713 err = kvm_vcpu_init(&vmx->vcpu, kvm, id); 6714 if (err) 6715 goto free_vcpu; 6716 6717 err = -ENOMEM; 6718 6719 /* 6720 * If PML is turned on, failure on enabling PML just results in failure 6721 * of creating the vcpu, therefore we can simplify PML logic (by 6722 * avoiding dealing with cases, such as enabling PML partially on vcpus 6723 * for the guest, etc. 6724 */ 6725 if (enable_pml) { 6726 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6727 if (!vmx->pml_pg) 6728 goto uninit_vcpu; 6729 } 6730 6731 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT); 6732 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) 6733 > PAGE_SIZE); 6734 6735 if (!vmx->guest_msrs) 6736 goto free_pml; 6737 6738 err = alloc_loaded_vmcs(&vmx->vmcs01); 6739 if (err < 0) 6740 goto free_msrs; 6741 6742 msr_bitmap = vmx->vmcs01.msr_bitmap; 6743 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6744 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6745 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6746 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6747 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6748 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6749 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6750 if (kvm_cstate_in_guest(kvm)) { 6751 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6752 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6753 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6754 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6755 } 6756 vmx->msr_bitmap_mode = 0; 6757 6758 vmx->loaded_vmcs = &vmx->vmcs01; 6759 cpu = get_cpu(); 6760 vmx_vcpu_load(&vmx->vcpu, cpu); 6761 vmx->vcpu.cpu = cpu; 6762 vmx_vcpu_setup(vmx); 6763 vmx_vcpu_put(&vmx->vcpu); 6764 put_cpu(); 6765 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { 6766 err = alloc_apic_access_page(kvm); 6767 if (err) 6768 goto free_vmcs; 6769 } 6770 6771 if (enable_ept && !enable_unrestricted_guest) { 6772 err = init_rmode_identity_map(kvm); 6773 if (err) 6774 goto free_vmcs; 6775 } 6776 6777 if (nested) 6778 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6779 vmx_capability.ept, 6780 kvm_vcpu_apicv_active(&vmx->vcpu)); 6781 else 6782 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6783 6784 vmx->nested.posted_intr_nv = -1; 6785 vmx->nested.current_vmptr = -1ull; 6786 6787 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; 6788 6789 /* 6790 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6791 * or POSTED_INTR_WAKEUP_VECTOR. 6792 */ 6793 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6794 vmx->pi_desc.sn = 1; 6795 6796 vmx->ept_pointer = INVALID_PAGE; 6797 6798 return &vmx->vcpu; 6799 6800 free_vmcs: 6801 free_loaded_vmcs(vmx->loaded_vmcs); 6802 free_msrs: 6803 kfree(vmx->guest_msrs); 6804 free_pml: 6805 vmx_destroy_pml_buffer(vmx); 6806 uninit_vcpu: 6807 kvm_vcpu_uninit(&vmx->vcpu); 6808 free_vcpu: 6809 free_vpid(vmx->vpid); 6810 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); 6811 free_user_fpu: 6812 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); 6813 free_partial_vcpu: 6814 kmem_cache_free(kvm_vcpu_cache, vmx); 6815 return ERR_PTR(err); 6816 } 6817 6818 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6819 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6820 6821 static int vmx_vm_init(struct kvm *kvm) 6822 { 6823 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6824 6825 if (!ple_gap) 6826 kvm->arch.pause_in_guest = true; 6827 6828 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6829 switch (l1tf_mitigation) { 6830 case L1TF_MITIGATION_OFF: 6831 case L1TF_MITIGATION_FLUSH_NOWARN: 6832 /* 'I explicitly don't care' is set */ 6833 break; 6834 case L1TF_MITIGATION_FLUSH: 6835 case L1TF_MITIGATION_FLUSH_NOSMT: 6836 case L1TF_MITIGATION_FULL: 6837 /* 6838 * Warn upon starting the first VM in a potentially 6839 * insecure environment. 6840 */ 6841 if (sched_smt_active()) 6842 pr_warn_once(L1TF_MSG_SMT); 6843 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6844 pr_warn_once(L1TF_MSG_L1D); 6845 break; 6846 case L1TF_MITIGATION_FULL_FORCE: 6847 /* Flush is enforced */ 6848 break; 6849 } 6850 } 6851 return 0; 6852 } 6853 6854 static int __init vmx_check_processor_compat(void) 6855 { 6856 struct vmcs_config vmcs_conf; 6857 struct vmx_capability vmx_cap; 6858 6859 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6860 return -EIO; 6861 if (nested) 6862 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept, 6863 enable_apicv); 6864 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6865 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6866 smp_processor_id()); 6867 return -EIO; 6868 } 6869 return 0; 6870 } 6871 6872 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6873 { 6874 u8 cache; 6875 u64 ipat = 0; 6876 6877 /* For VT-d and EPT combination 6878 * 1. MMIO: always map as UC 6879 * 2. EPT with VT-d: 6880 * a. VT-d without snooping control feature: can't guarantee the 6881 * result, try to trust guest. 6882 * b. VT-d with snooping control feature: snooping control feature of 6883 * VT-d engine can guarantee the cache correctness. Just set it 6884 * to WB to keep consistent with host. So the same as item 3. 6885 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6886 * consistent with host MTRR 6887 */ 6888 if (is_mmio) { 6889 cache = MTRR_TYPE_UNCACHABLE; 6890 goto exit; 6891 } 6892 6893 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6894 ipat = VMX_EPT_IPAT_BIT; 6895 cache = MTRR_TYPE_WRBACK; 6896 goto exit; 6897 } 6898 6899 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6900 ipat = VMX_EPT_IPAT_BIT; 6901 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6902 cache = MTRR_TYPE_WRBACK; 6903 else 6904 cache = MTRR_TYPE_UNCACHABLE; 6905 goto exit; 6906 } 6907 6908 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6909 6910 exit: 6911 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6912 } 6913 6914 static int vmx_get_lpage_level(void) 6915 { 6916 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6917 return PT_DIRECTORY_LEVEL; 6918 else 6919 /* For shadow and EPT supported 1GB page */ 6920 return PT_PDPE_LEVEL; 6921 } 6922 6923 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6924 { 6925 /* 6926 * These bits in the secondary execution controls field 6927 * are dynamic, the others are mostly based on the hypervisor 6928 * architecture and the guest's CPUID. Do not touch the 6929 * dynamic bits. 6930 */ 6931 u32 mask = 6932 SECONDARY_EXEC_SHADOW_VMCS | 6933 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6934 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6935 SECONDARY_EXEC_DESC; 6936 6937 u32 new_ctl = vmx->secondary_exec_control; 6938 u32 cur_ctl = secondary_exec_controls_get(vmx); 6939 6940 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6941 } 6942 6943 /* 6944 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6945 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6946 */ 6947 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6948 { 6949 struct vcpu_vmx *vmx = to_vmx(vcpu); 6950 struct kvm_cpuid_entry2 *entry; 6951 6952 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6953 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6954 6955 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6956 if (entry && (entry->_reg & (_cpuid_mask))) \ 6957 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6958 } while (0) 6959 6960 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6961 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); 6962 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); 6963 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); 6964 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); 6965 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); 6966 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); 6967 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); 6968 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); 6969 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); 6970 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); 6971 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); 6972 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); 6973 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); 6974 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); 6975 6976 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6977 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); 6978 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); 6979 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); 6980 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); 6981 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); 6982 6983 #undef cr4_fixed1_update 6984 } 6985 6986 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 6987 { 6988 struct vcpu_vmx *vmx = to_vmx(vcpu); 6989 6990 if (kvm_mpx_supported()) { 6991 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 6992 6993 if (mpx_enabled) { 6994 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 6995 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 6996 } else { 6997 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 6998 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 6999 } 7000 } 7001 } 7002 7003 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7004 { 7005 struct vcpu_vmx *vmx = to_vmx(vcpu); 7006 struct kvm_cpuid_entry2 *best = NULL; 7007 int i; 7008 7009 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7010 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7011 if (!best) 7012 return; 7013 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7014 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7015 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7016 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7017 } 7018 7019 /* Get the number of configurable Address Ranges for filtering */ 7020 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7021 PT_CAP_num_address_ranges); 7022 7023 /* Initialize and clear the no dependency bits */ 7024 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7025 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7026 7027 /* 7028 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7029 * will inject an #GP 7030 */ 7031 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7032 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7033 7034 /* 7035 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7036 * PSBFreq can be set 7037 */ 7038 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7039 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7040 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7041 7042 /* 7043 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7044 * MTCFreq can be set 7045 */ 7046 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7047 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7048 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7049 7050 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7051 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7052 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7053 RTIT_CTL_PTW_EN); 7054 7055 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7056 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7057 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7058 7059 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7060 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7061 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7062 7063 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7064 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7065 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7066 7067 /* unmask address range configure area */ 7068 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7069 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7070 } 7071 7072 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7073 { 7074 struct vcpu_vmx *vmx = to_vmx(vcpu); 7075 7076 if (cpu_has_secondary_exec_ctrls()) { 7077 vmx_compute_secondary_exec_control(vmx); 7078 vmcs_set_secondary_exec_control(vmx); 7079 } 7080 7081 if (nested_vmx_allowed(vcpu)) 7082 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7083 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 7084 else 7085 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7086 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 7087 7088 if (nested_vmx_allowed(vcpu)) { 7089 nested_vmx_cr_fixed1_bits_update(vcpu); 7090 nested_vmx_entry_exit_ctls_update(vcpu); 7091 } 7092 7093 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7094 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7095 update_intel_pt_cfg(vcpu); 7096 } 7097 7098 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 7099 { 7100 if (func == 1 && nested) 7101 entry->ecx |= bit(X86_FEATURE_VMX); 7102 } 7103 7104 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7105 { 7106 to_vmx(vcpu)->req_immediate_exit = true; 7107 } 7108 7109 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7110 struct x86_instruction_info *info, 7111 enum x86_intercept_stage stage) 7112 { 7113 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7114 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7115 7116 /* 7117 * RDPID causes #UD if disabled through secondary execution controls. 7118 * Because it is marked as EmulateOnUD, we need to intercept it here. 7119 */ 7120 if (info->intercept == x86_intercept_rdtscp && 7121 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7122 ctxt->exception.vector = UD_VECTOR; 7123 ctxt->exception.error_code_valid = false; 7124 return X86EMUL_PROPAGATE_FAULT; 7125 } 7126 7127 /* TODO: check more intercepts... */ 7128 return X86EMUL_CONTINUE; 7129 } 7130 7131 #ifdef CONFIG_X86_64 7132 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7133 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7134 u64 divisor, u64 *result) 7135 { 7136 u64 low = a << shift, high = a >> (64 - shift); 7137 7138 /* To avoid the overflow on divq */ 7139 if (high >= divisor) 7140 return 1; 7141 7142 /* Low hold the result, high hold rem which is discarded */ 7143 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7144 "rm" (divisor), "0" (low), "1" (high)); 7145 *result = low; 7146 7147 return 0; 7148 } 7149 7150 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7151 bool *expired) 7152 { 7153 struct vcpu_vmx *vmx; 7154 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7155 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7156 7157 if (kvm_mwait_in_guest(vcpu->kvm) || 7158 kvm_can_post_timer_interrupt(vcpu)) 7159 return -EOPNOTSUPP; 7160 7161 vmx = to_vmx(vcpu); 7162 tscl = rdtsc(); 7163 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7164 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7165 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7166 ktimer->timer_advance_ns); 7167 7168 if (delta_tsc > lapic_timer_advance_cycles) 7169 delta_tsc -= lapic_timer_advance_cycles; 7170 else 7171 delta_tsc = 0; 7172 7173 /* Convert to host delta tsc if tsc scaling is enabled */ 7174 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7175 delta_tsc && u64_shl_div_u64(delta_tsc, 7176 kvm_tsc_scaling_ratio_frac_bits, 7177 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7178 return -ERANGE; 7179 7180 /* 7181 * If the delta tsc can't fit in the 32 bit after the multi shift, 7182 * we can't use the preemption timer. 7183 * It's possible that it fits on later vmentries, but checking 7184 * on every vmentry is costly so we just use an hrtimer. 7185 */ 7186 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7187 return -ERANGE; 7188 7189 vmx->hv_deadline_tsc = tscl + delta_tsc; 7190 *expired = !delta_tsc; 7191 return 0; 7192 } 7193 7194 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7195 { 7196 to_vmx(vcpu)->hv_deadline_tsc = -1; 7197 } 7198 #endif 7199 7200 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7201 { 7202 if (!kvm_pause_in_guest(vcpu->kvm)) 7203 shrink_ple_window(vcpu); 7204 } 7205 7206 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7207 struct kvm_memory_slot *slot) 7208 { 7209 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7210 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7211 } 7212 7213 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7214 struct kvm_memory_slot *slot) 7215 { 7216 kvm_mmu_slot_set_dirty(kvm, slot); 7217 } 7218 7219 static void vmx_flush_log_dirty(struct kvm *kvm) 7220 { 7221 kvm_flush_pml_buffers(kvm); 7222 } 7223 7224 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7225 { 7226 struct vmcs12 *vmcs12; 7227 struct vcpu_vmx *vmx = to_vmx(vcpu); 7228 gpa_t gpa, dst; 7229 7230 if (is_guest_mode(vcpu)) { 7231 WARN_ON_ONCE(vmx->nested.pml_full); 7232 7233 /* 7234 * Check if PML is enabled for the nested guest. 7235 * Whether eptp bit 6 is set is already checked 7236 * as part of A/D emulation. 7237 */ 7238 vmcs12 = get_vmcs12(vcpu); 7239 if (!nested_cpu_has_pml(vmcs12)) 7240 return 0; 7241 7242 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7243 vmx->nested.pml_full = true; 7244 return 1; 7245 } 7246 7247 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7248 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7249 7250 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7251 offset_in_page(dst), sizeof(gpa))) 7252 return 0; 7253 7254 vmcs12->guest_pml_index--; 7255 } 7256 7257 return 0; 7258 } 7259 7260 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7261 struct kvm_memory_slot *memslot, 7262 gfn_t offset, unsigned long mask) 7263 { 7264 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7265 } 7266 7267 static void __pi_post_block(struct kvm_vcpu *vcpu) 7268 { 7269 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7270 struct pi_desc old, new; 7271 unsigned int dest; 7272 7273 do { 7274 old.control = new.control = pi_desc->control; 7275 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7276 "Wakeup handler not enabled while the VCPU is blocked\n"); 7277 7278 dest = cpu_physical_id(vcpu->cpu); 7279 7280 if (x2apic_enabled()) 7281 new.ndst = dest; 7282 else 7283 new.ndst = (dest << 8) & 0xFF00; 7284 7285 /* set 'NV' to 'notification vector' */ 7286 new.nv = POSTED_INTR_VECTOR; 7287 } while (cmpxchg64(&pi_desc->control, old.control, 7288 new.control) != old.control); 7289 7290 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7291 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7292 list_del(&vcpu->blocked_vcpu_list); 7293 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7294 vcpu->pre_pcpu = -1; 7295 } 7296 } 7297 7298 /* 7299 * This routine does the following things for vCPU which is going 7300 * to be blocked if VT-d PI is enabled. 7301 * - Store the vCPU to the wakeup list, so when interrupts happen 7302 * we can find the right vCPU to wake up. 7303 * - Change the Posted-interrupt descriptor as below: 7304 * 'NDST' <-- vcpu->pre_pcpu 7305 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7306 * - If 'ON' is set during this process, which means at least one 7307 * interrupt is posted for this vCPU, we cannot block it, in 7308 * this case, return 1, otherwise, return 0. 7309 * 7310 */ 7311 static int pi_pre_block(struct kvm_vcpu *vcpu) 7312 { 7313 unsigned int dest; 7314 struct pi_desc old, new; 7315 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7316 7317 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7318 !irq_remapping_cap(IRQ_POSTING_CAP) || 7319 !kvm_vcpu_apicv_active(vcpu)) 7320 return 0; 7321 7322 WARN_ON(irqs_disabled()); 7323 local_irq_disable(); 7324 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7325 vcpu->pre_pcpu = vcpu->cpu; 7326 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7327 list_add_tail(&vcpu->blocked_vcpu_list, 7328 &per_cpu(blocked_vcpu_on_cpu, 7329 vcpu->pre_pcpu)); 7330 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7331 } 7332 7333 do { 7334 old.control = new.control = pi_desc->control; 7335 7336 WARN((pi_desc->sn == 1), 7337 "Warning: SN field of posted-interrupts " 7338 "is set before blocking\n"); 7339 7340 /* 7341 * Since vCPU can be preempted during this process, 7342 * vcpu->cpu could be different with pre_pcpu, we 7343 * need to set pre_pcpu as the destination of wakeup 7344 * notification event, then we can find the right vCPU 7345 * to wakeup in wakeup handler if interrupts happen 7346 * when the vCPU is in blocked state. 7347 */ 7348 dest = cpu_physical_id(vcpu->pre_pcpu); 7349 7350 if (x2apic_enabled()) 7351 new.ndst = dest; 7352 else 7353 new.ndst = (dest << 8) & 0xFF00; 7354 7355 /* set 'NV' to 'wakeup vector' */ 7356 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7357 } while (cmpxchg64(&pi_desc->control, old.control, 7358 new.control) != old.control); 7359 7360 /* We should not block the vCPU if an interrupt is posted for it. */ 7361 if (pi_test_on(pi_desc) == 1) 7362 __pi_post_block(vcpu); 7363 7364 local_irq_enable(); 7365 return (vcpu->pre_pcpu == -1); 7366 } 7367 7368 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7369 { 7370 if (pi_pre_block(vcpu)) 7371 return 1; 7372 7373 if (kvm_lapic_hv_timer_in_use(vcpu)) 7374 kvm_lapic_switch_to_sw_timer(vcpu); 7375 7376 return 0; 7377 } 7378 7379 static void pi_post_block(struct kvm_vcpu *vcpu) 7380 { 7381 if (vcpu->pre_pcpu == -1) 7382 return; 7383 7384 WARN_ON(irqs_disabled()); 7385 local_irq_disable(); 7386 __pi_post_block(vcpu); 7387 local_irq_enable(); 7388 } 7389 7390 static void vmx_post_block(struct kvm_vcpu *vcpu) 7391 { 7392 if (kvm_x86_ops->set_hv_timer) 7393 kvm_lapic_switch_to_hv_timer(vcpu); 7394 7395 pi_post_block(vcpu); 7396 } 7397 7398 /* 7399 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7400 * 7401 * @kvm: kvm 7402 * @host_irq: host irq of the interrupt 7403 * @guest_irq: gsi of the interrupt 7404 * @set: set or unset PI 7405 * returns 0 on success, < 0 on failure 7406 */ 7407 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7408 uint32_t guest_irq, bool set) 7409 { 7410 struct kvm_kernel_irq_routing_entry *e; 7411 struct kvm_irq_routing_table *irq_rt; 7412 struct kvm_lapic_irq irq; 7413 struct kvm_vcpu *vcpu; 7414 struct vcpu_data vcpu_info; 7415 int idx, ret = 0; 7416 7417 if (!kvm_arch_has_assigned_device(kvm) || 7418 !irq_remapping_cap(IRQ_POSTING_CAP) || 7419 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7420 return 0; 7421 7422 idx = srcu_read_lock(&kvm->irq_srcu); 7423 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7424 if (guest_irq >= irq_rt->nr_rt_entries || 7425 hlist_empty(&irq_rt->map[guest_irq])) { 7426 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7427 guest_irq, irq_rt->nr_rt_entries); 7428 goto out; 7429 } 7430 7431 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7432 if (e->type != KVM_IRQ_ROUTING_MSI) 7433 continue; 7434 /* 7435 * VT-d PI cannot support posting multicast/broadcast 7436 * interrupts to a vCPU, we still use interrupt remapping 7437 * for these kind of interrupts. 7438 * 7439 * For lowest-priority interrupts, we only support 7440 * those with single CPU as the destination, e.g. user 7441 * configures the interrupts via /proc/irq or uses 7442 * irqbalance to make the interrupts single-CPU. 7443 * 7444 * We will support full lowest-priority interrupt later. 7445 * 7446 * In addition, we can only inject generic interrupts using 7447 * the PI mechanism, refuse to route others through it. 7448 */ 7449 7450 kvm_set_msi_irq(kvm, e, &irq); 7451 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7452 !kvm_irq_is_postable(&irq)) { 7453 /* 7454 * Make sure the IRTE is in remapped mode if 7455 * we don't handle it in posted mode. 7456 */ 7457 ret = irq_set_vcpu_affinity(host_irq, NULL); 7458 if (ret < 0) { 7459 printk(KERN_INFO 7460 "failed to back to remapped mode, irq: %u\n", 7461 host_irq); 7462 goto out; 7463 } 7464 7465 continue; 7466 } 7467 7468 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7469 vcpu_info.vector = irq.vector; 7470 7471 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7472 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7473 7474 if (set) 7475 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7476 else 7477 ret = irq_set_vcpu_affinity(host_irq, NULL); 7478 7479 if (ret < 0) { 7480 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7481 __func__); 7482 goto out; 7483 } 7484 } 7485 7486 ret = 0; 7487 out: 7488 srcu_read_unlock(&kvm->irq_srcu, idx); 7489 return ret; 7490 } 7491 7492 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7493 { 7494 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7495 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7496 FEATURE_CONTROL_LMCE; 7497 else 7498 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7499 ~FEATURE_CONTROL_LMCE; 7500 } 7501 7502 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7503 { 7504 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7505 if (to_vmx(vcpu)->nested.nested_run_pending) 7506 return 0; 7507 return 1; 7508 } 7509 7510 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7511 { 7512 struct vcpu_vmx *vmx = to_vmx(vcpu); 7513 7514 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7515 if (vmx->nested.smm.guest_mode) 7516 nested_vmx_vmexit(vcpu, -1, 0, 0); 7517 7518 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7519 vmx->nested.vmxon = false; 7520 vmx_clear_hlt(vcpu); 7521 return 0; 7522 } 7523 7524 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7525 { 7526 struct vcpu_vmx *vmx = to_vmx(vcpu); 7527 int ret; 7528 7529 if (vmx->nested.smm.vmxon) { 7530 vmx->nested.vmxon = true; 7531 vmx->nested.smm.vmxon = false; 7532 } 7533 7534 if (vmx->nested.smm.guest_mode) { 7535 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7536 if (ret) 7537 return ret; 7538 7539 vmx->nested.smm.guest_mode = false; 7540 } 7541 return 0; 7542 } 7543 7544 static int enable_smi_window(struct kvm_vcpu *vcpu) 7545 { 7546 return 0; 7547 } 7548 7549 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7550 { 7551 return false; 7552 } 7553 7554 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7555 { 7556 return to_vmx(vcpu)->nested.vmxon; 7557 } 7558 7559 static __init int hardware_setup(void) 7560 { 7561 unsigned long host_bndcfgs; 7562 struct desc_ptr dt; 7563 int r, i; 7564 7565 rdmsrl_safe(MSR_EFER, &host_efer); 7566 7567 store_idt(&dt); 7568 host_idt_base = dt.address; 7569 7570 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7571 kvm_define_shared_msr(i, vmx_msr_index[i]); 7572 7573 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7574 return -EIO; 7575 7576 if (boot_cpu_has(X86_FEATURE_NX)) 7577 kvm_enable_efer_bits(EFER_NX); 7578 7579 if (boot_cpu_has(X86_FEATURE_MPX)) { 7580 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7581 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7582 } 7583 7584 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7585 rdmsrl(MSR_IA32_XSS, host_xss); 7586 7587 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7588 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7589 enable_vpid = 0; 7590 7591 if (!cpu_has_vmx_ept() || 7592 !cpu_has_vmx_ept_4levels() || 7593 !cpu_has_vmx_ept_mt_wb() || 7594 !cpu_has_vmx_invept_global()) 7595 enable_ept = 0; 7596 7597 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7598 enable_ept_ad_bits = 0; 7599 7600 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7601 enable_unrestricted_guest = 0; 7602 7603 if (!cpu_has_vmx_flexpriority()) 7604 flexpriority_enabled = 0; 7605 7606 if (!cpu_has_virtual_nmis()) 7607 enable_vnmi = 0; 7608 7609 /* 7610 * set_apic_access_page_addr() is used to reload apic access 7611 * page upon invalidation. No need to do anything if not 7612 * using the APIC_ACCESS_ADDR VMCS field. 7613 */ 7614 if (!flexpriority_enabled) 7615 kvm_x86_ops->set_apic_access_page_addr = NULL; 7616 7617 if (!cpu_has_vmx_tpr_shadow()) 7618 kvm_x86_ops->update_cr8_intercept = NULL; 7619 7620 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7621 kvm_disable_largepages(); 7622 7623 #if IS_ENABLED(CONFIG_HYPERV) 7624 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7625 && enable_ept) { 7626 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7627 kvm_x86_ops->tlb_remote_flush_with_range = 7628 hv_remote_flush_tlb_with_range; 7629 } 7630 #endif 7631 7632 if (!cpu_has_vmx_ple()) { 7633 ple_gap = 0; 7634 ple_window = 0; 7635 ple_window_grow = 0; 7636 ple_window_max = 0; 7637 ple_window_shrink = 0; 7638 } 7639 7640 if (!cpu_has_vmx_apicv()) { 7641 enable_apicv = 0; 7642 kvm_x86_ops->sync_pir_to_irr = NULL; 7643 } 7644 7645 if (cpu_has_vmx_tsc_scaling()) { 7646 kvm_has_tsc_control = true; 7647 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7648 kvm_tsc_scaling_ratio_frac_bits = 48; 7649 } 7650 7651 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7652 7653 if (enable_ept) 7654 vmx_enable_tdp(); 7655 else 7656 kvm_disable_tdp(); 7657 7658 /* 7659 * Only enable PML when hardware supports PML feature, and both EPT 7660 * and EPT A/D bit features are enabled -- PML depends on them to work. 7661 */ 7662 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7663 enable_pml = 0; 7664 7665 if (!enable_pml) { 7666 kvm_x86_ops->slot_enable_log_dirty = NULL; 7667 kvm_x86_ops->slot_disable_log_dirty = NULL; 7668 kvm_x86_ops->flush_log_dirty = NULL; 7669 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7670 } 7671 7672 if (!cpu_has_vmx_preemption_timer()) 7673 enable_preemption_timer = false; 7674 7675 if (enable_preemption_timer) { 7676 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7677 u64 vmx_msr; 7678 7679 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7680 cpu_preemption_timer_multi = 7681 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7682 7683 if (tsc_khz) 7684 use_timer_freq = (u64)tsc_khz * 1000; 7685 use_timer_freq >>= cpu_preemption_timer_multi; 7686 7687 /* 7688 * KVM "disables" the preemption timer by setting it to its max 7689 * value. Don't use the timer if it might cause spurious exits 7690 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7691 */ 7692 if (use_timer_freq > 0xffffffffu / 10) 7693 enable_preemption_timer = false; 7694 } 7695 7696 if (!enable_preemption_timer) { 7697 kvm_x86_ops->set_hv_timer = NULL; 7698 kvm_x86_ops->cancel_hv_timer = NULL; 7699 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7700 } 7701 7702 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7703 7704 kvm_mce_cap_supported |= MCG_LMCE_P; 7705 7706 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7707 return -EINVAL; 7708 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7709 pt_mode = PT_MODE_SYSTEM; 7710 7711 if (nested) { 7712 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7713 vmx_capability.ept, enable_apicv); 7714 7715 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7716 if (r) 7717 return r; 7718 } 7719 7720 r = alloc_kvm_area(); 7721 if (r) 7722 nested_vmx_hardware_unsetup(); 7723 return r; 7724 } 7725 7726 static __exit void hardware_unsetup(void) 7727 { 7728 if (nested) 7729 nested_vmx_hardware_unsetup(); 7730 7731 free_kvm_area(); 7732 } 7733 7734 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7735 .cpu_has_kvm_support = cpu_has_kvm_support, 7736 .disabled_by_bios = vmx_disabled_by_bios, 7737 .hardware_setup = hardware_setup, 7738 .hardware_unsetup = hardware_unsetup, 7739 .check_processor_compatibility = vmx_check_processor_compat, 7740 .hardware_enable = hardware_enable, 7741 .hardware_disable = hardware_disable, 7742 .cpu_has_accelerated_tpr = report_flexpriority, 7743 .has_emulated_msr = vmx_has_emulated_msr, 7744 7745 .vm_init = vmx_vm_init, 7746 .vm_alloc = vmx_vm_alloc, 7747 .vm_free = vmx_vm_free, 7748 7749 .vcpu_create = vmx_create_vcpu, 7750 .vcpu_free = vmx_free_vcpu, 7751 .vcpu_reset = vmx_vcpu_reset, 7752 7753 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7754 .vcpu_load = vmx_vcpu_load, 7755 .vcpu_put = vmx_vcpu_put, 7756 7757 .update_bp_intercept = update_exception_bitmap, 7758 .get_msr_feature = vmx_get_msr_feature, 7759 .get_msr = vmx_get_msr, 7760 .set_msr = vmx_set_msr, 7761 .get_segment_base = vmx_get_segment_base, 7762 .get_segment = vmx_get_segment, 7763 .set_segment = vmx_set_segment, 7764 .get_cpl = vmx_get_cpl, 7765 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7766 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7767 .decache_cr3 = vmx_decache_cr3, 7768 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7769 .set_cr0 = vmx_set_cr0, 7770 .set_cr3 = vmx_set_cr3, 7771 .set_cr4 = vmx_set_cr4, 7772 .set_efer = vmx_set_efer, 7773 .get_idt = vmx_get_idt, 7774 .set_idt = vmx_set_idt, 7775 .get_gdt = vmx_get_gdt, 7776 .set_gdt = vmx_set_gdt, 7777 .get_dr6 = vmx_get_dr6, 7778 .set_dr6 = vmx_set_dr6, 7779 .set_dr7 = vmx_set_dr7, 7780 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7781 .cache_reg = vmx_cache_reg, 7782 .get_rflags = vmx_get_rflags, 7783 .set_rflags = vmx_set_rflags, 7784 7785 .tlb_flush = vmx_flush_tlb, 7786 .tlb_flush_gva = vmx_flush_tlb_gva, 7787 7788 .run = vmx_vcpu_run, 7789 .handle_exit = vmx_handle_exit, 7790 .skip_emulated_instruction = skip_emulated_instruction, 7791 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7792 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7793 .patch_hypercall = vmx_patch_hypercall, 7794 .set_irq = vmx_inject_irq, 7795 .set_nmi = vmx_inject_nmi, 7796 .queue_exception = vmx_queue_exception, 7797 .cancel_injection = vmx_cancel_injection, 7798 .interrupt_allowed = vmx_interrupt_allowed, 7799 .nmi_allowed = vmx_nmi_allowed, 7800 .get_nmi_mask = vmx_get_nmi_mask, 7801 .set_nmi_mask = vmx_set_nmi_mask, 7802 .enable_nmi_window = enable_nmi_window, 7803 .enable_irq_window = enable_irq_window, 7804 .update_cr8_intercept = update_cr8_intercept, 7805 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7806 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7807 .get_enable_apicv = vmx_get_enable_apicv, 7808 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7809 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7810 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7811 .hwapic_irr_update = vmx_hwapic_irr_update, 7812 .hwapic_isr_update = vmx_hwapic_isr_update, 7813 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7814 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7815 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7816 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7817 7818 .set_tss_addr = vmx_set_tss_addr, 7819 .set_identity_map_addr = vmx_set_identity_map_addr, 7820 .get_tdp_level = get_ept_level, 7821 .get_mt_mask = vmx_get_mt_mask, 7822 7823 .get_exit_info = vmx_get_exit_info, 7824 7825 .get_lpage_level = vmx_get_lpage_level, 7826 7827 .cpuid_update = vmx_cpuid_update, 7828 7829 .rdtscp_supported = vmx_rdtscp_supported, 7830 .invpcid_supported = vmx_invpcid_supported, 7831 7832 .set_supported_cpuid = vmx_set_supported_cpuid, 7833 7834 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7835 7836 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7837 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7838 7839 .set_tdp_cr3 = vmx_set_cr3, 7840 7841 .check_intercept = vmx_check_intercept, 7842 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7843 .mpx_supported = vmx_mpx_supported, 7844 .xsaves_supported = vmx_xsaves_supported, 7845 .umip_emulated = vmx_umip_emulated, 7846 .pt_supported = vmx_pt_supported, 7847 7848 .request_immediate_exit = vmx_request_immediate_exit, 7849 7850 .sched_in = vmx_sched_in, 7851 7852 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7853 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7854 .flush_log_dirty = vmx_flush_log_dirty, 7855 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7856 .write_log_dirty = vmx_write_pml_buffer, 7857 7858 .pre_block = vmx_pre_block, 7859 .post_block = vmx_post_block, 7860 7861 .pmu_ops = &intel_pmu_ops, 7862 7863 .update_pi_irte = vmx_update_pi_irte, 7864 7865 #ifdef CONFIG_X86_64 7866 .set_hv_timer = vmx_set_hv_timer, 7867 .cancel_hv_timer = vmx_cancel_hv_timer, 7868 #endif 7869 7870 .setup_mce = vmx_setup_mce, 7871 7872 .smi_allowed = vmx_smi_allowed, 7873 .pre_enter_smm = vmx_pre_enter_smm, 7874 .pre_leave_smm = vmx_pre_leave_smm, 7875 .enable_smi_window = enable_smi_window, 7876 7877 .check_nested_events = NULL, 7878 .get_nested_state = NULL, 7879 .set_nested_state = NULL, 7880 .get_vmcs12_pages = NULL, 7881 .nested_enable_evmcs = NULL, 7882 .nested_get_evmcs_version = NULL, 7883 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7884 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7885 }; 7886 7887 static void vmx_cleanup_l1d_flush(void) 7888 { 7889 if (vmx_l1d_flush_pages) { 7890 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7891 vmx_l1d_flush_pages = NULL; 7892 } 7893 /* Restore state so sysfs ignores VMX */ 7894 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 7895 } 7896 7897 static void vmx_exit(void) 7898 { 7899 #ifdef CONFIG_KEXEC_CORE 7900 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 7901 synchronize_rcu(); 7902 #endif 7903 7904 kvm_exit(); 7905 7906 #if IS_ENABLED(CONFIG_HYPERV) 7907 if (static_branch_unlikely(&enable_evmcs)) { 7908 int cpu; 7909 struct hv_vp_assist_page *vp_ap; 7910 /* 7911 * Reset everything to support using non-enlightened VMCS 7912 * access later (e.g. when we reload the module with 7913 * enlightened_vmcs=0) 7914 */ 7915 for_each_online_cpu(cpu) { 7916 vp_ap = hv_get_vp_assist_page(cpu); 7917 7918 if (!vp_ap) 7919 continue; 7920 7921 vp_ap->nested_control.features.directhypercall = 0; 7922 vp_ap->current_nested_vmcs = 0; 7923 vp_ap->enlighten_vmentry = 0; 7924 } 7925 7926 static_branch_disable(&enable_evmcs); 7927 } 7928 #endif 7929 vmx_cleanup_l1d_flush(); 7930 } 7931 module_exit(vmx_exit); 7932 7933 static int __init vmx_init(void) 7934 { 7935 int r; 7936 7937 #if IS_ENABLED(CONFIG_HYPERV) 7938 /* 7939 * Enlightened VMCS usage should be recommended and the host needs 7940 * to support eVMCS v1 or above. We can also disable eVMCS support 7941 * with module parameter. 7942 */ 7943 if (enlightened_vmcs && 7944 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 7945 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 7946 KVM_EVMCS_VERSION) { 7947 int cpu; 7948 7949 /* Check that we have assist pages on all online CPUs */ 7950 for_each_online_cpu(cpu) { 7951 if (!hv_get_vp_assist_page(cpu)) { 7952 enlightened_vmcs = false; 7953 break; 7954 } 7955 } 7956 7957 if (enlightened_vmcs) { 7958 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 7959 static_branch_enable(&enable_evmcs); 7960 } 7961 7962 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 7963 vmx_x86_ops.enable_direct_tlbflush 7964 = hv_enable_direct_tlbflush; 7965 7966 } else { 7967 enlightened_vmcs = false; 7968 } 7969 #endif 7970 7971 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 7972 __alignof__(struct vcpu_vmx), THIS_MODULE); 7973 if (r) 7974 return r; 7975 7976 /* 7977 * Must be called after kvm_init() so enable_ept is properly set 7978 * up. Hand the parameter mitigation value in which was stored in 7979 * the pre module init parser. If no parameter was given, it will 7980 * contain 'auto' which will be turned into the default 'cond' 7981 * mitigation mode. 7982 */ 7983 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 7984 if (r) { 7985 vmx_exit(); 7986 return r; 7987 } 7988 7989 #ifdef CONFIG_KEXEC_CORE 7990 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 7991 crash_vmclear_local_loaded_vmcss); 7992 #endif 7993 vmx_check_vmcs12_offsets(); 7994 7995 return 0; 7996 } 7997 module_init(vmx_init); 7998