1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/debugreg.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/io.h> 38 #include <asm/irq_remapping.h> 39 #include <asm/kexec.h> 40 #include <asm/perf_event.h> 41 #include <asm/mce.h> 42 #include <asm/mmu_context.h> 43 #include <asm/mshyperv.h> 44 #include <asm/spec-ctrl.h> 45 #include <asm/virtext.h> 46 #include <asm/vmx.h> 47 48 #include "capabilities.h" 49 #include "cpuid.h" 50 #include "evmcs.h" 51 #include "irq.h" 52 #include "kvm_cache_regs.h" 53 #include "lapic.h" 54 #include "mmu.h" 55 #include "nested.h" 56 #include "ops.h" 57 #include "pmu.h" 58 #include "trace.h" 59 #include "vmcs.h" 60 #include "vmcs12.h" 61 #include "vmx.h" 62 #include "x86.h" 63 64 MODULE_AUTHOR("Qumranet"); 65 MODULE_LICENSE("GPL"); 66 67 static const struct x86_cpu_id vmx_cpu_id[] = { 68 X86_FEATURE_MATCH(X86_FEATURE_VMX), 69 {} 70 }; 71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 72 73 bool __read_mostly enable_vpid = 1; 74 module_param_named(vpid, enable_vpid, bool, 0444); 75 76 static bool __read_mostly enable_vnmi = 1; 77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 78 79 bool __read_mostly flexpriority_enabled = 1; 80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 81 82 bool __read_mostly enable_ept = 1; 83 module_param_named(ept, enable_ept, bool, S_IRUGO); 84 85 bool __read_mostly enable_unrestricted_guest = 1; 86 module_param_named(unrestricted_guest, 87 enable_unrestricted_guest, bool, S_IRUGO); 88 89 bool __read_mostly enable_ept_ad_bits = 1; 90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 91 92 static bool __read_mostly emulate_invalid_guest_state = true; 93 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 94 95 static bool __read_mostly fasteoi = 1; 96 module_param(fasteoi, bool, S_IRUGO); 97 98 static bool __read_mostly enable_apicv = 1; 99 module_param(enable_apicv, bool, S_IRUGO); 100 101 /* 102 * If nested=1, nested virtualization is supported, i.e., guests may use 103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 104 * use VMX instructions. 105 */ 106 static bool __read_mostly nested = 1; 107 module_param(nested, bool, S_IRUGO); 108 109 bool __read_mostly enable_pml = 1; 110 module_param_named(pml, enable_pml, bool, S_IRUGO); 111 112 static bool __read_mostly dump_invalid_vmcs = 0; 113 module_param(dump_invalid_vmcs, bool, 0644); 114 115 #define MSR_BITMAP_MODE_X2APIC 1 116 #define MSR_BITMAP_MODE_X2APIC_APICV 2 117 118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 119 120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 121 static int __read_mostly cpu_preemption_timer_multi; 122 static bool __read_mostly enable_preemption_timer = 1; 123 #ifdef CONFIG_X86_64 124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 125 #endif 126 127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 129 #define KVM_VM_CR0_ALWAYS_ON \ 130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 132 #define KVM_CR4_GUEST_OWNED_BITS \ 133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 135 136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 139 140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 141 142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 145 RTIT_STATUS_BYTECNT)) 146 147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 149 150 /* 151 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 152 * ple_gap: upper bound on the amount of time between two successive 153 * executions of PAUSE in a loop. Also indicate if ple enabled. 154 * According to test, this time is usually smaller than 128 cycles. 155 * ple_window: upper bound on the amount of time a guest is allowed to execute 156 * in a PAUSE loop. Tests indicate that most spinlocks are held for 157 * less than 2^12 cycles 158 * Time is measured based on a counter that runs at the same rate as the TSC, 159 * refer SDM volume 3b section 21.6.13 & 22.1.3. 160 */ 161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 162 module_param(ple_gap, uint, 0444); 163 164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 165 module_param(ple_window, uint, 0444); 166 167 /* Default doubles per-vcpu window every exit. */ 168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 169 module_param(ple_window_grow, uint, 0444); 170 171 /* Default resets per-vcpu window every exit to ple_window. */ 172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 173 module_param(ple_window_shrink, uint, 0444); 174 175 /* Default is to compute the maximum so we can never overflow. */ 176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 177 module_param(ple_window_max, uint, 0444); 178 179 /* Default is SYSTEM mode, 1 for host-guest mode */ 180 int __read_mostly pt_mode = PT_MODE_SYSTEM; 181 module_param(pt_mode, int, S_IRUGO); 182 183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 185 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 186 187 /* Storage for pre module init parameter parsing */ 188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 189 190 static const struct { 191 const char *option; 192 bool for_parse; 193 } vmentry_l1d_param[] = { 194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 196 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 200 }; 201 202 #define L1D_CACHE_ORDER 4 203 static void *vmx_l1d_flush_pages; 204 205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 206 { 207 struct page *page; 208 unsigned int i; 209 210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 212 return 0; 213 } 214 215 if (!enable_ept) { 216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 217 return 0; 218 } 219 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 221 u64 msr; 222 223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 226 return 0; 227 } 228 } 229 230 /* If set to auto use the default l1tf mitigation method */ 231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 232 switch (l1tf_mitigation) { 233 case L1TF_MITIGATION_OFF: 234 l1tf = VMENTER_L1D_FLUSH_NEVER; 235 break; 236 case L1TF_MITIGATION_FLUSH_NOWARN: 237 case L1TF_MITIGATION_FLUSH: 238 case L1TF_MITIGATION_FLUSH_NOSMT: 239 l1tf = VMENTER_L1D_FLUSH_COND; 240 break; 241 case L1TF_MITIGATION_FULL: 242 case L1TF_MITIGATION_FULL_FORCE: 243 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 244 break; 245 } 246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 } 249 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 252 /* 253 * This allocation for vmx_l1d_flush_pages is not tied to a VM 254 * lifetime and so should not be charged to a memcg. 255 */ 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 257 if (!page) 258 return -ENOMEM; 259 vmx_l1d_flush_pages = page_address(page); 260 261 /* 262 * Initialize each page with a different pattern in 263 * order to protect against KSM in the nested 264 * virtualization case. 265 */ 266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 268 PAGE_SIZE); 269 } 270 } 271 272 l1tf_vmx_mitigation = l1tf; 273 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 275 static_branch_enable(&vmx_l1d_should_flush); 276 else 277 static_branch_disable(&vmx_l1d_should_flush); 278 279 if (l1tf == VMENTER_L1D_FLUSH_COND) 280 static_branch_enable(&vmx_l1d_flush_cond); 281 else 282 static_branch_disable(&vmx_l1d_flush_cond); 283 return 0; 284 } 285 286 static int vmentry_l1d_flush_parse(const char *s) 287 { 288 unsigned int i; 289 290 if (s) { 291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 292 if (vmentry_l1d_param[i].for_parse && 293 sysfs_streq(s, vmentry_l1d_param[i].option)) 294 return i; 295 } 296 } 297 return -EINVAL; 298 } 299 300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 301 { 302 int l1tf, ret; 303 304 l1tf = vmentry_l1d_flush_parse(s); 305 if (l1tf < 0) 306 return l1tf; 307 308 if (!boot_cpu_has(X86_BUG_L1TF)) 309 return 0; 310 311 /* 312 * Has vmx_init() run already? If not then this is the pre init 313 * parameter parsing. In that case just store the value and let 314 * vmx_init() do the proper setup after enable_ept has been 315 * established. 316 */ 317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 318 vmentry_l1d_flush_param = l1tf; 319 return 0; 320 } 321 322 mutex_lock(&vmx_l1d_flush_mutex); 323 ret = vmx_setup_l1d_flush(l1tf); 324 mutex_unlock(&vmx_l1d_flush_mutex); 325 return ret; 326 } 327 328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 329 { 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 331 return sprintf(s, "???\n"); 332 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 334 } 335 336 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 337 .set = vmentry_l1d_flush_set, 338 .get = vmentry_l1d_flush_get, 339 }; 340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 341 342 static bool guest_state_valid(struct kvm_vcpu *vcpu); 343 static u32 vmx_segment_access_rights(struct kvm_segment *var); 344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 345 u32 msr, int type); 346 347 void vmx_vmexit(void); 348 349 #define vmx_insn_failed(fmt...) \ 350 do { \ 351 WARN_ONCE(1, fmt); \ 352 pr_warn_ratelimited(fmt); \ 353 } while (0) 354 355 asmlinkage void vmread_error(unsigned long field, bool fault) 356 { 357 if (fault) 358 kvm_spurious_fault(); 359 else 360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 361 } 362 363 noinline void vmwrite_error(unsigned long field, unsigned long value) 364 { 365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 367 } 368 369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 370 { 371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 372 } 373 374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 375 { 376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 377 } 378 379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 380 { 381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 382 ext, vpid, gva); 383 } 384 385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 386 { 387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 388 ext, eptp, gpa); 389 } 390 391 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 392 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 393 /* 394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 396 */ 397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 398 399 /* 400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 401 * can find which vCPU should be waken up. 402 */ 403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 405 406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 407 static DEFINE_SPINLOCK(vmx_vpid_lock); 408 409 struct vmcs_config vmcs_config; 410 struct vmx_capability vmx_capability; 411 412 #define VMX_SEGMENT_FIELD(seg) \ 413 [VCPU_SREG_##seg] = { \ 414 .selector = GUEST_##seg##_SELECTOR, \ 415 .base = GUEST_##seg##_BASE, \ 416 .limit = GUEST_##seg##_LIMIT, \ 417 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 418 } 419 420 static const struct kvm_vmx_segment_field { 421 unsigned selector; 422 unsigned base; 423 unsigned limit; 424 unsigned ar_bytes; 425 } kvm_vmx_segment_fields[] = { 426 VMX_SEGMENT_FIELD(CS), 427 VMX_SEGMENT_FIELD(DS), 428 VMX_SEGMENT_FIELD(ES), 429 VMX_SEGMENT_FIELD(FS), 430 VMX_SEGMENT_FIELD(GS), 431 VMX_SEGMENT_FIELD(SS), 432 VMX_SEGMENT_FIELD(TR), 433 VMX_SEGMENT_FIELD(LDTR), 434 }; 435 436 u64 host_efer; 437 static unsigned long host_idt_base; 438 439 /* 440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 441 * will emulate SYSCALL in legacy mode if the vendor string in guest 442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 443 * support this emulation, IA32_STAR must always be included in 444 * vmx_msr_index[], even in i386 builds. 445 */ 446 const u32 vmx_msr_index[] = { 447 #ifdef CONFIG_X86_64 448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 449 #endif 450 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 451 MSR_IA32_TSX_CTRL, 452 }; 453 454 #if IS_ENABLED(CONFIG_HYPERV) 455 static bool __read_mostly enlightened_vmcs = true; 456 module_param(enlightened_vmcs, bool, 0444); 457 458 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 459 static void check_ept_pointer_match(struct kvm *kvm) 460 { 461 struct kvm_vcpu *vcpu; 462 u64 tmp_eptp = INVALID_PAGE; 463 int i; 464 465 kvm_for_each_vcpu(i, vcpu, kvm) { 466 if (!VALID_PAGE(tmp_eptp)) { 467 tmp_eptp = to_vmx(vcpu)->ept_pointer; 468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 469 to_kvm_vmx(kvm)->ept_pointers_match 470 = EPT_POINTERS_MISMATCH; 471 return; 472 } 473 } 474 475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 476 } 477 478 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 479 void *data) 480 { 481 struct kvm_tlb_range *range = data; 482 483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 484 range->pages); 485 } 486 487 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 489 { 490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 491 492 /* 493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 494 * of the base of EPT PML4 table, strip off EPT configuration 495 * information. 496 */ 497 if (range) 498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 499 kvm_fill_hv_flush_list_func, (void *)range); 500 else 501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 502 } 503 504 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 505 struct kvm_tlb_range *range) 506 { 507 struct kvm_vcpu *vcpu; 508 int ret = 0, i; 509 510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 511 512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 513 check_ept_pointer_match(kvm); 514 515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 516 kvm_for_each_vcpu(i, vcpu, kvm) { 517 /* If ept_pointer is invalid pointer, bypass flush request. */ 518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 519 ret |= __hv_remote_flush_tlb_with_range( 520 kvm, vcpu, range); 521 } 522 } else { 523 ret = __hv_remote_flush_tlb_with_range(kvm, 524 kvm_get_vcpu(kvm, 0), range); 525 } 526 527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 528 return ret; 529 } 530 static int hv_remote_flush_tlb(struct kvm *kvm) 531 { 532 return hv_remote_flush_tlb_with_range(kvm, NULL); 533 } 534 535 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 536 { 537 struct hv_enlightened_vmcs *evmcs; 538 struct hv_partition_assist_pg **p_hv_pa_pg = 539 &vcpu->kvm->arch.hyperv.hv_pa_pg; 540 /* 541 * Synthetic VM-Exit is not enabled in current code and so All 542 * evmcs in singe VM shares same assist page. 543 */ 544 if (!*p_hv_pa_pg) 545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 546 547 if (!*p_hv_pa_pg) 548 return -ENOMEM; 549 550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 551 552 evmcs->partition_assist_page = 553 __pa(*p_hv_pa_pg); 554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 556 557 return 0; 558 } 559 560 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 561 562 /* 563 * Comment's format: document - errata name - stepping - processor name. 564 * Refer from 565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 566 */ 567 static u32 vmx_preemption_cpu_tfms[] = { 568 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 569 0x000206E6, 570 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 571 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 572 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 573 0x00020652, 574 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 575 0x00020655, 576 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 577 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 578 /* 579 * 320767.pdf - AAP86 - B1 - 580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 581 */ 582 0x000106E5, 583 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 584 0x000106A0, 585 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 586 0x000106A1, 587 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 588 0x000106A4, 589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 592 0x000106A5, 593 /* Xeon E3-1220 V2 */ 594 0x000306A8, 595 }; 596 597 static inline bool cpu_has_broken_vmx_preemption_timer(void) 598 { 599 u32 eax = cpuid_eax(0x00000001), i; 600 601 /* Clear the reserved bits */ 602 eax &= ~(0x3U << 14 | 0xfU << 28); 603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 604 if (eax == vmx_preemption_cpu_tfms[i]) 605 return true; 606 607 return false; 608 } 609 610 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 611 { 612 return flexpriority_enabled && lapic_in_kernel(vcpu); 613 } 614 615 static inline bool report_flexpriority(void) 616 { 617 return flexpriority_enabled; 618 } 619 620 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 621 { 622 int i; 623 624 for (i = 0; i < vmx->nmsrs; ++i) 625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 626 return i; 627 return -1; 628 } 629 630 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 631 { 632 int i; 633 634 i = __find_msr_index(vmx, msr); 635 if (i >= 0) 636 return &vmx->guest_msrs[i]; 637 return NULL; 638 } 639 640 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 641 { 642 int ret = 0; 643 644 u64 old_msr_data = msr->data; 645 msr->data = data; 646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 647 preempt_disable(); 648 ret = kvm_set_shared_msr(msr->index, msr->data, 649 msr->mask); 650 preempt_enable(); 651 if (ret) 652 msr->data = old_msr_data; 653 } 654 return ret; 655 } 656 657 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 658 { 659 vmcs_clear(loaded_vmcs->vmcs); 660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 661 vmcs_clear(loaded_vmcs->shadow_vmcs); 662 loaded_vmcs->cpu = -1; 663 loaded_vmcs->launched = 0; 664 } 665 666 #ifdef CONFIG_KEXEC_CORE 667 /* 668 * This bitmap is used to indicate whether the vmclear 669 * operation is enabled on all cpus. All disabled by 670 * default. 671 */ 672 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 673 674 static inline void crash_enable_local_vmclear(int cpu) 675 { 676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 677 } 678 679 static inline void crash_disable_local_vmclear(int cpu) 680 { 681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 682 } 683 684 static inline int crash_local_vmclear_enabled(int cpu) 685 { 686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 687 } 688 689 static void crash_vmclear_local_loaded_vmcss(void) 690 { 691 int cpu = raw_smp_processor_id(); 692 struct loaded_vmcs *v; 693 694 if (!crash_local_vmclear_enabled(cpu)) 695 return; 696 697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 698 loaded_vmcss_on_cpu_link) 699 vmcs_clear(v->vmcs); 700 } 701 #else 702 static inline void crash_enable_local_vmclear(int cpu) { } 703 static inline void crash_disable_local_vmclear(int cpu) { } 704 #endif /* CONFIG_KEXEC_CORE */ 705 706 static void __loaded_vmcs_clear(void *arg) 707 { 708 struct loaded_vmcs *loaded_vmcs = arg; 709 int cpu = raw_smp_processor_id(); 710 711 if (loaded_vmcs->cpu != cpu) 712 return; /* vcpu migration can race with cpu offline */ 713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 714 per_cpu(current_vmcs, cpu) = NULL; 715 crash_disable_local_vmclear(cpu); 716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 717 718 /* 719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 720 * is before setting loaded_vmcs->vcpu to -1 which is done in 721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 722 * then adds the vmcs into percpu list before it is deleted. 723 */ 724 smp_wmb(); 725 726 loaded_vmcs_init(loaded_vmcs); 727 crash_enable_local_vmclear(cpu); 728 } 729 730 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 731 { 732 int cpu = loaded_vmcs->cpu; 733 734 if (cpu != -1) 735 smp_call_function_single(cpu, 736 __loaded_vmcs_clear, loaded_vmcs, 1); 737 } 738 739 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 740 unsigned field) 741 { 742 bool ret; 743 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 744 745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 747 vmx->segment_cache.bitmask = 0; 748 } 749 ret = vmx->segment_cache.bitmask & mask; 750 vmx->segment_cache.bitmask |= mask; 751 return ret; 752 } 753 754 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 755 { 756 u16 *p = &vmx->segment_cache.seg[seg].selector; 757 758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 760 return *p; 761 } 762 763 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 764 { 765 ulong *p = &vmx->segment_cache.seg[seg].base; 766 767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 769 return *p; 770 } 771 772 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 773 { 774 u32 *p = &vmx->segment_cache.seg[seg].limit; 775 776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 778 return *p; 779 } 780 781 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 782 { 783 u32 *p = &vmx->segment_cache.seg[seg].ar; 784 785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 787 return *p; 788 } 789 790 void update_exception_bitmap(struct kvm_vcpu *vcpu) 791 { 792 u32 eb; 793 794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 795 (1u << DB_VECTOR) | (1u << AC_VECTOR); 796 /* 797 * Guest access to VMware backdoor ports could legitimately 798 * trigger #GP because of TSS I/O permission bitmap. 799 * We intercept those #GP and allow access to them anyway 800 * as VMware does. 801 */ 802 if (enable_vmware_backdoor) 803 eb |= (1u << GP_VECTOR); 804 if ((vcpu->guest_debug & 805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 807 eb |= 1u << BP_VECTOR; 808 if (to_vmx(vcpu)->rmode.vm86_active) 809 eb = ~0; 810 if (enable_ept) 811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 812 813 /* When we are running a nested L2 guest and L1 specified for it a 814 * certain exception bitmap, we must trap the same exceptions and pass 815 * them to L1. When running L2, we will only handle the exceptions 816 * specified above if L1 did not want them. 817 */ 818 if (is_guest_mode(vcpu)) 819 eb |= get_vmcs12(vcpu)->exception_bitmap; 820 821 vmcs_write32(EXCEPTION_BITMAP, eb); 822 } 823 824 /* 825 * Check if MSR is intercepted for currently loaded MSR bitmap. 826 */ 827 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 828 { 829 unsigned long *msr_bitmap; 830 int f = sizeof(unsigned long); 831 832 if (!cpu_has_vmx_msr_bitmap()) 833 return true; 834 835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 836 837 if (msr <= 0x1fff) { 838 return !!test_bit(msr, msr_bitmap + 0x800 / f); 839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 840 msr &= 0x1fff; 841 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 842 } 843 844 return true; 845 } 846 847 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 848 unsigned long entry, unsigned long exit) 849 { 850 vm_entry_controls_clearbit(vmx, entry); 851 vm_exit_controls_clearbit(vmx, exit); 852 } 853 854 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 855 { 856 unsigned int i; 857 858 for (i = 0; i < m->nr; ++i) { 859 if (m->val[i].index == msr) 860 return i; 861 } 862 return -ENOENT; 863 } 864 865 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 866 { 867 int i; 868 struct msr_autoload *m = &vmx->msr_autoload; 869 870 switch (msr) { 871 case MSR_EFER: 872 if (cpu_has_load_ia32_efer()) { 873 clear_atomic_switch_msr_special(vmx, 874 VM_ENTRY_LOAD_IA32_EFER, 875 VM_EXIT_LOAD_IA32_EFER); 876 return; 877 } 878 break; 879 case MSR_CORE_PERF_GLOBAL_CTRL: 880 if (cpu_has_load_perf_global_ctrl()) { 881 clear_atomic_switch_msr_special(vmx, 882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 884 return; 885 } 886 break; 887 } 888 i = vmx_find_msr_index(&m->guest, msr); 889 if (i < 0) 890 goto skip_guest; 891 --m->guest.nr; 892 m->guest.val[i] = m->guest.val[m->guest.nr]; 893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 894 895 skip_guest: 896 i = vmx_find_msr_index(&m->host, msr); 897 if (i < 0) 898 return; 899 900 --m->host.nr; 901 m->host.val[i] = m->host.val[m->host.nr]; 902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 903 } 904 905 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 906 unsigned long entry, unsigned long exit, 907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 908 u64 guest_val, u64 host_val) 909 { 910 vmcs_write64(guest_val_vmcs, guest_val); 911 if (host_val_vmcs != HOST_IA32_EFER) 912 vmcs_write64(host_val_vmcs, host_val); 913 vm_entry_controls_setbit(vmx, entry); 914 vm_exit_controls_setbit(vmx, exit); 915 } 916 917 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 918 u64 guest_val, u64 host_val, bool entry_only) 919 { 920 int i, j = 0; 921 struct msr_autoload *m = &vmx->msr_autoload; 922 923 switch (msr) { 924 case MSR_EFER: 925 if (cpu_has_load_ia32_efer()) { 926 add_atomic_switch_msr_special(vmx, 927 VM_ENTRY_LOAD_IA32_EFER, 928 VM_EXIT_LOAD_IA32_EFER, 929 GUEST_IA32_EFER, 930 HOST_IA32_EFER, 931 guest_val, host_val); 932 return; 933 } 934 break; 935 case MSR_CORE_PERF_GLOBAL_CTRL: 936 if (cpu_has_load_perf_global_ctrl()) { 937 add_atomic_switch_msr_special(vmx, 938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 940 GUEST_IA32_PERF_GLOBAL_CTRL, 941 HOST_IA32_PERF_GLOBAL_CTRL, 942 guest_val, host_val); 943 return; 944 } 945 break; 946 case MSR_IA32_PEBS_ENABLE: 947 /* PEBS needs a quiescent period after being disabled (to write 948 * a record). Disabling PEBS through VMX MSR swapping doesn't 949 * provide that period, so a CPU could write host's record into 950 * guest's memory. 951 */ 952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 953 } 954 955 i = vmx_find_msr_index(&m->guest, msr); 956 if (!entry_only) 957 j = vmx_find_msr_index(&m->host, msr); 958 959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 961 printk_once(KERN_WARNING "Not enough msr switch entries. " 962 "Can't add msr %x\n", msr); 963 return; 964 } 965 if (i < 0) { 966 i = m->guest.nr++; 967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 968 } 969 m->guest.val[i].index = msr; 970 m->guest.val[i].value = guest_val; 971 972 if (entry_only) 973 return; 974 975 if (j < 0) { 976 j = m->host.nr++; 977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 978 } 979 m->host.val[j].index = msr; 980 m->host.val[j].value = host_val; 981 } 982 983 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 984 { 985 u64 guest_efer = vmx->vcpu.arch.efer; 986 u64 ignore_bits = 0; 987 988 /* Shadow paging assumes NX to be available. */ 989 if (!enable_ept) 990 guest_efer |= EFER_NX; 991 992 /* 993 * LMA and LME handled by hardware; SCE meaningless outside long mode. 994 */ 995 ignore_bits |= EFER_SCE; 996 #ifdef CONFIG_X86_64 997 ignore_bits |= EFER_LMA | EFER_LME; 998 /* SCE is meaningful only in long mode on Intel */ 999 if (guest_efer & EFER_LMA) 1000 ignore_bits &= ~(u64)EFER_SCE; 1001 #endif 1002 1003 /* 1004 * On EPT, we can't emulate NX, so we must switch EFER atomically. 1005 * On CPUs that support "load IA32_EFER", always switch EFER 1006 * atomically, since it's faster than switching it manually. 1007 */ 1008 if (cpu_has_load_ia32_efer() || 1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 1010 if (!(guest_efer & EFER_LMA)) 1011 guest_efer &= ~EFER_LME; 1012 if (guest_efer != host_efer) 1013 add_atomic_switch_msr(vmx, MSR_EFER, 1014 guest_efer, host_efer, false); 1015 else 1016 clear_atomic_switch_msr(vmx, MSR_EFER); 1017 return false; 1018 } else { 1019 clear_atomic_switch_msr(vmx, MSR_EFER); 1020 1021 guest_efer &= ~ignore_bits; 1022 guest_efer |= host_efer & ignore_bits; 1023 1024 vmx->guest_msrs[efer_offset].data = guest_efer; 1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1026 1027 return true; 1028 } 1029 } 1030 1031 #ifdef CONFIG_X86_32 1032 /* 1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1034 * VMCS rather than the segment table. KVM uses this helper to figure 1035 * out the current bases to poke them into the VMCS before entry. 1036 */ 1037 static unsigned long segment_base(u16 selector) 1038 { 1039 struct desc_struct *table; 1040 unsigned long v; 1041 1042 if (!(selector & ~SEGMENT_RPL_MASK)) 1043 return 0; 1044 1045 table = get_current_gdt_ro(); 1046 1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1048 u16 ldt_selector = kvm_read_ldt(); 1049 1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1051 return 0; 1052 1053 table = (struct desc_struct *)segment_base(ldt_selector); 1054 } 1055 v = get_desc_base(&table[selector >> 3]); 1056 return v; 1057 } 1058 #endif 1059 1060 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1061 { 1062 return (pt_mode == PT_MODE_HOST_GUEST) && 1063 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1064 } 1065 1066 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1067 { 1068 u32 i; 1069 1070 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1071 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1072 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1073 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1074 for (i = 0; i < addr_range; i++) { 1075 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1076 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1077 } 1078 } 1079 1080 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1081 { 1082 u32 i; 1083 1084 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1085 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1086 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1087 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1088 for (i = 0; i < addr_range; i++) { 1089 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1090 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1091 } 1092 } 1093 1094 static void pt_guest_enter(struct vcpu_vmx *vmx) 1095 { 1096 if (pt_mode == PT_MODE_SYSTEM) 1097 return; 1098 1099 /* 1100 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1101 * Save host state before VM entry. 1102 */ 1103 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1104 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1105 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1106 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1107 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1108 } 1109 } 1110 1111 static void pt_guest_exit(struct vcpu_vmx *vmx) 1112 { 1113 if (pt_mode == PT_MODE_SYSTEM) 1114 return; 1115 1116 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1117 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1118 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1119 } 1120 1121 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1122 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1123 } 1124 1125 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1126 unsigned long fs_base, unsigned long gs_base) 1127 { 1128 if (unlikely(fs_sel != host->fs_sel)) { 1129 if (!(fs_sel & 7)) 1130 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1131 else 1132 vmcs_write16(HOST_FS_SELECTOR, 0); 1133 host->fs_sel = fs_sel; 1134 } 1135 if (unlikely(gs_sel != host->gs_sel)) { 1136 if (!(gs_sel & 7)) 1137 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1138 else 1139 vmcs_write16(HOST_GS_SELECTOR, 0); 1140 host->gs_sel = gs_sel; 1141 } 1142 if (unlikely(fs_base != host->fs_base)) { 1143 vmcs_writel(HOST_FS_BASE, fs_base); 1144 host->fs_base = fs_base; 1145 } 1146 if (unlikely(gs_base != host->gs_base)) { 1147 vmcs_writel(HOST_GS_BASE, gs_base); 1148 host->gs_base = gs_base; 1149 } 1150 } 1151 1152 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1153 { 1154 struct vcpu_vmx *vmx = to_vmx(vcpu); 1155 struct vmcs_host_state *host_state; 1156 #ifdef CONFIG_X86_64 1157 int cpu = raw_smp_processor_id(); 1158 #endif 1159 unsigned long fs_base, gs_base; 1160 u16 fs_sel, gs_sel; 1161 int i; 1162 1163 vmx->req_immediate_exit = false; 1164 1165 /* 1166 * Note that guest MSRs to be saved/restored can also be changed 1167 * when guest state is loaded. This happens when guest transitions 1168 * to/from long-mode by setting MSR_EFER.LMA. 1169 */ 1170 if (!vmx->guest_msrs_ready) { 1171 vmx->guest_msrs_ready = true; 1172 for (i = 0; i < vmx->save_nmsrs; ++i) 1173 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1174 vmx->guest_msrs[i].data, 1175 vmx->guest_msrs[i].mask); 1176 1177 } 1178 if (vmx->guest_state_loaded) 1179 return; 1180 1181 host_state = &vmx->loaded_vmcs->host_state; 1182 1183 /* 1184 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1185 * allow segment selectors with cpl > 0 or ti == 1. 1186 */ 1187 host_state->ldt_sel = kvm_read_ldt(); 1188 1189 #ifdef CONFIG_X86_64 1190 savesegment(ds, host_state->ds_sel); 1191 savesegment(es, host_state->es_sel); 1192 1193 gs_base = cpu_kernelmode_gs_base(cpu); 1194 if (likely(is_64bit_mm(current->mm))) { 1195 save_fsgs_for_kvm(); 1196 fs_sel = current->thread.fsindex; 1197 gs_sel = current->thread.gsindex; 1198 fs_base = current->thread.fsbase; 1199 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1200 } else { 1201 savesegment(fs, fs_sel); 1202 savesegment(gs, gs_sel); 1203 fs_base = read_msr(MSR_FS_BASE); 1204 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1205 } 1206 1207 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1208 #else 1209 savesegment(fs, fs_sel); 1210 savesegment(gs, gs_sel); 1211 fs_base = segment_base(fs_sel); 1212 gs_base = segment_base(gs_sel); 1213 #endif 1214 1215 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1216 vmx->guest_state_loaded = true; 1217 } 1218 1219 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1220 { 1221 struct vmcs_host_state *host_state; 1222 1223 if (!vmx->guest_state_loaded) 1224 return; 1225 1226 host_state = &vmx->loaded_vmcs->host_state; 1227 1228 ++vmx->vcpu.stat.host_state_reload; 1229 1230 #ifdef CONFIG_X86_64 1231 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1232 #endif 1233 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1234 kvm_load_ldt(host_state->ldt_sel); 1235 #ifdef CONFIG_X86_64 1236 load_gs_index(host_state->gs_sel); 1237 #else 1238 loadsegment(gs, host_state->gs_sel); 1239 #endif 1240 } 1241 if (host_state->fs_sel & 7) 1242 loadsegment(fs, host_state->fs_sel); 1243 #ifdef CONFIG_X86_64 1244 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1245 loadsegment(ds, host_state->ds_sel); 1246 loadsegment(es, host_state->es_sel); 1247 } 1248 #endif 1249 invalidate_tss_limit(); 1250 #ifdef CONFIG_X86_64 1251 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1252 #endif 1253 load_fixmap_gdt(raw_smp_processor_id()); 1254 vmx->guest_state_loaded = false; 1255 vmx->guest_msrs_ready = false; 1256 } 1257 1258 #ifdef CONFIG_X86_64 1259 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1260 { 1261 preempt_disable(); 1262 if (vmx->guest_state_loaded) 1263 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1264 preempt_enable(); 1265 return vmx->msr_guest_kernel_gs_base; 1266 } 1267 1268 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1269 { 1270 preempt_disable(); 1271 if (vmx->guest_state_loaded) 1272 wrmsrl(MSR_KERNEL_GS_BASE, data); 1273 preempt_enable(); 1274 vmx->msr_guest_kernel_gs_base = data; 1275 } 1276 #endif 1277 1278 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1279 { 1280 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1281 struct pi_desc old, new; 1282 unsigned int dest; 1283 1284 /* 1285 * In case of hot-plug or hot-unplug, we may have to undo 1286 * vmx_vcpu_pi_put even if there is no assigned device. And we 1287 * always keep PI.NDST up to date for simplicity: it makes the 1288 * code easier, and CPU migration is not a fast path. 1289 */ 1290 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1291 return; 1292 1293 /* 1294 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1295 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1296 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1297 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1298 * correctly. 1299 */ 1300 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1301 pi_clear_sn(pi_desc); 1302 goto after_clear_sn; 1303 } 1304 1305 /* The full case. */ 1306 do { 1307 old.control = new.control = pi_desc->control; 1308 1309 dest = cpu_physical_id(cpu); 1310 1311 if (x2apic_enabled()) 1312 new.ndst = dest; 1313 else 1314 new.ndst = (dest << 8) & 0xFF00; 1315 1316 new.sn = 0; 1317 } while (cmpxchg64(&pi_desc->control, old.control, 1318 new.control) != old.control); 1319 1320 after_clear_sn: 1321 1322 /* 1323 * Clear SN before reading the bitmap. The VT-d firmware 1324 * writes the bitmap and reads SN atomically (5.2.3 in the 1325 * spec), so it doesn't really have a memory barrier that 1326 * pairs with this, but we cannot do that and we need one. 1327 */ 1328 smp_mb__after_atomic(); 1329 1330 if (!pi_is_pir_empty(pi_desc)) 1331 pi_set_on(pi_desc); 1332 } 1333 1334 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1335 { 1336 struct vcpu_vmx *vmx = to_vmx(vcpu); 1337 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1338 1339 if (!already_loaded) { 1340 loaded_vmcs_clear(vmx->loaded_vmcs); 1341 local_irq_disable(); 1342 crash_disable_local_vmclear(cpu); 1343 1344 /* 1345 * Read loaded_vmcs->cpu should be before fetching 1346 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1347 * See the comments in __loaded_vmcs_clear(). 1348 */ 1349 smp_rmb(); 1350 1351 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1352 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1353 crash_enable_local_vmclear(cpu); 1354 local_irq_enable(); 1355 } 1356 1357 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1358 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1359 vmcs_load(vmx->loaded_vmcs->vmcs); 1360 indirect_branch_prediction_barrier(); 1361 } 1362 1363 if (!already_loaded) { 1364 void *gdt = get_current_gdt_ro(); 1365 unsigned long sysenter_esp; 1366 1367 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1368 1369 /* 1370 * Linux uses per-cpu TSS and GDT, so set these when switching 1371 * processors. See 22.2.4. 1372 */ 1373 vmcs_writel(HOST_TR_BASE, 1374 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1375 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1376 1377 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1378 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1379 1380 vmx->loaded_vmcs->cpu = cpu; 1381 } 1382 1383 /* Setup TSC multiplier */ 1384 if (kvm_has_tsc_control && 1385 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1386 decache_tsc_multiplier(vmx); 1387 } 1388 1389 /* 1390 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1391 * vcpu mutex is already taken. 1392 */ 1393 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1394 { 1395 struct vcpu_vmx *vmx = to_vmx(vcpu); 1396 1397 vmx_vcpu_load_vmcs(vcpu, cpu); 1398 1399 vmx_vcpu_pi_load(vcpu, cpu); 1400 1401 vmx->host_pkru = read_pkru(); 1402 vmx->host_debugctlmsr = get_debugctlmsr(); 1403 } 1404 1405 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1406 { 1407 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1408 1409 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1410 !irq_remapping_cap(IRQ_POSTING_CAP) || 1411 !kvm_vcpu_apicv_active(vcpu)) 1412 return; 1413 1414 /* Set SN when the vCPU is preempted */ 1415 if (vcpu->preempted) 1416 pi_set_sn(pi_desc); 1417 } 1418 1419 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1420 { 1421 vmx_vcpu_pi_put(vcpu); 1422 1423 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1424 } 1425 1426 static bool emulation_required(struct kvm_vcpu *vcpu) 1427 { 1428 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1429 } 1430 1431 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1432 { 1433 struct vcpu_vmx *vmx = to_vmx(vcpu); 1434 unsigned long rflags, save_rflags; 1435 1436 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1437 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1438 rflags = vmcs_readl(GUEST_RFLAGS); 1439 if (vmx->rmode.vm86_active) { 1440 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1441 save_rflags = vmx->rmode.save_rflags; 1442 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1443 } 1444 vmx->rflags = rflags; 1445 } 1446 return vmx->rflags; 1447 } 1448 1449 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1450 { 1451 struct vcpu_vmx *vmx = to_vmx(vcpu); 1452 unsigned long old_rflags; 1453 1454 if (enable_unrestricted_guest) { 1455 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1456 vmx->rflags = rflags; 1457 vmcs_writel(GUEST_RFLAGS, rflags); 1458 return; 1459 } 1460 1461 old_rflags = vmx_get_rflags(vcpu); 1462 vmx->rflags = rflags; 1463 if (vmx->rmode.vm86_active) { 1464 vmx->rmode.save_rflags = rflags; 1465 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1466 } 1467 vmcs_writel(GUEST_RFLAGS, rflags); 1468 1469 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1470 vmx->emulation_required = emulation_required(vcpu); 1471 } 1472 1473 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1474 { 1475 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1476 int ret = 0; 1477 1478 if (interruptibility & GUEST_INTR_STATE_STI) 1479 ret |= KVM_X86_SHADOW_INT_STI; 1480 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1481 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1482 1483 return ret; 1484 } 1485 1486 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1487 { 1488 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1489 u32 interruptibility = interruptibility_old; 1490 1491 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1492 1493 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1494 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1495 else if (mask & KVM_X86_SHADOW_INT_STI) 1496 interruptibility |= GUEST_INTR_STATE_STI; 1497 1498 if ((interruptibility != interruptibility_old)) 1499 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1500 } 1501 1502 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1503 { 1504 struct vcpu_vmx *vmx = to_vmx(vcpu); 1505 unsigned long value; 1506 1507 /* 1508 * Any MSR write that attempts to change bits marked reserved will 1509 * case a #GP fault. 1510 */ 1511 if (data & vmx->pt_desc.ctl_bitmask) 1512 return 1; 1513 1514 /* 1515 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1516 * result in a #GP unless the same write also clears TraceEn. 1517 */ 1518 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1519 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1520 return 1; 1521 1522 /* 1523 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1524 * and FabricEn would cause #GP, if 1525 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1526 */ 1527 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1528 !(data & RTIT_CTL_FABRIC_EN) && 1529 !intel_pt_validate_cap(vmx->pt_desc.caps, 1530 PT_CAP_single_range_output)) 1531 return 1; 1532 1533 /* 1534 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1535 * utilize encodings marked reserved will casue a #GP fault. 1536 */ 1537 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1538 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1539 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1540 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1541 return 1; 1542 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1543 PT_CAP_cycle_thresholds); 1544 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1545 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1546 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1547 return 1; 1548 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1549 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1550 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1551 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1552 return 1; 1553 1554 /* 1555 * If ADDRx_CFG is reserved or the encodings is >2 will 1556 * cause a #GP fault. 1557 */ 1558 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1559 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1560 return 1; 1561 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1562 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1563 return 1; 1564 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1565 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1566 return 1; 1567 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1568 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1569 return 1; 1570 1571 return 0; 1572 } 1573 1574 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1575 { 1576 unsigned long rip; 1577 1578 /* 1579 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1580 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1581 * set when EPT misconfig occurs. In practice, real hardware updates 1582 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1583 * (namely Hyper-V) don't set it due to it being undefined behavior, 1584 * i.e. we end up advancing IP with some random value. 1585 */ 1586 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1587 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1588 rip = kvm_rip_read(vcpu); 1589 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1590 kvm_rip_write(vcpu, rip); 1591 } else { 1592 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1593 return 0; 1594 } 1595 1596 /* skipping an emulated instruction also counts */ 1597 vmx_set_interrupt_shadow(vcpu, 0); 1598 1599 return 1; 1600 } 1601 1602 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1603 { 1604 /* 1605 * Ensure that we clear the HLT state in the VMCS. We don't need to 1606 * explicitly skip the instruction because if the HLT state is set, 1607 * then the instruction is already executing and RIP has already been 1608 * advanced. 1609 */ 1610 if (kvm_hlt_in_guest(vcpu->kvm) && 1611 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1612 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1613 } 1614 1615 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1616 { 1617 struct vcpu_vmx *vmx = to_vmx(vcpu); 1618 unsigned nr = vcpu->arch.exception.nr; 1619 bool has_error_code = vcpu->arch.exception.has_error_code; 1620 u32 error_code = vcpu->arch.exception.error_code; 1621 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1622 1623 kvm_deliver_exception_payload(vcpu); 1624 1625 if (has_error_code) { 1626 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1627 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1628 } 1629 1630 if (vmx->rmode.vm86_active) { 1631 int inc_eip = 0; 1632 if (kvm_exception_is_soft(nr)) 1633 inc_eip = vcpu->arch.event_exit_inst_len; 1634 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1635 return; 1636 } 1637 1638 WARN_ON_ONCE(vmx->emulation_required); 1639 1640 if (kvm_exception_is_soft(nr)) { 1641 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1642 vmx->vcpu.arch.event_exit_inst_len); 1643 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1644 } else 1645 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1646 1647 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1648 1649 vmx_clear_hlt(vcpu); 1650 } 1651 1652 static bool vmx_rdtscp_supported(void) 1653 { 1654 return cpu_has_vmx_rdtscp(); 1655 } 1656 1657 static bool vmx_invpcid_supported(void) 1658 { 1659 return cpu_has_vmx_invpcid(); 1660 } 1661 1662 /* 1663 * Swap MSR entry in host/guest MSR entry array. 1664 */ 1665 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1666 { 1667 struct shared_msr_entry tmp; 1668 1669 tmp = vmx->guest_msrs[to]; 1670 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1671 vmx->guest_msrs[from] = tmp; 1672 } 1673 1674 /* 1675 * Set up the vmcs to automatically save and restore system 1676 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1677 * mode, as fiddling with msrs is very expensive. 1678 */ 1679 static void setup_msrs(struct vcpu_vmx *vmx) 1680 { 1681 int save_nmsrs, index; 1682 1683 save_nmsrs = 0; 1684 #ifdef CONFIG_X86_64 1685 /* 1686 * The SYSCALL MSRs are only needed on long mode guests, and only 1687 * when EFER.SCE is set. 1688 */ 1689 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1690 index = __find_msr_index(vmx, MSR_STAR); 1691 if (index >= 0) 1692 move_msr_up(vmx, index, save_nmsrs++); 1693 index = __find_msr_index(vmx, MSR_LSTAR); 1694 if (index >= 0) 1695 move_msr_up(vmx, index, save_nmsrs++); 1696 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1697 if (index >= 0) 1698 move_msr_up(vmx, index, save_nmsrs++); 1699 } 1700 #endif 1701 index = __find_msr_index(vmx, MSR_EFER); 1702 if (index >= 0 && update_transition_efer(vmx, index)) 1703 move_msr_up(vmx, index, save_nmsrs++); 1704 index = __find_msr_index(vmx, MSR_TSC_AUX); 1705 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1706 move_msr_up(vmx, index, save_nmsrs++); 1707 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1708 if (index >= 0) 1709 move_msr_up(vmx, index, save_nmsrs++); 1710 1711 vmx->save_nmsrs = save_nmsrs; 1712 vmx->guest_msrs_ready = false; 1713 1714 if (cpu_has_vmx_msr_bitmap()) 1715 vmx_update_msr_bitmap(&vmx->vcpu); 1716 } 1717 1718 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1719 { 1720 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1721 1722 if (is_guest_mode(vcpu) && 1723 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1724 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1725 1726 return vcpu->arch.tsc_offset; 1727 } 1728 1729 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1730 { 1731 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1732 u64 g_tsc_offset = 0; 1733 1734 /* 1735 * We're here if L1 chose not to trap WRMSR to TSC. According 1736 * to the spec, this should set L1's TSC; The offset that L1 1737 * set for L2 remains unchanged, and still needs to be added 1738 * to the newly set TSC to get L2's TSC. 1739 */ 1740 if (is_guest_mode(vcpu) && 1741 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1742 g_tsc_offset = vmcs12->tsc_offset; 1743 1744 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1745 vcpu->arch.tsc_offset - g_tsc_offset, 1746 offset); 1747 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1748 return offset + g_tsc_offset; 1749 } 1750 1751 /* 1752 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1753 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1754 * all guests if the "nested" module option is off, and can also be disabled 1755 * for a single guest by disabling its VMX cpuid bit. 1756 */ 1757 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1758 { 1759 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1760 } 1761 1762 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1763 uint64_t val) 1764 { 1765 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1766 1767 return !(val & ~valid_bits); 1768 } 1769 1770 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1771 { 1772 switch (msr->index) { 1773 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1774 if (!nested) 1775 return 1; 1776 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1777 default: 1778 return 1; 1779 } 1780 } 1781 1782 /* 1783 * Reads an msr value (of 'msr_index') into 'pdata'. 1784 * Returns 0 on success, non-0 otherwise. 1785 * Assumes vcpu_load() was already called. 1786 */ 1787 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1788 { 1789 struct vcpu_vmx *vmx = to_vmx(vcpu); 1790 struct shared_msr_entry *msr; 1791 u32 index; 1792 1793 switch (msr_info->index) { 1794 #ifdef CONFIG_X86_64 1795 case MSR_FS_BASE: 1796 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1797 break; 1798 case MSR_GS_BASE: 1799 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1800 break; 1801 case MSR_KERNEL_GS_BASE: 1802 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1803 break; 1804 #endif 1805 case MSR_EFER: 1806 return kvm_get_msr_common(vcpu, msr_info); 1807 case MSR_IA32_TSX_CTRL: 1808 if (!msr_info->host_initiated && 1809 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1810 return 1; 1811 goto find_shared_msr; 1812 case MSR_IA32_UMWAIT_CONTROL: 1813 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1814 return 1; 1815 1816 msr_info->data = vmx->msr_ia32_umwait_control; 1817 break; 1818 case MSR_IA32_SPEC_CTRL: 1819 if (!msr_info->host_initiated && 1820 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1821 return 1; 1822 1823 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1824 break; 1825 case MSR_IA32_SYSENTER_CS: 1826 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1827 break; 1828 case MSR_IA32_SYSENTER_EIP: 1829 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1830 break; 1831 case MSR_IA32_SYSENTER_ESP: 1832 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1833 break; 1834 case MSR_IA32_BNDCFGS: 1835 if (!kvm_mpx_supported() || 1836 (!msr_info->host_initiated && 1837 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1838 return 1; 1839 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1840 break; 1841 case MSR_IA32_MCG_EXT_CTL: 1842 if (!msr_info->host_initiated && 1843 !(vmx->msr_ia32_feature_control & 1844 FEAT_CTL_LMCE_ENABLED)) 1845 return 1; 1846 msr_info->data = vcpu->arch.mcg_ext_ctl; 1847 break; 1848 case MSR_IA32_FEAT_CTL: 1849 msr_info->data = vmx->msr_ia32_feature_control; 1850 break; 1851 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1852 if (!nested_vmx_allowed(vcpu)) 1853 return 1; 1854 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1855 &msr_info->data)) 1856 return 1; 1857 /* 1858 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1859 * Hyper-V versions are still trying to use corresponding 1860 * features when they are exposed. Filter out the essential 1861 * minimum. 1862 */ 1863 if (!msr_info->host_initiated && 1864 vmx->nested.enlightened_vmcs_enabled) 1865 nested_evmcs_filter_control_msr(msr_info->index, 1866 &msr_info->data); 1867 break; 1868 case MSR_IA32_RTIT_CTL: 1869 if (pt_mode != PT_MODE_HOST_GUEST) 1870 return 1; 1871 msr_info->data = vmx->pt_desc.guest.ctl; 1872 break; 1873 case MSR_IA32_RTIT_STATUS: 1874 if (pt_mode != PT_MODE_HOST_GUEST) 1875 return 1; 1876 msr_info->data = vmx->pt_desc.guest.status; 1877 break; 1878 case MSR_IA32_RTIT_CR3_MATCH: 1879 if ((pt_mode != PT_MODE_HOST_GUEST) || 1880 !intel_pt_validate_cap(vmx->pt_desc.caps, 1881 PT_CAP_cr3_filtering)) 1882 return 1; 1883 msr_info->data = vmx->pt_desc.guest.cr3_match; 1884 break; 1885 case MSR_IA32_RTIT_OUTPUT_BASE: 1886 if ((pt_mode != PT_MODE_HOST_GUEST) || 1887 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1888 PT_CAP_topa_output) && 1889 !intel_pt_validate_cap(vmx->pt_desc.caps, 1890 PT_CAP_single_range_output))) 1891 return 1; 1892 msr_info->data = vmx->pt_desc.guest.output_base; 1893 break; 1894 case MSR_IA32_RTIT_OUTPUT_MASK: 1895 if ((pt_mode != PT_MODE_HOST_GUEST) || 1896 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1897 PT_CAP_topa_output) && 1898 !intel_pt_validate_cap(vmx->pt_desc.caps, 1899 PT_CAP_single_range_output))) 1900 return 1; 1901 msr_info->data = vmx->pt_desc.guest.output_mask; 1902 break; 1903 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1904 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1905 if ((pt_mode != PT_MODE_HOST_GUEST) || 1906 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1907 PT_CAP_num_address_ranges))) 1908 return 1; 1909 if (index % 2) 1910 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1911 else 1912 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1913 break; 1914 case MSR_TSC_AUX: 1915 if (!msr_info->host_initiated && 1916 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1917 return 1; 1918 goto find_shared_msr; 1919 default: 1920 find_shared_msr: 1921 msr = find_msr_entry(vmx, msr_info->index); 1922 if (msr) { 1923 msr_info->data = msr->data; 1924 break; 1925 } 1926 return kvm_get_msr_common(vcpu, msr_info); 1927 } 1928 1929 return 0; 1930 } 1931 1932 /* 1933 * Writes msr value into the appropriate "register". 1934 * Returns 0 on success, non-0 otherwise. 1935 * Assumes vcpu_load() was already called. 1936 */ 1937 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1938 { 1939 struct vcpu_vmx *vmx = to_vmx(vcpu); 1940 struct shared_msr_entry *msr; 1941 int ret = 0; 1942 u32 msr_index = msr_info->index; 1943 u64 data = msr_info->data; 1944 u32 index; 1945 1946 switch (msr_index) { 1947 case MSR_EFER: 1948 ret = kvm_set_msr_common(vcpu, msr_info); 1949 break; 1950 #ifdef CONFIG_X86_64 1951 case MSR_FS_BASE: 1952 vmx_segment_cache_clear(vmx); 1953 vmcs_writel(GUEST_FS_BASE, data); 1954 break; 1955 case MSR_GS_BASE: 1956 vmx_segment_cache_clear(vmx); 1957 vmcs_writel(GUEST_GS_BASE, data); 1958 break; 1959 case MSR_KERNEL_GS_BASE: 1960 vmx_write_guest_kernel_gs_base(vmx, data); 1961 break; 1962 #endif 1963 case MSR_IA32_SYSENTER_CS: 1964 if (is_guest_mode(vcpu)) 1965 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1966 vmcs_write32(GUEST_SYSENTER_CS, data); 1967 break; 1968 case MSR_IA32_SYSENTER_EIP: 1969 if (is_guest_mode(vcpu)) 1970 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1971 vmcs_writel(GUEST_SYSENTER_EIP, data); 1972 break; 1973 case MSR_IA32_SYSENTER_ESP: 1974 if (is_guest_mode(vcpu)) 1975 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1976 vmcs_writel(GUEST_SYSENTER_ESP, data); 1977 break; 1978 case MSR_IA32_DEBUGCTLMSR: 1979 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1980 VM_EXIT_SAVE_DEBUG_CONTROLS) 1981 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1982 1983 ret = kvm_set_msr_common(vcpu, msr_info); 1984 break; 1985 1986 case MSR_IA32_BNDCFGS: 1987 if (!kvm_mpx_supported() || 1988 (!msr_info->host_initiated && 1989 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1990 return 1; 1991 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1992 (data & MSR_IA32_BNDCFGS_RSVD)) 1993 return 1; 1994 vmcs_write64(GUEST_BNDCFGS, data); 1995 break; 1996 case MSR_IA32_UMWAIT_CONTROL: 1997 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1998 return 1; 1999 2000 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 2001 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 2002 return 1; 2003 2004 vmx->msr_ia32_umwait_control = data; 2005 break; 2006 case MSR_IA32_SPEC_CTRL: 2007 if (!msr_info->host_initiated && 2008 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2009 return 1; 2010 2011 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2012 return 1; 2013 2014 vmx->spec_ctrl = data; 2015 if (!data) 2016 break; 2017 2018 /* 2019 * For non-nested: 2020 * When it's written (to non-zero) for the first time, pass 2021 * it through. 2022 * 2023 * For nested: 2024 * The handling of the MSR bitmap for L2 guests is done in 2025 * nested_vmx_prepare_msr_bitmap. We should not touch the 2026 * vmcs02.msr_bitmap here since it gets completely overwritten 2027 * in the merging. We update the vmcs01 here for L1 as well 2028 * since it will end up touching the MSR anyway now. 2029 */ 2030 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2031 MSR_IA32_SPEC_CTRL, 2032 MSR_TYPE_RW); 2033 break; 2034 case MSR_IA32_TSX_CTRL: 2035 if (!msr_info->host_initiated && 2036 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2037 return 1; 2038 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2039 return 1; 2040 goto find_shared_msr; 2041 case MSR_IA32_PRED_CMD: 2042 if (!msr_info->host_initiated && 2043 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2044 return 1; 2045 2046 if (data & ~PRED_CMD_IBPB) 2047 return 1; 2048 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2049 return 1; 2050 if (!data) 2051 break; 2052 2053 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2054 2055 /* 2056 * For non-nested: 2057 * When it's written (to non-zero) for the first time, pass 2058 * it through. 2059 * 2060 * For nested: 2061 * The handling of the MSR bitmap for L2 guests is done in 2062 * nested_vmx_prepare_msr_bitmap. We should not touch the 2063 * vmcs02.msr_bitmap here since it gets completely overwritten 2064 * in the merging. 2065 */ 2066 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2067 MSR_TYPE_W); 2068 break; 2069 case MSR_IA32_CR_PAT: 2070 if (!kvm_pat_valid(data)) 2071 return 1; 2072 2073 if (is_guest_mode(vcpu) && 2074 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2075 get_vmcs12(vcpu)->guest_ia32_pat = data; 2076 2077 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2078 vmcs_write64(GUEST_IA32_PAT, data); 2079 vcpu->arch.pat = data; 2080 break; 2081 } 2082 ret = kvm_set_msr_common(vcpu, msr_info); 2083 break; 2084 case MSR_IA32_TSC_ADJUST: 2085 ret = kvm_set_msr_common(vcpu, msr_info); 2086 break; 2087 case MSR_IA32_MCG_EXT_CTL: 2088 if ((!msr_info->host_initiated && 2089 !(to_vmx(vcpu)->msr_ia32_feature_control & 2090 FEAT_CTL_LMCE_ENABLED)) || 2091 (data & ~MCG_EXT_CTL_LMCE_EN)) 2092 return 1; 2093 vcpu->arch.mcg_ext_ctl = data; 2094 break; 2095 case MSR_IA32_FEAT_CTL: 2096 if (!vmx_feature_control_msr_valid(vcpu, data) || 2097 (to_vmx(vcpu)->msr_ia32_feature_control & 2098 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2099 return 1; 2100 vmx->msr_ia32_feature_control = data; 2101 if (msr_info->host_initiated && data == 0) 2102 vmx_leave_nested(vcpu); 2103 break; 2104 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2105 if (!msr_info->host_initiated) 2106 return 1; /* they are read-only */ 2107 if (!nested_vmx_allowed(vcpu)) 2108 return 1; 2109 return vmx_set_vmx_msr(vcpu, msr_index, data); 2110 case MSR_IA32_RTIT_CTL: 2111 if ((pt_mode != PT_MODE_HOST_GUEST) || 2112 vmx_rtit_ctl_check(vcpu, data) || 2113 vmx->nested.vmxon) 2114 return 1; 2115 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2116 vmx->pt_desc.guest.ctl = data; 2117 pt_update_intercept_for_msr(vmx); 2118 break; 2119 case MSR_IA32_RTIT_STATUS: 2120 if (!pt_can_write_msr(vmx)) 2121 return 1; 2122 if (data & MSR_IA32_RTIT_STATUS_MASK) 2123 return 1; 2124 vmx->pt_desc.guest.status = data; 2125 break; 2126 case MSR_IA32_RTIT_CR3_MATCH: 2127 if (!pt_can_write_msr(vmx)) 2128 return 1; 2129 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2130 PT_CAP_cr3_filtering)) 2131 return 1; 2132 vmx->pt_desc.guest.cr3_match = data; 2133 break; 2134 case MSR_IA32_RTIT_OUTPUT_BASE: 2135 if (!pt_can_write_msr(vmx)) 2136 return 1; 2137 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2138 PT_CAP_topa_output) && 2139 !intel_pt_validate_cap(vmx->pt_desc.caps, 2140 PT_CAP_single_range_output)) 2141 return 1; 2142 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2143 return 1; 2144 vmx->pt_desc.guest.output_base = data; 2145 break; 2146 case MSR_IA32_RTIT_OUTPUT_MASK: 2147 if (!pt_can_write_msr(vmx)) 2148 return 1; 2149 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2150 PT_CAP_topa_output) && 2151 !intel_pt_validate_cap(vmx->pt_desc.caps, 2152 PT_CAP_single_range_output)) 2153 return 1; 2154 vmx->pt_desc.guest.output_mask = data; 2155 break; 2156 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2157 if (!pt_can_write_msr(vmx)) 2158 return 1; 2159 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2160 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2161 PT_CAP_num_address_ranges)) 2162 return 1; 2163 if (is_noncanonical_address(data, vcpu)) 2164 return 1; 2165 if (index % 2) 2166 vmx->pt_desc.guest.addr_b[index / 2] = data; 2167 else 2168 vmx->pt_desc.guest.addr_a[index / 2] = data; 2169 break; 2170 case MSR_TSC_AUX: 2171 if (!msr_info->host_initiated && 2172 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2173 return 1; 2174 /* Check reserved bit, higher 32 bits should be zero */ 2175 if ((data >> 32) != 0) 2176 return 1; 2177 goto find_shared_msr; 2178 2179 default: 2180 find_shared_msr: 2181 msr = find_msr_entry(vmx, msr_index); 2182 if (msr) 2183 ret = vmx_set_guest_msr(vmx, msr, data); 2184 else 2185 ret = kvm_set_msr_common(vcpu, msr_info); 2186 } 2187 2188 return ret; 2189 } 2190 2191 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2192 { 2193 kvm_register_mark_available(vcpu, reg); 2194 2195 switch (reg) { 2196 case VCPU_REGS_RSP: 2197 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2198 break; 2199 case VCPU_REGS_RIP: 2200 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2201 break; 2202 case VCPU_EXREG_PDPTR: 2203 if (enable_ept) 2204 ept_save_pdptrs(vcpu); 2205 break; 2206 case VCPU_EXREG_CR3: 2207 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2208 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2209 break; 2210 default: 2211 WARN_ON_ONCE(1); 2212 break; 2213 } 2214 } 2215 2216 static __init int cpu_has_kvm_support(void) 2217 { 2218 return cpu_has_vmx(); 2219 } 2220 2221 static __init int vmx_disabled_by_bios(void) 2222 { 2223 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2224 !boot_cpu_has(X86_FEATURE_VMX); 2225 } 2226 2227 static void kvm_cpu_vmxon(u64 addr) 2228 { 2229 cr4_set_bits(X86_CR4_VMXE); 2230 intel_pt_handle_vmx(1); 2231 2232 asm volatile ("vmxon %0" : : "m"(addr)); 2233 } 2234 2235 static int hardware_enable(void) 2236 { 2237 int cpu = raw_smp_processor_id(); 2238 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2239 2240 if (cr4_read_shadow() & X86_CR4_VMXE) 2241 return -EBUSY; 2242 2243 /* 2244 * This can happen if we hot-added a CPU but failed to allocate 2245 * VP assist page for it. 2246 */ 2247 if (static_branch_unlikely(&enable_evmcs) && 2248 !hv_get_vp_assist_page(cpu)) 2249 return -EFAULT; 2250 2251 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2252 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2253 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2254 2255 /* 2256 * Now we can enable the vmclear operation in kdump 2257 * since the loaded_vmcss_on_cpu list on this cpu 2258 * has been initialized. 2259 * 2260 * Though the cpu is not in VMX operation now, there 2261 * is no problem to enable the vmclear operation 2262 * for the loaded_vmcss_on_cpu list is empty! 2263 */ 2264 crash_enable_local_vmclear(cpu); 2265 2266 kvm_cpu_vmxon(phys_addr); 2267 if (enable_ept) 2268 ept_sync_global(); 2269 2270 return 0; 2271 } 2272 2273 static void vmclear_local_loaded_vmcss(void) 2274 { 2275 int cpu = raw_smp_processor_id(); 2276 struct loaded_vmcs *v, *n; 2277 2278 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2279 loaded_vmcss_on_cpu_link) 2280 __loaded_vmcs_clear(v); 2281 } 2282 2283 2284 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2285 * tricks. 2286 */ 2287 static void kvm_cpu_vmxoff(void) 2288 { 2289 asm volatile (__ex("vmxoff")); 2290 2291 intel_pt_handle_vmx(0); 2292 cr4_clear_bits(X86_CR4_VMXE); 2293 } 2294 2295 static void hardware_disable(void) 2296 { 2297 vmclear_local_loaded_vmcss(); 2298 kvm_cpu_vmxoff(); 2299 } 2300 2301 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2302 u32 msr, u32 *result) 2303 { 2304 u32 vmx_msr_low, vmx_msr_high; 2305 u32 ctl = ctl_min | ctl_opt; 2306 2307 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2308 2309 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2310 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2311 2312 /* Ensure minimum (required) set of control bits are supported. */ 2313 if (ctl_min & ~ctl) 2314 return -EIO; 2315 2316 *result = ctl; 2317 return 0; 2318 } 2319 2320 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2321 struct vmx_capability *vmx_cap) 2322 { 2323 u32 vmx_msr_low, vmx_msr_high; 2324 u32 min, opt, min2, opt2; 2325 u32 _pin_based_exec_control = 0; 2326 u32 _cpu_based_exec_control = 0; 2327 u32 _cpu_based_2nd_exec_control = 0; 2328 u32 _vmexit_control = 0; 2329 u32 _vmentry_control = 0; 2330 2331 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2332 min = CPU_BASED_HLT_EXITING | 2333 #ifdef CONFIG_X86_64 2334 CPU_BASED_CR8_LOAD_EXITING | 2335 CPU_BASED_CR8_STORE_EXITING | 2336 #endif 2337 CPU_BASED_CR3_LOAD_EXITING | 2338 CPU_BASED_CR3_STORE_EXITING | 2339 CPU_BASED_UNCOND_IO_EXITING | 2340 CPU_BASED_MOV_DR_EXITING | 2341 CPU_BASED_USE_TSC_OFFSETTING | 2342 CPU_BASED_MWAIT_EXITING | 2343 CPU_BASED_MONITOR_EXITING | 2344 CPU_BASED_INVLPG_EXITING | 2345 CPU_BASED_RDPMC_EXITING; 2346 2347 opt = CPU_BASED_TPR_SHADOW | 2348 CPU_BASED_USE_MSR_BITMAPS | 2349 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2350 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2351 &_cpu_based_exec_control) < 0) 2352 return -EIO; 2353 #ifdef CONFIG_X86_64 2354 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2355 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2356 ~CPU_BASED_CR8_STORE_EXITING; 2357 #endif 2358 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2359 min2 = 0; 2360 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2361 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2362 SECONDARY_EXEC_WBINVD_EXITING | 2363 SECONDARY_EXEC_ENABLE_VPID | 2364 SECONDARY_EXEC_ENABLE_EPT | 2365 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2366 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2367 SECONDARY_EXEC_DESC | 2368 SECONDARY_EXEC_RDTSCP | 2369 SECONDARY_EXEC_ENABLE_INVPCID | 2370 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2371 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2372 SECONDARY_EXEC_SHADOW_VMCS | 2373 SECONDARY_EXEC_XSAVES | 2374 SECONDARY_EXEC_RDSEED_EXITING | 2375 SECONDARY_EXEC_RDRAND_EXITING | 2376 SECONDARY_EXEC_ENABLE_PML | 2377 SECONDARY_EXEC_TSC_SCALING | 2378 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2379 SECONDARY_EXEC_PT_USE_GPA | 2380 SECONDARY_EXEC_PT_CONCEAL_VMX | 2381 SECONDARY_EXEC_ENABLE_VMFUNC | 2382 SECONDARY_EXEC_ENCLS_EXITING; 2383 if (adjust_vmx_controls(min2, opt2, 2384 MSR_IA32_VMX_PROCBASED_CTLS2, 2385 &_cpu_based_2nd_exec_control) < 0) 2386 return -EIO; 2387 } 2388 #ifndef CONFIG_X86_64 2389 if (!(_cpu_based_2nd_exec_control & 2390 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2391 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2392 #endif 2393 2394 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2395 _cpu_based_2nd_exec_control &= ~( 2396 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2397 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2398 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2399 2400 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2401 &vmx_cap->ept, &vmx_cap->vpid); 2402 2403 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2404 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2405 enabled */ 2406 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2407 CPU_BASED_CR3_STORE_EXITING | 2408 CPU_BASED_INVLPG_EXITING); 2409 } else if (vmx_cap->ept) { 2410 vmx_cap->ept = 0; 2411 pr_warn_once("EPT CAP should not exist if not support " 2412 "1-setting enable EPT VM-execution control\n"); 2413 } 2414 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2415 vmx_cap->vpid) { 2416 vmx_cap->vpid = 0; 2417 pr_warn_once("VPID CAP should not exist if not support " 2418 "1-setting enable VPID VM-execution control\n"); 2419 } 2420 2421 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2422 #ifdef CONFIG_X86_64 2423 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2424 #endif 2425 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2426 VM_EXIT_LOAD_IA32_PAT | 2427 VM_EXIT_LOAD_IA32_EFER | 2428 VM_EXIT_CLEAR_BNDCFGS | 2429 VM_EXIT_PT_CONCEAL_PIP | 2430 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2431 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2432 &_vmexit_control) < 0) 2433 return -EIO; 2434 2435 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2436 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2437 PIN_BASED_VMX_PREEMPTION_TIMER; 2438 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2439 &_pin_based_exec_control) < 0) 2440 return -EIO; 2441 2442 if (cpu_has_broken_vmx_preemption_timer()) 2443 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2444 if (!(_cpu_based_2nd_exec_control & 2445 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2446 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2447 2448 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2449 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2450 VM_ENTRY_LOAD_IA32_PAT | 2451 VM_ENTRY_LOAD_IA32_EFER | 2452 VM_ENTRY_LOAD_BNDCFGS | 2453 VM_ENTRY_PT_CONCEAL_PIP | 2454 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2455 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2456 &_vmentry_control) < 0) 2457 return -EIO; 2458 2459 /* 2460 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2461 * can't be used due to an errata where VM Exit may incorrectly clear 2462 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2463 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2464 */ 2465 if (boot_cpu_data.x86 == 0x6) { 2466 switch (boot_cpu_data.x86_model) { 2467 case 26: /* AAK155 */ 2468 case 30: /* AAP115 */ 2469 case 37: /* AAT100 */ 2470 case 44: /* BC86,AAY89,BD102 */ 2471 case 46: /* BA97 */ 2472 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2473 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2474 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2475 "does not work properly. Using workaround\n"); 2476 break; 2477 default: 2478 break; 2479 } 2480 } 2481 2482 2483 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2484 2485 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2486 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2487 return -EIO; 2488 2489 #ifdef CONFIG_X86_64 2490 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2491 if (vmx_msr_high & (1u<<16)) 2492 return -EIO; 2493 #endif 2494 2495 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2496 if (((vmx_msr_high >> 18) & 15) != 6) 2497 return -EIO; 2498 2499 vmcs_conf->size = vmx_msr_high & 0x1fff; 2500 vmcs_conf->order = get_order(vmcs_conf->size); 2501 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2502 2503 vmcs_conf->revision_id = vmx_msr_low; 2504 2505 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2506 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2507 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2508 vmcs_conf->vmexit_ctrl = _vmexit_control; 2509 vmcs_conf->vmentry_ctrl = _vmentry_control; 2510 2511 if (static_branch_unlikely(&enable_evmcs)) 2512 evmcs_sanitize_exec_ctrls(vmcs_conf); 2513 2514 return 0; 2515 } 2516 2517 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2518 { 2519 int node = cpu_to_node(cpu); 2520 struct page *pages; 2521 struct vmcs *vmcs; 2522 2523 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2524 if (!pages) 2525 return NULL; 2526 vmcs = page_address(pages); 2527 memset(vmcs, 0, vmcs_config.size); 2528 2529 /* KVM supports Enlightened VMCS v1 only */ 2530 if (static_branch_unlikely(&enable_evmcs)) 2531 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2532 else 2533 vmcs->hdr.revision_id = vmcs_config.revision_id; 2534 2535 if (shadow) 2536 vmcs->hdr.shadow_vmcs = 1; 2537 return vmcs; 2538 } 2539 2540 void free_vmcs(struct vmcs *vmcs) 2541 { 2542 free_pages((unsigned long)vmcs, vmcs_config.order); 2543 } 2544 2545 /* 2546 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2547 */ 2548 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2549 { 2550 if (!loaded_vmcs->vmcs) 2551 return; 2552 loaded_vmcs_clear(loaded_vmcs); 2553 free_vmcs(loaded_vmcs->vmcs); 2554 loaded_vmcs->vmcs = NULL; 2555 if (loaded_vmcs->msr_bitmap) 2556 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2557 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2558 } 2559 2560 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2561 { 2562 loaded_vmcs->vmcs = alloc_vmcs(false); 2563 if (!loaded_vmcs->vmcs) 2564 return -ENOMEM; 2565 2566 loaded_vmcs->shadow_vmcs = NULL; 2567 loaded_vmcs->hv_timer_soft_disabled = false; 2568 loaded_vmcs_init(loaded_vmcs); 2569 2570 if (cpu_has_vmx_msr_bitmap()) { 2571 loaded_vmcs->msr_bitmap = (unsigned long *) 2572 __get_free_page(GFP_KERNEL_ACCOUNT); 2573 if (!loaded_vmcs->msr_bitmap) 2574 goto out_vmcs; 2575 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2576 2577 if (IS_ENABLED(CONFIG_HYPERV) && 2578 static_branch_unlikely(&enable_evmcs) && 2579 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2580 struct hv_enlightened_vmcs *evmcs = 2581 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2582 2583 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2584 } 2585 } 2586 2587 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2588 memset(&loaded_vmcs->controls_shadow, 0, 2589 sizeof(struct vmcs_controls_shadow)); 2590 2591 return 0; 2592 2593 out_vmcs: 2594 free_loaded_vmcs(loaded_vmcs); 2595 return -ENOMEM; 2596 } 2597 2598 static void free_kvm_area(void) 2599 { 2600 int cpu; 2601 2602 for_each_possible_cpu(cpu) { 2603 free_vmcs(per_cpu(vmxarea, cpu)); 2604 per_cpu(vmxarea, cpu) = NULL; 2605 } 2606 } 2607 2608 static __init int alloc_kvm_area(void) 2609 { 2610 int cpu; 2611 2612 for_each_possible_cpu(cpu) { 2613 struct vmcs *vmcs; 2614 2615 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2616 if (!vmcs) { 2617 free_kvm_area(); 2618 return -ENOMEM; 2619 } 2620 2621 /* 2622 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2623 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2624 * revision_id reported by MSR_IA32_VMX_BASIC. 2625 * 2626 * However, even though not explicitly documented by 2627 * TLFS, VMXArea passed as VMXON argument should 2628 * still be marked with revision_id reported by 2629 * physical CPU. 2630 */ 2631 if (static_branch_unlikely(&enable_evmcs)) 2632 vmcs->hdr.revision_id = vmcs_config.revision_id; 2633 2634 per_cpu(vmxarea, cpu) = vmcs; 2635 } 2636 return 0; 2637 } 2638 2639 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2640 struct kvm_segment *save) 2641 { 2642 if (!emulate_invalid_guest_state) { 2643 /* 2644 * CS and SS RPL should be equal during guest entry according 2645 * to VMX spec, but in reality it is not always so. Since vcpu 2646 * is in the middle of the transition from real mode to 2647 * protected mode it is safe to assume that RPL 0 is a good 2648 * default value. 2649 */ 2650 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2651 save->selector &= ~SEGMENT_RPL_MASK; 2652 save->dpl = save->selector & SEGMENT_RPL_MASK; 2653 save->s = 1; 2654 } 2655 vmx_set_segment(vcpu, save, seg); 2656 } 2657 2658 static void enter_pmode(struct kvm_vcpu *vcpu) 2659 { 2660 unsigned long flags; 2661 struct vcpu_vmx *vmx = to_vmx(vcpu); 2662 2663 /* 2664 * Update real mode segment cache. It may be not up-to-date if sement 2665 * register was written while vcpu was in a guest mode. 2666 */ 2667 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2668 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2669 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2670 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2671 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2672 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2673 2674 vmx->rmode.vm86_active = 0; 2675 2676 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2677 2678 flags = vmcs_readl(GUEST_RFLAGS); 2679 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2680 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2681 vmcs_writel(GUEST_RFLAGS, flags); 2682 2683 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2684 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2685 2686 update_exception_bitmap(vcpu); 2687 2688 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2689 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2690 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2691 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2692 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2693 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2694 } 2695 2696 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2697 { 2698 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2699 struct kvm_segment var = *save; 2700 2701 var.dpl = 0x3; 2702 if (seg == VCPU_SREG_CS) 2703 var.type = 0x3; 2704 2705 if (!emulate_invalid_guest_state) { 2706 var.selector = var.base >> 4; 2707 var.base = var.base & 0xffff0; 2708 var.limit = 0xffff; 2709 var.g = 0; 2710 var.db = 0; 2711 var.present = 1; 2712 var.s = 1; 2713 var.l = 0; 2714 var.unusable = 0; 2715 var.type = 0x3; 2716 var.avl = 0; 2717 if (save->base & 0xf) 2718 printk_once(KERN_WARNING "kvm: segment base is not " 2719 "paragraph aligned when entering " 2720 "protected mode (seg=%d)", seg); 2721 } 2722 2723 vmcs_write16(sf->selector, var.selector); 2724 vmcs_writel(sf->base, var.base); 2725 vmcs_write32(sf->limit, var.limit); 2726 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2727 } 2728 2729 static void enter_rmode(struct kvm_vcpu *vcpu) 2730 { 2731 unsigned long flags; 2732 struct vcpu_vmx *vmx = to_vmx(vcpu); 2733 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2734 2735 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2736 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2737 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2738 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2739 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2740 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2741 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2742 2743 vmx->rmode.vm86_active = 1; 2744 2745 /* 2746 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2747 * vcpu. Warn the user that an update is overdue. 2748 */ 2749 if (!kvm_vmx->tss_addr) 2750 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2751 "called before entering vcpu\n"); 2752 2753 vmx_segment_cache_clear(vmx); 2754 2755 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2756 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2757 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2758 2759 flags = vmcs_readl(GUEST_RFLAGS); 2760 vmx->rmode.save_rflags = flags; 2761 2762 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2763 2764 vmcs_writel(GUEST_RFLAGS, flags); 2765 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2766 update_exception_bitmap(vcpu); 2767 2768 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2769 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2770 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2771 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2772 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2773 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2774 2775 kvm_mmu_reset_context(vcpu); 2776 } 2777 2778 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2779 { 2780 struct vcpu_vmx *vmx = to_vmx(vcpu); 2781 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2782 2783 if (!msr) 2784 return; 2785 2786 vcpu->arch.efer = efer; 2787 if (efer & EFER_LMA) { 2788 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2789 msr->data = efer; 2790 } else { 2791 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2792 2793 msr->data = efer & ~EFER_LME; 2794 } 2795 setup_msrs(vmx); 2796 } 2797 2798 #ifdef CONFIG_X86_64 2799 2800 static void enter_lmode(struct kvm_vcpu *vcpu) 2801 { 2802 u32 guest_tr_ar; 2803 2804 vmx_segment_cache_clear(to_vmx(vcpu)); 2805 2806 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2807 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2808 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2809 __func__); 2810 vmcs_write32(GUEST_TR_AR_BYTES, 2811 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2812 | VMX_AR_TYPE_BUSY_64_TSS); 2813 } 2814 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2815 } 2816 2817 static void exit_lmode(struct kvm_vcpu *vcpu) 2818 { 2819 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2820 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2821 } 2822 2823 #endif 2824 2825 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2826 { 2827 int vpid = to_vmx(vcpu)->vpid; 2828 2829 if (!vpid_sync_vcpu_addr(vpid, addr)) 2830 vpid_sync_context(vpid); 2831 2832 /* 2833 * If VPIDs are not supported or enabled, then the above is a no-op. 2834 * But we don't really need a TLB flush in that case anyway, because 2835 * each VM entry/exit includes an implicit flush when VPID is 0. 2836 */ 2837 } 2838 2839 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2840 { 2841 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2842 2843 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2844 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2845 } 2846 2847 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2848 { 2849 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2850 2851 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2852 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2853 } 2854 2855 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2856 { 2857 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2858 2859 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2860 return; 2861 2862 if (is_pae_paging(vcpu)) { 2863 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2864 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2865 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2866 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2867 } 2868 } 2869 2870 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2871 { 2872 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2873 2874 if (is_pae_paging(vcpu)) { 2875 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2876 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2877 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2878 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2879 } 2880 2881 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2882 } 2883 2884 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2885 unsigned long cr0, 2886 struct kvm_vcpu *vcpu) 2887 { 2888 struct vcpu_vmx *vmx = to_vmx(vcpu); 2889 2890 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2891 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2892 if (!(cr0 & X86_CR0_PG)) { 2893 /* From paging/starting to nonpaging */ 2894 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2895 CPU_BASED_CR3_STORE_EXITING); 2896 vcpu->arch.cr0 = cr0; 2897 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2898 } else if (!is_paging(vcpu)) { 2899 /* From nonpaging to paging */ 2900 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2901 CPU_BASED_CR3_STORE_EXITING); 2902 vcpu->arch.cr0 = cr0; 2903 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2904 } 2905 2906 if (!(cr0 & X86_CR0_WP)) 2907 *hw_cr0 &= ~X86_CR0_WP; 2908 } 2909 2910 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2911 { 2912 struct vcpu_vmx *vmx = to_vmx(vcpu); 2913 unsigned long hw_cr0; 2914 2915 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2916 if (enable_unrestricted_guest) 2917 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2918 else { 2919 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2920 2921 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2922 enter_pmode(vcpu); 2923 2924 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2925 enter_rmode(vcpu); 2926 } 2927 2928 #ifdef CONFIG_X86_64 2929 if (vcpu->arch.efer & EFER_LME) { 2930 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2931 enter_lmode(vcpu); 2932 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2933 exit_lmode(vcpu); 2934 } 2935 #endif 2936 2937 if (enable_ept && !enable_unrestricted_guest) 2938 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2939 2940 vmcs_writel(CR0_READ_SHADOW, cr0); 2941 vmcs_writel(GUEST_CR0, hw_cr0); 2942 vcpu->arch.cr0 = cr0; 2943 2944 /* depends on vcpu->arch.cr0 to be set to a new value */ 2945 vmx->emulation_required = emulation_required(vcpu); 2946 } 2947 2948 static int get_ept_level(struct kvm_vcpu *vcpu) 2949 { 2950 /* Nested EPT currently only supports 4-level walks. */ 2951 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu))) 2952 return 4; 2953 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2954 return 5; 2955 return 4; 2956 } 2957 2958 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2959 { 2960 u64 eptp = VMX_EPTP_MT_WB; 2961 2962 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2963 2964 if (enable_ept_ad_bits && 2965 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2966 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2967 eptp |= (root_hpa & PAGE_MASK); 2968 2969 return eptp; 2970 } 2971 2972 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 2973 { 2974 struct kvm *kvm = vcpu->kvm; 2975 bool update_guest_cr3 = true; 2976 unsigned long guest_cr3; 2977 u64 eptp; 2978 2979 guest_cr3 = cr3; 2980 if (enable_ept) { 2981 eptp = construct_eptp(vcpu, cr3); 2982 vmcs_write64(EPT_POINTER, eptp); 2983 2984 if (kvm_x86_ops->tlb_remote_flush) { 2985 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2986 to_vmx(vcpu)->ept_pointer = eptp; 2987 to_kvm_vmx(kvm)->ept_pointers_match 2988 = EPT_POINTERS_CHECK; 2989 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2990 } 2991 2992 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 2993 if (is_guest_mode(vcpu)) 2994 update_guest_cr3 = false; 2995 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 2996 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 2997 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 2998 guest_cr3 = vcpu->arch.cr3; 2999 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3000 update_guest_cr3 = false; 3001 ept_load_pdptrs(vcpu); 3002 } 3003 3004 if (update_guest_cr3) 3005 vmcs_writel(GUEST_CR3, guest_cr3); 3006 } 3007 3008 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3009 { 3010 struct vcpu_vmx *vmx = to_vmx(vcpu); 3011 /* 3012 * Pass through host's Machine Check Enable value to hw_cr4, which 3013 * is in force while we are in guest mode. Do not let guests control 3014 * this bit, even if host CR4.MCE == 0. 3015 */ 3016 unsigned long hw_cr4; 3017 3018 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3019 if (enable_unrestricted_guest) 3020 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3021 else if (vmx->rmode.vm86_active) 3022 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3023 else 3024 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3025 3026 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3027 if (cr4 & X86_CR4_UMIP) { 3028 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3029 hw_cr4 &= ~X86_CR4_UMIP; 3030 } else if (!is_guest_mode(vcpu) || 3031 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3032 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3033 } 3034 } 3035 3036 if (cr4 & X86_CR4_VMXE) { 3037 /* 3038 * To use VMXON (and later other VMX instructions), a guest 3039 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3040 * So basically the check on whether to allow nested VMX 3041 * is here. We operate under the default treatment of SMM, 3042 * so VMX cannot be enabled under SMM. 3043 */ 3044 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3045 return 1; 3046 } 3047 3048 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3049 return 1; 3050 3051 vcpu->arch.cr4 = cr4; 3052 3053 if (!enable_unrestricted_guest) { 3054 if (enable_ept) { 3055 if (!is_paging(vcpu)) { 3056 hw_cr4 &= ~X86_CR4_PAE; 3057 hw_cr4 |= X86_CR4_PSE; 3058 } else if (!(cr4 & X86_CR4_PAE)) { 3059 hw_cr4 &= ~X86_CR4_PAE; 3060 } 3061 } 3062 3063 /* 3064 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3065 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3066 * to be manually disabled when guest switches to non-paging 3067 * mode. 3068 * 3069 * If !enable_unrestricted_guest, the CPU is always running 3070 * with CR0.PG=1 and CR4 needs to be modified. 3071 * If enable_unrestricted_guest, the CPU automatically 3072 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3073 */ 3074 if (!is_paging(vcpu)) 3075 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3076 } 3077 3078 vmcs_writel(CR4_READ_SHADOW, cr4); 3079 vmcs_writel(GUEST_CR4, hw_cr4); 3080 return 0; 3081 } 3082 3083 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3084 { 3085 struct vcpu_vmx *vmx = to_vmx(vcpu); 3086 u32 ar; 3087 3088 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3089 *var = vmx->rmode.segs[seg]; 3090 if (seg == VCPU_SREG_TR 3091 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3092 return; 3093 var->base = vmx_read_guest_seg_base(vmx, seg); 3094 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3095 return; 3096 } 3097 var->base = vmx_read_guest_seg_base(vmx, seg); 3098 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3099 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3100 ar = vmx_read_guest_seg_ar(vmx, seg); 3101 var->unusable = (ar >> 16) & 1; 3102 var->type = ar & 15; 3103 var->s = (ar >> 4) & 1; 3104 var->dpl = (ar >> 5) & 3; 3105 /* 3106 * Some userspaces do not preserve unusable property. Since usable 3107 * segment has to be present according to VMX spec we can use present 3108 * property to amend userspace bug by making unusable segment always 3109 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3110 * segment as unusable. 3111 */ 3112 var->present = !var->unusable; 3113 var->avl = (ar >> 12) & 1; 3114 var->l = (ar >> 13) & 1; 3115 var->db = (ar >> 14) & 1; 3116 var->g = (ar >> 15) & 1; 3117 } 3118 3119 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3120 { 3121 struct kvm_segment s; 3122 3123 if (to_vmx(vcpu)->rmode.vm86_active) { 3124 vmx_get_segment(vcpu, &s, seg); 3125 return s.base; 3126 } 3127 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3128 } 3129 3130 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3131 { 3132 struct vcpu_vmx *vmx = to_vmx(vcpu); 3133 3134 if (unlikely(vmx->rmode.vm86_active)) 3135 return 0; 3136 else { 3137 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3138 return VMX_AR_DPL(ar); 3139 } 3140 } 3141 3142 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3143 { 3144 u32 ar; 3145 3146 if (var->unusable || !var->present) 3147 ar = 1 << 16; 3148 else { 3149 ar = var->type & 15; 3150 ar |= (var->s & 1) << 4; 3151 ar |= (var->dpl & 3) << 5; 3152 ar |= (var->present & 1) << 7; 3153 ar |= (var->avl & 1) << 12; 3154 ar |= (var->l & 1) << 13; 3155 ar |= (var->db & 1) << 14; 3156 ar |= (var->g & 1) << 15; 3157 } 3158 3159 return ar; 3160 } 3161 3162 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3163 { 3164 struct vcpu_vmx *vmx = to_vmx(vcpu); 3165 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3166 3167 vmx_segment_cache_clear(vmx); 3168 3169 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3170 vmx->rmode.segs[seg] = *var; 3171 if (seg == VCPU_SREG_TR) 3172 vmcs_write16(sf->selector, var->selector); 3173 else if (var->s) 3174 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3175 goto out; 3176 } 3177 3178 vmcs_writel(sf->base, var->base); 3179 vmcs_write32(sf->limit, var->limit); 3180 vmcs_write16(sf->selector, var->selector); 3181 3182 /* 3183 * Fix the "Accessed" bit in AR field of segment registers for older 3184 * qemu binaries. 3185 * IA32 arch specifies that at the time of processor reset the 3186 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3187 * is setting it to 0 in the userland code. This causes invalid guest 3188 * state vmexit when "unrestricted guest" mode is turned on. 3189 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3190 * tree. Newer qemu binaries with that qemu fix would not need this 3191 * kvm hack. 3192 */ 3193 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3194 var->type |= 0x1; /* Accessed */ 3195 3196 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3197 3198 out: 3199 vmx->emulation_required = emulation_required(vcpu); 3200 } 3201 3202 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3203 { 3204 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3205 3206 *db = (ar >> 14) & 1; 3207 *l = (ar >> 13) & 1; 3208 } 3209 3210 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3211 { 3212 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3213 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3214 } 3215 3216 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3217 { 3218 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3219 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3220 } 3221 3222 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3223 { 3224 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3225 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3226 } 3227 3228 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3229 { 3230 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3231 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3232 } 3233 3234 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3235 { 3236 struct kvm_segment var; 3237 u32 ar; 3238 3239 vmx_get_segment(vcpu, &var, seg); 3240 var.dpl = 0x3; 3241 if (seg == VCPU_SREG_CS) 3242 var.type = 0x3; 3243 ar = vmx_segment_access_rights(&var); 3244 3245 if (var.base != (var.selector << 4)) 3246 return false; 3247 if (var.limit != 0xffff) 3248 return false; 3249 if (ar != 0xf3) 3250 return false; 3251 3252 return true; 3253 } 3254 3255 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3256 { 3257 struct kvm_segment cs; 3258 unsigned int cs_rpl; 3259 3260 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3261 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3262 3263 if (cs.unusable) 3264 return false; 3265 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3266 return false; 3267 if (!cs.s) 3268 return false; 3269 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3270 if (cs.dpl > cs_rpl) 3271 return false; 3272 } else { 3273 if (cs.dpl != cs_rpl) 3274 return false; 3275 } 3276 if (!cs.present) 3277 return false; 3278 3279 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3280 return true; 3281 } 3282 3283 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3284 { 3285 struct kvm_segment ss; 3286 unsigned int ss_rpl; 3287 3288 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3289 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3290 3291 if (ss.unusable) 3292 return true; 3293 if (ss.type != 3 && ss.type != 7) 3294 return false; 3295 if (!ss.s) 3296 return false; 3297 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3298 return false; 3299 if (!ss.present) 3300 return false; 3301 3302 return true; 3303 } 3304 3305 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3306 { 3307 struct kvm_segment var; 3308 unsigned int rpl; 3309 3310 vmx_get_segment(vcpu, &var, seg); 3311 rpl = var.selector & SEGMENT_RPL_MASK; 3312 3313 if (var.unusable) 3314 return true; 3315 if (!var.s) 3316 return false; 3317 if (!var.present) 3318 return false; 3319 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3320 if (var.dpl < rpl) /* DPL < RPL */ 3321 return false; 3322 } 3323 3324 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3325 * rights flags 3326 */ 3327 return true; 3328 } 3329 3330 static bool tr_valid(struct kvm_vcpu *vcpu) 3331 { 3332 struct kvm_segment tr; 3333 3334 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3335 3336 if (tr.unusable) 3337 return false; 3338 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3339 return false; 3340 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3341 return false; 3342 if (!tr.present) 3343 return false; 3344 3345 return true; 3346 } 3347 3348 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3349 { 3350 struct kvm_segment ldtr; 3351 3352 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3353 3354 if (ldtr.unusable) 3355 return true; 3356 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3357 return false; 3358 if (ldtr.type != 2) 3359 return false; 3360 if (!ldtr.present) 3361 return false; 3362 3363 return true; 3364 } 3365 3366 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3367 { 3368 struct kvm_segment cs, ss; 3369 3370 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3371 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3372 3373 return ((cs.selector & SEGMENT_RPL_MASK) == 3374 (ss.selector & SEGMENT_RPL_MASK)); 3375 } 3376 3377 /* 3378 * Check if guest state is valid. Returns true if valid, false if 3379 * not. 3380 * We assume that registers are always usable 3381 */ 3382 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3383 { 3384 if (enable_unrestricted_guest) 3385 return true; 3386 3387 /* real mode guest state checks */ 3388 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3389 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3390 return false; 3391 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3392 return false; 3393 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3394 return false; 3395 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3396 return false; 3397 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3398 return false; 3399 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3400 return false; 3401 } else { 3402 /* protected mode guest state checks */ 3403 if (!cs_ss_rpl_check(vcpu)) 3404 return false; 3405 if (!code_segment_valid(vcpu)) 3406 return false; 3407 if (!stack_segment_valid(vcpu)) 3408 return false; 3409 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3410 return false; 3411 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3412 return false; 3413 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3414 return false; 3415 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3416 return false; 3417 if (!tr_valid(vcpu)) 3418 return false; 3419 if (!ldtr_valid(vcpu)) 3420 return false; 3421 } 3422 /* TODO: 3423 * - Add checks on RIP 3424 * - Add checks on RFLAGS 3425 */ 3426 3427 return true; 3428 } 3429 3430 static int init_rmode_tss(struct kvm *kvm) 3431 { 3432 gfn_t fn; 3433 u16 data = 0; 3434 int idx, r; 3435 3436 idx = srcu_read_lock(&kvm->srcu); 3437 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3438 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3439 if (r < 0) 3440 goto out; 3441 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3442 r = kvm_write_guest_page(kvm, fn++, &data, 3443 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3444 if (r < 0) 3445 goto out; 3446 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3447 if (r < 0) 3448 goto out; 3449 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3450 if (r < 0) 3451 goto out; 3452 data = ~0; 3453 r = kvm_write_guest_page(kvm, fn, &data, 3454 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3455 sizeof(u8)); 3456 out: 3457 srcu_read_unlock(&kvm->srcu, idx); 3458 return r; 3459 } 3460 3461 static int init_rmode_identity_map(struct kvm *kvm) 3462 { 3463 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3464 int i, r = 0; 3465 kvm_pfn_t identity_map_pfn; 3466 u32 tmp; 3467 3468 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3469 mutex_lock(&kvm->slots_lock); 3470 3471 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3472 goto out; 3473 3474 if (!kvm_vmx->ept_identity_map_addr) 3475 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3476 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3477 3478 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3479 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3480 if (r < 0) 3481 goto out; 3482 3483 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3484 if (r < 0) 3485 goto out; 3486 /* Set up identity-mapping pagetable for EPT in real mode */ 3487 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3488 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3489 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3490 r = kvm_write_guest_page(kvm, identity_map_pfn, 3491 &tmp, i * sizeof(tmp), sizeof(tmp)); 3492 if (r < 0) 3493 goto out; 3494 } 3495 kvm_vmx->ept_identity_pagetable_done = true; 3496 3497 out: 3498 mutex_unlock(&kvm->slots_lock); 3499 return r; 3500 } 3501 3502 static void seg_setup(int seg) 3503 { 3504 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3505 unsigned int ar; 3506 3507 vmcs_write16(sf->selector, 0); 3508 vmcs_writel(sf->base, 0); 3509 vmcs_write32(sf->limit, 0xffff); 3510 ar = 0x93; 3511 if (seg == VCPU_SREG_CS) 3512 ar |= 0x08; /* code segment */ 3513 3514 vmcs_write32(sf->ar_bytes, ar); 3515 } 3516 3517 static int alloc_apic_access_page(struct kvm *kvm) 3518 { 3519 struct page *page; 3520 int r = 0; 3521 3522 mutex_lock(&kvm->slots_lock); 3523 if (kvm->arch.apic_access_page_done) 3524 goto out; 3525 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3526 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3527 if (r) 3528 goto out; 3529 3530 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3531 if (is_error_page(page)) { 3532 r = -EFAULT; 3533 goto out; 3534 } 3535 3536 /* 3537 * Do not pin the page in memory, so that memory hot-unplug 3538 * is able to migrate it. 3539 */ 3540 put_page(page); 3541 kvm->arch.apic_access_page_done = true; 3542 out: 3543 mutex_unlock(&kvm->slots_lock); 3544 return r; 3545 } 3546 3547 int allocate_vpid(void) 3548 { 3549 int vpid; 3550 3551 if (!enable_vpid) 3552 return 0; 3553 spin_lock(&vmx_vpid_lock); 3554 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3555 if (vpid < VMX_NR_VPIDS) 3556 __set_bit(vpid, vmx_vpid_bitmap); 3557 else 3558 vpid = 0; 3559 spin_unlock(&vmx_vpid_lock); 3560 return vpid; 3561 } 3562 3563 void free_vpid(int vpid) 3564 { 3565 if (!enable_vpid || vpid == 0) 3566 return; 3567 spin_lock(&vmx_vpid_lock); 3568 __clear_bit(vpid, vmx_vpid_bitmap); 3569 spin_unlock(&vmx_vpid_lock); 3570 } 3571 3572 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3573 u32 msr, int type) 3574 { 3575 int f = sizeof(unsigned long); 3576 3577 if (!cpu_has_vmx_msr_bitmap()) 3578 return; 3579 3580 if (static_branch_unlikely(&enable_evmcs)) 3581 evmcs_touch_msr_bitmap(); 3582 3583 /* 3584 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3585 * have the write-low and read-high bitmap offsets the wrong way round. 3586 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3587 */ 3588 if (msr <= 0x1fff) { 3589 if (type & MSR_TYPE_R) 3590 /* read-low */ 3591 __clear_bit(msr, msr_bitmap + 0x000 / f); 3592 3593 if (type & MSR_TYPE_W) 3594 /* write-low */ 3595 __clear_bit(msr, msr_bitmap + 0x800 / f); 3596 3597 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3598 msr &= 0x1fff; 3599 if (type & MSR_TYPE_R) 3600 /* read-high */ 3601 __clear_bit(msr, msr_bitmap + 0x400 / f); 3602 3603 if (type & MSR_TYPE_W) 3604 /* write-high */ 3605 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3606 3607 } 3608 } 3609 3610 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3611 u32 msr, int type) 3612 { 3613 int f = sizeof(unsigned long); 3614 3615 if (!cpu_has_vmx_msr_bitmap()) 3616 return; 3617 3618 if (static_branch_unlikely(&enable_evmcs)) 3619 evmcs_touch_msr_bitmap(); 3620 3621 /* 3622 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3623 * have the write-low and read-high bitmap offsets the wrong way round. 3624 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3625 */ 3626 if (msr <= 0x1fff) { 3627 if (type & MSR_TYPE_R) 3628 /* read-low */ 3629 __set_bit(msr, msr_bitmap + 0x000 / f); 3630 3631 if (type & MSR_TYPE_W) 3632 /* write-low */ 3633 __set_bit(msr, msr_bitmap + 0x800 / f); 3634 3635 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3636 msr &= 0x1fff; 3637 if (type & MSR_TYPE_R) 3638 /* read-high */ 3639 __set_bit(msr, msr_bitmap + 0x400 / f); 3640 3641 if (type & MSR_TYPE_W) 3642 /* write-high */ 3643 __set_bit(msr, msr_bitmap + 0xc00 / f); 3644 3645 } 3646 } 3647 3648 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3649 u32 msr, int type, bool value) 3650 { 3651 if (value) 3652 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3653 else 3654 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3655 } 3656 3657 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3658 { 3659 u8 mode = 0; 3660 3661 if (cpu_has_secondary_exec_ctrls() && 3662 (secondary_exec_controls_get(to_vmx(vcpu)) & 3663 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3664 mode |= MSR_BITMAP_MODE_X2APIC; 3665 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3666 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3667 } 3668 3669 return mode; 3670 } 3671 3672 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3673 u8 mode) 3674 { 3675 int msr; 3676 3677 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3678 unsigned word = msr / BITS_PER_LONG; 3679 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3680 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3681 } 3682 3683 if (mode & MSR_BITMAP_MODE_X2APIC) { 3684 /* 3685 * TPR reads and writes can be virtualized even if virtual interrupt 3686 * delivery is not in use. 3687 */ 3688 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3689 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3690 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3691 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3692 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3693 } 3694 } 3695 } 3696 3697 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3698 { 3699 struct vcpu_vmx *vmx = to_vmx(vcpu); 3700 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3701 u8 mode = vmx_msr_bitmap_mode(vcpu); 3702 u8 changed = mode ^ vmx->msr_bitmap_mode; 3703 3704 if (!changed) 3705 return; 3706 3707 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3708 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3709 3710 vmx->msr_bitmap_mode = mode; 3711 } 3712 3713 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3714 { 3715 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3716 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3717 u32 i; 3718 3719 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3720 MSR_TYPE_RW, flag); 3721 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3722 MSR_TYPE_RW, flag); 3723 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3724 MSR_TYPE_RW, flag); 3725 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3726 MSR_TYPE_RW, flag); 3727 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3728 vmx_set_intercept_for_msr(msr_bitmap, 3729 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3730 vmx_set_intercept_for_msr(msr_bitmap, 3731 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3732 } 3733 } 3734 3735 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3736 { 3737 struct vcpu_vmx *vmx = to_vmx(vcpu); 3738 void *vapic_page; 3739 u32 vppr; 3740 int rvi; 3741 3742 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3743 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3744 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3745 return false; 3746 3747 rvi = vmx_get_rvi(); 3748 3749 vapic_page = vmx->nested.virtual_apic_map.hva; 3750 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3751 3752 return ((rvi & 0xf0) > (vppr & 0xf0)); 3753 } 3754 3755 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3756 bool nested) 3757 { 3758 #ifdef CONFIG_SMP 3759 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3760 3761 if (vcpu->mode == IN_GUEST_MODE) { 3762 /* 3763 * The vector of interrupt to be delivered to vcpu had 3764 * been set in PIR before this function. 3765 * 3766 * Following cases will be reached in this block, and 3767 * we always send a notification event in all cases as 3768 * explained below. 3769 * 3770 * Case 1: vcpu keeps in non-root mode. Sending a 3771 * notification event posts the interrupt to vcpu. 3772 * 3773 * Case 2: vcpu exits to root mode and is still 3774 * runnable. PIR will be synced to vIRR before the 3775 * next vcpu entry. Sending a notification event in 3776 * this case has no effect, as vcpu is not in root 3777 * mode. 3778 * 3779 * Case 3: vcpu exits to root mode and is blocked. 3780 * vcpu_block() has already synced PIR to vIRR and 3781 * never blocks vcpu if vIRR is not cleared. Therefore, 3782 * a blocked vcpu here does not wait for any requested 3783 * interrupts in PIR, and sending a notification event 3784 * which has no effect is safe here. 3785 */ 3786 3787 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3788 return true; 3789 } 3790 #endif 3791 return false; 3792 } 3793 3794 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3795 int vector) 3796 { 3797 struct vcpu_vmx *vmx = to_vmx(vcpu); 3798 3799 if (is_guest_mode(vcpu) && 3800 vector == vmx->nested.posted_intr_nv) { 3801 /* 3802 * If a posted intr is not recognized by hardware, 3803 * we will accomplish it in the next vmentry. 3804 */ 3805 vmx->nested.pi_pending = true; 3806 kvm_make_request(KVM_REQ_EVENT, vcpu); 3807 /* the PIR and ON have been set by L1. */ 3808 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3809 kvm_vcpu_kick(vcpu); 3810 return 0; 3811 } 3812 return -1; 3813 } 3814 /* 3815 * Send interrupt to vcpu via posted interrupt way. 3816 * 1. If target vcpu is running(non-root mode), send posted interrupt 3817 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3818 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3819 * interrupt from PIR in next vmentry. 3820 */ 3821 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3822 { 3823 struct vcpu_vmx *vmx = to_vmx(vcpu); 3824 int r; 3825 3826 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3827 if (!r) 3828 return; 3829 3830 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3831 return; 3832 3833 /* If a previous notification has sent the IPI, nothing to do. */ 3834 if (pi_test_and_set_on(&vmx->pi_desc)) 3835 return; 3836 3837 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3838 kvm_vcpu_kick(vcpu); 3839 } 3840 3841 /* 3842 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3843 * will not change in the lifetime of the guest. 3844 * Note that host-state that does change is set elsewhere. E.g., host-state 3845 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3846 */ 3847 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3848 { 3849 u32 low32, high32; 3850 unsigned long tmpl; 3851 unsigned long cr0, cr3, cr4; 3852 3853 cr0 = read_cr0(); 3854 WARN_ON(cr0 & X86_CR0_TS); 3855 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3856 3857 /* 3858 * Save the most likely value for this task's CR3 in the VMCS. 3859 * We can't use __get_current_cr3_fast() because we're not atomic. 3860 */ 3861 cr3 = __read_cr3(); 3862 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3863 vmx->loaded_vmcs->host_state.cr3 = cr3; 3864 3865 /* Save the most likely value for this task's CR4 in the VMCS. */ 3866 cr4 = cr4_read_shadow(); 3867 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3868 vmx->loaded_vmcs->host_state.cr4 = cr4; 3869 3870 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3871 #ifdef CONFIG_X86_64 3872 /* 3873 * Load null selectors, so we can avoid reloading them in 3874 * vmx_prepare_switch_to_host(), in case userspace uses 3875 * the null selectors too (the expected case). 3876 */ 3877 vmcs_write16(HOST_DS_SELECTOR, 0); 3878 vmcs_write16(HOST_ES_SELECTOR, 0); 3879 #else 3880 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3881 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3882 #endif 3883 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3884 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3885 3886 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3887 3888 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3889 3890 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3891 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3892 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3893 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3894 3895 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3896 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3897 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3898 } 3899 3900 if (cpu_has_load_ia32_efer()) 3901 vmcs_write64(HOST_IA32_EFER, host_efer); 3902 } 3903 3904 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3905 { 3906 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3907 if (enable_ept) 3908 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3909 if (is_guest_mode(&vmx->vcpu)) 3910 vmx->vcpu.arch.cr4_guest_owned_bits &= 3911 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3912 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3913 } 3914 3915 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3916 { 3917 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3918 3919 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3920 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3921 3922 if (!enable_vnmi) 3923 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3924 3925 if (!enable_preemption_timer) 3926 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3927 3928 return pin_based_exec_ctrl; 3929 } 3930 3931 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3932 { 3933 struct vcpu_vmx *vmx = to_vmx(vcpu); 3934 3935 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3936 if (cpu_has_secondary_exec_ctrls()) { 3937 if (kvm_vcpu_apicv_active(vcpu)) 3938 secondary_exec_controls_setbit(vmx, 3939 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3940 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3941 else 3942 secondary_exec_controls_clearbit(vmx, 3943 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3944 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3945 } 3946 3947 if (cpu_has_vmx_msr_bitmap()) 3948 vmx_update_msr_bitmap(vcpu); 3949 } 3950 3951 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3952 { 3953 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3954 3955 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3956 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3957 3958 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3959 exec_control &= ~CPU_BASED_TPR_SHADOW; 3960 #ifdef CONFIG_X86_64 3961 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3962 CPU_BASED_CR8_LOAD_EXITING; 3963 #endif 3964 } 3965 if (!enable_ept) 3966 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3967 CPU_BASED_CR3_LOAD_EXITING | 3968 CPU_BASED_INVLPG_EXITING; 3969 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3970 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3971 CPU_BASED_MONITOR_EXITING); 3972 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3973 exec_control &= ~CPU_BASED_HLT_EXITING; 3974 return exec_control; 3975 } 3976 3977 3978 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 3979 { 3980 struct kvm_vcpu *vcpu = &vmx->vcpu; 3981 3982 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 3983 3984 if (pt_mode == PT_MODE_SYSTEM) 3985 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 3986 if (!cpu_need_virtualize_apic_accesses(vcpu)) 3987 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 3988 if (vmx->vpid == 0) 3989 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 3990 if (!enable_ept) { 3991 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 3992 enable_unrestricted_guest = 0; 3993 } 3994 if (!enable_unrestricted_guest) 3995 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 3996 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 3997 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 3998 if (!kvm_vcpu_apicv_active(vcpu)) 3999 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4000 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4001 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4002 4003 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4004 * in vmx_set_cr4. */ 4005 exec_control &= ~SECONDARY_EXEC_DESC; 4006 4007 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4008 (handle_vmptrld). 4009 We can NOT enable shadow_vmcs here because we don't have yet 4010 a current VMCS12 4011 */ 4012 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4013 4014 if (!enable_pml) 4015 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4016 4017 if (vmx_xsaves_supported()) { 4018 /* Exposing XSAVES only when XSAVE is exposed */ 4019 bool xsaves_enabled = 4020 boot_cpu_has(X86_FEATURE_XSAVE) && 4021 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4022 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4023 4024 vcpu->arch.xsaves_enabled = xsaves_enabled; 4025 4026 if (!xsaves_enabled) 4027 exec_control &= ~SECONDARY_EXEC_XSAVES; 4028 4029 if (nested) { 4030 if (xsaves_enabled) 4031 vmx->nested.msrs.secondary_ctls_high |= 4032 SECONDARY_EXEC_XSAVES; 4033 else 4034 vmx->nested.msrs.secondary_ctls_high &= 4035 ~SECONDARY_EXEC_XSAVES; 4036 } 4037 } 4038 4039 if (vmx_rdtscp_supported()) { 4040 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4041 if (!rdtscp_enabled) 4042 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4043 4044 if (nested) { 4045 if (rdtscp_enabled) 4046 vmx->nested.msrs.secondary_ctls_high |= 4047 SECONDARY_EXEC_RDTSCP; 4048 else 4049 vmx->nested.msrs.secondary_ctls_high &= 4050 ~SECONDARY_EXEC_RDTSCP; 4051 } 4052 } 4053 4054 if (vmx_invpcid_supported()) { 4055 /* Exposing INVPCID only when PCID is exposed */ 4056 bool invpcid_enabled = 4057 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4058 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4059 4060 if (!invpcid_enabled) { 4061 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4062 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4063 } 4064 4065 if (nested) { 4066 if (invpcid_enabled) 4067 vmx->nested.msrs.secondary_ctls_high |= 4068 SECONDARY_EXEC_ENABLE_INVPCID; 4069 else 4070 vmx->nested.msrs.secondary_ctls_high &= 4071 ~SECONDARY_EXEC_ENABLE_INVPCID; 4072 } 4073 } 4074 4075 if (vmx_rdrand_supported()) { 4076 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4077 if (rdrand_enabled) 4078 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4079 4080 if (nested) { 4081 if (rdrand_enabled) 4082 vmx->nested.msrs.secondary_ctls_high |= 4083 SECONDARY_EXEC_RDRAND_EXITING; 4084 else 4085 vmx->nested.msrs.secondary_ctls_high &= 4086 ~SECONDARY_EXEC_RDRAND_EXITING; 4087 } 4088 } 4089 4090 if (vmx_rdseed_supported()) { 4091 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4092 if (rdseed_enabled) 4093 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4094 4095 if (nested) { 4096 if (rdseed_enabled) 4097 vmx->nested.msrs.secondary_ctls_high |= 4098 SECONDARY_EXEC_RDSEED_EXITING; 4099 else 4100 vmx->nested.msrs.secondary_ctls_high &= 4101 ~SECONDARY_EXEC_RDSEED_EXITING; 4102 } 4103 } 4104 4105 if (vmx_waitpkg_supported()) { 4106 bool waitpkg_enabled = 4107 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4108 4109 if (!waitpkg_enabled) 4110 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4111 4112 if (nested) { 4113 if (waitpkg_enabled) 4114 vmx->nested.msrs.secondary_ctls_high |= 4115 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4116 else 4117 vmx->nested.msrs.secondary_ctls_high &= 4118 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4119 } 4120 } 4121 4122 vmx->secondary_exec_control = exec_control; 4123 } 4124 4125 static void ept_set_mmio_spte_mask(void) 4126 { 4127 /* 4128 * EPT Misconfigurations can be generated if the value of bits 2:0 4129 * of an EPT paging-structure entry is 110b (write/execute). 4130 */ 4131 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4132 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4133 } 4134 4135 #define VMX_XSS_EXIT_BITMAP 0 4136 4137 /* 4138 * Noting that the initialization of Guest-state Area of VMCS is in 4139 * vmx_vcpu_reset(). 4140 */ 4141 static void init_vmcs(struct vcpu_vmx *vmx) 4142 { 4143 if (nested) 4144 nested_vmx_set_vmcs_shadowing_bitmap(); 4145 4146 if (cpu_has_vmx_msr_bitmap()) 4147 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4148 4149 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4150 4151 /* Control */ 4152 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4153 4154 exec_controls_set(vmx, vmx_exec_control(vmx)); 4155 4156 if (cpu_has_secondary_exec_ctrls()) { 4157 vmx_compute_secondary_exec_control(vmx); 4158 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4159 } 4160 4161 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4162 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4163 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4164 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4165 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4166 4167 vmcs_write16(GUEST_INTR_STATUS, 0); 4168 4169 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4170 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4171 } 4172 4173 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4174 vmcs_write32(PLE_GAP, ple_gap); 4175 vmx->ple_window = ple_window; 4176 vmx->ple_window_dirty = true; 4177 } 4178 4179 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4180 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4181 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4182 4183 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4184 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4185 vmx_set_constant_host_state(vmx); 4186 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4187 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4188 4189 if (cpu_has_vmx_vmfunc()) 4190 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4191 4192 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4193 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4194 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4195 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4196 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4197 4198 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4199 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4200 4201 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4202 4203 /* 22.2.1, 20.8.1 */ 4204 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4205 4206 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4207 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4208 4209 set_cr4_guest_host_mask(vmx); 4210 4211 if (vmx->vpid != 0) 4212 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4213 4214 if (vmx_xsaves_supported()) 4215 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4216 4217 if (enable_pml) { 4218 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4219 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4220 } 4221 4222 if (cpu_has_vmx_encls_vmexit()) 4223 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4224 4225 if (pt_mode == PT_MODE_HOST_GUEST) { 4226 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4227 /* Bit[6~0] are forced to 1, writes are ignored. */ 4228 vmx->pt_desc.guest.output_mask = 0x7F; 4229 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4230 } 4231 } 4232 4233 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4234 { 4235 struct vcpu_vmx *vmx = to_vmx(vcpu); 4236 struct msr_data apic_base_msr; 4237 u64 cr0; 4238 4239 vmx->rmode.vm86_active = 0; 4240 vmx->spec_ctrl = 0; 4241 4242 vmx->msr_ia32_umwait_control = 0; 4243 4244 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4245 vmx->hv_deadline_tsc = -1; 4246 kvm_set_cr8(vcpu, 0); 4247 4248 if (!init_event) { 4249 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4250 MSR_IA32_APICBASE_ENABLE; 4251 if (kvm_vcpu_is_reset_bsp(vcpu)) 4252 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4253 apic_base_msr.host_initiated = true; 4254 kvm_set_apic_base(vcpu, &apic_base_msr); 4255 } 4256 4257 vmx_segment_cache_clear(vmx); 4258 4259 seg_setup(VCPU_SREG_CS); 4260 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4261 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4262 4263 seg_setup(VCPU_SREG_DS); 4264 seg_setup(VCPU_SREG_ES); 4265 seg_setup(VCPU_SREG_FS); 4266 seg_setup(VCPU_SREG_GS); 4267 seg_setup(VCPU_SREG_SS); 4268 4269 vmcs_write16(GUEST_TR_SELECTOR, 0); 4270 vmcs_writel(GUEST_TR_BASE, 0); 4271 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4272 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4273 4274 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4275 vmcs_writel(GUEST_LDTR_BASE, 0); 4276 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4277 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4278 4279 if (!init_event) { 4280 vmcs_write32(GUEST_SYSENTER_CS, 0); 4281 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4282 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4283 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4284 } 4285 4286 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4287 kvm_rip_write(vcpu, 0xfff0); 4288 4289 vmcs_writel(GUEST_GDTR_BASE, 0); 4290 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4291 4292 vmcs_writel(GUEST_IDTR_BASE, 0); 4293 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4294 4295 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4296 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4297 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4298 if (kvm_mpx_supported()) 4299 vmcs_write64(GUEST_BNDCFGS, 0); 4300 4301 setup_msrs(vmx); 4302 4303 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4304 4305 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4306 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4307 if (cpu_need_tpr_shadow(vcpu)) 4308 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4309 __pa(vcpu->arch.apic->regs)); 4310 vmcs_write32(TPR_THRESHOLD, 0); 4311 } 4312 4313 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4314 4315 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4316 vmx->vcpu.arch.cr0 = cr0; 4317 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4318 vmx_set_cr4(vcpu, 0); 4319 vmx_set_efer(vcpu, 0); 4320 4321 update_exception_bitmap(vcpu); 4322 4323 vpid_sync_context(vmx->vpid); 4324 if (init_event) 4325 vmx_clear_hlt(vcpu); 4326 } 4327 4328 static void enable_irq_window(struct kvm_vcpu *vcpu) 4329 { 4330 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4331 } 4332 4333 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4334 { 4335 if (!enable_vnmi || 4336 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4337 enable_irq_window(vcpu); 4338 return; 4339 } 4340 4341 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4342 } 4343 4344 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4345 { 4346 struct vcpu_vmx *vmx = to_vmx(vcpu); 4347 uint32_t intr; 4348 int irq = vcpu->arch.interrupt.nr; 4349 4350 trace_kvm_inj_virq(irq); 4351 4352 ++vcpu->stat.irq_injections; 4353 if (vmx->rmode.vm86_active) { 4354 int inc_eip = 0; 4355 if (vcpu->arch.interrupt.soft) 4356 inc_eip = vcpu->arch.event_exit_inst_len; 4357 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4358 return; 4359 } 4360 intr = irq | INTR_INFO_VALID_MASK; 4361 if (vcpu->arch.interrupt.soft) { 4362 intr |= INTR_TYPE_SOFT_INTR; 4363 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4364 vmx->vcpu.arch.event_exit_inst_len); 4365 } else 4366 intr |= INTR_TYPE_EXT_INTR; 4367 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4368 4369 vmx_clear_hlt(vcpu); 4370 } 4371 4372 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4373 { 4374 struct vcpu_vmx *vmx = to_vmx(vcpu); 4375 4376 if (!enable_vnmi) { 4377 /* 4378 * Tracking the NMI-blocked state in software is built upon 4379 * finding the next open IRQ window. This, in turn, depends on 4380 * well-behaving guests: They have to keep IRQs disabled at 4381 * least as long as the NMI handler runs. Otherwise we may 4382 * cause NMI nesting, maybe breaking the guest. But as this is 4383 * highly unlikely, we can live with the residual risk. 4384 */ 4385 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4386 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4387 } 4388 4389 ++vcpu->stat.nmi_injections; 4390 vmx->loaded_vmcs->nmi_known_unmasked = false; 4391 4392 if (vmx->rmode.vm86_active) { 4393 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4394 return; 4395 } 4396 4397 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4398 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4399 4400 vmx_clear_hlt(vcpu); 4401 } 4402 4403 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4404 { 4405 struct vcpu_vmx *vmx = to_vmx(vcpu); 4406 bool masked; 4407 4408 if (!enable_vnmi) 4409 return vmx->loaded_vmcs->soft_vnmi_blocked; 4410 if (vmx->loaded_vmcs->nmi_known_unmasked) 4411 return false; 4412 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4413 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4414 return masked; 4415 } 4416 4417 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4418 { 4419 struct vcpu_vmx *vmx = to_vmx(vcpu); 4420 4421 if (!enable_vnmi) { 4422 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4423 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4424 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4425 } 4426 } else { 4427 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4428 if (masked) 4429 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4430 GUEST_INTR_STATE_NMI); 4431 else 4432 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4433 GUEST_INTR_STATE_NMI); 4434 } 4435 } 4436 4437 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4438 { 4439 if (to_vmx(vcpu)->nested.nested_run_pending) 4440 return 0; 4441 4442 if (!enable_vnmi && 4443 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4444 return 0; 4445 4446 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4447 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4448 | GUEST_INTR_STATE_NMI)); 4449 } 4450 4451 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4452 { 4453 return (!to_vmx(vcpu)->nested.nested_run_pending && 4454 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4455 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4456 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4457 } 4458 4459 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4460 { 4461 int ret; 4462 4463 if (enable_unrestricted_guest) 4464 return 0; 4465 4466 mutex_lock(&kvm->slots_lock); 4467 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4468 PAGE_SIZE * 3); 4469 mutex_unlock(&kvm->slots_lock); 4470 4471 if (ret) 4472 return ret; 4473 to_kvm_vmx(kvm)->tss_addr = addr; 4474 return init_rmode_tss(kvm); 4475 } 4476 4477 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4478 { 4479 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4480 return 0; 4481 } 4482 4483 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4484 { 4485 switch (vec) { 4486 case BP_VECTOR: 4487 /* 4488 * Update instruction length as we may reinject the exception 4489 * from user space while in guest debugging mode. 4490 */ 4491 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4492 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4493 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4494 return false; 4495 /* fall through */ 4496 case DB_VECTOR: 4497 if (vcpu->guest_debug & 4498 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4499 return false; 4500 /* fall through */ 4501 case DE_VECTOR: 4502 case OF_VECTOR: 4503 case BR_VECTOR: 4504 case UD_VECTOR: 4505 case DF_VECTOR: 4506 case SS_VECTOR: 4507 case GP_VECTOR: 4508 case MF_VECTOR: 4509 return true; 4510 break; 4511 } 4512 return false; 4513 } 4514 4515 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4516 int vec, u32 err_code) 4517 { 4518 /* 4519 * Instruction with address size override prefix opcode 0x67 4520 * Cause the #SS fault with 0 error code in VM86 mode. 4521 */ 4522 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4523 if (kvm_emulate_instruction(vcpu, 0)) { 4524 if (vcpu->arch.halt_request) { 4525 vcpu->arch.halt_request = 0; 4526 return kvm_vcpu_halt(vcpu); 4527 } 4528 return 1; 4529 } 4530 return 0; 4531 } 4532 4533 /* 4534 * Forward all other exceptions that are valid in real mode. 4535 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4536 * the required debugging infrastructure rework. 4537 */ 4538 kvm_queue_exception(vcpu, vec); 4539 return 1; 4540 } 4541 4542 /* 4543 * Trigger machine check on the host. We assume all the MSRs are already set up 4544 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4545 * We pass a fake environment to the machine check handler because we want 4546 * the guest to be always treated like user space, no matter what context 4547 * it used internally. 4548 */ 4549 static void kvm_machine_check(void) 4550 { 4551 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4552 struct pt_regs regs = { 4553 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4554 .flags = X86_EFLAGS_IF, 4555 }; 4556 4557 do_machine_check(®s, 0); 4558 #endif 4559 } 4560 4561 static int handle_machine_check(struct kvm_vcpu *vcpu) 4562 { 4563 /* handled by vmx_vcpu_run() */ 4564 return 1; 4565 } 4566 4567 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4568 { 4569 struct vcpu_vmx *vmx = to_vmx(vcpu); 4570 struct kvm_run *kvm_run = vcpu->run; 4571 u32 intr_info, ex_no, error_code; 4572 unsigned long cr2, rip, dr6; 4573 u32 vect_info; 4574 4575 vect_info = vmx->idt_vectoring_info; 4576 intr_info = vmx->exit_intr_info; 4577 4578 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4579 return 1; /* handled by handle_exception_nmi_irqoff() */ 4580 4581 if (is_invalid_opcode(intr_info)) 4582 return handle_ud(vcpu); 4583 4584 error_code = 0; 4585 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4586 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4587 4588 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4589 WARN_ON_ONCE(!enable_vmware_backdoor); 4590 4591 /* 4592 * VMware backdoor emulation on #GP interception only handles 4593 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4594 * error code on #GP. 4595 */ 4596 if (error_code) { 4597 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4598 return 1; 4599 } 4600 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4601 } 4602 4603 /* 4604 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4605 * MMIO, it is better to report an internal error. 4606 * See the comments in vmx_handle_exit. 4607 */ 4608 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4609 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4610 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4611 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4612 vcpu->run->internal.ndata = 3; 4613 vcpu->run->internal.data[0] = vect_info; 4614 vcpu->run->internal.data[1] = intr_info; 4615 vcpu->run->internal.data[2] = error_code; 4616 return 0; 4617 } 4618 4619 if (is_page_fault(intr_info)) { 4620 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4621 /* EPT won't cause page fault directly */ 4622 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4623 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4624 } 4625 4626 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4627 4628 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4629 return handle_rmode_exception(vcpu, ex_no, error_code); 4630 4631 switch (ex_no) { 4632 case AC_VECTOR: 4633 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4634 return 1; 4635 case DB_VECTOR: 4636 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4637 if (!(vcpu->guest_debug & 4638 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4639 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4640 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4641 if (is_icebp(intr_info)) 4642 WARN_ON(!skip_emulated_instruction(vcpu)); 4643 4644 kvm_queue_exception(vcpu, DB_VECTOR); 4645 return 1; 4646 } 4647 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4648 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4649 /* fall through */ 4650 case BP_VECTOR: 4651 /* 4652 * Update instruction length as we may reinject #BP from 4653 * user space while in guest debugging mode. Reading it for 4654 * #DB as well causes no harm, it is not used in that case. 4655 */ 4656 vmx->vcpu.arch.event_exit_inst_len = 4657 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4658 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4659 rip = kvm_rip_read(vcpu); 4660 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4661 kvm_run->debug.arch.exception = ex_no; 4662 break; 4663 default: 4664 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4665 kvm_run->ex.exception = ex_no; 4666 kvm_run->ex.error_code = error_code; 4667 break; 4668 } 4669 return 0; 4670 } 4671 4672 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4673 { 4674 ++vcpu->stat.irq_exits; 4675 return 1; 4676 } 4677 4678 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4679 { 4680 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4681 vcpu->mmio_needed = 0; 4682 return 0; 4683 } 4684 4685 static int handle_io(struct kvm_vcpu *vcpu) 4686 { 4687 unsigned long exit_qualification; 4688 int size, in, string; 4689 unsigned port; 4690 4691 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4692 string = (exit_qualification & 16) != 0; 4693 4694 ++vcpu->stat.io_exits; 4695 4696 if (string) 4697 return kvm_emulate_instruction(vcpu, 0); 4698 4699 port = exit_qualification >> 16; 4700 size = (exit_qualification & 7) + 1; 4701 in = (exit_qualification & 8) != 0; 4702 4703 return kvm_fast_pio(vcpu, size, port, in); 4704 } 4705 4706 static void 4707 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4708 { 4709 /* 4710 * Patch in the VMCALL instruction: 4711 */ 4712 hypercall[0] = 0x0f; 4713 hypercall[1] = 0x01; 4714 hypercall[2] = 0xc1; 4715 } 4716 4717 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4718 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4719 { 4720 if (is_guest_mode(vcpu)) { 4721 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4722 unsigned long orig_val = val; 4723 4724 /* 4725 * We get here when L2 changed cr0 in a way that did not change 4726 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4727 * but did change L0 shadowed bits. So we first calculate the 4728 * effective cr0 value that L1 would like to write into the 4729 * hardware. It consists of the L2-owned bits from the new 4730 * value combined with the L1-owned bits from L1's guest_cr0. 4731 */ 4732 val = (val & ~vmcs12->cr0_guest_host_mask) | 4733 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4734 4735 if (!nested_guest_cr0_valid(vcpu, val)) 4736 return 1; 4737 4738 if (kvm_set_cr0(vcpu, val)) 4739 return 1; 4740 vmcs_writel(CR0_READ_SHADOW, orig_val); 4741 return 0; 4742 } else { 4743 if (to_vmx(vcpu)->nested.vmxon && 4744 !nested_host_cr0_valid(vcpu, val)) 4745 return 1; 4746 4747 return kvm_set_cr0(vcpu, val); 4748 } 4749 } 4750 4751 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4752 { 4753 if (is_guest_mode(vcpu)) { 4754 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4755 unsigned long orig_val = val; 4756 4757 /* analogously to handle_set_cr0 */ 4758 val = (val & ~vmcs12->cr4_guest_host_mask) | 4759 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4760 if (kvm_set_cr4(vcpu, val)) 4761 return 1; 4762 vmcs_writel(CR4_READ_SHADOW, orig_val); 4763 return 0; 4764 } else 4765 return kvm_set_cr4(vcpu, val); 4766 } 4767 4768 static int handle_desc(struct kvm_vcpu *vcpu) 4769 { 4770 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4771 return kvm_emulate_instruction(vcpu, 0); 4772 } 4773 4774 static int handle_cr(struct kvm_vcpu *vcpu) 4775 { 4776 unsigned long exit_qualification, val; 4777 int cr; 4778 int reg; 4779 int err; 4780 int ret; 4781 4782 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4783 cr = exit_qualification & 15; 4784 reg = (exit_qualification >> 8) & 15; 4785 switch ((exit_qualification >> 4) & 3) { 4786 case 0: /* mov to cr */ 4787 val = kvm_register_readl(vcpu, reg); 4788 trace_kvm_cr_write(cr, val); 4789 switch (cr) { 4790 case 0: 4791 err = handle_set_cr0(vcpu, val); 4792 return kvm_complete_insn_gp(vcpu, err); 4793 case 3: 4794 WARN_ON_ONCE(enable_unrestricted_guest); 4795 err = kvm_set_cr3(vcpu, val); 4796 return kvm_complete_insn_gp(vcpu, err); 4797 case 4: 4798 err = handle_set_cr4(vcpu, val); 4799 return kvm_complete_insn_gp(vcpu, err); 4800 case 8: { 4801 u8 cr8_prev = kvm_get_cr8(vcpu); 4802 u8 cr8 = (u8)val; 4803 err = kvm_set_cr8(vcpu, cr8); 4804 ret = kvm_complete_insn_gp(vcpu, err); 4805 if (lapic_in_kernel(vcpu)) 4806 return ret; 4807 if (cr8_prev <= cr8) 4808 return ret; 4809 /* 4810 * TODO: we might be squashing a 4811 * KVM_GUESTDBG_SINGLESTEP-triggered 4812 * KVM_EXIT_DEBUG here. 4813 */ 4814 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4815 return 0; 4816 } 4817 } 4818 break; 4819 case 2: /* clts */ 4820 WARN_ONCE(1, "Guest should always own CR0.TS"); 4821 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4822 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4823 return kvm_skip_emulated_instruction(vcpu); 4824 case 1: /*mov from cr*/ 4825 switch (cr) { 4826 case 3: 4827 WARN_ON_ONCE(enable_unrestricted_guest); 4828 val = kvm_read_cr3(vcpu); 4829 kvm_register_write(vcpu, reg, val); 4830 trace_kvm_cr_read(cr, val); 4831 return kvm_skip_emulated_instruction(vcpu); 4832 case 8: 4833 val = kvm_get_cr8(vcpu); 4834 kvm_register_write(vcpu, reg, val); 4835 trace_kvm_cr_read(cr, val); 4836 return kvm_skip_emulated_instruction(vcpu); 4837 } 4838 break; 4839 case 3: /* lmsw */ 4840 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4841 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4842 kvm_lmsw(vcpu, val); 4843 4844 return kvm_skip_emulated_instruction(vcpu); 4845 default: 4846 break; 4847 } 4848 vcpu->run->exit_reason = 0; 4849 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4850 (int)(exit_qualification >> 4) & 3, cr); 4851 return 0; 4852 } 4853 4854 static int handle_dr(struct kvm_vcpu *vcpu) 4855 { 4856 unsigned long exit_qualification; 4857 int dr, dr7, reg; 4858 4859 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4860 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4861 4862 /* First, if DR does not exist, trigger UD */ 4863 if (!kvm_require_dr(vcpu, dr)) 4864 return 1; 4865 4866 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4867 if (!kvm_require_cpl(vcpu, 0)) 4868 return 1; 4869 dr7 = vmcs_readl(GUEST_DR7); 4870 if (dr7 & DR7_GD) { 4871 /* 4872 * As the vm-exit takes precedence over the debug trap, we 4873 * need to emulate the latter, either for the host or the 4874 * guest debugging itself. 4875 */ 4876 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4877 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4878 vcpu->run->debug.arch.dr7 = dr7; 4879 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4880 vcpu->run->debug.arch.exception = DB_VECTOR; 4881 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4882 return 0; 4883 } else { 4884 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4885 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4886 kvm_queue_exception(vcpu, DB_VECTOR); 4887 return 1; 4888 } 4889 } 4890 4891 if (vcpu->guest_debug == 0) { 4892 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4893 4894 /* 4895 * No more DR vmexits; force a reload of the debug registers 4896 * and reenter on this instruction. The next vmexit will 4897 * retrieve the full state of the debug registers. 4898 */ 4899 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4900 return 1; 4901 } 4902 4903 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4904 if (exit_qualification & TYPE_MOV_FROM_DR) { 4905 unsigned long val; 4906 4907 if (kvm_get_dr(vcpu, dr, &val)) 4908 return 1; 4909 kvm_register_write(vcpu, reg, val); 4910 } else 4911 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4912 return 1; 4913 4914 return kvm_skip_emulated_instruction(vcpu); 4915 } 4916 4917 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4918 { 4919 return vcpu->arch.dr6; 4920 } 4921 4922 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4923 { 4924 } 4925 4926 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4927 { 4928 get_debugreg(vcpu->arch.db[0], 0); 4929 get_debugreg(vcpu->arch.db[1], 1); 4930 get_debugreg(vcpu->arch.db[2], 2); 4931 get_debugreg(vcpu->arch.db[3], 3); 4932 get_debugreg(vcpu->arch.dr6, 6); 4933 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4934 4935 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4936 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4937 } 4938 4939 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4940 { 4941 vmcs_writel(GUEST_DR7, val); 4942 } 4943 4944 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4945 { 4946 kvm_apic_update_ppr(vcpu); 4947 return 1; 4948 } 4949 4950 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4951 { 4952 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4953 4954 kvm_make_request(KVM_REQ_EVENT, vcpu); 4955 4956 ++vcpu->stat.irq_window_exits; 4957 return 1; 4958 } 4959 4960 static int handle_vmcall(struct kvm_vcpu *vcpu) 4961 { 4962 return kvm_emulate_hypercall(vcpu); 4963 } 4964 4965 static int handle_invd(struct kvm_vcpu *vcpu) 4966 { 4967 return kvm_emulate_instruction(vcpu, 0); 4968 } 4969 4970 static int handle_invlpg(struct kvm_vcpu *vcpu) 4971 { 4972 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4973 4974 kvm_mmu_invlpg(vcpu, exit_qualification); 4975 return kvm_skip_emulated_instruction(vcpu); 4976 } 4977 4978 static int handle_rdpmc(struct kvm_vcpu *vcpu) 4979 { 4980 int err; 4981 4982 err = kvm_rdpmc(vcpu); 4983 return kvm_complete_insn_gp(vcpu, err); 4984 } 4985 4986 static int handle_wbinvd(struct kvm_vcpu *vcpu) 4987 { 4988 return kvm_emulate_wbinvd(vcpu); 4989 } 4990 4991 static int handle_xsetbv(struct kvm_vcpu *vcpu) 4992 { 4993 u64 new_bv = kvm_read_edx_eax(vcpu); 4994 u32 index = kvm_rcx_read(vcpu); 4995 4996 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 4997 return kvm_skip_emulated_instruction(vcpu); 4998 return 1; 4999 } 5000 5001 static int handle_apic_access(struct kvm_vcpu *vcpu) 5002 { 5003 if (likely(fasteoi)) { 5004 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5005 int access_type, offset; 5006 5007 access_type = exit_qualification & APIC_ACCESS_TYPE; 5008 offset = exit_qualification & APIC_ACCESS_OFFSET; 5009 /* 5010 * Sane guest uses MOV to write EOI, with written value 5011 * not cared. So make a short-circuit here by avoiding 5012 * heavy instruction emulation. 5013 */ 5014 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5015 (offset == APIC_EOI)) { 5016 kvm_lapic_set_eoi(vcpu); 5017 return kvm_skip_emulated_instruction(vcpu); 5018 } 5019 } 5020 return kvm_emulate_instruction(vcpu, 0); 5021 } 5022 5023 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5024 { 5025 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5026 int vector = exit_qualification & 0xff; 5027 5028 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5029 kvm_apic_set_eoi_accelerated(vcpu, vector); 5030 return 1; 5031 } 5032 5033 static int handle_apic_write(struct kvm_vcpu *vcpu) 5034 { 5035 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5036 u32 offset = exit_qualification & 0xfff; 5037 5038 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5039 kvm_apic_write_nodecode(vcpu, offset); 5040 return 1; 5041 } 5042 5043 static int handle_task_switch(struct kvm_vcpu *vcpu) 5044 { 5045 struct vcpu_vmx *vmx = to_vmx(vcpu); 5046 unsigned long exit_qualification; 5047 bool has_error_code = false; 5048 u32 error_code = 0; 5049 u16 tss_selector; 5050 int reason, type, idt_v, idt_index; 5051 5052 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5053 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5054 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5055 5056 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5057 5058 reason = (u32)exit_qualification >> 30; 5059 if (reason == TASK_SWITCH_GATE && idt_v) { 5060 switch (type) { 5061 case INTR_TYPE_NMI_INTR: 5062 vcpu->arch.nmi_injected = false; 5063 vmx_set_nmi_mask(vcpu, true); 5064 break; 5065 case INTR_TYPE_EXT_INTR: 5066 case INTR_TYPE_SOFT_INTR: 5067 kvm_clear_interrupt_queue(vcpu); 5068 break; 5069 case INTR_TYPE_HARD_EXCEPTION: 5070 if (vmx->idt_vectoring_info & 5071 VECTORING_INFO_DELIVER_CODE_MASK) { 5072 has_error_code = true; 5073 error_code = 5074 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5075 } 5076 /* fall through */ 5077 case INTR_TYPE_SOFT_EXCEPTION: 5078 kvm_clear_exception_queue(vcpu); 5079 break; 5080 default: 5081 break; 5082 } 5083 } 5084 tss_selector = exit_qualification; 5085 5086 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5087 type != INTR_TYPE_EXT_INTR && 5088 type != INTR_TYPE_NMI_INTR)) 5089 WARN_ON(!skip_emulated_instruction(vcpu)); 5090 5091 /* 5092 * TODO: What about debug traps on tss switch? 5093 * Are we supposed to inject them and update dr6? 5094 */ 5095 return kvm_task_switch(vcpu, tss_selector, 5096 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5097 reason, has_error_code, error_code); 5098 } 5099 5100 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5101 { 5102 unsigned long exit_qualification; 5103 gpa_t gpa; 5104 u64 error_code; 5105 5106 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5107 5108 /* 5109 * EPT violation happened while executing iret from NMI, 5110 * "blocked by NMI" bit has to be set before next VM entry. 5111 * There are errata that may cause this bit to not be set: 5112 * AAK134, BY25. 5113 */ 5114 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5115 enable_vnmi && 5116 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5117 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5118 5119 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5120 trace_kvm_page_fault(gpa, exit_qualification); 5121 5122 /* Is it a read fault? */ 5123 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5124 ? PFERR_USER_MASK : 0; 5125 /* Is it a write fault? */ 5126 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5127 ? PFERR_WRITE_MASK : 0; 5128 /* Is it a fetch fault? */ 5129 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5130 ? PFERR_FETCH_MASK : 0; 5131 /* ept page table entry is present? */ 5132 error_code |= (exit_qualification & 5133 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5134 EPT_VIOLATION_EXECUTABLE)) 5135 ? PFERR_PRESENT_MASK : 0; 5136 5137 error_code |= (exit_qualification & 0x100) != 0 ? 5138 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5139 5140 vcpu->arch.exit_qualification = exit_qualification; 5141 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5142 } 5143 5144 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5145 { 5146 gpa_t gpa; 5147 5148 /* 5149 * A nested guest cannot optimize MMIO vmexits, because we have an 5150 * nGPA here instead of the required GPA. 5151 */ 5152 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5153 if (!is_guest_mode(vcpu) && 5154 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5155 trace_kvm_fast_mmio(gpa); 5156 return kvm_skip_emulated_instruction(vcpu); 5157 } 5158 5159 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5160 } 5161 5162 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5163 { 5164 WARN_ON_ONCE(!enable_vnmi); 5165 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5166 ++vcpu->stat.nmi_window_exits; 5167 kvm_make_request(KVM_REQ_EVENT, vcpu); 5168 5169 return 1; 5170 } 5171 5172 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5173 { 5174 struct vcpu_vmx *vmx = to_vmx(vcpu); 5175 bool intr_window_requested; 5176 unsigned count = 130; 5177 5178 /* 5179 * We should never reach the point where we are emulating L2 5180 * due to invalid guest state as that means we incorrectly 5181 * allowed a nested VMEntry with an invalid vmcs12. 5182 */ 5183 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5184 5185 intr_window_requested = exec_controls_get(vmx) & 5186 CPU_BASED_INTR_WINDOW_EXITING; 5187 5188 while (vmx->emulation_required && count-- != 0) { 5189 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5190 return handle_interrupt_window(&vmx->vcpu); 5191 5192 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5193 return 1; 5194 5195 if (!kvm_emulate_instruction(vcpu, 0)) 5196 return 0; 5197 5198 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5199 vcpu->arch.exception.pending) { 5200 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5201 vcpu->run->internal.suberror = 5202 KVM_INTERNAL_ERROR_EMULATION; 5203 vcpu->run->internal.ndata = 0; 5204 return 0; 5205 } 5206 5207 if (vcpu->arch.halt_request) { 5208 vcpu->arch.halt_request = 0; 5209 return kvm_vcpu_halt(vcpu); 5210 } 5211 5212 /* 5213 * Note, return 1 and not 0, vcpu_run() is responsible for 5214 * morphing the pending signal into the proper return code. 5215 */ 5216 if (signal_pending(current)) 5217 return 1; 5218 5219 if (need_resched()) 5220 schedule(); 5221 } 5222 5223 return 1; 5224 } 5225 5226 static void grow_ple_window(struct kvm_vcpu *vcpu) 5227 { 5228 struct vcpu_vmx *vmx = to_vmx(vcpu); 5229 unsigned int old = vmx->ple_window; 5230 5231 vmx->ple_window = __grow_ple_window(old, ple_window, 5232 ple_window_grow, 5233 ple_window_max); 5234 5235 if (vmx->ple_window != old) { 5236 vmx->ple_window_dirty = true; 5237 trace_kvm_ple_window_update(vcpu->vcpu_id, 5238 vmx->ple_window, old); 5239 } 5240 } 5241 5242 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5243 { 5244 struct vcpu_vmx *vmx = to_vmx(vcpu); 5245 unsigned int old = vmx->ple_window; 5246 5247 vmx->ple_window = __shrink_ple_window(old, ple_window, 5248 ple_window_shrink, 5249 ple_window); 5250 5251 if (vmx->ple_window != old) { 5252 vmx->ple_window_dirty = true; 5253 trace_kvm_ple_window_update(vcpu->vcpu_id, 5254 vmx->ple_window, old); 5255 } 5256 } 5257 5258 /* 5259 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5260 */ 5261 static void wakeup_handler(void) 5262 { 5263 struct kvm_vcpu *vcpu; 5264 int cpu = smp_processor_id(); 5265 5266 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5267 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5268 blocked_vcpu_list) { 5269 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5270 5271 if (pi_test_on(pi_desc) == 1) 5272 kvm_vcpu_kick(vcpu); 5273 } 5274 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5275 } 5276 5277 static void vmx_enable_tdp(void) 5278 { 5279 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5280 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5281 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5282 0ull, VMX_EPT_EXECUTABLE_MASK, 5283 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5284 VMX_EPT_RWX_MASK, 0ull); 5285 5286 ept_set_mmio_spte_mask(); 5287 kvm_enable_tdp(); 5288 } 5289 5290 /* 5291 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5292 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5293 */ 5294 static int handle_pause(struct kvm_vcpu *vcpu) 5295 { 5296 if (!kvm_pause_in_guest(vcpu->kvm)) 5297 grow_ple_window(vcpu); 5298 5299 /* 5300 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5301 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5302 * never set PAUSE_EXITING and just set PLE if supported, 5303 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5304 */ 5305 kvm_vcpu_on_spin(vcpu, true); 5306 return kvm_skip_emulated_instruction(vcpu); 5307 } 5308 5309 static int handle_nop(struct kvm_vcpu *vcpu) 5310 { 5311 return kvm_skip_emulated_instruction(vcpu); 5312 } 5313 5314 static int handle_mwait(struct kvm_vcpu *vcpu) 5315 { 5316 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5317 return handle_nop(vcpu); 5318 } 5319 5320 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5321 { 5322 kvm_queue_exception(vcpu, UD_VECTOR); 5323 return 1; 5324 } 5325 5326 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5327 { 5328 return 1; 5329 } 5330 5331 static int handle_monitor(struct kvm_vcpu *vcpu) 5332 { 5333 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5334 return handle_nop(vcpu); 5335 } 5336 5337 static int handle_invpcid(struct kvm_vcpu *vcpu) 5338 { 5339 u32 vmx_instruction_info; 5340 unsigned long type; 5341 bool pcid_enabled; 5342 gva_t gva; 5343 struct x86_exception e; 5344 unsigned i; 5345 unsigned long roots_to_free = 0; 5346 struct { 5347 u64 pcid; 5348 u64 gla; 5349 } operand; 5350 5351 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5352 kvm_queue_exception(vcpu, UD_VECTOR); 5353 return 1; 5354 } 5355 5356 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5357 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5358 5359 if (type > 3) { 5360 kvm_inject_gp(vcpu, 0); 5361 return 1; 5362 } 5363 5364 /* According to the Intel instruction reference, the memory operand 5365 * is read even if it isn't needed (e.g., for type==all) 5366 */ 5367 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5368 vmx_instruction_info, false, 5369 sizeof(operand), &gva)) 5370 return 1; 5371 5372 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5373 kvm_inject_page_fault(vcpu, &e); 5374 return 1; 5375 } 5376 5377 if (operand.pcid >> 12 != 0) { 5378 kvm_inject_gp(vcpu, 0); 5379 return 1; 5380 } 5381 5382 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5383 5384 switch (type) { 5385 case INVPCID_TYPE_INDIV_ADDR: 5386 if ((!pcid_enabled && (operand.pcid != 0)) || 5387 is_noncanonical_address(operand.gla, vcpu)) { 5388 kvm_inject_gp(vcpu, 0); 5389 return 1; 5390 } 5391 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5392 return kvm_skip_emulated_instruction(vcpu); 5393 5394 case INVPCID_TYPE_SINGLE_CTXT: 5395 if (!pcid_enabled && (operand.pcid != 0)) { 5396 kvm_inject_gp(vcpu, 0); 5397 return 1; 5398 } 5399 5400 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5401 kvm_mmu_sync_roots(vcpu); 5402 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5403 } 5404 5405 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5406 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5407 == operand.pcid) 5408 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5409 5410 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5411 /* 5412 * If neither the current cr3 nor any of the prev_roots use the 5413 * given PCID, then nothing needs to be done here because a 5414 * resync will happen anyway before switching to any other CR3. 5415 */ 5416 5417 return kvm_skip_emulated_instruction(vcpu); 5418 5419 case INVPCID_TYPE_ALL_NON_GLOBAL: 5420 /* 5421 * Currently, KVM doesn't mark global entries in the shadow 5422 * page tables, so a non-global flush just degenerates to a 5423 * global flush. If needed, we could optimize this later by 5424 * keeping track of global entries in shadow page tables. 5425 */ 5426 5427 /* fall-through */ 5428 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5429 kvm_mmu_unload(vcpu); 5430 return kvm_skip_emulated_instruction(vcpu); 5431 5432 default: 5433 BUG(); /* We have already checked above that type <= 3 */ 5434 } 5435 } 5436 5437 static int handle_pml_full(struct kvm_vcpu *vcpu) 5438 { 5439 unsigned long exit_qualification; 5440 5441 trace_kvm_pml_full(vcpu->vcpu_id); 5442 5443 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5444 5445 /* 5446 * PML buffer FULL happened while executing iret from NMI, 5447 * "blocked by NMI" bit has to be set before next VM entry. 5448 */ 5449 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5450 enable_vnmi && 5451 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5452 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5453 GUEST_INTR_STATE_NMI); 5454 5455 /* 5456 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5457 * here.., and there's no userspace involvement needed for PML. 5458 */ 5459 return 1; 5460 } 5461 5462 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5463 { 5464 struct vcpu_vmx *vmx = to_vmx(vcpu); 5465 5466 if (!vmx->req_immediate_exit && 5467 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5468 kvm_lapic_expired_hv_timer(vcpu); 5469 5470 return 1; 5471 } 5472 5473 /* 5474 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5475 * are overwritten by nested_vmx_setup() when nested=1. 5476 */ 5477 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5478 { 5479 kvm_queue_exception(vcpu, UD_VECTOR); 5480 return 1; 5481 } 5482 5483 static int handle_encls(struct kvm_vcpu *vcpu) 5484 { 5485 /* 5486 * SGX virtualization is not yet supported. There is no software 5487 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5488 * to prevent the guest from executing ENCLS. 5489 */ 5490 kvm_queue_exception(vcpu, UD_VECTOR); 5491 return 1; 5492 } 5493 5494 /* 5495 * The exit handlers return 1 if the exit was handled fully and guest execution 5496 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5497 * to be done to userspace and return 0. 5498 */ 5499 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5500 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5501 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5502 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5503 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5504 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5505 [EXIT_REASON_CR_ACCESS] = handle_cr, 5506 [EXIT_REASON_DR_ACCESS] = handle_dr, 5507 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5508 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5509 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5510 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5511 [EXIT_REASON_HLT] = kvm_emulate_halt, 5512 [EXIT_REASON_INVD] = handle_invd, 5513 [EXIT_REASON_INVLPG] = handle_invlpg, 5514 [EXIT_REASON_RDPMC] = handle_rdpmc, 5515 [EXIT_REASON_VMCALL] = handle_vmcall, 5516 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5517 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5518 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5519 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5520 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5521 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5522 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5523 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5524 [EXIT_REASON_VMON] = handle_vmx_instruction, 5525 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5526 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5527 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5528 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5529 [EXIT_REASON_WBINVD] = handle_wbinvd, 5530 [EXIT_REASON_XSETBV] = handle_xsetbv, 5531 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5532 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5533 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5534 [EXIT_REASON_LDTR_TR] = handle_desc, 5535 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5536 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5537 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5538 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5539 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5540 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5541 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5542 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5543 [EXIT_REASON_RDRAND] = handle_invalid_op, 5544 [EXIT_REASON_RDSEED] = handle_invalid_op, 5545 [EXIT_REASON_PML_FULL] = handle_pml_full, 5546 [EXIT_REASON_INVPCID] = handle_invpcid, 5547 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5548 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5549 [EXIT_REASON_ENCLS] = handle_encls, 5550 }; 5551 5552 static const int kvm_vmx_max_exit_handlers = 5553 ARRAY_SIZE(kvm_vmx_exit_handlers); 5554 5555 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5556 { 5557 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5558 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5559 } 5560 5561 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5562 { 5563 if (vmx->pml_pg) { 5564 __free_page(vmx->pml_pg); 5565 vmx->pml_pg = NULL; 5566 } 5567 } 5568 5569 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5570 { 5571 struct vcpu_vmx *vmx = to_vmx(vcpu); 5572 u64 *pml_buf; 5573 u16 pml_idx; 5574 5575 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5576 5577 /* Do nothing if PML buffer is empty */ 5578 if (pml_idx == (PML_ENTITY_NUM - 1)) 5579 return; 5580 5581 /* PML index always points to next available PML buffer entity */ 5582 if (pml_idx >= PML_ENTITY_NUM) 5583 pml_idx = 0; 5584 else 5585 pml_idx++; 5586 5587 pml_buf = page_address(vmx->pml_pg); 5588 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5589 u64 gpa; 5590 5591 gpa = pml_buf[pml_idx]; 5592 WARN_ON(gpa & (PAGE_SIZE - 1)); 5593 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5594 } 5595 5596 /* reset PML index */ 5597 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5598 } 5599 5600 /* 5601 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5602 * Called before reporting dirty_bitmap to userspace. 5603 */ 5604 static void kvm_flush_pml_buffers(struct kvm *kvm) 5605 { 5606 int i; 5607 struct kvm_vcpu *vcpu; 5608 /* 5609 * We only need to kick vcpu out of guest mode here, as PML buffer 5610 * is flushed at beginning of all VMEXITs, and it's obvious that only 5611 * vcpus running in guest are possible to have unflushed GPAs in PML 5612 * buffer. 5613 */ 5614 kvm_for_each_vcpu(i, vcpu, kvm) 5615 kvm_vcpu_kick(vcpu); 5616 } 5617 5618 static void vmx_dump_sel(char *name, uint32_t sel) 5619 { 5620 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5621 name, vmcs_read16(sel), 5622 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5623 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5624 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5625 } 5626 5627 static void vmx_dump_dtsel(char *name, uint32_t limit) 5628 { 5629 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5630 name, vmcs_read32(limit), 5631 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5632 } 5633 5634 void dump_vmcs(void) 5635 { 5636 u32 vmentry_ctl, vmexit_ctl; 5637 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5638 unsigned long cr4; 5639 u64 efer; 5640 int i, n; 5641 5642 if (!dump_invalid_vmcs) { 5643 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5644 return; 5645 } 5646 5647 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5648 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5649 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5650 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5651 cr4 = vmcs_readl(GUEST_CR4); 5652 efer = vmcs_read64(GUEST_IA32_EFER); 5653 secondary_exec_control = 0; 5654 if (cpu_has_secondary_exec_ctrls()) 5655 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5656 5657 pr_err("*** Guest State ***\n"); 5658 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5659 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5660 vmcs_readl(CR0_GUEST_HOST_MASK)); 5661 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5662 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5663 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5664 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5665 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5666 { 5667 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5668 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5669 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5670 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5671 } 5672 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5673 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5674 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5675 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5676 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5677 vmcs_readl(GUEST_SYSENTER_ESP), 5678 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5679 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5680 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5681 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5682 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5683 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5684 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5685 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5686 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5687 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5688 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5689 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5690 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5691 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5692 efer, vmcs_read64(GUEST_IA32_PAT)); 5693 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5694 vmcs_read64(GUEST_IA32_DEBUGCTL), 5695 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5696 if (cpu_has_load_perf_global_ctrl() && 5697 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5698 pr_err("PerfGlobCtl = 0x%016llx\n", 5699 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5700 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5701 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5702 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5703 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5704 vmcs_read32(GUEST_ACTIVITY_STATE)); 5705 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5706 pr_err("InterruptStatus = %04x\n", 5707 vmcs_read16(GUEST_INTR_STATUS)); 5708 5709 pr_err("*** Host State ***\n"); 5710 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5711 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5712 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5713 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5714 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5715 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5716 vmcs_read16(HOST_TR_SELECTOR)); 5717 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5718 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5719 vmcs_readl(HOST_TR_BASE)); 5720 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5721 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5722 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5723 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5724 vmcs_readl(HOST_CR4)); 5725 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5726 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5727 vmcs_read32(HOST_IA32_SYSENTER_CS), 5728 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5729 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5730 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5731 vmcs_read64(HOST_IA32_EFER), 5732 vmcs_read64(HOST_IA32_PAT)); 5733 if (cpu_has_load_perf_global_ctrl() && 5734 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5735 pr_err("PerfGlobCtl = 0x%016llx\n", 5736 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5737 5738 pr_err("*** Control State ***\n"); 5739 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5740 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5741 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5742 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5743 vmcs_read32(EXCEPTION_BITMAP), 5744 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5745 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5746 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5747 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5748 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5749 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5750 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5751 vmcs_read32(VM_EXIT_INTR_INFO), 5752 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5753 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5754 pr_err(" reason=%08x qualification=%016lx\n", 5755 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5756 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5757 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5758 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5759 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5760 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5761 pr_err("TSC Multiplier = 0x%016llx\n", 5762 vmcs_read64(TSC_MULTIPLIER)); 5763 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5764 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5765 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5766 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5767 } 5768 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5769 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5770 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5771 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5772 } 5773 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5774 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5775 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5776 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5777 n = vmcs_read32(CR3_TARGET_COUNT); 5778 for (i = 0; i + 1 < n; i += 4) 5779 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5780 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5781 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5782 if (i < n) 5783 pr_err("CR3 target%u=%016lx\n", 5784 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5785 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5786 pr_err("PLE Gap=%08x Window=%08x\n", 5787 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5788 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5789 pr_err("Virtual processor ID = 0x%04x\n", 5790 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5791 } 5792 5793 /* 5794 * The guest has exited. See if we can fix it or if we need userspace 5795 * assistance. 5796 */ 5797 static int vmx_handle_exit(struct kvm_vcpu *vcpu, 5798 enum exit_fastpath_completion exit_fastpath) 5799 { 5800 struct vcpu_vmx *vmx = to_vmx(vcpu); 5801 u32 exit_reason = vmx->exit_reason; 5802 u32 vectoring_info = vmx->idt_vectoring_info; 5803 5804 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5805 5806 /* 5807 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5808 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5809 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5810 * mode as if vcpus is in root mode, the PML buffer must has been 5811 * flushed already. 5812 */ 5813 if (enable_pml) 5814 vmx_flush_pml_buffer(vcpu); 5815 5816 /* If guest state is invalid, start emulating */ 5817 if (vmx->emulation_required) 5818 return handle_invalid_guest_state(vcpu); 5819 5820 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5821 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5822 5823 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5824 dump_vmcs(); 5825 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5826 vcpu->run->fail_entry.hardware_entry_failure_reason 5827 = exit_reason; 5828 return 0; 5829 } 5830 5831 if (unlikely(vmx->fail)) { 5832 dump_vmcs(); 5833 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5834 vcpu->run->fail_entry.hardware_entry_failure_reason 5835 = vmcs_read32(VM_INSTRUCTION_ERROR); 5836 return 0; 5837 } 5838 5839 /* 5840 * Note: 5841 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5842 * delivery event since it indicates guest is accessing MMIO. 5843 * The vm-exit can be triggered again after return to guest that 5844 * will cause infinite loop. 5845 */ 5846 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5847 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5848 exit_reason != EXIT_REASON_EPT_VIOLATION && 5849 exit_reason != EXIT_REASON_PML_FULL && 5850 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5851 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5852 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5853 vcpu->run->internal.ndata = 3; 5854 vcpu->run->internal.data[0] = vectoring_info; 5855 vcpu->run->internal.data[1] = exit_reason; 5856 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5857 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5858 vcpu->run->internal.ndata++; 5859 vcpu->run->internal.data[3] = 5860 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5861 } 5862 return 0; 5863 } 5864 5865 if (unlikely(!enable_vnmi && 5866 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5867 if (vmx_interrupt_allowed(vcpu)) { 5868 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5869 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5870 vcpu->arch.nmi_pending) { 5871 /* 5872 * This CPU don't support us in finding the end of an 5873 * NMI-blocked window if the guest runs with IRQs 5874 * disabled. So we pull the trigger after 1 s of 5875 * futile waiting, but inform the user about this. 5876 */ 5877 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5878 "state on VCPU %d after 1 s timeout\n", 5879 __func__, vcpu->vcpu_id); 5880 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5881 } 5882 } 5883 5884 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { 5885 kvm_skip_emulated_instruction(vcpu); 5886 return 1; 5887 } 5888 5889 if (exit_reason >= kvm_vmx_max_exit_handlers) 5890 goto unexpected_vmexit; 5891 #ifdef CONFIG_RETPOLINE 5892 if (exit_reason == EXIT_REASON_MSR_WRITE) 5893 return kvm_emulate_wrmsr(vcpu); 5894 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5895 return handle_preemption_timer(vcpu); 5896 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 5897 return handle_interrupt_window(vcpu); 5898 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5899 return handle_external_interrupt(vcpu); 5900 else if (exit_reason == EXIT_REASON_HLT) 5901 return kvm_emulate_halt(vcpu); 5902 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5903 return handle_ept_misconfig(vcpu); 5904 #endif 5905 5906 exit_reason = array_index_nospec(exit_reason, 5907 kvm_vmx_max_exit_handlers); 5908 if (!kvm_vmx_exit_handlers[exit_reason]) 5909 goto unexpected_vmexit; 5910 5911 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5912 5913 unexpected_vmexit: 5914 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 5915 dump_vmcs(); 5916 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5917 vcpu->run->internal.suberror = 5918 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5919 vcpu->run->internal.ndata = 1; 5920 vcpu->run->internal.data[0] = exit_reason; 5921 return 0; 5922 } 5923 5924 /* 5925 * Software based L1D cache flush which is used when microcode providing 5926 * the cache control MSR is not loaded. 5927 * 5928 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5929 * flush it is required to read in 64 KiB because the replacement algorithm 5930 * is not exactly LRU. This could be sized at runtime via topology 5931 * information but as all relevant affected CPUs have 32KiB L1D cache size 5932 * there is no point in doing so. 5933 */ 5934 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5935 { 5936 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5937 5938 /* 5939 * This code is only executed when the the flush mode is 'cond' or 5940 * 'always' 5941 */ 5942 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5943 bool flush_l1d; 5944 5945 /* 5946 * Clear the per-vcpu flush bit, it gets set again 5947 * either from vcpu_run() or from one of the unsafe 5948 * VMEXIT handlers. 5949 */ 5950 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5951 vcpu->arch.l1tf_flush_l1d = false; 5952 5953 /* 5954 * Clear the per-cpu flush bit, it gets set again from 5955 * the interrupt handlers. 5956 */ 5957 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 5958 kvm_clear_cpu_l1tf_flush_l1d(); 5959 5960 if (!flush_l1d) 5961 return; 5962 } 5963 5964 vcpu->stat.l1d_flush++; 5965 5966 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 5967 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 5968 return; 5969 } 5970 5971 asm volatile( 5972 /* First ensure the pages are in the TLB */ 5973 "xorl %%eax, %%eax\n" 5974 ".Lpopulate_tlb:\n\t" 5975 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5976 "addl $4096, %%eax\n\t" 5977 "cmpl %%eax, %[size]\n\t" 5978 "jne .Lpopulate_tlb\n\t" 5979 "xorl %%eax, %%eax\n\t" 5980 "cpuid\n\t" 5981 /* Now fill the cache */ 5982 "xorl %%eax, %%eax\n" 5983 ".Lfill_cache:\n" 5984 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5985 "addl $64, %%eax\n\t" 5986 "cmpl %%eax, %[size]\n\t" 5987 "jne .Lfill_cache\n\t" 5988 "lfence\n" 5989 :: [flush_pages] "r" (vmx_l1d_flush_pages), 5990 [size] "r" (size) 5991 : "eax", "ebx", "ecx", "edx"); 5992 } 5993 5994 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 5995 { 5996 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5997 int tpr_threshold; 5998 5999 if (is_guest_mode(vcpu) && 6000 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6001 return; 6002 6003 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6004 if (is_guest_mode(vcpu)) 6005 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6006 else 6007 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6008 } 6009 6010 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6011 { 6012 struct vcpu_vmx *vmx = to_vmx(vcpu); 6013 u32 sec_exec_control; 6014 6015 if (!lapic_in_kernel(vcpu)) 6016 return; 6017 6018 if (!flexpriority_enabled && 6019 !cpu_has_vmx_virtualize_x2apic_mode()) 6020 return; 6021 6022 /* Postpone execution until vmcs01 is the current VMCS. */ 6023 if (is_guest_mode(vcpu)) { 6024 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6025 return; 6026 } 6027 6028 sec_exec_control = secondary_exec_controls_get(vmx); 6029 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6030 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6031 6032 switch (kvm_get_apic_mode(vcpu)) { 6033 case LAPIC_MODE_INVALID: 6034 WARN_ONCE(true, "Invalid local APIC state"); 6035 case LAPIC_MODE_DISABLED: 6036 break; 6037 case LAPIC_MODE_XAPIC: 6038 if (flexpriority_enabled) { 6039 sec_exec_control |= 6040 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6041 vmx_flush_tlb(vcpu, true); 6042 } 6043 break; 6044 case LAPIC_MODE_X2APIC: 6045 if (cpu_has_vmx_virtualize_x2apic_mode()) 6046 sec_exec_control |= 6047 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6048 break; 6049 } 6050 secondary_exec_controls_set(vmx, sec_exec_control); 6051 6052 vmx_update_msr_bitmap(vcpu); 6053 } 6054 6055 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6056 { 6057 if (!is_guest_mode(vcpu)) { 6058 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6059 vmx_flush_tlb(vcpu, true); 6060 } 6061 } 6062 6063 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6064 { 6065 u16 status; 6066 u8 old; 6067 6068 if (max_isr == -1) 6069 max_isr = 0; 6070 6071 status = vmcs_read16(GUEST_INTR_STATUS); 6072 old = status >> 8; 6073 if (max_isr != old) { 6074 status &= 0xff; 6075 status |= max_isr << 8; 6076 vmcs_write16(GUEST_INTR_STATUS, status); 6077 } 6078 } 6079 6080 static void vmx_set_rvi(int vector) 6081 { 6082 u16 status; 6083 u8 old; 6084 6085 if (vector == -1) 6086 vector = 0; 6087 6088 status = vmcs_read16(GUEST_INTR_STATUS); 6089 old = (u8)status & 0xff; 6090 if ((u8)vector != old) { 6091 status &= ~0xff; 6092 status |= (u8)vector; 6093 vmcs_write16(GUEST_INTR_STATUS, status); 6094 } 6095 } 6096 6097 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6098 { 6099 /* 6100 * When running L2, updating RVI is only relevant when 6101 * vmcs12 virtual-interrupt-delivery enabled. 6102 * However, it can be enabled only when L1 also 6103 * intercepts external-interrupts and in that case 6104 * we should not update vmcs02 RVI but instead intercept 6105 * interrupt. Therefore, do nothing when running L2. 6106 */ 6107 if (!is_guest_mode(vcpu)) 6108 vmx_set_rvi(max_irr); 6109 } 6110 6111 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6112 { 6113 struct vcpu_vmx *vmx = to_vmx(vcpu); 6114 int max_irr; 6115 bool max_irr_updated; 6116 6117 WARN_ON(!vcpu->arch.apicv_active); 6118 if (pi_test_on(&vmx->pi_desc)) { 6119 pi_clear_on(&vmx->pi_desc); 6120 /* 6121 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6122 * But on x86 this is just a compiler barrier anyway. 6123 */ 6124 smp_mb__after_atomic(); 6125 max_irr_updated = 6126 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6127 6128 /* 6129 * If we are running L2 and L1 has a new pending interrupt 6130 * which can be injected, we should re-evaluate 6131 * what should be done with this new L1 interrupt. 6132 * If L1 intercepts external-interrupts, we should 6133 * exit from L2 to L1. Otherwise, interrupt should be 6134 * delivered directly to L2. 6135 */ 6136 if (is_guest_mode(vcpu) && max_irr_updated) { 6137 if (nested_exit_on_intr(vcpu)) 6138 kvm_vcpu_exiting_guest_mode(vcpu); 6139 else 6140 kvm_make_request(KVM_REQ_EVENT, vcpu); 6141 } 6142 } else { 6143 max_irr = kvm_lapic_find_highest_irr(vcpu); 6144 } 6145 vmx_hwapic_irr_update(vcpu, max_irr); 6146 return max_irr; 6147 } 6148 6149 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6150 { 6151 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6152 6153 return pi_test_on(pi_desc) || 6154 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6155 } 6156 6157 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6158 { 6159 if (!kvm_vcpu_apicv_active(vcpu)) 6160 return; 6161 6162 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6163 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6164 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6165 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6166 } 6167 6168 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6169 { 6170 struct vcpu_vmx *vmx = to_vmx(vcpu); 6171 6172 pi_clear_on(&vmx->pi_desc); 6173 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6174 } 6175 6176 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6177 { 6178 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6179 6180 /* if exit due to PF check for async PF */ 6181 if (is_page_fault(vmx->exit_intr_info)) 6182 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6183 6184 /* Handle machine checks before interrupts are enabled */ 6185 if (is_machine_check(vmx->exit_intr_info)) 6186 kvm_machine_check(); 6187 6188 /* We need to handle NMIs before interrupts are enabled */ 6189 if (is_nmi(vmx->exit_intr_info)) { 6190 kvm_before_interrupt(&vmx->vcpu); 6191 asm("int $2"); 6192 kvm_after_interrupt(&vmx->vcpu); 6193 } 6194 } 6195 6196 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6197 { 6198 unsigned int vector; 6199 unsigned long entry; 6200 #ifdef CONFIG_X86_64 6201 unsigned long tmp; 6202 #endif 6203 gate_desc *desc; 6204 u32 intr_info; 6205 6206 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6207 if (WARN_ONCE(!is_external_intr(intr_info), 6208 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6209 return; 6210 6211 vector = intr_info & INTR_INFO_VECTOR_MASK; 6212 desc = (gate_desc *)host_idt_base + vector; 6213 entry = gate_offset(desc); 6214 6215 kvm_before_interrupt(vcpu); 6216 6217 asm volatile( 6218 #ifdef CONFIG_X86_64 6219 "mov %%" _ASM_SP ", %[sp]\n\t" 6220 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6221 "push $%c[ss]\n\t" 6222 "push %[sp]\n\t" 6223 #endif 6224 "pushf\n\t" 6225 __ASM_SIZE(push) " $%c[cs]\n\t" 6226 CALL_NOSPEC 6227 : 6228 #ifdef CONFIG_X86_64 6229 [sp]"=&r"(tmp), 6230 #endif 6231 ASM_CALL_CONSTRAINT 6232 : 6233 THUNK_TARGET(entry), 6234 [ss]"i"(__KERNEL_DS), 6235 [cs]"i"(__KERNEL_CS) 6236 ); 6237 6238 kvm_after_interrupt(vcpu); 6239 } 6240 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6241 6242 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu, 6243 enum exit_fastpath_completion *exit_fastpath) 6244 { 6245 struct vcpu_vmx *vmx = to_vmx(vcpu); 6246 6247 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6248 handle_external_interrupt_irqoff(vcpu); 6249 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6250 handle_exception_nmi_irqoff(vmx); 6251 else if (!is_guest_mode(vcpu) && 6252 vmx->exit_reason == EXIT_REASON_MSR_WRITE) 6253 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); 6254 } 6255 6256 static bool vmx_has_emulated_msr(int index) 6257 { 6258 switch (index) { 6259 case MSR_IA32_SMBASE: 6260 /* 6261 * We cannot do SMM unless we can run the guest in big 6262 * real mode. 6263 */ 6264 return enable_unrestricted_guest || emulate_invalid_guest_state; 6265 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6266 return nested; 6267 case MSR_AMD64_VIRT_SPEC_CTRL: 6268 /* This is AMD only. */ 6269 return false; 6270 default: 6271 return true; 6272 } 6273 } 6274 6275 static bool vmx_pt_supported(void) 6276 { 6277 return pt_mode == PT_MODE_HOST_GUEST; 6278 } 6279 6280 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6281 { 6282 u32 exit_intr_info; 6283 bool unblock_nmi; 6284 u8 vector; 6285 bool idtv_info_valid; 6286 6287 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6288 6289 if (enable_vnmi) { 6290 if (vmx->loaded_vmcs->nmi_known_unmasked) 6291 return; 6292 /* 6293 * Can't use vmx->exit_intr_info since we're not sure what 6294 * the exit reason is. 6295 */ 6296 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6297 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6298 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6299 /* 6300 * SDM 3: 27.7.1.2 (September 2008) 6301 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6302 * a guest IRET fault. 6303 * SDM 3: 23.2.2 (September 2008) 6304 * Bit 12 is undefined in any of the following cases: 6305 * If the VM exit sets the valid bit in the IDT-vectoring 6306 * information field. 6307 * If the VM exit is due to a double fault. 6308 */ 6309 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6310 vector != DF_VECTOR && !idtv_info_valid) 6311 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6312 GUEST_INTR_STATE_NMI); 6313 else 6314 vmx->loaded_vmcs->nmi_known_unmasked = 6315 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6316 & GUEST_INTR_STATE_NMI); 6317 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6318 vmx->loaded_vmcs->vnmi_blocked_time += 6319 ktime_to_ns(ktime_sub(ktime_get(), 6320 vmx->loaded_vmcs->entry_time)); 6321 } 6322 6323 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6324 u32 idt_vectoring_info, 6325 int instr_len_field, 6326 int error_code_field) 6327 { 6328 u8 vector; 6329 int type; 6330 bool idtv_info_valid; 6331 6332 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6333 6334 vcpu->arch.nmi_injected = false; 6335 kvm_clear_exception_queue(vcpu); 6336 kvm_clear_interrupt_queue(vcpu); 6337 6338 if (!idtv_info_valid) 6339 return; 6340 6341 kvm_make_request(KVM_REQ_EVENT, vcpu); 6342 6343 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6344 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6345 6346 switch (type) { 6347 case INTR_TYPE_NMI_INTR: 6348 vcpu->arch.nmi_injected = true; 6349 /* 6350 * SDM 3: 27.7.1.2 (September 2008) 6351 * Clear bit "block by NMI" before VM entry if a NMI 6352 * delivery faulted. 6353 */ 6354 vmx_set_nmi_mask(vcpu, false); 6355 break; 6356 case INTR_TYPE_SOFT_EXCEPTION: 6357 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6358 /* fall through */ 6359 case INTR_TYPE_HARD_EXCEPTION: 6360 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6361 u32 err = vmcs_read32(error_code_field); 6362 kvm_requeue_exception_e(vcpu, vector, err); 6363 } else 6364 kvm_requeue_exception(vcpu, vector); 6365 break; 6366 case INTR_TYPE_SOFT_INTR: 6367 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6368 /* fall through */ 6369 case INTR_TYPE_EXT_INTR: 6370 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6371 break; 6372 default: 6373 break; 6374 } 6375 } 6376 6377 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6378 { 6379 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6380 VM_EXIT_INSTRUCTION_LEN, 6381 IDT_VECTORING_ERROR_CODE); 6382 } 6383 6384 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6385 { 6386 __vmx_complete_interrupts(vcpu, 6387 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6388 VM_ENTRY_INSTRUCTION_LEN, 6389 VM_ENTRY_EXCEPTION_ERROR_CODE); 6390 6391 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6392 } 6393 6394 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6395 { 6396 int i, nr_msrs; 6397 struct perf_guest_switch_msr *msrs; 6398 6399 msrs = perf_guest_get_msrs(&nr_msrs); 6400 6401 if (!msrs) 6402 return; 6403 6404 for (i = 0; i < nr_msrs; i++) 6405 if (msrs[i].host == msrs[i].guest) 6406 clear_atomic_switch_msr(vmx, msrs[i].msr); 6407 else 6408 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6409 msrs[i].host, false); 6410 } 6411 6412 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6413 { 6414 u32 host_umwait_control; 6415 6416 if (!vmx_has_waitpkg(vmx)) 6417 return; 6418 6419 host_umwait_control = get_umwait_control_msr(); 6420 6421 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6422 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6423 vmx->msr_ia32_umwait_control, 6424 host_umwait_control, false); 6425 else 6426 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6427 } 6428 6429 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6430 { 6431 struct vcpu_vmx *vmx = to_vmx(vcpu); 6432 u64 tscl; 6433 u32 delta_tsc; 6434 6435 if (vmx->req_immediate_exit) { 6436 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6437 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6438 } else if (vmx->hv_deadline_tsc != -1) { 6439 tscl = rdtsc(); 6440 if (vmx->hv_deadline_tsc > tscl) 6441 /* set_hv_timer ensures the delta fits in 32-bits */ 6442 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6443 cpu_preemption_timer_multi); 6444 else 6445 delta_tsc = 0; 6446 6447 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6448 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6449 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6450 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6451 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6452 } 6453 } 6454 6455 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6456 { 6457 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6458 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6459 vmcs_writel(HOST_RSP, host_rsp); 6460 } 6461 } 6462 6463 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6464 6465 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6466 { 6467 struct vcpu_vmx *vmx = to_vmx(vcpu); 6468 unsigned long cr3, cr4; 6469 6470 /* Record the guest's net vcpu time for enforced NMI injections. */ 6471 if (unlikely(!enable_vnmi && 6472 vmx->loaded_vmcs->soft_vnmi_blocked)) 6473 vmx->loaded_vmcs->entry_time = ktime_get(); 6474 6475 /* Don't enter VMX if guest state is invalid, let the exit handler 6476 start emulation until we arrive back to a valid state */ 6477 if (vmx->emulation_required) 6478 return; 6479 6480 if (vmx->ple_window_dirty) { 6481 vmx->ple_window_dirty = false; 6482 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6483 } 6484 6485 if (vmx->nested.need_vmcs12_to_shadow_sync) 6486 nested_sync_vmcs12_to_shadow(vcpu); 6487 6488 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6489 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6490 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6491 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6492 6493 cr3 = __get_current_cr3_fast(); 6494 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6495 vmcs_writel(HOST_CR3, cr3); 6496 vmx->loaded_vmcs->host_state.cr3 = cr3; 6497 } 6498 6499 cr4 = cr4_read_shadow(); 6500 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6501 vmcs_writel(HOST_CR4, cr4); 6502 vmx->loaded_vmcs->host_state.cr4 = cr4; 6503 } 6504 6505 /* When single-stepping over STI and MOV SS, we must clear the 6506 * corresponding interruptibility bits in the guest state. Otherwise 6507 * vmentry fails as it then expects bit 14 (BS) in pending debug 6508 * exceptions being set, but that's not correct for the guest debugging 6509 * case. */ 6510 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6511 vmx_set_interrupt_shadow(vcpu, 0); 6512 6513 kvm_load_guest_xsave_state(vcpu); 6514 6515 if (static_cpu_has(X86_FEATURE_PKU) && 6516 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6517 vcpu->arch.pkru != vmx->host_pkru) 6518 __write_pkru(vcpu->arch.pkru); 6519 6520 pt_guest_enter(vmx); 6521 6522 atomic_switch_perf_msrs(vmx); 6523 atomic_switch_umwait_control_msr(vmx); 6524 6525 if (enable_preemption_timer) 6526 vmx_update_hv_timer(vcpu); 6527 6528 if (lapic_in_kernel(vcpu) && 6529 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6530 kvm_wait_lapic_expire(vcpu); 6531 6532 /* 6533 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6534 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6535 * is no need to worry about the conditional branch over the wrmsr 6536 * being speculatively taken. 6537 */ 6538 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6539 6540 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6541 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6542 vmx_l1d_flush(vcpu); 6543 else if (static_branch_unlikely(&mds_user_clear)) 6544 mds_clear_cpu_buffers(); 6545 6546 if (vcpu->arch.cr2 != read_cr2()) 6547 write_cr2(vcpu->arch.cr2); 6548 6549 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6550 vmx->loaded_vmcs->launched); 6551 6552 vcpu->arch.cr2 = read_cr2(); 6553 6554 /* 6555 * We do not use IBRS in the kernel. If this vCPU has used the 6556 * SPEC_CTRL MSR it may have left it on; save the value and 6557 * turn it off. This is much more efficient than blindly adding 6558 * it to the atomic save/restore list. Especially as the former 6559 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6560 * 6561 * For non-nested case: 6562 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6563 * save it. 6564 * 6565 * For nested case: 6566 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6567 * save it. 6568 */ 6569 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6570 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6571 6572 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6573 6574 /* All fields are clean at this point */ 6575 if (static_branch_unlikely(&enable_evmcs)) 6576 current_evmcs->hv_clean_fields |= 6577 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6578 6579 if (static_branch_unlikely(&enable_evmcs)) 6580 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6581 6582 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6583 if (vmx->host_debugctlmsr) 6584 update_debugctlmsr(vmx->host_debugctlmsr); 6585 6586 #ifndef CONFIG_X86_64 6587 /* 6588 * The sysexit path does not restore ds/es, so we must set them to 6589 * a reasonable value ourselves. 6590 * 6591 * We can't defer this to vmx_prepare_switch_to_host() since that 6592 * function may be executed in interrupt context, which saves and 6593 * restore segments around it, nullifying its effect. 6594 */ 6595 loadsegment(ds, __USER_DS); 6596 loadsegment(es, __USER_DS); 6597 #endif 6598 6599 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6600 | (1 << VCPU_EXREG_RFLAGS) 6601 | (1 << VCPU_EXREG_PDPTR) 6602 | (1 << VCPU_EXREG_SEGMENTS) 6603 | (1 << VCPU_EXREG_CR3)); 6604 vcpu->arch.regs_dirty = 0; 6605 6606 pt_guest_exit(vmx); 6607 6608 /* 6609 * eager fpu is enabled if PKEY is supported and CR4 is switched 6610 * back on host, so it is safe to read guest PKRU from current 6611 * XSAVE. 6612 */ 6613 if (static_cpu_has(X86_FEATURE_PKU) && 6614 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6615 vcpu->arch.pkru = rdpkru(); 6616 if (vcpu->arch.pkru != vmx->host_pkru) 6617 __write_pkru(vmx->host_pkru); 6618 } 6619 6620 kvm_load_host_xsave_state(vcpu); 6621 6622 vmx->nested.nested_run_pending = 0; 6623 vmx->idt_vectoring_info = 0; 6624 6625 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6626 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6627 kvm_machine_check(); 6628 6629 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6630 return; 6631 6632 vmx->loaded_vmcs->launched = 1; 6633 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6634 6635 vmx_recover_nmi_blocking(vmx); 6636 vmx_complete_interrupts(vmx); 6637 } 6638 6639 static struct kvm *vmx_vm_alloc(void) 6640 { 6641 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6642 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6643 PAGE_KERNEL); 6644 return &kvm_vmx->kvm; 6645 } 6646 6647 static void vmx_vm_free(struct kvm *kvm) 6648 { 6649 kfree(kvm->arch.hyperv.hv_pa_pg); 6650 vfree(to_kvm_vmx(kvm)); 6651 } 6652 6653 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6654 { 6655 struct vcpu_vmx *vmx = to_vmx(vcpu); 6656 6657 if (enable_pml) 6658 vmx_destroy_pml_buffer(vmx); 6659 free_vpid(vmx->vpid); 6660 nested_vmx_free_vcpu(vcpu); 6661 free_loaded_vmcs(vmx->loaded_vmcs); 6662 } 6663 6664 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6665 { 6666 struct vcpu_vmx *vmx; 6667 unsigned long *msr_bitmap; 6668 int i, cpu, err; 6669 6670 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6671 vmx = to_vmx(vcpu); 6672 6673 err = -ENOMEM; 6674 6675 vmx->vpid = allocate_vpid(); 6676 6677 /* 6678 * If PML is turned on, failure on enabling PML just results in failure 6679 * of creating the vcpu, therefore we can simplify PML logic (by 6680 * avoiding dealing with cases, such as enabling PML partially on vcpus 6681 * for the guest), etc. 6682 */ 6683 if (enable_pml) { 6684 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6685 if (!vmx->pml_pg) 6686 goto free_vpid; 6687 } 6688 6689 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6690 6691 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6692 u32 index = vmx_msr_index[i]; 6693 u32 data_low, data_high; 6694 int j = vmx->nmsrs; 6695 6696 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6697 continue; 6698 if (wrmsr_safe(index, data_low, data_high) < 0) 6699 continue; 6700 6701 vmx->guest_msrs[j].index = i; 6702 vmx->guest_msrs[j].data = 0; 6703 switch (index) { 6704 case MSR_IA32_TSX_CTRL: 6705 /* 6706 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6707 * let's avoid changing CPUID bits under the host 6708 * kernel's feet. 6709 */ 6710 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6711 break; 6712 default: 6713 vmx->guest_msrs[j].mask = -1ull; 6714 break; 6715 } 6716 ++vmx->nmsrs; 6717 } 6718 6719 err = alloc_loaded_vmcs(&vmx->vmcs01); 6720 if (err < 0) 6721 goto free_pml; 6722 6723 msr_bitmap = vmx->vmcs01.msr_bitmap; 6724 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6725 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6726 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6727 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6728 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6729 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6730 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6731 if (kvm_cstate_in_guest(vcpu->kvm)) { 6732 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6733 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6734 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6735 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6736 } 6737 vmx->msr_bitmap_mode = 0; 6738 6739 vmx->loaded_vmcs = &vmx->vmcs01; 6740 cpu = get_cpu(); 6741 vmx_vcpu_load(vcpu, cpu); 6742 vcpu->cpu = cpu; 6743 init_vmcs(vmx); 6744 vmx_vcpu_put(vcpu); 6745 put_cpu(); 6746 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6747 err = alloc_apic_access_page(vcpu->kvm); 6748 if (err) 6749 goto free_vmcs; 6750 } 6751 6752 if (enable_ept && !enable_unrestricted_guest) { 6753 err = init_rmode_identity_map(vcpu->kvm); 6754 if (err) 6755 goto free_vmcs; 6756 } 6757 6758 if (nested) 6759 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6760 vmx_capability.ept, 6761 kvm_vcpu_apicv_active(vcpu)); 6762 else 6763 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6764 6765 vmx->nested.posted_intr_nv = -1; 6766 vmx->nested.current_vmptr = -1ull; 6767 6768 vcpu->arch.microcode_version = 0x100000000ULL; 6769 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6770 6771 /* 6772 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6773 * or POSTED_INTR_WAKEUP_VECTOR. 6774 */ 6775 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6776 vmx->pi_desc.sn = 1; 6777 6778 vmx->ept_pointer = INVALID_PAGE; 6779 6780 return 0; 6781 6782 free_vmcs: 6783 free_loaded_vmcs(vmx->loaded_vmcs); 6784 free_pml: 6785 vmx_destroy_pml_buffer(vmx); 6786 free_vpid: 6787 free_vpid(vmx->vpid); 6788 return err; 6789 } 6790 6791 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6792 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6793 6794 static int vmx_vm_init(struct kvm *kvm) 6795 { 6796 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6797 6798 if (!ple_gap) 6799 kvm->arch.pause_in_guest = true; 6800 6801 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6802 switch (l1tf_mitigation) { 6803 case L1TF_MITIGATION_OFF: 6804 case L1TF_MITIGATION_FLUSH_NOWARN: 6805 /* 'I explicitly don't care' is set */ 6806 break; 6807 case L1TF_MITIGATION_FLUSH: 6808 case L1TF_MITIGATION_FLUSH_NOSMT: 6809 case L1TF_MITIGATION_FULL: 6810 /* 6811 * Warn upon starting the first VM in a potentially 6812 * insecure environment. 6813 */ 6814 if (sched_smt_active()) 6815 pr_warn_once(L1TF_MSG_SMT); 6816 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6817 pr_warn_once(L1TF_MSG_L1D); 6818 break; 6819 case L1TF_MITIGATION_FULL_FORCE: 6820 /* Flush is enforced */ 6821 break; 6822 } 6823 } 6824 kvm_apicv_init(kvm, enable_apicv); 6825 return 0; 6826 } 6827 6828 static int __init vmx_check_processor_compat(void) 6829 { 6830 struct vmcs_config vmcs_conf; 6831 struct vmx_capability vmx_cap; 6832 6833 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6834 !this_cpu_has(X86_FEATURE_VMX)) { 6835 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6836 return -EIO; 6837 } 6838 6839 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6840 return -EIO; 6841 if (nested) 6842 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept, 6843 enable_apicv); 6844 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6845 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6846 smp_processor_id()); 6847 return -EIO; 6848 } 6849 return 0; 6850 } 6851 6852 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6853 { 6854 u8 cache; 6855 u64 ipat = 0; 6856 6857 /* For VT-d and EPT combination 6858 * 1. MMIO: always map as UC 6859 * 2. EPT with VT-d: 6860 * a. VT-d without snooping control feature: can't guarantee the 6861 * result, try to trust guest. 6862 * b. VT-d with snooping control feature: snooping control feature of 6863 * VT-d engine can guarantee the cache correctness. Just set it 6864 * to WB to keep consistent with host. So the same as item 3. 6865 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6866 * consistent with host MTRR 6867 */ 6868 if (is_mmio) { 6869 cache = MTRR_TYPE_UNCACHABLE; 6870 goto exit; 6871 } 6872 6873 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6874 ipat = VMX_EPT_IPAT_BIT; 6875 cache = MTRR_TYPE_WRBACK; 6876 goto exit; 6877 } 6878 6879 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6880 ipat = VMX_EPT_IPAT_BIT; 6881 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6882 cache = MTRR_TYPE_WRBACK; 6883 else 6884 cache = MTRR_TYPE_UNCACHABLE; 6885 goto exit; 6886 } 6887 6888 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6889 6890 exit: 6891 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6892 } 6893 6894 static int vmx_get_lpage_level(void) 6895 { 6896 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6897 return PT_DIRECTORY_LEVEL; 6898 else 6899 /* For shadow and EPT supported 1GB page */ 6900 return PT_PDPE_LEVEL; 6901 } 6902 6903 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6904 { 6905 /* 6906 * These bits in the secondary execution controls field 6907 * are dynamic, the others are mostly based on the hypervisor 6908 * architecture and the guest's CPUID. Do not touch the 6909 * dynamic bits. 6910 */ 6911 u32 mask = 6912 SECONDARY_EXEC_SHADOW_VMCS | 6913 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6914 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6915 SECONDARY_EXEC_DESC; 6916 6917 u32 new_ctl = vmx->secondary_exec_control; 6918 u32 cur_ctl = secondary_exec_controls_get(vmx); 6919 6920 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6921 } 6922 6923 /* 6924 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6925 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6926 */ 6927 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6928 { 6929 struct vcpu_vmx *vmx = to_vmx(vcpu); 6930 struct kvm_cpuid_entry2 *entry; 6931 6932 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6933 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6934 6935 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6936 if (entry && (entry->_reg & (_cpuid_mask))) \ 6937 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6938 } while (0) 6939 6940 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6941 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 6942 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 6943 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 6944 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 6945 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 6946 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 6947 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 6948 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 6949 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 6950 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 6951 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 6952 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 6953 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 6954 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 6955 6956 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6957 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 6958 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 6959 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 6960 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 6961 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 6962 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 6963 6964 #undef cr4_fixed1_update 6965 } 6966 6967 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 6968 { 6969 struct vcpu_vmx *vmx = to_vmx(vcpu); 6970 6971 if (kvm_mpx_supported()) { 6972 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 6973 6974 if (mpx_enabled) { 6975 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 6976 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 6977 } else { 6978 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 6979 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 6980 } 6981 } 6982 } 6983 6984 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 6985 { 6986 struct vcpu_vmx *vmx = to_vmx(vcpu); 6987 struct kvm_cpuid_entry2 *best = NULL; 6988 int i; 6989 6990 for (i = 0; i < PT_CPUID_LEAVES; i++) { 6991 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 6992 if (!best) 6993 return; 6994 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 6995 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 6996 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 6997 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 6998 } 6999 7000 /* Get the number of configurable Address Ranges for filtering */ 7001 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7002 PT_CAP_num_address_ranges); 7003 7004 /* Initialize and clear the no dependency bits */ 7005 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7006 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7007 7008 /* 7009 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7010 * will inject an #GP 7011 */ 7012 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7013 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7014 7015 /* 7016 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7017 * PSBFreq can be set 7018 */ 7019 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7020 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7021 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7022 7023 /* 7024 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7025 * MTCFreq can be set 7026 */ 7027 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7028 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7029 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7030 7031 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7032 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7033 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7034 RTIT_CTL_PTW_EN); 7035 7036 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7037 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7038 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7039 7040 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7041 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7042 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7043 7044 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7045 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7046 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7047 7048 /* unmask address range configure area */ 7049 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7050 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7051 } 7052 7053 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7054 { 7055 struct vcpu_vmx *vmx = to_vmx(vcpu); 7056 7057 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7058 vcpu->arch.xsaves_enabled = false; 7059 7060 if (cpu_has_secondary_exec_ctrls()) { 7061 vmx_compute_secondary_exec_control(vmx); 7062 vmcs_set_secondary_exec_control(vmx); 7063 } 7064 7065 if (nested_vmx_allowed(vcpu)) 7066 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7067 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7068 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7069 else 7070 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7071 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7072 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7073 7074 if (nested_vmx_allowed(vcpu)) { 7075 nested_vmx_cr_fixed1_bits_update(vcpu); 7076 nested_vmx_entry_exit_ctls_update(vcpu); 7077 } 7078 7079 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7080 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7081 update_intel_pt_cfg(vcpu); 7082 7083 if (boot_cpu_has(X86_FEATURE_RTM)) { 7084 struct shared_msr_entry *msr; 7085 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7086 if (msr) { 7087 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7088 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7089 } 7090 } 7091 } 7092 7093 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 7094 { 7095 if (func == 1 && nested) 7096 entry->ecx |= feature_bit(VMX); 7097 } 7098 7099 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7100 { 7101 to_vmx(vcpu)->req_immediate_exit = true; 7102 } 7103 7104 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7105 struct x86_instruction_info *info, 7106 enum x86_intercept_stage stage) 7107 { 7108 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7109 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7110 7111 /* 7112 * RDPID causes #UD if disabled through secondary execution controls. 7113 * Because it is marked as EmulateOnUD, we need to intercept it here. 7114 */ 7115 if (info->intercept == x86_intercept_rdtscp && 7116 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7117 ctxt->exception.vector = UD_VECTOR; 7118 ctxt->exception.error_code_valid = false; 7119 return X86EMUL_PROPAGATE_FAULT; 7120 } 7121 7122 /* TODO: check more intercepts... */ 7123 return X86EMUL_CONTINUE; 7124 } 7125 7126 #ifdef CONFIG_X86_64 7127 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7128 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7129 u64 divisor, u64 *result) 7130 { 7131 u64 low = a << shift, high = a >> (64 - shift); 7132 7133 /* To avoid the overflow on divq */ 7134 if (high >= divisor) 7135 return 1; 7136 7137 /* Low hold the result, high hold rem which is discarded */ 7138 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7139 "rm" (divisor), "0" (low), "1" (high)); 7140 *result = low; 7141 7142 return 0; 7143 } 7144 7145 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7146 bool *expired) 7147 { 7148 struct vcpu_vmx *vmx; 7149 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7150 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7151 7152 if (kvm_mwait_in_guest(vcpu->kvm) || 7153 kvm_can_post_timer_interrupt(vcpu)) 7154 return -EOPNOTSUPP; 7155 7156 vmx = to_vmx(vcpu); 7157 tscl = rdtsc(); 7158 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7159 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7160 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7161 ktimer->timer_advance_ns); 7162 7163 if (delta_tsc > lapic_timer_advance_cycles) 7164 delta_tsc -= lapic_timer_advance_cycles; 7165 else 7166 delta_tsc = 0; 7167 7168 /* Convert to host delta tsc if tsc scaling is enabled */ 7169 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7170 delta_tsc && u64_shl_div_u64(delta_tsc, 7171 kvm_tsc_scaling_ratio_frac_bits, 7172 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7173 return -ERANGE; 7174 7175 /* 7176 * If the delta tsc can't fit in the 32 bit after the multi shift, 7177 * we can't use the preemption timer. 7178 * It's possible that it fits on later vmentries, but checking 7179 * on every vmentry is costly so we just use an hrtimer. 7180 */ 7181 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7182 return -ERANGE; 7183 7184 vmx->hv_deadline_tsc = tscl + delta_tsc; 7185 *expired = !delta_tsc; 7186 return 0; 7187 } 7188 7189 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7190 { 7191 to_vmx(vcpu)->hv_deadline_tsc = -1; 7192 } 7193 #endif 7194 7195 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7196 { 7197 if (!kvm_pause_in_guest(vcpu->kvm)) 7198 shrink_ple_window(vcpu); 7199 } 7200 7201 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7202 struct kvm_memory_slot *slot) 7203 { 7204 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7205 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7206 } 7207 7208 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7209 struct kvm_memory_slot *slot) 7210 { 7211 kvm_mmu_slot_set_dirty(kvm, slot); 7212 } 7213 7214 static void vmx_flush_log_dirty(struct kvm *kvm) 7215 { 7216 kvm_flush_pml_buffers(kvm); 7217 } 7218 7219 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7220 { 7221 struct vmcs12 *vmcs12; 7222 struct vcpu_vmx *vmx = to_vmx(vcpu); 7223 gpa_t gpa, dst; 7224 7225 if (is_guest_mode(vcpu)) { 7226 WARN_ON_ONCE(vmx->nested.pml_full); 7227 7228 /* 7229 * Check if PML is enabled for the nested guest. 7230 * Whether eptp bit 6 is set is already checked 7231 * as part of A/D emulation. 7232 */ 7233 vmcs12 = get_vmcs12(vcpu); 7234 if (!nested_cpu_has_pml(vmcs12)) 7235 return 0; 7236 7237 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7238 vmx->nested.pml_full = true; 7239 return 1; 7240 } 7241 7242 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7243 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7244 7245 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7246 offset_in_page(dst), sizeof(gpa))) 7247 return 0; 7248 7249 vmcs12->guest_pml_index--; 7250 } 7251 7252 return 0; 7253 } 7254 7255 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7256 struct kvm_memory_slot *memslot, 7257 gfn_t offset, unsigned long mask) 7258 { 7259 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7260 } 7261 7262 static void __pi_post_block(struct kvm_vcpu *vcpu) 7263 { 7264 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7265 struct pi_desc old, new; 7266 unsigned int dest; 7267 7268 do { 7269 old.control = new.control = pi_desc->control; 7270 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7271 "Wakeup handler not enabled while the VCPU is blocked\n"); 7272 7273 dest = cpu_physical_id(vcpu->cpu); 7274 7275 if (x2apic_enabled()) 7276 new.ndst = dest; 7277 else 7278 new.ndst = (dest << 8) & 0xFF00; 7279 7280 /* set 'NV' to 'notification vector' */ 7281 new.nv = POSTED_INTR_VECTOR; 7282 } while (cmpxchg64(&pi_desc->control, old.control, 7283 new.control) != old.control); 7284 7285 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7286 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7287 list_del(&vcpu->blocked_vcpu_list); 7288 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7289 vcpu->pre_pcpu = -1; 7290 } 7291 } 7292 7293 /* 7294 * This routine does the following things for vCPU which is going 7295 * to be blocked if VT-d PI is enabled. 7296 * - Store the vCPU to the wakeup list, so when interrupts happen 7297 * we can find the right vCPU to wake up. 7298 * - Change the Posted-interrupt descriptor as below: 7299 * 'NDST' <-- vcpu->pre_pcpu 7300 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7301 * - If 'ON' is set during this process, which means at least one 7302 * interrupt is posted for this vCPU, we cannot block it, in 7303 * this case, return 1, otherwise, return 0. 7304 * 7305 */ 7306 static int pi_pre_block(struct kvm_vcpu *vcpu) 7307 { 7308 unsigned int dest; 7309 struct pi_desc old, new; 7310 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7311 7312 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7313 !irq_remapping_cap(IRQ_POSTING_CAP) || 7314 !kvm_vcpu_apicv_active(vcpu)) 7315 return 0; 7316 7317 WARN_ON(irqs_disabled()); 7318 local_irq_disable(); 7319 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7320 vcpu->pre_pcpu = vcpu->cpu; 7321 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7322 list_add_tail(&vcpu->blocked_vcpu_list, 7323 &per_cpu(blocked_vcpu_on_cpu, 7324 vcpu->pre_pcpu)); 7325 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7326 } 7327 7328 do { 7329 old.control = new.control = pi_desc->control; 7330 7331 WARN((pi_desc->sn == 1), 7332 "Warning: SN field of posted-interrupts " 7333 "is set before blocking\n"); 7334 7335 /* 7336 * Since vCPU can be preempted during this process, 7337 * vcpu->cpu could be different with pre_pcpu, we 7338 * need to set pre_pcpu as the destination of wakeup 7339 * notification event, then we can find the right vCPU 7340 * to wakeup in wakeup handler if interrupts happen 7341 * when the vCPU is in blocked state. 7342 */ 7343 dest = cpu_physical_id(vcpu->pre_pcpu); 7344 7345 if (x2apic_enabled()) 7346 new.ndst = dest; 7347 else 7348 new.ndst = (dest << 8) & 0xFF00; 7349 7350 /* set 'NV' to 'wakeup vector' */ 7351 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7352 } while (cmpxchg64(&pi_desc->control, old.control, 7353 new.control) != old.control); 7354 7355 /* We should not block the vCPU if an interrupt is posted for it. */ 7356 if (pi_test_on(pi_desc) == 1) 7357 __pi_post_block(vcpu); 7358 7359 local_irq_enable(); 7360 return (vcpu->pre_pcpu == -1); 7361 } 7362 7363 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7364 { 7365 if (pi_pre_block(vcpu)) 7366 return 1; 7367 7368 if (kvm_lapic_hv_timer_in_use(vcpu)) 7369 kvm_lapic_switch_to_sw_timer(vcpu); 7370 7371 return 0; 7372 } 7373 7374 static void pi_post_block(struct kvm_vcpu *vcpu) 7375 { 7376 if (vcpu->pre_pcpu == -1) 7377 return; 7378 7379 WARN_ON(irqs_disabled()); 7380 local_irq_disable(); 7381 __pi_post_block(vcpu); 7382 local_irq_enable(); 7383 } 7384 7385 static void vmx_post_block(struct kvm_vcpu *vcpu) 7386 { 7387 if (kvm_x86_ops->set_hv_timer) 7388 kvm_lapic_switch_to_hv_timer(vcpu); 7389 7390 pi_post_block(vcpu); 7391 } 7392 7393 /* 7394 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7395 * 7396 * @kvm: kvm 7397 * @host_irq: host irq of the interrupt 7398 * @guest_irq: gsi of the interrupt 7399 * @set: set or unset PI 7400 * returns 0 on success, < 0 on failure 7401 */ 7402 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7403 uint32_t guest_irq, bool set) 7404 { 7405 struct kvm_kernel_irq_routing_entry *e; 7406 struct kvm_irq_routing_table *irq_rt; 7407 struct kvm_lapic_irq irq; 7408 struct kvm_vcpu *vcpu; 7409 struct vcpu_data vcpu_info; 7410 int idx, ret = 0; 7411 7412 if (!kvm_arch_has_assigned_device(kvm) || 7413 !irq_remapping_cap(IRQ_POSTING_CAP) || 7414 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7415 return 0; 7416 7417 idx = srcu_read_lock(&kvm->irq_srcu); 7418 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7419 if (guest_irq >= irq_rt->nr_rt_entries || 7420 hlist_empty(&irq_rt->map[guest_irq])) { 7421 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7422 guest_irq, irq_rt->nr_rt_entries); 7423 goto out; 7424 } 7425 7426 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7427 if (e->type != KVM_IRQ_ROUTING_MSI) 7428 continue; 7429 /* 7430 * VT-d PI cannot support posting multicast/broadcast 7431 * interrupts to a vCPU, we still use interrupt remapping 7432 * for these kind of interrupts. 7433 * 7434 * For lowest-priority interrupts, we only support 7435 * those with single CPU as the destination, e.g. user 7436 * configures the interrupts via /proc/irq or uses 7437 * irqbalance to make the interrupts single-CPU. 7438 * 7439 * We will support full lowest-priority interrupt later. 7440 * 7441 * In addition, we can only inject generic interrupts using 7442 * the PI mechanism, refuse to route others through it. 7443 */ 7444 7445 kvm_set_msi_irq(kvm, e, &irq); 7446 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7447 !kvm_irq_is_postable(&irq)) { 7448 /* 7449 * Make sure the IRTE is in remapped mode if 7450 * we don't handle it in posted mode. 7451 */ 7452 ret = irq_set_vcpu_affinity(host_irq, NULL); 7453 if (ret < 0) { 7454 printk(KERN_INFO 7455 "failed to back to remapped mode, irq: %u\n", 7456 host_irq); 7457 goto out; 7458 } 7459 7460 continue; 7461 } 7462 7463 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7464 vcpu_info.vector = irq.vector; 7465 7466 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7467 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7468 7469 if (set) 7470 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7471 else 7472 ret = irq_set_vcpu_affinity(host_irq, NULL); 7473 7474 if (ret < 0) { 7475 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7476 __func__); 7477 goto out; 7478 } 7479 } 7480 7481 ret = 0; 7482 out: 7483 srcu_read_unlock(&kvm->irq_srcu, idx); 7484 return ret; 7485 } 7486 7487 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7488 { 7489 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7490 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7491 FEAT_CTL_LMCE_ENABLED; 7492 else 7493 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7494 ~FEAT_CTL_LMCE_ENABLED; 7495 } 7496 7497 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7498 { 7499 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7500 if (to_vmx(vcpu)->nested.nested_run_pending) 7501 return 0; 7502 return 1; 7503 } 7504 7505 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7506 { 7507 struct vcpu_vmx *vmx = to_vmx(vcpu); 7508 7509 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7510 if (vmx->nested.smm.guest_mode) 7511 nested_vmx_vmexit(vcpu, -1, 0, 0); 7512 7513 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7514 vmx->nested.vmxon = false; 7515 vmx_clear_hlt(vcpu); 7516 return 0; 7517 } 7518 7519 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7520 { 7521 struct vcpu_vmx *vmx = to_vmx(vcpu); 7522 int ret; 7523 7524 if (vmx->nested.smm.vmxon) { 7525 vmx->nested.vmxon = true; 7526 vmx->nested.smm.vmxon = false; 7527 } 7528 7529 if (vmx->nested.smm.guest_mode) { 7530 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7531 if (ret) 7532 return ret; 7533 7534 vmx->nested.smm.guest_mode = false; 7535 } 7536 return 0; 7537 } 7538 7539 static int enable_smi_window(struct kvm_vcpu *vcpu) 7540 { 7541 return 0; 7542 } 7543 7544 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7545 { 7546 return false; 7547 } 7548 7549 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7550 { 7551 return to_vmx(vcpu)->nested.vmxon; 7552 } 7553 7554 static __init int hardware_setup(void) 7555 { 7556 unsigned long host_bndcfgs; 7557 struct desc_ptr dt; 7558 int r, i; 7559 7560 rdmsrl_safe(MSR_EFER, &host_efer); 7561 7562 store_idt(&dt); 7563 host_idt_base = dt.address; 7564 7565 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7566 kvm_define_shared_msr(i, vmx_msr_index[i]); 7567 7568 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7569 return -EIO; 7570 7571 if (boot_cpu_has(X86_FEATURE_NX)) 7572 kvm_enable_efer_bits(EFER_NX); 7573 7574 if (boot_cpu_has(X86_FEATURE_MPX)) { 7575 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7576 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7577 } 7578 7579 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7580 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7581 enable_vpid = 0; 7582 7583 if (!cpu_has_vmx_ept() || 7584 !cpu_has_vmx_ept_4levels() || 7585 !cpu_has_vmx_ept_mt_wb() || 7586 !cpu_has_vmx_invept_global()) 7587 enable_ept = 0; 7588 7589 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7590 enable_ept_ad_bits = 0; 7591 7592 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7593 enable_unrestricted_guest = 0; 7594 7595 if (!cpu_has_vmx_flexpriority()) 7596 flexpriority_enabled = 0; 7597 7598 if (!cpu_has_virtual_nmis()) 7599 enable_vnmi = 0; 7600 7601 /* 7602 * set_apic_access_page_addr() is used to reload apic access 7603 * page upon invalidation. No need to do anything if not 7604 * using the APIC_ACCESS_ADDR VMCS field. 7605 */ 7606 if (!flexpriority_enabled) 7607 kvm_x86_ops->set_apic_access_page_addr = NULL; 7608 7609 if (!cpu_has_vmx_tpr_shadow()) 7610 kvm_x86_ops->update_cr8_intercept = NULL; 7611 7612 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7613 kvm_disable_largepages(); 7614 7615 #if IS_ENABLED(CONFIG_HYPERV) 7616 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7617 && enable_ept) { 7618 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7619 kvm_x86_ops->tlb_remote_flush_with_range = 7620 hv_remote_flush_tlb_with_range; 7621 } 7622 #endif 7623 7624 if (!cpu_has_vmx_ple()) { 7625 ple_gap = 0; 7626 ple_window = 0; 7627 ple_window_grow = 0; 7628 ple_window_max = 0; 7629 ple_window_shrink = 0; 7630 } 7631 7632 if (!cpu_has_vmx_apicv()) { 7633 enable_apicv = 0; 7634 kvm_x86_ops->sync_pir_to_irr = NULL; 7635 } 7636 7637 if (cpu_has_vmx_tsc_scaling()) { 7638 kvm_has_tsc_control = true; 7639 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7640 kvm_tsc_scaling_ratio_frac_bits = 48; 7641 } 7642 7643 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7644 7645 if (enable_ept) 7646 vmx_enable_tdp(); 7647 else 7648 kvm_disable_tdp(); 7649 7650 /* 7651 * Only enable PML when hardware supports PML feature, and both EPT 7652 * and EPT A/D bit features are enabled -- PML depends on them to work. 7653 */ 7654 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7655 enable_pml = 0; 7656 7657 if (!enable_pml) { 7658 kvm_x86_ops->slot_enable_log_dirty = NULL; 7659 kvm_x86_ops->slot_disable_log_dirty = NULL; 7660 kvm_x86_ops->flush_log_dirty = NULL; 7661 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7662 } 7663 7664 if (!cpu_has_vmx_preemption_timer()) 7665 enable_preemption_timer = false; 7666 7667 if (enable_preemption_timer) { 7668 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7669 u64 vmx_msr; 7670 7671 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7672 cpu_preemption_timer_multi = 7673 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7674 7675 if (tsc_khz) 7676 use_timer_freq = (u64)tsc_khz * 1000; 7677 use_timer_freq >>= cpu_preemption_timer_multi; 7678 7679 /* 7680 * KVM "disables" the preemption timer by setting it to its max 7681 * value. Don't use the timer if it might cause spurious exits 7682 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7683 */ 7684 if (use_timer_freq > 0xffffffffu / 10) 7685 enable_preemption_timer = false; 7686 } 7687 7688 if (!enable_preemption_timer) { 7689 kvm_x86_ops->set_hv_timer = NULL; 7690 kvm_x86_ops->cancel_hv_timer = NULL; 7691 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7692 } 7693 7694 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7695 7696 kvm_mce_cap_supported |= MCG_LMCE_P; 7697 7698 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7699 return -EINVAL; 7700 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7701 pt_mode = PT_MODE_SYSTEM; 7702 7703 if (nested) { 7704 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7705 vmx_capability.ept, enable_apicv); 7706 7707 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7708 if (r) 7709 return r; 7710 } 7711 7712 r = alloc_kvm_area(); 7713 if (r) 7714 nested_vmx_hardware_unsetup(); 7715 return r; 7716 } 7717 7718 static __exit void hardware_unsetup(void) 7719 { 7720 if (nested) 7721 nested_vmx_hardware_unsetup(); 7722 7723 free_kvm_area(); 7724 } 7725 7726 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7727 { 7728 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7729 BIT(APICV_INHIBIT_REASON_HYPERV); 7730 7731 return supported & BIT(bit); 7732 } 7733 7734 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7735 .cpu_has_kvm_support = cpu_has_kvm_support, 7736 .disabled_by_bios = vmx_disabled_by_bios, 7737 .hardware_setup = hardware_setup, 7738 .hardware_unsetup = hardware_unsetup, 7739 .check_processor_compatibility = vmx_check_processor_compat, 7740 .hardware_enable = hardware_enable, 7741 .hardware_disable = hardware_disable, 7742 .cpu_has_accelerated_tpr = report_flexpriority, 7743 .has_emulated_msr = vmx_has_emulated_msr, 7744 7745 .vm_init = vmx_vm_init, 7746 .vm_alloc = vmx_vm_alloc, 7747 .vm_free = vmx_vm_free, 7748 7749 .vcpu_create = vmx_create_vcpu, 7750 .vcpu_free = vmx_free_vcpu, 7751 .vcpu_reset = vmx_vcpu_reset, 7752 7753 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7754 .vcpu_load = vmx_vcpu_load, 7755 .vcpu_put = vmx_vcpu_put, 7756 7757 .update_bp_intercept = update_exception_bitmap, 7758 .get_msr_feature = vmx_get_msr_feature, 7759 .get_msr = vmx_get_msr, 7760 .set_msr = vmx_set_msr, 7761 .get_segment_base = vmx_get_segment_base, 7762 .get_segment = vmx_get_segment, 7763 .set_segment = vmx_set_segment, 7764 .get_cpl = vmx_get_cpl, 7765 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7766 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7767 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7768 .set_cr0 = vmx_set_cr0, 7769 .set_cr3 = vmx_set_cr3, 7770 .set_cr4 = vmx_set_cr4, 7771 .set_efer = vmx_set_efer, 7772 .get_idt = vmx_get_idt, 7773 .set_idt = vmx_set_idt, 7774 .get_gdt = vmx_get_gdt, 7775 .set_gdt = vmx_set_gdt, 7776 .get_dr6 = vmx_get_dr6, 7777 .set_dr6 = vmx_set_dr6, 7778 .set_dr7 = vmx_set_dr7, 7779 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7780 .cache_reg = vmx_cache_reg, 7781 .get_rflags = vmx_get_rflags, 7782 .set_rflags = vmx_set_rflags, 7783 7784 .tlb_flush = vmx_flush_tlb, 7785 .tlb_flush_gva = vmx_flush_tlb_gva, 7786 7787 .run = vmx_vcpu_run, 7788 .handle_exit = vmx_handle_exit, 7789 .skip_emulated_instruction = skip_emulated_instruction, 7790 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7791 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7792 .patch_hypercall = vmx_patch_hypercall, 7793 .set_irq = vmx_inject_irq, 7794 .set_nmi = vmx_inject_nmi, 7795 .queue_exception = vmx_queue_exception, 7796 .cancel_injection = vmx_cancel_injection, 7797 .interrupt_allowed = vmx_interrupt_allowed, 7798 .nmi_allowed = vmx_nmi_allowed, 7799 .get_nmi_mask = vmx_get_nmi_mask, 7800 .set_nmi_mask = vmx_set_nmi_mask, 7801 .enable_nmi_window = enable_nmi_window, 7802 .enable_irq_window = enable_irq_window, 7803 .update_cr8_intercept = update_cr8_intercept, 7804 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7805 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7806 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7807 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7808 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7809 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7810 .hwapic_irr_update = vmx_hwapic_irr_update, 7811 .hwapic_isr_update = vmx_hwapic_isr_update, 7812 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7813 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7814 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7815 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7816 7817 .set_tss_addr = vmx_set_tss_addr, 7818 .set_identity_map_addr = vmx_set_identity_map_addr, 7819 .get_tdp_level = get_ept_level, 7820 .get_mt_mask = vmx_get_mt_mask, 7821 7822 .get_exit_info = vmx_get_exit_info, 7823 7824 .get_lpage_level = vmx_get_lpage_level, 7825 7826 .cpuid_update = vmx_cpuid_update, 7827 7828 .rdtscp_supported = vmx_rdtscp_supported, 7829 .invpcid_supported = vmx_invpcid_supported, 7830 7831 .set_supported_cpuid = vmx_set_supported_cpuid, 7832 7833 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7834 7835 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7836 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7837 7838 .set_tdp_cr3 = vmx_set_cr3, 7839 7840 .check_intercept = vmx_check_intercept, 7841 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7842 .mpx_supported = vmx_mpx_supported, 7843 .xsaves_supported = vmx_xsaves_supported, 7844 .umip_emulated = vmx_umip_emulated, 7845 .pt_supported = vmx_pt_supported, 7846 .pku_supported = vmx_pku_supported, 7847 7848 .request_immediate_exit = vmx_request_immediate_exit, 7849 7850 .sched_in = vmx_sched_in, 7851 7852 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7853 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7854 .flush_log_dirty = vmx_flush_log_dirty, 7855 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7856 .write_log_dirty = vmx_write_pml_buffer, 7857 7858 .pre_block = vmx_pre_block, 7859 .post_block = vmx_post_block, 7860 7861 .pmu_ops = &intel_pmu_ops, 7862 7863 .update_pi_irte = vmx_update_pi_irte, 7864 7865 #ifdef CONFIG_X86_64 7866 .set_hv_timer = vmx_set_hv_timer, 7867 .cancel_hv_timer = vmx_cancel_hv_timer, 7868 #endif 7869 7870 .setup_mce = vmx_setup_mce, 7871 7872 .smi_allowed = vmx_smi_allowed, 7873 .pre_enter_smm = vmx_pre_enter_smm, 7874 .pre_leave_smm = vmx_pre_leave_smm, 7875 .enable_smi_window = enable_smi_window, 7876 7877 .check_nested_events = NULL, 7878 .get_nested_state = NULL, 7879 .set_nested_state = NULL, 7880 .get_vmcs12_pages = NULL, 7881 .nested_enable_evmcs = NULL, 7882 .nested_get_evmcs_version = NULL, 7883 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7884 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7885 }; 7886 7887 static void vmx_cleanup_l1d_flush(void) 7888 { 7889 if (vmx_l1d_flush_pages) { 7890 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7891 vmx_l1d_flush_pages = NULL; 7892 } 7893 /* Restore state so sysfs ignores VMX */ 7894 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 7895 } 7896 7897 static void vmx_exit(void) 7898 { 7899 #ifdef CONFIG_KEXEC_CORE 7900 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 7901 synchronize_rcu(); 7902 #endif 7903 7904 kvm_exit(); 7905 7906 #if IS_ENABLED(CONFIG_HYPERV) 7907 if (static_branch_unlikely(&enable_evmcs)) { 7908 int cpu; 7909 struct hv_vp_assist_page *vp_ap; 7910 /* 7911 * Reset everything to support using non-enlightened VMCS 7912 * access later (e.g. when we reload the module with 7913 * enlightened_vmcs=0) 7914 */ 7915 for_each_online_cpu(cpu) { 7916 vp_ap = hv_get_vp_assist_page(cpu); 7917 7918 if (!vp_ap) 7919 continue; 7920 7921 vp_ap->nested_control.features.directhypercall = 0; 7922 vp_ap->current_nested_vmcs = 0; 7923 vp_ap->enlighten_vmentry = 0; 7924 } 7925 7926 static_branch_disable(&enable_evmcs); 7927 } 7928 #endif 7929 vmx_cleanup_l1d_flush(); 7930 } 7931 module_exit(vmx_exit); 7932 7933 static int __init vmx_init(void) 7934 { 7935 int r; 7936 7937 #if IS_ENABLED(CONFIG_HYPERV) 7938 /* 7939 * Enlightened VMCS usage should be recommended and the host needs 7940 * to support eVMCS v1 or above. We can also disable eVMCS support 7941 * with module parameter. 7942 */ 7943 if (enlightened_vmcs && 7944 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 7945 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 7946 KVM_EVMCS_VERSION) { 7947 int cpu; 7948 7949 /* Check that we have assist pages on all online CPUs */ 7950 for_each_online_cpu(cpu) { 7951 if (!hv_get_vp_assist_page(cpu)) { 7952 enlightened_vmcs = false; 7953 break; 7954 } 7955 } 7956 7957 if (enlightened_vmcs) { 7958 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 7959 static_branch_enable(&enable_evmcs); 7960 } 7961 7962 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 7963 vmx_x86_ops.enable_direct_tlbflush 7964 = hv_enable_direct_tlbflush; 7965 7966 } else { 7967 enlightened_vmcs = false; 7968 } 7969 #endif 7970 7971 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 7972 __alignof__(struct vcpu_vmx), THIS_MODULE); 7973 if (r) 7974 return r; 7975 7976 /* 7977 * Must be called after kvm_init() so enable_ept is properly set 7978 * up. Hand the parameter mitigation value in which was stored in 7979 * the pre module init parser. If no parameter was given, it will 7980 * contain 'auto' which will be turned into the default 'cond' 7981 * mitigation mode. 7982 */ 7983 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 7984 if (r) { 7985 vmx_exit(); 7986 return r; 7987 } 7988 7989 #ifdef CONFIG_KEXEC_CORE 7990 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 7991 crash_vmclear_local_loaded_vmcss); 7992 #endif 7993 vmx_check_vmcs12_offsets(); 7994 7995 return 0; 7996 } 7997 module_init(vmx_init); 7998