1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/debugreg.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/io.h> 38 #include <asm/irq_remapping.h> 39 #include <asm/kexec.h> 40 #include <asm/perf_event.h> 41 #include <asm/mce.h> 42 #include <asm/mmu_context.h> 43 #include <asm/mshyperv.h> 44 #include <asm/spec-ctrl.h> 45 #include <asm/virtext.h> 46 #include <asm/vmx.h> 47 48 #include "capabilities.h" 49 #include "cpuid.h" 50 #include "evmcs.h" 51 #include "irq.h" 52 #include "kvm_cache_regs.h" 53 #include "lapic.h" 54 #include "mmu.h" 55 #include "nested.h" 56 #include "ops.h" 57 #include "pmu.h" 58 #include "trace.h" 59 #include "vmcs.h" 60 #include "vmcs12.h" 61 #include "vmx.h" 62 #include "x86.h" 63 64 MODULE_AUTHOR("Qumranet"); 65 MODULE_LICENSE("GPL"); 66 67 #ifdef MODULE 68 static const struct x86_cpu_id vmx_cpu_id[] = { 69 X86_FEATURE_MATCH(X86_FEATURE_VMX), 70 {} 71 }; 72 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 73 #endif 74 75 bool __read_mostly enable_vpid = 1; 76 module_param_named(vpid, enable_vpid, bool, 0444); 77 78 static bool __read_mostly enable_vnmi = 1; 79 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 80 81 bool __read_mostly flexpriority_enabled = 1; 82 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 83 84 bool __read_mostly enable_ept = 1; 85 module_param_named(ept, enable_ept, bool, S_IRUGO); 86 87 bool __read_mostly enable_unrestricted_guest = 1; 88 module_param_named(unrestricted_guest, 89 enable_unrestricted_guest, bool, S_IRUGO); 90 91 bool __read_mostly enable_ept_ad_bits = 1; 92 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 93 94 static bool __read_mostly emulate_invalid_guest_state = true; 95 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 96 97 static bool __read_mostly fasteoi = 1; 98 module_param(fasteoi, bool, S_IRUGO); 99 100 bool __read_mostly enable_apicv = 1; 101 module_param(enable_apicv, bool, S_IRUGO); 102 103 /* 104 * If nested=1, nested virtualization is supported, i.e., guests may use 105 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 106 * use VMX instructions. 107 */ 108 static bool __read_mostly nested = 1; 109 module_param(nested, bool, S_IRUGO); 110 111 bool __read_mostly enable_pml = 1; 112 module_param_named(pml, enable_pml, bool, S_IRUGO); 113 114 static bool __read_mostly dump_invalid_vmcs = 0; 115 module_param(dump_invalid_vmcs, bool, 0644); 116 117 #define MSR_BITMAP_MODE_X2APIC 1 118 #define MSR_BITMAP_MODE_X2APIC_APICV 2 119 120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 121 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 123 static int __read_mostly cpu_preemption_timer_multi; 124 static bool __read_mostly enable_preemption_timer = 1; 125 #ifdef CONFIG_X86_64 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 127 #endif 128 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 131 #define KVM_VM_CR0_ALWAYS_ON \ 132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 134 #define KVM_CR4_GUEST_OWNED_BITS \ 135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 137 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 141 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 143 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 147 RTIT_STATUS_BYTECNT)) 148 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 151 152 /* 153 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 154 * ple_gap: upper bound on the amount of time between two successive 155 * executions of PAUSE in a loop. Also indicate if ple enabled. 156 * According to test, this time is usually smaller than 128 cycles. 157 * ple_window: upper bound on the amount of time a guest is allowed to execute 158 * in a PAUSE loop. Tests indicate that most spinlocks are held for 159 * less than 2^12 cycles 160 * Time is measured based on a counter that runs at the same rate as the TSC, 161 * refer SDM volume 3b section 21.6.13 & 22.1.3. 162 */ 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 164 module_param(ple_gap, uint, 0444); 165 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 167 module_param(ple_window, uint, 0444); 168 169 /* Default doubles per-vcpu window every exit. */ 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 171 module_param(ple_window_grow, uint, 0444); 172 173 /* Default resets per-vcpu window every exit to ple_window. */ 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 175 module_param(ple_window_shrink, uint, 0444); 176 177 /* Default is to compute the maximum so we can never overflow. */ 178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 179 module_param(ple_window_max, uint, 0444); 180 181 /* Default is SYSTEM mode, 1 for host-guest mode */ 182 int __read_mostly pt_mode = PT_MODE_SYSTEM; 183 module_param(pt_mode, int, S_IRUGO); 184 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 188 189 /* Storage for pre module init parameter parsing */ 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 191 192 static const struct { 193 const char *option; 194 bool for_parse; 195 } vmentry_l1d_param[] = { 196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 198 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 202 }; 203 204 #define L1D_CACHE_ORDER 4 205 static void *vmx_l1d_flush_pages; 206 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 208 { 209 struct page *page; 210 unsigned int i; 211 212 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 214 return 0; 215 } 216 217 if (!enable_ept) { 218 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 219 return 0; 220 } 221 222 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 223 u64 msr; 224 225 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 226 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 227 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 228 return 0; 229 } 230 } 231 232 /* If set to auto use the default l1tf mitigation method */ 233 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 234 switch (l1tf_mitigation) { 235 case L1TF_MITIGATION_OFF: 236 l1tf = VMENTER_L1D_FLUSH_NEVER; 237 break; 238 case L1TF_MITIGATION_FLUSH_NOWARN: 239 case L1TF_MITIGATION_FLUSH: 240 case L1TF_MITIGATION_FLUSH_NOSMT: 241 l1tf = VMENTER_L1D_FLUSH_COND; 242 break; 243 case L1TF_MITIGATION_FULL: 244 case L1TF_MITIGATION_FULL_FORCE: 245 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 246 break; 247 } 248 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 249 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 250 } 251 252 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 253 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 254 /* 255 * This allocation for vmx_l1d_flush_pages is not tied to a VM 256 * lifetime and so should not be charged to a memcg. 257 */ 258 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 259 if (!page) 260 return -ENOMEM; 261 vmx_l1d_flush_pages = page_address(page); 262 263 /* 264 * Initialize each page with a different pattern in 265 * order to protect against KSM in the nested 266 * virtualization case. 267 */ 268 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 269 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 270 PAGE_SIZE); 271 } 272 } 273 274 l1tf_vmx_mitigation = l1tf; 275 276 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 277 static_branch_enable(&vmx_l1d_should_flush); 278 else 279 static_branch_disable(&vmx_l1d_should_flush); 280 281 if (l1tf == VMENTER_L1D_FLUSH_COND) 282 static_branch_enable(&vmx_l1d_flush_cond); 283 else 284 static_branch_disable(&vmx_l1d_flush_cond); 285 return 0; 286 } 287 288 static int vmentry_l1d_flush_parse(const char *s) 289 { 290 unsigned int i; 291 292 if (s) { 293 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 294 if (vmentry_l1d_param[i].for_parse && 295 sysfs_streq(s, vmentry_l1d_param[i].option)) 296 return i; 297 } 298 } 299 return -EINVAL; 300 } 301 302 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 303 { 304 int l1tf, ret; 305 306 l1tf = vmentry_l1d_flush_parse(s); 307 if (l1tf < 0) 308 return l1tf; 309 310 if (!boot_cpu_has(X86_BUG_L1TF)) 311 return 0; 312 313 /* 314 * Has vmx_init() run already? If not then this is the pre init 315 * parameter parsing. In that case just store the value and let 316 * vmx_init() do the proper setup after enable_ept has been 317 * established. 318 */ 319 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 320 vmentry_l1d_flush_param = l1tf; 321 return 0; 322 } 323 324 mutex_lock(&vmx_l1d_flush_mutex); 325 ret = vmx_setup_l1d_flush(l1tf); 326 mutex_unlock(&vmx_l1d_flush_mutex); 327 return ret; 328 } 329 330 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 331 { 332 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 333 return sprintf(s, "???\n"); 334 335 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 336 } 337 338 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 339 .set = vmentry_l1d_flush_set, 340 .get = vmentry_l1d_flush_get, 341 }; 342 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 343 344 static bool guest_state_valid(struct kvm_vcpu *vcpu); 345 static u32 vmx_segment_access_rights(struct kvm_segment *var); 346 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 347 u32 msr, int type); 348 349 void vmx_vmexit(void); 350 351 #define vmx_insn_failed(fmt...) \ 352 do { \ 353 WARN_ONCE(1, fmt); \ 354 pr_warn_ratelimited(fmt); \ 355 } while (0) 356 357 asmlinkage void vmread_error(unsigned long field, bool fault) 358 { 359 if (fault) 360 kvm_spurious_fault(); 361 else 362 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 363 } 364 365 noinline void vmwrite_error(unsigned long field, unsigned long value) 366 { 367 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 368 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 369 } 370 371 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 372 { 373 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 374 } 375 376 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 377 { 378 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 379 } 380 381 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 382 { 383 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 384 ext, vpid, gva); 385 } 386 387 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 388 { 389 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 390 ext, eptp, gpa); 391 } 392 393 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 394 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 395 /* 396 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 397 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 398 */ 399 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 400 401 /* 402 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 403 * can find which vCPU should be waken up. 404 */ 405 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 406 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 407 408 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 409 static DEFINE_SPINLOCK(vmx_vpid_lock); 410 411 struct vmcs_config vmcs_config; 412 struct vmx_capability vmx_capability; 413 414 #define VMX_SEGMENT_FIELD(seg) \ 415 [VCPU_SREG_##seg] = { \ 416 .selector = GUEST_##seg##_SELECTOR, \ 417 .base = GUEST_##seg##_BASE, \ 418 .limit = GUEST_##seg##_LIMIT, \ 419 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 420 } 421 422 static const struct kvm_vmx_segment_field { 423 unsigned selector; 424 unsigned base; 425 unsigned limit; 426 unsigned ar_bytes; 427 } kvm_vmx_segment_fields[] = { 428 VMX_SEGMENT_FIELD(CS), 429 VMX_SEGMENT_FIELD(DS), 430 VMX_SEGMENT_FIELD(ES), 431 VMX_SEGMENT_FIELD(FS), 432 VMX_SEGMENT_FIELD(GS), 433 VMX_SEGMENT_FIELD(SS), 434 VMX_SEGMENT_FIELD(TR), 435 VMX_SEGMENT_FIELD(LDTR), 436 }; 437 438 u64 host_efer; 439 static unsigned long host_idt_base; 440 441 /* 442 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 443 * will emulate SYSCALL in legacy mode if the vendor string in guest 444 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 445 * support this emulation, IA32_STAR must always be included in 446 * vmx_msr_index[], even in i386 builds. 447 */ 448 const u32 vmx_msr_index[] = { 449 #ifdef CONFIG_X86_64 450 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 451 #endif 452 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 453 MSR_IA32_TSX_CTRL, 454 }; 455 456 #if IS_ENABLED(CONFIG_HYPERV) 457 static bool __read_mostly enlightened_vmcs = true; 458 module_param(enlightened_vmcs, bool, 0444); 459 460 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 461 static void check_ept_pointer_match(struct kvm *kvm) 462 { 463 struct kvm_vcpu *vcpu; 464 u64 tmp_eptp = INVALID_PAGE; 465 int i; 466 467 kvm_for_each_vcpu(i, vcpu, kvm) { 468 if (!VALID_PAGE(tmp_eptp)) { 469 tmp_eptp = to_vmx(vcpu)->ept_pointer; 470 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 471 to_kvm_vmx(kvm)->ept_pointers_match 472 = EPT_POINTERS_MISMATCH; 473 return; 474 } 475 } 476 477 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 478 } 479 480 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 481 void *data) 482 { 483 struct kvm_tlb_range *range = data; 484 485 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 486 range->pages); 487 } 488 489 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 490 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 491 { 492 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 493 494 /* 495 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 496 * of the base of EPT PML4 table, strip off EPT configuration 497 * information. 498 */ 499 if (range) 500 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 501 kvm_fill_hv_flush_list_func, (void *)range); 502 else 503 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 504 } 505 506 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 507 struct kvm_tlb_range *range) 508 { 509 struct kvm_vcpu *vcpu; 510 int ret = 0, i; 511 512 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 513 514 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 515 check_ept_pointer_match(kvm); 516 517 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 518 kvm_for_each_vcpu(i, vcpu, kvm) { 519 /* If ept_pointer is invalid pointer, bypass flush request. */ 520 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 521 ret |= __hv_remote_flush_tlb_with_range( 522 kvm, vcpu, range); 523 } 524 } else { 525 ret = __hv_remote_flush_tlb_with_range(kvm, 526 kvm_get_vcpu(kvm, 0), range); 527 } 528 529 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 530 return ret; 531 } 532 static int hv_remote_flush_tlb(struct kvm *kvm) 533 { 534 return hv_remote_flush_tlb_with_range(kvm, NULL); 535 } 536 537 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 538 { 539 struct hv_enlightened_vmcs *evmcs; 540 struct hv_partition_assist_pg **p_hv_pa_pg = 541 &vcpu->kvm->arch.hyperv.hv_pa_pg; 542 /* 543 * Synthetic VM-Exit is not enabled in current code and so All 544 * evmcs in singe VM shares same assist page. 545 */ 546 if (!*p_hv_pa_pg) 547 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 548 549 if (!*p_hv_pa_pg) 550 return -ENOMEM; 551 552 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 553 554 evmcs->partition_assist_page = 555 __pa(*p_hv_pa_pg); 556 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 557 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 558 559 return 0; 560 } 561 562 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 563 564 /* 565 * Comment's format: document - errata name - stepping - processor name. 566 * Refer from 567 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 568 */ 569 static u32 vmx_preemption_cpu_tfms[] = { 570 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 571 0x000206E6, 572 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 573 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 574 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 575 0x00020652, 576 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 577 0x00020655, 578 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 579 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 580 /* 581 * 320767.pdf - AAP86 - B1 - 582 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 583 */ 584 0x000106E5, 585 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 586 0x000106A0, 587 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 588 0x000106A1, 589 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 590 0x000106A4, 591 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 592 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 593 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 594 0x000106A5, 595 /* Xeon E3-1220 V2 */ 596 0x000306A8, 597 }; 598 599 static inline bool cpu_has_broken_vmx_preemption_timer(void) 600 { 601 u32 eax = cpuid_eax(0x00000001), i; 602 603 /* Clear the reserved bits */ 604 eax &= ~(0x3U << 14 | 0xfU << 28); 605 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 606 if (eax == vmx_preemption_cpu_tfms[i]) 607 return true; 608 609 return false; 610 } 611 612 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 613 { 614 return flexpriority_enabled && lapic_in_kernel(vcpu); 615 } 616 617 static inline bool report_flexpriority(void) 618 { 619 return flexpriority_enabled; 620 } 621 622 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 623 { 624 int i; 625 626 for (i = 0; i < vmx->nmsrs; ++i) 627 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 628 return i; 629 return -1; 630 } 631 632 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 633 { 634 int i; 635 636 i = __find_msr_index(vmx, msr); 637 if (i >= 0) 638 return &vmx->guest_msrs[i]; 639 return NULL; 640 } 641 642 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 643 { 644 int ret = 0; 645 646 u64 old_msr_data = msr->data; 647 msr->data = data; 648 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 649 preempt_disable(); 650 ret = kvm_set_shared_msr(msr->index, msr->data, 651 msr->mask); 652 preempt_enable(); 653 if (ret) 654 msr->data = old_msr_data; 655 } 656 return ret; 657 } 658 659 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 660 { 661 vmcs_clear(loaded_vmcs->vmcs); 662 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 663 vmcs_clear(loaded_vmcs->shadow_vmcs); 664 loaded_vmcs->cpu = -1; 665 loaded_vmcs->launched = 0; 666 } 667 668 #ifdef CONFIG_KEXEC_CORE 669 /* 670 * This bitmap is used to indicate whether the vmclear 671 * operation is enabled on all cpus. All disabled by 672 * default. 673 */ 674 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 675 676 static inline void crash_enable_local_vmclear(int cpu) 677 { 678 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 679 } 680 681 static inline void crash_disable_local_vmclear(int cpu) 682 { 683 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 684 } 685 686 static inline int crash_local_vmclear_enabled(int cpu) 687 { 688 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 689 } 690 691 static void crash_vmclear_local_loaded_vmcss(void) 692 { 693 int cpu = raw_smp_processor_id(); 694 struct loaded_vmcs *v; 695 696 if (!crash_local_vmclear_enabled(cpu)) 697 return; 698 699 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 700 loaded_vmcss_on_cpu_link) 701 vmcs_clear(v->vmcs); 702 } 703 #else 704 static inline void crash_enable_local_vmclear(int cpu) { } 705 static inline void crash_disable_local_vmclear(int cpu) { } 706 #endif /* CONFIG_KEXEC_CORE */ 707 708 static void __loaded_vmcs_clear(void *arg) 709 { 710 struct loaded_vmcs *loaded_vmcs = arg; 711 int cpu = raw_smp_processor_id(); 712 713 if (loaded_vmcs->cpu != cpu) 714 return; /* vcpu migration can race with cpu offline */ 715 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 716 per_cpu(current_vmcs, cpu) = NULL; 717 crash_disable_local_vmclear(cpu); 718 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 719 720 /* 721 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 722 * is before setting loaded_vmcs->vcpu to -1 which is done in 723 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 724 * then adds the vmcs into percpu list before it is deleted. 725 */ 726 smp_wmb(); 727 728 loaded_vmcs_init(loaded_vmcs); 729 crash_enable_local_vmclear(cpu); 730 } 731 732 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 733 { 734 int cpu = loaded_vmcs->cpu; 735 736 if (cpu != -1) 737 smp_call_function_single(cpu, 738 __loaded_vmcs_clear, loaded_vmcs, 1); 739 } 740 741 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 742 unsigned field) 743 { 744 bool ret; 745 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 746 747 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 748 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 749 vmx->segment_cache.bitmask = 0; 750 } 751 ret = vmx->segment_cache.bitmask & mask; 752 vmx->segment_cache.bitmask |= mask; 753 return ret; 754 } 755 756 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 757 { 758 u16 *p = &vmx->segment_cache.seg[seg].selector; 759 760 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 761 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 762 return *p; 763 } 764 765 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 766 { 767 ulong *p = &vmx->segment_cache.seg[seg].base; 768 769 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 770 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 771 return *p; 772 } 773 774 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 775 { 776 u32 *p = &vmx->segment_cache.seg[seg].limit; 777 778 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 779 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 780 return *p; 781 } 782 783 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 784 { 785 u32 *p = &vmx->segment_cache.seg[seg].ar; 786 787 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 788 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 789 return *p; 790 } 791 792 void update_exception_bitmap(struct kvm_vcpu *vcpu) 793 { 794 u32 eb; 795 796 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 797 (1u << DB_VECTOR) | (1u << AC_VECTOR); 798 /* 799 * Guest access to VMware backdoor ports could legitimately 800 * trigger #GP because of TSS I/O permission bitmap. 801 * We intercept those #GP and allow access to them anyway 802 * as VMware does. 803 */ 804 if (enable_vmware_backdoor) 805 eb |= (1u << GP_VECTOR); 806 if ((vcpu->guest_debug & 807 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 808 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 809 eb |= 1u << BP_VECTOR; 810 if (to_vmx(vcpu)->rmode.vm86_active) 811 eb = ~0; 812 if (enable_ept) 813 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 814 815 /* When we are running a nested L2 guest and L1 specified for it a 816 * certain exception bitmap, we must trap the same exceptions and pass 817 * them to L1. When running L2, we will only handle the exceptions 818 * specified above if L1 did not want them. 819 */ 820 if (is_guest_mode(vcpu)) 821 eb |= get_vmcs12(vcpu)->exception_bitmap; 822 823 vmcs_write32(EXCEPTION_BITMAP, eb); 824 } 825 826 /* 827 * Check if MSR is intercepted for currently loaded MSR bitmap. 828 */ 829 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 830 { 831 unsigned long *msr_bitmap; 832 int f = sizeof(unsigned long); 833 834 if (!cpu_has_vmx_msr_bitmap()) 835 return true; 836 837 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 838 839 if (msr <= 0x1fff) { 840 return !!test_bit(msr, msr_bitmap + 0x800 / f); 841 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 842 msr &= 0x1fff; 843 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 844 } 845 846 return true; 847 } 848 849 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 850 unsigned long entry, unsigned long exit) 851 { 852 vm_entry_controls_clearbit(vmx, entry); 853 vm_exit_controls_clearbit(vmx, exit); 854 } 855 856 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 857 { 858 unsigned int i; 859 860 for (i = 0; i < m->nr; ++i) { 861 if (m->val[i].index == msr) 862 return i; 863 } 864 return -ENOENT; 865 } 866 867 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 868 { 869 int i; 870 struct msr_autoload *m = &vmx->msr_autoload; 871 872 switch (msr) { 873 case MSR_EFER: 874 if (cpu_has_load_ia32_efer()) { 875 clear_atomic_switch_msr_special(vmx, 876 VM_ENTRY_LOAD_IA32_EFER, 877 VM_EXIT_LOAD_IA32_EFER); 878 return; 879 } 880 break; 881 case MSR_CORE_PERF_GLOBAL_CTRL: 882 if (cpu_has_load_perf_global_ctrl()) { 883 clear_atomic_switch_msr_special(vmx, 884 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 885 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 886 return; 887 } 888 break; 889 } 890 i = vmx_find_msr_index(&m->guest, msr); 891 if (i < 0) 892 goto skip_guest; 893 --m->guest.nr; 894 m->guest.val[i] = m->guest.val[m->guest.nr]; 895 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 896 897 skip_guest: 898 i = vmx_find_msr_index(&m->host, msr); 899 if (i < 0) 900 return; 901 902 --m->host.nr; 903 m->host.val[i] = m->host.val[m->host.nr]; 904 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 905 } 906 907 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 908 unsigned long entry, unsigned long exit, 909 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 910 u64 guest_val, u64 host_val) 911 { 912 vmcs_write64(guest_val_vmcs, guest_val); 913 if (host_val_vmcs != HOST_IA32_EFER) 914 vmcs_write64(host_val_vmcs, host_val); 915 vm_entry_controls_setbit(vmx, entry); 916 vm_exit_controls_setbit(vmx, exit); 917 } 918 919 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 920 u64 guest_val, u64 host_val, bool entry_only) 921 { 922 int i, j = 0; 923 struct msr_autoload *m = &vmx->msr_autoload; 924 925 switch (msr) { 926 case MSR_EFER: 927 if (cpu_has_load_ia32_efer()) { 928 add_atomic_switch_msr_special(vmx, 929 VM_ENTRY_LOAD_IA32_EFER, 930 VM_EXIT_LOAD_IA32_EFER, 931 GUEST_IA32_EFER, 932 HOST_IA32_EFER, 933 guest_val, host_val); 934 return; 935 } 936 break; 937 case MSR_CORE_PERF_GLOBAL_CTRL: 938 if (cpu_has_load_perf_global_ctrl()) { 939 add_atomic_switch_msr_special(vmx, 940 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 941 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 942 GUEST_IA32_PERF_GLOBAL_CTRL, 943 HOST_IA32_PERF_GLOBAL_CTRL, 944 guest_val, host_val); 945 return; 946 } 947 break; 948 case MSR_IA32_PEBS_ENABLE: 949 /* PEBS needs a quiescent period after being disabled (to write 950 * a record). Disabling PEBS through VMX MSR swapping doesn't 951 * provide that period, so a CPU could write host's record into 952 * guest's memory. 953 */ 954 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 955 } 956 957 i = vmx_find_msr_index(&m->guest, msr); 958 if (!entry_only) 959 j = vmx_find_msr_index(&m->host, msr); 960 961 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 962 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 963 printk_once(KERN_WARNING "Not enough msr switch entries. " 964 "Can't add msr %x\n", msr); 965 return; 966 } 967 if (i < 0) { 968 i = m->guest.nr++; 969 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 970 } 971 m->guest.val[i].index = msr; 972 m->guest.val[i].value = guest_val; 973 974 if (entry_only) 975 return; 976 977 if (j < 0) { 978 j = m->host.nr++; 979 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 980 } 981 m->host.val[j].index = msr; 982 m->host.val[j].value = host_val; 983 } 984 985 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 986 { 987 u64 guest_efer = vmx->vcpu.arch.efer; 988 u64 ignore_bits = 0; 989 990 /* Shadow paging assumes NX to be available. */ 991 if (!enable_ept) 992 guest_efer |= EFER_NX; 993 994 /* 995 * LMA and LME handled by hardware; SCE meaningless outside long mode. 996 */ 997 ignore_bits |= EFER_SCE; 998 #ifdef CONFIG_X86_64 999 ignore_bits |= EFER_LMA | EFER_LME; 1000 /* SCE is meaningful only in long mode on Intel */ 1001 if (guest_efer & EFER_LMA) 1002 ignore_bits &= ~(u64)EFER_SCE; 1003 #endif 1004 1005 /* 1006 * On EPT, we can't emulate NX, so we must switch EFER atomically. 1007 * On CPUs that support "load IA32_EFER", always switch EFER 1008 * atomically, since it's faster than switching it manually. 1009 */ 1010 if (cpu_has_load_ia32_efer() || 1011 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 1012 if (!(guest_efer & EFER_LMA)) 1013 guest_efer &= ~EFER_LME; 1014 if (guest_efer != host_efer) 1015 add_atomic_switch_msr(vmx, MSR_EFER, 1016 guest_efer, host_efer, false); 1017 else 1018 clear_atomic_switch_msr(vmx, MSR_EFER); 1019 return false; 1020 } else { 1021 clear_atomic_switch_msr(vmx, MSR_EFER); 1022 1023 guest_efer &= ~ignore_bits; 1024 guest_efer |= host_efer & ignore_bits; 1025 1026 vmx->guest_msrs[efer_offset].data = guest_efer; 1027 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1028 1029 return true; 1030 } 1031 } 1032 1033 #ifdef CONFIG_X86_32 1034 /* 1035 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1036 * VMCS rather than the segment table. KVM uses this helper to figure 1037 * out the current bases to poke them into the VMCS before entry. 1038 */ 1039 static unsigned long segment_base(u16 selector) 1040 { 1041 struct desc_struct *table; 1042 unsigned long v; 1043 1044 if (!(selector & ~SEGMENT_RPL_MASK)) 1045 return 0; 1046 1047 table = get_current_gdt_ro(); 1048 1049 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1050 u16 ldt_selector = kvm_read_ldt(); 1051 1052 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1053 return 0; 1054 1055 table = (struct desc_struct *)segment_base(ldt_selector); 1056 } 1057 v = get_desc_base(&table[selector >> 3]); 1058 return v; 1059 } 1060 #endif 1061 1062 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1063 { 1064 return (pt_mode == PT_MODE_HOST_GUEST) && 1065 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1066 } 1067 1068 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1069 { 1070 u32 i; 1071 1072 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1073 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1074 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1075 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1076 for (i = 0; i < addr_range; i++) { 1077 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1078 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1079 } 1080 } 1081 1082 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1083 { 1084 u32 i; 1085 1086 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1087 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1088 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1089 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1090 for (i = 0; i < addr_range; i++) { 1091 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1092 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1093 } 1094 } 1095 1096 static void pt_guest_enter(struct vcpu_vmx *vmx) 1097 { 1098 if (pt_mode == PT_MODE_SYSTEM) 1099 return; 1100 1101 /* 1102 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1103 * Save host state before VM entry. 1104 */ 1105 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1106 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1107 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1108 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1109 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1110 } 1111 } 1112 1113 static void pt_guest_exit(struct vcpu_vmx *vmx) 1114 { 1115 if (pt_mode == PT_MODE_SYSTEM) 1116 return; 1117 1118 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1119 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1120 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1121 } 1122 1123 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1124 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1125 } 1126 1127 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1128 unsigned long fs_base, unsigned long gs_base) 1129 { 1130 if (unlikely(fs_sel != host->fs_sel)) { 1131 if (!(fs_sel & 7)) 1132 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1133 else 1134 vmcs_write16(HOST_FS_SELECTOR, 0); 1135 host->fs_sel = fs_sel; 1136 } 1137 if (unlikely(gs_sel != host->gs_sel)) { 1138 if (!(gs_sel & 7)) 1139 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1140 else 1141 vmcs_write16(HOST_GS_SELECTOR, 0); 1142 host->gs_sel = gs_sel; 1143 } 1144 if (unlikely(fs_base != host->fs_base)) { 1145 vmcs_writel(HOST_FS_BASE, fs_base); 1146 host->fs_base = fs_base; 1147 } 1148 if (unlikely(gs_base != host->gs_base)) { 1149 vmcs_writel(HOST_GS_BASE, gs_base); 1150 host->gs_base = gs_base; 1151 } 1152 } 1153 1154 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1155 { 1156 struct vcpu_vmx *vmx = to_vmx(vcpu); 1157 struct vmcs_host_state *host_state; 1158 #ifdef CONFIG_X86_64 1159 int cpu = raw_smp_processor_id(); 1160 #endif 1161 unsigned long fs_base, gs_base; 1162 u16 fs_sel, gs_sel; 1163 int i; 1164 1165 vmx->req_immediate_exit = false; 1166 1167 /* 1168 * Note that guest MSRs to be saved/restored can also be changed 1169 * when guest state is loaded. This happens when guest transitions 1170 * to/from long-mode by setting MSR_EFER.LMA. 1171 */ 1172 if (!vmx->guest_msrs_ready) { 1173 vmx->guest_msrs_ready = true; 1174 for (i = 0; i < vmx->save_nmsrs; ++i) 1175 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1176 vmx->guest_msrs[i].data, 1177 vmx->guest_msrs[i].mask); 1178 1179 } 1180 1181 if (vmx->nested.need_vmcs12_to_shadow_sync) 1182 nested_sync_vmcs12_to_shadow(vcpu); 1183 1184 if (vmx->guest_state_loaded) 1185 return; 1186 1187 host_state = &vmx->loaded_vmcs->host_state; 1188 1189 /* 1190 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1191 * allow segment selectors with cpl > 0 or ti == 1. 1192 */ 1193 host_state->ldt_sel = kvm_read_ldt(); 1194 1195 #ifdef CONFIG_X86_64 1196 savesegment(ds, host_state->ds_sel); 1197 savesegment(es, host_state->es_sel); 1198 1199 gs_base = cpu_kernelmode_gs_base(cpu); 1200 if (likely(is_64bit_mm(current->mm))) { 1201 save_fsgs_for_kvm(); 1202 fs_sel = current->thread.fsindex; 1203 gs_sel = current->thread.gsindex; 1204 fs_base = current->thread.fsbase; 1205 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1206 } else { 1207 savesegment(fs, fs_sel); 1208 savesegment(gs, gs_sel); 1209 fs_base = read_msr(MSR_FS_BASE); 1210 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1211 } 1212 1213 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1214 #else 1215 savesegment(fs, fs_sel); 1216 savesegment(gs, gs_sel); 1217 fs_base = segment_base(fs_sel); 1218 gs_base = segment_base(gs_sel); 1219 #endif 1220 1221 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1222 vmx->guest_state_loaded = true; 1223 } 1224 1225 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1226 { 1227 struct vmcs_host_state *host_state; 1228 1229 if (!vmx->guest_state_loaded) 1230 return; 1231 1232 host_state = &vmx->loaded_vmcs->host_state; 1233 1234 ++vmx->vcpu.stat.host_state_reload; 1235 1236 #ifdef CONFIG_X86_64 1237 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1238 #endif 1239 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1240 kvm_load_ldt(host_state->ldt_sel); 1241 #ifdef CONFIG_X86_64 1242 load_gs_index(host_state->gs_sel); 1243 #else 1244 loadsegment(gs, host_state->gs_sel); 1245 #endif 1246 } 1247 if (host_state->fs_sel & 7) 1248 loadsegment(fs, host_state->fs_sel); 1249 #ifdef CONFIG_X86_64 1250 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1251 loadsegment(ds, host_state->ds_sel); 1252 loadsegment(es, host_state->es_sel); 1253 } 1254 #endif 1255 invalidate_tss_limit(); 1256 #ifdef CONFIG_X86_64 1257 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1258 #endif 1259 load_fixmap_gdt(raw_smp_processor_id()); 1260 vmx->guest_state_loaded = false; 1261 vmx->guest_msrs_ready = false; 1262 } 1263 1264 #ifdef CONFIG_X86_64 1265 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1266 { 1267 preempt_disable(); 1268 if (vmx->guest_state_loaded) 1269 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1270 preempt_enable(); 1271 return vmx->msr_guest_kernel_gs_base; 1272 } 1273 1274 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1275 { 1276 preempt_disable(); 1277 if (vmx->guest_state_loaded) 1278 wrmsrl(MSR_KERNEL_GS_BASE, data); 1279 preempt_enable(); 1280 vmx->msr_guest_kernel_gs_base = data; 1281 } 1282 #endif 1283 1284 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1285 { 1286 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1287 struct pi_desc old, new; 1288 unsigned int dest; 1289 1290 /* 1291 * In case of hot-plug or hot-unplug, we may have to undo 1292 * vmx_vcpu_pi_put even if there is no assigned device. And we 1293 * always keep PI.NDST up to date for simplicity: it makes the 1294 * code easier, and CPU migration is not a fast path. 1295 */ 1296 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1297 return; 1298 1299 /* 1300 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1301 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1302 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1303 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1304 * correctly. 1305 */ 1306 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1307 pi_clear_sn(pi_desc); 1308 goto after_clear_sn; 1309 } 1310 1311 /* The full case. */ 1312 do { 1313 old.control = new.control = pi_desc->control; 1314 1315 dest = cpu_physical_id(cpu); 1316 1317 if (x2apic_enabled()) 1318 new.ndst = dest; 1319 else 1320 new.ndst = (dest << 8) & 0xFF00; 1321 1322 new.sn = 0; 1323 } while (cmpxchg64(&pi_desc->control, old.control, 1324 new.control) != old.control); 1325 1326 after_clear_sn: 1327 1328 /* 1329 * Clear SN before reading the bitmap. The VT-d firmware 1330 * writes the bitmap and reads SN atomically (5.2.3 in the 1331 * spec), so it doesn't really have a memory barrier that 1332 * pairs with this, but we cannot do that and we need one. 1333 */ 1334 smp_mb__after_atomic(); 1335 1336 if (!pi_is_pir_empty(pi_desc)) 1337 pi_set_on(pi_desc); 1338 } 1339 1340 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1341 { 1342 struct vcpu_vmx *vmx = to_vmx(vcpu); 1343 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1344 1345 if (!already_loaded) { 1346 loaded_vmcs_clear(vmx->loaded_vmcs); 1347 local_irq_disable(); 1348 crash_disable_local_vmclear(cpu); 1349 1350 /* 1351 * Read loaded_vmcs->cpu should be before fetching 1352 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1353 * See the comments in __loaded_vmcs_clear(). 1354 */ 1355 smp_rmb(); 1356 1357 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1358 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1359 crash_enable_local_vmclear(cpu); 1360 local_irq_enable(); 1361 } 1362 1363 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1364 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1365 vmcs_load(vmx->loaded_vmcs->vmcs); 1366 indirect_branch_prediction_barrier(); 1367 } 1368 1369 if (!already_loaded) { 1370 void *gdt = get_current_gdt_ro(); 1371 unsigned long sysenter_esp; 1372 1373 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1374 1375 /* 1376 * Linux uses per-cpu TSS and GDT, so set these when switching 1377 * processors. See 22.2.4. 1378 */ 1379 vmcs_writel(HOST_TR_BASE, 1380 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1381 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1382 1383 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1384 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1385 1386 vmx->loaded_vmcs->cpu = cpu; 1387 } 1388 1389 /* Setup TSC multiplier */ 1390 if (kvm_has_tsc_control && 1391 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1392 decache_tsc_multiplier(vmx); 1393 } 1394 1395 /* 1396 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1397 * vcpu mutex is already taken. 1398 */ 1399 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1400 { 1401 struct vcpu_vmx *vmx = to_vmx(vcpu); 1402 1403 vmx_vcpu_load_vmcs(vcpu, cpu); 1404 1405 vmx_vcpu_pi_load(vcpu, cpu); 1406 1407 vmx->host_pkru = read_pkru(); 1408 vmx->host_debugctlmsr = get_debugctlmsr(); 1409 } 1410 1411 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1412 { 1413 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1414 1415 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1416 !irq_remapping_cap(IRQ_POSTING_CAP) || 1417 !kvm_vcpu_apicv_active(vcpu)) 1418 return; 1419 1420 /* Set SN when the vCPU is preempted */ 1421 if (vcpu->preempted) 1422 pi_set_sn(pi_desc); 1423 } 1424 1425 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1426 { 1427 vmx_vcpu_pi_put(vcpu); 1428 1429 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1430 } 1431 1432 static bool emulation_required(struct kvm_vcpu *vcpu) 1433 { 1434 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1435 } 1436 1437 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1438 { 1439 struct vcpu_vmx *vmx = to_vmx(vcpu); 1440 unsigned long rflags, save_rflags; 1441 1442 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1443 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1444 rflags = vmcs_readl(GUEST_RFLAGS); 1445 if (vmx->rmode.vm86_active) { 1446 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1447 save_rflags = vmx->rmode.save_rflags; 1448 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1449 } 1450 vmx->rflags = rflags; 1451 } 1452 return vmx->rflags; 1453 } 1454 1455 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1456 { 1457 struct vcpu_vmx *vmx = to_vmx(vcpu); 1458 unsigned long old_rflags; 1459 1460 if (enable_unrestricted_guest) { 1461 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1462 vmx->rflags = rflags; 1463 vmcs_writel(GUEST_RFLAGS, rflags); 1464 return; 1465 } 1466 1467 old_rflags = vmx_get_rflags(vcpu); 1468 vmx->rflags = rflags; 1469 if (vmx->rmode.vm86_active) { 1470 vmx->rmode.save_rflags = rflags; 1471 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1472 } 1473 vmcs_writel(GUEST_RFLAGS, rflags); 1474 1475 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1476 vmx->emulation_required = emulation_required(vcpu); 1477 } 1478 1479 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1480 { 1481 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1482 int ret = 0; 1483 1484 if (interruptibility & GUEST_INTR_STATE_STI) 1485 ret |= KVM_X86_SHADOW_INT_STI; 1486 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1487 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1488 1489 return ret; 1490 } 1491 1492 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1493 { 1494 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1495 u32 interruptibility = interruptibility_old; 1496 1497 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1498 1499 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1500 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1501 else if (mask & KVM_X86_SHADOW_INT_STI) 1502 interruptibility |= GUEST_INTR_STATE_STI; 1503 1504 if ((interruptibility != interruptibility_old)) 1505 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1506 } 1507 1508 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1509 { 1510 struct vcpu_vmx *vmx = to_vmx(vcpu); 1511 unsigned long value; 1512 1513 /* 1514 * Any MSR write that attempts to change bits marked reserved will 1515 * case a #GP fault. 1516 */ 1517 if (data & vmx->pt_desc.ctl_bitmask) 1518 return 1; 1519 1520 /* 1521 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1522 * result in a #GP unless the same write also clears TraceEn. 1523 */ 1524 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1525 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1526 return 1; 1527 1528 /* 1529 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1530 * and FabricEn would cause #GP, if 1531 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1532 */ 1533 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1534 !(data & RTIT_CTL_FABRIC_EN) && 1535 !intel_pt_validate_cap(vmx->pt_desc.caps, 1536 PT_CAP_single_range_output)) 1537 return 1; 1538 1539 /* 1540 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1541 * utilize encodings marked reserved will casue a #GP fault. 1542 */ 1543 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1544 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1545 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1546 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1547 return 1; 1548 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1549 PT_CAP_cycle_thresholds); 1550 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1551 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1552 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1553 return 1; 1554 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1555 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1556 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1557 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1558 return 1; 1559 1560 /* 1561 * If ADDRx_CFG is reserved or the encodings is >2 will 1562 * cause a #GP fault. 1563 */ 1564 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1565 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1566 return 1; 1567 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1568 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1569 return 1; 1570 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1571 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1572 return 1; 1573 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1574 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1575 return 1; 1576 1577 return 0; 1578 } 1579 1580 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1581 { 1582 unsigned long rip; 1583 1584 /* 1585 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1586 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1587 * set when EPT misconfig occurs. In practice, real hardware updates 1588 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1589 * (namely Hyper-V) don't set it due to it being undefined behavior, 1590 * i.e. we end up advancing IP with some random value. 1591 */ 1592 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1593 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1594 rip = kvm_rip_read(vcpu); 1595 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1596 kvm_rip_write(vcpu, rip); 1597 } else { 1598 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1599 return 0; 1600 } 1601 1602 /* skipping an emulated instruction also counts */ 1603 vmx_set_interrupt_shadow(vcpu, 0); 1604 1605 return 1; 1606 } 1607 1608 1609 /* 1610 * Recognizes a pending MTF VM-exit and records the nested state for later 1611 * delivery. 1612 */ 1613 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu) 1614 { 1615 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1616 struct vcpu_vmx *vmx = to_vmx(vcpu); 1617 1618 if (!is_guest_mode(vcpu)) 1619 return; 1620 1621 /* 1622 * Per the SDM, MTF takes priority over debug-trap exceptions besides 1623 * T-bit traps. As instruction emulation is completed (i.e. at the 1624 * instruction boundary), any #DB exception pending delivery must be a 1625 * debug-trap. Record the pending MTF state to be delivered in 1626 * vmx_check_nested_events(). 1627 */ 1628 if (nested_cpu_has_mtf(vmcs12) && 1629 (!vcpu->arch.exception.pending || 1630 vcpu->arch.exception.nr == DB_VECTOR)) 1631 vmx->nested.mtf_pending = true; 1632 else 1633 vmx->nested.mtf_pending = false; 1634 } 1635 1636 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu) 1637 { 1638 vmx_update_emulated_instruction(vcpu); 1639 return skip_emulated_instruction(vcpu); 1640 } 1641 1642 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1643 { 1644 /* 1645 * Ensure that we clear the HLT state in the VMCS. We don't need to 1646 * explicitly skip the instruction because if the HLT state is set, 1647 * then the instruction is already executing and RIP has already been 1648 * advanced. 1649 */ 1650 if (kvm_hlt_in_guest(vcpu->kvm) && 1651 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1652 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1653 } 1654 1655 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1656 { 1657 struct vcpu_vmx *vmx = to_vmx(vcpu); 1658 unsigned nr = vcpu->arch.exception.nr; 1659 bool has_error_code = vcpu->arch.exception.has_error_code; 1660 u32 error_code = vcpu->arch.exception.error_code; 1661 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1662 1663 kvm_deliver_exception_payload(vcpu); 1664 1665 if (has_error_code) { 1666 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1667 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1668 } 1669 1670 if (vmx->rmode.vm86_active) { 1671 int inc_eip = 0; 1672 if (kvm_exception_is_soft(nr)) 1673 inc_eip = vcpu->arch.event_exit_inst_len; 1674 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1675 return; 1676 } 1677 1678 WARN_ON_ONCE(vmx->emulation_required); 1679 1680 if (kvm_exception_is_soft(nr)) { 1681 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1682 vmx->vcpu.arch.event_exit_inst_len); 1683 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1684 } else 1685 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1686 1687 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1688 1689 vmx_clear_hlt(vcpu); 1690 } 1691 1692 static bool vmx_rdtscp_supported(void) 1693 { 1694 return cpu_has_vmx_rdtscp(); 1695 } 1696 1697 static bool vmx_invpcid_supported(void) 1698 { 1699 return cpu_has_vmx_invpcid(); 1700 } 1701 1702 /* 1703 * Swap MSR entry in host/guest MSR entry array. 1704 */ 1705 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1706 { 1707 struct shared_msr_entry tmp; 1708 1709 tmp = vmx->guest_msrs[to]; 1710 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1711 vmx->guest_msrs[from] = tmp; 1712 } 1713 1714 /* 1715 * Set up the vmcs to automatically save and restore system 1716 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1717 * mode, as fiddling with msrs is very expensive. 1718 */ 1719 static void setup_msrs(struct vcpu_vmx *vmx) 1720 { 1721 int save_nmsrs, index; 1722 1723 save_nmsrs = 0; 1724 #ifdef CONFIG_X86_64 1725 /* 1726 * The SYSCALL MSRs are only needed on long mode guests, and only 1727 * when EFER.SCE is set. 1728 */ 1729 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1730 index = __find_msr_index(vmx, MSR_STAR); 1731 if (index >= 0) 1732 move_msr_up(vmx, index, save_nmsrs++); 1733 index = __find_msr_index(vmx, MSR_LSTAR); 1734 if (index >= 0) 1735 move_msr_up(vmx, index, save_nmsrs++); 1736 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1737 if (index >= 0) 1738 move_msr_up(vmx, index, save_nmsrs++); 1739 } 1740 #endif 1741 index = __find_msr_index(vmx, MSR_EFER); 1742 if (index >= 0 && update_transition_efer(vmx, index)) 1743 move_msr_up(vmx, index, save_nmsrs++); 1744 index = __find_msr_index(vmx, MSR_TSC_AUX); 1745 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1746 move_msr_up(vmx, index, save_nmsrs++); 1747 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1748 if (index >= 0) 1749 move_msr_up(vmx, index, save_nmsrs++); 1750 1751 vmx->save_nmsrs = save_nmsrs; 1752 vmx->guest_msrs_ready = false; 1753 1754 if (cpu_has_vmx_msr_bitmap()) 1755 vmx_update_msr_bitmap(&vmx->vcpu); 1756 } 1757 1758 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1759 { 1760 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1761 1762 if (is_guest_mode(vcpu) && 1763 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1764 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1765 1766 return vcpu->arch.tsc_offset; 1767 } 1768 1769 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1770 { 1771 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1772 u64 g_tsc_offset = 0; 1773 1774 /* 1775 * We're here if L1 chose not to trap WRMSR to TSC. According 1776 * to the spec, this should set L1's TSC; The offset that L1 1777 * set for L2 remains unchanged, and still needs to be added 1778 * to the newly set TSC to get L2's TSC. 1779 */ 1780 if (is_guest_mode(vcpu) && 1781 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1782 g_tsc_offset = vmcs12->tsc_offset; 1783 1784 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1785 vcpu->arch.tsc_offset - g_tsc_offset, 1786 offset); 1787 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1788 return offset + g_tsc_offset; 1789 } 1790 1791 /* 1792 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1793 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1794 * all guests if the "nested" module option is off, and can also be disabled 1795 * for a single guest by disabling its VMX cpuid bit. 1796 */ 1797 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1798 { 1799 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1800 } 1801 1802 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1803 uint64_t val) 1804 { 1805 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1806 1807 return !(val & ~valid_bits); 1808 } 1809 1810 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1811 { 1812 switch (msr->index) { 1813 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1814 if (!nested) 1815 return 1; 1816 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1817 default: 1818 return 1; 1819 } 1820 } 1821 1822 /* 1823 * Reads an msr value (of 'msr_index') into 'pdata'. 1824 * Returns 0 on success, non-0 otherwise. 1825 * Assumes vcpu_load() was already called. 1826 */ 1827 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1828 { 1829 struct vcpu_vmx *vmx = to_vmx(vcpu); 1830 struct shared_msr_entry *msr; 1831 u32 index; 1832 1833 switch (msr_info->index) { 1834 #ifdef CONFIG_X86_64 1835 case MSR_FS_BASE: 1836 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1837 break; 1838 case MSR_GS_BASE: 1839 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1840 break; 1841 case MSR_KERNEL_GS_BASE: 1842 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1843 break; 1844 #endif 1845 case MSR_EFER: 1846 return kvm_get_msr_common(vcpu, msr_info); 1847 case MSR_IA32_TSX_CTRL: 1848 if (!msr_info->host_initiated && 1849 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1850 return 1; 1851 goto find_shared_msr; 1852 case MSR_IA32_UMWAIT_CONTROL: 1853 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1854 return 1; 1855 1856 msr_info->data = vmx->msr_ia32_umwait_control; 1857 break; 1858 case MSR_IA32_SPEC_CTRL: 1859 if (!msr_info->host_initiated && 1860 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1861 return 1; 1862 1863 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1864 break; 1865 case MSR_IA32_SYSENTER_CS: 1866 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1867 break; 1868 case MSR_IA32_SYSENTER_EIP: 1869 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1870 break; 1871 case MSR_IA32_SYSENTER_ESP: 1872 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1873 break; 1874 case MSR_IA32_BNDCFGS: 1875 if (!kvm_mpx_supported() || 1876 (!msr_info->host_initiated && 1877 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1878 return 1; 1879 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1880 break; 1881 case MSR_IA32_MCG_EXT_CTL: 1882 if (!msr_info->host_initiated && 1883 !(vmx->msr_ia32_feature_control & 1884 FEAT_CTL_LMCE_ENABLED)) 1885 return 1; 1886 msr_info->data = vcpu->arch.mcg_ext_ctl; 1887 break; 1888 case MSR_IA32_FEAT_CTL: 1889 msr_info->data = vmx->msr_ia32_feature_control; 1890 break; 1891 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1892 if (!nested_vmx_allowed(vcpu)) 1893 return 1; 1894 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1895 &msr_info->data)) 1896 return 1; 1897 /* 1898 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1899 * Hyper-V versions are still trying to use corresponding 1900 * features when they are exposed. Filter out the essential 1901 * minimum. 1902 */ 1903 if (!msr_info->host_initiated && 1904 vmx->nested.enlightened_vmcs_enabled) 1905 nested_evmcs_filter_control_msr(msr_info->index, 1906 &msr_info->data); 1907 break; 1908 case MSR_IA32_RTIT_CTL: 1909 if (pt_mode != PT_MODE_HOST_GUEST) 1910 return 1; 1911 msr_info->data = vmx->pt_desc.guest.ctl; 1912 break; 1913 case MSR_IA32_RTIT_STATUS: 1914 if (pt_mode != PT_MODE_HOST_GUEST) 1915 return 1; 1916 msr_info->data = vmx->pt_desc.guest.status; 1917 break; 1918 case MSR_IA32_RTIT_CR3_MATCH: 1919 if ((pt_mode != PT_MODE_HOST_GUEST) || 1920 !intel_pt_validate_cap(vmx->pt_desc.caps, 1921 PT_CAP_cr3_filtering)) 1922 return 1; 1923 msr_info->data = vmx->pt_desc.guest.cr3_match; 1924 break; 1925 case MSR_IA32_RTIT_OUTPUT_BASE: 1926 if ((pt_mode != PT_MODE_HOST_GUEST) || 1927 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1928 PT_CAP_topa_output) && 1929 !intel_pt_validate_cap(vmx->pt_desc.caps, 1930 PT_CAP_single_range_output))) 1931 return 1; 1932 msr_info->data = vmx->pt_desc.guest.output_base; 1933 break; 1934 case MSR_IA32_RTIT_OUTPUT_MASK: 1935 if ((pt_mode != PT_MODE_HOST_GUEST) || 1936 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1937 PT_CAP_topa_output) && 1938 !intel_pt_validate_cap(vmx->pt_desc.caps, 1939 PT_CAP_single_range_output))) 1940 return 1; 1941 msr_info->data = vmx->pt_desc.guest.output_mask; 1942 break; 1943 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1944 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1945 if ((pt_mode != PT_MODE_HOST_GUEST) || 1946 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1947 PT_CAP_num_address_ranges))) 1948 return 1; 1949 if (index % 2) 1950 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1951 else 1952 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1953 break; 1954 case MSR_TSC_AUX: 1955 if (!msr_info->host_initiated && 1956 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1957 return 1; 1958 goto find_shared_msr; 1959 default: 1960 find_shared_msr: 1961 msr = find_msr_entry(vmx, msr_info->index); 1962 if (msr) { 1963 msr_info->data = msr->data; 1964 break; 1965 } 1966 return kvm_get_msr_common(vcpu, msr_info); 1967 } 1968 1969 return 0; 1970 } 1971 1972 /* 1973 * Writes msr value into the appropriate "register". 1974 * Returns 0 on success, non-0 otherwise. 1975 * Assumes vcpu_load() was already called. 1976 */ 1977 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1978 { 1979 struct vcpu_vmx *vmx = to_vmx(vcpu); 1980 struct shared_msr_entry *msr; 1981 int ret = 0; 1982 u32 msr_index = msr_info->index; 1983 u64 data = msr_info->data; 1984 u32 index; 1985 1986 switch (msr_index) { 1987 case MSR_EFER: 1988 ret = kvm_set_msr_common(vcpu, msr_info); 1989 break; 1990 #ifdef CONFIG_X86_64 1991 case MSR_FS_BASE: 1992 vmx_segment_cache_clear(vmx); 1993 vmcs_writel(GUEST_FS_BASE, data); 1994 break; 1995 case MSR_GS_BASE: 1996 vmx_segment_cache_clear(vmx); 1997 vmcs_writel(GUEST_GS_BASE, data); 1998 break; 1999 case MSR_KERNEL_GS_BASE: 2000 vmx_write_guest_kernel_gs_base(vmx, data); 2001 break; 2002 #endif 2003 case MSR_IA32_SYSENTER_CS: 2004 if (is_guest_mode(vcpu)) 2005 get_vmcs12(vcpu)->guest_sysenter_cs = data; 2006 vmcs_write32(GUEST_SYSENTER_CS, data); 2007 break; 2008 case MSR_IA32_SYSENTER_EIP: 2009 if (is_guest_mode(vcpu)) 2010 get_vmcs12(vcpu)->guest_sysenter_eip = data; 2011 vmcs_writel(GUEST_SYSENTER_EIP, data); 2012 break; 2013 case MSR_IA32_SYSENTER_ESP: 2014 if (is_guest_mode(vcpu)) 2015 get_vmcs12(vcpu)->guest_sysenter_esp = data; 2016 vmcs_writel(GUEST_SYSENTER_ESP, data); 2017 break; 2018 case MSR_IA32_DEBUGCTLMSR: 2019 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 2020 VM_EXIT_SAVE_DEBUG_CONTROLS) 2021 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 2022 2023 ret = kvm_set_msr_common(vcpu, msr_info); 2024 break; 2025 2026 case MSR_IA32_BNDCFGS: 2027 if (!kvm_mpx_supported() || 2028 (!msr_info->host_initiated && 2029 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 2030 return 1; 2031 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 2032 (data & MSR_IA32_BNDCFGS_RSVD)) 2033 return 1; 2034 vmcs_write64(GUEST_BNDCFGS, data); 2035 break; 2036 case MSR_IA32_UMWAIT_CONTROL: 2037 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 2038 return 1; 2039 2040 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 2041 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 2042 return 1; 2043 2044 vmx->msr_ia32_umwait_control = data; 2045 break; 2046 case MSR_IA32_SPEC_CTRL: 2047 if (!msr_info->host_initiated && 2048 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2049 return 1; 2050 2051 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2052 return 1; 2053 2054 vmx->spec_ctrl = data; 2055 if (!data) 2056 break; 2057 2058 /* 2059 * For non-nested: 2060 * When it's written (to non-zero) for the first time, pass 2061 * it through. 2062 * 2063 * For nested: 2064 * The handling of the MSR bitmap for L2 guests is done in 2065 * nested_vmx_prepare_msr_bitmap. We should not touch the 2066 * vmcs02.msr_bitmap here since it gets completely overwritten 2067 * in the merging. We update the vmcs01 here for L1 as well 2068 * since it will end up touching the MSR anyway now. 2069 */ 2070 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2071 MSR_IA32_SPEC_CTRL, 2072 MSR_TYPE_RW); 2073 break; 2074 case MSR_IA32_TSX_CTRL: 2075 if (!msr_info->host_initiated && 2076 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2077 return 1; 2078 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2079 return 1; 2080 goto find_shared_msr; 2081 case MSR_IA32_PRED_CMD: 2082 if (!msr_info->host_initiated && 2083 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2084 return 1; 2085 2086 if (data & ~PRED_CMD_IBPB) 2087 return 1; 2088 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2089 return 1; 2090 if (!data) 2091 break; 2092 2093 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2094 2095 /* 2096 * For non-nested: 2097 * When it's written (to non-zero) for the first time, pass 2098 * it through. 2099 * 2100 * For nested: 2101 * The handling of the MSR bitmap for L2 guests is done in 2102 * nested_vmx_prepare_msr_bitmap. We should not touch the 2103 * vmcs02.msr_bitmap here since it gets completely overwritten 2104 * in the merging. 2105 */ 2106 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2107 MSR_TYPE_W); 2108 break; 2109 case MSR_IA32_CR_PAT: 2110 if (!kvm_pat_valid(data)) 2111 return 1; 2112 2113 if (is_guest_mode(vcpu) && 2114 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2115 get_vmcs12(vcpu)->guest_ia32_pat = data; 2116 2117 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2118 vmcs_write64(GUEST_IA32_PAT, data); 2119 vcpu->arch.pat = data; 2120 break; 2121 } 2122 ret = kvm_set_msr_common(vcpu, msr_info); 2123 break; 2124 case MSR_IA32_TSC_ADJUST: 2125 ret = kvm_set_msr_common(vcpu, msr_info); 2126 break; 2127 case MSR_IA32_MCG_EXT_CTL: 2128 if ((!msr_info->host_initiated && 2129 !(to_vmx(vcpu)->msr_ia32_feature_control & 2130 FEAT_CTL_LMCE_ENABLED)) || 2131 (data & ~MCG_EXT_CTL_LMCE_EN)) 2132 return 1; 2133 vcpu->arch.mcg_ext_ctl = data; 2134 break; 2135 case MSR_IA32_FEAT_CTL: 2136 if (!vmx_feature_control_msr_valid(vcpu, data) || 2137 (to_vmx(vcpu)->msr_ia32_feature_control & 2138 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2139 return 1; 2140 vmx->msr_ia32_feature_control = data; 2141 if (msr_info->host_initiated && data == 0) 2142 vmx_leave_nested(vcpu); 2143 break; 2144 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2145 if (!msr_info->host_initiated) 2146 return 1; /* they are read-only */ 2147 if (!nested_vmx_allowed(vcpu)) 2148 return 1; 2149 return vmx_set_vmx_msr(vcpu, msr_index, data); 2150 case MSR_IA32_RTIT_CTL: 2151 if ((pt_mode != PT_MODE_HOST_GUEST) || 2152 vmx_rtit_ctl_check(vcpu, data) || 2153 vmx->nested.vmxon) 2154 return 1; 2155 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2156 vmx->pt_desc.guest.ctl = data; 2157 pt_update_intercept_for_msr(vmx); 2158 break; 2159 case MSR_IA32_RTIT_STATUS: 2160 if (!pt_can_write_msr(vmx)) 2161 return 1; 2162 if (data & MSR_IA32_RTIT_STATUS_MASK) 2163 return 1; 2164 vmx->pt_desc.guest.status = data; 2165 break; 2166 case MSR_IA32_RTIT_CR3_MATCH: 2167 if (!pt_can_write_msr(vmx)) 2168 return 1; 2169 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2170 PT_CAP_cr3_filtering)) 2171 return 1; 2172 vmx->pt_desc.guest.cr3_match = data; 2173 break; 2174 case MSR_IA32_RTIT_OUTPUT_BASE: 2175 if (!pt_can_write_msr(vmx)) 2176 return 1; 2177 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2178 PT_CAP_topa_output) && 2179 !intel_pt_validate_cap(vmx->pt_desc.caps, 2180 PT_CAP_single_range_output)) 2181 return 1; 2182 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2183 return 1; 2184 vmx->pt_desc.guest.output_base = data; 2185 break; 2186 case MSR_IA32_RTIT_OUTPUT_MASK: 2187 if (!pt_can_write_msr(vmx)) 2188 return 1; 2189 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2190 PT_CAP_topa_output) && 2191 !intel_pt_validate_cap(vmx->pt_desc.caps, 2192 PT_CAP_single_range_output)) 2193 return 1; 2194 vmx->pt_desc.guest.output_mask = data; 2195 break; 2196 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2197 if (!pt_can_write_msr(vmx)) 2198 return 1; 2199 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2200 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2201 PT_CAP_num_address_ranges)) 2202 return 1; 2203 if (is_noncanonical_address(data, vcpu)) 2204 return 1; 2205 if (index % 2) 2206 vmx->pt_desc.guest.addr_b[index / 2] = data; 2207 else 2208 vmx->pt_desc.guest.addr_a[index / 2] = data; 2209 break; 2210 case MSR_TSC_AUX: 2211 if (!msr_info->host_initiated && 2212 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2213 return 1; 2214 /* Check reserved bit, higher 32 bits should be zero */ 2215 if ((data >> 32) != 0) 2216 return 1; 2217 goto find_shared_msr; 2218 2219 default: 2220 find_shared_msr: 2221 msr = find_msr_entry(vmx, msr_index); 2222 if (msr) 2223 ret = vmx_set_guest_msr(vmx, msr, data); 2224 else 2225 ret = kvm_set_msr_common(vcpu, msr_info); 2226 } 2227 2228 return ret; 2229 } 2230 2231 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2232 { 2233 kvm_register_mark_available(vcpu, reg); 2234 2235 switch (reg) { 2236 case VCPU_REGS_RSP: 2237 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2238 break; 2239 case VCPU_REGS_RIP: 2240 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2241 break; 2242 case VCPU_EXREG_PDPTR: 2243 if (enable_ept) 2244 ept_save_pdptrs(vcpu); 2245 break; 2246 case VCPU_EXREG_CR3: 2247 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2248 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2249 break; 2250 default: 2251 WARN_ON_ONCE(1); 2252 break; 2253 } 2254 } 2255 2256 static __init int cpu_has_kvm_support(void) 2257 { 2258 return cpu_has_vmx(); 2259 } 2260 2261 static __init int vmx_disabled_by_bios(void) 2262 { 2263 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2264 !boot_cpu_has(X86_FEATURE_VMX); 2265 } 2266 2267 static void kvm_cpu_vmxon(u64 addr) 2268 { 2269 cr4_set_bits(X86_CR4_VMXE); 2270 intel_pt_handle_vmx(1); 2271 2272 asm volatile ("vmxon %0" : : "m"(addr)); 2273 } 2274 2275 static int hardware_enable(void) 2276 { 2277 int cpu = raw_smp_processor_id(); 2278 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2279 2280 if (cr4_read_shadow() & X86_CR4_VMXE) 2281 return -EBUSY; 2282 2283 /* 2284 * This can happen if we hot-added a CPU but failed to allocate 2285 * VP assist page for it. 2286 */ 2287 if (static_branch_unlikely(&enable_evmcs) && 2288 !hv_get_vp_assist_page(cpu)) 2289 return -EFAULT; 2290 2291 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2292 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2293 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2294 2295 /* 2296 * Now we can enable the vmclear operation in kdump 2297 * since the loaded_vmcss_on_cpu list on this cpu 2298 * has been initialized. 2299 * 2300 * Though the cpu is not in VMX operation now, there 2301 * is no problem to enable the vmclear operation 2302 * for the loaded_vmcss_on_cpu list is empty! 2303 */ 2304 crash_enable_local_vmclear(cpu); 2305 2306 kvm_cpu_vmxon(phys_addr); 2307 if (enable_ept) 2308 ept_sync_global(); 2309 2310 return 0; 2311 } 2312 2313 static void vmclear_local_loaded_vmcss(void) 2314 { 2315 int cpu = raw_smp_processor_id(); 2316 struct loaded_vmcs *v, *n; 2317 2318 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2319 loaded_vmcss_on_cpu_link) 2320 __loaded_vmcs_clear(v); 2321 } 2322 2323 2324 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2325 * tricks. 2326 */ 2327 static void kvm_cpu_vmxoff(void) 2328 { 2329 asm volatile (__ex("vmxoff")); 2330 2331 intel_pt_handle_vmx(0); 2332 cr4_clear_bits(X86_CR4_VMXE); 2333 } 2334 2335 static void hardware_disable(void) 2336 { 2337 vmclear_local_loaded_vmcss(); 2338 kvm_cpu_vmxoff(); 2339 } 2340 2341 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2342 u32 msr, u32 *result) 2343 { 2344 u32 vmx_msr_low, vmx_msr_high; 2345 u32 ctl = ctl_min | ctl_opt; 2346 2347 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2348 2349 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2350 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2351 2352 /* Ensure minimum (required) set of control bits are supported. */ 2353 if (ctl_min & ~ctl) 2354 return -EIO; 2355 2356 *result = ctl; 2357 return 0; 2358 } 2359 2360 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2361 struct vmx_capability *vmx_cap) 2362 { 2363 u32 vmx_msr_low, vmx_msr_high; 2364 u32 min, opt, min2, opt2; 2365 u32 _pin_based_exec_control = 0; 2366 u32 _cpu_based_exec_control = 0; 2367 u32 _cpu_based_2nd_exec_control = 0; 2368 u32 _vmexit_control = 0; 2369 u32 _vmentry_control = 0; 2370 2371 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2372 min = CPU_BASED_HLT_EXITING | 2373 #ifdef CONFIG_X86_64 2374 CPU_BASED_CR8_LOAD_EXITING | 2375 CPU_BASED_CR8_STORE_EXITING | 2376 #endif 2377 CPU_BASED_CR3_LOAD_EXITING | 2378 CPU_BASED_CR3_STORE_EXITING | 2379 CPU_BASED_UNCOND_IO_EXITING | 2380 CPU_BASED_MOV_DR_EXITING | 2381 CPU_BASED_USE_TSC_OFFSETTING | 2382 CPU_BASED_MWAIT_EXITING | 2383 CPU_BASED_MONITOR_EXITING | 2384 CPU_BASED_INVLPG_EXITING | 2385 CPU_BASED_RDPMC_EXITING; 2386 2387 opt = CPU_BASED_TPR_SHADOW | 2388 CPU_BASED_USE_MSR_BITMAPS | 2389 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2390 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2391 &_cpu_based_exec_control) < 0) 2392 return -EIO; 2393 #ifdef CONFIG_X86_64 2394 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2395 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2396 ~CPU_BASED_CR8_STORE_EXITING; 2397 #endif 2398 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2399 min2 = 0; 2400 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2401 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2402 SECONDARY_EXEC_WBINVD_EXITING | 2403 SECONDARY_EXEC_ENABLE_VPID | 2404 SECONDARY_EXEC_ENABLE_EPT | 2405 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2406 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2407 SECONDARY_EXEC_DESC | 2408 SECONDARY_EXEC_RDTSCP | 2409 SECONDARY_EXEC_ENABLE_INVPCID | 2410 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2411 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2412 SECONDARY_EXEC_SHADOW_VMCS | 2413 SECONDARY_EXEC_XSAVES | 2414 SECONDARY_EXEC_RDSEED_EXITING | 2415 SECONDARY_EXEC_RDRAND_EXITING | 2416 SECONDARY_EXEC_ENABLE_PML | 2417 SECONDARY_EXEC_TSC_SCALING | 2418 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2419 SECONDARY_EXEC_PT_USE_GPA | 2420 SECONDARY_EXEC_PT_CONCEAL_VMX | 2421 SECONDARY_EXEC_ENABLE_VMFUNC | 2422 SECONDARY_EXEC_ENCLS_EXITING; 2423 if (adjust_vmx_controls(min2, opt2, 2424 MSR_IA32_VMX_PROCBASED_CTLS2, 2425 &_cpu_based_2nd_exec_control) < 0) 2426 return -EIO; 2427 } 2428 #ifndef CONFIG_X86_64 2429 if (!(_cpu_based_2nd_exec_control & 2430 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2431 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2432 #endif 2433 2434 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2435 _cpu_based_2nd_exec_control &= ~( 2436 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2437 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2438 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2439 2440 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2441 &vmx_cap->ept, &vmx_cap->vpid); 2442 2443 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2444 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2445 enabled */ 2446 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2447 CPU_BASED_CR3_STORE_EXITING | 2448 CPU_BASED_INVLPG_EXITING); 2449 } else if (vmx_cap->ept) { 2450 vmx_cap->ept = 0; 2451 pr_warn_once("EPT CAP should not exist if not support " 2452 "1-setting enable EPT VM-execution control\n"); 2453 } 2454 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2455 vmx_cap->vpid) { 2456 vmx_cap->vpid = 0; 2457 pr_warn_once("VPID CAP should not exist if not support " 2458 "1-setting enable VPID VM-execution control\n"); 2459 } 2460 2461 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2462 #ifdef CONFIG_X86_64 2463 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2464 #endif 2465 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2466 VM_EXIT_LOAD_IA32_PAT | 2467 VM_EXIT_LOAD_IA32_EFER | 2468 VM_EXIT_CLEAR_BNDCFGS | 2469 VM_EXIT_PT_CONCEAL_PIP | 2470 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2471 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2472 &_vmexit_control) < 0) 2473 return -EIO; 2474 2475 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2476 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2477 PIN_BASED_VMX_PREEMPTION_TIMER; 2478 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2479 &_pin_based_exec_control) < 0) 2480 return -EIO; 2481 2482 if (cpu_has_broken_vmx_preemption_timer()) 2483 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2484 if (!(_cpu_based_2nd_exec_control & 2485 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2486 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2487 2488 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2489 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2490 VM_ENTRY_LOAD_IA32_PAT | 2491 VM_ENTRY_LOAD_IA32_EFER | 2492 VM_ENTRY_LOAD_BNDCFGS | 2493 VM_ENTRY_PT_CONCEAL_PIP | 2494 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2495 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2496 &_vmentry_control) < 0) 2497 return -EIO; 2498 2499 /* 2500 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2501 * can't be used due to an errata where VM Exit may incorrectly clear 2502 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2503 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2504 */ 2505 if (boot_cpu_data.x86 == 0x6) { 2506 switch (boot_cpu_data.x86_model) { 2507 case 26: /* AAK155 */ 2508 case 30: /* AAP115 */ 2509 case 37: /* AAT100 */ 2510 case 44: /* BC86,AAY89,BD102 */ 2511 case 46: /* BA97 */ 2512 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2513 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2514 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2515 "does not work properly. Using workaround\n"); 2516 break; 2517 default: 2518 break; 2519 } 2520 } 2521 2522 2523 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2524 2525 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2526 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2527 return -EIO; 2528 2529 #ifdef CONFIG_X86_64 2530 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2531 if (vmx_msr_high & (1u<<16)) 2532 return -EIO; 2533 #endif 2534 2535 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2536 if (((vmx_msr_high >> 18) & 15) != 6) 2537 return -EIO; 2538 2539 vmcs_conf->size = vmx_msr_high & 0x1fff; 2540 vmcs_conf->order = get_order(vmcs_conf->size); 2541 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2542 2543 vmcs_conf->revision_id = vmx_msr_low; 2544 2545 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2546 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2547 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2548 vmcs_conf->vmexit_ctrl = _vmexit_control; 2549 vmcs_conf->vmentry_ctrl = _vmentry_control; 2550 2551 if (static_branch_unlikely(&enable_evmcs)) 2552 evmcs_sanitize_exec_ctrls(vmcs_conf); 2553 2554 return 0; 2555 } 2556 2557 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2558 { 2559 int node = cpu_to_node(cpu); 2560 struct page *pages; 2561 struct vmcs *vmcs; 2562 2563 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2564 if (!pages) 2565 return NULL; 2566 vmcs = page_address(pages); 2567 memset(vmcs, 0, vmcs_config.size); 2568 2569 /* KVM supports Enlightened VMCS v1 only */ 2570 if (static_branch_unlikely(&enable_evmcs)) 2571 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2572 else 2573 vmcs->hdr.revision_id = vmcs_config.revision_id; 2574 2575 if (shadow) 2576 vmcs->hdr.shadow_vmcs = 1; 2577 return vmcs; 2578 } 2579 2580 void free_vmcs(struct vmcs *vmcs) 2581 { 2582 free_pages((unsigned long)vmcs, vmcs_config.order); 2583 } 2584 2585 /* 2586 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2587 */ 2588 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2589 { 2590 if (!loaded_vmcs->vmcs) 2591 return; 2592 loaded_vmcs_clear(loaded_vmcs); 2593 free_vmcs(loaded_vmcs->vmcs); 2594 loaded_vmcs->vmcs = NULL; 2595 if (loaded_vmcs->msr_bitmap) 2596 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2597 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2598 } 2599 2600 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2601 { 2602 loaded_vmcs->vmcs = alloc_vmcs(false); 2603 if (!loaded_vmcs->vmcs) 2604 return -ENOMEM; 2605 2606 loaded_vmcs->shadow_vmcs = NULL; 2607 loaded_vmcs->hv_timer_soft_disabled = false; 2608 loaded_vmcs_init(loaded_vmcs); 2609 2610 if (cpu_has_vmx_msr_bitmap()) { 2611 loaded_vmcs->msr_bitmap = (unsigned long *) 2612 __get_free_page(GFP_KERNEL_ACCOUNT); 2613 if (!loaded_vmcs->msr_bitmap) 2614 goto out_vmcs; 2615 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2616 2617 if (IS_ENABLED(CONFIG_HYPERV) && 2618 static_branch_unlikely(&enable_evmcs) && 2619 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2620 struct hv_enlightened_vmcs *evmcs = 2621 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2622 2623 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2624 } 2625 } 2626 2627 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2628 memset(&loaded_vmcs->controls_shadow, 0, 2629 sizeof(struct vmcs_controls_shadow)); 2630 2631 return 0; 2632 2633 out_vmcs: 2634 free_loaded_vmcs(loaded_vmcs); 2635 return -ENOMEM; 2636 } 2637 2638 static void free_kvm_area(void) 2639 { 2640 int cpu; 2641 2642 for_each_possible_cpu(cpu) { 2643 free_vmcs(per_cpu(vmxarea, cpu)); 2644 per_cpu(vmxarea, cpu) = NULL; 2645 } 2646 } 2647 2648 static __init int alloc_kvm_area(void) 2649 { 2650 int cpu; 2651 2652 for_each_possible_cpu(cpu) { 2653 struct vmcs *vmcs; 2654 2655 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2656 if (!vmcs) { 2657 free_kvm_area(); 2658 return -ENOMEM; 2659 } 2660 2661 /* 2662 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2663 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2664 * revision_id reported by MSR_IA32_VMX_BASIC. 2665 * 2666 * However, even though not explicitly documented by 2667 * TLFS, VMXArea passed as VMXON argument should 2668 * still be marked with revision_id reported by 2669 * physical CPU. 2670 */ 2671 if (static_branch_unlikely(&enable_evmcs)) 2672 vmcs->hdr.revision_id = vmcs_config.revision_id; 2673 2674 per_cpu(vmxarea, cpu) = vmcs; 2675 } 2676 return 0; 2677 } 2678 2679 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2680 struct kvm_segment *save) 2681 { 2682 if (!emulate_invalid_guest_state) { 2683 /* 2684 * CS and SS RPL should be equal during guest entry according 2685 * to VMX spec, but in reality it is not always so. Since vcpu 2686 * is in the middle of the transition from real mode to 2687 * protected mode it is safe to assume that RPL 0 is a good 2688 * default value. 2689 */ 2690 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2691 save->selector &= ~SEGMENT_RPL_MASK; 2692 save->dpl = save->selector & SEGMENT_RPL_MASK; 2693 save->s = 1; 2694 } 2695 vmx_set_segment(vcpu, save, seg); 2696 } 2697 2698 static void enter_pmode(struct kvm_vcpu *vcpu) 2699 { 2700 unsigned long flags; 2701 struct vcpu_vmx *vmx = to_vmx(vcpu); 2702 2703 /* 2704 * Update real mode segment cache. It may be not up-to-date if sement 2705 * register was written while vcpu was in a guest mode. 2706 */ 2707 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2708 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2709 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2710 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2711 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2712 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2713 2714 vmx->rmode.vm86_active = 0; 2715 2716 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2717 2718 flags = vmcs_readl(GUEST_RFLAGS); 2719 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2720 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2721 vmcs_writel(GUEST_RFLAGS, flags); 2722 2723 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2724 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2725 2726 update_exception_bitmap(vcpu); 2727 2728 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2729 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2730 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2731 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2732 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2733 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2734 } 2735 2736 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2737 { 2738 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2739 struct kvm_segment var = *save; 2740 2741 var.dpl = 0x3; 2742 if (seg == VCPU_SREG_CS) 2743 var.type = 0x3; 2744 2745 if (!emulate_invalid_guest_state) { 2746 var.selector = var.base >> 4; 2747 var.base = var.base & 0xffff0; 2748 var.limit = 0xffff; 2749 var.g = 0; 2750 var.db = 0; 2751 var.present = 1; 2752 var.s = 1; 2753 var.l = 0; 2754 var.unusable = 0; 2755 var.type = 0x3; 2756 var.avl = 0; 2757 if (save->base & 0xf) 2758 printk_once(KERN_WARNING "kvm: segment base is not " 2759 "paragraph aligned when entering " 2760 "protected mode (seg=%d)", seg); 2761 } 2762 2763 vmcs_write16(sf->selector, var.selector); 2764 vmcs_writel(sf->base, var.base); 2765 vmcs_write32(sf->limit, var.limit); 2766 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2767 } 2768 2769 static void enter_rmode(struct kvm_vcpu *vcpu) 2770 { 2771 unsigned long flags; 2772 struct vcpu_vmx *vmx = to_vmx(vcpu); 2773 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2774 2775 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2776 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2777 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2778 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2779 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2780 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2781 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2782 2783 vmx->rmode.vm86_active = 1; 2784 2785 /* 2786 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2787 * vcpu. Warn the user that an update is overdue. 2788 */ 2789 if (!kvm_vmx->tss_addr) 2790 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2791 "called before entering vcpu\n"); 2792 2793 vmx_segment_cache_clear(vmx); 2794 2795 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2796 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2797 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2798 2799 flags = vmcs_readl(GUEST_RFLAGS); 2800 vmx->rmode.save_rflags = flags; 2801 2802 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2803 2804 vmcs_writel(GUEST_RFLAGS, flags); 2805 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2806 update_exception_bitmap(vcpu); 2807 2808 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2809 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2810 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2811 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2812 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2813 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2814 2815 kvm_mmu_reset_context(vcpu); 2816 } 2817 2818 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2819 { 2820 struct vcpu_vmx *vmx = to_vmx(vcpu); 2821 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2822 2823 if (!msr) 2824 return; 2825 2826 vcpu->arch.efer = efer; 2827 if (efer & EFER_LMA) { 2828 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2829 msr->data = efer; 2830 } else { 2831 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2832 2833 msr->data = efer & ~EFER_LME; 2834 } 2835 setup_msrs(vmx); 2836 } 2837 2838 #ifdef CONFIG_X86_64 2839 2840 static void enter_lmode(struct kvm_vcpu *vcpu) 2841 { 2842 u32 guest_tr_ar; 2843 2844 vmx_segment_cache_clear(to_vmx(vcpu)); 2845 2846 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2847 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2848 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2849 __func__); 2850 vmcs_write32(GUEST_TR_AR_BYTES, 2851 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2852 | VMX_AR_TYPE_BUSY_64_TSS); 2853 } 2854 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2855 } 2856 2857 static void exit_lmode(struct kvm_vcpu *vcpu) 2858 { 2859 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2860 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2861 } 2862 2863 #endif 2864 2865 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2866 { 2867 int vpid = to_vmx(vcpu)->vpid; 2868 2869 if (!vpid_sync_vcpu_addr(vpid, addr)) 2870 vpid_sync_context(vpid); 2871 2872 /* 2873 * If VPIDs are not supported or enabled, then the above is a no-op. 2874 * But we don't really need a TLB flush in that case anyway, because 2875 * each VM entry/exit includes an implicit flush when VPID is 0. 2876 */ 2877 } 2878 2879 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2880 { 2881 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2882 2883 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2884 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2885 } 2886 2887 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2888 { 2889 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2890 2891 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2892 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2893 } 2894 2895 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2896 { 2897 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2898 2899 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2900 return; 2901 2902 if (is_pae_paging(vcpu)) { 2903 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2904 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2905 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2906 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2907 } 2908 } 2909 2910 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2911 { 2912 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2913 2914 if (is_pae_paging(vcpu)) { 2915 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2916 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2917 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2918 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2919 } 2920 2921 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2922 } 2923 2924 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2925 unsigned long cr0, 2926 struct kvm_vcpu *vcpu) 2927 { 2928 struct vcpu_vmx *vmx = to_vmx(vcpu); 2929 2930 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2931 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2932 if (!(cr0 & X86_CR0_PG)) { 2933 /* From paging/starting to nonpaging */ 2934 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2935 CPU_BASED_CR3_STORE_EXITING); 2936 vcpu->arch.cr0 = cr0; 2937 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2938 } else if (!is_paging(vcpu)) { 2939 /* From nonpaging to paging */ 2940 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2941 CPU_BASED_CR3_STORE_EXITING); 2942 vcpu->arch.cr0 = cr0; 2943 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2944 } 2945 2946 if (!(cr0 & X86_CR0_WP)) 2947 *hw_cr0 &= ~X86_CR0_WP; 2948 } 2949 2950 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2951 { 2952 struct vcpu_vmx *vmx = to_vmx(vcpu); 2953 unsigned long hw_cr0; 2954 2955 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2956 if (enable_unrestricted_guest) 2957 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2958 else { 2959 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2960 2961 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2962 enter_pmode(vcpu); 2963 2964 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2965 enter_rmode(vcpu); 2966 } 2967 2968 #ifdef CONFIG_X86_64 2969 if (vcpu->arch.efer & EFER_LME) { 2970 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2971 enter_lmode(vcpu); 2972 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2973 exit_lmode(vcpu); 2974 } 2975 #endif 2976 2977 if (enable_ept && !enable_unrestricted_guest) 2978 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2979 2980 vmcs_writel(CR0_READ_SHADOW, cr0); 2981 vmcs_writel(GUEST_CR0, hw_cr0); 2982 vcpu->arch.cr0 = cr0; 2983 2984 /* depends on vcpu->arch.cr0 to be set to a new value */ 2985 vmx->emulation_required = emulation_required(vcpu); 2986 } 2987 2988 static int get_ept_level(struct kvm_vcpu *vcpu) 2989 { 2990 /* Nested EPT currently only supports 4-level walks. */ 2991 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu))) 2992 return 4; 2993 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2994 return 5; 2995 return 4; 2996 } 2997 2998 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2999 { 3000 u64 eptp = VMX_EPTP_MT_WB; 3001 3002 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 3003 3004 if (enable_ept_ad_bits && 3005 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 3006 eptp |= VMX_EPTP_AD_ENABLE_BIT; 3007 eptp |= (root_hpa & PAGE_MASK); 3008 3009 return eptp; 3010 } 3011 3012 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 3013 { 3014 struct kvm *kvm = vcpu->kvm; 3015 bool update_guest_cr3 = true; 3016 unsigned long guest_cr3; 3017 u64 eptp; 3018 3019 guest_cr3 = cr3; 3020 if (enable_ept) { 3021 eptp = construct_eptp(vcpu, cr3); 3022 vmcs_write64(EPT_POINTER, eptp); 3023 3024 if (kvm_x86_ops->tlb_remote_flush) { 3025 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3026 to_vmx(vcpu)->ept_pointer = eptp; 3027 to_kvm_vmx(kvm)->ept_pointers_match 3028 = EPT_POINTERS_CHECK; 3029 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3030 } 3031 3032 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 3033 if (is_guest_mode(vcpu)) 3034 update_guest_cr3 = false; 3035 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 3036 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3037 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 3038 guest_cr3 = vcpu->arch.cr3; 3039 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3040 update_guest_cr3 = false; 3041 ept_load_pdptrs(vcpu); 3042 } 3043 3044 if (update_guest_cr3) 3045 vmcs_writel(GUEST_CR3, guest_cr3); 3046 } 3047 3048 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3049 { 3050 struct vcpu_vmx *vmx = to_vmx(vcpu); 3051 /* 3052 * Pass through host's Machine Check Enable value to hw_cr4, which 3053 * is in force while we are in guest mode. Do not let guests control 3054 * this bit, even if host CR4.MCE == 0. 3055 */ 3056 unsigned long hw_cr4; 3057 3058 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3059 if (enable_unrestricted_guest) 3060 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3061 else if (vmx->rmode.vm86_active) 3062 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3063 else 3064 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3065 3066 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3067 if (cr4 & X86_CR4_UMIP) { 3068 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3069 hw_cr4 &= ~X86_CR4_UMIP; 3070 } else if (!is_guest_mode(vcpu) || 3071 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3072 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3073 } 3074 } 3075 3076 if (cr4 & X86_CR4_VMXE) { 3077 /* 3078 * To use VMXON (and later other VMX instructions), a guest 3079 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3080 * So basically the check on whether to allow nested VMX 3081 * is here. We operate under the default treatment of SMM, 3082 * so VMX cannot be enabled under SMM. 3083 */ 3084 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3085 return 1; 3086 } 3087 3088 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3089 return 1; 3090 3091 vcpu->arch.cr4 = cr4; 3092 3093 if (!enable_unrestricted_guest) { 3094 if (enable_ept) { 3095 if (!is_paging(vcpu)) { 3096 hw_cr4 &= ~X86_CR4_PAE; 3097 hw_cr4 |= X86_CR4_PSE; 3098 } else if (!(cr4 & X86_CR4_PAE)) { 3099 hw_cr4 &= ~X86_CR4_PAE; 3100 } 3101 } 3102 3103 /* 3104 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3105 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3106 * to be manually disabled when guest switches to non-paging 3107 * mode. 3108 * 3109 * If !enable_unrestricted_guest, the CPU is always running 3110 * with CR0.PG=1 and CR4 needs to be modified. 3111 * If enable_unrestricted_guest, the CPU automatically 3112 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3113 */ 3114 if (!is_paging(vcpu)) 3115 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3116 } 3117 3118 vmcs_writel(CR4_READ_SHADOW, cr4); 3119 vmcs_writel(GUEST_CR4, hw_cr4); 3120 return 0; 3121 } 3122 3123 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3124 { 3125 struct vcpu_vmx *vmx = to_vmx(vcpu); 3126 u32 ar; 3127 3128 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3129 *var = vmx->rmode.segs[seg]; 3130 if (seg == VCPU_SREG_TR 3131 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3132 return; 3133 var->base = vmx_read_guest_seg_base(vmx, seg); 3134 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3135 return; 3136 } 3137 var->base = vmx_read_guest_seg_base(vmx, seg); 3138 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3139 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3140 ar = vmx_read_guest_seg_ar(vmx, seg); 3141 var->unusable = (ar >> 16) & 1; 3142 var->type = ar & 15; 3143 var->s = (ar >> 4) & 1; 3144 var->dpl = (ar >> 5) & 3; 3145 /* 3146 * Some userspaces do not preserve unusable property. Since usable 3147 * segment has to be present according to VMX spec we can use present 3148 * property to amend userspace bug by making unusable segment always 3149 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3150 * segment as unusable. 3151 */ 3152 var->present = !var->unusable; 3153 var->avl = (ar >> 12) & 1; 3154 var->l = (ar >> 13) & 1; 3155 var->db = (ar >> 14) & 1; 3156 var->g = (ar >> 15) & 1; 3157 } 3158 3159 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3160 { 3161 struct kvm_segment s; 3162 3163 if (to_vmx(vcpu)->rmode.vm86_active) { 3164 vmx_get_segment(vcpu, &s, seg); 3165 return s.base; 3166 } 3167 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3168 } 3169 3170 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3171 { 3172 struct vcpu_vmx *vmx = to_vmx(vcpu); 3173 3174 if (unlikely(vmx->rmode.vm86_active)) 3175 return 0; 3176 else { 3177 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3178 return VMX_AR_DPL(ar); 3179 } 3180 } 3181 3182 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3183 { 3184 u32 ar; 3185 3186 if (var->unusable || !var->present) 3187 ar = 1 << 16; 3188 else { 3189 ar = var->type & 15; 3190 ar |= (var->s & 1) << 4; 3191 ar |= (var->dpl & 3) << 5; 3192 ar |= (var->present & 1) << 7; 3193 ar |= (var->avl & 1) << 12; 3194 ar |= (var->l & 1) << 13; 3195 ar |= (var->db & 1) << 14; 3196 ar |= (var->g & 1) << 15; 3197 } 3198 3199 return ar; 3200 } 3201 3202 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3203 { 3204 struct vcpu_vmx *vmx = to_vmx(vcpu); 3205 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3206 3207 vmx_segment_cache_clear(vmx); 3208 3209 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3210 vmx->rmode.segs[seg] = *var; 3211 if (seg == VCPU_SREG_TR) 3212 vmcs_write16(sf->selector, var->selector); 3213 else if (var->s) 3214 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3215 goto out; 3216 } 3217 3218 vmcs_writel(sf->base, var->base); 3219 vmcs_write32(sf->limit, var->limit); 3220 vmcs_write16(sf->selector, var->selector); 3221 3222 /* 3223 * Fix the "Accessed" bit in AR field of segment registers for older 3224 * qemu binaries. 3225 * IA32 arch specifies that at the time of processor reset the 3226 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3227 * is setting it to 0 in the userland code. This causes invalid guest 3228 * state vmexit when "unrestricted guest" mode is turned on. 3229 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3230 * tree. Newer qemu binaries with that qemu fix would not need this 3231 * kvm hack. 3232 */ 3233 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3234 var->type |= 0x1; /* Accessed */ 3235 3236 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3237 3238 out: 3239 vmx->emulation_required = emulation_required(vcpu); 3240 } 3241 3242 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3243 { 3244 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3245 3246 *db = (ar >> 14) & 1; 3247 *l = (ar >> 13) & 1; 3248 } 3249 3250 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3251 { 3252 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3253 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3254 } 3255 3256 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3257 { 3258 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3259 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3260 } 3261 3262 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3263 { 3264 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3265 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3266 } 3267 3268 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3269 { 3270 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3271 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3272 } 3273 3274 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3275 { 3276 struct kvm_segment var; 3277 u32 ar; 3278 3279 vmx_get_segment(vcpu, &var, seg); 3280 var.dpl = 0x3; 3281 if (seg == VCPU_SREG_CS) 3282 var.type = 0x3; 3283 ar = vmx_segment_access_rights(&var); 3284 3285 if (var.base != (var.selector << 4)) 3286 return false; 3287 if (var.limit != 0xffff) 3288 return false; 3289 if (ar != 0xf3) 3290 return false; 3291 3292 return true; 3293 } 3294 3295 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3296 { 3297 struct kvm_segment cs; 3298 unsigned int cs_rpl; 3299 3300 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3301 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3302 3303 if (cs.unusable) 3304 return false; 3305 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3306 return false; 3307 if (!cs.s) 3308 return false; 3309 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3310 if (cs.dpl > cs_rpl) 3311 return false; 3312 } else { 3313 if (cs.dpl != cs_rpl) 3314 return false; 3315 } 3316 if (!cs.present) 3317 return false; 3318 3319 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3320 return true; 3321 } 3322 3323 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3324 { 3325 struct kvm_segment ss; 3326 unsigned int ss_rpl; 3327 3328 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3329 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3330 3331 if (ss.unusable) 3332 return true; 3333 if (ss.type != 3 && ss.type != 7) 3334 return false; 3335 if (!ss.s) 3336 return false; 3337 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3338 return false; 3339 if (!ss.present) 3340 return false; 3341 3342 return true; 3343 } 3344 3345 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3346 { 3347 struct kvm_segment var; 3348 unsigned int rpl; 3349 3350 vmx_get_segment(vcpu, &var, seg); 3351 rpl = var.selector & SEGMENT_RPL_MASK; 3352 3353 if (var.unusable) 3354 return true; 3355 if (!var.s) 3356 return false; 3357 if (!var.present) 3358 return false; 3359 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3360 if (var.dpl < rpl) /* DPL < RPL */ 3361 return false; 3362 } 3363 3364 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3365 * rights flags 3366 */ 3367 return true; 3368 } 3369 3370 static bool tr_valid(struct kvm_vcpu *vcpu) 3371 { 3372 struct kvm_segment tr; 3373 3374 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3375 3376 if (tr.unusable) 3377 return false; 3378 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3379 return false; 3380 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3381 return false; 3382 if (!tr.present) 3383 return false; 3384 3385 return true; 3386 } 3387 3388 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3389 { 3390 struct kvm_segment ldtr; 3391 3392 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3393 3394 if (ldtr.unusable) 3395 return true; 3396 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3397 return false; 3398 if (ldtr.type != 2) 3399 return false; 3400 if (!ldtr.present) 3401 return false; 3402 3403 return true; 3404 } 3405 3406 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3407 { 3408 struct kvm_segment cs, ss; 3409 3410 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3411 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3412 3413 return ((cs.selector & SEGMENT_RPL_MASK) == 3414 (ss.selector & SEGMENT_RPL_MASK)); 3415 } 3416 3417 /* 3418 * Check if guest state is valid. Returns true if valid, false if 3419 * not. 3420 * We assume that registers are always usable 3421 */ 3422 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3423 { 3424 if (enable_unrestricted_guest) 3425 return true; 3426 3427 /* real mode guest state checks */ 3428 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3429 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3430 return false; 3431 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3432 return false; 3433 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3434 return false; 3435 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3436 return false; 3437 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3438 return false; 3439 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3440 return false; 3441 } else { 3442 /* protected mode guest state checks */ 3443 if (!cs_ss_rpl_check(vcpu)) 3444 return false; 3445 if (!code_segment_valid(vcpu)) 3446 return false; 3447 if (!stack_segment_valid(vcpu)) 3448 return false; 3449 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3450 return false; 3451 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3452 return false; 3453 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3454 return false; 3455 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3456 return false; 3457 if (!tr_valid(vcpu)) 3458 return false; 3459 if (!ldtr_valid(vcpu)) 3460 return false; 3461 } 3462 /* TODO: 3463 * - Add checks on RIP 3464 * - Add checks on RFLAGS 3465 */ 3466 3467 return true; 3468 } 3469 3470 static int init_rmode_tss(struct kvm *kvm) 3471 { 3472 gfn_t fn; 3473 u16 data = 0; 3474 int idx, r; 3475 3476 idx = srcu_read_lock(&kvm->srcu); 3477 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3478 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3479 if (r < 0) 3480 goto out; 3481 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3482 r = kvm_write_guest_page(kvm, fn++, &data, 3483 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3484 if (r < 0) 3485 goto out; 3486 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3487 if (r < 0) 3488 goto out; 3489 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3490 if (r < 0) 3491 goto out; 3492 data = ~0; 3493 r = kvm_write_guest_page(kvm, fn, &data, 3494 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3495 sizeof(u8)); 3496 out: 3497 srcu_read_unlock(&kvm->srcu, idx); 3498 return r; 3499 } 3500 3501 static int init_rmode_identity_map(struct kvm *kvm) 3502 { 3503 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3504 int i, r = 0; 3505 kvm_pfn_t identity_map_pfn; 3506 u32 tmp; 3507 3508 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3509 mutex_lock(&kvm->slots_lock); 3510 3511 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3512 goto out; 3513 3514 if (!kvm_vmx->ept_identity_map_addr) 3515 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3516 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3517 3518 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3519 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3520 if (r < 0) 3521 goto out; 3522 3523 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3524 if (r < 0) 3525 goto out; 3526 /* Set up identity-mapping pagetable for EPT in real mode */ 3527 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3528 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3529 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3530 r = kvm_write_guest_page(kvm, identity_map_pfn, 3531 &tmp, i * sizeof(tmp), sizeof(tmp)); 3532 if (r < 0) 3533 goto out; 3534 } 3535 kvm_vmx->ept_identity_pagetable_done = true; 3536 3537 out: 3538 mutex_unlock(&kvm->slots_lock); 3539 return r; 3540 } 3541 3542 static void seg_setup(int seg) 3543 { 3544 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3545 unsigned int ar; 3546 3547 vmcs_write16(sf->selector, 0); 3548 vmcs_writel(sf->base, 0); 3549 vmcs_write32(sf->limit, 0xffff); 3550 ar = 0x93; 3551 if (seg == VCPU_SREG_CS) 3552 ar |= 0x08; /* code segment */ 3553 3554 vmcs_write32(sf->ar_bytes, ar); 3555 } 3556 3557 static int alloc_apic_access_page(struct kvm *kvm) 3558 { 3559 struct page *page; 3560 int r = 0; 3561 3562 mutex_lock(&kvm->slots_lock); 3563 if (kvm->arch.apic_access_page_done) 3564 goto out; 3565 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3566 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3567 if (r) 3568 goto out; 3569 3570 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3571 if (is_error_page(page)) { 3572 r = -EFAULT; 3573 goto out; 3574 } 3575 3576 /* 3577 * Do not pin the page in memory, so that memory hot-unplug 3578 * is able to migrate it. 3579 */ 3580 put_page(page); 3581 kvm->arch.apic_access_page_done = true; 3582 out: 3583 mutex_unlock(&kvm->slots_lock); 3584 return r; 3585 } 3586 3587 int allocate_vpid(void) 3588 { 3589 int vpid; 3590 3591 if (!enable_vpid) 3592 return 0; 3593 spin_lock(&vmx_vpid_lock); 3594 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3595 if (vpid < VMX_NR_VPIDS) 3596 __set_bit(vpid, vmx_vpid_bitmap); 3597 else 3598 vpid = 0; 3599 spin_unlock(&vmx_vpid_lock); 3600 return vpid; 3601 } 3602 3603 void free_vpid(int vpid) 3604 { 3605 if (!enable_vpid || vpid == 0) 3606 return; 3607 spin_lock(&vmx_vpid_lock); 3608 __clear_bit(vpid, vmx_vpid_bitmap); 3609 spin_unlock(&vmx_vpid_lock); 3610 } 3611 3612 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3613 u32 msr, int type) 3614 { 3615 int f = sizeof(unsigned long); 3616 3617 if (!cpu_has_vmx_msr_bitmap()) 3618 return; 3619 3620 if (static_branch_unlikely(&enable_evmcs)) 3621 evmcs_touch_msr_bitmap(); 3622 3623 /* 3624 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3625 * have the write-low and read-high bitmap offsets the wrong way round. 3626 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3627 */ 3628 if (msr <= 0x1fff) { 3629 if (type & MSR_TYPE_R) 3630 /* read-low */ 3631 __clear_bit(msr, msr_bitmap + 0x000 / f); 3632 3633 if (type & MSR_TYPE_W) 3634 /* write-low */ 3635 __clear_bit(msr, msr_bitmap + 0x800 / f); 3636 3637 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3638 msr &= 0x1fff; 3639 if (type & MSR_TYPE_R) 3640 /* read-high */ 3641 __clear_bit(msr, msr_bitmap + 0x400 / f); 3642 3643 if (type & MSR_TYPE_W) 3644 /* write-high */ 3645 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3646 3647 } 3648 } 3649 3650 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3651 u32 msr, int type) 3652 { 3653 int f = sizeof(unsigned long); 3654 3655 if (!cpu_has_vmx_msr_bitmap()) 3656 return; 3657 3658 if (static_branch_unlikely(&enable_evmcs)) 3659 evmcs_touch_msr_bitmap(); 3660 3661 /* 3662 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3663 * have the write-low and read-high bitmap offsets the wrong way round. 3664 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3665 */ 3666 if (msr <= 0x1fff) { 3667 if (type & MSR_TYPE_R) 3668 /* read-low */ 3669 __set_bit(msr, msr_bitmap + 0x000 / f); 3670 3671 if (type & MSR_TYPE_W) 3672 /* write-low */ 3673 __set_bit(msr, msr_bitmap + 0x800 / f); 3674 3675 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3676 msr &= 0x1fff; 3677 if (type & MSR_TYPE_R) 3678 /* read-high */ 3679 __set_bit(msr, msr_bitmap + 0x400 / f); 3680 3681 if (type & MSR_TYPE_W) 3682 /* write-high */ 3683 __set_bit(msr, msr_bitmap + 0xc00 / f); 3684 3685 } 3686 } 3687 3688 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3689 u32 msr, int type, bool value) 3690 { 3691 if (value) 3692 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3693 else 3694 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3695 } 3696 3697 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3698 { 3699 u8 mode = 0; 3700 3701 if (cpu_has_secondary_exec_ctrls() && 3702 (secondary_exec_controls_get(to_vmx(vcpu)) & 3703 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3704 mode |= MSR_BITMAP_MODE_X2APIC; 3705 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3706 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3707 } 3708 3709 return mode; 3710 } 3711 3712 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3713 u8 mode) 3714 { 3715 int msr; 3716 3717 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3718 unsigned word = msr / BITS_PER_LONG; 3719 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3720 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3721 } 3722 3723 if (mode & MSR_BITMAP_MODE_X2APIC) { 3724 /* 3725 * TPR reads and writes can be virtualized even if virtual interrupt 3726 * delivery is not in use. 3727 */ 3728 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3729 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3730 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3731 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3732 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3733 } 3734 } 3735 } 3736 3737 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3738 { 3739 struct vcpu_vmx *vmx = to_vmx(vcpu); 3740 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3741 u8 mode = vmx_msr_bitmap_mode(vcpu); 3742 u8 changed = mode ^ vmx->msr_bitmap_mode; 3743 3744 if (!changed) 3745 return; 3746 3747 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3748 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3749 3750 vmx->msr_bitmap_mode = mode; 3751 } 3752 3753 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3754 { 3755 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3756 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3757 u32 i; 3758 3759 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3760 MSR_TYPE_RW, flag); 3761 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3762 MSR_TYPE_RW, flag); 3763 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3764 MSR_TYPE_RW, flag); 3765 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3766 MSR_TYPE_RW, flag); 3767 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3768 vmx_set_intercept_for_msr(msr_bitmap, 3769 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3770 vmx_set_intercept_for_msr(msr_bitmap, 3771 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3772 } 3773 } 3774 3775 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3776 { 3777 struct vcpu_vmx *vmx = to_vmx(vcpu); 3778 void *vapic_page; 3779 u32 vppr; 3780 int rvi; 3781 3782 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3783 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3784 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3785 return false; 3786 3787 rvi = vmx_get_rvi(); 3788 3789 vapic_page = vmx->nested.virtual_apic_map.hva; 3790 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3791 3792 return ((rvi & 0xf0) > (vppr & 0xf0)); 3793 } 3794 3795 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3796 bool nested) 3797 { 3798 #ifdef CONFIG_SMP 3799 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3800 3801 if (vcpu->mode == IN_GUEST_MODE) { 3802 /* 3803 * The vector of interrupt to be delivered to vcpu had 3804 * been set in PIR before this function. 3805 * 3806 * Following cases will be reached in this block, and 3807 * we always send a notification event in all cases as 3808 * explained below. 3809 * 3810 * Case 1: vcpu keeps in non-root mode. Sending a 3811 * notification event posts the interrupt to vcpu. 3812 * 3813 * Case 2: vcpu exits to root mode and is still 3814 * runnable. PIR will be synced to vIRR before the 3815 * next vcpu entry. Sending a notification event in 3816 * this case has no effect, as vcpu is not in root 3817 * mode. 3818 * 3819 * Case 3: vcpu exits to root mode and is blocked. 3820 * vcpu_block() has already synced PIR to vIRR and 3821 * never blocks vcpu if vIRR is not cleared. Therefore, 3822 * a blocked vcpu here does not wait for any requested 3823 * interrupts in PIR, and sending a notification event 3824 * which has no effect is safe here. 3825 */ 3826 3827 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3828 return true; 3829 } 3830 #endif 3831 return false; 3832 } 3833 3834 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3835 int vector) 3836 { 3837 struct vcpu_vmx *vmx = to_vmx(vcpu); 3838 3839 if (is_guest_mode(vcpu) && 3840 vector == vmx->nested.posted_intr_nv) { 3841 /* 3842 * If a posted intr is not recognized by hardware, 3843 * we will accomplish it in the next vmentry. 3844 */ 3845 vmx->nested.pi_pending = true; 3846 kvm_make_request(KVM_REQ_EVENT, vcpu); 3847 /* the PIR and ON have been set by L1. */ 3848 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3849 kvm_vcpu_kick(vcpu); 3850 return 0; 3851 } 3852 return -1; 3853 } 3854 /* 3855 * Send interrupt to vcpu via posted interrupt way. 3856 * 1. If target vcpu is running(non-root mode), send posted interrupt 3857 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3858 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3859 * interrupt from PIR in next vmentry. 3860 */ 3861 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3862 { 3863 struct vcpu_vmx *vmx = to_vmx(vcpu); 3864 int r; 3865 3866 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3867 if (!r) 3868 return 0; 3869 3870 if (!vcpu->arch.apicv_active) 3871 return -1; 3872 3873 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3874 return 0; 3875 3876 /* If a previous notification has sent the IPI, nothing to do. */ 3877 if (pi_test_and_set_on(&vmx->pi_desc)) 3878 return 0; 3879 3880 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3881 kvm_vcpu_kick(vcpu); 3882 3883 return 0; 3884 } 3885 3886 /* 3887 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3888 * will not change in the lifetime of the guest. 3889 * Note that host-state that does change is set elsewhere. E.g., host-state 3890 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3891 */ 3892 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3893 { 3894 u32 low32, high32; 3895 unsigned long tmpl; 3896 unsigned long cr0, cr3, cr4; 3897 3898 cr0 = read_cr0(); 3899 WARN_ON(cr0 & X86_CR0_TS); 3900 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3901 3902 /* 3903 * Save the most likely value for this task's CR3 in the VMCS. 3904 * We can't use __get_current_cr3_fast() because we're not atomic. 3905 */ 3906 cr3 = __read_cr3(); 3907 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3908 vmx->loaded_vmcs->host_state.cr3 = cr3; 3909 3910 /* Save the most likely value for this task's CR4 in the VMCS. */ 3911 cr4 = cr4_read_shadow(); 3912 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3913 vmx->loaded_vmcs->host_state.cr4 = cr4; 3914 3915 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3916 #ifdef CONFIG_X86_64 3917 /* 3918 * Load null selectors, so we can avoid reloading them in 3919 * vmx_prepare_switch_to_host(), in case userspace uses 3920 * the null selectors too (the expected case). 3921 */ 3922 vmcs_write16(HOST_DS_SELECTOR, 0); 3923 vmcs_write16(HOST_ES_SELECTOR, 0); 3924 #else 3925 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3926 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3927 #endif 3928 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3929 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3930 3931 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3932 3933 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3934 3935 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3936 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3937 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3938 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3939 3940 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3941 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3942 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3943 } 3944 3945 if (cpu_has_load_ia32_efer()) 3946 vmcs_write64(HOST_IA32_EFER, host_efer); 3947 } 3948 3949 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3950 { 3951 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3952 if (enable_ept) 3953 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3954 if (is_guest_mode(&vmx->vcpu)) 3955 vmx->vcpu.arch.cr4_guest_owned_bits &= 3956 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3957 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3958 } 3959 3960 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3961 { 3962 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3963 3964 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3965 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3966 3967 if (!enable_vnmi) 3968 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3969 3970 if (!enable_preemption_timer) 3971 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3972 3973 return pin_based_exec_ctrl; 3974 } 3975 3976 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3977 { 3978 struct vcpu_vmx *vmx = to_vmx(vcpu); 3979 3980 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3981 if (cpu_has_secondary_exec_ctrls()) { 3982 if (kvm_vcpu_apicv_active(vcpu)) 3983 secondary_exec_controls_setbit(vmx, 3984 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3985 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3986 else 3987 secondary_exec_controls_clearbit(vmx, 3988 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3989 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3990 } 3991 3992 if (cpu_has_vmx_msr_bitmap()) 3993 vmx_update_msr_bitmap(vcpu); 3994 } 3995 3996 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3997 { 3998 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3999 4000 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 4001 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 4002 4003 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 4004 exec_control &= ~CPU_BASED_TPR_SHADOW; 4005 #ifdef CONFIG_X86_64 4006 exec_control |= CPU_BASED_CR8_STORE_EXITING | 4007 CPU_BASED_CR8_LOAD_EXITING; 4008 #endif 4009 } 4010 if (!enable_ept) 4011 exec_control |= CPU_BASED_CR3_STORE_EXITING | 4012 CPU_BASED_CR3_LOAD_EXITING | 4013 CPU_BASED_INVLPG_EXITING; 4014 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 4015 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 4016 CPU_BASED_MONITOR_EXITING); 4017 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 4018 exec_control &= ~CPU_BASED_HLT_EXITING; 4019 return exec_control; 4020 } 4021 4022 4023 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 4024 { 4025 struct kvm_vcpu *vcpu = &vmx->vcpu; 4026 4027 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 4028 4029 if (pt_mode == PT_MODE_SYSTEM) 4030 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 4031 if (!cpu_need_virtualize_apic_accesses(vcpu)) 4032 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4033 if (vmx->vpid == 0) 4034 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4035 if (!enable_ept) { 4036 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4037 enable_unrestricted_guest = 0; 4038 } 4039 if (!enable_unrestricted_guest) 4040 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4041 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4042 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4043 if (!kvm_vcpu_apicv_active(vcpu)) 4044 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4045 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4046 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4047 4048 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4049 * in vmx_set_cr4. */ 4050 exec_control &= ~SECONDARY_EXEC_DESC; 4051 4052 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4053 (handle_vmptrld). 4054 We can NOT enable shadow_vmcs here because we don't have yet 4055 a current VMCS12 4056 */ 4057 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4058 4059 if (!enable_pml) 4060 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4061 4062 if (vmx_xsaves_supported()) { 4063 /* Exposing XSAVES only when XSAVE is exposed */ 4064 bool xsaves_enabled = 4065 boot_cpu_has(X86_FEATURE_XSAVE) && 4066 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4067 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4068 4069 vcpu->arch.xsaves_enabled = xsaves_enabled; 4070 4071 if (!xsaves_enabled) 4072 exec_control &= ~SECONDARY_EXEC_XSAVES; 4073 4074 if (nested) { 4075 if (xsaves_enabled) 4076 vmx->nested.msrs.secondary_ctls_high |= 4077 SECONDARY_EXEC_XSAVES; 4078 else 4079 vmx->nested.msrs.secondary_ctls_high &= 4080 ~SECONDARY_EXEC_XSAVES; 4081 } 4082 } 4083 4084 if (vmx_rdtscp_supported()) { 4085 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4086 if (!rdtscp_enabled) 4087 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4088 4089 if (nested) { 4090 if (rdtscp_enabled) 4091 vmx->nested.msrs.secondary_ctls_high |= 4092 SECONDARY_EXEC_RDTSCP; 4093 else 4094 vmx->nested.msrs.secondary_ctls_high &= 4095 ~SECONDARY_EXEC_RDTSCP; 4096 } 4097 } 4098 4099 if (vmx_invpcid_supported()) { 4100 /* Exposing INVPCID only when PCID is exposed */ 4101 bool invpcid_enabled = 4102 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4103 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4104 4105 if (!invpcid_enabled) { 4106 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4107 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4108 } 4109 4110 if (nested) { 4111 if (invpcid_enabled) 4112 vmx->nested.msrs.secondary_ctls_high |= 4113 SECONDARY_EXEC_ENABLE_INVPCID; 4114 else 4115 vmx->nested.msrs.secondary_ctls_high &= 4116 ~SECONDARY_EXEC_ENABLE_INVPCID; 4117 } 4118 } 4119 4120 if (vmx_rdrand_supported()) { 4121 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4122 if (rdrand_enabled) 4123 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4124 4125 if (nested) { 4126 if (rdrand_enabled) 4127 vmx->nested.msrs.secondary_ctls_high |= 4128 SECONDARY_EXEC_RDRAND_EXITING; 4129 else 4130 vmx->nested.msrs.secondary_ctls_high &= 4131 ~SECONDARY_EXEC_RDRAND_EXITING; 4132 } 4133 } 4134 4135 if (vmx_rdseed_supported()) { 4136 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4137 if (rdseed_enabled) 4138 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4139 4140 if (nested) { 4141 if (rdseed_enabled) 4142 vmx->nested.msrs.secondary_ctls_high |= 4143 SECONDARY_EXEC_RDSEED_EXITING; 4144 else 4145 vmx->nested.msrs.secondary_ctls_high &= 4146 ~SECONDARY_EXEC_RDSEED_EXITING; 4147 } 4148 } 4149 4150 if (vmx_waitpkg_supported()) { 4151 bool waitpkg_enabled = 4152 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4153 4154 if (!waitpkg_enabled) 4155 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4156 4157 if (nested) { 4158 if (waitpkg_enabled) 4159 vmx->nested.msrs.secondary_ctls_high |= 4160 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4161 else 4162 vmx->nested.msrs.secondary_ctls_high &= 4163 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4164 } 4165 } 4166 4167 vmx->secondary_exec_control = exec_control; 4168 } 4169 4170 static void ept_set_mmio_spte_mask(void) 4171 { 4172 /* 4173 * EPT Misconfigurations can be generated if the value of bits 2:0 4174 * of an EPT paging-structure entry is 110b (write/execute). 4175 */ 4176 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4177 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4178 } 4179 4180 #define VMX_XSS_EXIT_BITMAP 0 4181 4182 /* 4183 * Noting that the initialization of Guest-state Area of VMCS is in 4184 * vmx_vcpu_reset(). 4185 */ 4186 static void init_vmcs(struct vcpu_vmx *vmx) 4187 { 4188 if (nested) 4189 nested_vmx_set_vmcs_shadowing_bitmap(); 4190 4191 if (cpu_has_vmx_msr_bitmap()) 4192 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4193 4194 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4195 4196 /* Control */ 4197 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4198 4199 exec_controls_set(vmx, vmx_exec_control(vmx)); 4200 4201 if (cpu_has_secondary_exec_ctrls()) { 4202 vmx_compute_secondary_exec_control(vmx); 4203 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4204 } 4205 4206 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4207 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4208 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4209 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4210 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4211 4212 vmcs_write16(GUEST_INTR_STATUS, 0); 4213 4214 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4215 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4216 } 4217 4218 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4219 vmcs_write32(PLE_GAP, ple_gap); 4220 vmx->ple_window = ple_window; 4221 vmx->ple_window_dirty = true; 4222 } 4223 4224 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4225 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4226 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4227 4228 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4229 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4230 vmx_set_constant_host_state(vmx); 4231 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4232 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4233 4234 if (cpu_has_vmx_vmfunc()) 4235 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4236 4237 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4238 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4239 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4240 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4241 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4242 4243 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4244 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4245 4246 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4247 4248 /* 22.2.1, 20.8.1 */ 4249 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4250 4251 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4252 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4253 4254 set_cr4_guest_host_mask(vmx); 4255 4256 if (vmx->vpid != 0) 4257 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4258 4259 if (vmx_xsaves_supported()) 4260 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4261 4262 if (enable_pml) { 4263 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4264 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4265 } 4266 4267 if (cpu_has_vmx_encls_vmexit()) 4268 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4269 4270 if (pt_mode == PT_MODE_HOST_GUEST) { 4271 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4272 /* Bit[6~0] are forced to 1, writes are ignored. */ 4273 vmx->pt_desc.guest.output_mask = 0x7F; 4274 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4275 } 4276 } 4277 4278 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4279 { 4280 struct vcpu_vmx *vmx = to_vmx(vcpu); 4281 struct msr_data apic_base_msr; 4282 u64 cr0; 4283 4284 vmx->rmode.vm86_active = 0; 4285 vmx->spec_ctrl = 0; 4286 4287 vmx->msr_ia32_umwait_control = 0; 4288 4289 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4290 vmx->hv_deadline_tsc = -1; 4291 kvm_set_cr8(vcpu, 0); 4292 4293 if (!init_event) { 4294 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4295 MSR_IA32_APICBASE_ENABLE; 4296 if (kvm_vcpu_is_reset_bsp(vcpu)) 4297 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4298 apic_base_msr.host_initiated = true; 4299 kvm_set_apic_base(vcpu, &apic_base_msr); 4300 } 4301 4302 vmx_segment_cache_clear(vmx); 4303 4304 seg_setup(VCPU_SREG_CS); 4305 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4306 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4307 4308 seg_setup(VCPU_SREG_DS); 4309 seg_setup(VCPU_SREG_ES); 4310 seg_setup(VCPU_SREG_FS); 4311 seg_setup(VCPU_SREG_GS); 4312 seg_setup(VCPU_SREG_SS); 4313 4314 vmcs_write16(GUEST_TR_SELECTOR, 0); 4315 vmcs_writel(GUEST_TR_BASE, 0); 4316 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4317 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4318 4319 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4320 vmcs_writel(GUEST_LDTR_BASE, 0); 4321 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4322 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4323 4324 if (!init_event) { 4325 vmcs_write32(GUEST_SYSENTER_CS, 0); 4326 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4327 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4328 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4329 } 4330 4331 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4332 kvm_rip_write(vcpu, 0xfff0); 4333 4334 vmcs_writel(GUEST_GDTR_BASE, 0); 4335 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4336 4337 vmcs_writel(GUEST_IDTR_BASE, 0); 4338 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4339 4340 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4341 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4342 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4343 if (kvm_mpx_supported()) 4344 vmcs_write64(GUEST_BNDCFGS, 0); 4345 4346 setup_msrs(vmx); 4347 4348 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4349 4350 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4351 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4352 if (cpu_need_tpr_shadow(vcpu)) 4353 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4354 __pa(vcpu->arch.apic->regs)); 4355 vmcs_write32(TPR_THRESHOLD, 0); 4356 } 4357 4358 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4359 4360 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4361 vmx->vcpu.arch.cr0 = cr0; 4362 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4363 vmx_set_cr4(vcpu, 0); 4364 vmx_set_efer(vcpu, 0); 4365 4366 update_exception_bitmap(vcpu); 4367 4368 vpid_sync_context(vmx->vpid); 4369 if (init_event) 4370 vmx_clear_hlt(vcpu); 4371 } 4372 4373 static void enable_irq_window(struct kvm_vcpu *vcpu) 4374 { 4375 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4376 } 4377 4378 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4379 { 4380 if (!enable_vnmi || 4381 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4382 enable_irq_window(vcpu); 4383 return; 4384 } 4385 4386 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4387 } 4388 4389 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4390 { 4391 struct vcpu_vmx *vmx = to_vmx(vcpu); 4392 uint32_t intr; 4393 int irq = vcpu->arch.interrupt.nr; 4394 4395 trace_kvm_inj_virq(irq); 4396 4397 ++vcpu->stat.irq_injections; 4398 if (vmx->rmode.vm86_active) { 4399 int inc_eip = 0; 4400 if (vcpu->arch.interrupt.soft) 4401 inc_eip = vcpu->arch.event_exit_inst_len; 4402 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4403 return; 4404 } 4405 intr = irq | INTR_INFO_VALID_MASK; 4406 if (vcpu->arch.interrupt.soft) { 4407 intr |= INTR_TYPE_SOFT_INTR; 4408 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4409 vmx->vcpu.arch.event_exit_inst_len); 4410 } else 4411 intr |= INTR_TYPE_EXT_INTR; 4412 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4413 4414 vmx_clear_hlt(vcpu); 4415 } 4416 4417 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4418 { 4419 struct vcpu_vmx *vmx = to_vmx(vcpu); 4420 4421 if (!enable_vnmi) { 4422 /* 4423 * Tracking the NMI-blocked state in software is built upon 4424 * finding the next open IRQ window. This, in turn, depends on 4425 * well-behaving guests: They have to keep IRQs disabled at 4426 * least as long as the NMI handler runs. Otherwise we may 4427 * cause NMI nesting, maybe breaking the guest. But as this is 4428 * highly unlikely, we can live with the residual risk. 4429 */ 4430 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4431 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4432 } 4433 4434 ++vcpu->stat.nmi_injections; 4435 vmx->loaded_vmcs->nmi_known_unmasked = false; 4436 4437 if (vmx->rmode.vm86_active) { 4438 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4439 return; 4440 } 4441 4442 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4443 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4444 4445 vmx_clear_hlt(vcpu); 4446 } 4447 4448 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4449 { 4450 struct vcpu_vmx *vmx = to_vmx(vcpu); 4451 bool masked; 4452 4453 if (!enable_vnmi) 4454 return vmx->loaded_vmcs->soft_vnmi_blocked; 4455 if (vmx->loaded_vmcs->nmi_known_unmasked) 4456 return false; 4457 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4458 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4459 return masked; 4460 } 4461 4462 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4463 { 4464 struct vcpu_vmx *vmx = to_vmx(vcpu); 4465 4466 if (!enable_vnmi) { 4467 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4468 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4469 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4470 } 4471 } else { 4472 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4473 if (masked) 4474 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4475 GUEST_INTR_STATE_NMI); 4476 else 4477 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4478 GUEST_INTR_STATE_NMI); 4479 } 4480 } 4481 4482 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4483 { 4484 if (to_vmx(vcpu)->nested.nested_run_pending) 4485 return 0; 4486 4487 if (!enable_vnmi && 4488 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4489 return 0; 4490 4491 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4492 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4493 | GUEST_INTR_STATE_NMI)); 4494 } 4495 4496 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4497 { 4498 return (!to_vmx(vcpu)->nested.nested_run_pending && 4499 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4500 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4501 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4502 } 4503 4504 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4505 { 4506 int ret; 4507 4508 if (enable_unrestricted_guest) 4509 return 0; 4510 4511 mutex_lock(&kvm->slots_lock); 4512 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4513 PAGE_SIZE * 3); 4514 mutex_unlock(&kvm->slots_lock); 4515 4516 if (ret) 4517 return ret; 4518 to_kvm_vmx(kvm)->tss_addr = addr; 4519 return init_rmode_tss(kvm); 4520 } 4521 4522 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4523 { 4524 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4525 return 0; 4526 } 4527 4528 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4529 { 4530 switch (vec) { 4531 case BP_VECTOR: 4532 /* 4533 * Update instruction length as we may reinject the exception 4534 * from user space while in guest debugging mode. 4535 */ 4536 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4537 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4538 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4539 return false; 4540 /* fall through */ 4541 case DB_VECTOR: 4542 if (vcpu->guest_debug & 4543 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4544 return false; 4545 /* fall through */ 4546 case DE_VECTOR: 4547 case OF_VECTOR: 4548 case BR_VECTOR: 4549 case UD_VECTOR: 4550 case DF_VECTOR: 4551 case SS_VECTOR: 4552 case GP_VECTOR: 4553 case MF_VECTOR: 4554 return true; 4555 break; 4556 } 4557 return false; 4558 } 4559 4560 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4561 int vec, u32 err_code) 4562 { 4563 /* 4564 * Instruction with address size override prefix opcode 0x67 4565 * Cause the #SS fault with 0 error code in VM86 mode. 4566 */ 4567 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4568 if (kvm_emulate_instruction(vcpu, 0)) { 4569 if (vcpu->arch.halt_request) { 4570 vcpu->arch.halt_request = 0; 4571 return kvm_vcpu_halt(vcpu); 4572 } 4573 return 1; 4574 } 4575 return 0; 4576 } 4577 4578 /* 4579 * Forward all other exceptions that are valid in real mode. 4580 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4581 * the required debugging infrastructure rework. 4582 */ 4583 kvm_queue_exception(vcpu, vec); 4584 return 1; 4585 } 4586 4587 /* 4588 * Trigger machine check on the host. We assume all the MSRs are already set up 4589 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4590 * We pass a fake environment to the machine check handler because we want 4591 * the guest to be always treated like user space, no matter what context 4592 * it used internally. 4593 */ 4594 static void kvm_machine_check(void) 4595 { 4596 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4597 struct pt_regs regs = { 4598 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4599 .flags = X86_EFLAGS_IF, 4600 }; 4601 4602 do_machine_check(®s, 0); 4603 #endif 4604 } 4605 4606 static int handle_machine_check(struct kvm_vcpu *vcpu) 4607 { 4608 /* handled by vmx_vcpu_run() */ 4609 return 1; 4610 } 4611 4612 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4613 { 4614 struct vcpu_vmx *vmx = to_vmx(vcpu); 4615 struct kvm_run *kvm_run = vcpu->run; 4616 u32 intr_info, ex_no, error_code; 4617 unsigned long cr2, rip, dr6; 4618 u32 vect_info; 4619 4620 vect_info = vmx->idt_vectoring_info; 4621 intr_info = vmx->exit_intr_info; 4622 4623 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4624 return 1; /* handled by handle_exception_nmi_irqoff() */ 4625 4626 if (is_invalid_opcode(intr_info)) 4627 return handle_ud(vcpu); 4628 4629 error_code = 0; 4630 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4631 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4632 4633 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4634 WARN_ON_ONCE(!enable_vmware_backdoor); 4635 4636 /* 4637 * VMware backdoor emulation on #GP interception only handles 4638 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4639 * error code on #GP. 4640 */ 4641 if (error_code) { 4642 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4643 return 1; 4644 } 4645 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4646 } 4647 4648 /* 4649 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4650 * MMIO, it is better to report an internal error. 4651 * See the comments in vmx_handle_exit. 4652 */ 4653 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4654 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4655 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4656 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4657 vcpu->run->internal.ndata = 3; 4658 vcpu->run->internal.data[0] = vect_info; 4659 vcpu->run->internal.data[1] = intr_info; 4660 vcpu->run->internal.data[2] = error_code; 4661 return 0; 4662 } 4663 4664 if (is_page_fault(intr_info)) { 4665 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4666 /* EPT won't cause page fault directly */ 4667 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4668 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4669 } 4670 4671 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4672 4673 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4674 return handle_rmode_exception(vcpu, ex_no, error_code); 4675 4676 switch (ex_no) { 4677 case AC_VECTOR: 4678 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4679 return 1; 4680 case DB_VECTOR: 4681 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4682 if (!(vcpu->guest_debug & 4683 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4684 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4685 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4686 if (is_icebp(intr_info)) 4687 WARN_ON(!skip_emulated_instruction(vcpu)); 4688 4689 kvm_queue_exception(vcpu, DB_VECTOR); 4690 return 1; 4691 } 4692 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4693 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4694 /* fall through */ 4695 case BP_VECTOR: 4696 /* 4697 * Update instruction length as we may reinject #BP from 4698 * user space while in guest debugging mode. Reading it for 4699 * #DB as well causes no harm, it is not used in that case. 4700 */ 4701 vmx->vcpu.arch.event_exit_inst_len = 4702 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4703 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4704 rip = kvm_rip_read(vcpu); 4705 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4706 kvm_run->debug.arch.exception = ex_no; 4707 break; 4708 default: 4709 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4710 kvm_run->ex.exception = ex_no; 4711 kvm_run->ex.error_code = error_code; 4712 break; 4713 } 4714 return 0; 4715 } 4716 4717 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4718 { 4719 ++vcpu->stat.irq_exits; 4720 return 1; 4721 } 4722 4723 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4724 { 4725 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4726 vcpu->mmio_needed = 0; 4727 return 0; 4728 } 4729 4730 static int handle_io(struct kvm_vcpu *vcpu) 4731 { 4732 unsigned long exit_qualification; 4733 int size, in, string; 4734 unsigned port; 4735 4736 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4737 string = (exit_qualification & 16) != 0; 4738 4739 ++vcpu->stat.io_exits; 4740 4741 if (string) 4742 return kvm_emulate_instruction(vcpu, 0); 4743 4744 port = exit_qualification >> 16; 4745 size = (exit_qualification & 7) + 1; 4746 in = (exit_qualification & 8) != 0; 4747 4748 return kvm_fast_pio(vcpu, size, port, in); 4749 } 4750 4751 static void 4752 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4753 { 4754 /* 4755 * Patch in the VMCALL instruction: 4756 */ 4757 hypercall[0] = 0x0f; 4758 hypercall[1] = 0x01; 4759 hypercall[2] = 0xc1; 4760 } 4761 4762 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4763 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4764 { 4765 if (is_guest_mode(vcpu)) { 4766 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4767 unsigned long orig_val = val; 4768 4769 /* 4770 * We get here when L2 changed cr0 in a way that did not change 4771 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4772 * but did change L0 shadowed bits. So we first calculate the 4773 * effective cr0 value that L1 would like to write into the 4774 * hardware. It consists of the L2-owned bits from the new 4775 * value combined with the L1-owned bits from L1's guest_cr0. 4776 */ 4777 val = (val & ~vmcs12->cr0_guest_host_mask) | 4778 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4779 4780 if (!nested_guest_cr0_valid(vcpu, val)) 4781 return 1; 4782 4783 if (kvm_set_cr0(vcpu, val)) 4784 return 1; 4785 vmcs_writel(CR0_READ_SHADOW, orig_val); 4786 return 0; 4787 } else { 4788 if (to_vmx(vcpu)->nested.vmxon && 4789 !nested_host_cr0_valid(vcpu, val)) 4790 return 1; 4791 4792 return kvm_set_cr0(vcpu, val); 4793 } 4794 } 4795 4796 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4797 { 4798 if (is_guest_mode(vcpu)) { 4799 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4800 unsigned long orig_val = val; 4801 4802 /* analogously to handle_set_cr0 */ 4803 val = (val & ~vmcs12->cr4_guest_host_mask) | 4804 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4805 if (kvm_set_cr4(vcpu, val)) 4806 return 1; 4807 vmcs_writel(CR4_READ_SHADOW, orig_val); 4808 return 0; 4809 } else 4810 return kvm_set_cr4(vcpu, val); 4811 } 4812 4813 static int handle_desc(struct kvm_vcpu *vcpu) 4814 { 4815 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4816 return kvm_emulate_instruction(vcpu, 0); 4817 } 4818 4819 static int handle_cr(struct kvm_vcpu *vcpu) 4820 { 4821 unsigned long exit_qualification, val; 4822 int cr; 4823 int reg; 4824 int err; 4825 int ret; 4826 4827 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4828 cr = exit_qualification & 15; 4829 reg = (exit_qualification >> 8) & 15; 4830 switch ((exit_qualification >> 4) & 3) { 4831 case 0: /* mov to cr */ 4832 val = kvm_register_readl(vcpu, reg); 4833 trace_kvm_cr_write(cr, val); 4834 switch (cr) { 4835 case 0: 4836 err = handle_set_cr0(vcpu, val); 4837 return kvm_complete_insn_gp(vcpu, err); 4838 case 3: 4839 WARN_ON_ONCE(enable_unrestricted_guest); 4840 err = kvm_set_cr3(vcpu, val); 4841 return kvm_complete_insn_gp(vcpu, err); 4842 case 4: 4843 err = handle_set_cr4(vcpu, val); 4844 return kvm_complete_insn_gp(vcpu, err); 4845 case 8: { 4846 u8 cr8_prev = kvm_get_cr8(vcpu); 4847 u8 cr8 = (u8)val; 4848 err = kvm_set_cr8(vcpu, cr8); 4849 ret = kvm_complete_insn_gp(vcpu, err); 4850 if (lapic_in_kernel(vcpu)) 4851 return ret; 4852 if (cr8_prev <= cr8) 4853 return ret; 4854 /* 4855 * TODO: we might be squashing a 4856 * KVM_GUESTDBG_SINGLESTEP-triggered 4857 * KVM_EXIT_DEBUG here. 4858 */ 4859 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4860 return 0; 4861 } 4862 } 4863 break; 4864 case 2: /* clts */ 4865 WARN_ONCE(1, "Guest should always own CR0.TS"); 4866 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4867 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4868 return kvm_skip_emulated_instruction(vcpu); 4869 case 1: /*mov from cr*/ 4870 switch (cr) { 4871 case 3: 4872 WARN_ON_ONCE(enable_unrestricted_guest); 4873 val = kvm_read_cr3(vcpu); 4874 kvm_register_write(vcpu, reg, val); 4875 trace_kvm_cr_read(cr, val); 4876 return kvm_skip_emulated_instruction(vcpu); 4877 case 8: 4878 val = kvm_get_cr8(vcpu); 4879 kvm_register_write(vcpu, reg, val); 4880 trace_kvm_cr_read(cr, val); 4881 return kvm_skip_emulated_instruction(vcpu); 4882 } 4883 break; 4884 case 3: /* lmsw */ 4885 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4886 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4887 kvm_lmsw(vcpu, val); 4888 4889 return kvm_skip_emulated_instruction(vcpu); 4890 default: 4891 break; 4892 } 4893 vcpu->run->exit_reason = 0; 4894 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4895 (int)(exit_qualification >> 4) & 3, cr); 4896 return 0; 4897 } 4898 4899 static int handle_dr(struct kvm_vcpu *vcpu) 4900 { 4901 unsigned long exit_qualification; 4902 int dr, dr7, reg; 4903 4904 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4905 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4906 4907 /* First, if DR does not exist, trigger UD */ 4908 if (!kvm_require_dr(vcpu, dr)) 4909 return 1; 4910 4911 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4912 if (!kvm_require_cpl(vcpu, 0)) 4913 return 1; 4914 dr7 = vmcs_readl(GUEST_DR7); 4915 if (dr7 & DR7_GD) { 4916 /* 4917 * As the vm-exit takes precedence over the debug trap, we 4918 * need to emulate the latter, either for the host or the 4919 * guest debugging itself. 4920 */ 4921 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4922 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4923 vcpu->run->debug.arch.dr7 = dr7; 4924 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4925 vcpu->run->debug.arch.exception = DB_VECTOR; 4926 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4927 return 0; 4928 } else { 4929 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4930 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4931 kvm_queue_exception(vcpu, DB_VECTOR); 4932 return 1; 4933 } 4934 } 4935 4936 if (vcpu->guest_debug == 0) { 4937 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4938 4939 /* 4940 * No more DR vmexits; force a reload of the debug registers 4941 * and reenter on this instruction. The next vmexit will 4942 * retrieve the full state of the debug registers. 4943 */ 4944 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4945 return 1; 4946 } 4947 4948 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4949 if (exit_qualification & TYPE_MOV_FROM_DR) { 4950 unsigned long val; 4951 4952 if (kvm_get_dr(vcpu, dr, &val)) 4953 return 1; 4954 kvm_register_write(vcpu, reg, val); 4955 } else 4956 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4957 return 1; 4958 4959 return kvm_skip_emulated_instruction(vcpu); 4960 } 4961 4962 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4963 { 4964 return vcpu->arch.dr6; 4965 } 4966 4967 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4968 { 4969 } 4970 4971 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4972 { 4973 get_debugreg(vcpu->arch.db[0], 0); 4974 get_debugreg(vcpu->arch.db[1], 1); 4975 get_debugreg(vcpu->arch.db[2], 2); 4976 get_debugreg(vcpu->arch.db[3], 3); 4977 get_debugreg(vcpu->arch.dr6, 6); 4978 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4979 4980 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4981 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4982 } 4983 4984 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4985 { 4986 vmcs_writel(GUEST_DR7, val); 4987 } 4988 4989 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4990 { 4991 kvm_apic_update_ppr(vcpu); 4992 return 1; 4993 } 4994 4995 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4996 { 4997 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4998 4999 kvm_make_request(KVM_REQ_EVENT, vcpu); 5000 5001 ++vcpu->stat.irq_window_exits; 5002 return 1; 5003 } 5004 5005 static int handle_vmcall(struct kvm_vcpu *vcpu) 5006 { 5007 return kvm_emulate_hypercall(vcpu); 5008 } 5009 5010 static int handle_invd(struct kvm_vcpu *vcpu) 5011 { 5012 return kvm_emulate_instruction(vcpu, 0); 5013 } 5014 5015 static int handle_invlpg(struct kvm_vcpu *vcpu) 5016 { 5017 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5018 5019 kvm_mmu_invlpg(vcpu, exit_qualification); 5020 return kvm_skip_emulated_instruction(vcpu); 5021 } 5022 5023 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5024 { 5025 int err; 5026 5027 err = kvm_rdpmc(vcpu); 5028 return kvm_complete_insn_gp(vcpu, err); 5029 } 5030 5031 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5032 { 5033 return kvm_emulate_wbinvd(vcpu); 5034 } 5035 5036 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5037 { 5038 u64 new_bv = kvm_read_edx_eax(vcpu); 5039 u32 index = kvm_rcx_read(vcpu); 5040 5041 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5042 return kvm_skip_emulated_instruction(vcpu); 5043 return 1; 5044 } 5045 5046 static int handle_apic_access(struct kvm_vcpu *vcpu) 5047 { 5048 if (likely(fasteoi)) { 5049 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5050 int access_type, offset; 5051 5052 access_type = exit_qualification & APIC_ACCESS_TYPE; 5053 offset = exit_qualification & APIC_ACCESS_OFFSET; 5054 /* 5055 * Sane guest uses MOV to write EOI, with written value 5056 * not cared. So make a short-circuit here by avoiding 5057 * heavy instruction emulation. 5058 */ 5059 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5060 (offset == APIC_EOI)) { 5061 kvm_lapic_set_eoi(vcpu); 5062 return kvm_skip_emulated_instruction(vcpu); 5063 } 5064 } 5065 return kvm_emulate_instruction(vcpu, 0); 5066 } 5067 5068 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5069 { 5070 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5071 int vector = exit_qualification & 0xff; 5072 5073 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5074 kvm_apic_set_eoi_accelerated(vcpu, vector); 5075 return 1; 5076 } 5077 5078 static int handle_apic_write(struct kvm_vcpu *vcpu) 5079 { 5080 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5081 u32 offset = exit_qualification & 0xfff; 5082 5083 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5084 kvm_apic_write_nodecode(vcpu, offset); 5085 return 1; 5086 } 5087 5088 static int handle_task_switch(struct kvm_vcpu *vcpu) 5089 { 5090 struct vcpu_vmx *vmx = to_vmx(vcpu); 5091 unsigned long exit_qualification; 5092 bool has_error_code = false; 5093 u32 error_code = 0; 5094 u16 tss_selector; 5095 int reason, type, idt_v, idt_index; 5096 5097 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5098 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5099 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5100 5101 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5102 5103 reason = (u32)exit_qualification >> 30; 5104 if (reason == TASK_SWITCH_GATE && idt_v) { 5105 switch (type) { 5106 case INTR_TYPE_NMI_INTR: 5107 vcpu->arch.nmi_injected = false; 5108 vmx_set_nmi_mask(vcpu, true); 5109 break; 5110 case INTR_TYPE_EXT_INTR: 5111 case INTR_TYPE_SOFT_INTR: 5112 kvm_clear_interrupt_queue(vcpu); 5113 break; 5114 case INTR_TYPE_HARD_EXCEPTION: 5115 if (vmx->idt_vectoring_info & 5116 VECTORING_INFO_DELIVER_CODE_MASK) { 5117 has_error_code = true; 5118 error_code = 5119 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5120 } 5121 /* fall through */ 5122 case INTR_TYPE_SOFT_EXCEPTION: 5123 kvm_clear_exception_queue(vcpu); 5124 break; 5125 default: 5126 break; 5127 } 5128 } 5129 tss_selector = exit_qualification; 5130 5131 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5132 type != INTR_TYPE_EXT_INTR && 5133 type != INTR_TYPE_NMI_INTR)) 5134 WARN_ON(!skip_emulated_instruction(vcpu)); 5135 5136 /* 5137 * TODO: What about debug traps on tss switch? 5138 * Are we supposed to inject them and update dr6? 5139 */ 5140 return kvm_task_switch(vcpu, tss_selector, 5141 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5142 reason, has_error_code, error_code); 5143 } 5144 5145 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5146 { 5147 unsigned long exit_qualification; 5148 gpa_t gpa; 5149 u64 error_code; 5150 5151 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5152 5153 /* 5154 * EPT violation happened while executing iret from NMI, 5155 * "blocked by NMI" bit has to be set before next VM entry. 5156 * There are errata that may cause this bit to not be set: 5157 * AAK134, BY25. 5158 */ 5159 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5160 enable_vnmi && 5161 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5162 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5163 5164 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5165 trace_kvm_page_fault(gpa, exit_qualification); 5166 5167 /* Is it a read fault? */ 5168 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5169 ? PFERR_USER_MASK : 0; 5170 /* Is it a write fault? */ 5171 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5172 ? PFERR_WRITE_MASK : 0; 5173 /* Is it a fetch fault? */ 5174 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5175 ? PFERR_FETCH_MASK : 0; 5176 /* ept page table entry is present? */ 5177 error_code |= (exit_qualification & 5178 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5179 EPT_VIOLATION_EXECUTABLE)) 5180 ? PFERR_PRESENT_MASK : 0; 5181 5182 error_code |= (exit_qualification & 0x100) != 0 ? 5183 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5184 5185 vcpu->arch.exit_qualification = exit_qualification; 5186 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5187 } 5188 5189 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5190 { 5191 gpa_t gpa; 5192 5193 /* 5194 * A nested guest cannot optimize MMIO vmexits, because we have an 5195 * nGPA here instead of the required GPA. 5196 */ 5197 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5198 if (!is_guest_mode(vcpu) && 5199 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5200 trace_kvm_fast_mmio(gpa); 5201 return kvm_skip_emulated_instruction(vcpu); 5202 } 5203 5204 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5205 } 5206 5207 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5208 { 5209 WARN_ON_ONCE(!enable_vnmi); 5210 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5211 ++vcpu->stat.nmi_window_exits; 5212 kvm_make_request(KVM_REQ_EVENT, vcpu); 5213 5214 return 1; 5215 } 5216 5217 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5218 { 5219 struct vcpu_vmx *vmx = to_vmx(vcpu); 5220 bool intr_window_requested; 5221 unsigned count = 130; 5222 5223 /* 5224 * We should never reach the point where we are emulating L2 5225 * due to invalid guest state as that means we incorrectly 5226 * allowed a nested VMEntry with an invalid vmcs12. 5227 */ 5228 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5229 5230 intr_window_requested = exec_controls_get(vmx) & 5231 CPU_BASED_INTR_WINDOW_EXITING; 5232 5233 while (vmx->emulation_required && count-- != 0) { 5234 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5235 return handle_interrupt_window(&vmx->vcpu); 5236 5237 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5238 return 1; 5239 5240 if (!kvm_emulate_instruction(vcpu, 0)) 5241 return 0; 5242 5243 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5244 vcpu->arch.exception.pending) { 5245 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5246 vcpu->run->internal.suberror = 5247 KVM_INTERNAL_ERROR_EMULATION; 5248 vcpu->run->internal.ndata = 0; 5249 return 0; 5250 } 5251 5252 if (vcpu->arch.halt_request) { 5253 vcpu->arch.halt_request = 0; 5254 return kvm_vcpu_halt(vcpu); 5255 } 5256 5257 /* 5258 * Note, return 1 and not 0, vcpu_run() is responsible for 5259 * morphing the pending signal into the proper return code. 5260 */ 5261 if (signal_pending(current)) 5262 return 1; 5263 5264 if (need_resched()) 5265 schedule(); 5266 } 5267 5268 return 1; 5269 } 5270 5271 static void grow_ple_window(struct kvm_vcpu *vcpu) 5272 { 5273 struct vcpu_vmx *vmx = to_vmx(vcpu); 5274 unsigned int old = vmx->ple_window; 5275 5276 vmx->ple_window = __grow_ple_window(old, ple_window, 5277 ple_window_grow, 5278 ple_window_max); 5279 5280 if (vmx->ple_window != old) { 5281 vmx->ple_window_dirty = true; 5282 trace_kvm_ple_window_update(vcpu->vcpu_id, 5283 vmx->ple_window, old); 5284 } 5285 } 5286 5287 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5288 { 5289 struct vcpu_vmx *vmx = to_vmx(vcpu); 5290 unsigned int old = vmx->ple_window; 5291 5292 vmx->ple_window = __shrink_ple_window(old, ple_window, 5293 ple_window_shrink, 5294 ple_window); 5295 5296 if (vmx->ple_window != old) { 5297 vmx->ple_window_dirty = true; 5298 trace_kvm_ple_window_update(vcpu->vcpu_id, 5299 vmx->ple_window, old); 5300 } 5301 } 5302 5303 /* 5304 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5305 */ 5306 static void wakeup_handler(void) 5307 { 5308 struct kvm_vcpu *vcpu; 5309 int cpu = smp_processor_id(); 5310 5311 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5312 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5313 blocked_vcpu_list) { 5314 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5315 5316 if (pi_test_on(pi_desc) == 1) 5317 kvm_vcpu_kick(vcpu); 5318 } 5319 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5320 } 5321 5322 static void vmx_enable_tdp(void) 5323 { 5324 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5325 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5326 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5327 0ull, VMX_EPT_EXECUTABLE_MASK, 5328 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5329 VMX_EPT_RWX_MASK, 0ull); 5330 5331 ept_set_mmio_spte_mask(); 5332 kvm_enable_tdp(); 5333 } 5334 5335 /* 5336 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5337 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5338 */ 5339 static int handle_pause(struct kvm_vcpu *vcpu) 5340 { 5341 if (!kvm_pause_in_guest(vcpu->kvm)) 5342 grow_ple_window(vcpu); 5343 5344 /* 5345 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5346 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5347 * never set PAUSE_EXITING and just set PLE if supported, 5348 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5349 */ 5350 kvm_vcpu_on_spin(vcpu, true); 5351 return kvm_skip_emulated_instruction(vcpu); 5352 } 5353 5354 static int handle_nop(struct kvm_vcpu *vcpu) 5355 { 5356 return kvm_skip_emulated_instruction(vcpu); 5357 } 5358 5359 static int handle_mwait(struct kvm_vcpu *vcpu) 5360 { 5361 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5362 return handle_nop(vcpu); 5363 } 5364 5365 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5366 { 5367 kvm_queue_exception(vcpu, UD_VECTOR); 5368 return 1; 5369 } 5370 5371 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5372 { 5373 return 1; 5374 } 5375 5376 static int handle_monitor(struct kvm_vcpu *vcpu) 5377 { 5378 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5379 return handle_nop(vcpu); 5380 } 5381 5382 static int handle_invpcid(struct kvm_vcpu *vcpu) 5383 { 5384 u32 vmx_instruction_info; 5385 unsigned long type; 5386 bool pcid_enabled; 5387 gva_t gva; 5388 struct x86_exception e; 5389 unsigned i; 5390 unsigned long roots_to_free = 0; 5391 struct { 5392 u64 pcid; 5393 u64 gla; 5394 } operand; 5395 5396 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5397 kvm_queue_exception(vcpu, UD_VECTOR); 5398 return 1; 5399 } 5400 5401 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5402 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5403 5404 if (type > 3) { 5405 kvm_inject_gp(vcpu, 0); 5406 return 1; 5407 } 5408 5409 /* According to the Intel instruction reference, the memory operand 5410 * is read even if it isn't needed (e.g., for type==all) 5411 */ 5412 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5413 vmx_instruction_info, false, 5414 sizeof(operand), &gva)) 5415 return 1; 5416 5417 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5418 kvm_inject_page_fault(vcpu, &e); 5419 return 1; 5420 } 5421 5422 if (operand.pcid >> 12 != 0) { 5423 kvm_inject_gp(vcpu, 0); 5424 return 1; 5425 } 5426 5427 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5428 5429 switch (type) { 5430 case INVPCID_TYPE_INDIV_ADDR: 5431 if ((!pcid_enabled && (operand.pcid != 0)) || 5432 is_noncanonical_address(operand.gla, vcpu)) { 5433 kvm_inject_gp(vcpu, 0); 5434 return 1; 5435 } 5436 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5437 return kvm_skip_emulated_instruction(vcpu); 5438 5439 case INVPCID_TYPE_SINGLE_CTXT: 5440 if (!pcid_enabled && (operand.pcid != 0)) { 5441 kvm_inject_gp(vcpu, 0); 5442 return 1; 5443 } 5444 5445 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5446 kvm_mmu_sync_roots(vcpu); 5447 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5448 } 5449 5450 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5451 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5452 == operand.pcid) 5453 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5454 5455 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5456 /* 5457 * If neither the current cr3 nor any of the prev_roots use the 5458 * given PCID, then nothing needs to be done here because a 5459 * resync will happen anyway before switching to any other CR3. 5460 */ 5461 5462 return kvm_skip_emulated_instruction(vcpu); 5463 5464 case INVPCID_TYPE_ALL_NON_GLOBAL: 5465 /* 5466 * Currently, KVM doesn't mark global entries in the shadow 5467 * page tables, so a non-global flush just degenerates to a 5468 * global flush. If needed, we could optimize this later by 5469 * keeping track of global entries in shadow page tables. 5470 */ 5471 5472 /* fall-through */ 5473 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5474 kvm_mmu_unload(vcpu); 5475 return kvm_skip_emulated_instruction(vcpu); 5476 5477 default: 5478 BUG(); /* We have already checked above that type <= 3 */ 5479 } 5480 } 5481 5482 static int handle_pml_full(struct kvm_vcpu *vcpu) 5483 { 5484 unsigned long exit_qualification; 5485 5486 trace_kvm_pml_full(vcpu->vcpu_id); 5487 5488 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5489 5490 /* 5491 * PML buffer FULL happened while executing iret from NMI, 5492 * "blocked by NMI" bit has to be set before next VM entry. 5493 */ 5494 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5495 enable_vnmi && 5496 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5497 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5498 GUEST_INTR_STATE_NMI); 5499 5500 /* 5501 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5502 * here.., and there's no userspace involvement needed for PML. 5503 */ 5504 return 1; 5505 } 5506 5507 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5508 { 5509 struct vcpu_vmx *vmx = to_vmx(vcpu); 5510 5511 if (!vmx->req_immediate_exit && 5512 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5513 kvm_lapic_expired_hv_timer(vcpu); 5514 5515 return 1; 5516 } 5517 5518 /* 5519 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5520 * are overwritten by nested_vmx_setup() when nested=1. 5521 */ 5522 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5523 { 5524 kvm_queue_exception(vcpu, UD_VECTOR); 5525 return 1; 5526 } 5527 5528 static int handle_encls(struct kvm_vcpu *vcpu) 5529 { 5530 /* 5531 * SGX virtualization is not yet supported. There is no software 5532 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5533 * to prevent the guest from executing ENCLS. 5534 */ 5535 kvm_queue_exception(vcpu, UD_VECTOR); 5536 return 1; 5537 } 5538 5539 /* 5540 * The exit handlers return 1 if the exit was handled fully and guest execution 5541 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5542 * to be done to userspace and return 0. 5543 */ 5544 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5545 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5546 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5547 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5548 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5549 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5550 [EXIT_REASON_CR_ACCESS] = handle_cr, 5551 [EXIT_REASON_DR_ACCESS] = handle_dr, 5552 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5553 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5554 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5555 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5556 [EXIT_REASON_HLT] = kvm_emulate_halt, 5557 [EXIT_REASON_INVD] = handle_invd, 5558 [EXIT_REASON_INVLPG] = handle_invlpg, 5559 [EXIT_REASON_RDPMC] = handle_rdpmc, 5560 [EXIT_REASON_VMCALL] = handle_vmcall, 5561 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5562 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5563 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5564 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5565 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5566 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5567 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5568 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5569 [EXIT_REASON_VMON] = handle_vmx_instruction, 5570 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5571 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5572 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5573 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5574 [EXIT_REASON_WBINVD] = handle_wbinvd, 5575 [EXIT_REASON_XSETBV] = handle_xsetbv, 5576 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5577 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5578 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5579 [EXIT_REASON_LDTR_TR] = handle_desc, 5580 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5581 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5582 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5583 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5584 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5585 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5586 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5587 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5588 [EXIT_REASON_RDRAND] = handle_invalid_op, 5589 [EXIT_REASON_RDSEED] = handle_invalid_op, 5590 [EXIT_REASON_PML_FULL] = handle_pml_full, 5591 [EXIT_REASON_INVPCID] = handle_invpcid, 5592 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5593 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5594 [EXIT_REASON_ENCLS] = handle_encls, 5595 }; 5596 5597 static const int kvm_vmx_max_exit_handlers = 5598 ARRAY_SIZE(kvm_vmx_exit_handlers); 5599 5600 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5601 { 5602 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5603 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5604 } 5605 5606 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5607 { 5608 if (vmx->pml_pg) { 5609 __free_page(vmx->pml_pg); 5610 vmx->pml_pg = NULL; 5611 } 5612 } 5613 5614 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5615 { 5616 struct vcpu_vmx *vmx = to_vmx(vcpu); 5617 u64 *pml_buf; 5618 u16 pml_idx; 5619 5620 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5621 5622 /* Do nothing if PML buffer is empty */ 5623 if (pml_idx == (PML_ENTITY_NUM - 1)) 5624 return; 5625 5626 /* PML index always points to next available PML buffer entity */ 5627 if (pml_idx >= PML_ENTITY_NUM) 5628 pml_idx = 0; 5629 else 5630 pml_idx++; 5631 5632 pml_buf = page_address(vmx->pml_pg); 5633 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5634 u64 gpa; 5635 5636 gpa = pml_buf[pml_idx]; 5637 WARN_ON(gpa & (PAGE_SIZE - 1)); 5638 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5639 } 5640 5641 /* reset PML index */ 5642 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5643 } 5644 5645 /* 5646 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5647 * Called before reporting dirty_bitmap to userspace. 5648 */ 5649 static void kvm_flush_pml_buffers(struct kvm *kvm) 5650 { 5651 int i; 5652 struct kvm_vcpu *vcpu; 5653 /* 5654 * We only need to kick vcpu out of guest mode here, as PML buffer 5655 * is flushed at beginning of all VMEXITs, and it's obvious that only 5656 * vcpus running in guest are possible to have unflushed GPAs in PML 5657 * buffer. 5658 */ 5659 kvm_for_each_vcpu(i, vcpu, kvm) 5660 kvm_vcpu_kick(vcpu); 5661 } 5662 5663 static void vmx_dump_sel(char *name, uint32_t sel) 5664 { 5665 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5666 name, vmcs_read16(sel), 5667 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5668 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5669 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5670 } 5671 5672 static void vmx_dump_dtsel(char *name, uint32_t limit) 5673 { 5674 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5675 name, vmcs_read32(limit), 5676 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5677 } 5678 5679 void dump_vmcs(void) 5680 { 5681 u32 vmentry_ctl, vmexit_ctl; 5682 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5683 unsigned long cr4; 5684 u64 efer; 5685 int i, n; 5686 5687 if (!dump_invalid_vmcs) { 5688 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5689 return; 5690 } 5691 5692 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5693 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5694 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5695 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5696 cr4 = vmcs_readl(GUEST_CR4); 5697 efer = vmcs_read64(GUEST_IA32_EFER); 5698 secondary_exec_control = 0; 5699 if (cpu_has_secondary_exec_ctrls()) 5700 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5701 5702 pr_err("*** Guest State ***\n"); 5703 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5704 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5705 vmcs_readl(CR0_GUEST_HOST_MASK)); 5706 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5707 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5708 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5709 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5710 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5711 { 5712 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5713 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5714 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5715 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5716 } 5717 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5718 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5719 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5720 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5721 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5722 vmcs_readl(GUEST_SYSENTER_ESP), 5723 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5724 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5725 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5726 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5727 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5728 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5729 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5730 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5731 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5732 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5733 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5734 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5735 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5736 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5737 efer, vmcs_read64(GUEST_IA32_PAT)); 5738 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5739 vmcs_read64(GUEST_IA32_DEBUGCTL), 5740 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5741 if (cpu_has_load_perf_global_ctrl() && 5742 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5743 pr_err("PerfGlobCtl = 0x%016llx\n", 5744 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5745 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5746 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5747 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5748 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5749 vmcs_read32(GUEST_ACTIVITY_STATE)); 5750 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5751 pr_err("InterruptStatus = %04x\n", 5752 vmcs_read16(GUEST_INTR_STATUS)); 5753 5754 pr_err("*** Host State ***\n"); 5755 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5756 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5757 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5758 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5759 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5760 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5761 vmcs_read16(HOST_TR_SELECTOR)); 5762 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5763 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5764 vmcs_readl(HOST_TR_BASE)); 5765 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5766 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5767 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5768 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5769 vmcs_readl(HOST_CR4)); 5770 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5771 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5772 vmcs_read32(HOST_IA32_SYSENTER_CS), 5773 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5774 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5775 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5776 vmcs_read64(HOST_IA32_EFER), 5777 vmcs_read64(HOST_IA32_PAT)); 5778 if (cpu_has_load_perf_global_ctrl() && 5779 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5780 pr_err("PerfGlobCtl = 0x%016llx\n", 5781 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5782 5783 pr_err("*** Control State ***\n"); 5784 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5785 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5786 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5787 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5788 vmcs_read32(EXCEPTION_BITMAP), 5789 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5790 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5791 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5792 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5793 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5794 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5795 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5796 vmcs_read32(VM_EXIT_INTR_INFO), 5797 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5798 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5799 pr_err(" reason=%08x qualification=%016lx\n", 5800 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5801 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5802 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5803 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5804 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5805 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5806 pr_err("TSC Multiplier = 0x%016llx\n", 5807 vmcs_read64(TSC_MULTIPLIER)); 5808 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5809 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5810 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5811 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5812 } 5813 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5814 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5815 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5816 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5817 } 5818 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5819 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5820 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5821 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5822 n = vmcs_read32(CR3_TARGET_COUNT); 5823 for (i = 0; i + 1 < n; i += 4) 5824 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5825 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5826 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5827 if (i < n) 5828 pr_err("CR3 target%u=%016lx\n", 5829 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5830 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5831 pr_err("PLE Gap=%08x Window=%08x\n", 5832 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5833 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5834 pr_err("Virtual processor ID = 0x%04x\n", 5835 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5836 } 5837 5838 /* 5839 * The guest has exited. See if we can fix it or if we need userspace 5840 * assistance. 5841 */ 5842 static int vmx_handle_exit(struct kvm_vcpu *vcpu, 5843 enum exit_fastpath_completion exit_fastpath) 5844 { 5845 struct vcpu_vmx *vmx = to_vmx(vcpu); 5846 u32 exit_reason = vmx->exit_reason; 5847 u32 vectoring_info = vmx->idt_vectoring_info; 5848 5849 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5850 5851 /* 5852 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5853 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5854 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5855 * mode as if vcpus is in root mode, the PML buffer must has been 5856 * flushed already. 5857 */ 5858 if (enable_pml) 5859 vmx_flush_pml_buffer(vcpu); 5860 5861 /* If guest state is invalid, start emulating */ 5862 if (vmx->emulation_required) 5863 return handle_invalid_guest_state(vcpu); 5864 5865 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5866 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5867 5868 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5869 dump_vmcs(); 5870 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5871 vcpu->run->fail_entry.hardware_entry_failure_reason 5872 = exit_reason; 5873 return 0; 5874 } 5875 5876 if (unlikely(vmx->fail)) { 5877 dump_vmcs(); 5878 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5879 vcpu->run->fail_entry.hardware_entry_failure_reason 5880 = vmcs_read32(VM_INSTRUCTION_ERROR); 5881 return 0; 5882 } 5883 5884 /* 5885 * Note: 5886 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5887 * delivery event since it indicates guest is accessing MMIO. 5888 * The vm-exit can be triggered again after return to guest that 5889 * will cause infinite loop. 5890 */ 5891 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5892 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5893 exit_reason != EXIT_REASON_EPT_VIOLATION && 5894 exit_reason != EXIT_REASON_PML_FULL && 5895 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5896 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5897 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5898 vcpu->run->internal.ndata = 3; 5899 vcpu->run->internal.data[0] = vectoring_info; 5900 vcpu->run->internal.data[1] = exit_reason; 5901 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5902 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5903 vcpu->run->internal.ndata++; 5904 vcpu->run->internal.data[3] = 5905 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5906 } 5907 return 0; 5908 } 5909 5910 if (unlikely(!enable_vnmi && 5911 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5912 if (vmx_interrupt_allowed(vcpu)) { 5913 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5914 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5915 vcpu->arch.nmi_pending) { 5916 /* 5917 * This CPU don't support us in finding the end of an 5918 * NMI-blocked window if the guest runs with IRQs 5919 * disabled. So we pull the trigger after 1 s of 5920 * futile waiting, but inform the user about this. 5921 */ 5922 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5923 "state on VCPU %d after 1 s timeout\n", 5924 __func__, vcpu->vcpu_id); 5925 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5926 } 5927 } 5928 5929 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { 5930 kvm_skip_emulated_instruction(vcpu); 5931 return 1; 5932 } 5933 5934 if (exit_reason >= kvm_vmx_max_exit_handlers) 5935 goto unexpected_vmexit; 5936 #ifdef CONFIG_RETPOLINE 5937 if (exit_reason == EXIT_REASON_MSR_WRITE) 5938 return kvm_emulate_wrmsr(vcpu); 5939 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5940 return handle_preemption_timer(vcpu); 5941 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 5942 return handle_interrupt_window(vcpu); 5943 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5944 return handle_external_interrupt(vcpu); 5945 else if (exit_reason == EXIT_REASON_HLT) 5946 return kvm_emulate_halt(vcpu); 5947 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5948 return handle_ept_misconfig(vcpu); 5949 #endif 5950 5951 exit_reason = array_index_nospec(exit_reason, 5952 kvm_vmx_max_exit_handlers); 5953 if (!kvm_vmx_exit_handlers[exit_reason]) 5954 goto unexpected_vmexit; 5955 5956 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5957 5958 unexpected_vmexit: 5959 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 5960 dump_vmcs(); 5961 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5962 vcpu->run->internal.suberror = 5963 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5964 vcpu->run->internal.ndata = 1; 5965 vcpu->run->internal.data[0] = exit_reason; 5966 return 0; 5967 } 5968 5969 /* 5970 * Software based L1D cache flush which is used when microcode providing 5971 * the cache control MSR is not loaded. 5972 * 5973 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5974 * flush it is required to read in 64 KiB because the replacement algorithm 5975 * is not exactly LRU. This could be sized at runtime via topology 5976 * information but as all relevant affected CPUs have 32KiB L1D cache size 5977 * there is no point in doing so. 5978 */ 5979 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5980 { 5981 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5982 5983 /* 5984 * This code is only executed when the the flush mode is 'cond' or 5985 * 'always' 5986 */ 5987 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5988 bool flush_l1d; 5989 5990 /* 5991 * Clear the per-vcpu flush bit, it gets set again 5992 * either from vcpu_run() or from one of the unsafe 5993 * VMEXIT handlers. 5994 */ 5995 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5996 vcpu->arch.l1tf_flush_l1d = false; 5997 5998 /* 5999 * Clear the per-cpu flush bit, it gets set again from 6000 * the interrupt handlers. 6001 */ 6002 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 6003 kvm_clear_cpu_l1tf_flush_l1d(); 6004 6005 if (!flush_l1d) 6006 return; 6007 } 6008 6009 vcpu->stat.l1d_flush++; 6010 6011 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 6012 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6013 return; 6014 } 6015 6016 asm volatile( 6017 /* First ensure the pages are in the TLB */ 6018 "xorl %%eax, %%eax\n" 6019 ".Lpopulate_tlb:\n\t" 6020 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6021 "addl $4096, %%eax\n\t" 6022 "cmpl %%eax, %[size]\n\t" 6023 "jne .Lpopulate_tlb\n\t" 6024 "xorl %%eax, %%eax\n\t" 6025 "cpuid\n\t" 6026 /* Now fill the cache */ 6027 "xorl %%eax, %%eax\n" 6028 ".Lfill_cache:\n" 6029 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6030 "addl $64, %%eax\n\t" 6031 "cmpl %%eax, %[size]\n\t" 6032 "jne .Lfill_cache\n\t" 6033 "lfence\n" 6034 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6035 [size] "r" (size) 6036 : "eax", "ebx", "ecx", "edx"); 6037 } 6038 6039 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6040 { 6041 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6042 int tpr_threshold; 6043 6044 if (is_guest_mode(vcpu) && 6045 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6046 return; 6047 6048 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6049 if (is_guest_mode(vcpu)) 6050 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6051 else 6052 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6053 } 6054 6055 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6056 { 6057 struct vcpu_vmx *vmx = to_vmx(vcpu); 6058 u32 sec_exec_control; 6059 6060 if (!lapic_in_kernel(vcpu)) 6061 return; 6062 6063 if (!flexpriority_enabled && 6064 !cpu_has_vmx_virtualize_x2apic_mode()) 6065 return; 6066 6067 /* Postpone execution until vmcs01 is the current VMCS. */ 6068 if (is_guest_mode(vcpu)) { 6069 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6070 return; 6071 } 6072 6073 sec_exec_control = secondary_exec_controls_get(vmx); 6074 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6075 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6076 6077 switch (kvm_get_apic_mode(vcpu)) { 6078 case LAPIC_MODE_INVALID: 6079 WARN_ONCE(true, "Invalid local APIC state"); 6080 case LAPIC_MODE_DISABLED: 6081 break; 6082 case LAPIC_MODE_XAPIC: 6083 if (flexpriority_enabled) { 6084 sec_exec_control |= 6085 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6086 vmx_flush_tlb(vcpu, true); 6087 } 6088 break; 6089 case LAPIC_MODE_X2APIC: 6090 if (cpu_has_vmx_virtualize_x2apic_mode()) 6091 sec_exec_control |= 6092 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6093 break; 6094 } 6095 secondary_exec_controls_set(vmx, sec_exec_control); 6096 6097 vmx_update_msr_bitmap(vcpu); 6098 } 6099 6100 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6101 { 6102 if (!is_guest_mode(vcpu)) { 6103 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6104 vmx_flush_tlb(vcpu, true); 6105 } 6106 } 6107 6108 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6109 { 6110 u16 status; 6111 u8 old; 6112 6113 if (max_isr == -1) 6114 max_isr = 0; 6115 6116 status = vmcs_read16(GUEST_INTR_STATUS); 6117 old = status >> 8; 6118 if (max_isr != old) { 6119 status &= 0xff; 6120 status |= max_isr << 8; 6121 vmcs_write16(GUEST_INTR_STATUS, status); 6122 } 6123 } 6124 6125 static void vmx_set_rvi(int vector) 6126 { 6127 u16 status; 6128 u8 old; 6129 6130 if (vector == -1) 6131 vector = 0; 6132 6133 status = vmcs_read16(GUEST_INTR_STATUS); 6134 old = (u8)status & 0xff; 6135 if ((u8)vector != old) { 6136 status &= ~0xff; 6137 status |= (u8)vector; 6138 vmcs_write16(GUEST_INTR_STATUS, status); 6139 } 6140 } 6141 6142 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6143 { 6144 /* 6145 * When running L2, updating RVI is only relevant when 6146 * vmcs12 virtual-interrupt-delivery enabled. 6147 * However, it can be enabled only when L1 also 6148 * intercepts external-interrupts and in that case 6149 * we should not update vmcs02 RVI but instead intercept 6150 * interrupt. Therefore, do nothing when running L2. 6151 */ 6152 if (!is_guest_mode(vcpu)) 6153 vmx_set_rvi(max_irr); 6154 } 6155 6156 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6157 { 6158 struct vcpu_vmx *vmx = to_vmx(vcpu); 6159 int max_irr; 6160 bool max_irr_updated; 6161 6162 WARN_ON(!vcpu->arch.apicv_active); 6163 if (pi_test_on(&vmx->pi_desc)) { 6164 pi_clear_on(&vmx->pi_desc); 6165 /* 6166 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6167 * But on x86 this is just a compiler barrier anyway. 6168 */ 6169 smp_mb__after_atomic(); 6170 max_irr_updated = 6171 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6172 6173 /* 6174 * If we are running L2 and L1 has a new pending interrupt 6175 * which can be injected, we should re-evaluate 6176 * what should be done with this new L1 interrupt. 6177 * If L1 intercepts external-interrupts, we should 6178 * exit from L2 to L1. Otherwise, interrupt should be 6179 * delivered directly to L2. 6180 */ 6181 if (is_guest_mode(vcpu) && max_irr_updated) { 6182 if (nested_exit_on_intr(vcpu)) 6183 kvm_vcpu_exiting_guest_mode(vcpu); 6184 else 6185 kvm_make_request(KVM_REQ_EVENT, vcpu); 6186 } 6187 } else { 6188 max_irr = kvm_lapic_find_highest_irr(vcpu); 6189 } 6190 vmx_hwapic_irr_update(vcpu, max_irr); 6191 return max_irr; 6192 } 6193 6194 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6195 { 6196 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6197 6198 return pi_test_on(pi_desc) || 6199 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6200 } 6201 6202 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6203 { 6204 if (!kvm_vcpu_apicv_active(vcpu)) 6205 return; 6206 6207 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6208 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6209 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6210 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6211 } 6212 6213 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6214 { 6215 struct vcpu_vmx *vmx = to_vmx(vcpu); 6216 6217 pi_clear_on(&vmx->pi_desc); 6218 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6219 } 6220 6221 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6222 { 6223 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6224 6225 /* if exit due to PF check for async PF */ 6226 if (is_page_fault(vmx->exit_intr_info)) 6227 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6228 6229 /* Handle machine checks before interrupts are enabled */ 6230 if (is_machine_check(vmx->exit_intr_info)) 6231 kvm_machine_check(); 6232 6233 /* We need to handle NMIs before interrupts are enabled */ 6234 if (is_nmi(vmx->exit_intr_info)) { 6235 kvm_before_interrupt(&vmx->vcpu); 6236 asm("int $2"); 6237 kvm_after_interrupt(&vmx->vcpu); 6238 } 6239 } 6240 6241 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6242 { 6243 unsigned int vector; 6244 unsigned long entry; 6245 #ifdef CONFIG_X86_64 6246 unsigned long tmp; 6247 #endif 6248 gate_desc *desc; 6249 u32 intr_info; 6250 6251 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6252 if (WARN_ONCE(!is_external_intr(intr_info), 6253 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6254 return; 6255 6256 vector = intr_info & INTR_INFO_VECTOR_MASK; 6257 desc = (gate_desc *)host_idt_base + vector; 6258 entry = gate_offset(desc); 6259 6260 kvm_before_interrupt(vcpu); 6261 6262 asm volatile( 6263 #ifdef CONFIG_X86_64 6264 "mov %%" _ASM_SP ", %[sp]\n\t" 6265 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6266 "push $%c[ss]\n\t" 6267 "push %[sp]\n\t" 6268 #endif 6269 "pushf\n\t" 6270 __ASM_SIZE(push) " $%c[cs]\n\t" 6271 CALL_NOSPEC 6272 : 6273 #ifdef CONFIG_X86_64 6274 [sp]"=&r"(tmp), 6275 #endif 6276 ASM_CALL_CONSTRAINT 6277 : 6278 THUNK_TARGET(entry), 6279 [ss]"i"(__KERNEL_DS), 6280 [cs]"i"(__KERNEL_CS) 6281 ); 6282 6283 kvm_after_interrupt(vcpu); 6284 } 6285 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6286 6287 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu, 6288 enum exit_fastpath_completion *exit_fastpath) 6289 { 6290 struct vcpu_vmx *vmx = to_vmx(vcpu); 6291 6292 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6293 handle_external_interrupt_irqoff(vcpu); 6294 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6295 handle_exception_nmi_irqoff(vmx); 6296 else if (!is_guest_mode(vcpu) && 6297 vmx->exit_reason == EXIT_REASON_MSR_WRITE) 6298 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); 6299 } 6300 6301 static bool vmx_has_emulated_msr(int index) 6302 { 6303 switch (index) { 6304 case MSR_IA32_SMBASE: 6305 /* 6306 * We cannot do SMM unless we can run the guest in big 6307 * real mode. 6308 */ 6309 return enable_unrestricted_guest || emulate_invalid_guest_state; 6310 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6311 return nested; 6312 case MSR_AMD64_VIRT_SPEC_CTRL: 6313 /* This is AMD only. */ 6314 return false; 6315 default: 6316 return true; 6317 } 6318 } 6319 6320 static bool vmx_pt_supported(void) 6321 { 6322 return pt_mode == PT_MODE_HOST_GUEST; 6323 } 6324 6325 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6326 { 6327 u32 exit_intr_info; 6328 bool unblock_nmi; 6329 u8 vector; 6330 bool idtv_info_valid; 6331 6332 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6333 6334 if (enable_vnmi) { 6335 if (vmx->loaded_vmcs->nmi_known_unmasked) 6336 return; 6337 /* 6338 * Can't use vmx->exit_intr_info since we're not sure what 6339 * the exit reason is. 6340 */ 6341 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6342 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6343 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6344 /* 6345 * SDM 3: 27.7.1.2 (September 2008) 6346 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6347 * a guest IRET fault. 6348 * SDM 3: 23.2.2 (September 2008) 6349 * Bit 12 is undefined in any of the following cases: 6350 * If the VM exit sets the valid bit in the IDT-vectoring 6351 * information field. 6352 * If the VM exit is due to a double fault. 6353 */ 6354 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6355 vector != DF_VECTOR && !idtv_info_valid) 6356 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6357 GUEST_INTR_STATE_NMI); 6358 else 6359 vmx->loaded_vmcs->nmi_known_unmasked = 6360 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6361 & GUEST_INTR_STATE_NMI); 6362 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6363 vmx->loaded_vmcs->vnmi_blocked_time += 6364 ktime_to_ns(ktime_sub(ktime_get(), 6365 vmx->loaded_vmcs->entry_time)); 6366 } 6367 6368 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6369 u32 idt_vectoring_info, 6370 int instr_len_field, 6371 int error_code_field) 6372 { 6373 u8 vector; 6374 int type; 6375 bool idtv_info_valid; 6376 6377 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6378 6379 vcpu->arch.nmi_injected = false; 6380 kvm_clear_exception_queue(vcpu); 6381 kvm_clear_interrupt_queue(vcpu); 6382 6383 if (!idtv_info_valid) 6384 return; 6385 6386 kvm_make_request(KVM_REQ_EVENT, vcpu); 6387 6388 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6389 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6390 6391 switch (type) { 6392 case INTR_TYPE_NMI_INTR: 6393 vcpu->arch.nmi_injected = true; 6394 /* 6395 * SDM 3: 27.7.1.2 (September 2008) 6396 * Clear bit "block by NMI" before VM entry if a NMI 6397 * delivery faulted. 6398 */ 6399 vmx_set_nmi_mask(vcpu, false); 6400 break; 6401 case INTR_TYPE_SOFT_EXCEPTION: 6402 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6403 /* fall through */ 6404 case INTR_TYPE_HARD_EXCEPTION: 6405 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6406 u32 err = vmcs_read32(error_code_field); 6407 kvm_requeue_exception_e(vcpu, vector, err); 6408 } else 6409 kvm_requeue_exception(vcpu, vector); 6410 break; 6411 case INTR_TYPE_SOFT_INTR: 6412 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6413 /* fall through */ 6414 case INTR_TYPE_EXT_INTR: 6415 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6416 break; 6417 default: 6418 break; 6419 } 6420 } 6421 6422 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6423 { 6424 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6425 VM_EXIT_INSTRUCTION_LEN, 6426 IDT_VECTORING_ERROR_CODE); 6427 } 6428 6429 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6430 { 6431 __vmx_complete_interrupts(vcpu, 6432 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6433 VM_ENTRY_INSTRUCTION_LEN, 6434 VM_ENTRY_EXCEPTION_ERROR_CODE); 6435 6436 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6437 } 6438 6439 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6440 { 6441 int i, nr_msrs; 6442 struct perf_guest_switch_msr *msrs; 6443 6444 msrs = perf_guest_get_msrs(&nr_msrs); 6445 6446 if (!msrs) 6447 return; 6448 6449 for (i = 0; i < nr_msrs; i++) 6450 if (msrs[i].host == msrs[i].guest) 6451 clear_atomic_switch_msr(vmx, msrs[i].msr); 6452 else 6453 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6454 msrs[i].host, false); 6455 } 6456 6457 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6458 { 6459 u32 host_umwait_control; 6460 6461 if (!vmx_has_waitpkg(vmx)) 6462 return; 6463 6464 host_umwait_control = get_umwait_control_msr(); 6465 6466 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6467 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6468 vmx->msr_ia32_umwait_control, 6469 host_umwait_control, false); 6470 else 6471 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6472 } 6473 6474 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6475 { 6476 struct vcpu_vmx *vmx = to_vmx(vcpu); 6477 u64 tscl; 6478 u32 delta_tsc; 6479 6480 if (vmx->req_immediate_exit) { 6481 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6482 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6483 } else if (vmx->hv_deadline_tsc != -1) { 6484 tscl = rdtsc(); 6485 if (vmx->hv_deadline_tsc > tscl) 6486 /* set_hv_timer ensures the delta fits in 32-bits */ 6487 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6488 cpu_preemption_timer_multi); 6489 else 6490 delta_tsc = 0; 6491 6492 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6493 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6494 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6495 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6496 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6497 } 6498 } 6499 6500 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6501 { 6502 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6503 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6504 vmcs_writel(HOST_RSP, host_rsp); 6505 } 6506 } 6507 6508 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6509 6510 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6511 { 6512 struct vcpu_vmx *vmx = to_vmx(vcpu); 6513 unsigned long cr3, cr4; 6514 6515 /* Record the guest's net vcpu time for enforced NMI injections. */ 6516 if (unlikely(!enable_vnmi && 6517 vmx->loaded_vmcs->soft_vnmi_blocked)) 6518 vmx->loaded_vmcs->entry_time = ktime_get(); 6519 6520 /* Don't enter VMX if guest state is invalid, let the exit handler 6521 start emulation until we arrive back to a valid state */ 6522 if (vmx->emulation_required) 6523 return; 6524 6525 if (vmx->ple_window_dirty) { 6526 vmx->ple_window_dirty = false; 6527 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6528 } 6529 6530 /* 6531 * We did this in prepare_switch_to_guest, because it needs to 6532 * be within srcu_read_lock. 6533 */ 6534 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync); 6535 6536 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6537 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6538 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6539 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6540 6541 cr3 = __get_current_cr3_fast(); 6542 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6543 vmcs_writel(HOST_CR3, cr3); 6544 vmx->loaded_vmcs->host_state.cr3 = cr3; 6545 } 6546 6547 cr4 = cr4_read_shadow(); 6548 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6549 vmcs_writel(HOST_CR4, cr4); 6550 vmx->loaded_vmcs->host_state.cr4 = cr4; 6551 } 6552 6553 /* When single-stepping over STI and MOV SS, we must clear the 6554 * corresponding interruptibility bits in the guest state. Otherwise 6555 * vmentry fails as it then expects bit 14 (BS) in pending debug 6556 * exceptions being set, but that's not correct for the guest debugging 6557 * case. */ 6558 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6559 vmx_set_interrupt_shadow(vcpu, 0); 6560 6561 kvm_load_guest_xsave_state(vcpu); 6562 6563 if (static_cpu_has(X86_FEATURE_PKU) && 6564 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6565 vcpu->arch.pkru != vmx->host_pkru) 6566 __write_pkru(vcpu->arch.pkru); 6567 6568 pt_guest_enter(vmx); 6569 6570 atomic_switch_perf_msrs(vmx); 6571 atomic_switch_umwait_control_msr(vmx); 6572 6573 if (enable_preemption_timer) 6574 vmx_update_hv_timer(vcpu); 6575 6576 if (lapic_in_kernel(vcpu) && 6577 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6578 kvm_wait_lapic_expire(vcpu); 6579 6580 /* 6581 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6582 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6583 * is no need to worry about the conditional branch over the wrmsr 6584 * being speculatively taken. 6585 */ 6586 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6587 6588 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6589 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6590 vmx_l1d_flush(vcpu); 6591 else if (static_branch_unlikely(&mds_user_clear)) 6592 mds_clear_cpu_buffers(); 6593 6594 if (vcpu->arch.cr2 != read_cr2()) 6595 write_cr2(vcpu->arch.cr2); 6596 6597 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6598 vmx->loaded_vmcs->launched); 6599 6600 vcpu->arch.cr2 = read_cr2(); 6601 6602 /* 6603 * We do not use IBRS in the kernel. If this vCPU has used the 6604 * SPEC_CTRL MSR it may have left it on; save the value and 6605 * turn it off. This is much more efficient than blindly adding 6606 * it to the atomic save/restore list. Especially as the former 6607 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6608 * 6609 * For non-nested case: 6610 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6611 * save it. 6612 * 6613 * For nested case: 6614 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6615 * save it. 6616 */ 6617 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6618 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6619 6620 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6621 6622 /* All fields are clean at this point */ 6623 if (static_branch_unlikely(&enable_evmcs)) 6624 current_evmcs->hv_clean_fields |= 6625 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6626 6627 if (static_branch_unlikely(&enable_evmcs)) 6628 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6629 6630 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6631 if (vmx->host_debugctlmsr) 6632 update_debugctlmsr(vmx->host_debugctlmsr); 6633 6634 #ifndef CONFIG_X86_64 6635 /* 6636 * The sysexit path does not restore ds/es, so we must set them to 6637 * a reasonable value ourselves. 6638 * 6639 * We can't defer this to vmx_prepare_switch_to_host() since that 6640 * function may be executed in interrupt context, which saves and 6641 * restore segments around it, nullifying its effect. 6642 */ 6643 loadsegment(ds, __USER_DS); 6644 loadsegment(es, __USER_DS); 6645 #endif 6646 6647 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6648 | (1 << VCPU_EXREG_RFLAGS) 6649 | (1 << VCPU_EXREG_PDPTR) 6650 | (1 << VCPU_EXREG_SEGMENTS) 6651 | (1 << VCPU_EXREG_CR3)); 6652 vcpu->arch.regs_dirty = 0; 6653 6654 pt_guest_exit(vmx); 6655 6656 /* 6657 * eager fpu is enabled if PKEY is supported and CR4 is switched 6658 * back on host, so it is safe to read guest PKRU from current 6659 * XSAVE. 6660 */ 6661 if (static_cpu_has(X86_FEATURE_PKU) && 6662 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6663 vcpu->arch.pkru = rdpkru(); 6664 if (vcpu->arch.pkru != vmx->host_pkru) 6665 __write_pkru(vmx->host_pkru); 6666 } 6667 6668 kvm_load_host_xsave_state(vcpu); 6669 6670 vmx->nested.nested_run_pending = 0; 6671 vmx->idt_vectoring_info = 0; 6672 6673 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6674 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6675 kvm_machine_check(); 6676 6677 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6678 return; 6679 6680 vmx->loaded_vmcs->launched = 1; 6681 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6682 6683 vmx_recover_nmi_blocking(vmx); 6684 vmx_complete_interrupts(vmx); 6685 } 6686 6687 static struct kvm *vmx_vm_alloc(void) 6688 { 6689 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6690 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6691 PAGE_KERNEL); 6692 return &kvm_vmx->kvm; 6693 } 6694 6695 static void vmx_vm_free(struct kvm *kvm) 6696 { 6697 kfree(kvm->arch.hyperv.hv_pa_pg); 6698 vfree(to_kvm_vmx(kvm)); 6699 } 6700 6701 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6702 { 6703 struct vcpu_vmx *vmx = to_vmx(vcpu); 6704 6705 if (enable_pml) 6706 vmx_destroy_pml_buffer(vmx); 6707 free_vpid(vmx->vpid); 6708 nested_vmx_free_vcpu(vcpu); 6709 free_loaded_vmcs(vmx->loaded_vmcs); 6710 } 6711 6712 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6713 { 6714 struct vcpu_vmx *vmx; 6715 unsigned long *msr_bitmap; 6716 int i, cpu, err; 6717 6718 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6719 vmx = to_vmx(vcpu); 6720 6721 err = -ENOMEM; 6722 6723 vmx->vpid = allocate_vpid(); 6724 6725 /* 6726 * If PML is turned on, failure on enabling PML just results in failure 6727 * of creating the vcpu, therefore we can simplify PML logic (by 6728 * avoiding dealing with cases, such as enabling PML partially on vcpus 6729 * for the guest), etc. 6730 */ 6731 if (enable_pml) { 6732 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6733 if (!vmx->pml_pg) 6734 goto free_vpid; 6735 } 6736 6737 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6738 6739 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6740 u32 index = vmx_msr_index[i]; 6741 u32 data_low, data_high; 6742 int j = vmx->nmsrs; 6743 6744 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6745 continue; 6746 if (wrmsr_safe(index, data_low, data_high) < 0) 6747 continue; 6748 6749 vmx->guest_msrs[j].index = i; 6750 vmx->guest_msrs[j].data = 0; 6751 switch (index) { 6752 case MSR_IA32_TSX_CTRL: 6753 /* 6754 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6755 * let's avoid changing CPUID bits under the host 6756 * kernel's feet. 6757 */ 6758 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6759 break; 6760 default: 6761 vmx->guest_msrs[j].mask = -1ull; 6762 break; 6763 } 6764 ++vmx->nmsrs; 6765 } 6766 6767 err = alloc_loaded_vmcs(&vmx->vmcs01); 6768 if (err < 0) 6769 goto free_pml; 6770 6771 msr_bitmap = vmx->vmcs01.msr_bitmap; 6772 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6773 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6774 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6775 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6776 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6777 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6778 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6779 if (kvm_cstate_in_guest(vcpu->kvm)) { 6780 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6781 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6782 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6783 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6784 } 6785 vmx->msr_bitmap_mode = 0; 6786 6787 vmx->loaded_vmcs = &vmx->vmcs01; 6788 cpu = get_cpu(); 6789 vmx_vcpu_load(vcpu, cpu); 6790 vcpu->cpu = cpu; 6791 init_vmcs(vmx); 6792 vmx_vcpu_put(vcpu); 6793 put_cpu(); 6794 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6795 err = alloc_apic_access_page(vcpu->kvm); 6796 if (err) 6797 goto free_vmcs; 6798 } 6799 6800 if (enable_ept && !enable_unrestricted_guest) { 6801 err = init_rmode_identity_map(vcpu->kvm); 6802 if (err) 6803 goto free_vmcs; 6804 } 6805 6806 if (nested) 6807 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6808 vmx_capability.ept); 6809 else 6810 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6811 6812 vmx->nested.posted_intr_nv = -1; 6813 vmx->nested.current_vmptr = -1ull; 6814 6815 vcpu->arch.microcode_version = 0x100000000ULL; 6816 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6817 6818 /* 6819 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6820 * or POSTED_INTR_WAKEUP_VECTOR. 6821 */ 6822 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6823 vmx->pi_desc.sn = 1; 6824 6825 vmx->ept_pointer = INVALID_PAGE; 6826 6827 return 0; 6828 6829 free_vmcs: 6830 free_loaded_vmcs(vmx->loaded_vmcs); 6831 free_pml: 6832 vmx_destroy_pml_buffer(vmx); 6833 free_vpid: 6834 free_vpid(vmx->vpid); 6835 return err; 6836 } 6837 6838 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6839 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6840 6841 static int vmx_vm_init(struct kvm *kvm) 6842 { 6843 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6844 6845 if (!ple_gap) 6846 kvm->arch.pause_in_guest = true; 6847 6848 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6849 switch (l1tf_mitigation) { 6850 case L1TF_MITIGATION_OFF: 6851 case L1TF_MITIGATION_FLUSH_NOWARN: 6852 /* 'I explicitly don't care' is set */ 6853 break; 6854 case L1TF_MITIGATION_FLUSH: 6855 case L1TF_MITIGATION_FLUSH_NOSMT: 6856 case L1TF_MITIGATION_FULL: 6857 /* 6858 * Warn upon starting the first VM in a potentially 6859 * insecure environment. 6860 */ 6861 if (sched_smt_active()) 6862 pr_warn_once(L1TF_MSG_SMT); 6863 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6864 pr_warn_once(L1TF_MSG_L1D); 6865 break; 6866 case L1TF_MITIGATION_FULL_FORCE: 6867 /* Flush is enforced */ 6868 break; 6869 } 6870 } 6871 kvm_apicv_init(kvm, enable_apicv); 6872 return 0; 6873 } 6874 6875 static int __init vmx_check_processor_compat(void) 6876 { 6877 struct vmcs_config vmcs_conf; 6878 struct vmx_capability vmx_cap; 6879 6880 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6881 !this_cpu_has(X86_FEATURE_VMX)) { 6882 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6883 return -EIO; 6884 } 6885 6886 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6887 return -EIO; 6888 if (nested) 6889 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept); 6890 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6891 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6892 smp_processor_id()); 6893 return -EIO; 6894 } 6895 return 0; 6896 } 6897 6898 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6899 { 6900 u8 cache; 6901 u64 ipat = 0; 6902 6903 /* For VT-d and EPT combination 6904 * 1. MMIO: always map as UC 6905 * 2. EPT with VT-d: 6906 * a. VT-d without snooping control feature: can't guarantee the 6907 * result, try to trust guest. 6908 * b. VT-d with snooping control feature: snooping control feature of 6909 * VT-d engine can guarantee the cache correctness. Just set it 6910 * to WB to keep consistent with host. So the same as item 3. 6911 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6912 * consistent with host MTRR 6913 */ 6914 if (is_mmio) { 6915 cache = MTRR_TYPE_UNCACHABLE; 6916 goto exit; 6917 } 6918 6919 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6920 ipat = VMX_EPT_IPAT_BIT; 6921 cache = MTRR_TYPE_WRBACK; 6922 goto exit; 6923 } 6924 6925 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6926 ipat = VMX_EPT_IPAT_BIT; 6927 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6928 cache = MTRR_TYPE_WRBACK; 6929 else 6930 cache = MTRR_TYPE_UNCACHABLE; 6931 goto exit; 6932 } 6933 6934 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6935 6936 exit: 6937 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6938 } 6939 6940 static int vmx_get_lpage_level(void) 6941 { 6942 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6943 return PT_DIRECTORY_LEVEL; 6944 else 6945 /* For shadow and EPT supported 1GB page */ 6946 return PT_PDPE_LEVEL; 6947 } 6948 6949 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6950 { 6951 /* 6952 * These bits in the secondary execution controls field 6953 * are dynamic, the others are mostly based on the hypervisor 6954 * architecture and the guest's CPUID. Do not touch the 6955 * dynamic bits. 6956 */ 6957 u32 mask = 6958 SECONDARY_EXEC_SHADOW_VMCS | 6959 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6960 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6961 SECONDARY_EXEC_DESC; 6962 6963 u32 new_ctl = vmx->secondary_exec_control; 6964 u32 cur_ctl = secondary_exec_controls_get(vmx); 6965 6966 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6967 } 6968 6969 /* 6970 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6971 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6972 */ 6973 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6974 { 6975 struct vcpu_vmx *vmx = to_vmx(vcpu); 6976 struct kvm_cpuid_entry2 *entry; 6977 6978 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6979 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6980 6981 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6982 if (entry && (entry->_reg & (_cpuid_mask))) \ 6983 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6984 } while (0) 6985 6986 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6987 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 6988 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 6989 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 6990 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 6991 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 6992 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 6993 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 6994 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 6995 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 6996 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 6997 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 6998 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 6999 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 7000 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 7001 7002 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 7003 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 7004 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 7005 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 7006 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 7007 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 7008 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 7009 7010 #undef cr4_fixed1_update 7011 } 7012 7013 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 7014 { 7015 struct vcpu_vmx *vmx = to_vmx(vcpu); 7016 7017 if (kvm_mpx_supported()) { 7018 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 7019 7020 if (mpx_enabled) { 7021 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 7022 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 7023 } else { 7024 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 7025 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 7026 } 7027 } 7028 } 7029 7030 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7031 { 7032 struct vcpu_vmx *vmx = to_vmx(vcpu); 7033 struct kvm_cpuid_entry2 *best = NULL; 7034 int i; 7035 7036 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7037 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7038 if (!best) 7039 return; 7040 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7041 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7042 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7043 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7044 } 7045 7046 /* Get the number of configurable Address Ranges for filtering */ 7047 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7048 PT_CAP_num_address_ranges); 7049 7050 /* Initialize and clear the no dependency bits */ 7051 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7052 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7053 7054 /* 7055 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7056 * will inject an #GP 7057 */ 7058 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7059 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7060 7061 /* 7062 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7063 * PSBFreq can be set 7064 */ 7065 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7066 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7067 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7068 7069 /* 7070 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7071 * MTCFreq can be set 7072 */ 7073 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7074 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7075 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7076 7077 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7078 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7079 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7080 RTIT_CTL_PTW_EN); 7081 7082 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7083 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7084 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7085 7086 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7087 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7088 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7089 7090 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7091 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7092 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7093 7094 /* unmask address range configure area */ 7095 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7096 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7097 } 7098 7099 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7100 { 7101 struct vcpu_vmx *vmx = to_vmx(vcpu); 7102 7103 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7104 vcpu->arch.xsaves_enabled = false; 7105 7106 if (cpu_has_secondary_exec_ctrls()) { 7107 vmx_compute_secondary_exec_control(vmx); 7108 vmcs_set_secondary_exec_control(vmx); 7109 } 7110 7111 if (nested_vmx_allowed(vcpu)) 7112 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7113 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7114 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7115 else 7116 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7117 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7118 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7119 7120 if (nested_vmx_allowed(vcpu)) { 7121 nested_vmx_cr_fixed1_bits_update(vcpu); 7122 nested_vmx_entry_exit_ctls_update(vcpu); 7123 } 7124 7125 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7126 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7127 update_intel_pt_cfg(vcpu); 7128 7129 if (boot_cpu_has(X86_FEATURE_RTM)) { 7130 struct shared_msr_entry *msr; 7131 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7132 if (msr) { 7133 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7134 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7135 } 7136 } 7137 } 7138 7139 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 7140 { 7141 if (func == 1 && nested) 7142 entry->ecx |= feature_bit(VMX); 7143 } 7144 7145 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7146 { 7147 to_vmx(vcpu)->req_immediate_exit = true; 7148 } 7149 7150 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, 7151 struct x86_instruction_info *info) 7152 { 7153 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7154 unsigned short port; 7155 bool intercept; 7156 int size; 7157 7158 if (info->intercept == x86_intercept_in || 7159 info->intercept == x86_intercept_ins) { 7160 port = info->src_val; 7161 size = info->dst_bytes; 7162 } else { 7163 port = info->dst_val; 7164 size = info->src_bytes; 7165 } 7166 7167 /* 7168 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction 7169 * VM-exits depend on the 'unconditional IO exiting' VM-execution 7170 * control. 7171 * 7172 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. 7173 */ 7174 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 7175 intercept = nested_cpu_has(vmcs12, 7176 CPU_BASED_UNCOND_IO_EXITING); 7177 else 7178 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); 7179 7180 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7181 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 7182 } 7183 7184 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7185 struct x86_instruction_info *info, 7186 enum x86_intercept_stage stage) 7187 { 7188 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7189 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7190 7191 switch (info->intercept) { 7192 /* 7193 * RDPID causes #UD if disabled through secondary execution controls. 7194 * Because it is marked as EmulateOnUD, we need to intercept it here. 7195 */ 7196 case x86_intercept_rdtscp: 7197 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7198 ctxt->exception.vector = UD_VECTOR; 7199 ctxt->exception.error_code_valid = false; 7200 return X86EMUL_PROPAGATE_FAULT; 7201 } 7202 break; 7203 7204 case x86_intercept_in: 7205 case x86_intercept_ins: 7206 case x86_intercept_out: 7207 case x86_intercept_outs: 7208 return vmx_check_intercept_io(vcpu, info); 7209 7210 case x86_intercept_lgdt: 7211 case x86_intercept_lidt: 7212 case x86_intercept_lldt: 7213 case x86_intercept_ltr: 7214 case x86_intercept_sgdt: 7215 case x86_intercept_sidt: 7216 case x86_intercept_sldt: 7217 case x86_intercept_str: 7218 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC)) 7219 return X86EMUL_CONTINUE; 7220 7221 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7222 break; 7223 7224 /* TODO: check more intercepts... */ 7225 default: 7226 break; 7227 } 7228 7229 return X86EMUL_UNHANDLEABLE; 7230 } 7231 7232 #ifdef CONFIG_X86_64 7233 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7234 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7235 u64 divisor, u64 *result) 7236 { 7237 u64 low = a << shift, high = a >> (64 - shift); 7238 7239 /* To avoid the overflow on divq */ 7240 if (high >= divisor) 7241 return 1; 7242 7243 /* Low hold the result, high hold rem which is discarded */ 7244 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7245 "rm" (divisor), "0" (low), "1" (high)); 7246 *result = low; 7247 7248 return 0; 7249 } 7250 7251 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7252 bool *expired) 7253 { 7254 struct vcpu_vmx *vmx; 7255 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7256 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7257 7258 if (kvm_mwait_in_guest(vcpu->kvm) || 7259 kvm_can_post_timer_interrupt(vcpu)) 7260 return -EOPNOTSUPP; 7261 7262 vmx = to_vmx(vcpu); 7263 tscl = rdtsc(); 7264 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7265 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7266 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7267 ktimer->timer_advance_ns); 7268 7269 if (delta_tsc > lapic_timer_advance_cycles) 7270 delta_tsc -= lapic_timer_advance_cycles; 7271 else 7272 delta_tsc = 0; 7273 7274 /* Convert to host delta tsc if tsc scaling is enabled */ 7275 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7276 delta_tsc && u64_shl_div_u64(delta_tsc, 7277 kvm_tsc_scaling_ratio_frac_bits, 7278 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7279 return -ERANGE; 7280 7281 /* 7282 * If the delta tsc can't fit in the 32 bit after the multi shift, 7283 * we can't use the preemption timer. 7284 * It's possible that it fits on later vmentries, but checking 7285 * on every vmentry is costly so we just use an hrtimer. 7286 */ 7287 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7288 return -ERANGE; 7289 7290 vmx->hv_deadline_tsc = tscl + delta_tsc; 7291 *expired = !delta_tsc; 7292 return 0; 7293 } 7294 7295 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7296 { 7297 to_vmx(vcpu)->hv_deadline_tsc = -1; 7298 } 7299 #endif 7300 7301 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7302 { 7303 if (!kvm_pause_in_guest(vcpu->kvm)) 7304 shrink_ple_window(vcpu); 7305 } 7306 7307 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7308 struct kvm_memory_slot *slot) 7309 { 7310 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7311 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7312 } 7313 7314 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7315 struct kvm_memory_slot *slot) 7316 { 7317 kvm_mmu_slot_set_dirty(kvm, slot); 7318 } 7319 7320 static void vmx_flush_log_dirty(struct kvm *kvm) 7321 { 7322 kvm_flush_pml_buffers(kvm); 7323 } 7324 7325 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7326 { 7327 struct vmcs12 *vmcs12; 7328 struct vcpu_vmx *vmx = to_vmx(vcpu); 7329 gpa_t gpa, dst; 7330 7331 if (is_guest_mode(vcpu)) { 7332 WARN_ON_ONCE(vmx->nested.pml_full); 7333 7334 /* 7335 * Check if PML is enabled for the nested guest. 7336 * Whether eptp bit 6 is set is already checked 7337 * as part of A/D emulation. 7338 */ 7339 vmcs12 = get_vmcs12(vcpu); 7340 if (!nested_cpu_has_pml(vmcs12)) 7341 return 0; 7342 7343 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7344 vmx->nested.pml_full = true; 7345 return 1; 7346 } 7347 7348 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7349 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7350 7351 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7352 offset_in_page(dst), sizeof(gpa))) 7353 return 0; 7354 7355 vmcs12->guest_pml_index--; 7356 } 7357 7358 return 0; 7359 } 7360 7361 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7362 struct kvm_memory_slot *memslot, 7363 gfn_t offset, unsigned long mask) 7364 { 7365 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7366 } 7367 7368 static void __pi_post_block(struct kvm_vcpu *vcpu) 7369 { 7370 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7371 struct pi_desc old, new; 7372 unsigned int dest; 7373 7374 do { 7375 old.control = new.control = pi_desc->control; 7376 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7377 "Wakeup handler not enabled while the VCPU is blocked\n"); 7378 7379 dest = cpu_physical_id(vcpu->cpu); 7380 7381 if (x2apic_enabled()) 7382 new.ndst = dest; 7383 else 7384 new.ndst = (dest << 8) & 0xFF00; 7385 7386 /* set 'NV' to 'notification vector' */ 7387 new.nv = POSTED_INTR_VECTOR; 7388 } while (cmpxchg64(&pi_desc->control, old.control, 7389 new.control) != old.control); 7390 7391 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7392 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7393 list_del(&vcpu->blocked_vcpu_list); 7394 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7395 vcpu->pre_pcpu = -1; 7396 } 7397 } 7398 7399 /* 7400 * This routine does the following things for vCPU which is going 7401 * to be blocked if VT-d PI is enabled. 7402 * - Store the vCPU to the wakeup list, so when interrupts happen 7403 * we can find the right vCPU to wake up. 7404 * - Change the Posted-interrupt descriptor as below: 7405 * 'NDST' <-- vcpu->pre_pcpu 7406 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7407 * - If 'ON' is set during this process, which means at least one 7408 * interrupt is posted for this vCPU, we cannot block it, in 7409 * this case, return 1, otherwise, return 0. 7410 * 7411 */ 7412 static int pi_pre_block(struct kvm_vcpu *vcpu) 7413 { 7414 unsigned int dest; 7415 struct pi_desc old, new; 7416 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7417 7418 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7419 !irq_remapping_cap(IRQ_POSTING_CAP) || 7420 !kvm_vcpu_apicv_active(vcpu)) 7421 return 0; 7422 7423 WARN_ON(irqs_disabled()); 7424 local_irq_disable(); 7425 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7426 vcpu->pre_pcpu = vcpu->cpu; 7427 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7428 list_add_tail(&vcpu->blocked_vcpu_list, 7429 &per_cpu(blocked_vcpu_on_cpu, 7430 vcpu->pre_pcpu)); 7431 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7432 } 7433 7434 do { 7435 old.control = new.control = pi_desc->control; 7436 7437 WARN((pi_desc->sn == 1), 7438 "Warning: SN field of posted-interrupts " 7439 "is set before blocking\n"); 7440 7441 /* 7442 * Since vCPU can be preempted during this process, 7443 * vcpu->cpu could be different with pre_pcpu, we 7444 * need to set pre_pcpu as the destination of wakeup 7445 * notification event, then we can find the right vCPU 7446 * to wakeup in wakeup handler if interrupts happen 7447 * when the vCPU is in blocked state. 7448 */ 7449 dest = cpu_physical_id(vcpu->pre_pcpu); 7450 7451 if (x2apic_enabled()) 7452 new.ndst = dest; 7453 else 7454 new.ndst = (dest << 8) & 0xFF00; 7455 7456 /* set 'NV' to 'wakeup vector' */ 7457 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7458 } while (cmpxchg64(&pi_desc->control, old.control, 7459 new.control) != old.control); 7460 7461 /* We should not block the vCPU if an interrupt is posted for it. */ 7462 if (pi_test_on(pi_desc) == 1) 7463 __pi_post_block(vcpu); 7464 7465 local_irq_enable(); 7466 return (vcpu->pre_pcpu == -1); 7467 } 7468 7469 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7470 { 7471 if (pi_pre_block(vcpu)) 7472 return 1; 7473 7474 if (kvm_lapic_hv_timer_in_use(vcpu)) 7475 kvm_lapic_switch_to_sw_timer(vcpu); 7476 7477 return 0; 7478 } 7479 7480 static void pi_post_block(struct kvm_vcpu *vcpu) 7481 { 7482 if (vcpu->pre_pcpu == -1) 7483 return; 7484 7485 WARN_ON(irqs_disabled()); 7486 local_irq_disable(); 7487 __pi_post_block(vcpu); 7488 local_irq_enable(); 7489 } 7490 7491 static void vmx_post_block(struct kvm_vcpu *vcpu) 7492 { 7493 if (kvm_x86_ops->set_hv_timer) 7494 kvm_lapic_switch_to_hv_timer(vcpu); 7495 7496 pi_post_block(vcpu); 7497 } 7498 7499 /* 7500 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7501 * 7502 * @kvm: kvm 7503 * @host_irq: host irq of the interrupt 7504 * @guest_irq: gsi of the interrupt 7505 * @set: set or unset PI 7506 * returns 0 on success, < 0 on failure 7507 */ 7508 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7509 uint32_t guest_irq, bool set) 7510 { 7511 struct kvm_kernel_irq_routing_entry *e; 7512 struct kvm_irq_routing_table *irq_rt; 7513 struct kvm_lapic_irq irq; 7514 struct kvm_vcpu *vcpu; 7515 struct vcpu_data vcpu_info; 7516 int idx, ret = 0; 7517 7518 if (!kvm_arch_has_assigned_device(kvm) || 7519 !irq_remapping_cap(IRQ_POSTING_CAP) || 7520 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7521 return 0; 7522 7523 idx = srcu_read_lock(&kvm->irq_srcu); 7524 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7525 if (guest_irq >= irq_rt->nr_rt_entries || 7526 hlist_empty(&irq_rt->map[guest_irq])) { 7527 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7528 guest_irq, irq_rt->nr_rt_entries); 7529 goto out; 7530 } 7531 7532 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7533 if (e->type != KVM_IRQ_ROUTING_MSI) 7534 continue; 7535 /* 7536 * VT-d PI cannot support posting multicast/broadcast 7537 * interrupts to a vCPU, we still use interrupt remapping 7538 * for these kind of interrupts. 7539 * 7540 * For lowest-priority interrupts, we only support 7541 * those with single CPU as the destination, e.g. user 7542 * configures the interrupts via /proc/irq or uses 7543 * irqbalance to make the interrupts single-CPU. 7544 * 7545 * We will support full lowest-priority interrupt later. 7546 * 7547 * In addition, we can only inject generic interrupts using 7548 * the PI mechanism, refuse to route others through it. 7549 */ 7550 7551 kvm_set_msi_irq(kvm, e, &irq); 7552 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7553 !kvm_irq_is_postable(&irq)) { 7554 /* 7555 * Make sure the IRTE is in remapped mode if 7556 * we don't handle it in posted mode. 7557 */ 7558 ret = irq_set_vcpu_affinity(host_irq, NULL); 7559 if (ret < 0) { 7560 printk(KERN_INFO 7561 "failed to back to remapped mode, irq: %u\n", 7562 host_irq); 7563 goto out; 7564 } 7565 7566 continue; 7567 } 7568 7569 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7570 vcpu_info.vector = irq.vector; 7571 7572 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7573 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7574 7575 if (set) 7576 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7577 else 7578 ret = irq_set_vcpu_affinity(host_irq, NULL); 7579 7580 if (ret < 0) { 7581 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7582 __func__); 7583 goto out; 7584 } 7585 } 7586 7587 ret = 0; 7588 out: 7589 srcu_read_unlock(&kvm->irq_srcu, idx); 7590 return ret; 7591 } 7592 7593 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7594 { 7595 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7596 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7597 FEAT_CTL_LMCE_ENABLED; 7598 else 7599 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7600 ~FEAT_CTL_LMCE_ENABLED; 7601 } 7602 7603 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7604 { 7605 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7606 if (to_vmx(vcpu)->nested.nested_run_pending) 7607 return 0; 7608 return 1; 7609 } 7610 7611 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7612 { 7613 struct vcpu_vmx *vmx = to_vmx(vcpu); 7614 7615 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7616 if (vmx->nested.smm.guest_mode) 7617 nested_vmx_vmexit(vcpu, -1, 0, 0); 7618 7619 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7620 vmx->nested.vmxon = false; 7621 vmx_clear_hlt(vcpu); 7622 return 0; 7623 } 7624 7625 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7626 { 7627 struct vcpu_vmx *vmx = to_vmx(vcpu); 7628 int ret; 7629 7630 if (vmx->nested.smm.vmxon) { 7631 vmx->nested.vmxon = true; 7632 vmx->nested.smm.vmxon = false; 7633 } 7634 7635 if (vmx->nested.smm.guest_mode) { 7636 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7637 if (ret) 7638 return ret; 7639 7640 vmx->nested.smm.guest_mode = false; 7641 } 7642 return 0; 7643 } 7644 7645 static int enable_smi_window(struct kvm_vcpu *vcpu) 7646 { 7647 return 0; 7648 } 7649 7650 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7651 { 7652 return false; 7653 } 7654 7655 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7656 { 7657 return to_vmx(vcpu)->nested.vmxon; 7658 } 7659 7660 static __init int hardware_setup(void) 7661 { 7662 unsigned long host_bndcfgs; 7663 struct desc_ptr dt; 7664 int r, i; 7665 7666 rdmsrl_safe(MSR_EFER, &host_efer); 7667 7668 store_idt(&dt); 7669 host_idt_base = dt.address; 7670 7671 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7672 kvm_define_shared_msr(i, vmx_msr_index[i]); 7673 7674 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7675 return -EIO; 7676 7677 if (boot_cpu_has(X86_FEATURE_NX)) 7678 kvm_enable_efer_bits(EFER_NX); 7679 7680 if (boot_cpu_has(X86_FEATURE_MPX)) { 7681 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7682 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7683 } 7684 7685 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7686 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7687 enable_vpid = 0; 7688 7689 if (!cpu_has_vmx_ept() || 7690 !cpu_has_vmx_ept_4levels() || 7691 !cpu_has_vmx_ept_mt_wb() || 7692 !cpu_has_vmx_invept_global()) 7693 enable_ept = 0; 7694 7695 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7696 enable_ept_ad_bits = 0; 7697 7698 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7699 enable_unrestricted_guest = 0; 7700 7701 if (!cpu_has_vmx_flexpriority()) 7702 flexpriority_enabled = 0; 7703 7704 if (!cpu_has_virtual_nmis()) 7705 enable_vnmi = 0; 7706 7707 /* 7708 * set_apic_access_page_addr() is used to reload apic access 7709 * page upon invalidation. No need to do anything if not 7710 * using the APIC_ACCESS_ADDR VMCS field. 7711 */ 7712 if (!flexpriority_enabled) 7713 kvm_x86_ops->set_apic_access_page_addr = NULL; 7714 7715 if (!cpu_has_vmx_tpr_shadow()) 7716 kvm_x86_ops->update_cr8_intercept = NULL; 7717 7718 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7719 kvm_disable_largepages(); 7720 7721 #if IS_ENABLED(CONFIG_HYPERV) 7722 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7723 && enable_ept) { 7724 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7725 kvm_x86_ops->tlb_remote_flush_with_range = 7726 hv_remote_flush_tlb_with_range; 7727 } 7728 #endif 7729 7730 if (!cpu_has_vmx_ple()) { 7731 ple_gap = 0; 7732 ple_window = 0; 7733 ple_window_grow = 0; 7734 ple_window_max = 0; 7735 ple_window_shrink = 0; 7736 } 7737 7738 if (!cpu_has_vmx_apicv()) { 7739 enable_apicv = 0; 7740 kvm_x86_ops->sync_pir_to_irr = NULL; 7741 } 7742 7743 if (cpu_has_vmx_tsc_scaling()) { 7744 kvm_has_tsc_control = true; 7745 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7746 kvm_tsc_scaling_ratio_frac_bits = 48; 7747 } 7748 7749 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7750 7751 if (enable_ept) 7752 vmx_enable_tdp(); 7753 else 7754 kvm_disable_tdp(); 7755 7756 /* 7757 * Only enable PML when hardware supports PML feature, and both EPT 7758 * and EPT A/D bit features are enabled -- PML depends on them to work. 7759 */ 7760 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7761 enable_pml = 0; 7762 7763 if (!enable_pml) { 7764 kvm_x86_ops->slot_enable_log_dirty = NULL; 7765 kvm_x86_ops->slot_disable_log_dirty = NULL; 7766 kvm_x86_ops->flush_log_dirty = NULL; 7767 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7768 } 7769 7770 if (!cpu_has_vmx_preemption_timer()) 7771 enable_preemption_timer = false; 7772 7773 if (enable_preemption_timer) { 7774 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7775 u64 vmx_msr; 7776 7777 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7778 cpu_preemption_timer_multi = 7779 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7780 7781 if (tsc_khz) 7782 use_timer_freq = (u64)tsc_khz * 1000; 7783 use_timer_freq >>= cpu_preemption_timer_multi; 7784 7785 /* 7786 * KVM "disables" the preemption timer by setting it to its max 7787 * value. Don't use the timer if it might cause spurious exits 7788 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7789 */ 7790 if (use_timer_freq > 0xffffffffu / 10) 7791 enable_preemption_timer = false; 7792 } 7793 7794 if (!enable_preemption_timer) { 7795 kvm_x86_ops->set_hv_timer = NULL; 7796 kvm_x86_ops->cancel_hv_timer = NULL; 7797 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7798 } 7799 7800 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7801 7802 kvm_mce_cap_supported |= MCG_LMCE_P; 7803 7804 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7805 return -EINVAL; 7806 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7807 pt_mode = PT_MODE_SYSTEM; 7808 7809 if (nested) { 7810 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7811 vmx_capability.ept); 7812 7813 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7814 if (r) 7815 return r; 7816 } 7817 7818 r = alloc_kvm_area(); 7819 if (r) 7820 nested_vmx_hardware_unsetup(); 7821 return r; 7822 } 7823 7824 static __exit void hardware_unsetup(void) 7825 { 7826 if (nested) 7827 nested_vmx_hardware_unsetup(); 7828 7829 free_kvm_area(); 7830 } 7831 7832 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7833 { 7834 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7835 BIT(APICV_INHIBIT_REASON_HYPERV); 7836 7837 return supported & BIT(bit); 7838 } 7839 7840 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7841 .cpu_has_kvm_support = cpu_has_kvm_support, 7842 .disabled_by_bios = vmx_disabled_by_bios, 7843 .hardware_setup = hardware_setup, 7844 .hardware_unsetup = hardware_unsetup, 7845 .check_processor_compatibility = vmx_check_processor_compat, 7846 .hardware_enable = hardware_enable, 7847 .hardware_disable = hardware_disable, 7848 .cpu_has_accelerated_tpr = report_flexpriority, 7849 .has_emulated_msr = vmx_has_emulated_msr, 7850 7851 .vm_init = vmx_vm_init, 7852 .vm_alloc = vmx_vm_alloc, 7853 .vm_free = vmx_vm_free, 7854 7855 .vcpu_create = vmx_create_vcpu, 7856 .vcpu_free = vmx_free_vcpu, 7857 .vcpu_reset = vmx_vcpu_reset, 7858 7859 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7860 .vcpu_load = vmx_vcpu_load, 7861 .vcpu_put = vmx_vcpu_put, 7862 7863 .update_bp_intercept = update_exception_bitmap, 7864 .get_msr_feature = vmx_get_msr_feature, 7865 .get_msr = vmx_get_msr, 7866 .set_msr = vmx_set_msr, 7867 .get_segment_base = vmx_get_segment_base, 7868 .get_segment = vmx_get_segment, 7869 .set_segment = vmx_set_segment, 7870 .get_cpl = vmx_get_cpl, 7871 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7872 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7873 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7874 .set_cr0 = vmx_set_cr0, 7875 .set_cr3 = vmx_set_cr3, 7876 .set_cr4 = vmx_set_cr4, 7877 .set_efer = vmx_set_efer, 7878 .get_idt = vmx_get_idt, 7879 .set_idt = vmx_set_idt, 7880 .get_gdt = vmx_get_gdt, 7881 .set_gdt = vmx_set_gdt, 7882 .get_dr6 = vmx_get_dr6, 7883 .set_dr6 = vmx_set_dr6, 7884 .set_dr7 = vmx_set_dr7, 7885 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7886 .cache_reg = vmx_cache_reg, 7887 .get_rflags = vmx_get_rflags, 7888 .set_rflags = vmx_set_rflags, 7889 7890 .tlb_flush = vmx_flush_tlb, 7891 .tlb_flush_gva = vmx_flush_tlb_gva, 7892 7893 .run = vmx_vcpu_run, 7894 .handle_exit = vmx_handle_exit, 7895 .skip_emulated_instruction = vmx_skip_emulated_instruction, 7896 .update_emulated_instruction = vmx_update_emulated_instruction, 7897 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7898 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7899 .patch_hypercall = vmx_patch_hypercall, 7900 .set_irq = vmx_inject_irq, 7901 .set_nmi = vmx_inject_nmi, 7902 .queue_exception = vmx_queue_exception, 7903 .cancel_injection = vmx_cancel_injection, 7904 .interrupt_allowed = vmx_interrupt_allowed, 7905 .nmi_allowed = vmx_nmi_allowed, 7906 .get_nmi_mask = vmx_get_nmi_mask, 7907 .set_nmi_mask = vmx_set_nmi_mask, 7908 .enable_nmi_window = enable_nmi_window, 7909 .enable_irq_window = enable_irq_window, 7910 .update_cr8_intercept = update_cr8_intercept, 7911 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7912 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7913 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7914 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7915 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7916 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7917 .hwapic_irr_update = vmx_hwapic_irr_update, 7918 .hwapic_isr_update = vmx_hwapic_isr_update, 7919 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7920 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7921 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7922 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7923 7924 .set_tss_addr = vmx_set_tss_addr, 7925 .set_identity_map_addr = vmx_set_identity_map_addr, 7926 .get_tdp_level = get_ept_level, 7927 .get_mt_mask = vmx_get_mt_mask, 7928 7929 .get_exit_info = vmx_get_exit_info, 7930 7931 .get_lpage_level = vmx_get_lpage_level, 7932 7933 .cpuid_update = vmx_cpuid_update, 7934 7935 .rdtscp_supported = vmx_rdtscp_supported, 7936 .invpcid_supported = vmx_invpcid_supported, 7937 7938 .set_supported_cpuid = vmx_set_supported_cpuid, 7939 7940 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7941 7942 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7943 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7944 7945 .set_tdp_cr3 = vmx_set_cr3, 7946 7947 .check_intercept = vmx_check_intercept, 7948 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7949 .mpx_supported = vmx_mpx_supported, 7950 .xsaves_supported = vmx_xsaves_supported, 7951 .umip_emulated = vmx_umip_emulated, 7952 .pt_supported = vmx_pt_supported, 7953 .pku_supported = vmx_pku_supported, 7954 7955 .request_immediate_exit = vmx_request_immediate_exit, 7956 7957 .sched_in = vmx_sched_in, 7958 7959 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7960 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7961 .flush_log_dirty = vmx_flush_log_dirty, 7962 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7963 .write_log_dirty = vmx_write_pml_buffer, 7964 7965 .pre_block = vmx_pre_block, 7966 .post_block = vmx_post_block, 7967 7968 .pmu_ops = &intel_pmu_ops, 7969 7970 .update_pi_irte = vmx_update_pi_irte, 7971 7972 #ifdef CONFIG_X86_64 7973 .set_hv_timer = vmx_set_hv_timer, 7974 .cancel_hv_timer = vmx_cancel_hv_timer, 7975 #endif 7976 7977 .setup_mce = vmx_setup_mce, 7978 7979 .smi_allowed = vmx_smi_allowed, 7980 .pre_enter_smm = vmx_pre_enter_smm, 7981 .pre_leave_smm = vmx_pre_leave_smm, 7982 .enable_smi_window = enable_smi_window, 7983 7984 .check_nested_events = NULL, 7985 .get_nested_state = NULL, 7986 .set_nested_state = NULL, 7987 .get_vmcs12_pages = NULL, 7988 .nested_enable_evmcs = NULL, 7989 .nested_get_evmcs_version = NULL, 7990 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7991 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7992 }; 7993 7994 static void vmx_cleanup_l1d_flush(void) 7995 { 7996 if (vmx_l1d_flush_pages) { 7997 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7998 vmx_l1d_flush_pages = NULL; 7999 } 8000 /* Restore state so sysfs ignores VMX */ 8001 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 8002 } 8003 8004 static void vmx_exit(void) 8005 { 8006 #ifdef CONFIG_KEXEC_CORE 8007 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 8008 synchronize_rcu(); 8009 #endif 8010 8011 kvm_exit(); 8012 8013 #if IS_ENABLED(CONFIG_HYPERV) 8014 if (static_branch_unlikely(&enable_evmcs)) { 8015 int cpu; 8016 struct hv_vp_assist_page *vp_ap; 8017 /* 8018 * Reset everything to support using non-enlightened VMCS 8019 * access later (e.g. when we reload the module with 8020 * enlightened_vmcs=0) 8021 */ 8022 for_each_online_cpu(cpu) { 8023 vp_ap = hv_get_vp_assist_page(cpu); 8024 8025 if (!vp_ap) 8026 continue; 8027 8028 vp_ap->nested_control.features.directhypercall = 0; 8029 vp_ap->current_nested_vmcs = 0; 8030 vp_ap->enlighten_vmentry = 0; 8031 } 8032 8033 static_branch_disable(&enable_evmcs); 8034 } 8035 #endif 8036 vmx_cleanup_l1d_flush(); 8037 } 8038 module_exit(vmx_exit); 8039 8040 static int __init vmx_init(void) 8041 { 8042 int r; 8043 8044 #if IS_ENABLED(CONFIG_HYPERV) 8045 /* 8046 * Enlightened VMCS usage should be recommended and the host needs 8047 * to support eVMCS v1 or above. We can also disable eVMCS support 8048 * with module parameter. 8049 */ 8050 if (enlightened_vmcs && 8051 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 8052 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 8053 KVM_EVMCS_VERSION) { 8054 int cpu; 8055 8056 /* Check that we have assist pages on all online CPUs */ 8057 for_each_online_cpu(cpu) { 8058 if (!hv_get_vp_assist_page(cpu)) { 8059 enlightened_vmcs = false; 8060 break; 8061 } 8062 } 8063 8064 if (enlightened_vmcs) { 8065 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 8066 static_branch_enable(&enable_evmcs); 8067 } 8068 8069 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 8070 vmx_x86_ops.enable_direct_tlbflush 8071 = hv_enable_direct_tlbflush; 8072 8073 } else { 8074 enlightened_vmcs = false; 8075 } 8076 #endif 8077 8078 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 8079 __alignof__(struct vcpu_vmx), THIS_MODULE); 8080 if (r) 8081 return r; 8082 8083 /* 8084 * Must be called after kvm_init() so enable_ept is properly set 8085 * up. Hand the parameter mitigation value in which was stored in 8086 * the pre module init parser. If no parameter was given, it will 8087 * contain 'auto' which will be turned into the default 'cond' 8088 * mitigation mode. 8089 */ 8090 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 8091 if (r) { 8092 vmx_exit(); 8093 return r; 8094 } 8095 8096 #ifdef CONFIG_KEXEC_CORE 8097 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 8098 crash_vmclear_local_loaded_vmcss); 8099 #endif 8100 vmx_check_vmcs12_offsets(); 8101 8102 return 0; 8103 } 8104 module_init(vmx_init); 8105