1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/debugreg.h> 36 #include <asm/desc.h> 37 #include <asm/fpu/internal.h> 38 #include <asm/io.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/kexec.h> 41 #include <asm/perf_event.h> 42 #include <asm/mce.h> 43 #include <asm/mmu_context.h> 44 #include <asm/mshyperv.h> 45 #include <asm/mwait.h> 46 #include <asm/spec-ctrl.h> 47 #include <asm/virtext.h> 48 #include <asm/vmx.h> 49 50 #include "capabilities.h" 51 #include "cpuid.h" 52 #include "evmcs.h" 53 #include "irq.h" 54 #include "kvm_cache_regs.h" 55 #include "lapic.h" 56 #include "mmu.h" 57 #include "nested.h" 58 #include "ops.h" 59 #include "pmu.h" 60 #include "trace.h" 61 #include "vmcs.h" 62 #include "vmcs12.h" 63 #include "vmx.h" 64 #include "x86.h" 65 66 MODULE_AUTHOR("Qumranet"); 67 MODULE_LICENSE("GPL"); 68 69 #ifdef MODULE 70 static const struct x86_cpu_id vmx_cpu_id[] = { 71 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL), 72 {} 73 }; 74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 75 #endif 76 77 bool __read_mostly enable_vpid = 1; 78 module_param_named(vpid, enable_vpid, bool, 0444); 79 80 static bool __read_mostly enable_vnmi = 1; 81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 82 83 bool __read_mostly flexpriority_enabled = 1; 84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 85 86 bool __read_mostly enable_ept = 1; 87 module_param_named(ept, enable_ept, bool, S_IRUGO); 88 89 bool __read_mostly enable_unrestricted_guest = 1; 90 module_param_named(unrestricted_guest, 91 enable_unrestricted_guest, bool, S_IRUGO); 92 93 bool __read_mostly enable_ept_ad_bits = 1; 94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 95 96 static bool __read_mostly emulate_invalid_guest_state = true; 97 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 98 99 static bool __read_mostly fasteoi = 1; 100 module_param(fasteoi, bool, S_IRUGO); 101 102 bool __read_mostly enable_apicv = 1; 103 module_param(enable_apicv, bool, S_IRUGO); 104 105 /* 106 * If nested=1, nested virtualization is supported, i.e., guests may use 107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 108 * use VMX instructions. 109 */ 110 static bool __read_mostly nested = 1; 111 module_param(nested, bool, S_IRUGO); 112 113 bool __read_mostly enable_pml = 1; 114 module_param_named(pml, enable_pml, bool, S_IRUGO); 115 116 static bool __read_mostly dump_invalid_vmcs = 0; 117 module_param(dump_invalid_vmcs, bool, 0644); 118 119 #define MSR_BITMAP_MODE_X2APIC 1 120 #define MSR_BITMAP_MODE_X2APIC_APICV 2 121 122 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 123 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 125 static int __read_mostly cpu_preemption_timer_multi; 126 static bool __read_mostly enable_preemption_timer = 1; 127 #ifdef CONFIG_X86_64 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 129 #endif 130 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 133 #define KVM_VM_CR0_ALWAYS_ON \ 134 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 135 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 136 #define KVM_CR4_GUEST_OWNED_BITS \ 137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 138 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 139 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 143 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 145 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 147 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 148 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 149 RTIT_STATUS_BYTECNT)) 150 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 152 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 153 154 /* 155 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 156 * ple_gap: upper bound on the amount of time between two successive 157 * executions of PAUSE in a loop. Also indicate if ple enabled. 158 * According to test, this time is usually smaller than 128 cycles. 159 * ple_window: upper bound on the amount of time a guest is allowed to execute 160 * in a PAUSE loop. Tests indicate that most spinlocks are held for 161 * less than 2^12 cycles 162 * Time is measured based on a counter that runs at the same rate as the TSC, 163 * refer SDM volume 3b section 21.6.13 & 22.1.3. 164 */ 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 166 module_param(ple_gap, uint, 0444); 167 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 169 module_param(ple_window, uint, 0444); 170 171 /* Default doubles per-vcpu window every exit. */ 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 173 module_param(ple_window_grow, uint, 0444); 174 175 /* Default resets per-vcpu window every exit to ple_window. */ 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 177 module_param(ple_window_shrink, uint, 0444); 178 179 /* Default is to compute the maximum so we can never overflow. */ 180 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 181 module_param(ple_window_max, uint, 0444); 182 183 /* Default is SYSTEM mode, 1 for host-guest mode */ 184 int __read_mostly pt_mode = PT_MODE_SYSTEM; 185 module_param(pt_mode, int, S_IRUGO); 186 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 190 191 /* Storage for pre module init parameter parsing */ 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 193 194 static const struct { 195 const char *option; 196 bool for_parse; 197 } vmentry_l1d_param[] = { 198 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 199 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 200 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 201 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 202 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 203 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 204 }; 205 206 #define L1D_CACHE_ORDER 4 207 static void *vmx_l1d_flush_pages; 208 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 210 { 211 struct page *page; 212 unsigned int i; 213 214 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 215 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 216 return 0; 217 } 218 219 if (!enable_ept) { 220 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 221 return 0; 222 } 223 224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 225 u64 msr; 226 227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 228 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 229 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 230 return 0; 231 } 232 } 233 234 /* If set to auto use the default l1tf mitigation method */ 235 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 236 switch (l1tf_mitigation) { 237 case L1TF_MITIGATION_OFF: 238 l1tf = VMENTER_L1D_FLUSH_NEVER; 239 break; 240 case L1TF_MITIGATION_FLUSH_NOWARN: 241 case L1TF_MITIGATION_FLUSH: 242 case L1TF_MITIGATION_FLUSH_NOSMT: 243 l1tf = VMENTER_L1D_FLUSH_COND; 244 break; 245 case L1TF_MITIGATION_FULL: 246 case L1TF_MITIGATION_FULL_FORCE: 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 break; 249 } 250 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 251 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 252 } 253 254 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 256 /* 257 * This allocation for vmx_l1d_flush_pages is not tied to a VM 258 * lifetime and so should not be charged to a memcg. 259 */ 260 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 261 if (!page) 262 return -ENOMEM; 263 vmx_l1d_flush_pages = page_address(page); 264 265 /* 266 * Initialize each page with a different pattern in 267 * order to protect against KSM in the nested 268 * virtualization case. 269 */ 270 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 271 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 272 PAGE_SIZE); 273 } 274 } 275 276 l1tf_vmx_mitigation = l1tf; 277 278 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 279 static_branch_enable(&vmx_l1d_should_flush); 280 else 281 static_branch_disable(&vmx_l1d_should_flush); 282 283 if (l1tf == VMENTER_L1D_FLUSH_COND) 284 static_branch_enable(&vmx_l1d_flush_cond); 285 else 286 static_branch_disable(&vmx_l1d_flush_cond); 287 return 0; 288 } 289 290 static int vmentry_l1d_flush_parse(const char *s) 291 { 292 unsigned int i; 293 294 if (s) { 295 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 296 if (vmentry_l1d_param[i].for_parse && 297 sysfs_streq(s, vmentry_l1d_param[i].option)) 298 return i; 299 } 300 } 301 return -EINVAL; 302 } 303 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 305 { 306 int l1tf, ret; 307 308 l1tf = vmentry_l1d_flush_parse(s); 309 if (l1tf < 0) 310 return l1tf; 311 312 if (!boot_cpu_has(X86_BUG_L1TF)) 313 return 0; 314 315 /* 316 * Has vmx_init() run already? If not then this is the pre init 317 * parameter parsing. In that case just store the value and let 318 * vmx_init() do the proper setup after enable_ept has been 319 * established. 320 */ 321 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 322 vmentry_l1d_flush_param = l1tf; 323 return 0; 324 } 325 326 mutex_lock(&vmx_l1d_flush_mutex); 327 ret = vmx_setup_l1d_flush(l1tf); 328 mutex_unlock(&vmx_l1d_flush_mutex); 329 return ret; 330 } 331 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 333 { 334 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 335 return sprintf(s, "???\n"); 336 337 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 338 } 339 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 341 .set = vmentry_l1d_flush_set, 342 .get = vmentry_l1d_flush_get, 343 }; 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 345 346 static bool guest_state_valid(struct kvm_vcpu *vcpu); 347 static u32 vmx_segment_access_rights(struct kvm_segment *var); 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 349 u32 msr, int type); 350 351 void vmx_vmexit(void); 352 353 #define vmx_insn_failed(fmt...) \ 354 do { \ 355 WARN_ONCE(1, fmt); \ 356 pr_warn_ratelimited(fmt); \ 357 } while (0) 358 359 asmlinkage void vmread_error(unsigned long field, bool fault) 360 { 361 if (fault) 362 kvm_spurious_fault(); 363 else 364 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 365 } 366 367 noinline void vmwrite_error(unsigned long field, unsigned long value) 368 { 369 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 370 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 371 } 372 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 374 { 375 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 376 } 377 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 379 { 380 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 381 } 382 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 384 { 385 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 386 ext, vpid, gva); 387 } 388 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 390 { 391 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 392 ext, eptp, gpa); 393 } 394 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 397 /* 398 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 399 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 400 */ 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 402 403 /* 404 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 405 * can find which vCPU should be waken up. 406 */ 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 409 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 411 static DEFINE_SPINLOCK(vmx_vpid_lock); 412 413 struct vmcs_config vmcs_config; 414 struct vmx_capability vmx_capability; 415 416 #define VMX_SEGMENT_FIELD(seg) \ 417 [VCPU_SREG_##seg] = { \ 418 .selector = GUEST_##seg##_SELECTOR, \ 419 .base = GUEST_##seg##_BASE, \ 420 .limit = GUEST_##seg##_LIMIT, \ 421 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 422 } 423 424 static const struct kvm_vmx_segment_field { 425 unsigned selector; 426 unsigned base; 427 unsigned limit; 428 unsigned ar_bytes; 429 } kvm_vmx_segment_fields[] = { 430 VMX_SEGMENT_FIELD(CS), 431 VMX_SEGMENT_FIELD(DS), 432 VMX_SEGMENT_FIELD(ES), 433 VMX_SEGMENT_FIELD(FS), 434 VMX_SEGMENT_FIELD(GS), 435 VMX_SEGMENT_FIELD(SS), 436 VMX_SEGMENT_FIELD(TR), 437 VMX_SEGMENT_FIELD(LDTR), 438 }; 439 440 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 441 { 442 vmx->segment_cache.bitmask = 0; 443 } 444 445 static unsigned long host_idt_base; 446 447 /* 448 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 449 * will emulate SYSCALL in legacy mode if the vendor string in guest 450 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 451 * support this emulation, IA32_STAR must always be included in 452 * vmx_msr_index[], even in i386 builds. 453 */ 454 const u32 vmx_msr_index[] = { 455 #ifdef CONFIG_X86_64 456 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 457 #endif 458 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 459 MSR_IA32_TSX_CTRL, 460 }; 461 462 #if IS_ENABLED(CONFIG_HYPERV) 463 static bool __read_mostly enlightened_vmcs = true; 464 module_param(enlightened_vmcs, bool, 0444); 465 466 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 467 static void check_ept_pointer_match(struct kvm *kvm) 468 { 469 struct kvm_vcpu *vcpu; 470 u64 tmp_eptp = INVALID_PAGE; 471 int i; 472 473 kvm_for_each_vcpu(i, vcpu, kvm) { 474 if (!VALID_PAGE(tmp_eptp)) { 475 tmp_eptp = to_vmx(vcpu)->ept_pointer; 476 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 477 to_kvm_vmx(kvm)->ept_pointers_match 478 = EPT_POINTERS_MISMATCH; 479 return; 480 } 481 } 482 483 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 484 } 485 486 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 487 void *data) 488 { 489 struct kvm_tlb_range *range = data; 490 491 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 492 range->pages); 493 } 494 495 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 496 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 497 { 498 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 499 500 /* 501 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 502 * of the base of EPT PML4 table, strip off EPT configuration 503 * information. 504 */ 505 if (range) 506 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 507 kvm_fill_hv_flush_list_func, (void *)range); 508 else 509 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 510 } 511 512 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 513 struct kvm_tlb_range *range) 514 { 515 struct kvm_vcpu *vcpu; 516 int ret = 0, i; 517 518 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 519 520 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 521 check_ept_pointer_match(kvm); 522 523 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 524 kvm_for_each_vcpu(i, vcpu, kvm) { 525 /* If ept_pointer is invalid pointer, bypass flush request. */ 526 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 527 ret |= __hv_remote_flush_tlb_with_range( 528 kvm, vcpu, range); 529 } 530 } else { 531 ret = __hv_remote_flush_tlb_with_range(kvm, 532 kvm_get_vcpu(kvm, 0), range); 533 } 534 535 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 536 return ret; 537 } 538 static int hv_remote_flush_tlb(struct kvm *kvm) 539 { 540 return hv_remote_flush_tlb_with_range(kvm, NULL); 541 } 542 543 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 544 { 545 struct hv_enlightened_vmcs *evmcs; 546 struct hv_partition_assist_pg **p_hv_pa_pg = 547 &vcpu->kvm->arch.hyperv.hv_pa_pg; 548 /* 549 * Synthetic VM-Exit is not enabled in current code and so All 550 * evmcs in singe VM shares same assist page. 551 */ 552 if (!*p_hv_pa_pg) 553 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 554 555 if (!*p_hv_pa_pg) 556 return -ENOMEM; 557 558 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 559 560 evmcs->partition_assist_page = 561 __pa(*p_hv_pa_pg); 562 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 563 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 564 565 return 0; 566 } 567 568 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 569 570 /* 571 * Comment's format: document - errata name - stepping - processor name. 572 * Refer from 573 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 574 */ 575 static u32 vmx_preemption_cpu_tfms[] = { 576 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 577 0x000206E6, 578 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 579 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 580 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 581 0x00020652, 582 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 583 0x00020655, 584 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 585 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 586 /* 587 * 320767.pdf - AAP86 - B1 - 588 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 589 */ 590 0x000106E5, 591 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 592 0x000106A0, 593 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 594 0x000106A1, 595 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 596 0x000106A4, 597 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 598 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 599 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 600 0x000106A5, 601 /* Xeon E3-1220 V2 */ 602 0x000306A8, 603 }; 604 605 static inline bool cpu_has_broken_vmx_preemption_timer(void) 606 { 607 u32 eax = cpuid_eax(0x00000001), i; 608 609 /* Clear the reserved bits */ 610 eax &= ~(0x3U << 14 | 0xfU << 28); 611 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 612 if (eax == vmx_preemption_cpu_tfms[i]) 613 return true; 614 615 return false; 616 } 617 618 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 619 { 620 return flexpriority_enabled && lapic_in_kernel(vcpu); 621 } 622 623 static inline bool report_flexpriority(void) 624 { 625 return flexpriority_enabled; 626 } 627 628 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 629 { 630 int i; 631 632 for (i = 0; i < vmx->nmsrs; ++i) 633 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 634 return i; 635 return -1; 636 } 637 638 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 639 { 640 int i; 641 642 i = __find_msr_index(vmx, msr); 643 if (i >= 0) 644 return &vmx->guest_msrs[i]; 645 return NULL; 646 } 647 648 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 649 { 650 int ret = 0; 651 652 u64 old_msr_data = msr->data; 653 msr->data = data; 654 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 655 preempt_disable(); 656 ret = kvm_set_shared_msr(msr->index, msr->data, 657 msr->mask); 658 preempt_enable(); 659 if (ret) 660 msr->data = old_msr_data; 661 } 662 return ret; 663 } 664 665 #ifdef CONFIG_KEXEC_CORE 666 static void crash_vmclear_local_loaded_vmcss(void) 667 { 668 int cpu = raw_smp_processor_id(); 669 struct loaded_vmcs *v; 670 671 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 672 loaded_vmcss_on_cpu_link) 673 vmcs_clear(v->vmcs); 674 } 675 #endif /* CONFIG_KEXEC_CORE */ 676 677 static void __loaded_vmcs_clear(void *arg) 678 { 679 struct loaded_vmcs *loaded_vmcs = arg; 680 int cpu = raw_smp_processor_id(); 681 682 if (loaded_vmcs->cpu != cpu) 683 return; /* vcpu migration can race with cpu offline */ 684 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 685 per_cpu(current_vmcs, cpu) = NULL; 686 687 vmcs_clear(loaded_vmcs->vmcs); 688 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 689 vmcs_clear(loaded_vmcs->shadow_vmcs); 690 691 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 692 693 /* 694 * Ensure all writes to loaded_vmcs, including deleting it from its 695 * current percpu list, complete before setting loaded_vmcs->vcpu to 696 * -1, otherwise a different cpu can see vcpu == -1 first and add 697 * loaded_vmcs to its percpu list before it's deleted from this cpu's 698 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs(). 699 */ 700 smp_wmb(); 701 702 loaded_vmcs->cpu = -1; 703 loaded_vmcs->launched = 0; 704 } 705 706 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 707 { 708 int cpu = loaded_vmcs->cpu; 709 710 if (cpu != -1) 711 smp_call_function_single(cpu, 712 __loaded_vmcs_clear, loaded_vmcs, 1); 713 } 714 715 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 716 unsigned field) 717 { 718 bool ret; 719 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 720 721 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 722 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 723 vmx->segment_cache.bitmask = 0; 724 } 725 ret = vmx->segment_cache.bitmask & mask; 726 vmx->segment_cache.bitmask |= mask; 727 return ret; 728 } 729 730 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 731 { 732 u16 *p = &vmx->segment_cache.seg[seg].selector; 733 734 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 735 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 736 return *p; 737 } 738 739 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 740 { 741 ulong *p = &vmx->segment_cache.seg[seg].base; 742 743 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 744 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 745 return *p; 746 } 747 748 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 749 { 750 u32 *p = &vmx->segment_cache.seg[seg].limit; 751 752 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 753 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 754 return *p; 755 } 756 757 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 758 { 759 u32 *p = &vmx->segment_cache.seg[seg].ar; 760 761 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 762 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 763 return *p; 764 } 765 766 void update_exception_bitmap(struct kvm_vcpu *vcpu) 767 { 768 u32 eb; 769 770 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 771 (1u << DB_VECTOR) | (1u << AC_VECTOR); 772 /* 773 * Guest access to VMware backdoor ports could legitimately 774 * trigger #GP because of TSS I/O permission bitmap. 775 * We intercept those #GP and allow access to them anyway 776 * as VMware does. 777 */ 778 if (enable_vmware_backdoor) 779 eb |= (1u << GP_VECTOR); 780 if ((vcpu->guest_debug & 781 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 782 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 783 eb |= 1u << BP_VECTOR; 784 if (to_vmx(vcpu)->rmode.vm86_active) 785 eb = ~0; 786 if (enable_ept) 787 eb &= ~(1u << PF_VECTOR); 788 789 /* When we are running a nested L2 guest and L1 specified for it a 790 * certain exception bitmap, we must trap the same exceptions and pass 791 * them to L1. When running L2, we will only handle the exceptions 792 * specified above if L1 did not want them. 793 */ 794 if (is_guest_mode(vcpu)) 795 eb |= get_vmcs12(vcpu)->exception_bitmap; 796 797 vmcs_write32(EXCEPTION_BITMAP, eb); 798 } 799 800 /* 801 * Check if MSR is intercepted for currently loaded MSR bitmap. 802 */ 803 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 804 { 805 unsigned long *msr_bitmap; 806 int f = sizeof(unsigned long); 807 808 if (!cpu_has_vmx_msr_bitmap()) 809 return true; 810 811 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 812 813 if (msr <= 0x1fff) { 814 return !!test_bit(msr, msr_bitmap + 0x800 / f); 815 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 816 msr &= 0x1fff; 817 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 818 } 819 820 return true; 821 } 822 823 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 824 unsigned long entry, unsigned long exit) 825 { 826 vm_entry_controls_clearbit(vmx, entry); 827 vm_exit_controls_clearbit(vmx, exit); 828 } 829 830 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 831 { 832 unsigned int i; 833 834 for (i = 0; i < m->nr; ++i) { 835 if (m->val[i].index == msr) 836 return i; 837 } 838 return -ENOENT; 839 } 840 841 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 842 { 843 int i; 844 struct msr_autoload *m = &vmx->msr_autoload; 845 846 switch (msr) { 847 case MSR_EFER: 848 if (cpu_has_load_ia32_efer()) { 849 clear_atomic_switch_msr_special(vmx, 850 VM_ENTRY_LOAD_IA32_EFER, 851 VM_EXIT_LOAD_IA32_EFER); 852 return; 853 } 854 break; 855 case MSR_CORE_PERF_GLOBAL_CTRL: 856 if (cpu_has_load_perf_global_ctrl()) { 857 clear_atomic_switch_msr_special(vmx, 858 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 859 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 860 return; 861 } 862 break; 863 } 864 i = vmx_find_msr_index(&m->guest, msr); 865 if (i < 0) 866 goto skip_guest; 867 --m->guest.nr; 868 m->guest.val[i] = m->guest.val[m->guest.nr]; 869 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 870 871 skip_guest: 872 i = vmx_find_msr_index(&m->host, msr); 873 if (i < 0) 874 return; 875 876 --m->host.nr; 877 m->host.val[i] = m->host.val[m->host.nr]; 878 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 879 } 880 881 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 882 unsigned long entry, unsigned long exit, 883 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 884 u64 guest_val, u64 host_val) 885 { 886 vmcs_write64(guest_val_vmcs, guest_val); 887 if (host_val_vmcs != HOST_IA32_EFER) 888 vmcs_write64(host_val_vmcs, host_val); 889 vm_entry_controls_setbit(vmx, entry); 890 vm_exit_controls_setbit(vmx, exit); 891 } 892 893 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 894 u64 guest_val, u64 host_val, bool entry_only) 895 { 896 int i, j = 0; 897 struct msr_autoload *m = &vmx->msr_autoload; 898 899 switch (msr) { 900 case MSR_EFER: 901 if (cpu_has_load_ia32_efer()) { 902 add_atomic_switch_msr_special(vmx, 903 VM_ENTRY_LOAD_IA32_EFER, 904 VM_EXIT_LOAD_IA32_EFER, 905 GUEST_IA32_EFER, 906 HOST_IA32_EFER, 907 guest_val, host_val); 908 return; 909 } 910 break; 911 case MSR_CORE_PERF_GLOBAL_CTRL: 912 if (cpu_has_load_perf_global_ctrl()) { 913 add_atomic_switch_msr_special(vmx, 914 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 915 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 916 GUEST_IA32_PERF_GLOBAL_CTRL, 917 HOST_IA32_PERF_GLOBAL_CTRL, 918 guest_val, host_val); 919 return; 920 } 921 break; 922 case MSR_IA32_PEBS_ENABLE: 923 /* PEBS needs a quiescent period after being disabled (to write 924 * a record). Disabling PEBS through VMX MSR swapping doesn't 925 * provide that period, so a CPU could write host's record into 926 * guest's memory. 927 */ 928 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 929 } 930 931 i = vmx_find_msr_index(&m->guest, msr); 932 if (!entry_only) 933 j = vmx_find_msr_index(&m->host, msr); 934 935 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 936 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 937 printk_once(KERN_WARNING "Not enough msr switch entries. " 938 "Can't add msr %x\n", msr); 939 return; 940 } 941 if (i < 0) { 942 i = m->guest.nr++; 943 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 944 } 945 m->guest.val[i].index = msr; 946 m->guest.val[i].value = guest_val; 947 948 if (entry_only) 949 return; 950 951 if (j < 0) { 952 j = m->host.nr++; 953 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 954 } 955 m->host.val[j].index = msr; 956 m->host.val[j].value = host_val; 957 } 958 959 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 960 { 961 u64 guest_efer = vmx->vcpu.arch.efer; 962 u64 ignore_bits = 0; 963 964 /* Shadow paging assumes NX to be available. */ 965 if (!enable_ept) 966 guest_efer |= EFER_NX; 967 968 /* 969 * LMA and LME handled by hardware; SCE meaningless outside long mode. 970 */ 971 ignore_bits |= EFER_SCE; 972 #ifdef CONFIG_X86_64 973 ignore_bits |= EFER_LMA | EFER_LME; 974 /* SCE is meaningful only in long mode on Intel */ 975 if (guest_efer & EFER_LMA) 976 ignore_bits &= ~(u64)EFER_SCE; 977 #endif 978 979 /* 980 * On EPT, we can't emulate NX, so we must switch EFER atomically. 981 * On CPUs that support "load IA32_EFER", always switch EFER 982 * atomically, since it's faster than switching it manually. 983 */ 984 if (cpu_has_load_ia32_efer() || 985 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 986 if (!(guest_efer & EFER_LMA)) 987 guest_efer &= ~EFER_LME; 988 if (guest_efer != host_efer) 989 add_atomic_switch_msr(vmx, MSR_EFER, 990 guest_efer, host_efer, false); 991 else 992 clear_atomic_switch_msr(vmx, MSR_EFER); 993 return false; 994 } else { 995 clear_atomic_switch_msr(vmx, MSR_EFER); 996 997 guest_efer &= ~ignore_bits; 998 guest_efer |= host_efer & ignore_bits; 999 1000 vmx->guest_msrs[efer_offset].data = guest_efer; 1001 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1002 1003 return true; 1004 } 1005 } 1006 1007 #ifdef CONFIG_X86_32 1008 /* 1009 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1010 * VMCS rather than the segment table. KVM uses this helper to figure 1011 * out the current bases to poke them into the VMCS before entry. 1012 */ 1013 static unsigned long segment_base(u16 selector) 1014 { 1015 struct desc_struct *table; 1016 unsigned long v; 1017 1018 if (!(selector & ~SEGMENT_RPL_MASK)) 1019 return 0; 1020 1021 table = get_current_gdt_ro(); 1022 1023 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1024 u16 ldt_selector = kvm_read_ldt(); 1025 1026 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1027 return 0; 1028 1029 table = (struct desc_struct *)segment_base(ldt_selector); 1030 } 1031 v = get_desc_base(&table[selector >> 3]); 1032 return v; 1033 } 1034 #endif 1035 1036 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1037 { 1038 return vmx_pt_mode_is_host_guest() && 1039 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1040 } 1041 1042 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1043 { 1044 u32 i; 1045 1046 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1047 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1048 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1049 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1050 for (i = 0; i < addr_range; i++) { 1051 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1052 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1053 } 1054 } 1055 1056 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1057 { 1058 u32 i; 1059 1060 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1061 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1062 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1063 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1064 for (i = 0; i < addr_range; i++) { 1065 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1066 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1067 } 1068 } 1069 1070 static void pt_guest_enter(struct vcpu_vmx *vmx) 1071 { 1072 if (vmx_pt_mode_is_system()) 1073 return; 1074 1075 /* 1076 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1077 * Save host state before VM entry. 1078 */ 1079 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1080 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1081 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1082 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1083 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1084 } 1085 } 1086 1087 static void pt_guest_exit(struct vcpu_vmx *vmx) 1088 { 1089 if (vmx_pt_mode_is_system()) 1090 return; 1091 1092 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1093 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1094 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1095 } 1096 1097 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1098 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1099 } 1100 1101 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1102 unsigned long fs_base, unsigned long gs_base) 1103 { 1104 if (unlikely(fs_sel != host->fs_sel)) { 1105 if (!(fs_sel & 7)) 1106 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1107 else 1108 vmcs_write16(HOST_FS_SELECTOR, 0); 1109 host->fs_sel = fs_sel; 1110 } 1111 if (unlikely(gs_sel != host->gs_sel)) { 1112 if (!(gs_sel & 7)) 1113 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1114 else 1115 vmcs_write16(HOST_GS_SELECTOR, 0); 1116 host->gs_sel = gs_sel; 1117 } 1118 if (unlikely(fs_base != host->fs_base)) { 1119 vmcs_writel(HOST_FS_BASE, fs_base); 1120 host->fs_base = fs_base; 1121 } 1122 if (unlikely(gs_base != host->gs_base)) { 1123 vmcs_writel(HOST_GS_BASE, gs_base); 1124 host->gs_base = gs_base; 1125 } 1126 } 1127 1128 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1129 { 1130 struct vcpu_vmx *vmx = to_vmx(vcpu); 1131 struct vmcs_host_state *host_state; 1132 #ifdef CONFIG_X86_64 1133 int cpu = raw_smp_processor_id(); 1134 #endif 1135 unsigned long fs_base, gs_base; 1136 u16 fs_sel, gs_sel; 1137 int i; 1138 1139 vmx->req_immediate_exit = false; 1140 1141 /* 1142 * Note that guest MSRs to be saved/restored can also be changed 1143 * when guest state is loaded. This happens when guest transitions 1144 * to/from long-mode by setting MSR_EFER.LMA. 1145 */ 1146 if (!vmx->guest_msrs_ready) { 1147 vmx->guest_msrs_ready = true; 1148 for (i = 0; i < vmx->save_nmsrs; ++i) 1149 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1150 vmx->guest_msrs[i].data, 1151 vmx->guest_msrs[i].mask); 1152 1153 } 1154 1155 if (vmx->nested.need_vmcs12_to_shadow_sync) 1156 nested_sync_vmcs12_to_shadow(vcpu); 1157 1158 if (vmx->guest_state_loaded) 1159 return; 1160 1161 host_state = &vmx->loaded_vmcs->host_state; 1162 1163 /* 1164 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1165 * allow segment selectors with cpl > 0 or ti == 1. 1166 */ 1167 host_state->ldt_sel = kvm_read_ldt(); 1168 1169 #ifdef CONFIG_X86_64 1170 savesegment(ds, host_state->ds_sel); 1171 savesegment(es, host_state->es_sel); 1172 1173 gs_base = cpu_kernelmode_gs_base(cpu); 1174 if (likely(is_64bit_mm(current->mm))) { 1175 save_fsgs_for_kvm(); 1176 fs_sel = current->thread.fsindex; 1177 gs_sel = current->thread.gsindex; 1178 fs_base = current->thread.fsbase; 1179 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1180 } else { 1181 savesegment(fs, fs_sel); 1182 savesegment(gs, gs_sel); 1183 fs_base = read_msr(MSR_FS_BASE); 1184 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1185 } 1186 1187 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1188 #else 1189 savesegment(fs, fs_sel); 1190 savesegment(gs, gs_sel); 1191 fs_base = segment_base(fs_sel); 1192 gs_base = segment_base(gs_sel); 1193 #endif 1194 1195 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1196 vmx->guest_state_loaded = true; 1197 } 1198 1199 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1200 { 1201 struct vmcs_host_state *host_state; 1202 1203 if (!vmx->guest_state_loaded) 1204 return; 1205 1206 host_state = &vmx->loaded_vmcs->host_state; 1207 1208 ++vmx->vcpu.stat.host_state_reload; 1209 1210 #ifdef CONFIG_X86_64 1211 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1212 #endif 1213 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1214 kvm_load_ldt(host_state->ldt_sel); 1215 #ifdef CONFIG_X86_64 1216 load_gs_index(host_state->gs_sel); 1217 #else 1218 loadsegment(gs, host_state->gs_sel); 1219 #endif 1220 } 1221 if (host_state->fs_sel & 7) 1222 loadsegment(fs, host_state->fs_sel); 1223 #ifdef CONFIG_X86_64 1224 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1225 loadsegment(ds, host_state->ds_sel); 1226 loadsegment(es, host_state->es_sel); 1227 } 1228 #endif 1229 invalidate_tss_limit(); 1230 #ifdef CONFIG_X86_64 1231 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1232 #endif 1233 load_fixmap_gdt(raw_smp_processor_id()); 1234 vmx->guest_state_loaded = false; 1235 vmx->guest_msrs_ready = false; 1236 } 1237 1238 #ifdef CONFIG_X86_64 1239 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1240 { 1241 preempt_disable(); 1242 if (vmx->guest_state_loaded) 1243 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1244 preempt_enable(); 1245 return vmx->msr_guest_kernel_gs_base; 1246 } 1247 1248 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1249 { 1250 preempt_disable(); 1251 if (vmx->guest_state_loaded) 1252 wrmsrl(MSR_KERNEL_GS_BASE, data); 1253 preempt_enable(); 1254 vmx->msr_guest_kernel_gs_base = data; 1255 } 1256 #endif 1257 1258 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1259 { 1260 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1261 struct pi_desc old, new; 1262 unsigned int dest; 1263 1264 /* 1265 * In case of hot-plug or hot-unplug, we may have to undo 1266 * vmx_vcpu_pi_put even if there is no assigned device. And we 1267 * always keep PI.NDST up to date for simplicity: it makes the 1268 * code easier, and CPU migration is not a fast path. 1269 */ 1270 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1271 return; 1272 1273 /* 1274 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1275 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1276 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1277 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1278 * correctly. 1279 */ 1280 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1281 pi_clear_sn(pi_desc); 1282 goto after_clear_sn; 1283 } 1284 1285 /* The full case. */ 1286 do { 1287 old.control = new.control = pi_desc->control; 1288 1289 dest = cpu_physical_id(cpu); 1290 1291 if (x2apic_enabled()) 1292 new.ndst = dest; 1293 else 1294 new.ndst = (dest << 8) & 0xFF00; 1295 1296 new.sn = 0; 1297 } while (cmpxchg64(&pi_desc->control, old.control, 1298 new.control) != old.control); 1299 1300 after_clear_sn: 1301 1302 /* 1303 * Clear SN before reading the bitmap. The VT-d firmware 1304 * writes the bitmap and reads SN atomically (5.2.3 in the 1305 * spec), so it doesn't really have a memory barrier that 1306 * pairs with this, but we cannot do that and we need one. 1307 */ 1308 smp_mb__after_atomic(); 1309 1310 if (!pi_is_pir_empty(pi_desc)) 1311 pi_set_on(pi_desc); 1312 } 1313 1314 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, 1315 struct loaded_vmcs *buddy) 1316 { 1317 struct vcpu_vmx *vmx = to_vmx(vcpu); 1318 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1319 struct vmcs *prev; 1320 1321 if (!already_loaded) { 1322 loaded_vmcs_clear(vmx->loaded_vmcs); 1323 local_irq_disable(); 1324 1325 /* 1326 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to 1327 * this cpu's percpu list, otherwise it may not yet be deleted 1328 * from its previous cpu's percpu list. Pairs with the 1329 * smb_wmb() in __loaded_vmcs_clear(). 1330 */ 1331 smp_rmb(); 1332 1333 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1334 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1335 local_irq_enable(); 1336 } 1337 1338 prev = per_cpu(current_vmcs, cpu); 1339 if (prev != vmx->loaded_vmcs->vmcs) { 1340 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1341 vmcs_load(vmx->loaded_vmcs->vmcs); 1342 1343 /* 1344 * No indirect branch prediction barrier needed when switching 1345 * the active VMCS within a guest, e.g. on nested VM-Enter. 1346 * The L1 VMM can protect itself with retpolines, IBPB or IBRS. 1347 */ 1348 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev)) 1349 indirect_branch_prediction_barrier(); 1350 } 1351 1352 if (!already_loaded) { 1353 void *gdt = get_current_gdt_ro(); 1354 unsigned long sysenter_esp; 1355 1356 /* 1357 * Flush all EPTP/VPID contexts, the new pCPU may have stale 1358 * TLB entries from its previous association with the vCPU. 1359 */ 1360 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1361 1362 /* 1363 * Linux uses per-cpu TSS and GDT, so set these when switching 1364 * processors. See 22.2.4. 1365 */ 1366 vmcs_writel(HOST_TR_BASE, 1367 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1368 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1369 1370 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1371 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1372 1373 vmx->loaded_vmcs->cpu = cpu; 1374 } 1375 1376 /* Setup TSC multiplier */ 1377 if (kvm_has_tsc_control && 1378 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1379 decache_tsc_multiplier(vmx); 1380 } 1381 1382 /* 1383 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1384 * vcpu mutex is already taken. 1385 */ 1386 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1387 { 1388 struct vcpu_vmx *vmx = to_vmx(vcpu); 1389 1390 vmx_vcpu_load_vmcs(vcpu, cpu, NULL); 1391 1392 vmx_vcpu_pi_load(vcpu, cpu); 1393 1394 vmx->host_debugctlmsr = get_debugctlmsr(); 1395 } 1396 1397 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1398 { 1399 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1400 1401 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1402 !irq_remapping_cap(IRQ_POSTING_CAP) || 1403 !kvm_vcpu_apicv_active(vcpu)) 1404 return; 1405 1406 /* Set SN when the vCPU is preempted */ 1407 if (vcpu->preempted) 1408 pi_set_sn(pi_desc); 1409 } 1410 1411 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1412 { 1413 vmx_vcpu_pi_put(vcpu); 1414 1415 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1416 } 1417 1418 static bool emulation_required(struct kvm_vcpu *vcpu) 1419 { 1420 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1421 } 1422 1423 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1424 { 1425 struct vcpu_vmx *vmx = to_vmx(vcpu); 1426 unsigned long rflags, save_rflags; 1427 1428 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1429 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1430 rflags = vmcs_readl(GUEST_RFLAGS); 1431 if (vmx->rmode.vm86_active) { 1432 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1433 save_rflags = vmx->rmode.save_rflags; 1434 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1435 } 1436 vmx->rflags = rflags; 1437 } 1438 return vmx->rflags; 1439 } 1440 1441 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1442 { 1443 struct vcpu_vmx *vmx = to_vmx(vcpu); 1444 unsigned long old_rflags; 1445 1446 if (enable_unrestricted_guest) { 1447 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1448 vmx->rflags = rflags; 1449 vmcs_writel(GUEST_RFLAGS, rflags); 1450 return; 1451 } 1452 1453 old_rflags = vmx_get_rflags(vcpu); 1454 vmx->rflags = rflags; 1455 if (vmx->rmode.vm86_active) { 1456 vmx->rmode.save_rflags = rflags; 1457 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1458 } 1459 vmcs_writel(GUEST_RFLAGS, rflags); 1460 1461 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1462 vmx->emulation_required = emulation_required(vcpu); 1463 } 1464 1465 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1466 { 1467 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1468 int ret = 0; 1469 1470 if (interruptibility & GUEST_INTR_STATE_STI) 1471 ret |= KVM_X86_SHADOW_INT_STI; 1472 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1473 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1474 1475 return ret; 1476 } 1477 1478 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1479 { 1480 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1481 u32 interruptibility = interruptibility_old; 1482 1483 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1484 1485 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1486 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1487 else if (mask & KVM_X86_SHADOW_INT_STI) 1488 interruptibility |= GUEST_INTR_STATE_STI; 1489 1490 if ((interruptibility != interruptibility_old)) 1491 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1492 } 1493 1494 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1495 { 1496 struct vcpu_vmx *vmx = to_vmx(vcpu); 1497 unsigned long value; 1498 1499 /* 1500 * Any MSR write that attempts to change bits marked reserved will 1501 * case a #GP fault. 1502 */ 1503 if (data & vmx->pt_desc.ctl_bitmask) 1504 return 1; 1505 1506 /* 1507 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1508 * result in a #GP unless the same write also clears TraceEn. 1509 */ 1510 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1511 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1512 return 1; 1513 1514 /* 1515 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1516 * and FabricEn would cause #GP, if 1517 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1518 */ 1519 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1520 !(data & RTIT_CTL_FABRIC_EN) && 1521 !intel_pt_validate_cap(vmx->pt_desc.caps, 1522 PT_CAP_single_range_output)) 1523 return 1; 1524 1525 /* 1526 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1527 * utilize encodings marked reserved will casue a #GP fault. 1528 */ 1529 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1530 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1531 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1532 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1533 return 1; 1534 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1535 PT_CAP_cycle_thresholds); 1536 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1537 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1538 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1539 return 1; 1540 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1541 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1542 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1543 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1544 return 1; 1545 1546 /* 1547 * If ADDRx_CFG is reserved or the encodings is >2 will 1548 * cause a #GP fault. 1549 */ 1550 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1551 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1552 return 1; 1553 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1554 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1555 return 1; 1556 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1557 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1558 return 1; 1559 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1560 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1561 return 1; 1562 1563 return 0; 1564 } 1565 1566 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1567 { 1568 unsigned long rip, orig_rip; 1569 1570 /* 1571 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1572 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1573 * set when EPT misconfig occurs. In practice, real hardware updates 1574 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1575 * (namely Hyper-V) don't set it due to it being undefined behavior, 1576 * i.e. we end up advancing IP with some random value. 1577 */ 1578 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1579 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1580 orig_rip = kvm_rip_read(vcpu); 1581 rip = orig_rip + vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1582 #ifdef CONFIG_X86_64 1583 /* 1584 * We need to mask out the high 32 bits of RIP if not in 64-bit 1585 * mode, but just finding out that we are in 64-bit mode is 1586 * quite expensive. Only do it if there was a carry. 1587 */ 1588 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu)) 1589 rip = (u32)rip; 1590 #endif 1591 kvm_rip_write(vcpu, rip); 1592 } else { 1593 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1594 return 0; 1595 } 1596 1597 /* skipping an emulated instruction also counts */ 1598 vmx_set_interrupt_shadow(vcpu, 0); 1599 1600 return 1; 1601 } 1602 1603 1604 /* 1605 * Recognizes a pending MTF VM-exit and records the nested state for later 1606 * delivery. 1607 */ 1608 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu) 1609 { 1610 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1611 struct vcpu_vmx *vmx = to_vmx(vcpu); 1612 1613 if (!is_guest_mode(vcpu)) 1614 return; 1615 1616 /* 1617 * Per the SDM, MTF takes priority over debug-trap exceptions besides 1618 * T-bit traps. As instruction emulation is completed (i.e. at the 1619 * instruction boundary), any #DB exception pending delivery must be a 1620 * debug-trap. Record the pending MTF state to be delivered in 1621 * vmx_check_nested_events(). 1622 */ 1623 if (nested_cpu_has_mtf(vmcs12) && 1624 (!vcpu->arch.exception.pending || 1625 vcpu->arch.exception.nr == DB_VECTOR)) 1626 vmx->nested.mtf_pending = true; 1627 else 1628 vmx->nested.mtf_pending = false; 1629 } 1630 1631 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu) 1632 { 1633 vmx_update_emulated_instruction(vcpu); 1634 return skip_emulated_instruction(vcpu); 1635 } 1636 1637 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1638 { 1639 /* 1640 * Ensure that we clear the HLT state in the VMCS. We don't need to 1641 * explicitly skip the instruction because if the HLT state is set, 1642 * then the instruction is already executing and RIP has already been 1643 * advanced. 1644 */ 1645 if (kvm_hlt_in_guest(vcpu->kvm) && 1646 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1647 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1648 } 1649 1650 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1651 { 1652 struct vcpu_vmx *vmx = to_vmx(vcpu); 1653 unsigned nr = vcpu->arch.exception.nr; 1654 bool has_error_code = vcpu->arch.exception.has_error_code; 1655 u32 error_code = vcpu->arch.exception.error_code; 1656 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1657 1658 kvm_deliver_exception_payload(vcpu); 1659 1660 if (has_error_code) { 1661 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1662 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1663 } 1664 1665 if (vmx->rmode.vm86_active) { 1666 int inc_eip = 0; 1667 if (kvm_exception_is_soft(nr)) 1668 inc_eip = vcpu->arch.event_exit_inst_len; 1669 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1670 return; 1671 } 1672 1673 WARN_ON_ONCE(vmx->emulation_required); 1674 1675 if (kvm_exception_is_soft(nr)) { 1676 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1677 vmx->vcpu.arch.event_exit_inst_len); 1678 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1679 } else 1680 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1681 1682 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1683 1684 vmx_clear_hlt(vcpu); 1685 } 1686 1687 /* 1688 * Swap MSR entry in host/guest MSR entry array. 1689 */ 1690 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1691 { 1692 struct shared_msr_entry tmp; 1693 1694 tmp = vmx->guest_msrs[to]; 1695 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1696 vmx->guest_msrs[from] = tmp; 1697 } 1698 1699 /* 1700 * Set up the vmcs to automatically save and restore system 1701 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1702 * mode, as fiddling with msrs is very expensive. 1703 */ 1704 static void setup_msrs(struct vcpu_vmx *vmx) 1705 { 1706 int save_nmsrs, index; 1707 1708 save_nmsrs = 0; 1709 #ifdef CONFIG_X86_64 1710 /* 1711 * The SYSCALL MSRs are only needed on long mode guests, and only 1712 * when EFER.SCE is set. 1713 */ 1714 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1715 index = __find_msr_index(vmx, MSR_STAR); 1716 if (index >= 0) 1717 move_msr_up(vmx, index, save_nmsrs++); 1718 index = __find_msr_index(vmx, MSR_LSTAR); 1719 if (index >= 0) 1720 move_msr_up(vmx, index, save_nmsrs++); 1721 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1722 if (index >= 0) 1723 move_msr_up(vmx, index, save_nmsrs++); 1724 } 1725 #endif 1726 index = __find_msr_index(vmx, MSR_EFER); 1727 if (index >= 0 && update_transition_efer(vmx, index)) 1728 move_msr_up(vmx, index, save_nmsrs++); 1729 index = __find_msr_index(vmx, MSR_TSC_AUX); 1730 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1731 move_msr_up(vmx, index, save_nmsrs++); 1732 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1733 if (index >= 0) 1734 move_msr_up(vmx, index, save_nmsrs++); 1735 1736 vmx->save_nmsrs = save_nmsrs; 1737 vmx->guest_msrs_ready = false; 1738 1739 if (cpu_has_vmx_msr_bitmap()) 1740 vmx_update_msr_bitmap(&vmx->vcpu); 1741 } 1742 1743 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1744 { 1745 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1746 u64 g_tsc_offset = 0; 1747 1748 /* 1749 * We're here if L1 chose not to trap WRMSR to TSC. According 1750 * to the spec, this should set L1's TSC; The offset that L1 1751 * set for L2 remains unchanged, and still needs to be added 1752 * to the newly set TSC to get L2's TSC. 1753 */ 1754 if (is_guest_mode(vcpu) && 1755 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1756 g_tsc_offset = vmcs12->tsc_offset; 1757 1758 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1759 vcpu->arch.tsc_offset - g_tsc_offset, 1760 offset); 1761 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1762 return offset + g_tsc_offset; 1763 } 1764 1765 /* 1766 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1767 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1768 * all guests if the "nested" module option is off, and can also be disabled 1769 * for a single guest by disabling its VMX cpuid bit. 1770 */ 1771 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1772 { 1773 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1774 } 1775 1776 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1777 uint64_t val) 1778 { 1779 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1780 1781 return !(val & ~valid_bits); 1782 } 1783 1784 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1785 { 1786 switch (msr->index) { 1787 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1788 if (!nested) 1789 return 1; 1790 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1791 case MSR_IA32_PERF_CAPABILITIES: 1792 msr->data = vmx_get_perf_capabilities(); 1793 return 0; 1794 default: 1795 return 1; 1796 } 1797 } 1798 1799 /* 1800 * Reads an msr value (of 'msr_index') into 'pdata'. 1801 * Returns 0 on success, non-0 otherwise. 1802 * Assumes vcpu_load() was already called. 1803 */ 1804 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1805 { 1806 struct vcpu_vmx *vmx = to_vmx(vcpu); 1807 struct shared_msr_entry *msr; 1808 u32 index; 1809 1810 switch (msr_info->index) { 1811 #ifdef CONFIG_X86_64 1812 case MSR_FS_BASE: 1813 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1814 break; 1815 case MSR_GS_BASE: 1816 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1817 break; 1818 case MSR_KERNEL_GS_BASE: 1819 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1820 break; 1821 #endif 1822 case MSR_EFER: 1823 return kvm_get_msr_common(vcpu, msr_info); 1824 case MSR_IA32_TSX_CTRL: 1825 if (!msr_info->host_initiated && 1826 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1827 return 1; 1828 goto find_shared_msr; 1829 case MSR_IA32_UMWAIT_CONTROL: 1830 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1831 return 1; 1832 1833 msr_info->data = vmx->msr_ia32_umwait_control; 1834 break; 1835 case MSR_IA32_SPEC_CTRL: 1836 if (!msr_info->host_initiated && 1837 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1838 return 1; 1839 1840 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1841 break; 1842 case MSR_IA32_SYSENTER_CS: 1843 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1844 break; 1845 case MSR_IA32_SYSENTER_EIP: 1846 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1847 break; 1848 case MSR_IA32_SYSENTER_ESP: 1849 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1850 break; 1851 case MSR_IA32_BNDCFGS: 1852 if (!kvm_mpx_supported() || 1853 (!msr_info->host_initiated && 1854 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1855 return 1; 1856 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1857 break; 1858 case MSR_IA32_MCG_EXT_CTL: 1859 if (!msr_info->host_initiated && 1860 !(vmx->msr_ia32_feature_control & 1861 FEAT_CTL_LMCE_ENABLED)) 1862 return 1; 1863 msr_info->data = vcpu->arch.mcg_ext_ctl; 1864 break; 1865 case MSR_IA32_FEAT_CTL: 1866 msr_info->data = vmx->msr_ia32_feature_control; 1867 break; 1868 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1869 if (!nested_vmx_allowed(vcpu)) 1870 return 1; 1871 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1872 &msr_info->data)) 1873 return 1; 1874 /* 1875 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1876 * Hyper-V versions are still trying to use corresponding 1877 * features when they are exposed. Filter out the essential 1878 * minimum. 1879 */ 1880 if (!msr_info->host_initiated && 1881 vmx->nested.enlightened_vmcs_enabled) 1882 nested_evmcs_filter_control_msr(msr_info->index, 1883 &msr_info->data); 1884 break; 1885 case MSR_IA32_RTIT_CTL: 1886 if (!vmx_pt_mode_is_host_guest()) 1887 return 1; 1888 msr_info->data = vmx->pt_desc.guest.ctl; 1889 break; 1890 case MSR_IA32_RTIT_STATUS: 1891 if (!vmx_pt_mode_is_host_guest()) 1892 return 1; 1893 msr_info->data = vmx->pt_desc.guest.status; 1894 break; 1895 case MSR_IA32_RTIT_CR3_MATCH: 1896 if (!vmx_pt_mode_is_host_guest() || 1897 !intel_pt_validate_cap(vmx->pt_desc.caps, 1898 PT_CAP_cr3_filtering)) 1899 return 1; 1900 msr_info->data = vmx->pt_desc.guest.cr3_match; 1901 break; 1902 case MSR_IA32_RTIT_OUTPUT_BASE: 1903 if (!vmx_pt_mode_is_host_guest() || 1904 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1905 PT_CAP_topa_output) && 1906 !intel_pt_validate_cap(vmx->pt_desc.caps, 1907 PT_CAP_single_range_output))) 1908 return 1; 1909 msr_info->data = vmx->pt_desc.guest.output_base; 1910 break; 1911 case MSR_IA32_RTIT_OUTPUT_MASK: 1912 if (!vmx_pt_mode_is_host_guest() || 1913 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1914 PT_CAP_topa_output) && 1915 !intel_pt_validate_cap(vmx->pt_desc.caps, 1916 PT_CAP_single_range_output))) 1917 return 1; 1918 msr_info->data = vmx->pt_desc.guest.output_mask; 1919 break; 1920 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1921 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1922 if (!vmx_pt_mode_is_host_guest() || 1923 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1924 PT_CAP_num_address_ranges))) 1925 return 1; 1926 if (index % 2) 1927 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1928 else 1929 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1930 break; 1931 case MSR_TSC_AUX: 1932 if (!msr_info->host_initiated && 1933 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1934 return 1; 1935 goto find_shared_msr; 1936 default: 1937 find_shared_msr: 1938 msr = find_msr_entry(vmx, msr_info->index); 1939 if (msr) { 1940 msr_info->data = msr->data; 1941 break; 1942 } 1943 return kvm_get_msr_common(vcpu, msr_info); 1944 } 1945 1946 return 0; 1947 } 1948 1949 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu, 1950 u64 data) 1951 { 1952 #ifdef CONFIG_X86_64 1953 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1954 return (u32)data; 1955 #endif 1956 return (unsigned long)data; 1957 } 1958 1959 /* 1960 * Writes msr value into the appropriate "register". 1961 * Returns 0 on success, non-0 otherwise. 1962 * Assumes vcpu_load() was already called. 1963 */ 1964 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1965 { 1966 struct vcpu_vmx *vmx = to_vmx(vcpu); 1967 struct shared_msr_entry *msr; 1968 int ret = 0; 1969 u32 msr_index = msr_info->index; 1970 u64 data = msr_info->data; 1971 u32 index; 1972 1973 switch (msr_index) { 1974 case MSR_EFER: 1975 ret = kvm_set_msr_common(vcpu, msr_info); 1976 break; 1977 #ifdef CONFIG_X86_64 1978 case MSR_FS_BASE: 1979 vmx_segment_cache_clear(vmx); 1980 vmcs_writel(GUEST_FS_BASE, data); 1981 break; 1982 case MSR_GS_BASE: 1983 vmx_segment_cache_clear(vmx); 1984 vmcs_writel(GUEST_GS_BASE, data); 1985 break; 1986 case MSR_KERNEL_GS_BASE: 1987 vmx_write_guest_kernel_gs_base(vmx, data); 1988 break; 1989 #endif 1990 case MSR_IA32_SYSENTER_CS: 1991 if (is_guest_mode(vcpu)) 1992 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1993 vmcs_write32(GUEST_SYSENTER_CS, data); 1994 break; 1995 case MSR_IA32_SYSENTER_EIP: 1996 if (is_guest_mode(vcpu)) { 1997 data = nested_vmx_truncate_sysenter_addr(vcpu, data); 1998 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1999 } 2000 vmcs_writel(GUEST_SYSENTER_EIP, data); 2001 break; 2002 case MSR_IA32_SYSENTER_ESP: 2003 if (is_guest_mode(vcpu)) { 2004 data = nested_vmx_truncate_sysenter_addr(vcpu, data); 2005 get_vmcs12(vcpu)->guest_sysenter_esp = data; 2006 } 2007 vmcs_writel(GUEST_SYSENTER_ESP, data); 2008 break; 2009 case MSR_IA32_DEBUGCTLMSR: 2010 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 2011 VM_EXIT_SAVE_DEBUG_CONTROLS) 2012 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 2013 2014 ret = kvm_set_msr_common(vcpu, msr_info); 2015 break; 2016 2017 case MSR_IA32_BNDCFGS: 2018 if (!kvm_mpx_supported() || 2019 (!msr_info->host_initiated && 2020 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 2021 return 1; 2022 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 2023 (data & MSR_IA32_BNDCFGS_RSVD)) 2024 return 1; 2025 vmcs_write64(GUEST_BNDCFGS, data); 2026 break; 2027 case MSR_IA32_UMWAIT_CONTROL: 2028 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 2029 return 1; 2030 2031 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 2032 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 2033 return 1; 2034 2035 vmx->msr_ia32_umwait_control = data; 2036 break; 2037 case MSR_IA32_SPEC_CTRL: 2038 if (!msr_info->host_initiated && 2039 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2040 return 1; 2041 2042 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2043 return 1; 2044 2045 vmx->spec_ctrl = data; 2046 if (!data) 2047 break; 2048 2049 /* 2050 * For non-nested: 2051 * When it's written (to non-zero) for the first time, pass 2052 * it through. 2053 * 2054 * For nested: 2055 * The handling of the MSR bitmap for L2 guests is done in 2056 * nested_vmx_prepare_msr_bitmap. We should not touch the 2057 * vmcs02.msr_bitmap here since it gets completely overwritten 2058 * in the merging. We update the vmcs01 here for L1 as well 2059 * since it will end up touching the MSR anyway now. 2060 */ 2061 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2062 MSR_IA32_SPEC_CTRL, 2063 MSR_TYPE_RW); 2064 break; 2065 case MSR_IA32_TSX_CTRL: 2066 if (!msr_info->host_initiated && 2067 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2068 return 1; 2069 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2070 return 1; 2071 goto find_shared_msr; 2072 case MSR_IA32_PRED_CMD: 2073 if (!msr_info->host_initiated && 2074 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2075 return 1; 2076 2077 if (data & ~PRED_CMD_IBPB) 2078 return 1; 2079 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2080 return 1; 2081 if (!data) 2082 break; 2083 2084 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2085 2086 /* 2087 * For non-nested: 2088 * When it's written (to non-zero) for the first time, pass 2089 * it through. 2090 * 2091 * For nested: 2092 * The handling of the MSR bitmap for L2 guests is done in 2093 * nested_vmx_prepare_msr_bitmap. We should not touch the 2094 * vmcs02.msr_bitmap here since it gets completely overwritten 2095 * in the merging. 2096 */ 2097 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2098 MSR_TYPE_W); 2099 break; 2100 case MSR_IA32_CR_PAT: 2101 if (!kvm_pat_valid(data)) 2102 return 1; 2103 2104 if (is_guest_mode(vcpu) && 2105 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2106 get_vmcs12(vcpu)->guest_ia32_pat = data; 2107 2108 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2109 vmcs_write64(GUEST_IA32_PAT, data); 2110 vcpu->arch.pat = data; 2111 break; 2112 } 2113 ret = kvm_set_msr_common(vcpu, msr_info); 2114 break; 2115 case MSR_IA32_TSC_ADJUST: 2116 ret = kvm_set_msr_common(vcpu, msr_info); 2117 break; 2118 case MSR_IA32_MCG_EXT_CTL: 2119 if ((!msr_info->host_initiated && 2120 !(to_vmx(vcpu)->msr_ia32_feature_control & 2121 FEAT_CTL_LMCE_ENABLED)) || 2122 (data & ~MCG_EXT_CTL_LMCE_EN)) 2123 return 1; 2124 vcpu->arch.mcg_ext_ctl = data; 2125 break; 2126 case MSR_IA32_FEAT_CTL: 2127 if (!vmx_feature_control_msr_valid(vcpu, data) || 2128 (to_vmx(vcpu)->msr_ia32_feature_control & 2129 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2130 return 1; 2131 vmx->msr_ia32_feature_control = data; 2132 if (msr_info->host_initiated && data == 0) 2133 vmx_leave_nested(vcpu); 2134 break; 2135 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2136 if (!msr_info->host_initiated) 2137 return 1; /* they are read-only */ 2138 if (!nested_vmx_allowed(vcpu)) 2139 return 1; 2140 return vmx_set_vmx_msr(vcpu, msr_index, data); 2141 case MSR_IA32_RTIT_CTL: 2142 if (!vmx_pt_mode_is_host_guest() || 2143 vmx_rtit_ctl_check(vcpu, data) || 2144 vmx->nested.vmxon) 2145 return 1; 2146 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2147 vmx->pt_desc.guest.ctl = data; 2148 pt_update_intercept_for_msr(vmx); 2149 break; 2150 case MSR_IA32_RTIT_STATUS: 2151 if (!pt_can_write_msr(vmx)) 2152 return 1; 2153 if (data & MSR_IA32_RTIT_STATUS_MASK) 2154 return 1; 2155 vmx->pt_desc.guest.status = data; 2156 break; 2157 case MSR_IA32_RTIT_CR3_MATCH: 2158 if (!pt_can_write_msr(vmx)) 2159 return 1; 2160 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2161 PT_CAP_cr3_filtering)) 2162 return 1; 2163 vmx->pt_desc.guest.cr3_match = data; 2164 break; 2165 case MSR_IA32_RTIT_OUTPUT_BASE: 2166 if (!pt_can_write_msr(vmx)) 2167 return 1; 2168 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2169 PT_CAP_topa_output) && 2170 !intel_pt_validate_cap(vmx->pt_desc.caps, 2171 PT_CAP_single_range_output)) 2172 return 1; 2173 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2174 return 1; 2175 vmx->pt_desc.guest.output_base = data; 2176 break; 2177 case MSR_IA32_RTIT_OUTPUT_MASK: 2178 if (!pt_can_write_msr(vmx)) 2179 return 1; 2180 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2181 PT_CAP_topa_output) && 2182 !intel_pt_validate_cap(vmx->pt_desc.caps, 2183 PT_CAP_single_range_output)) 2184 return 1; 2185 vmx->pt_desc.guest.output_mask = data; 2186 break; 2187 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2188 if (!pt_can_write_msr(vmx)) 2189 return 1; 2190 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2191 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2192 PT_CAP_num_address_ranges)) 2193 return 1; 2194 if (is_noncanonical_address(data, vcpu)) 2195 return 1; 2196 if (index % 2) 2197 vmx->pt_desc.guest.addr_b[index / 2] = data; 2198 else 2199 vmx->pt_desc.guest.addr_a[index / 2] = data; 2200 break; 2201 case MSR_TSC_AUX: 2202 if (!msr_info->host_initiated && 2203 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2204 return 1; 2205 /* Check reserved bit, higher 32 bits should be zero */ 2206 if ((data >> 32) != 0) 2207 return 1; 2208 goto find_shared_msr; 2209 2210 default: 2211 find_shared_msr: 2212 msr = find_msr_entry(vmx, msr_index); 2213 if (msr) 2214 ret = vmx_set_guest_msr(vmx, msr, data); 2215 else 2216 ret = kvm_set_msr_common(vcpu, msr_info); 2217 } 2218 2219 return ret; 2220 } 2221 2222 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2223 { 2224 unsigned long guest_owned_bits; 2225 2226 kvm_register_mark_available(vcpu, reg); 2227 2228 switch (reg) { 2229 case VCPU_REGS_RSP: 2230 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2231 break; 2232 case VCPU_REGS_RIP: 2233 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2234 break; 2235 case VCPU_EXREG_PDPTR: 2236 if (enable_ept) 2237 ept_save_pdptrs(vcpu); 2238 break; 2239 case VCPU_EXREG_CR0: 2240 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2241 2242 vcpu->arch.cr0 &= ~guest_owned_bits; 2243 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits; 2244 break; 2245 case VCPU_EXREG_CR3: 2246 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2247 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2248 break; 2249 case VCPU_EXREG_CR4: 2250 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2251 2252 vcpu->arch.cr4 &= ~guest_owned_bits; 2253 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits; 2254 break; 2255 default: 2256 WARN_ON_ONCE(1); 2257 break; 2258 } 2259 } 2260 2261 static __init int cpu_has_kvm_support(void) 2262 { 2263 return cpu_has_vmx(); 2264 } 2265 2266 static __init int vmx_disabled_by_bios(void) 2267 { 2268 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2269 !boot_cpu_has(X86_FEATURE_VMX); 2270 } 2271 2272 static int kvm_cpu_vmxon(u64 vmxon_pointer) 2273 { 2274 u64 msr; 2275 2276 cr4_set_bits(X86_CR4_VMXE); 2277 intel_pt_handle_vmx(1); 2278 2279 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t" 2280 _ASM_EXTABLE(1b, %l[fault]) 2281 : : [vmxon_pointer] "m"(vmxon_pointer) 2282 : : fault); 2283 return 0; 2284 2285 fault: 2286 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n", 2287 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); 2288 intel_pt_handle_vmx(0); 2289 cr4_clear_bits(X86_CR4_VMXE); 2290 2291 return -EFAULT; 2292 } 2293 2294 static int hardware_enable(void) 2295 { 2296 int cpu = raw_smp_processor_id(); 2297 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2298 int r; 2299 2300 if (cr4_read_shadow() & X86_CR4_VMXE) 2301 return -EBUSY; 2302 2303 /* 2304 * This can happen if we hot-added a CPU but failed to allocate 2305 * VP assist page for it. 2306 */ 2307 if (static_branch_unlikely(&enable_evmcs) && 2308 !hv_get_vp_assist_page(cpu)) 2309 return -EFAULT; 2310 2311 r = kvm_cpu_vmxon(phys_addr); 2312 if (r) 2313 return r; 2314 2315 if (enable_ept) 2316 ept_sync_global(); 2317 2318 return 0; 2319 } 2320 2321 static void vmclear_local_loaded_vmcss(void) 2322 { 2323 int cpu = raw_smp_processor_id(); 2324 struct loaded_vmcs *v, *n; 2325 2326 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2327 loaded_vmcss_on_cpu_link) 2328 __loaded_vmcs_clear(v); 2329 } 2330 2331 2332 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2333 * tricks. 2334 */ 2335 static void kvm_cpu_vmxoff(void) 2336 { 2337 asm volatile (__ex("vmxoff")); 2338 2339 intel_pt_handle_vmx(0); 2340 cr4_clear_bits(X86_CR4_VMXE); 2341 } 2342 2343 static void hardware_disable(void) 2344 { 2345 vmclear_local_loaded_vmcss(); 2346 kvm_cpu_vmxoff(); 2347 } 2348 2349 /* 2350 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID 2351 * directly instead of going through cpu_has(), to ensure KVM is trapping 2352 * ENCLS whenever it's supported in hardware. It does not matter whether 2353 * the host OS supports or has enabled SGX. 2354 */ 2355 static bool cpu_has_sgx(void) 2356 { 2357 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0)); 2358 } 2359 2360 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2361 u32 msr, u32 *result) 2362 { 2363 u32 vmx_msr_low, vmx_msr_high; 2364 u32 ctl = ctl_min | ctl_opt; 2365 2366 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2367 2368 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2369 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2370 2371 /* Ensure minimum (required) set of control bits are supported. */ 2372 if (ctl_min & ~ctl) 2373 return -EIO; 2374 2375 *result = ctl; 2376 return 0; 2377 } 2378 2379 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2380 struct vmx_capability *vmx_cap) 2381 { 2382 u32 vmx_msr_low, vmx_msr_high; 2383 u32 min, opt, min2, opt2; 2384 u32 _pin_based_exec_control = 0; 2385 u32 _cpu_based_exec_control = 0; 2386 u32 _cpu_based_2nd_exec_control = 0; 2387 u32 _vmexit_control = 0; 2388 u32 _vmentry_control = 0; 2389 2390 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2391 min = CPU_BASED_HLT_EXITING | 2392 #ifdef CONFIG_X86_64 2393 CPU_BASED_CR8_LOAD_EXITING | 2394 CPU_BASED_CR8_STORE_EXITING | 2395 #endif 2396 CPU_BASED_CR3_LOAD_EXITING | 2397 CPU_BASED_CR3_STORE_EXITING | 2398 CPU_BASED_UNCOND_IO_EXITING | 2399 CPU_BASED_MOV_DR_EXITING | 2400 CPU_BASED_USE_TSC_OFFSETTING | 2401 CPU_BASED_MWAIT_EXITING | 2402 CPU_BASED_MONITOR_EXITING | 2403 CPU_BASED_INVLPG_EXITING | 2404 CPU_BASED_RDPMC_EXITING; 2405 2406 opt = CPU_BASED_TPR_SHADOW | 2407 CPU_BASED_USE_MSR_BITMAPS | 2408 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2409 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2410 &_cpu_based_exec_control) < 0) 2411 return -EIO; 2412 #ifdef CONFIG_X86_64 2413 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2414 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2415 ~CPU_BASED_CR8_STORE_EXITING; 2416 #endif 2417 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2418 min2 = 0; 2419 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2420 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2421 SECONDARY_EXEC_WBINVD_EXITING | 2422 SECONDARY_EXEC_ENABLE_VPID | 2423 SECONDARY_EXEC_ENABLE_EPT | 2424 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2425 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2426 SECONDARY_EXEC_DESC | 2427 SECONDARY_EXEC_RDTSCP | 2428 SECONDARY_EXEC_ENABLE_INVPCID | 2429 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2430 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2431 SECONDARY_EXEC_SHADOW_VMCS | 2432 SECONDARY_EXEC_XSAVES | 2433 SECONDARY_EXEC_RDSEED_EXITING | 2434 SECONDARY_EXEC_RDRAND_EXITING | 2435 SECONDARY_EXEC_ENABLE_PML | 2436 SECONDARY_EXEC_TSC_SCALING | 2437 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2438 SECONDARY_EXEC_PT_USE_GPA | 2439 SECONDARY_EXEC_PT_CONCEAL_VMX | 2440 SECONDARY_EXEC_ENABLE_VMFUNC; 2441 if (cpu_has_sgx()) 2442 opt2 |= SECONDARY_EXEC_ENCLS_EXITING; 2443 if (adjust_vmx_controls(min2, opt2, 2444 MSR_IA32_VMX_PROCBASED_CTLS2, 2445 &_cpu_based_2nd_exec_control) < 0) 2446 return -EIO; 2447 } 2448 #ifndef CONFIG_X86_64 2449 if (!(_cpu_based_2nd_exec_control & 2450 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2451 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2452 #endif 2453 2454 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2455 _cpu_based_2nd_exec_control &= ~( 2456 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2457 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2458 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2459 2460 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2461 &vmx_cap->ept, &vmx_cap->vpid); 2462 2463 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2464 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2465 enabled */ 2466 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2467 CPU_BASED_CR3_STORE_EXITING | 2468 CPU_BASED_INVLPG_EXITING); 2469 } else if (vmx_cap->ept) { 2470 vmx_cap->ept = 0; 2471 pr_warn_once("EPT CAP should not exist if not support " 2472 "1-setting enable EPT VM-execution control\n"); 2473 } 2474 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2475 vmx_cap->vpid) { 2476 vmx_cap->vpid = 0; 2477 pr_warn_once("VPID CAP should not exist if not support " 2478 "1-setting enable VPID VM-execution control\n"); 2479 } 2480 2481 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2482 #ifdef CONFIG_X86_64 2483 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2484 #endif 2485 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2486 VM_EXIT_LOAD_IA32_PAT | 2487 VM_EXIT_LOAD_IA32_EFER | 2488 VM_EXIT_CLEAR_BNDCFGS | 2489 VM_EXIT_PT_CONCEAL_PIP | 2490 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2491 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2492 &_vmexit_control) < 0) 2493 return -EIO; 2494 2495 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2496 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2497 PIN_BASED_VMX_PREEMPTION_TIMER; 2498 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2499 &_pin_based_exec_control) < 0) 2500 return -EIO; 2501 2502 if (cpu_has_broken_vmx_preemption_timer()) 2503 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2504 if (!(_cpu_based_2nd_exec_control & 2505 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2506 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2507 2508 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2509 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2510 VM_ENTRY_LOAD_IA32_PAT | 2511 VM_ENTRY_LOAD_IA32_EFER | 2512 VM_ENTRY_LOAD_BNDCFGS | 2513 VM_ENTRY_PT_CONCEAL_PIP | 2514 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2515 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2516 &_vmentry_control) < 0) 2517 return -EIO; 2518 2519 /* 2520 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2521 * can't be used due to an errata where VM Exit may incorrectly clear 2522 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2523 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2524 */ 2525 if (boot_cpu_data.x86 == 0x6) { 2526 switch (boot_cpu_data.x86_model) { 2527 case 26: /* AAK155 */ 2528 case 30: /* AAP115 */ 2529 case 37: /* AAT100 */ 2530 case 44: /* BC86,AAY89,BD102 */ 2531 case 46: /* BA97 */ 2532 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2533 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2534 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2535 "does not work properly. Using workaround\n"); 2536 break; 2537 default: 2538 break; 2539 } 2540 } 2541 2542 2543 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2544 2545 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2546 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2547 return -EIO; 2548 2549 #ifdef CONFIG_X86_64 2550 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2551 if (vmx_msr_high & (1u<<16)) 2552 return -EIO; 2553 #endif 2554 2555 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2556 if (((vmx_msr_high >> 18) & 15) != 6) 2557 return -EIO; 2558 2559 vmcs_conf->size = vmx_msr_high & 0x1fff; 2560 vmcs_conf->order = get_order(vmcs_conf->size); 2561 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2562 2563 vmcs_conf->revision_id = vmx_msr_low; 2564 2565 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2566 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2567 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2568 vmcs_conf->vmexit_ctrl = _vmexit_control; 2569 vmcs_conf->vmentry_ctrl = _vmentry_control; 2570 2571 if (static_branch_unlikely(&enable_evmcs)) 2572 evmcs_sanitize_exec_ctrls(vmcs_conf); 2573 2574 return 0; 2575 } 2576 2577 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2578 { 2579 int node = cpu_to_node(cpu); 2580 struct page *pages; 2581 struct vmcs *vmcs; 2582 2583 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2584 if (!pages) 2585 return NULL; 2586 vmcs = page_address(pages); 2587 memset(vmcs, 0, vmcs_config.size); 2588 2589 /* KVM supports Enlightened VMCS v1 only */ 2590 if (static_branch_unlikely(&enable_evmcs)) 2591 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2592 else 2593 vmcs->hdr.revision_id = vmcs_config.revision_id; 2594 2595 if (shadow) 2596 vmcs->hdr.shadow_vmcs = 1; 2597 return vmcs; 2598 } 2599 2600 void free_vmcs(struct vmcs *vmcs) 2601 { 2602 free_pages((unsigned long)vmcs, vmcs_config.order); 2603 } 2604 2605 /* 2606 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2607 */ 2608 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2609 { 2610 if (!loaded_vmcs->vmcs) 2611 return; 2612 loaded_vmcs_clear(loaded_vmcs); 2613 free_vmcs(loaded_vmcs->vmcs); 2614 loaded_vmcs->vmcs = NULL; 2615 if (loaded_vmcs->msr_bitmap) 2616 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2617 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2618 } 2619 2620 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2621 { 2622 loaded_vmcs->vmcs = alloc_vmcs(false); 2623 if (!loaded_vmcs->vmcs) 2624 return -ENOMEM; 2625 2626 vmcs_clear(loaded_vmcs->vmcs); 2627 2628 loaded_vmcs->shadow_vmcs = NULL; 2629 loaded_vmcs->hv_timer_soft_disabled = false; 2630 loaded_vmcs->cpu = -1; 2631 loaded_vmcs->launched = 0; 2632 2633 if (cpu_has_vmx_msr_bitmap()) { 2634 loaded_vmcs->msr_bitmap = (unsigned long *) 2635 __get_free_page(GFP_KERNEL_ACCOUNT); 2636 if (!loaded_vmcs->msr_bitmap) 2637 goto out_vmcs; 2638 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2639 2640 if (IS_ENABLED(CONFIG_HYPERV) && 2641 static_branch_unlikely(&enable_evmcs) && 2642 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2643 struct hv_enlightened_vmcs *evmcs = 2644 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2645 2646 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2647 } 2648 } 2649 2650 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2651 memset(&loaded_vmcs->controls_shadow, 0, 2652 sizeof(struct vmcs_controls_shadow)); 2653 2654 return 0; 2655 2656 out_vmcs: 2657 free_loaded_vmcs(loaded_vmcs); 2658 return -ENOMEM; 2659 } 2660 2661 static void free_kvm_area(void) 2662 { 2663 int cpu; 2664 2665 for_each_possible_cpu(cpu) { 2666 free_vmcs(per_cpu(vmxarea, cpu)); 2667 per_cpu(vmxarea, cpu) = NULL; 2668 } 2669 } 2670 2671 static __init int alloc_kvm_area(void) 2672 { 2673 int cpu; 2674 2675 for_each_possible_cpu(cpu) { 2676 struct vmcs *vmcs; 2677 2678 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2679 if (!vmcs) { 2680 free_kvm_area(); 2681 return -ENOMEM; 2682 } 2683 2684 /* 2685 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2686 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2687 * revision_id reported by MSR_IA32_VMX_BASIC. 2688 * 2689 * However, even though not explicitly documented by 2690 * TLFS, VMXArea passed as VMXON argument should 2691 * still be marked with revision_id reported by 2692 * physical CPU. 2693 */ 2694 if (static_branch_unlikely(&enable_evmcs)) 2695 vmcs->hdr.revision_id = vmcs_config.revision_id; 2696 2697 per_cpu(vmxarea, cpu) = vmcs; 2698 } 2699 return 0; 2700 } 2701 2702 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2703 struct kvm_segment *save) 2704 { 2705 if (!emulate_invalid_guest_state) { 2706 /* 2707 * CS and SS RPL should be equal during guest entry according 2708 * to VMX spec, but in reality it is not always so. Since vcpu 2709 * is in the middle of the transition from real mode to 2710 * protected mode it is safe to assume that RPL 0 is a good 2711 * default value. 2712 */ 2713 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2714 save->selector &= ~SEGMENT_RPL_MASK; 2715 save->dpl = save->selector & SEGMENT_RPL_MASK; 2716 save->s = 1; 2717 } 2718 vmx_set_segment(vcpu, save, seg); 2719 } 2720 2721 static void enter_pmode(struct kvm_vcpu *vcpu) 2722 { 2723 unsigned long flags; 2724 struct vcpu_vmx *vmx = to_vmx(vcpu); 2725 2726 /* 2727 * Update real mode segment cache. It may be not up-to-date if sement 2728 * register was written while vcpu was in a guest mode. 2729 */ 2730 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2731 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2732 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2733 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2734 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2735 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2736 2737 vmx->rmode.vm86_active = 0; 2738 2739 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2740 2741 flags = vmcs_readl(GUEST_RFLAGS); 2742 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2743 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2744 vmcs_writel(GUEST_RFLAGS, flags); 2745 2746 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2747 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2748 2749 update_exception_bitmap(vcpu); 2750 2751 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2752 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2753 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2754 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2755 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2756 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2757 } 2758 2759 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2760 { 2761 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2762 struct kvm_segment var = *save; 2763 2764 var.dpl = 0x3; 2765 if (seg == VCPU_SREG_CS) 2766 var.type = 0x3; 2767 2768 if (!emulate_invalid_guest_state) { 2769 var.selector = var.base >> 4; 2770 var.base = var.base & 0xffff0; 2771 var.limit = 0xffff; 2772 var.g = 0; 2773 var.db = 0; 2774 var.present = 1; 2775 var.s = 1; 2776 var.l = 0; 2777 var.unusable = 0; 2778 var.type = 0x3; 2779 var.avl = 0; 2780 if (save->base & 0xf) 2781 printk_once(KERN_WARNING "kvm: segment base is not " 2782 "paragraph aligned when entering " 2783 "protected mode (seg=%d)", seg); 2784 } 2785 2786 vmcs_write16(sf->selector, var.selector); 2787 vmcs_writel(sf->base, var.base); 2788 vmcs_write32(sf->limit, var.limit); 2789 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2790 } 2791 2792 static void enter_rmode(struct kvm_vcpu *vcpu) 2793 { 2794 unsigned long flags; 2795 struct vcpu_vmx *vmx = to_vmx(vcpu); 2796 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2797 2798 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2799 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2800 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2801 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2802 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2803 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2804 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2805 2806 vmx->rmode.vm86_active = 1; 2807 2808 /* 2809 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2810 * vcpu. Warn the user that an update is overdue. 2811 */ 2812 if (!kvm_vmx->tss_addr) 2813 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2814 "called before entering vcpu\n"); 2815 2816 vmx_segment_cache_clear(vmx); 2817 2818 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2819 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2820 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2821 2822 flags = vmcs_readl(GUEST_RFLAGS); 2823 vmx->rmode.save_rflags = flags; 2824 2825 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2826 2827 vmcs_writel(GUEST_RFLAGS, flags); 2828 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2829 update_exception_bitmap(vcpu); 2830 2831 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2832 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2833 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2834 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2835 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2836 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2837 2838 kvm_mmu_reset_context(vcpu); 2839 } 2840 2841 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2842 { 2843 struct vcpu_vmx *vmx = to_vmx(vcpu); 2844 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2845 2846 if (!msr) 2847 return; 2848 2849 vcpu->arch.efer = efer; 2850 if (efer & EFER_LMA) { 2851 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2852 msr->data = efer; 2853 } else { 2854 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2855 2856 msr->data = efer & ~EFER_LME; 2857 } 2858 setup_msrs(vmx); 2859 } 2860 2861 #ifdef CONFIG_X86_64 2862 2863 static void enter_lmode(struct kvm_vcpu *vcpu) 2864 { 2865 u32 guest_tr_ar; 2866 2867 vmx_segment_cache_clear(to_vmx(vcpu)); 2868 2869 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2870 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2871 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2872 __func__); 2873 vmcs_write32(GUEST_TR_AR_BYTES, 2874 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2875 | VMX_AR_TYPE_BUSY_64_TSS); 2876 } 2877 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2878 } 2879 2880 static void exit_lmode(struct kvm_vcpu *vcpu) 2881 { 2882 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2883 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2884 } 2885 2886 #endif 2887 2888 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu) 2889 { 2890 struct vcpu_vmx *vmx = to_vmx(vcpu); 2891 2892 /* 2893 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as 2894 * the CPU is not required to invalidate guest-physical mappings on 2895 * VM-Entry, even if VPID is disabled. Guest-physical mappings are 2896 * associated with the root EPT structure and not any particular VPID 2897 * (INVVPID also isn't required to invalidate guest-physical mappings). 2898 */ 2899 if (enable_ept) { 2900 ept_sync_global(); 2901 } else if (enable_vpid) { 2902 if (cpu_has_vmx_invvpid_global()) { 2903 vpid_sync_vcpu_global(); 2904 } else { 2905 vpid_sync_vcpu_single(vmx->vpid); 2906 vpid_sync_vcpu_single(vmx->nested.vpid02); 2907 } 2908 } 2909 } 2910 2911 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu) 2912 { 2913 u64 root_hpa = vcpu->arch.mmu->root_hpa; 2914 2915 /* No flush required if the current context is invalid. */ 2916 if (!VALID_PAGE(root_hpa)) 2917 return; 2918 2919 if (enable_ept) 2920 ept_sync_context(construct_eptp(vcpu, root_hpa)); 2921 else if (!is_guest_mode(vcpu)) 2922 vpid_sync_context(to_vmx(vcpu)->vpid); 2923 else 2924 vpid_sync_context(nested_get_vpid02(vcpu)); 2925 } 2926 2927 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2928 { 2929 /* 2930 * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in 2931 * vmx_flush_tlb_guest() for an explanation of why this is ok. 2932 */ 2933 vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr); 2934 } 2935 2936 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu) 2937 { 2938 /* 2939 * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0 2940 * or a vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit 2941 * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is 2942 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed), 2943 * i.e. no explicit INVVPID is necessary. 2944 */ 2945 vpid_sync_context(to_vmx(vcpu)->vpid); 2946 } 2947 2948 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2949 { 2950 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2951 2952 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2953 return; 2954 2955 if (is_pae_paging(vcpu)) { 2956 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2957 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2958 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2959 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2960 } 2961 } 2962 2963 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2964 { 2965 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2966 2967 if (WARN_ON_ONCE(!is_pae_paging(vcpu))) 2968 return; 2969 2970 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2971 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2972 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2973 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2974 2975 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2976 } 2977 2978 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2979 unsigned long cr0, 2980 struct kvm_vcpu *vcpu) 2981 { 2982 struct vcpu_vmx *vmx = to_vmx(vcpu); 2983 2984 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2985 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2986 if (!(cr0 & X86_CR0_PG)) { 2987 /* From paging/starting to nonpaging */ 2988 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2989 CPU_BASED_CR3_STORE_EXITING); 2990 vcpu->arch.cr0 = cr0; 2991 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2992 } else if (!is_paging(vcpu)) { 2993 /* From nonpaging to paging */ 2994 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2995 CPU_BASED_CR3_STORE_EXITING); 2996 vcpu->arch.cr0 = cr0; 2997 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2998 } 2999 3000 if (!(cr0 & X86_CR0_WP)) 3001 *hw_cr0 &= ~X86_CR0_WP; 3002 } 3003 3004 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 3005 { 3006 struct vcpu_vmx *vmx = to_vmx(vcpu); 3007 unsigned long hw_cr0; 3008 3009 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 3010 if (enable_unrestricted_guest) 3011 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 3012 else { 3013 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 3014 3015 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 3016 enter_pmode(vcpu); 3017 3018 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 3019 enter_rmode(vcpu); 3020 } 3021 3022 #ifdef CONFIG_X86_64 3023 if (vcpu->arch.efer & EFER_LME) { 3024 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 3025 enter_lmode(vcpu); 3026 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 3027 exit_lmode(vcpu); 3028 } 3029 #endif 3030 3031 if (enable_ept && !enable_unrestricted_guest) 3032 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 3033 3034 vmcs_writel(CR0_READ_SHADOW, cr0); 3035 vmcs_writel(GUEST_CR0, hw_cr0); 3036 vcpu->arch.cr0 = cr0; 3037 kvm_register_mark_available(vcpu, VCPU_EXREG_CR0); 3038 3039 /* depends on vcpu->arch.cr0 to be set to a new value */ 3040 vmx->emulation_required = emulation_required(vcpu); 3041 } 3042 3043 static int vmx_get_tdp_level(struct kvm_vcpu *vcpu) 3044 { 3045 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 3046 return 5; 3047 return 4; 3048 } 3049 3050 static int get_ept_level(struct kvm_vcpu *vcpu) 3051 { 3052 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu))) 3053 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu)); 3054 3055 return vmx_get_tdp_level(vcpu); 3056 } 3057 3058 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 3059 { 3060 u64 eptp = VMX_EPTP_MT_WB; 3061 3062 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 3063 3064 if (enable_ept_ad_bits && 3065 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 3066 eptp |= VMX_EPTP_AD_ENABLE_BIT; 3067 eptp |= (root_hpa & PAGE_MASK); 3068 3069 return eptp; 3070 } 3071 3072 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd) 3073 { 3074 struct kvm *kvm = vcpu->kvm; 3075 bool update_guest_cr3 = true; 3076 unsigned long guest_cr3; 3077 u64 eptp; 3078 3079 if (enable_ept) { 3080 eptp = construct_eptp(vcpu, pgd); 3081 vmcs_write64(EPT_POINTER, eptp); 3082 3083 if (kvm_x86_ops.tlb_remote_flush) { 3084 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3085 to_vmx(vcpu)->ept_pointer = eptp; 3086 to_kvm_vmx(kvm)->ept_pointers_match 3087 = EPT_POINTERS_CHECK; 3088 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3089 } 3090 3091 if (!enable_unrestricted_guest && !is_paging(vcpu)) 3092 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3093 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 3094 guest_cr3 = vcpu->arch.cr3; 3095 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3096 update_guest_cr3 = false; 3097 ept_load_pdptrs(vcpu); 3098 } else { 3099 guest_cr3 = pgd; 3100 } 3101 3102 if (update_guest_cr3) 3103 vmcs_writel(GUEST_CR3, guest_cr3); 3104 } 3105 3106 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3107 { 3108 struct vcpu_vmx *vmx = to_vmx(vcpu); 3109 /* 3110 * Pass through host's Machine Check Enable value to hw_cr4, which 3111 * is in force while we are in guest mode. Do not let guests control 3112 * this bit, even if host CR4.MCE == 0. 3113 */ 3114 unsigned long hw_cr4; 3115 3116 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3117 if (enable_unrestricted_guest) 3118 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3119 else if (vmx->rmode.vm86_active) 3120 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3121 else 3122 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3123 3124 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3125 if (cr4 & X86_CR4_UMIP) { 3126 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3127 hw_cr4 &= ~X86_CR4_UMIP; 3128 } else if (!is_guest_mode(vcpu) || 3129 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3130 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3131 } 3132 } 3133 3134 if (cr4 & X86_CR4_VMXE) { 3135 /* 3136 * To use VMXON (and later other VMX instructions), a guest 3137 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3138 * So basically the check on whether to allow nested VMX 3139 * is here. We operate under the default treatment of SMM, 3140 * so VMX cannot be enabled under SMM. 3141 */ 3142 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3143 return 1; 3144 } 3145 3146 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3147 return 1; 3148 3149 vcpu->arch.cr4 = cr4; 3150 kvm_register_mark_available(vcpu, VCPU_EXREG_CR4); 3151 3152 if (!enable_unrestricted_guest) { 3153 if (enable_ept) { 3154 if (!is_paging(vcpu)) { 3155 hw_cr4 &= ~X86_CR4_PAE; 3156 hw_cr4 |= X86_CR4_PSE; 3157 } else if (!(cr4 & X86_CR4_PAE)) { 3158 hw_cr4 &= ~X86_CR4_PAE; 3159 } 3160 } 3161 3162 /* 3163 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3164 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3165 * to be manually disabled when guest switches to non-paging 3166 * mode. 3167 * 3168 * If !enable_unrestricted_guest, the CPU is always running 3169 * with CR0.PG=1 and CR4 needs to be modified. 3170 * If enable_unrestricted_guest, the CPU automatically 3171 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3172 */ 3173 if (!is_paging(vcpu)) 3174 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3175 } 3176 3177 vmcs_writel(CR4_READ_SHADOW, cr4); 3178 vmcs_writel(GUEST_CR4, hw_cr4); 3179 return 0; 3180 } 3181 3182 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3183 { 3184 struct vcpu_vmx *vmx = to_vmx(vcpu); 3185 u32 ar; 3186 3187 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3188 *var = vmx->rmode.segs[seg]; 3189 if (seg == VCPU_SREG_TR 3190 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3191 return; 3192 var->base = vmx_read_guest_seg_base(vmx, seg); 3193 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3194 return; 3195 } 3196 var->base = vmx_read_guest_seg_base(vmx, seg); 3197 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3198 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3199 ar = vmx_read_guest_seg_ar(vmx, seg); 3200 var->unusable = (ar >> 16) & 1; 3201 var->type = ar & 15; 3202 var->s = (ar >> 4) & 1; 3203 var->dpl = (ar >> 5) & 3; 3204 /* 3205 * Some userspaces do not preserve unusable property. Since usable 3206 * segment has to be present according to VMX spec we can use present 3207 * property to amend userspace bug by making unusable segment always 3208 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3209 * segment as unusable. 3210 */ 3211 var->present = !var->unusable; 3212 var->avl = (ar >> 12) & 1; 3213 var->l = (ar >> 13) & 1; 3214 var->db = (ar >> 14) & 1; 3215 var->g = (ar >> 15) & 1; 3216 } 3217 3218 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3219 { 3220 struct kvm_segment s; 3221 3222 if (to_vmx(vcpu)->rmode.vm86_active) { 3223 vmx_get_segment(vcpu, &s, seg); 3224 return s.base; 3225 } 3226 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3227 } 3228 3229 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3230 { 3231 struct vcpu_vmx *vmx = to_vmx(vcpu); 3232 3233 if (unlikely(vmx->rmode.vm86_active)) 3234 return 0; 3235 else { 3236 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3237 return VMX_AR_DPL(ar); 3238 } 3239 } 3240 3241 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3242 { 3243 u32 ar; 3244 3245 if (var->unusable || !var->present) 3246 ar = 1 << 16; 3247 else { 3248 ar = var->type & 15; 3249 ar |= (var->s & 1) << 4; 3250 ar |= (var->dpl & 3) << 5; 3251 ar |= (var->present & 1) << 7; 3252 ar |= (var->avl & 1) << 12; 3253 ar |= (var->l & 1) << 13; 3254 ar |= (var->db & 1) << 14; 3255 ar |= (var->g & 1) << 15; 3256 } 3257 3258 return ar; 3259 } 3260 3261 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3262 { 3263 struct vcpu_vmx *vmx = to_vmx(vcpu); 3264 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3265 3266 vmx_segment_cache_clear(vmx); 3267 3268 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3269 vmx->rmode.segs[seg] = *var; 3270 if (seg == VCPU_SREG_TR) 3271 vmcs_write16(sf->selector, var->selector); 3272 else if (var->s) 3273 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3274 goto out; 3275 } 3276 3277 vmcs_writel(sf->base, var->base); 3278 vmcs_write32(sf->limit, var->limit); 3279 vmcs_write16(sf->selector, var->selector); 3280 3281 /* 3282 * Fix the "Accessed" bit in AR field of segment registers for older 3283 * qemu binaries. 3284 * IA32 arch specifies that at the time of processor reset the 3285 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3286 * is setting it to 0 in the userland code. This causes invalid guest 3287 * state vmexit when "unrestricted guest" mode is turned on. 3288 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3289 * tree. Newer qemu binaries with that qemu fix would not need this 3290 * kvm hack. 3291 */ 3292 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3293 var->type |= 0x1; /* Accessed */ 3294 3295 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3296 3297 out: 3298 vmx->emulation_required = emulation_required(vcpu); 3299 } 3300 3301 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3302 { 3303 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3304 3305 *db = (ar >> 14) & 1; 3306 *l = (ar >> 13) & 1; 3307 } 3308 3309 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3310 { 3311 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3312 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3313 } 3314 3315 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3316 { 3317 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3318 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3319 } 3320 3321 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3322 { 3323 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3324 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3325 } 3326 3327 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3328 { 3329 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3330 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3331 } 3332 3333 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3334 { 3335 struct kvm_segment var; 3336 u32 ar; 3337 3338 vmx_get_segment(vcpu, &var, seg); 3339 var.dpl = 0x3; 3340 if (seg == VCPU_SREG_CS) 3341 var.type = 0x3; 3342 ar = vmx_segment_access_rights(&var); 3343 3344 if (var.base != (var.selector << 4)) 3345 return false; 3346 if (var.limit != 0xffff) 3347 return false; 3348 if (ar != 0xf3) 3349 return false; 3350 3351 return true; 3352 } 3353 3354 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3355 { 3356 struct kvm_segment cs; 3357 unsigned int cs_rpl; 3358 3359 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3360 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3361 3362 if (cs.unusable) 3363 return false; 3364 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3365 return false; 3366 if (!cs.s) 3367 return false; 3368 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3369 if (cs.dpl > cs_rpl) 3370 return false; 3371 } else { 3372 if (cs.dpl != cs_rpl) 3373 return false; 3374 } 3375 if (!cs.present) 3376 return false; 3377 3378 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3379 return true; 3380 } 3381 3382 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3383 { 3384 struct kvm_segment ss; 3385 unsigned int ss_rpl; 3386 3387 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3388 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3389 3390 if (ss.unusable) 3391 return true; 3392 if (ss.type != 3 && ss.type != 7) 3393 return false; 3394 if (!ss.s) 3395 return false; 3396 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3397 return false; 3398 if (!ss.present) 3399 return false; 3400 3401 return true; 3402 } 3403 3404 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3405 { 3406 struct kvm_segment var; 3407 unsigned int rpl; 3408 3409 vmx_get_segment(vcpu, &var, seg); 3410 rpl = var.selector & SEGMENT_RPL_MASK; 3411 3412 if (var.unusable) 3413 return true; 3414 if (!var.s) 3415 return false; 3416 if (!var.present) 3417 return false; 3418 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3419 if (var.dpl < rpl) /* DPL < RPL */ 3420 return false; 3421 } 3422 3423 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3424 * rights flags 3425 */ 3426 return true; 3427 } 3428 3429 static bool tr_valid(struct kvm_vcpu *vcpu) 3430 { 3431 struct kvm_segment tr; 3432 3433 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3434 3435 if (tr.unusable) 3436 return false; 3437 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3438 return false; 3439 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3440 return false; 3441 if (!tr.present) 3442 return false; 3443 3444 return true; 3445 } 3446 3447 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3448 { 3449 struct kvm_segment ldtr; 3450 3451 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3452 3453 if (ldtr.unusable) 3454 return true; 3455 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3456 return false; 3457 if (ldtr.type != 2) 3458 return false; 3459 if (!ldtr.present) 3460 return false; 3461 3462 return true; 3463 } 3464 3465 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3466 { 3467 struct kvm_segment cs, ss; 3468 3469 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3470 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3471 3472 return ((cs.selector & SEGMENT_RPL_MASK) == 3473 (ss.selector & SEGMENT_RPL_MASK)); 3474 } 3475 3476 /* 3477 * Check if guest state is valid. Returns true if valid, false if 3478 * not. 3479 * We assume that registers are always usable 3480 */ 3481 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3482 { 3483 if (enable_unrestricted_guest) 3484 return true; 3485 3486 /* real mode guest state checks */ 3487 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3488 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3489 return false; 3490 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3491 return false; 3492 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3493 return false; 3494 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3495 return false; 3496 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3497 return false; 3498 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3499 return false; 3500 } else { 3501 /* protected mode guest state checks */ 3502 if (!cs_ss_rpl_check(vcpu)) 3503 return false; 3504 if (!code_segment_valid(vcpu)) 3505 return false; 3506 if (!stack_segment_valid(vcpu)) 3507 return false; 3508 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3509 return false; 3510 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3511 return false; 3512 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3513 return false; 3514 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3515 return false; 3516 if (!tr_valid(vcpu)) 3517 return false; 3518 if (!ldtr_valid(vcpu)) 3519 return false; 3520 } 3521 /* TODO: 3522 * - Add checks on RIP 3523 * - Add checks on RFLAGS 3524 */ 3525 3526 return true; 3527 } 3528 3529 static int init_rmode_tss(struct kvm *kvm) 3530 { 3531 gfn_t fn; 3532 u16 data = 0; 3533 int idx, r; 3534 3535 idx = srcu_read_lock(&kvm->srcu); 3536 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3537 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3538 if (r < 0) 3539 goto out; 3540 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3541 r = kvm_write_guest_page(kvm, fn++, &data, 3542 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3543 if (r < 0) 3544 goto out; 3545 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3546 if (r < 0) 3547 goto out; 3548 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3549 if (r < 0) 3550 goto out; 3551 data = ~0; 3552 r = kvm_write_guest_page(kvm, fn, &data, 3553 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3554 sizeof(u8)); 3555 out: 3556 srcu_read_unlock(&kvm->srcu, idx); 3557 return r; 3558 } 3559 3560 static int init_rmode_identity_map(struct kvm *kvm) 3561 { 3562 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3563 int i, r = 0; 3564 kvm_pfn_t identity_map_pfn; 3565 u32 tmp; 3566 3567 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3568 mutex_lock(&kvm->slots_lock); 3569 3570 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3571 goto out; 3572 3573 if (!kvm_vmx->ept_identity_map_addr) 3574 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3575 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3576 3577 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3578 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3579 if (r < 0) 3580 goto out; 3581 3582 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3583 if (r < 0) 3584 goto out; 3585 /* Set up identity-mapping pagetable for EPT in real mode */ 3586 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3587 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3588 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3589 r = kvm_write_guest_page(kvm, identity_map_pfn, 3590 &tmp, i * sizeof(tmp), sizeof(tmp)); 3591 if (r < 0) 3592 goto out; 3593 } 3594 kvm_vmx->ept_identity_pagetable_done = true; 3595 3596 out: 3597 mutex_unlock(&kvm->slots_lock); 3598 return r; 3599 } 3600 3601 static void seg_setup(int seg) 3602 { 3603 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3604 unsigned int ar; 3605 3606 vmcs_write16(sf->selector, 0); 3607 vmcs_writel(sf->base, 0); 3608 vmcs_write32(sf->limit, 0xffff); 3609 ar = 0x93; 3610 if (seg == VCPU_SREG_CS) 3611 ar |= 0x08; /* code segment */ 3612 3613 vmcs_write32(sf->ar_bytes, ar); 3614 } 3615 3616 static int alloc_apic_access_page(struct kvm *kvm) 3617 { 3618 struct page *page; 3619 int r = 0; 3620 3621 mutex_lock(&kvm->slots_lock); 3622 if (kvm->arch.apic_access_page_done) 3623 goto out; 3624 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3625 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3626 if (r) 3627 goto out; 3628 3629 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3630 if (is_error_page(page)) { 3631 r = -EFAULT; 3632 goto out; 3633 } 3634 3635 /* 3636 * Do not pin the page in memory, so that memory hot-unplug 3637 * is able to migrate it. 3638 */ 3639 put_page(page); 3640 kvm->arch.apic_access_page_done = true; 3641 out: 3642 mutex_unlock(&kvm->slots_lock); 3643 return r; 3644 } 3645 3646 int allocate_vpid(void) 3647 { 3648 int vpid; 3649 3650 if (!enable_vpid) 3651 return 0; 3652 spin_lock(&vmx_vpid_lock); 3653 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3654 if (vpid < VMX_NR_VPIDS) 3655 __set_bit(vpid, vmx_vpid_bitmap); 3656 else 3657 vpid = 0; 3658 spin_unlock(&vmx_vpid_lock); 3659 return vpid; 3660 } 3661 3662 void free_vpid(int vpid) 3663 { 3664 if (!enable_vpid || vpid == 0) 3665 return; 3666 spin_lock(&vmx_vpid_lock); 3667 __clear_bit(vpid, vmx_vpid_bitmap); 3668 spin_unlock(&vmx_vpid_lock); 3669 } 3670 3671 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3672 u32 msr, int type) 3673 { 3674 int f = sizeof(unsigned long); 3675 3676 if (!cpu_has_vmx_msr_bitmap()) 3677 return; 3678 3679 if (static_branch_unlikely(&enable_evmcs)) 3680 evmcs_touch_msr_bitmap(); 3681 3682 /* 3683 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3684 * have the write-low and read-high bitmap offsets the wrong way round. 3685 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3686 */ 3687 if (msr <= 0x1fff) { 3688 if (type & MSR_TYPE_R) 3689 /* read-low */ 3690 __clear_bit(msr, msr_bitmap + 0x000 / f); 3691 3692 if (type & MSR_TYPE_W) 3693 /* write-low */ 3694 __clear_bit(msr, msr_bitmap + 0x800 / f); 3695 3696 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3697 msr &= 0x1fff; 3698 if (type & MSR_TYPE_R) 3699 /* read-high */ 3700 __clear_bit(msr, msr_bitmap + 0x400 / f); 3701 3702 if (type & MSR_TYPE_W) 3703 /* write-high */ 3704 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3705 3706 } 3707 } 3708 3709 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3710 u32 msr, int type) 3711 { 3712 int f = sizeof(unsigned long); 3713 3714 if (!cpu_has_vmx_msr_bitmap()) 3715 return; 3716 3717 if (static_branch_unlikely(&enable_evmcs)) 3718 evmcs_touch_msr_bitmap(); 3719 3720 /* 3721 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3722 * have the write-low and read-high bitmap offsets the wrong way round. 3723 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3724 */ 3725 if (msr <= 0x1fff) { 3726 if (type & MSR_TYPE_R) 3727 /* read-low */ 3728 __set_bit(msr, msr_bitmap + 0x000 / f); 3729 3730 if (type & MSR_TYPE_W) 3731 /* write-low */ 3732 __set_bit(msr, msr_bitmap + 0x800 / f); 3733 3734 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3735 msr &= 0x1fff; 3736 if (type & MSR_TYPE_R) 3737 /* read-high */ 3738 __set_bit(msr, msr_bitmap + 0x400 / f); 3739 3740 if (type & MSR_TYPE_W) 3741 /* write-high */ 3742 __set_bit(msr, msr_bitmap + 0xc00 / f); 3743 3744 } 3745 } 3746 3747 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3748 u32 msr, int type, bool value) 3749 { 3750 if (value) 3751 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3752 else 3753 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3754 } 3755 3756 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3757 { 3758 u8 mode = 0; 3759 3760 if (cpu_has_secondary_exec_ctrls() && 3761 (secondary_exec_controls_get(to_vmx(vcpu)) & 3762 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3763 mode |= MSR_BITMAP_MODE_X2APIC; 3764 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3765 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3766 } 3767 3768 return mode; 3769 } 3770 3771 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3772 u8 mode) 3773 { 3774 int msr; 3775 3776 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3777 unsigned word = msr / BITS_PER_LONG; 3778 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3779 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3780 } 3781 3782 if (mode & MSR_BITMAP_MODE_X2APIC) { 3783 /* 3784 * TPR reads and writes can be virtualized even if virtual interrupt 3785 * delivery is not in use. 3786 */ 3787 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3788 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3789 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3790 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3791 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3792 } 3793 } 3794 } 3795 3796 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3797 { 3798 struct vcpu_vmx *vmx = to_vmx(vcpu); 3799 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3800 u8 mode = vmx_msr_bitmap_mode(vcpu); 3801 u8 changed = mode ^ vmx->msr_bitmap_mode; 3802 3803 if (!changed) 3804 return; 3805 3806 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3807 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3808 3809 vmx->msr_bitmap_mode = mode; 3810 } 3811 3812 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3813 { 3814 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3815 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3816 u32 i; 3817 3818 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3819 MSR_TYPE_RW, flag); 3820 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3821 MSR_TYPE_RW, flag); 3822 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3823 MSR_TYPE_RW, flag); 3824 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3825 MSR_TYPE_RW, flag); 3826 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3827 vmx_set_intercept_for_msr(msr_bitmap, 3828 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3829 vmx_set_intercept_for_msr(msr_bitmap, 3830 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3831 } 3832 } 3833 3834 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3835 { 3836 struct vcpu_vmx *vmx = to_vmx(vcpu); 3837 void *vapic_page; 3838 u32 vppr; 3839 int rvi; 3840 3841 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3842 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3843 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3844 return false; 3845 3846 rvi = vmx_get_rvi(); 3847 3848 vapic_page = vmx->nested.virtual_apic_map.hva; 3849 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3850 3851 return ((rvi & 0xf0) > (vppr & 0xf0)); 3852 } 3853 3854 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3855 bool nested) 3856 { 3857 #ifdef CONFIG_SMP 3858 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3859 3860 if (vcpu->mode == IN_GUEST_MODE) { 3861 /* 3862 * The vector of interrupt to be delivered to vcpu had 3863 * been set in PIR before this function. 3864 * 3865 * Following cases will be reached in this block, and 3866 * we always send a notification event in all cases as 3867 * explained below. 3868 * 3869 * Case 1: vcpu keeps in non-root mode. Sending a 3870 * notification event posts the interrupt to vcpu. 3871 * 3872 * Case 2: vcpu exits to root mode and is still 3873 * runnable. PIR will be synced to vIRR before the 3874 * next vcpu entry. Sending a notification event in 3875 * this case has no effect, as vcpu is not in root 3876 * mode. 3877 * 3878 * Case 3: vcpu exits to root mode and is blocked. 3879 * vcpu_block() has already synced PIR to vIRR and 3880 * never blocks vcpu if vIRR is not cleared. Therefore, 3881 * a blocked vcpu here does not wait for any requested 3882 * interrupts in PIR, and sending a notification event 3883 * which has no effect is safe here. 3884 */ 3885 3886 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3887 return true; 3888 } 3889 #endif 3890 return false; 3891 } 3892 3893 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3894 int vector) 3895 { 3896 struct vcpu_vmx *vmx = to_vmx(vcpu); 3897 3898 if (is_guest_mode(vcpu) && 3899 vector == vmx->nested.posted_intr_nv) { 3900 /* 3901 * If a posted intr is not recognized by hardware, 3902 * we will accomplish it in the next vmentry. 3903 */ 3904 vmx->nested.pi_pending = true; 3905 kvm_make_request(KVM_REQ_EVENT, vcpu); 3906 /* the PIR and ON have been set by L1. */ 3907 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3908 kvm_vcpu_kick(vcpu); 3909 return 0; 3910 } 3911 return -1; 3912 } 3913 /* 3914 * Send interrupt to vcpu via posted interrupt way. 3915 * 1. If target vcpu is running(non-root mode), send posted interrupt 3916 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3917 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3918 * interrupt from PIR in next vmentry. 3919 */ 3920 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3921 { 3922 struct vcpu_vmx *vmx = to_vmx(vcpu); 3923 int r; 3924 3925 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3926 if (!r) 3927 return 0; 3928 3929 if (!vcpu->arch.apicv_active) 3930 return -1; 3931 3932 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3933 return 0; 3934 3935 /* If a previous notification has sent the IPI, nothing to do. */ 3936 if (pi_test_and_set_on(&vmx->pi_desc)) 3937 return 0; 3938 3939 if (vcpu != kvm_get_running_vcpu() && 3940 !kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3941 kvm_vcpu_kick(vcpu); 3942 3943 return 0; 3944 } 3945 3946 /* 3947 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3948 * will not change in the lifetime of the guest. 3949 * Note that host-state that does change is set elsewhere. E.g., host-state 3950 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3951 */ 3952 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3953 { 3954 u32 low32, high32; 3955 unsigned long tmpl; 3956 unsigned long cr0, cr3, cr4; 3957 3958 cr0 = read_cr0(); 3959 WARN_ON(cr0 & X86_CR0_TS); 3960 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3961 3962 /* 3963 * Save the most likely value for this task's CR3 in the VMCS. 3964 * We can't use __get_current_cr3_fast() because we're not atomic. 3965 */ 3966 cr3 = __read_cr3(); 3967 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3968 vmx->loaded_vmcs->host_state.cr3 = cr3; 3969 3970 /* Save the most likely value for this task's CR4 in the VMCS. */ 3971 cr4 = cr4_read_shadow(); 3972 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3973 vmx->loaded_vmcs->host_state.cr4 = cr4; 3974 3975 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3976 #ifdef CONFIG_X86_64 3977 /* 3978 * Load null selectors, so we can avoid reloading them in 3979 * vmx_prepare_switch_to_host(), in case userspace uses 3980 * the null selectors too (the expected case). 3981 */ 3982 vmcs_write16(HOST_DS_SELECTOR, 0); 3983 vmcs_write16(HOST_ES_SELECTOR, 0); 3984 #else 3985 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3986 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3987 #endif 3988 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3989 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3990 3991 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3992 3993 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3994 3995 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3996 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3997 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3998 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3999 4000 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 4001 rdmsr(MSR_IA32_CR_PAT, low32, high32); 4002 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 4003 } 4004 4005 if (cpu_has_load_ia32_efer()) 4006 vmcs_write64(HOST_IA32_EFER, host_efer); 4007 } 4008 4009 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 4010 { 4011 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 4012 if (enable_ept) 4013 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 4014 if (is_guest_mode(&vmx->vcpu)) 4015 vmx->vcpu.arch.cr4_guest_owned_bits &= 4016 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 4017 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 4018 } 4019 4020 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 4021 { 4022 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 4023 4024 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 4025 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 4026 4027 if (!enable_vnmi) 4028 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 4029 4030 if (!enable_preemption_timer) 4031 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 4032 4033 return pin_based_exec_ctrl; 4034 } 4035 4036 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 4037 { 4038 struct vcpu_vmx *vmx = to_vmx(vcpu); 4039 4040 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4041 if (cpu_has_secondary_exec_ctrls()) { 4042 if (kvm_vcpu_apicv_active(vcpu)) 4043 secondary_exec_controls_setbit(vmx, 4044 SECONDARY_EXEC_APIC_REGISTER_VIRT | 4045 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4046 else 4047 secondary_exec_controls_clearbit(vmx, 4048 SECONDARY_EXEC_APIC_REGISTER_VIRT | 4049 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4050 } 4051 4052 if (cpu_has_vmx_msr_bitmap()) 4053 vmx_update_msr_bitmap(vcpu); 4054 } 4055 4056 u32 vmx_exec_control(struct vcpu_vmx *vmx) 4057 { 4058 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 4059 4060 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 4061 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 4062 4063 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 4064 exec_control &= ~CPU_BASED_TPR_SHADOW; 4065 #ifdef CONFIG_X86_64 4066 exec_control |= CPU_BASED_CR8_STORE_EXITING | 4067 CPU_BASED_CR8_LOAD_EXITING; 4068 #endif 4069 } 4070 if (!enable_ept) 4071 exec_control |= CPU_BASED_CR3_STORE_EXITING | 4072 CPU_BASED_CR3_LOAD_EXITING | 4073 CPU_BASED_INVLPG_EXITING; 4074 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 4075 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 4076 CPU_BASED_MONITOR_EXITING); 4077 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 4078 exec_control &= ~CPU_BASED_HLT_EXITING; 4079 return exec_control; 4080 } 4081 4082 4083 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 4084 { 4085 struct kvm_vcpu *vcpu = &vmx->vcpu; 4086 4087 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 4088 4089 if (vmx_pt_mode_is_system()) 4090 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 4091 if (!cpu_need_virtualize_apic_accesses(vcpu)) 4092 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4093 if (vmx->vpid == 0) 4094 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4095 if (!enable_ept) { 4096 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4097 enable_unrestricted_guest = 0; 4098 } 4099 if (!enable_unrestricted_guest) 4100 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4101 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4102 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4103 if (!kvm_vcpu_apicv_active(vcpu)) 4104 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4105 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4106 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4107 4108 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4109 * in vmx_set_cr4. */ 4110 exec_control &= ~SECONDARY_EXEC_DESC; 4111 4112 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4113 (handle_vmptrld). 4114 We can NOT enable shadow_vmcs here because we don't have yet 4115 a current VMCS12 4116 */ 4117 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4118 4119 if (!enable_pml) 4120 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4121 4122 if (vmx_xsaves_supported()) { 4123 /* Exposing XSAVES only when XSAVE is exposed */ 4124 bool xsaves_enabled = 4125 boot_cpu_has(X86_FEATURE_XSAVE) && 4126 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4127 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4128 4129 vcpu->arch.xsaves_enabled = xsaves_enabled; 4130 4131 if (!xsaves_enabled) 4132 exec_control &= ~SECONDARY_EXEC_XSAVES; 4133 4134 if (nested) { 4135 if (xsaves_enabled) 4136 vmx->nested.msrs.secondary_ctls_high |= 4137 SECONDARY_EXEC_XSAVES; 4138 else 4139 vmx->nested.msrs.secondary_ctls_high &= 4140 ~SECONDARY_EXEC_XSAVES; 4141 } 4142 } 4143 4144 if (cpu_has_vmx_rdtscp()) { 4145 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4146 if (!rdtscp_enabled) 4147 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4148 4149 if (nested) { 4150 if (rdtscp_enabled) 4151 vmx->nested.msrs.secondary_ctls_high |= 4152 SECONDARY_EXEC_RDTSCP; 4153 else 4154 vmx->nested.msrs.secondary_ctls_high &= 4155 ~SECONDARY_EXEC_RDTSCP; 4156 } 4157 } 4158 4159 if (cpu_has_vmx_invpcid()) { 4160 /* Exposing INVPCID only when PCID is exposed */ 4161 bool invpcid_enabled = 4162 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4163 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4164 4165 if (!invpcid_enabled) { 4166 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4167 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4168 } 4169 4170 if (nested) { 4171 if (invpcid_enabled) 4172 vmx->nested.msrs.secondary_ctls_high |= 4173 SECONDARY_EXEC_ENABLE_INVPCID; 4174 else 4175 vmx->nested.msrs.secondary_ctls_high &= 4176 ~SECONDARY_EXEC_ENABLE_INVPCID; 4177 } 4178 } 4179 4180 if (vmx_rdrand_supported()) { 4181 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4182 if (rdrand_enabled) 4183 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4184 4185 if (nested) { 4186 if (rdrand_enabled) 4187 vmx->nested.msrs.secondary_ctls_high |= 4188 SECONDARY_EXEC_RDRAND_EXITING; 4189 else 4190 vmx->nested.msrs.secondary_ctls_high &= 4191 ~SECONDARY_EXEC_RDRAND_EXITING; 4192 } 4193 } 4194 4195 if (vmx_rdseed_supported()) { 4196 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4197 if (rdseed_enabled) 4198 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4199 4200 if (nested) { 4201 if (rdseed_enabled) 4202 vmx->nested.msrs.secondary_ctls_high |= 4203 SECONDARY_EXEC_RDSEED_EXITING; 4204 else 4205 vmx->nested.msrs.secondary_ctls_high &= 4206 ~SECONDARY_EXEC_RDSEED_EXITING; 4207 } 4208 } 4209 4210 if (vmx_waitpkg_supported()) { 4211 bool waitpkg_enabled = 4212 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4213 4214 if (!waitpkg_enabled) 4215 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4216 4217 if (nested) { 4218 if (waitpkg_enabled) 4219 vmx->nested.msrs.secondary_ctls_high |= 4220 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4221 else 4222 vmx->nested.msrs.secondary_ctls_high &= 4223 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4224 } 4225 } 4226 4227 vmx->secondary_exec_control = exec_control; 4228 } 4229 4230 static void ept_set_mmio_spte_mask(void) 4231 { 4232 /* 4233 * EPT Misconfigurations can be generated if the value of bits 2:0 4234 * of an EPT paging-structure entry is 110b (write/execute). 4235 */ 4236 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 0); 4237 } 4238 4239 #define VMX_XSS_EXIT_BITMAP 0 4240 4241 /* 4242 * Noting that the initialization of Guest-state Area of VMCS is in 4243 * vmx_vcpu_reset(). 4244 */ 4245 static void init_vmcs(struct vcpu_vmx *vmx) 4246 { 4247 if (nested) 4248 nested_vmx_set_vmcs_shadowing_bitmap(); 4249 4250 if (cpu_has_vmx_msr_bitmap()) 4251 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4252 4253 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4254 4255 /* Control */ 4256 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4257 4258 exec_controls_set(vmx, vmx_exec_control(vmx)); 4259 4260 if (cpu_has_secondary_exec_ctrls()) { 4261 vmx_compute_secondary_exec_control(vmx); 4262 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4263 } 4264 4265 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4266 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4267 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4268 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4269 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4270 4271 vmcs_write16(GUEST_INTR_STATUS, 0); 4272 4273 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4274 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4275 } 4276 4277 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4278 vmcs_write32(PLE_GAP, ple_gap); 4279 vmx->ple_window = ple_window; 4280 vmx->ple_window_dirty = true; 4281 } 4282 4283 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4284 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4285 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4286 4287 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4288 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4289 vmx_set_constant_host_state(vmx); 4290 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4291 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4292 4293 if (cpu_has_vmx_vmfunc()) 4294 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4295 4296 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4297 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4298 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4299 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4300 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4301 4302 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4303 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4304 4305 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4306 4307 /* 22.2.1, 20.8.1 */ 4308 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4309 4310 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4311 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4312 4313 set_cr4_guest_host_mask(vmx); 4314 4315 if (vmx->vpid != 0) 4316 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4317 4318 if (vmx_xsaves_supported()) 4319 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4320 4321 if (enable_pml) { 4322 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4323 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4324 } 4325 4326 if (cpu_has_vmx_encls_vmexit()) 4327 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4328 4329 if (vmx_pt_mode_is_host_guest()) { 4330 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4331 /* Bit[6~0] are forced to 1, writes are ignored. */ 4332 vmx->pt_desc.guest.output_mask = 0x7F; 4333 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4334 } 4335 } 4336 4337 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4338 { 4339 struct vcpu_vmx *vmx = to_vmx(vcpu); 4340 struct msr_data apic_base_msr; 4341 u64 cr0; 4342 4343 vmx->rmode.vm86_active = 0; 4344 vmx->spec_ctrl = 0; 4345 4346 vmx->msr_ia32_umwait_control = 0; 4347 4348 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4349 vmx->hv_deadline_tsc = -1; 4350 kvm_set_cr8(vcpu, 0); 4351 4352 if (!init_event) { 4353 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4354 MSR_IA32_APICBASE_ENABLE; 4355 if (kvm_vcpu_is_reset_bsp(vcpu)) 4356 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4357 apic_base_msr.host_initiated = true; 4358 kvm_set_apic_base(vcpu, &apic_base_msr); 4359 } 4360 4361 vmx_segment_cache_clear(vmx); 4362 4363 seg_setup(VCPU_SREG_CS); 4364 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4365 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4366 4367 seg_setup(VCPU_SREG_DS); 4368 seg_setup(VCPU_SREG_ES); 4369 seg_setup(VCPU_SREG_FS); 4370 seg_setup(VCPU_SREG_GS); 4371 seg_setup(VCPU_SREG_SS); 4372 4373 vmcs_write16(GUEST_TR_SELECTOR, 0); 4374 vmcs_writel(GUEST_TR_BASE, 0); 4375 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4376 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4377 4378 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4379 vmcs_writel(GUEST_LDTR_BASE, 0); 4380 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4381 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4382 4383 if (!init_event) { 4384 vmcs_write32(GUEST_SYSENTER_CS, 0); 4385 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4386 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4387 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4388 } 4389 4390 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4391 kvm_rip_write(vcpu, 0xfff0); 4392 4393 vmcs_writel(GUEST_GDTR_BASE, 0); 4394 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4395 4396 vmcs_writel(GUEST_IDTR_BASE, 0); 4397 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4398 4399 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4400 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4401 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4402 if (kvm_mpx_supported()) 4403 vmcs_write64(GUEST_BNDCFGS, 0); 4404 4405 setup_msrs(vmx); 4406 4407 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4408 4409 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4410 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4411 if (cpu_need_tpr_shadow(vcpu)) 4412 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4413 __pa(vcpu->arch.apic->regs)); 4414 vmcs_write32(TPR_THRESHOLD, 0); 4415 } 4416 4417 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4418 4419 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4420 vmx->vcpu.arch.cr0 = cr0; 4421 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4422 vmx_set_cr4(vcpu, 0); 4423 vmx_set_efer(vcpu, 0); 4424 4425 update_exception_bitmap(vcpu); 4426 4427 vpid_sync_context(vmx->vpid); 4428 if (init_event) 4429 vmx_clear_hlt(vcpu); 4430 } 4431 4432 static void enable_irq_window(struct kvm_vcpu *vcpu) 4433 { 4434 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4435 } 4436 4437 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4438 { 4439 if (!enable_vnmi || 4440 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4441 enable_irq_window(vcpu); 4442 return; 4443 } 4444 4445 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4446 } 4447 4448 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4449 { 4450 struct vcpu_vmx *vmx = to_vmx(vcpu); 4451 uint32_t intr; 4452 int irq = vcpu->arch.interrupt.nr; 4453 4454 trace_kvm_inj_virq(irq); 4455 4456 ++vcpu->stat.irq_injections; 4457 if (vmx->rmode.vm86_active) { 4458 int inc_eip = 0; 4459 if (vcpu->arch.interrupt.soft) 4460 inc_eip = vcpu->arch.event_exit_inst_len; 4461 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4462 return; 4463 } 4464 intr = irq | INTR_INFO_VALID_MASK; 4465 if (vcpu->arch.interrupt.soft) { 4466 intr |= INTR_TYPE_SOFT_INTR; 4467 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4468 vmx->vcpu.arch.event_exit_inst_len); 4469 } else 4470 intr |= INTR_TYPE_EXT_INTR; 4471 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4472 4473 vmx_clear_hlt(vcpu); 4474 } 4475 4476 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4477 { 4478 struct vcpu_vmx *vmx = to_vmx(vcpu); 4479 4480 if (!enable_vnmi) { 4481 /* 4482 * Tracking the NMI-blocked state in software is built upon 4483 * finding the next open IRQ window. This, in turn, depends on 4484 * well-behaving guests: They have to keep IRQs disabled at 4485 * least as long as the NMI handler runs. Otherwise we may 4486 * cause NMI nesting, maybe breaking the guest. But as this is 4487 * highly unlikely, we can live with the residual risk. 4488 */ 4489 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4490 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4491 } 4492 4493 ++vcpu->stat.nmi_injections; 4494 vmx->loaded_vmcs->nmi_known_unmasked = false; 4495 4496 if (vmx->rmode.vm86_active) { 4497 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4498 return; 4499 } 4500 4501 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4502 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4503 4504 vmx_clear_hlt(vcpu); 4505 } 4506 4507 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4508 { 4509 struct vcpu_vmx *vmx = to_vmx(vcpu); 4510 bool masked; 4511 4512 if (!enable_vnmi) 4513 return vmx->loaded_vmcs->soft_vnmi_blocked; 4514 if (vmx->loaded_vmcs->nmi_known_unmasked) 4515 return false; 4516 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4517 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4518 return masked; 4519 } 4520 4521 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4522 { 4523 struct vcpu_vmx *vmx = to_vmx(vcpu); 4524 4525 if (!enable_vnmi) { 4526 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4527 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4528 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4529 } 4530 } else { 4531 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4532 if (masked) 4533 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4534 GUEST_INTR_STATE_NMI); 4535 else 4536 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4537 GUEST_INTR_STATE_NMI); 4538 } 4539 } 4540 4541 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu) 4542 { 4543 if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu)) 4544 return false; 4545 4546 if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4547 return true; 4548 4549 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4550 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | 4551 GUEST_INTR_STATE_NMI)); 4552 } 4553 4554 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection) 4555 { 4556 if (to_vmx(vcpu)->nested.nested_run_pending) 4557 return -EBUSY; 4558 4559 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */ 4560 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu)) 4561 return -EBUSY; 4562 4563 return !vmx_nmi_blocked(vcpu); 4564 } 4565 4566 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu) 4567 { 4568 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) 4569 return false; 4570 4571 return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) || 4572 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4573 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4574 } 4575 4576 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection) 4577 { 4578 if (to_vmx(vcpu)->nested.nested_run_pending) 4579 return -EBUSY; 4580 4581 /* 4582 * An IRQ must not be injected into L2 if it's supposed to VM-Exit, 4583 * e.g. if the IRQ arrived asynchronously after checking nested events. 4584 */ 4585 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) 4586 return -EBUSY; 4587 4588 return !vmx_interrupt_blocked(vcpu); 4589 } 4590 4591 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4592 { 4593 int ret; 4594 4595 if (enable_unrestricted_guest) 4596 return 0; 4597 4598 mutex_lock(&kvm->slots_lock); 4599 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4600 PAGE_SIZE * 3); 4601 mutex_unlock(&kvm->slots_lock); 4602 4603 if (ret) 4604 return ret; 4605 to_kvm_vmx(kvm)->tss_addr = addr; 4606 return init_rmode_tss(kvm); 4607 } 4608 4609 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4610 { 4611 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4612 return 0; 4613 } 4614 4615 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4616 { 4617 switch (vec) { 4618 case BP_VECTOR: 4619 /* 4620 * Update instruction length as we may reinject the exception 4621 * from user space while in guest debugging mode. 4622 */ 4623 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4624 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4625 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4626 return false; 4627 /* fall through */ 4628 case DB_VECTOR: 4629 return !(vcpu->guest_debug & 4630 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)); 4631 case DE_VECTOR: 4632 case OF_VECTOR: 4633 case BR_VECTOR: 4634 case UD_VECTOR: 4635 case DF_VECTOR: 4636 case SS_VECTOR: 4637 case GP_VECTOR: 4638 case MF_VECTOR: 4639 return true; 4640 } 4641 return false; 4642 } 4643 4644 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4645 int vec, u32 err_code) 4646 { 4647 /* 4648 * Instruction with address size override prefix opcode 0x67 4649 * Cause the #SS fault with 0 error code in VM86 mode. 4650 */ 4651 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4652 if (kvm_emulate_instruction(vcpu, 0)) { 4653 if (vcpu->arch.halt_request) { 4654 vcpu->arch.halt_request = 0; 4655 return kvm_vcpu_halt(vcpu); 4656 } 4657 return 1; 4658 } 4659 return 0; 4660 } 4661 4662 /* 4663 * Forward all other exceptions that are valid in real mode. 4664 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4665 * the required debugging infrastructure rework. 4666 */ 4667 kvm_queue_exception(vcpu, vec); 4668 return 1; 4669 } 4670 4671 /* 4672 * Trigger machine check on the host. We assume all the MSRs are already set up 4673 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4674 * We pass a fake environment to the machine check handler because we want 4675 * the guest to be always treated like user space, no matter what context 4676 * it used internally. 4677 */ 4678 static void kvm_machine_check(void) 4679 { 4680 #if defined(CONFIG_X86_MCE) 4681 struct pt_regs regs = { 4682 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4683 .flags = X86_EFLAGS_IF, 4684 }; 4685 4686 do_machine_check(®s, 0); 4687 #endif 4688 } 4689 4690 static int handle_machine_check(struct kvm_vcpu *vcpu) 4691 { 4692 /* handled by vmx_vcpu_run() */ 4693 return 1; 4694 } 4695 4696 /* 4697 * If the host has split lock detection disabled, then #AC is 4698 * unconditionally injected into the guest, which is the pre split lock 4699 * detection behaviour. 4700 * 4701 * If the host has split lock detection enabled then #AC is 4702 * only injected into the guest when: 4703 * - Guest CPL == 3 (user mode) 4704 * - Guest has #AC detection enabled in CR0 4705 * - Guest EFLAGS has AC bit set 4706 */ 4707 static inline bool guest_inject_ac(struct kvm_vcpu *vcpu) 4708 { 4709 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 4710 return true; 4711 4712 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) && 4713 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC); 4714 } 4715 4716 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4717 { 4718 struct vcpu_vmx *vmx = to_vmx(vcpu); 4719 struct kvm_run *kvm_run = vcpu->run; 4720 u32 intr_info, ex_no, error_code; 4721 unsigned long cr2, rip, dr6; 4722 u32 vect_info; 4723 4724 vect_info = vmx->idt_vectoring_info; 4725 intr_info = vmx_get_intr_info(vcpu); 4726 4727 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4728 return 1; /* handled by handle_exception_nmi_irqoff() */ 4729 4730 if (is_invalid_opcode(intr_info)) 4731 return handle_ud(vcpu); 4732 4733 error_code = 0; 4734 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4735 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4736 4737 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4738 WARN_ON_ONCE(!enable_vmware_backdoor); 4739 4740 /* 4741 * VMware backdoor emulation on #GP interception only handles 4742 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4743 * error code on #GP. 4744 */ 4745 if (error_code) { 4746 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4747 return 1; 4748 } 4749 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4750 } 4751 4752 /* 4753 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4754 * MMIO, it is better to report an internal error. 4755 * See the comments in vmx_handle_exit. 4756 */ 4757 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4758 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4759 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4760 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4761 vcpu->run->internal.ndata = 3; 4762 vcpu->run->internal.data[0] = vect_info; 4763 vcpu->run->internal.data[1] = intr_info; 4764 vcpu->run->internal.data[2] = error_code; 4765 return 0; 4766 } 4767 4768 if (is_page_fault(intr_info)) { 4769 cr2 = vmx_get_exit_qual(vcpu); 4770 /* EPT won't cause page fault directly */ 4771 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_flags && enable_ept); 4772 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4773 } 4774 4775 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4776 4777 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4778 return handle_rmode_exception(vcpu, ex_no, error_code); 4779 4780 switch (ex_no) { 4781 case DB_VECTOR: 4782 dr6 = vmx_get_exit_qual(vcpu); 4783 if (!(vcpu->guest_debug & 4784 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4785 if (is_icebp(intr_info)) 4786 WARN_ON(!skip_emulated_instruction(vcpu)); 4787 4788 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 4789 return 1; 4790 } 4791 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 4792 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4793 /* fall through */ 4794 case BP_VECTOR: 4795 /* 4796 * Update instruction length as we may reinject #BP from 4797 * user space while in guest debugging mode. Reading it for 4798 * #DB as well causes no harm, it is not used in that case. 4799 */ 4800 vmx->vcpu.arch.event_exit_inst_len = 4801 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4802 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4803 rip = kvm_rip_read(vcpu); 4804 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4805 kvm_run->debug.arch.exception = ex_no; 4806 break; 4807 case AC_VECTOR: 4808 if (guest_inject_ac(vcpu)) { 4809 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4810 return 1; 4811 } 4812 4813 /* 4814 * Handle split lock. Depending on detection mode this will 4815 * either warn and disable split lock detection for this 4816 * task or force SIGBUS on it. 4817 */ 4818 if (handle_guest_split_lock(kvm_rip_read(vcpu))) 4819 return 1; 4820 fallthrough; 4821 default: 4822 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4823 kvm_run->ex.exception = ex_no; 4824 kvm_run->ex.error_code = error_code; 4825 break; 4826 } 4827 return 0; 4828 } 4829 4830 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4831 { 4832 ++vcpu->stat.irq_exits; 4833 return 1; 4834 } 4835 4836 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4837 { 4838 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4839 vcpu->mmio_needed = 0; 4840 return 0; 4841 } 4842 4843 static int handle_io(struct kvm_vcpu *vcpu) 4844 { 4845 unsigned long exit_qualification; 4846 int size, in, string; 4847 unsigned port; 4848 4849 exit_qualification = vmx_get_exit_qual(vcpu); 4850 string = (exit_qualification & 16) != 0; 4851 4852 ++vcpu->stat.io_exits; 4853 4854 if (string) 4855 return kvm_emulate_instruction(vcpu, 0); 4856 4857 port = exit_qualification >> 16; 4858 size = (exit_qualification & 7) + 1; 4859 in = (exit_qualification & 8) != 0; 4860 4861 return kvm_fast_pio(vcpu, size, port, in); 4862 } 4863 4864 static void 4865 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4866 { 4867 /* 4868 * Patch in the VMCALL instruction: 4869 */ 4870 hypercall[0] = 0x0f; 4871 hypercall[1] = 0x01; 4872 hypercall[2] = 0xc1; 4873 } 4874 4875 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4876 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4877 { 4878 if (is_guest_mode(vcpu)) { 4879 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4880 unsigned long orig_val = val; 4881 4882 /* 4883 * We get here when L2 changed cr0 in a way that did not change 4884 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4885 * but did change L0 shadowed bits. So we first calculate the 4886 * effective cr0 value that L1 would like to write into the 4887 * hardware. It consists of the L2-owned bits from the new 4888 * value combined with the L1-owned bits from L1's guest_cr0. 4889 */ 4890 val = (val & ~vmcs12->cr0_guest_host_mask) | 4891 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4892 4893 if (!nested_guest_cr0_valid(vcpu, val)) 4894 return 1; 4895 4896 if (kvm_set_cr0(vcpu, val)) 4897 return 1; 4898 vmcs_writel(CR0_READ_SHADOW, orig_val); 4899 return 0; 4900 } else { 4901 if (to_vmx(vcpu)->nested.vmxon && 4902 !nested_host_cr0_valid(vcpu, val)) 4903 return 1; 4904 4905 return kvm_set_cr0(vcpu, val); 4906 } 4907 } 4908 4909 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4910 { 4911 if (is_guest_mode(vcpu)) { 4912 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4913 unsigned long orig_val = val; 4914 4915 /* analogously to handle_set_cr0 */ 4916 val = (val & ~vmcs12->cr4_guest_host_mask) | 4917 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4918 if (kvm_set_cr4(vcpu, val)) 4919 return 1; 4920 vmcs_writel(CR4_READ_SHADOW, orig_val); 4921 return 0; 4922 } else 4923 return kvm_set_cr4(vcpu, val); 4924 } 4925 4926 static int handle_desc(struct kvm_vcpu *vcpu) 4927 { 4928 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4929 return kvm_emulate_instruction(vcpu, 0); 4930 } 4931 4932 static int handle_cr(struct kvm_vcpu *vcpu) 4933 { 4934 unsigned long exit_qualification, val; 4935 int cr; 4936 int reg; 4937 int err; 4938 int ret; 4939 4940 exit_qualification = vmx_get_exit_qual(vcpu); 4941 cr = exit_qualification & 15; 4942 reg = (exit_qualification >> 8) & 15; 4943 switch ((exit_qualification >> 4) & 3) { 4944 case 0: /* mov to cr */ 4945 val = kvm_register_readl(vcpu, reg); 4946 trace_kvm_cr_write(cr, val); 4947 switch (cr) { 4948 case 0: 4949 err = handle_set_cr0(vcpu, val); 4950 return kvm_complete_insn_gp(vcpu, err); 4951 case 3: 4952 WARN_ON_ONCE(enable_unrestricted_guest); 4953 err = kvm_set_cr3(vcpu, val); 4954 return kvm_complete_insn_gp(vcpu, err); 4955 case 4: 4956 err = handle_set_cr4(vcpu, val); 4957 return kvm_complete_insn_gp(vcpu, err); 4958 case 8: { 4959 u8 cr8_prev = kvm_get_cr8(vcpu); 4960 u8 cr8 = (u8)val; 4961 err = kvm_set_cr8(vcpu, cr8); 4962 ret = kvm_complete_insn_gp(vcpu, err); 4963 if (lapic_in_kernel(vcpu)) 4964 return ret; 4965 if (cr8_prev <= cr8) 4966 return ret; 4967 /* 4968 * TODO: we might be squashing a 4969 * KVM_GUESTDBG_SINGLESTEP-triggered 4970 * KVM_EXIT_DEBUG here. 4971 */ 4972 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4973 return 0; 4974 } 4975 } 4976 break; 4977 case 2: /* clts */ 4978 WARN_ONCE(1, "Guest should always own CR0.TS"); 4979 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4980 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4981 return kvm_skip_emulated_instruction(vcpu); 4982 case 1: /*mov from cr*/ 4983 switch (cr) { 4984 case 3: 4985 WARN_ON_ONCE(enable_unrestricted_guest); 4986 val = kvm_read_cr3(vcpu); 4987 kvm_register_write(vcpu, reg, val); 4988 trace_kvm_cr_read(cr, val); 4989 return kvm_skip_emulated_instruction(vcpu); 4990 case 8: 4991 val = kvm_get_cr8(vcpu); 4992 kvm_register_write(vcpu, reg, val); 4993 trace_kvm_cr_read(cr, val); 4994 return kvm_skip_emulated_instruction(vcpu); 4995 } 4996 break; 4997 case 3: /* lmsw */ 4998 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4999 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 5000 kvm_lmsw(vcpu, val); 5001 5002 return kvm_skip_emulated_instruction(vcpu); 5003 default: 5004 break; 5005 } 5006 vcpu->run->exit_reason = 0; 5007 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 5008 (int)(exit_qualification >> 4) & 3, cr); 5009 return 0; 5010 } 5011 5012 static int handle_dr(struct kvm_vcpu *vcpu) 5013 { 5014 unsigned long exit_qualification; 5015 int dr, dr7, reg; 5016 5017 exit_qualification = vmx_get_exit_qual(vcpu); 5018 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 5019 5020 /* First, if DR does not exist, trigger UD */ 5021 if (!kvm_require_dr(vcpu, dr)) 5022 return 1; 5023 5024 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 5025 if (!kvm_require_cpl(vcpu, 0)) 5026 return 1; 5027 dr7 = vmcs_readl(GUEST_DR7); 5028 if (dr7 & DR7_GD) { 5029 /* 5030 * As the vm-exit takes precedence over the debug trap, we 5031 * need to emulate the latter, either for the host or the 5032 * guest debugging itself. 5033 */ 5034 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 5035 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1; 5036 vcpu->run->debug.arch.dr7 = dr7; 5037 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 5038 vcpu->run->debug.arch.exception = DB_VECTOR; 5039 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 5040 return 0; 5041 } else { 5042 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD); 5043 return 1; 5044 } 5045 } 5046 5047 if (vcpu->guest_debug == 0) { 5048 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 5049 5050 /* 5051 * No more DR vmexits; force a reload of the debug registers 5052 * and reenter on this instruction. The next vmexit will 5053 * retrieve the full state of the debug registers. 5054 */ 5055 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 5056 return 1; 5057 } 5058 5059 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 5060 if (exit_qualification & TYPE_MOV_FROM_DR) { 5061 unsigned long val; 5062 5063 if (kvm_get_dr(vcpu, dr, &val)) 5064 return 1; 5065 kvm_register_write(vcpu, reg, val); 5066 } else 5067 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 5068 return 1; 5069 5070 return kvm_skip_emulated_instruction(vcpu); 5071 } 5072 5073 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 5074 { 5075 get_debugreg(vcpu->arch.db[0], 0); 5076 get_debugreg(vcpu->arch.db[1], 1); 5077 get_debugreg(vcpu->arch.db[2], 2); 5078 get_debugreg(vcpu->arch.db[3], 3); 5079 get_debugreg(vcpu->arch.dr6, 6); 5080 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 5081 5082 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 5083 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 5084 } 5085 5086 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 5087 { 5088 vmcs_writel(GUEST_DR7, val); 5089 } 5090 5091 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 5092 { 5093 kvm_apic_update_ppr(vcpu); 5094 return 1; 5095 } 5096 5097 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 5098 { 5099 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 5100 5101 kvm_make_request(KVM_REQ_EVENT, vcpu); 5102 5103 ++vcpu->stat.irq_window_exits; 5104 return 1; 5105 } 5106 5107 static int handle_vmcall(struct kvm_vcpu *vcpu) 5108 { 5109 return kvm_emulate_hypercall(vcpu); 5110 } 5111 5112 static int handle_invd(struct kvm_vcpu *vcpu) 5113 { 5114 return kvm_emulate_instruction(vcpu, 0); 5115 } 5116 5117 static int handle_invlpg(struct kvm_vcpu *vcpu) 5118 { 5119 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5120 5121 kvm_mmu_invlpg(vcpu, exit_qualification); 5122 return kvm_skip_emulated_instruction(vcpu); 5123 } 5124 5125 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5126 { 5127 int err; 5128 5129 err = kvm_rdpmc(vcpu); 5130 return kvm_complete_insn_gp(vcpu, err); 5131 } 5132 5133 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5134 { 5135 return kvm_emulate_wbinvd(vcpu); 5136 } 5137 5138 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5139 { 5140 u64 new_bv = kvm_read_edx_eax(vcpu); 5141 u32 index = kvm_rcx_read(vcpu); 5142 5143 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5144 return kvm_skip_emulated_instruction(vcpu); 5145 return 1; 5146 } 5147 5148 static int handle_apic_access(struct kvm_vcpu *vcpu) 5149 { 5150 if (likely(fasteoi)) { 5151 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5152 int access_type, offset; 5153 5154 access_type = exit_qualification & APIC_ACCESS_TYPE; 5155 offset = exit_qualification & APIC_ACCESS_OFFSET; 5156 /* 5157 * Sane guest uses MOV to write EOI, with written value 5158 * not cared. So make a short-circuit here by avoiding 5159 * heavy instruction emulation. 5160 */ 5161 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5162 (offset == APIC_EOI)) { 5163 kvm_lapic_set_eoi(vcpu); 5164 return kvm_skip_emulated_instruction(vcpu); 5165 } 5166 } 5167 return kvm_emulate_instruction(vcpu, 0); 5168 } 5169 5170 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5171 { 5172 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5173 int vector = exit_qualification & 0xff; 5174 5175 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5176 kvm_apic_set_eoi_accelerated(vcpu, vector); 5177 return 1; 5178 } 5179 5180 static int handle_apic_write(struct kvm_vcpu *vcpu) 5181 { 5182 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5183 u32 offset = exit_qualification & 0xfff; 5184 5185 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5186 kvm_apic_write_nodecode(vcpu, offset); 5187 return 1; 5188 } 5189 5190 static int handle_task_switch(struct kvm_vcpu *vcpu) 5191 { 5192 struct vcpu_vmx *vmx = to_vmx(vcpu); 5193 unsigned long exit_qualification; 5194 bool has_error_code = false; 5195 u32 error_code = 0; 5196 u16 tss_selector; 5197 int reason, type, idt_v, idt_index; 5198 5199 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5200 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5201 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5202 5203 exit_qualification = vmx_get_exit_qual(vcpu); 5204 5205 reason = (u32)exit_qualification >> 30; 5206 if (reason == TASK_SWITCH_GATE && idt_v) { 5207 switch (type) { 5208 case INTR_TYPE_NMI_INTR: 5209 vcpu->arch.nmi_injected = false; 5210 vmx_set_nmi_mask(vcpu, true); 5211 break; 5212 case INTR_TYPE_EXT_INTR: 5213 case INTR_TYPE_SOFT_INTR: 5214 kvm_clear_interrupt_queue(vcpu); 5215 break; 5216 case INTR_TYPE_HARD_EXCEPTION: 5217 if (vmx->idt_vectoring_info & 5218 VECTORING_INFO_DELIVER_CODE_MASK) { 5219 has_error_code = true; 5220 error_code = 5221 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5222 } 5223 /* fall through */ 5224 case INTR_TYPE_SOFT_EXCEPTION: 5225 kvm_clear_exception_queue(vcpu); 5226 break; 5227 default: 5228 break; 5229 } 5230 } 5231 tss_selector = exit_qualification; 5232 5233 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5234 type != INTR_TYPE_EXT_INTR && 5235 type != INTR_TYPE_NMI_INTR)) 5236 WARN_ON(!skip_emulated_instruction(vcpu)); 5237 5238 /* 5239 * TODO: What about debug traps on tss switch? 5240 * Are we supposed to inject them and update dr6? 5241 */ 5242 return kvm_task_switch(vcpu, tss_selector, 5243 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5244 reason, has_error_code, error_code); 5245 } 5246 5247 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5248 { 5249 unsigned long exit_qualification; 5250 gpa_t gpa; 5251 u64 error_code; 5252 5253 exit_qualification = vmx_get_exit_qual(vcpu); 5254 5255 /* 5256 * EPT violation happened while executing iret from NMI, 5257 * "blocked by NMI" bit has to be set before next VM entry. 5258 * There are errata that may cause this bit to not be set: 5259 * AAK134, BY25. 5260 */ 5261 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5262 enable_vnmi && 5263 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5264 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5265 5266 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5267 trace_kvm_page_fault(gpa, exit_qualification); 5268 5269 /* Is it a read fault? */ 5270 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5271 ? PFERR_USER_MASK : 0; 5272 /* Is it a write fault? */ 5273 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5274 ? PFERR_WRITE_MASK : 0; 5275 /* Is it a fetch fault? */ 5276 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5277 ? PFERR_FETCH_MASK : 0; 5278 /* ept page table entry is present? */ 5279 error_code |= (exit_qualification & 5280 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5281 EPT_VIOLATION_EXECUTABLE)) 5282 ? PFERR_PRESENT_MASK : 0; 5283 5284 error_code |= (exit_qualification & 0x100) != 0 ? 5285 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5286 5287 vcpu->arch.exit_qualification = exit_qualification; 5288 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5289 } 5290 5291 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5292 { 5293 gpa_t gpa; 5294 5295 /* 5296 * A nested guest cannot optimize MMIO vmexits, because we have an 5297 * nGPA here instead of the required GPA. 5298 */ 5299 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5300 if (!is_guest_mode(vcpu) && 5301 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5302 trace_kvm_fast_mmio(gpa); 5303 return kvm_skip_emulated_instruction(vcpu); 5304 } 5305 5306 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5307 } 5308 5309 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5310 { 5311 WARN_ON_ONCE(!enable_vnmi); 5312 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5313 ++vcpu->stat.nmi_window_exits; 5314 kvm_make_request(KVM_REQ_EVENT, vcpu); 5315 5316 return 1; 5317 } 5318 5319 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5320 { 5321 struct vcpu_vmx *vmx = to_vmx(vcpu); 5322 bool intr_window_requested; 5323 unsigned count = 130; 5324 5325 intr_window_requested = exec_controls_get(vmx) & 5326 CPU_BASED_INTR_WINDOW_EXITING; 5327 5328 while (vmx->emulation_required && count-- != 0) { 5329 if (intr_window_requested && !vmx_interrupt_blocked(vcpu)) 5330 return handle_interrupt_window(&vmx->vcpu); 5331 5332 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5333 return 1; 5334 5335 if (!kvm_emulate_instruction(vcpu, 0)) 5336 return 0; 5337 5338 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5339 vcpu->arch.exception.pending) { 5340 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5341 vcpu->run->internal.suberror = 5342 KVM_INTERNAL_ERROR_EMULATION; 5343 vcpu->run->internal.ndata = 0; 5344 return 0; 5345 } 5346 5347 if (vcpu->arch.halt_request) { 5348 vcpu->arch.halt_request = 0; 5349 return kvm_vcpu_halt(vcpu); 5350 } 5351 5352 /* 5353 * Note, return 1 and not 0, vcpu_run() is responsible for 5354 * morphing the pending signal into the proper return code. 5355 */ 5356 if (signal_pending(current)) 5357 return 1; 5358 5359 if (need_resched()) 5360 schedule(); 5361 } 5362 5363 return 1; 5364 } 5365 5366 static void grow_ple_window(struct kvm_vcpu *vcpu) 5367 { 5368 struct vcpu_vmx *vmx = to_vmx(vcpu); 5369 unsigned int old = vmx->ple_window; 5370 5371 vmx->ple_window = __grow_ple_window(old, ple_window, 5372 ple_window_grow, 5373 ple_window_max); 5374 5375 if (vmx->ple_window != old) { 5376 vmx->ple_window_dirty = true; 5377 trace_kvm_ple_window_update(vcpu->vcpu_id, 5378 vmx->ple_window, old); 5379 } 5380 } 5381 5382 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5383 { 5384 struct vcpu_vmx *vmx = to_vmx(vcpu); 5385 unsigned int old = vmx->ple_window; 5386 5387 vmx->ple_window = __shrink_ple_window(old, ple_window, 5388 ple_window_shrink, 5389 ple_window); 5390 5391 if (vmx->ple_window != old) { 5392 vmx->ple_window_dirty = true; 5393 trace_kvm_ple_window_update(vcpu->vcpu_id, 5394 vmx->ple_window, old); 5395 } 5396 } 5397 5398 /* 5399 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5400 */ 5401 static void wakeup_handler(void) 5402 { 5403 struct kvm_vcpu *vcpu; 5404 int cpu = smp_processor_id(); 5405 5406 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5407 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5408 blocked_vcpu_list) { 5409 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5410 5411 if (pi_test_on(pi_desc) == 1) 5412 kvm_vcpu_kick(vcpu); 5413 } 5414 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5415 } 5416 5417 static void vmx_enable_tdp(void) 5418 { 5419 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5420 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5421 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5422 0ull, VMX_EPT_EXECUTABLE_MASK, 5423 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5424 VMX_EPT_RWX_MASK, 0ull); 5425 5426 ept_set_mmio_spte_mask(); 5427 } 5428 5429 /* 5430 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5431 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5432 */ 5433 static int handle_pause(struct kvm_vcpu *vcpu) 5434 { 5435 if (!kvm_pause_in_guest(vcpu->kvm)) 5436 grow_ple_window(vcpu); 5437 5438 /* 5439 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5440 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5441 * never set PAUSE_EXITING and just set PLE if supported, 5442 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5443 */ 5444 kvm_vcpu_on_spin(vcpu, true); 5445 return kvm_skip_emulated_instruction(vcpu); 5446 } 5447 5448 static int handle_nop(struct kvm_vcpu *vcpu) 5449 { 5450 return kvm_skip_emulated_instruction(vcpu); 5451 } 5452 5453 static int handle_mwait(struct kvm_vcpu *vcpu) 5454 { 5455 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5456 return handle_nop(vcpu); 5457 } 5458 5459 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5460 { 5461 kvm_queue_exception(vcpu, UD_VECTOR); 5462 return 1; 5463 } 5464 5465 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5466 { 5467 return 1; 5468 } 5469 5470 static int handle_monitor(struct kvm_vcpu *vcpu) 5471 { 5472 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5473 return handle_nop(vcpu); 5474 } 5475 5476 static int handle_invpcid(struct kvm_vcpu *vcpu) 5477 { 5478 u32 vmx_instruction_info; 5479 unsigned long type; 5480 bool pcid_enabled; 5481 gva_t gva; 5482 struct x86_exception e; 5483 unsigned i; 5484 unsigned long roots_to_free = 0; 5485 struct { 5486 u64 pcid; 5487 u64 gla; 5488 } operand; 5489 5490 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5491 kvm_queue_exception(vcpu, UD_VECTOR); 5492 return 1; 5493 } 5494 5495 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5496 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5497 5498 if (type > 3) { 5499 kvm_inject_gp(vcpu, 0); 5500 return 1; 5501 } 5502 5503 /* According to the Intel instruction reference, the memory operand 5504 * is read even if it isn't needed (e.g., for type==all) 5505 */ 5506 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), 5507 vmx_instruction_info, false, 5508 sizeof(operand), &gva)) 5509 return 1; 5510 5511 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5512 kvm_inject_emulated_page_fault(vcpu, &e); 5513 return 1; 5514 } 5515 5516 if (operand.pcid >> 12 != 0) { 5517 kvm_inject_gp(vcpu, 0); 5518 return 1; 5519 } 5520 5521 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5522 5523 switch (type) { 5524 case INVPCID_TYPE_INDIV_ADDR: 5525 if ((!pcid_enabled && (operand.pcid != 0)) || 5526 is_noncanonical_address(operand.gla, vcpu)) { 5527 kvm_inject_gp(vcpu, 0); 5528 return 1; 5529 } 5530 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5531 return kvm_skip_emulated_instruction(vcpu); 5532 5533 case INVPCID_TYPE_SINGLE_CTXT: 5534 if (!pcid_enabled && (operand.pcid != 0)) { 5535 kvm_inject_gp(vcpu, 0); 5536 return 1; 5537 } 5538 5539 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5540 kvm_mmu_sync_roots(vcpu); 5541 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 5542 } 5543 5544 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5545 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) 5546 == operand.pcid) 5547 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5548 5549 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5550 /* 5551 * If neither the current cr3 nor any of the prev_roots use the 5552 * given PCID, then nothing needs to be done here because a 5553 * resync will happen anyway before switching to any other CR3. 5554 */ 5555 5556 return kvm_skip_emulated_instruction(vcpu); 5557 5558 case INVPCID_TYPE_ALL_NON_GLOBAL: 5559 /* 5560 * Currently, KVM doesn't mark global entries in the shadow 5561 * page tables, so a non-global flush just degenerates to a 5562 * global flush. If needed, we could optimize this later by 5563 * keeping track of global entries in shadow page tables. 5564 */ 5565 5566 /* fall-through */ 5567 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5568 kvm_mmu_unload(vcpu); 5569 return kvm_skip_emulated_instruction(vcpu); 5570 5571 default: 5572 BUG(); /* We have already checked above that type <= 3 */ 5573 } 5574 } 5575 5576 static int handle_pml_full(struct kvm_vcpu *vcpu) 5577 { 5578 unsigned long exit_qualification; 5579 5580 trace_kvm_pml_full(vcpu->vcpu_id); 5581 5582 exit_qualification = vmx_get_exit_qual(vcpu); 5583 5584 /* 5585 * PML buffer FULL happened while executing iret from NMI, 5586 * "blocked by NMI" bit has to be set before next VM entry. 5587 */ 5588 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5589 enable_vnmi && 5590 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5591 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5592 GUEST_INTR_STATE_NMI); 5593 5594 /* 5595 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5596 * here.., and there's no userspace involvement needed for PML. 5597 */ 5598 return 1; 5599 } 5600 5601 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu) 5602 { 5603 struct vcpu_vmx *vmx = to_vmx(vcpu); 5604 5605 if (!vmx->req_immediate_exit && 5606 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) { 5607 kvm_lapic_expired_hv_timer(vcpu); 5608 return EXIT_FASTPATH_REENTER_GUEST; 5609 } 5610 5611 return EXIT_FASTPATH_NONE; 5612 } 5613 5614 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5615 { 5616 handle_fastpath_preemption_timer(vcpu); 5617 return 1; 5618 } 5619 5620 /* 5621 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5622 * are overwritten by nested_vmx_setup() when nested=1. 5623 */ 5624 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5625 { 5626 kvm_queue_exception(vcpu, UD_VECTOR); 5627 return 1; 5628 } 5629 5630 static int handle_encls(struct kvm_vcpu *vcpu) 5631 { 5632 /* 5633 * SGX virtualization is not yet supported. There is no software 5634 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5635 * to prevent the guest from executing ENCLS. 5636 */ 5637 kvm_queue_exception(vcpu, UD_VECTOR); 5638 return 1; 5639 } 5640 5641 /* 5642 * The exit handlers return 1 if the exit was handled fully and guest execution 5643 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5644 * to be done to userspace and return 0. 5645 */ 5646 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5647 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5648 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5649 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5650 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5651 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5652 [EXIT_REASON_CR_ACCESS] = handle_cr, 5653 [EXIT_REASON_DR_ACCESS] = handle_dr, 5654 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5655 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5656 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5657 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5658 [EXIT_REASON_HLT] = kvm_emulate_halt, 5659 [EXIT_REASON_INVD] = handle_invd, 5660 [EXIT_REASON_INVLPG] = handle_invlpg, 5661 [EXIT_REASON_RDPMC] = handle_rdpmc, 5662 [EXIT_REASON_VMCALL] = handle_vmcall, 5663 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5664 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5665 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5666 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5667 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5668 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5669 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5670 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5671 [EXIT_REASON_VMON] = handle_vmx_instruction, 5672 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5673 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5674 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5675 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5676 [EXIT_REASON_WBINVD] = handle_wbinvd, 5677 [EXIT_REASON_XSETBV] = handle_xsetbv, 5678 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5679 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5680 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5681 [EXIT_REASON_LDTR_TR] = handle_desc, 5682 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5683 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5684 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5685 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5686 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5687 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5688 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5689 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5690 [EXIT_REASON_RDRAND] = handle_invalid_op, 5691 [EXIT_REASON_RDSEED] = handle_invalid_op, 5692 [EXIT_REASON_PML_FULL] = handle_pml_full, 5693 [EXIT_REASON_INVPCID] = handle_invpcid, 5694 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5695 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5696 [EXIT_REASON_ENCLS] = handle_encls, 5697 }; 5698 5699 static const int kvm_vmx_max_exit_handlers = 5700 ARRAY_SIZE(kvm_vmx_exit_handlers); 5701 5702 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5703 { 5704 *info1 = vmx_get_exit_qual(vcpu); 5705 *info2 = vmx_get_intr_info(vcpu); 5706 } 5707 5708 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5709 { 5710 if (vmx->pml_pg) { 5711 __free_page(vmx->pml_pg); 5712 vmx->pml_pg = NULL; 5713 } 5714 } 5715 5716 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5717 { 5718 struct vcpu_vmx *vmx = to_vmx(vcpu); 5719 u64 *pml_buf; 5720 u16 pml_idx; 5721 5722 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5723 5724 /* Do nothing if PML buffer is empty */ 5725 if (pml_idx == (PML_ENTITY_NUM - 1)) 5726 return; 5727 5728 /* PML index always points to next available PML buffer entity */ 5729 if (pml_idx >= PML_ENTITY_NUM) 5730 pml_idx = 0; 5731 else 5732 pml_idx++; 5733 5734 pml_buf = page_address(vmx->pml_pg); 5735 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5736 u64 gpa; 5737 5738 gpa = pml_buf[pml_idx]; 5739 WARN_ON(gpa & (PAGE_SIZE - 1)); 5740 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5741 } 5742 5743 /* reset PML index */ 5744 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5745 } 5746 5747 /* 5748 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5749 * Called before reporting dirty_bitmap to userspace. 5750 */ 5751 static void kvm_flush_pml_buffers(struct kvm *kvm) 5752 { 5753 int i; 5754 struct kvm_vcpu *vcpu; 5755 /* 5756 * We only need to kick vcpu out of guest mode here, as PML buffer 5757 * is flushed at beginning of all VMEXITs, and it's obvious that only 5758 * vcpus running in guest are possible to have unflushed GPAs in PML 5759 * buffer. 5760 */ 5761 kvm_for_each_vcpu(i, vcpu, kvm) 5762 kvm_vcpu_kick(vcpu); 5763 } 5764 5765 static void vmx_dump_sel(char *name, uint32_t sel) 5766 { 5767 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5768 name, vmcs_read16(sel), 5769 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5770 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5771 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5772 } 5773 5774 static void vmx_dump_dtsel(char *name, uint32_t limit) 5775 { 5776 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5777 name, vmcs_read32(limit), 5778 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5779 } 5780 5781 void dump_vmcs(void) 5782 { 5783 u32 vmentry_ctl, vmexit_ctl; 5784 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5785 unsigned long cr4; 5786 u64 efer; 5787 5788 if (!dump_invalid_vmcs) { 5789 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5790 return; 5791 } 5792 5793 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5794 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5795 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5796 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5797 cr4 = vmcs_readl(GUEST_CR4); 5798 efer = vmcs_read64(GUEST_IA32_EFER); 5799 secondary_exec_control = 0; 5800 if (cpu_has_secondary_exec_ctrls()) 5801 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5802 5803 pr_err("*** Guest State ***\n"); 5804 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5805 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5806 vmcs_readl(CR0_GUEST_HOST_MASK)); 5807 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5808 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5809 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5810 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5811 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5812 { 5813 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5814 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5815 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5816 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5817 } 5818 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5819 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5820 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5821 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5822 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5823 vmcs_readl(GUEST_SYSENTER_ESP), 5824 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5825 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5826 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5827 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5828 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5829 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5830 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5831 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5832 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5833 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5834 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5835 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5836 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5837 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5838 efer, vmcs_read64(GUEST_IA32_PAT)); 5839 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5840 vmcs_read64(GUEST_IA32_DEBUGCTL), 5841 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5842 if (cpu_has_load_perf_global_ctrl() && 5843 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5844 pr_err("PerfGlobCtl = 0x%016llx\n", 5845 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5846 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5847 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5848 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5849 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5850 vmcs_read32(GUEST_ACTIVITY_STATE)); 5851 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5852 pr_err("InterruptStatus = %04x\n", 5853 vmcs_read16(GUEST_INTR_STATUS)); 5854 5855 pr_err("*** Host State ***\n"); 5856 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5857 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5858 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5859 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5860 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5861 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5862 vmcs_read16(HOST_TR_SELECTOR)); 5863 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5864 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5865 vmcs_readl(HOST_TR_BASE)); 5866 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5867 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5868 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5869 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5870 vmcs_readl(HOST_CR4)); 5871 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5872 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5873 vmcs_read32(HOST_IA32_SYSENTER_CS), 5874 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5875 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5876 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5877 vmcs_read64(HOST_IA32_EFER), 5878 vmcs_read64(HOST_IA32_PAT)); 5879 if (cpu_has_load_perf_global_ctrl() && 5880 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5881 pr_err("PerfGlobCtl = 0x%016llx\n", 5882 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5883 5884 pr_err("*** Control State ***\n"); 5885 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5886 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5887 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5888 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5889 vmcs_read32(EXCEPTION_BITMAP), 5890 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5891 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5892 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5893 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5894 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5895 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5896 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5897 vmcs_read32(VM_EXIT_INTR_INFO), 5898 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5899 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5900 pr_err(" reason=%08x qualification=%016lx\n", 5901 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5902 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5903 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5904 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5905 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5906 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5907 pr_err("TSC Multiplier = 0x%016llx\n", 5908 vmcs_read64(TSC_MULTIPLIER)); 5909 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5910 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5911 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5912 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5913 } 5914 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5915 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5916 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5917 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5918 } 5919 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5920 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5921 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5922 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5923 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5924 pr_err("PLE Gap=%08x Window=%08x\n", 5925 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5926 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5927 pr_err("Virtual processor ID = 0x%04x\n", 5928 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5929 } 5930 5931 /* 5932 * The guest has exited. See if we can fix it or if we need userspace 5933 * assistance. 5934 */ 5935 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath) 5936 { 5937 struct vcpu_vmx *vmx = to_vmx(vcpu); 5938 u32 exit_reason = vmx->exit_reason; 5939 u32 vectoring_info = vmx->idt_vectoring_info; 5940 5941 /* 5942 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5943 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5944 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5945 * mode as if vcpus is in root mode, the PML buffer must has been 5946 * flushed already. 5947 */ 5948 if (enable_pml) 5949 vmx_flush_pml_buffer(vcpu); 5950 5951 /* 5952 * We should never reach this point with a pending nested VM-Enter, and 5953 * more specifically emulation of L2 due to invalid guest state (see 5954 * below) should never happen as that means we incorrectly allowed a 5955 * nested VM-Enter with an invalid vmcs12. 5956 */ 5957 WARN_ON_ONCE(vmx->nested.nested_run_pending); 5958 5959 /* If guest state is invalid, start emulating */ 5960 if (vmx->emulation_required) 5961 return handle_invalid_guest_state(vcpu); 5962 5963 if (is_guest_mode(vcpu)) { 5964 /* 5965 * The host physical addresses of some pages of guest memory 5966 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC 5967 * Page). The CPU may write to these pages via their host 5968 * physical address while L2 is running, bypassing any 5969 * address-translation-based dirty tracking (e.g. EPT write 5970 * protection). 5971 * 5972 * Mark them dirty on every exit from L2 to prevent them from 5973 * getting out of sync with dirty tracking. 5974 */ 5975 nested_mark_vmcs12_pages_dirty(vcpu); 5976 5977 if (nested_vmx_reflect_vmexit(vcpu)) 5978 return 1; 5979 } 5980 5981 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5982 dump_vmcs(); 5983 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5984 vcpu->run->fail_entry.hardware_entry_failure_reason 5985 = exit_reason; 5986 return 0; 5987 } 5988 5989 if (unlikely(vmx->fail)) { 5990 dump_vmcs(); 5991 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5992 vcpu->run->fail_entry.hardware_entry_failure_reason 5993 = vmcs_read32(VM_INSTRUCTION_ERROR); 5994 return 0; 5995 } 5996 5997 /* 5998 * Note: 5999 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 6000 * delivery event since it indicates guest is accessing MMIO. 6001 * The vm-exit can be triggered again after return to guest that 6002 * will cause infinite loop. 6003 */ 6004 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 6005 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 6006 exit_reason != EXIT_REASON_EPT_VIOLATION && 6007 exit_reason != EXIT_REASON_PML_FULL && 6008 exit_reason != EXIT_REASON_TASK_SWITCH)) { 6009 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6010 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 6011 vcpu->run->internal.ndata = 3; 6012 vcpu->run->internal.data[0] = vectoring_info; 6013 vcpu->run->internal.data[1] = exit_reason; 6014 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 6015 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 6016 vcpu->run->internal.ndata++; 6017 vcpu->run->internal.data[3] = 6018 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 6019 } 6020 return 0; 6021 } 6022 6023 if (unlikely(!enable_vnmi && 6024 vmx->loaded_vmcs->soft_vnmi_blocked)) { 6025 if (!vmx_interrupt_blocked(vcpu)) { 6026 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 6027 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 6028 vcpu->arch.nmi_pending) { 6029 /* 6030 * This CPU don't support us in finding the end of an 6031 * NMI-blocked window if the guest runs with IRQs 6032 * disabled. So we pull the trigger after 1 s of 6033 * futile waiting, but inform the user about this. 6034 */ 6035 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 6036 "state on VCPU %d after 1 s timeout\n", 6037 __func__, vcpu->vcpu_id); 6038 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 6039 } 6040 } 6041 6042 if (exit_fastpath != EXIT_FASTPATH_NONE) 6043 return 1; 6044 6045 if (exit_reason >= kvm_vmx_max_exit_handlers) 6046 goto unexpected_vmexit; 6047 #ifdef CONFIG_RETPOLINE 6048 if (exit_reason == EXIT_REASON_MSR_WRITE) 6049 return kvm_emulate_wrmsr(vcpu); 6050 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 6051 return handle_preemption_timer(vcpu); 6052 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 6053 return handle_interrupt_window(vcpu); 6054 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6055 return handle_external_interrupt(vcpu); 6056 else if (exit_reason == EXIT_REASON_HLT) 6057 return kvm_emulate_halt(vcpu); 6058 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 6059 return handle_ept_misconfig(vcpu); 6060 #endif 6061 6062 exit_reason = array_index_nospec(exit_reason, 6063 kvm_vmx_max_exit_handlers); 6064 if (!kvm_vmx_exit_handlers[exit_reason]) 6065 goto unexpected_vmexit; 6066 6067 return kvm_vmx_exit_handlers[exit_reason](vcpu); 6068 6069 unexpected_vmexit: 6070 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 6071 dump_vmcs(); 6072 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6073 vcpu->run->internal.suberror = 6074 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 6075 vcpu->run->internal.ndata = 1; 6076 vcpu->run->internal.data[0] = exit_reason; 6077 return 0; 6078 } 6079 6080 /* 6081 * Software based L1D cache flush which is used when microcode providing 6082 * the cache control MSR is not loaded. 6083 * 6084 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 6085 * flush it is required to read in 64 KiB because the replacement algorithm 6086 * is not exactly LRU. This could be sized at runtime via topology 6087 * information but as all relevant affected CPUs have 32KiB L1D cache size 6088 * there is no point in doing so. 6089 */ 6090 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 6091 { 6092 int size = PAGE_SIZE << L1D_CACHE_ORDER; 6093 6094 /* 6095 * This code is only executed when the the flush mode is 'cond' or 6096 * 'always' 6097 */ 6098 if (static_branch_likely(&vmx_l1d_flush_cond)) { 6099 bool flush_l1d; 6100 6101 /* 6102 * Clear the per-vcpu flush bit, it gets set again 6103 * either from vcpu_run() or from one of the unsafe 6104 * VMEXIT handlers. 6105 */ 6106 flush_l1d = vcpu->arch.l1tf_flush_l1d; 6107 vcpu->arch.l1tf_flush_l1d = false; 6108 6109 /* 6110 * Clear the per-cpu flush bit, it gets set again from 6111 * the interrupt handlers. 6112 */ 6113 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 6114 kvm_clear_cpu_l1tf_flush_l1d(); 6115 6116 if (!flush_l1d) 6117 return; 6118 } 6119 6120 vcpu->stat.l1d_flush++; 6121 6122 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 6123 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6124 return; 6125 } 6126 6127 asm volatile( 6128 /* First ensure the pages are in the TLB */ 6129 "xorl %%eax, %%eax\n" 6130 ".Lpopulate_tlb:\n\t" 6131 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6132 "addl $4096, %%eax\n\t" 6133 "cmpl %%eax, %[size]\n\t" 6134 "jne .Lpopulate_tlb\n\t" 6135 "xorl %%eax, %%eax\n\t" 6136 "cpuid\n\t" 6137 /* Now fill the cache */ 6138 "xorl %%eax, %%eax\n" 6139 ".Lfill_cache:\n" 6140 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6141 "addl $64, %%eax\n\t" 6142 "cmpl %%eax, %[size]\n\t" 6143 "jne .Lfill_cache\n\t" 6144 "lfence\n" 6145 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6146 [size] "r" (size) 6147 : "eax", "ebx", "ecx", "edx"); 6148 } 6149 6150 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6151 { 6152 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6153 int tpr_threshold; 6154 6155 if (is_guest_mode(vcpu) && 6156 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6157 return; 6158 6159 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6160 if (is_guest_mode(vcpu)) 6161 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6162 else 6163 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6164 } 6165 6166 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6167 { 6168 struct vcpu_vmx *vmx = to_vmx(vcpu); 6169 u32 sec_exec_control; 6170 6171 if (!lapic_in_kernel(vcpu)) 6172 return; 6173 6174 if (!flexpriority_enabled && 6175 !cpu_has_vmx_virtualize_x2apic_mode()) 6176 return; 6177 6178 /* Postpone execution until vmcs01 is the current VMCS. */ 6179 if (is_guest_mode(vcpu)) { 6180 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6181 return; 6182 } 6183 6184 sec_exec_control = secondary_exec_controls_get(vmx); 6185 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6186 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6187 6188 switch (kvm_get_apic_mode(vcpu)) { 6189 case LAPIC_MODE_INVALID: 6190 WARN_ONCE(true, "Invalid local APIC state"); 6191 case LAPIC_MODE_DISABLED: 6192 break; 6193 case LAPIC_MODE_XAPIC: 6194 if (flexpriority_enabled) { 6195 sec_exec_control |= 6196 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6197 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 6198 6199 /* 6200 * Flush the TLB, reloading the APIC access page will 6201 * only do so if its physical address has changed, but 6202 * the guest may have inserted a non-APIC mapping into 6203 * the TLB while the APIC access page was disabled. 6204 */ 6205 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 6206 } 6207 break; 6208 case LAPIC_MODE_X2APIC: 6209 if (cpu_has_vmx_virtualize_x2apic_mode()) 6210 sec_exec_control |= 6211 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6212 break; 6213 } 6214 secondary_exec_controls_set(vmx, sec_exec_control); 6215 6216 vmx_update_msr_bitmap(vcpu); 6217 } 6218 6219 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu) 6220 { 6221 struct page *page; 6222 6223 /* Defer reload until vmcs01 is the current VMCS. */ 6224 if (is_guest_mode(vcpu)) { 6225 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true; 6226 return; 6227 } 6228 6229 if (!(secondary_exec_controls_get(to_vmx(vcpu)) & 6230 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 6231 return; 6232 6233 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6234 if (is_error_page(page)) 6235 return; 6236 6237 vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page)); 6238 vmx_flush_tlb_current(vcpu); 6239 6240 /* 6241 * Do not pin apic access page in memory, the MMU notifier 6242 * will call us again if it is migrated or swapped out. 6243 */ 6244 put_page(page); 6245 } 6246 6247 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6248 { 6249 u16 status; 6250 u8 old; 6251 6252 if (max_isr == -1) 6253 max_isr = 0; 6254 6255 status = vmcs_read16(GUEST_INTR_STATUS); 6256 old = status >> 8; 6257 if (max_isr != old) { 6258 status &= 0xff; 6259 status |= max_isr << 8; 6260 vmcs_write16(GUEST_INTR_STATUS, status); 6261 } 6262 } 6263 6264 static void vmx_set_rvi(int vector) 6265 { 6266 u16 status; 6267 u8 old; 6268 6269 if (vector == -1) 6270 vector = 0; 6271 6272 status = vmcs_read16(GUEST_INTR_STATUS); 6273 old = (u8)status & 0xff; 6274 if ((u8)vector != old) { 6275 status &= ~0xff; 6276 status |= (u8)vector; 6277 vmcs_write16(GUEST_INTR_STATUS, status); 6278 } 6279 } 6280 6281 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6282 { 6283 /* 6284 * When running L2, updating RVI is only relevant when 6285 * vmcs12 virtual-interrupt-delivery enabled. 6286 * However, it can be enabled only when L1 also 6287 * intercepts external-interrupts and in that case 6288 * we should not update vmcs02 RVI but instead intercept 6289 * interrupt. Therefore, do nothing when running L2. 6290 */ 6291 if (!is_guest_mode(vcpu)) 6292 vmx_set_rvi(max_irr); 6293 } 6294 6295 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6296 { 6297 struct vcpu_vmx *vmx = to_vmx(vcpu); 6298 int max_irr; 6299 bool max_irr_updated; 6300 6301 WARN_ON(!vcpu->arch.apicv_active); 6302 if (pi_test_on(&vmx->pi_desc)) { 6303 pi_clear_on(&vmx->pi_desc); 6304 /* 6305 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6306 * But on x86 this is just a compiler barrier anyway. 6307 */ 6308 smp_mb__after_atomic(); 6309 max_irr_updated = 6310 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6311 6312 /* 6313 * If we are running L2 and L1 has a new pending interrupt 6314 * which can be injected, we should re-evaluate 6315 * what should be done with this new L1 interrupt. 6316 * If L1 intercepts external-interrupts, we should 6317 * exit from L2 to L1. Otherwise, interrupt should be 6318 * delivered directly to L2. 6319 */ 6320 if (is_guest_mode(vcpu) && max_irr_updated) { 6321 if (nested_exit_on_intr(vcpu)) 6322 kvm_vcpu_exiting_guest_mode(vcpu); 6323 else 6324 kvm_make_request(KVM_REQ_EVENT, vcpu); 6325 } 6326 } else { 6327 max_irr = kvm_lapic_find_highest_irr(vcpu); 6328 } 6329 vmx_hwapic_irr_update(vcpu, max_irr); 6330 return max_irr; 6331 } 6332 6333 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6334 { 6335 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6336 6337 return pi_test_on(pi_desc) || 6338 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6339 } 6340 6341 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6342 { 6343 if (!kvm_vcpu_apicv_active(vcpu)) 6344 return; 6345 6346 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6347 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6348 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6349 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6350 } 6351 6352 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6353 { 6354 struct vcpu_vmx *vmx = to_vmx(vcpu); 6355 6356 pi_clear_on(&vmx->pi_desc); 6357 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6358 } 6359 6360 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6361 { 6362 u32 intr_info = vmx_get_intr_info(&vmx->vcpu); 6363 6364 /* if exit due to PF check for async PF */ 6365 if (is_page_fault(intr_info)) { 6366 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags(); 6367 /* Handle machine checks before interrupts are enabled */ 6368 } else if (is_machine_check(intr_info)) { 6369 kvm_machine_check(); 6370 /* We need to handle NMIs before interrupts are enabled */ 6371 } else if (is_nmi(intr_info)) { 6372 kvm_before_interrupt(&vmx->vcpu); 6373 asm("int $2"); 6374 kvm_after_interrupt(&vmx->vcpu); 6375 } 6376 } 6377 6378 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6379 { 6380 unsigned int vector; 6381 unsigned long entry; 6382 #ifdef CONFIG_X86_64 6383 unsigned long tmp; 6384 #endif 6385 gate_desc *desc; 6386 u32 intr_info = vmx_get_intr_info(vcpu); 6387 6388 if (WARN_ONCE(!is_external_intr(intr_info), 6389 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6390 return; 6391 6392 vector = intr_info & INTR_INFO_VECTOR_MASK; 6393 desc = (gate_desc *)host_idt_base + vector; 6394 entry = gate_offset(desc); 6395 6396 kvm_before_interrupt(vcpu); 6397 6398 asm volatile( 6399 #ifdef CONFIG_X86_64 6400 "mov %%rsp, %[sp]\n\t" 6401 "and $-16, %%rsp\n\t" 6402 "push %[ss]\n\t" 6403 "push %[sp]\n\t" 6404 #endif 6405 "pushf\n\t" 6406 "push %[cs]\n\t" 6407 CALL_NOSPEC 6408 : 6409 #ifdef CONFIG_X86_64 6410 [sp]"=&r"(tmp), 6411 #endif 6412 ASM_CALL_CONSTRAINT 6413 : 6414 [thunk_target]"r"(entry), 6415 #ifdef CONFIG_X86_64 6416 [ss]"i"(__KERNEL_DS), 6417 #endif 6418 [cs]"i"(__KERNEL_CS) 6419 ); 6420 6421 kvm_after_interrupt(vcpu); 6422 } 6423 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6424 6425 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu) 6426 { 6427 struct vcpu_vmx *vmx = to_vmx(vcpu); 6428 6429 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6430 handle_external_interrupt_irqoff(vcpu); 6431 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6432 handle_exception_nmi_irqoff(vmx); 6433 } 6434 6435 static bool vmx_has_emulated_msr(u32 index) 6436 { 6437 switch (index) { 6438 case MSR_IA32_SMBASE: 6439 /* 6440 * We cannot do SMM unless we can run the guest in big 6441 * real mode. 6442 */ 6443 return enable_unrestricted_guest || emulate_invalid_guest_state; 6444 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6445 return nested; 6446 case MSR_AMD64_VIRT_SPEC_CTRL: 6447 /* This is AMD only. */ 6448 return false; 6449 default: 6450 return true; 6451 } 6452 } 6453 6454 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6455 { 6456 u32 exit_intr_info; 6457 bool unblock_nmi; 6458 u8 vector; 6459 bool idtv_info_valid; 6460 6461 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6462 6463 if (enable_vnmi) { 6464 if (vmx->loaded_vmcs->nmi_known_unmasked) 6465 return; 6466 6467 exit_intr_info = vmx_get_intr_info(&vmx->vcpu); 6468 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6469 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6470 /* 6471 * SDM 3: 27.7.1.2 (September 2008) 6472 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6473 * a guest IRET fault. 6474 * SDM 3: 23.2.2 (September 2008) 6475 * Bit 12 is undefined in any of the following cases: 6476 * If the VM exit sets the valid bit in the IDT-vectoring 6477 * information field. 6478 * If the VM exit is due to a double fault. 6479 */ 6480 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6481 vector != DF_VECTOR && !idtv_info_valid) 6482 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6483 GUEST_INTR_STATE_NMI); 6484 else 6485 vmx->loaded_vmcs->nmi_known_unmasked = 6486 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6487 & GUEST_INTR_STATE_NMI); 6488 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6489 vmx->loaded_vmcs->vnmi_blocked_time += 6490 ktime_to_ns(ktime_sub(ktime_get(), 6491 vmx->loaded_vmcs->entry_time)); 6492 } 6493 6494 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6495 u32 idt_vectoring_info, 6496 int instr_len_field, 6497 int error_code_field) 6498 { 6499 u8 vector; 6500 int type; 6501 bool idtv_info_valid; 6502 6503 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6504 6505 vcpu->arch.nmi_injected = false; 6506 kvm_clear_exception_queue(vcpu); 6507 kvm_clear_interrupt_queue(vcpu); 6508 6509 if (!idtv_info_valid) 6510 return; 6511 6512 kvm_make_request(KVM_REQ_EVENT, vcpu); 6513 6514 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6515 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6516 6517 switch (type) { 6518 case INTR_TYPE_NMI_INTR: 6519 vcpu->arch.nmi_injected = true; 6520 /* 6521 * SDM 3: 27.7.1.2 (September 2008) 6522 * Clear bit "block by NMI" before VM entry if a NMI 6523 * delivery faulted. 6524 */ 6525 vmx_set_nmi_mask(vcpu, false); 6526 break; 6527 case INTR_TYPE_SOFT_EXCEPTION: 6528 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6529 /* fall through */ 6530 case INTR_TYPE_HARD_EXCEPTION: 6531 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6532 u32 err = vmcs_read32(error_code_field); 6533 kvm_requeue_exception_e(vcpu, vector, err); 6534 } else 6535 kvm_requeue_exception(vcpu, vector); 6536 break; 6537 case INTR_TYPE_SOFT_INTR: 6538 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6539 /* fall through */ 6540 case INTR_TYPE_EXT_INTR: 6541 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6542 break; 6543 default: 6544 break; 6545 } 6546 } 6547 6548 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6549 { 6550 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6551 VM_EXIT_INSTRUCTION_LEN, 6552 IDT_VECTORING_ERROR_CODE); 6553 } 6554 6555 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6556 { 6557 __vmx_complete_interrupts(vcpu, 6558 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6559 VM_ENTRY_INSTRUCTION_LEN, 6560 VM_ENTRY_EXCEPTION_ERROR_CODE); 6561 6562 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6563 } 6564 6565 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6566 { 6567 int i, nr_msrs; 6568 struct perf_guest_switch_msr *msrs; 6569 6570 msrs = perf_guest_get_msrs(&nr_msrs); 6571 6572 if (!msrs) 6573 return; 6574 6575 for (i = 0; i < nr_msrs; i++) 6576 if (msrs[i].host == msrs[i].guest) 6577 clear_atomic_switch_msr(vmx, msrs[i].msr); 6578 else 6579 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6580 msrs[i].host, false); 6581 } 6582 6583 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6584 { 6585 u32 host_umwait_control; 6586 6587 if (!vmx_has_waitpkg(vmx)) 6588 return; 6589 6590 host_umwait_control = get_umwait_control_msr(); 6591 6592 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6593 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6594 vmx->msr_ia32_umwait_control, 6595 host_umwait_control, false); 6596 else 6597 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6598 } 6599 6600 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6601 { 6602 struct vcpu_vmx *vmx = to_vmx(vcpu); 6603 u64 tscl; 6604 u32 delta_tsc; 6605 6606 if (vmx->req_immediate_exit) { 6607 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6608 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6609 } else if (vmx->hv_deadline_tsc != -1) { 6610 tscl = rdtsc(); 6611 if (vmx->hv_deadline_tsc > tscl) 6612 /* set_hv_timer ensures the delta fits in 32-bits */ 6613 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6614 cpu_preemption_timer_multi); 6615 else 6616 delta_tsc = 0; 6617 6618 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6619 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6620 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6621 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6622 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6623 } 6624 } 6625 6626 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6627 { 6628 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6629 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6630 vmcs_writel(HOST_RSP, host_rsp); 6631 } 6632 } 6633 6634 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu) 6635 { 6636 switch (to_vmx(vcpu)->exit_reason) { 6637 case EXIT_REASON_MSR_WRITE: 6638 return handle_fastpath_set_msr_irqoff(vcpu); 6639 case EXIT_REASON_PREEMPTION_TIMER: 6640 return handle_fastpath_preemption_timer(vcpu); 6641 default: 6642 return EXIT_FASTPATH_NONE; 6643 } 6644 } 6645 6646 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6647 6648 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu) 6649 { 6650 fastpath_t exit_fastpath; 6651 struct vcpu_vmx *vmx = to_vmx(vcpu); 6652 unsigned long cr3, cr4; 6653 6654 reenter_guest: 6655 /* Record the guest's net vcpu time for enforced NMI injections. */ 6656 if (unlikely(!enable_vnmi && 6657 vmx->loaded_vmcs->soft_vnmi_blocked)) 6658 vmx->loaded_vmcs->entry_time = ktime_get(); 6659 6660 /* Don't enter VMX if guest state is invalid, let the exit handler 6661 start emulation until we arrive back to a valid state */ 6662 if (vmx->emulation_required) 6663 return EXIT_FASTPATH_NONE; 6664 6665 if (vmx->ple_window_dirty) { 6666 vmx->ple_window_dirty = false; 6667 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6668 } 6669 6670 /* 6671 * We did this in prepare_switch_to_guest, because it needs to 6672 * be within srcu_read_lock. 6673 */ 6674 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync); 6675 6676 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6677 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6678 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6679 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6680 6681 cr3 = __get_current_cr3_fast(); 6682 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6683 vmcs_writel(HOST_CR3, cr3); 6684 vmx->loaded_vmcs->host_state.cr3 = cr3; 6685 } 6686 6687 cr4 = cr4_read_shadow(); 6688 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6689 vmcs_writel(HOST_CR4, cr4); 6690 vmx->loaded_vmcs->host_state.cr4 = cr4; 6691 } 6692 6693 /* When single-stepping over STI and MOV SS, we must clear the 6694 * corresponding interruptibility bits in the guest state. Otherwise 6695 * vmentry fails as it then expects bit 14 (BS) in pending debug 6696 * exceptions being set, but that's not correct for the guest debugging 6697 * case. */ 6698 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6699 vmx_set_interrupt_shadow(vcpu, 0); 6700 6701 kvm_load_guest_xsave_state(vcpu); 6702 6703 pt_guest_enter(vmx); 6704 6705 if (vcpu_to_pmu(vcpu)->version) 6706 atomic_switch_perf_msrs(vmx); 6707 atomic_switch_umwait_control_msr(vmx); 6708 6709 if (enable_preemption_timer) 6710 vmx_update_hv_timer(vcpu); 6711 6712 if (lapic_in_kernel(vcpu) && 6713 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6714 kvm_wait_lapic_expire(vcpu); 6715 6716 /* 6717 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6718 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6719 * is no need to worry about the conditional branch over the wrmsr 6720 * being speculatively taken. 6721 */ 6722 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6723 6724 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6725 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6726 vmx_l1d_flush(vcpu); 6727 else if (static_branch_unlikely(&mds_user_clear)) 6728 mds_clear_cpu_buffers(); 6729 6730 if (vcpu->arch.cr2 != read_cr2()) 6731 write_cr2(vcpu->arch.cr2); 6732 6733 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6734 vmx->loaded_vmcs->launched); 6735 6736 vcpu->arch.cr2 = read_cr2(); 6737 6738 /* 6739 * We do not use IBRS in the kernel. If this vCPU has used the 6740 * SPEC_CTRL MSR it may have left it on; save the value and 6741 * turn it off. This is much more efficient than blindly adding 6742 * it to the atomic save/restore list. Especially as the former 6743 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6744 * 6745 * For non-nested case: 6746 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6747 * save it. 6748 * 6749 * For nested case: 6750 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6751 * save it. 6752 */ 6753 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6754 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6755 6756 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6757 6758 /* All fields are clean at this point */ 6759 if (static_branch_unlikely(&enable_evmcs)) 6760 current_evmcs->hv_clean_fields |= 6761 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6762 6763 if (static_branch_unlikely(&enable_evmcs)) 6764 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6765 6766 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6767 if (vmx->host_debugctlmsr) 6768 update_debugctlmsr(vmx->host_debugctlmsr); 6769 6770 #ifndef CONFIG_X86_64 6771 /* 6772 * The sysexit path does not restore ds/es, so we must set them to 6773 * a reasonable value ourselves. 6774 * 6775 * We can't defer this to vmx_prepare_switch_to_host() since that 6776 * function may be executed in interrupt context, which saves and 6777 * restore segments around it, nullifying its effect. 6778 */ 6779 loadsegment(ds, __USER_DS); 6780 loadsegment(es, __USER_DS); 6781 #endif 6782 6783 vmx_register_cache_reset(vcpu); 6784 6785 pt_guest_exit(vmx); 6786 6787 kvm_load_host_xsave_state(vcpu); 6788 6789 vmx->nested.nested_run_pending = 0; 6790 vmx->idt_vectoring_info = 0; 6791 6792 if (unlikely(vmx->fail)) { 6793 vmx->exit_reason = 0xdead; 6794 return EXIT_FASTPATH_NONE; 6795 } 6796 6797 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); 6798 if (unlikely((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)) 6799 kvm_machine_check(); 6800 6801 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX); 6802 6803 if (unlikely(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6804 return EXIT_FASTPATH_NONE; 6805 6806 vmx->loaded_vmcs->launched = 1; 6807 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6808 6809 vmx_recover_nmi_blocking(vmx); 6810 vmx_complete_interrupts(vmx); 6811 6812 if (is_guest_mode(vcpu)) 6813 return EXIT_FASTPATH_NONE; 6814 6815 exit_fastpath = vmx_exit_handlers_fastpath(vcpu); 6816 if (exit_fastpath == EXIT_FASTPATH_REENTER_GUEST) { 6817 if (!kvm_vcpu_exit_request(vcpu)) { 6818 /* 6819 * FIXME: this goto should be a loop in vcpu_enter_guest, 6820 * but it would incur the cost of a retpoline for now. 6821 * Revisit once static calls are available. 6822 */ 6823 if (vcpu->arch.apicv_active) 6824 vmx_sync_pir_to_irr(vcpu); 6825 goto reenter_guest; 6826 } 6827 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 6828 } 6829 6830 return exit_fastpath; 6831 } 6832 6833 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6834 { 6835 struct vcpu_vmx *vmx = to_vmx(vcpu); 6836 6837 if (enable_pml) 6838 vmx_destroy_pml_buffer(vmx); 6839 free_vpid(vmx->vpid); 6840 nested_vmx_free_vcpu(vcpu); 6841 free_loaded_vmcs(vmx->loaded_vmcs); 6842 } 6843 6844 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6845 { 6846 struct vcpu_vmx *vmx; 6847 unsigned long *msr_bitmap; 6848 int i, cpu, err; 6849 6850 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6851 vmx = to_vmx(vcpu); 6852 6853 err = -ENOMEM; 6854 6855 vmx->vpid = allocate_vpid(); 6856 6857 /* 6858 * If PML is turned on, failure on enabling PML just results in failure 6859 * of creating the vcpu, therefore we can simplify PML logic (by 6860 * avoiding dealing with cases, such as enabling PML partially on vcpus 6861 * for the guest), etc. 6862 */ 6863 if (enable_pml) { 6864 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6865 if (!vmx->pml_pg) 6866 goto free_vpid; 6867 } 6868 6869 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6870 6871 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6872 u32 index = vmx_msr_index[i]; 6873 u32 data_low, data_high; 6874 int j = vmx->nmsrs; 6875 6876 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6877 continue; 6878 if (wrmsr_safe(index, data_low, data_high) < 0) 6879 continue; 6880 6881 vmx->guest_msrs[j].index = i; 6882 vmx->guest_msrs[j].data = 0; 6883 switch (index) { 6884 case MSR_IA32_TSX_CTRL: 6885 /* 6886 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6887 * let's avoid changing CPUID bits under the host 6888 * kernel's feet. 6889 */ 6890 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6891 break; 6892 default: 6893 vmx->guest_msrs[j].mask = -1ull; 6894 break; 6895 } 6896 ++vmx->nmsrs; 6897 } 6898 6899 err = alloc_loaded_vmcs(&vmx->vmcs01); 6900 if (err < 0) 6901 goto free_pml; 6902 6903 msr_bitmap = vmx->vmcs01.msr_bitmap; 6904 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6905 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6906 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6907 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6908 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6909 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6910 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6911 if (kvm_cstate_in_guest(vcpu->kvm)) { 6912 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6913 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6914 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6915 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6916 } 6917 vmx->msr_bitmap_mode = 0; 6918 6919 vmx->loaded_vmcs = &vmx->vmcs01; 6920 cpu = get_cpu(); 6921 vmx_vcpu_load(vcpu, cpu); 6922 vcpu->cpu = cpu; 6923 init_vmcs(vmx); 6924 vmx_vcpu_put(vcpu); 6925 put_cpu(); 6926 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6927 err = alloc_apic_access_page(vcpu->kvm); 6928 if (err) 6929 goto free_vmcs; 6930 } 6931 6932 if (enable_ept && !enable_unrestricted_guest) { 6933 err = init_rmode_identity_map(vcpu->kvm); 6934 if (err) 6935 goto free_vmcs; 6936 } 6937 6938 if (nested) 6939 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6940 vmx_capability.ept); 6941 else 6942 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6943 6944 vmx->nested.posted_intr_nv = -1; 6945 vmx->nested.current_vmptr = -1ull; 6946 6947 vcpu->arch.microcode_version = 0x100000000ULL; 6948 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6949 6950 /* 6951 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6952 * or POSTED_INTR_WAKEUP_VECTOR. 6953 */ 6954 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6955 vmx->pi_desc.sn = 1; 6956 6957 vmx->ept_pointer = INVALID_PAGE; 6958 6959 return 0; 6960 6961 free_vmcs: 6962 free_loaded_vmcs(vmx->loaded_vmcs); 6963 free_pml: 6964 vmx_destroy_pml_buffer(vmx); 6965 free_vpid: 6966 free_vpid(vmx->vpid); 6967 return err; 6968 } 6969 6970 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6971 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6972 6973 static int vmx_vm_init(struct kvm *kvm) 6974 { 6975 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6976 6977 if (!ple_gap) 6978 kvm->arch.pause_in_guest = true; 6979 6980 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6981 switch (l1tf_mitigation) { 6982 case L1TF_MITIGATION_OFF: 6983 case L1TF_MITIGATION_FLUSH_NOWARN: 6984 /* 'I explicitly don't care' is set */ 6985 break; 6986 case L1TF_MITIGATION_FLUSH: 6987 case L1TF_MITIGATION_FLUSH_NOSMT: 6988 case L1TF_MITIGATION_FULL: 6989 /* 6990 * Warn upon starting the first VM in a potentially 6991 * insecure environment. 6992 */ 6993 if (sched_smt_active()) 6994 pr_warn_once(L1TF_MSG_SMT); 6995 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6996 pr_warn_once(L1TF_MSG_L1D); 6997 break; 6998 case L1TF_MITIGATION_FULL_FORCE: 6999 /* Flush is enforced */ 7000 break; 7001 } 7002 } 7003 kvm_apicv_init(kvm, enable_apicv); 7004 return 0; 7005 } 7006 7007 static int __init vmx_check_processor_compat(void) 7008 { 7009 struct vmcs_config vmcs_conf; 7010 struct vmx_capability vmx_cap; 7011 7012 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 7013 !this_cpu_has(X86_FEATURE_VMX)) { 7014 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 7015 return -EIO; 7016 } 7017 7018 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 7019 return -EIO; 7020 if (nested) 7021 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept); 7022 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 7023 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 7024 smp_processor_id()); 7025 return -EIO; 7026 } 7027 return 0; 7028 } 7029 7030 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 7031 { 7032 u8 cache; 7033 u64 ipat = 0; 7034 7035 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in 7036 * memory aliases with conflicting memory types and sometimes MCEs. 7037 * We have to be careful as to what are honored and when. 7038 * 7039 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to 7040 * UC. The effective memory type is UC or WC depending on guest PAT. 7041 * This was historically the source of MCEs and we want to be 7042 * conservative. 7043 * 7044 * When there is no need to deal with noncoherent DMA (e.g., no VT-d 7045 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The 7046 * EPT memory type is set to WB. The effective memory type is forced 7047 * WB. 7048 * 7049 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The 7050 * EPT memory type is used to emulate guest CD/MTRR. 7051 */ 7052 7053 if (is_mmio) { 7054 cache = MTRR_TYPE_UNCACHABLE; 7055 goto exit; 7056 } 7057 7058 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 7059 ipat = VMX_EPT_IPAT_BIT; 7060 cache = MTRR_TYPE_WRBACK; 7061 goto exit; 7062 } 7063 7064 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 7065 ipat = VMX_EPT_IPAT_BIT; 7066 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 7067 cache = MTRR_TYPE_WRBACK; 7068 else 7069 cache = MTRR_TYPE_UNCACHABLE; 7070 goto exit; 7071 } 7072 7073 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 7074 7075 exit: 7076 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 7077 } 7078 7079 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 7080 { 7081 /* 7082 * These bits in the secondary execution controls field 7083 * are dynamic, the others are mostly based on the hypervisor 7084 * architecture and the guest's CPUID. Do not touch the 7085 * dynamic bits. 7086 */ 7087 u32 mask = 7088 SECONDARY_EXEC_SHADOW_VMCS | 7089 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 7090 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 7091 SECONDARY_EXEC_DESC; 7092 7093 u32 new_ctl = vmx->secondary_exec_control; 7094 u32 cur_ctl = secondary_exec_controls_get(vmx); 7095 7096 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 7097 } 7098 7099 /* 7100 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 7101 * (indicating "allowed-1") if they are supported in the guest's CPUID. 7102 */ 7103 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 7104 { 7105 struct vcpu_vmx *vmx = to_vmx(vcpu); 7106 struct kvm_cpuid_entry2 *entry; 7107 7108 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 7109 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 7110 7111 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 7112 if (entry && (entry->_reg & (_cpuid_mask))) \ 7113 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 7114 } while (0) 7115 7116 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 7117 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 7118 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 7119 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 7120 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 7121 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 7122 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 7123 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 7124 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 7125 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 7126 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 7127 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 7128 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 7129 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 7130 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 7131 7132 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 7133 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 7134 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 7135 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 7136 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 7137 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 7138 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 7139 7140 #undef cr4_fixed1_update 7141 } 7142 7143 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 7144 { 7145 struct vcpu_vmx *vmx = to_vmx(vcpu); 7146 7147 if (kvm_mpx_supported()) { 7148 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 7149 7150 if (mpx_enabled) { 7151 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 7152 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 7153 } else { 7154 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 7155 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 7156 } 7157 } 7158 } 7159 7160 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7161 { 7162 struct vcpu_vmx *vmx = to_vmx(vcpu); 7163 struct kvm_cpuid_entry2 *best = NULL; 7164 int i; 7165 7166 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7167 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7168 if (!best) 7169 return; 7170 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7171 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7172 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7173 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7174 } 7175 7176 /* Get the number of configurable Address Ranges for filtering */ 7177 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7178 PT_CAP_num_address_ranges); 7179 7180 /* Initialize and clear the no dependency bits */ 7181 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7182 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7183 7184 /* 7185 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7186 * will inject an #GP 7187 */ 7188 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7189 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7190 7191 /* 7192 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7193 * PSBFreq can be set 7194 */ 7195 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7196 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7197 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7198 7199 /* 7200 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7201 * MTCFreq can be set 7202 */ 7203 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7204 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7205 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7206 7207 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7208 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7209 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7210 RTIT_CTL_PTW_EN); 7211 7212 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7213 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7214 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7215 7216 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7217 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7218 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7219 7220 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7221 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7222 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7223 7224 /* unmask address range configure area */ 7225 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7226 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7227 } 7228 7229 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7230 { 7231 struct vcpu_vmx *vmx = to_vmx(vcpu); 7232 7233 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7234 vcpu->arch.xsaves_enabled = false; 7235 7236 if (cpu_has_secondary_exec_ctrls()) { 7237 vmx_compute_secondary_exec_control(vmx); 7238 vmcs_set_secondary_exec_control(vmx); 7239 } 7240 7241 if (nested_vmx_allowed(vcpu)) 7242 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7243 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7244 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7245 else 7246 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7247 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7248 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7249 7250 if (nested_vmx_allowed(vcpu)) { 7251 nested_vmx_cr_fixed1_bits_update(vcpu); 7252 nested_vmx_entry_exit_ctls_update(vcpu); 7253 } 7254 7255 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7256 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7257 update_intel_pt_cfg(vcpu); 7258 7259 if (boot_cpu_has(X86_FEATURE_RTM)) { 7260 struct shared_msr_entry *msr; 7261 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7262 if (msr) { 7263 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7264 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7265 } 7266 } 7267 } 7268 7269 static __init void vmx_set_cpu_caps(void) 7270 { 7271 kvm_set_cpu_caps(); 7272 7273 /* CPUID 0x1 */ 7274 if (nested) 7275 kvm_cpu_cap_set(X86_FEATURE_VMX); 7276 7277 /* CPUID 0x7 */ 7278 if (kvm_mpx_supported()) 7279 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX); 7280 if (cpu_has_vmx_invpcid()) 7281 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID); 7282 if (vmx_pt_mode_is_host_guest()) 7283 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT); 7284 7285 /* PKU is not yet implemented for shadow paging. */ 7286 if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE)) 7287 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU); 7288 7289 if (vmx_umip_emulated()) 7290 kvm_cpu_cap_set(X86_FEATURE_UMIP); 7291 7292 /* CPUID 0xD.1 */ 7293 supported_xss = 0; 7294 if (!vmx_xsaves_supported()) 7295 kvm_cpu_cap_clear(X86_FEATURE_XSAVES); 7296 7297 /* CPUID 0x80000001 */ 7298 if (!cpu_has_vmx_rdtscp()) 7299 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 7300 7301 if (vmx_waitpkg_supported()) 7302 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG); 7303 } 7304 7305 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7306 { 7307 to_vmx(vcpu)->req_immediate_exit = true; 7308 } 7309 7310 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, 7311 struct x86_instruction_info *info) 7312 { 7313 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7314 unsigned short port; 7315 bool intercept; 7316 int size; 7317 7318 if (info->intercept == x86_intercept_in || 7319 info->intercept == x86_intercept_ins) { 7320 port = info->src_val; 7321 size = info->dst_bytes; 7322 } else { 7323 port = info->dst_val; 7324 size = info->src_bytes; 7325 } 7326 7327 /* 7328 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction 7329 * VM-exits depend on the 'unconditional IO exiting' VM-execution 7330 * control. 7331 * 7332 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. 7333 */ 7334 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 7335 intercept = nested_cpu_has(vmcs12, 7336 CPU_BASED_UNCOND_IO_EXITING); 7337 else 7338 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); 7339 7340 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7341 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 7342 } 7343 7344 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7345 struct x86_instruction_info *info, 7346 enum x86_intercept_stage stage, 7347 struct x86_exception *exception) 7348 { 7349 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7350 7351 switch (info->intercept) { 7352 /* 7353 * RDPID causes #UD if disabled through secondary execution controls. 7354 * Because it is marked as EmulateOnUD, we need to intercept it here. 7355 */ 7356 case x86_intercept_rdtscp: 7357 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7358 exception->vector = UD_VECTOR; 7359 exception->error_code_valid = false; 7360 return X86EMUL_PROPAGATE_FAULT; 7361 } 7362 break; 7363 7364 case x86_intercept_in: 7365 case x86_intercept_ins: 7366 case x86_intercept_out: 7367 case x86_intercept_outs: 7368 return vmx_check_intercept_io(vcpu, info); 7369 7370 case x86_intercept_lgdt: 7371 case x86_intercept_lidt: 7372 case x86_intercept_lldt: 7373 case x86_intercept_ltr: 7374 case x86_intercept_sgdt: 7375 case x86_intercept_sidt: 7376 case x86_intercept_sldt: 7377 case x86_intercept_str: 7378 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC)) 7379 return X86EMUL_CONTINUE; 7380 7381 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7382 break; 7383 7384 /* TODO: check more intercepts... */ 7385 default: 7386 break; 7387 } 7388 7389 return X86EMUL_UNHANDLEABLE; 7390 } 7391 7392 #ifdef CONFIG_X86_64 7393 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7394 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7395 u64 divisor, u64 *result) 7396 { 7397 u64 low = a << shift, high = a >> (64 - shift); 7398 7399 /* To avoid the overflow on divq */ 7400 if (high >= divisor) 7401 return 1; 7402 7403 /* Low hold the result, high hold rem which is discarded */ 7404 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7405 "rm" (divisor), "0" (low), "1" (high)); 7406 *result = low; 7407 7408 return 0; 7409 } 7410 7411 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7412 bool *expired) 7413 { 7414 struct vcpu_vmx *vmx; 7415 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7416 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7417 7418 vmx = to_vmx(vcpu); 7419 tscl = rdtsc(); 7420 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7421 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7422 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7423 ktimer->timer_advance_ns); 7424 7425 if (delta_tsc > lapic_timer_advance_cycles) 7426 delta_tsc -= lapic_timer_advance_cycles; 7427 else 7428 delta_tsc = 0; 7429 7430 /* Convert to host delta tsc if tsc scaling is enabled */ 7431 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7432 delta_tsc && u64_shl_div_u64(delta_tsc, 7433 kvm_tsc_scaling_ratio_frac_bits, 7434 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7435 return -ERANGE; 7436 7437 /* 7438 * If the delta tsc can't fit in the 32 bit after the multi shift, 7439 * we can't use the preemption timer. 7440 * It's possible that it fits on later vmentries, but checking 7441 * on every vmentry is costly so we just use an hrtimer. 7442 */ 7443 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7444 return -ERANGE; 7445 7446 vmx->hv_deadline_tsc = tscl + delta_tsc; 7447 *expired = !delta_tsc; 7448 return 0; 7449 } 7450 7451 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7452 { 7453 to_vmx(vcpu)->hv_deadline_tsc = -1; 7454 } 7455 #endif 7456 7457 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7458 { 7459 if (!kvm_pause_in_guest(vcpu->kvm)) 7460 shrink_ple_window(vcpu); 7461 } 7462 7463 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7464 struct kvm_memory_slot *slot) 7465 { 7466 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 7467 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7468 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7469 } 7470 7471 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7472 struct kvm_memory_slot *slot) 7473 { 7474 kvm_mmu_slot_set_dirty(kvm, slot); 7475 } 7476 7477 static void vmx_flush_log_dirty(struct kvm *kvm) 7478 { 7479 kvm_flush_pml_buffers(kvm); 7480 } 7481 7482 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7483 { 7484 struct vmcs12 *vmcs12; 7485 struct vcpu_vmx *vmx = to_vmx(vcpu); 7486 gpa_t gpa, dst; 7487 7488 if (is_guest_mode(vcpu)) { 7489 WARN_ON_ONCE(vmx->nested.pml_full); 7490 7491 /* 7492 * Check if PML is enabled for the nested guest. 7493 * Whether eptp bit 6 is set is already checked 7494 * as part of A/D emulation. 7495 */ 7496 vmcs12 = get_vmcs12(vcpu); 7497 if (!nested_cpu_has_pml(vmcs12)) 7498 return 0; 7499 7500 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7501 vmx->nested.pml_full = true; 7502 return 1; 7503 } 7504 7505 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7506 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7507 7508 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7509 offset_in_page(dst), sizeof(gpa))) 7510 return 0; 7511 7512 vmcs12->guest_pml_index--; 7513 } 7514 7515 return 0; 7516 } 7517 7518 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7519 struct kvm_memory_slot *memslot, 7520 gfn_t offset, unsigned long mask) 7521 { 7522 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7523 } 7524 7525 static void __pi_post_block(struct kvm_vcpu *vcpu) 7526 { 7527 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7528 struct pi_desc old, new; 7529 unsigned int dest; 7530 7531 do { 7532 old.control = new.control = pi_desc->control; 7533 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7534 "Wakeup handler not enabled while the VCPU is blocked\n"); 7535 7536 dest = cpu_physical_id(vcpu->cpu); 7537 7538 if (x2apic_enabled()) 7539 new.ndst = dest; 7540 else 7541 new.ndst = (dest << 8) & 0xFF00; 7542 7543 /* set 'NV' to 'notification vector' */ 7544 new.nv = POSTED_INTR_VECTOR; 7545 } while (cmpxchg64(&pi_desc->control, old.control, 7546 new.control) != old.control); 7547 7548 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7549 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7550 list_del(&vcpu->blocked_vcpu_list); 7551 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7552 vcpu->pre_pcpu = -1; 7553 } 7554 } 7555 7556 /* 7557 * This routine does the following things for vCPU which is going 7558 * to be blocked if VT-d PI is enabled. 7559 * - Store the vCPU to the wakeup list, so when interrupts happen 7560 * we can find the right vCPU to wake up. 7561 * - Change the Posted-interrupt descriptor as below: 7562 * 'NDST' <-- vcpu->pre_pcpu 7563 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7564 * - If 'ON' is set during this process, which means at least one 7565 * interrupt is posted for this vCPU, we cannot block it, in 7566 * this case, return 1, otherwise, return 0. 7567 * 7568 */ 7569 static int pi_pre_block(struct kvm_vcpu *vcpu) 7570 { 7571 unsigned int dest; 7572 struct pi_desc old, new; 7573 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7574 7575 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7576 !irq_remapping_cap(IRQ_POSTING_CAP) || 7577 !kvm_vcpu_apicv_active(vcpu)) 7578 return 0; 7579 7580 WARN_ON(irqs_disabled()); 7581 local_irq_disable(); 7582 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7583 vcpu->pre_pcpu = vcpu->cpu; 7584 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7585 list_add_tail(&vcpu->blocked_vcpu_list, 7586 &per_cpu(blocked_vcpu_on_cpu, 7587 vcpu->pre_pcpu)); 7588 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7589 } 7590 7591 do { 7592 old.control = new.control = pi_desc->control; 7593 7594 WARN((pi_desc->sn == 1), 7595 "Warning: SN field of posted-interrupts " 7596 "is set before blocking\n"); 7597 7598 /* 7599 * Since vCPU can be preempted during this process, 7600 * vcpu->cpu could be different with pre_pcpu, we 7601 * need to set pre_pcpu as the destination of wakeup 7602 * notification event, then we can find the right vCPU 7603 * to wakeup in wakeup handler if interrupts happen 7604 * when the vCPU is in blocked state. 7605 */ 7606 dest = cpu_physical_id(vcpu->pre_pcpu); 7607 7608 if (x2apic_enabled()) 7609 new.ndst = dest; 7610 else 7611 new.ndst = (dest << 8) & 0xFF00; 7612 7613 /* set 'NV' to 'wakeup vector' */ 7614 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7615 } while (cmpxchg64(&pi_desc->control, old.control, 7616 new.control) != old.control); 7617 7618 /* We should not block the vCPU if an interrupt is posted for it. */ 7619 if (pi_test_on(pi_desc) == 1) 7620 __pi_post_block(vcpu); 7621 7622 local_irq_enable(); 7623 return (vcpu->pre_pcpu == -1); 7624 } 7625 7626 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7627 { 7628 if (pi_pre_block(vcpu)) 7629 return 1; 7630 7631 if (kvm_lapic_hv_timer_in_use(vcpu)) 7632 kvm_lapic_switch_to_sw_timer(vcpu); 7633 7634 return 0; 7635 } 7636 7637 static void pi_post_block(struct kvm_vcpu *vcpu) 7638 { 7639 if (vcpu->pre_pcpu == -1) 7640 return; 7641 7642 WARN_ON(irqs_disabled()); 7643 local_irq_disable(); 7644 __pi_post_block(vcpu); 7645 local_irq_enable(); 7646 } 7647 7648 static void vmx_post_block(struct kvm_vcpu *vcpu) 7649 { 7650 if (kvm_x86_ops.set_hv_timer) 7651 kvm_lapic_switch_to_hv_timer(vcpu); 7652 7653 pi_post_block(vcpu); 7654 } 7655 7656 /* 7657 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7658 * 7659 * @kvm: kvm 7660 * @host_irq: host irq of the interrupt 7661 * @guest_irq: gsi of the interrupt 7662 * @set: set or unset PI 7663 * returns 0 on success, < 0 on failure 7664 */ 7665 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7666 uint32_t guest_irq, bool set) 7667 { 7668 struct kvm_kernel_irq_routing_entry *e; 7669 struct kvm_irq_routing_table *irq_rt; 7670 struct kvm_lapic_irq irq; 7671 struct kvm_vcpu *vcpu; 7672 struct vcpu_data vcpu_info; 7673 int idx, ret = 0; 7674 7675 if (!kvm_arch_has_assigned_device(kvm) || 7676 !irq_remapping_cap(IRQ_POSTING_CAP) || 7677 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7678 return 0; 7679 7680 idx = srcu_read_lock(&kvm->irq_srcu); 7681 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7682 if (guest_irq >= irq_rt->nr_rt_entries || 7683 hlist_empty(&irq_rt->map[guest_irq])) { 7684 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7685 guest_irq, irq_rt->nr_rt_entries); 7686 goto out; 7687 } 7688 7689 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7690 if (e->type != KVM_IRQ_ROUTING_MSI) 7691 continue; 7692 /* 7693 * VT-d PI cannot support posting multicast/broadcast 7694 * interrupts to a vCPU, we still use interrupt remapping 7695 * for these kind of interrupts. 7696 * 7697 * For lowest-priority interrupts, we only support 7698 * those with single CPU as the destination, e.g. user 7699 * configures the interrupts via /proc/irq or uses 7700 * irqbalance to make the interrupts single-CPU. 7701 * 7702 * We will support full lowest-priority interrupt later. 7703 * 7704 * In addition, we can only inject generic interrupts using 7705 * the PI mechanism, refuse to route others through it. 7706 */ 7707 7708 kvm_set_msi_irq(kvm, e, &irq); 7709 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7710 !kvm_irq_is_postable(&irq)) { 7711 /* 7712 * Make sure the IRTE is in remapped mode if 7713 * we don't handle it in posted mode. 7714 */ 7715 ret = irq_set_vcpu_affinity(host_irq, NULL); 7716 if (ret < 0) { 7717 printk(KERN_INFO 7718 "failed to back to remapped mode, irq: %u\n", 7719 host_irq); 7720 goto out; 7721 } 7722 7723 continue; 7724 } 7725 7726 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7727 vcpu_info.vector = irq.vector; 7728 7729 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7730 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7731 7732 if (set) 7733 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7734 else 7735 ret = irq_set_vcpu_affinity(host_irq, NULL); 7736 7737 if (ret < 0) { 7738 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7739 __func__); 7740 goto out; 7741 } 7742 } 7743 7744 ret = 0; 7745 out: 7746 srcu_read_unlock(&kvm->irq_srcu, idx); 7747 return ret; 7748 } 7749 7750 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7751 { 7752 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7753 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7754 FEAT_CTL_LMCE_ENABLED; 7755 else 7756 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7757 ~FEAT_CTL_LMCE_ENABLED; 7758 } 7759 7760 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection) 7761 { 7762 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7763 if (to_vmx(vcpu)->nested.nested_run_pending) 7764 return -EBUSY; 7765 return !is_smm(vcpu); 7766 } 7767 7768 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7769 { 7770 struct vcpu_vmx *vmx = to_vmx(vcpu); 7771 7772 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7773 if (vmx->nested.smm.guest_mode) 7774 nested_vmx_vmexit(vcpu, -1, 0, 0); 7775 7776 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7777 vmx->nested.vmxon = false; 7778 vmx_clear_hlt(vcpu); 7779 return 0; 7780 } 7781 7782 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7783 { 7784 struct vcpu_vmx *vmx = to_vmx(vcpu); 7785 int ret; 7786 7787 if (vmx->nested.smm.vmxon) { 7788 vmx->nested.vmxon = true; 7789 vmx->nested.smm.vmxon = false; 7790 } 7791 7792 if (vmx->nested.smm.guest_mode) { 7793 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7794 if (ret) 7795 return ret; 7796 7797 vmx->nested.smm.guest_mode = false; 7798 } 7799 return 0; 7800 } 7801 7802 static void enable_smi_window(struct kvm_vcpu *vcpu) 7803 { 7804 /* RSM will cause a vmexit anyway. */ 7805 } 7806 7807 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7808 { 7809 return false; 7810 } 7811 7812 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7813 { 7814 return to_vmx(vcpu)->nested.vmxon; 7815 } 7816 7817 static void vmx_migrate_timers(struct kvm_vcpu *vcpu) 7818 { 7819 if (is_guest_mode(vcpu)) { 7820 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer; 7821 7822 if (hrtimer_try_to_cancel(timer) == 1) 7823 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); 7824 } 7825 } 7826 7827 static void hardware_unsetup(void) 7828 { 7829 if (nested) 7830 nested_vmx_hardware_unsetup(); 7831 7832 free_kvm_area(); 7833 } 7834 7835 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7836 { 7837 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7838 BIT(APICV_INHIBIT_REASON_HYPERV); 7839 7840 return supported & BIT(bit); 7841 } 7842 7843 static struct kvm_x86_ops vmx_x86_ops __initdata = { 7844 .hardware_unsetup = hardware_unsetup, 7845 7846 .hardware_enable = hardware_enable, 7847 .hardware_disable = hardware_disable, 7848 .cpu_has_accelerated_tpr = report_flexpriority, 7849 .has_emulated_msr = vmx_has_emulated_msr, 7850 7851 .vm_size = sizeof(struct kvm_vmx), 7852 .vm_init = vmx_vm_init, 7853 7854 .vcpu_create = vmx_create_vcpu, 7855 .vcpu_free = vmx_free_vcpu, 7856 .vcpu_reset = vmx_vcpu_reset, 7857 7858 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7859 .vcpu_load = vmx_vcpu_load, 7860 .vcpu_put = vmx_vcpu_put, 7861 7862 .update_bp_intercept = update_exception_bitmap, 7863 .get_msr_feature = vmx_get_msr_feature, 7864 .get_msr = vmx_get_msr, 7865 .set_msr = vmx_set_msr, 7866 .get_segment_base = vmx_get_segment_base, 7867 .get_segment = vmx_get_segment, 7868 .set_segment = vmx_set_segment, 7869 .get_cpl = vmx_get_cpl, 7870 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7871 .set_cr0 = vmx_set_cr0, 7872 .set_cr4 = vmx_set_cr4, 7873 .set_efer = vmx_set_efer, 7874 .get_idt = vmx_get_idt, 7875 .set_idt = vmx_set_idt, 7876 .get_gdt = vmx_get_gdt, 7877 .set_gdt = vmx_set_gdt, 7878 .set_dr7 = vmx_set_dr7, 7879 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7880 .cache_reg = vmx_cache_reg, 7881 .get_rflags = vmx_get_rflags, 7882 .set_rflags = vmx_set_rflags, 7883 7884 .tlb_flush_all = vmx_flush_tlb_all, 7885 .tlb_flush_current = vmx_flush_tlb_current, 7886 .tlb_flush_gva = vmx_flush_tlb_gva, 7887 .tlb_flush_guest = vmx_flush_tlb_guest, 7888 7889 .run = vmx_vcpu_run, 7890 .handle_exit = vmx_handle_exit, 7891 .skip_emulated_instruction = vmx_skip_emulated_instruction, 7892 .update_emulated_instruction = vmx_update_emulated_instruction, 7893 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7894 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7895 .patch_hypercall = vmx_patch_hypercall, 7896 .set_irq = vmx_inject_irq, 7897 .set_nmi = vmx_inject_nmi, 7898 .queue_exception = vmx_queue_exception, 7899 .cancel_injection = vmx_cancel_injection, 7900 .interrupt_allowed = vmx_interrupt_allowed, 7901 .nmi_allowed = vmx_nmi_allowed, 7902 .get_nmi_mask = vmx_get_nmi_mask, 7903 .set_nmi_mask = vmx_set_nmi_mask, 7904 .enable_nmi_window = enable_nmi_window, 7905 .enable_irq_window = enable_irq_window, 7906 .update_cr8_intercept = update_cr8_intercept, 7907 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7908 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7909 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7910 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7911 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7912 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7913 .hwapic_irr_update = vmx_hwapic_irr_update, 7914 .hwapic_isr_update = vmx_hwapic_isr_update, 7915 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7916 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7917 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7918 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7919 7920 .set_tss_addr = vmx_set_tss_addr, 7921 .set_identity_map_addr = vmx_set_identity_map_addr, 7922 .get_tdp_level = vmx_get_tdp_level, 7923 .get_mt_mask = vmx_get_mt_mask, 7924 7925 .get_exit_info = vmx_get_exit_info, 7926 7927 .cpuid_update = vmx_cpuid_update, 7928 7929 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7930 7931 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7932 7933 .load_mmu_pgd = vmx_load_mmu_pgd, 7934 7935 .check_intercept = vmx_check_intercept, 7936 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7937 7938 .request_immediate_exit = vmx_request_immediate_exit, 7939 7940 .sched_in = vmx_sched_in, 7941 7942 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7943 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7944 .flush_log_dirty = vmx_flush_log_dirty, 7945 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7946 .write_log_dirty = vmx_write_pml_buffer, 7947 7948 .pre_block = vmx_pre_block, 7949 .post_block = vmx_post_block, 7950 7951 .pmu_ops = &intel_pmu_ops, 7952 .nested_ops = &vmx_nested_ops, 7953 7954 .update_pi_irte = vmx_update_pi_irte, 7955 7956 #ifdef CONFIG_X86_64 7957 .set_hv_timer = vmx_set_hv_timer, 7958 .cancel_hv_timer = vmx_cancel_hv_timer, 7959 #endif 7960 7961 .setup_mce = vmx_setup_mce, 7962 7963 .smi_allowed = vmx_smi_allowed, 7964 .pre_enter_smm = vmx_pre_enter_smm, 7965 .pre_leave_smm = vmx_pre_leave_smm, 7966 .enable_smi_window = enable_smi_window, 7967 7968 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7969 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7970 .migrate_timers = vmx_migrate_timers, 7971 }; 7972 7973 static __init int hardware_setup(void) 7974 { 7975 unsigned long host_bndcfgs; 7976 struct desc_ptr dt; 7977 int r, i, ept_lpage_level; 7978 7979 store_idt(&dt); 7980 host_idt_base = dt.address; 7981 7982 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7983 kvm_define_shared_msr(i, vmx_msr_index[i]); 7984 7985 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7986 return -EIO; 7987 7988 if (boot_cpu_has(X86_FEATURE_NX)) 7989 kvm_enable_efer_bits(EFER_NX); 7990 7991 if (boot_cpu_has(X86_FEATURE_MPX)) { 7992 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7993 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7994 } 7995 7996 if (!cpu_has_vmx_mpx()) 7997 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | 7998 XFEATURE_MASK_BNDCSR); 7999 8000 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 8001 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 8002 enable_vpid = 0; 8003 8004 if (!cpu_has_vmx_ept() || 8005 !cpu_has_vmx_ept_4levels() || 8006 !cpu_has_vmx_ept_mt_wb() || 8007 !cpu_has_vmx_invept_global()) 8008 enable_ept = 0; 8009 8010 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 8011 enable_ept_ad_bits = 0; 8012 8013 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 8014 enable_unrestricted_guest = 0; 8015 8016 if (!cpu_has_vmx_flexpriority()) 8017 flexpriority_enabled = 0; 8018 8019 if (!cpu_has_virtual_nmis()) 8020 enable_vnmi = 0; 8021 8022 /* 8023 * set_apic_access_page_addr() is used to reload apic access 8024 * page upon invalidation. No need to do anything if not 8025 * using the APIC_ACCESS_ADDR VMCS field. 8026 */ 8027 if (!flexpriority_enabled) 8028 vmx_x86_ops.set_apic_access_page_addr = NULL; 8029 8030 if (!cpu_has_vmx_tpr_shadow()) 8031 vmx_x86_ops.update_cr8_intercept = NULL; 8032 8033 #if IS_ENABLED(CONFIG_HYPERV) 8034 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 8035 && enable_ept) { 8036 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb; 8037 vmx_x86_ops.tlb_remote_flush_with_range = 8038 hv_remote_flush_tlb_with_range; 8039 } 8040 #endif 8041 8042 if (!cpu_has_vmx_ple()) { 8043 ple_gap = 0; 8044 ple_window = 0; 8045 ple_window_grow = 0; 8046 ple_window_max = 0; 8047 ple_window_shrink = 0; 8048 } 8049 8050 if (!cpu_has_vmx_apicv()) { 8051 enable_apicv = 0; 8052 vmx_x86_ops.sync_pir_to_irr = NULL; 8053 } 8054 8055 if (cpu_has_vmx_tsc_scaling()) { 8056 kvm_has_tsc_control = true; 8057 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 8058 kvm_tsc_scaling_ratio_frac_bits = 48; 8059 } 8060 8061 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 8062 8063 if (enable_ept) 8064 vmx_enable_tdp(); 8065 8066 if (!enable_ept) 8067 ept_lpage_level = 0; 8068 else if (cpu_has_vmx_ept_1g_page()) 8069 ept_lpage_level = PG_LEVEL_1G; 8070 else if (cpu_has_vmx_ept_2m_page()) 8071 ept_lpage_level = PG_LEVEL_2M; 8072 else 8073 ept_lpage_level = PG_LEVEL_4K; 8074 kvm_configure_mmu(enable_ept, ept_lpage_level); 8075 8076 /* 8077 * Only enable PML when hardware supports PML feature, and both EPT 8078 * and EPT A/D bit features are enabled -- PML depends on them to work. 8079 */ 8080 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 8081 enable_pml = 0; 8082 8083 if (!enable_pml) { 8084 vmx_x86_ops.slot_enable_log_dirty = NULL; 8085 vmx_x86_ops.slot_disable_log_dirty = NULL; 8086 vmx_x86_ops.flush_log_dirty = NULL; 8087 vmx_x86_ops.enable_log_dirty_pt_masked = NULL; 8088 } 8089 8090 if (!cpu_has_vmx_preemption_timer()) 8091 enable_preemption_timer = false; 8092 8093 if (enable_preemption_timer) { 8094 u64 use_timer_freq = 5000ULL * 1000 * 1000; 8095 u64 vmx_msr; 8096 8097 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 8098 cpu_preemption_timer_multi = 8099 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 8100 8101 if (tsc_khz) 8102 use_timer_freq = (u64)tsc_khz * 1000; 8103 use_timer_freq >>= cpu_preemption_timer_multi; 8104 8105 /* 8106 * KVM "disables" the preemption timer by setting it to its max 8107 * value. Don't use the timer if it might cause spurious exits 8108 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 8109 */ 8110 if (use_timer_freq > 0xffffffffu / 10) 8111 enable_preemption_timer = false; 8112 } 8113 8114 if (!enable_preemption_timer) { 8115 vmx_x86_ops.set_hv_timer = NULL; 8116 vmx_x86_ops.cancel_hv_timer = NULL; 8117 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit; 8118 } 8119 8120 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 8121 8122 kvm_mce_cap_supported |= MCG_LMCE_P; 8123 8124 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 8125 return -EINVAL; 8126 if (!enable_ept || !cpu_has_vmx_intel_pt()) 8127 pt_mode = PT_MODE_SYSTEM; 8128 8129 if (nested) { 8130 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 8131 vmx_capability.ept); 8132 8133 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 8134 if (r) 8135 return r; 8136 } 8137 8138 vmx_set_cpu_caps(); 8139 8140 r = alloc_kvm_area(); 8141 if (r) 8142 nested_vmx_hardware_unsetup(); 8143 return r; 8144 } 8145 8146 static struct kvm_x86_init_ops vmx_init_ops __initdata = { 8147 .cpu_has_kvm_support = cpu_has_kvm_support, 8148 .disabled_by_bios = vmx_disabled_by_bios, 8149 .check_processor_compatibility = vmx_check_processor_compat, 8150 .hardware_setup = hardware_setup, 8151 8152 .runtime_ops = &vmx_x86_ops, 8153 }; 8154 8155 static void vmx_cleanup_l1d_flush(void) 8156 { 8157 if (vmx_l1d_flush_pages) { 8158 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 8159 vmx_l1d_flush_pages = NULL; 8160 } 8161 /* Restore state so sysfs ignores VMX */ 8162 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 8163 } 8164 8165 static void vmx_exit(void) 8166 { 8167 #ifdef CONFIG_KEXEC_CORE 8168 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 8169 synchronize_rcu(); 8170 #endif 8171 8172 kvm_exit(); 8173 8174 #if IS_ENABLED(CONFIG_HYPERV) 8175 if (static_branch_unlikely(&enable_evmcs)) { 8176 int cpu; 8177 struct hv_vp_assist_page *vp_ap; 8178 /* 8179 * Reset everything to support using non-enlightened VMCS 8180 * access later (e.g. when we reload the module with 8181 * enlightened_vmcs=0) 8182 */ 8183 for_each_online_cpu(cpu) { 8184 vp_ap = hv_get_vp_assist_page(cpu); 8185 8186 if (!vp_ap) 8187 continue; 8188 8189 vp_ap->nested_control.features.directhypercall = 0; 8190 vp_ap->current_nested_vmcs = 0; 8191 vp_ap->enlighten_vmentry = 0; 8192 } 8193 8194 static_branch_disable(&enable_evmcs); 8195 } 8196 #endif 8197 vmx_cleanup_l1d_flush(); 8198 } 8199 module_exit(vmx_exit); 8200 8201 static int __init vmx_init(void) 8202 { 8203 int r, cpu; 8204 8205 #if IS_ENABLED(CONFIG_HYPERV) 8206 /* 8207 * Enlightened VMCS usage should be recommended and the host needs 8208 * to support eVMCS v1 or above. We can also disable eVMCS support 8209 * with module parameter. 8210 */ 8211 if (enlightened_vmcs && 8212 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 8213 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 8214 KVM_EVMCS_VERSION) { 8215 int cpu; 8216 8217 /* Check that we have assist pages on all online CPUs */ 8218 for_each_online_cpu(cpu) { 8219 if (!hv_get_vp_assist_page(cpu)) { 8220 enlightened_vmcs = false; 8221 break; 8222 } 8223 } 8224 8225 if (enlightened_vmcs) { 8226 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 8227 static_branch_enable(&enable_evmcs); 8228 } 8229 8230 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 8231 vmx_x86_ops.enable_direct_tlbflush 8232 = hv_enable_direct_tlbflush; 8233 8234 } else { 8235 enlightened_vmcs = false; 8236 } 8237 #endif 8238 8239 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx), 8240 __alignof__(struct vcpu_vmx), THIS_MODULE); 8241 if (r) 8242 return r; 8243 8244 /* 8245 * Must be called after kvm_init() so enable_ept is properly set 8246 * up. Hand the parameter mitigation value in which was stored in 8247 * the pre module init parser. If no parameter was given, it will 8248 * contain 'auto' which will be turned into the default 'cond' 8249 * mitigation mode. 8250 */ 8251 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 8252 if (r) { 8253 vmx_exit(); 8254 return r; 8255 } 8256 8257 for_each_possible_cpu(cpu) { 8258 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 8259 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 8260 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 8261 } 8262 8263 #ifdef CONFIG_KEXEC_CORE 8264 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 8265 crash_vmclear_local_loaded_vmcss); 8266 #endif 8267 vmx_check_vmcs12_offsets(); 8268 8269 return 0; 8270 } 8271 module_init(vmx_init); 8272