1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/debugreg.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/io.h> 38 #include <asm/irq_remapping.h> 39 #include <asm/kexec.h> 40 #include <asm/perf_event.h> 41 #include <asm/mce.h> 42 #include <asm/mmu_context.h> 43 #include <asm/mshyperv.h> 44 #include <asm/spec-ctrl.h> 45 #include <asm/virtext.h> 46 #include <asm/vmx.h> 47 48 #include "capabilities.h" 49 #include "cpuid.h" 50 #include "evmcs.h" 51 #include "irq.h" 52 #include "kvm_cache_regs.h" 53 #include "lapic.h" 54 #include "mmu.h" 55 #include "nested.h" 56 #include "ops.h" 57 #include "pmu.h" 58 #include "trace.h" 59 #include "vmcs.h" 60 #include "vmcs12.h" 61 #include "vmx.h" 62 #include "x86.h" 63 64 MODULE_AUTHOR("Qumranet"); 65 MODULE_LICENSE("GPL"); 66 67 static const struct x86_cpu_id vmx_cpu_id[] = { 68 X86_FEATURE_MATCH(X86_FEATURE_VMX), 69 {} 70 }; 71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 72 73 bool __read_mostly enable_vpid = 1; 74 module_param_named(vpid, enable_vpid, bool, 0444); 75 76 static bool __read_mostly enable_vnmi = 1; 77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 78 79 bool __read_mostly flexpriority_enabled = 1; 80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 81 82 bool __read_mostly enable_ept = 1; 83 module_param_named(ept, enable_ept, bool, S_IRUGO); 84 85 bool __read_mostly enable_unrestricted_guest = 1; 86 module_param_named(unrestricted_guest, 87 enable_unrestricted_guest, bool, S_IRUGO); 88 89 bool __read_mostly enable_ept_ad_bits = 1; 90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 91 92 static bool __read_mostly emulate_invalid_guest_state = true; 93 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 94 95 static bool __read_mostly fasteoi = 1; 96 module_param(fasteoi, bool, S_IRUGO); 97 98 static bool __read_mostly enable_apicv = 1; 99 module_param(enable_apicv, bool, S_IRUGO); 100 101 /* 102 * If nested=1, nested virtualization is supported, i.e., guests may use 103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 104 * use VMX instructions. 105 */ 106 static bool __read_mostly nested = 1; 107 module_param(nested, bool, S_IRUGO); 108 109 bool __read_mostly enable_pml = 1; 110 module_param_named(pml, enable_pml, bool, S_IRUGO); 111 112 static bool __read_mostly dump_invalid_vmcs = 0; 113 module_param(dump_invalid_vmcs, bool, 0644); 114 115 #define MSR_BITMAP_MODE_X2APIC 1 116 #define MSR_BITMAP_MODE_X2APIC_APICV 2 117 118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 119 120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 121 static int __read_mostly cpu_preemption_timer_multi; 122 static bool __read_mostly enable_preemption_timer = 1; 123 #ifdef CONFIG_X86_64 124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 125 #endif 126 127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 129 #define KVM_VM_CR0_ALWAYS_ON \ 130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 132 #define KVM_CR4_GUEST_OWNED_BITS \ 133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 135 136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 139 140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 141 142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 145 RTIT_STATUS_BYTECNT)) 146 147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 149 150 /* 151 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 152 * ple_gap: upper bound on the amount of time between two successive 153 * executions of PAUSE in a loop. Also indicate if ple enabled. 154 * According to test, this time is usually smaller than 128 cycles. 155 * ple_window: upper bound on the amount of time a guest is allowed to execute 156 * in a PAUSE loop. Tests indicate that most spinlocks are held for 157 * less than 2^12 cycles 158 * Time is measured based on a counter that runs at the same rate as the TSC, 159 * refer SDM volume 3b section 21.6.13 & 22.1.3. 160 */ 161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 162 module_param(ple_gap, uint, 0444); 163 164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 165 module_param(ple_window, uint, 0444); 166 167 /* Default doubles per-vcpu window every exit. */ 168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 169 module_param(ple_window_grow, uint, 0444); 170 171 /* Default resets per-vcpu window every exit to ple_window. */ 172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 173 module_param(ple_window_shrink, uint, 0444); 174 175 /* Default is to compute the maximum so we can never overflow. */ 176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 177 module_param(ple_window_max, uint, 0444); 178 179 /* Default is SYSTEM mode, 1 for host-guest mode */ 180 int __read_mostly pt_mode = PT_MODE_SYSTEM; 181 module_param(pt_mode, int, S_IRUGO); 182 183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 185 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 186 187 /* Storage for pre module init parameter parsing */ 188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 189 190 static const struct { 191 const char *option; 192 bool for_parse; 193 } vmentry_l1d_param[] = { 194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 196 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 200 }; 201 202 #define L1D_CACHE_ORDER 4 203 static void *vmx_l1d_flush_pages; 204 205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 206 { 207 struct page *page; 208 unsigned int i; 209 210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 212 return 0; 213 } 214 215 if (!enable_ept) { 216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 217 return 0; 218 } 219 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 221 u64 msr; 222 223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 226 return 0; 227 } 228 } 229 230 /* If set to auto use the default l1tf mitigation method */ 231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 232 switch (l1tf_mitigation) { 233 case L1TF_MITIGATION_OFF: 234 l1tf = VMENTER_L1D_FLUSH_NEVER; 235 break; 236 case L1TF_MITIGATION_FLUSH_NOWARN: 237 case L1TF_MITIGATION_FLUSH: 238 case L1TF_MITIGATION_FLUSH_NOSMT: 239 l1tf = VMENTER_L1D_FLUSH_COND; 240 break; 241 case L1TF_MITIGATION_FULL: 242 case L1TF_MITIGATION_FULL_FORCE: 243 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 244 break; 245 } 246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 } 249 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 252 /* 253 * This allocation for vmx_l1d_flush_pages is not tied to a VM 254 * lifetime and so should not be charged to a memcg. 255 */ 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 257 if (!page) 258 return -ENOMEM; 259 vmx_l1d_flush_pages = page_address(page); 260 261 /* 262 * Initialize each page with a different pattern in 263 * order to protect against KSM in the nested 264 * virtualization case. 265 */ 266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 268 PAGE_SIZE); 269 } 270 } 271 272 l1tf_vmx_mitigation = l1tf; 273 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 275 static_branch_enable(&vmx_l1d_should_flush); 276 else 277 static_branch_disable(&vmx_l1d_should_flush); 278 279 if (l1tf == VMENTER_L1D_FLUSH_COND) 280 static_branch_enable(&vmx_l1d_flush_cond); 281 else 282 static_branch_disable(&vmx_l1d_flush_cond); 283 return 0; 284 } 285 286 static int vmentry_l1d_flush_parse(const char *s) 287 { 288 unsigned int i; 289 290 if (s) { 291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 292 if (vmentry_l1d_param[i].for_parse && 293 sysfs_streq(s, vmentry_l1d_param[i].option)) 294 return i; 295 } 296 } 297 return -EINVAL; 298 } 299 300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 301 { 302 int l1tf, ret; 303 304 l1tf = vmentry_l1d_flush_parse(s); 305 if (l1tf < 0) 306 return l1tf; 307 308 if (!boot_cpu_has(X86_BUG_L1TF)) 309 return 0; 310 311 /* 312 * Has vmx_init() run already? If not then this is the pre init 313 * parameter parsing. In that case just store the value and let 314 * vmx_init() do the proper setup after enable_ept has been 315 * established. 316 */ 317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 318 vmentry_l1d_flush_param = l1tf; 319 return 0; 320 } 321 322 mutex_lock(&vmx_l1d_flush_mutex); 323 ret = vmx_setup_l1d_flush(l1tf); 324 mutex_unlock(&vmx_l1d_flush_mutex); 325 return ret; 326 } 327 328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 329 { 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 331 return sprintf(s, "???\n"); 332 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 334 } 335 336 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 337 .set = vmentry_l1d_flush_set, 338 .get = vmentry_l1d_flush_get, 339 }; 340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 341 342 static bool guest_state_valid(struct kvm_vcpu *vcpu); 343 static u32 vmx_segment_access_rights(struct kvm_segment *var); 344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 345 u32 msr, int type); 346 347 void vmx_vmexit(void); 348 349 #define vmx_insn_failed(fmt...) \ 350 do { \ 351 WARN_ONCE(1, fmt); \ 352 pr_warn_ratelimited(fmt); \ 353 } while (0) 354 355 asmlinkage void vmread_error(unsigned long field, bool fault) 356 { 357 if (fault) 358 kvm_spurious_fault(); 359 else 360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 361 } 362 363 noinline void vmwrite_error(unsigned long field, unsigned long value) 364 { 365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 367 } 368 369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 370 { 371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 372 } 373 374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 375 { 376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 377 } 378 379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 380 { 381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 382 ext, vpid, gva); 383 } 384 385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 386 { 387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 388 ext, eptp, gpa); 389 } 390 391 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 392 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 393 /* 394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 396 */ 397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 398 399 /* 400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 401 * can find which vCPU should be waken up. 402 */ 403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 405 406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 407 static DEFINE_SPINLOCK(vmx_vpid_lock); 408 409 struct vmcs_config vmcs_config; 410 struct vmx_capability vmx_capability; 411 412 #define VMX_SEGMENT_FIELD(seg) \ 413 [VCPU_SREG_##seg] = { \ 414 .selector = GUEST_##seg##_SELECTOR, \ 415 .base = GUEST_##seg##_BASE, \ 416 .limit = GUEST_##seg##_LIMIT, \ 417 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 418 } 419 420 static const struct kvm_vmx_segment_field { 421 unsigned selector; 422 unsigned base; 423 unsigned limit; 424 unsigned ar_bytes; 425 } kvm_vmx_segment_fields[] = { 426 VMX_SEGMENT_FIELD(CS), 427 VMX_SEGMENT_FIELD(DS), 428 VMX_SEGMENT_FIELD(ES), 429 VMX_SEGMENT_FIELD(FS), 430 VMX_SEGMENT_FIELD(GS), 431 VMX_SEGMENT_FIELD(SS), 432 VMX_SEGMENT_FIELD(TR), 433 VMX_SEGMENT_FIELD(LDTR), 434 }; 435 436 u64 host_efer; 437 static unsigned long host_idt_base; 438 439 /* 440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 441 * will emulate SYSCALL in legacy mode if the vendor string in guest 442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 443 * support this emulation, IA32_STAR must always be included in 444 * vmx_msr_index[], even in i386 builds. 445 */ 446 const u32 vmx_msr_index[] = { 447 #ifdef CONFIG_X86_64 448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 449 #endif 450 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 451 MSR_IA32_TSX_CTRL, 452 }; 453 454 #if IS_ENABLED(CONFIG_HYPERV) 455 static bool __read_mostly enlightened_vmcs = true; 456 module_param(enlightened_vmcs, bool, 0444); 457 458 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 459 static void check_ept_pointer_match(struct kvm *kvm) 460 { 461 struct kvm_vcpu *vcpu; 462 u64 tmp_eptp = INVALID_PAGE; 463 int i; 464 465 kvm_for_each_vcpu(i, vcpu, kvm) { 466 if (!VALID_PAGE(tmp_eptp)) { 467 tmp_eptp = to_vmx(vcpu)->ept_pointer; 468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 469 to_kvm_vmx(kvm)->ept_pointers_match 470 = EPT_POINTERS_MISMATCH; 471 return; 472 } 473 } 474 475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 476 } 477 478 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 479 void *data) 480 { 481 struct kvm_tlb_range *range = data; 482 483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 484 range->pages); 485 } 486 487 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 489 { 490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 491 492 /* 493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 494 * of the base of EPT PML4 table, strip off EPT configuration 495 * information. 496 */ 497 if (range) 498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 499 kvm_fill_hv_flush_list_func, (void *)range); 500 else 501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 502 } 503 504 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 505 struct kvm_tlb_range *range) 506 { 507 struct kvm_vcpu *vcpu; 508 int ret = 0, i; 509 510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 511 512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 513 check_ept_pointer_match(kvm); 514 515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 516 kvm_for_each_vcpu(i, vcpu, kvm) { 517 /* If ept_pointer is invalid pointer, bypass flush request. */ 518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 519 ret |= __hv_remote_flush_tlb_with_range( 520 kvm, vcpu, range); 521 } 522 } else { 523 ret = __hv_remote_flush_tlb_with_range(kvm, 524 kvm_get_vcpu(kvm, 0), range); 525 } 526 527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 528 return ret; 529 } 530 static int hv_remote_flush_tlb(struct kvm *kvm) 531 { 532 return hv_remote_flush_tlb_with_range(kvm, NULL); 533 } 534 535 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 536 { 537 struct hv_enlightened_vmcs *evmcs; 538 struct hv_partition_assist_pg **p_hv_pa_pg = 539 &vcpu->kvm->arch.hyperv.hv_pa_pg; 540 /* 541 * Synthetic VM-Exit is not enabled in current code and so All 542 * evmcs in singe VM shares same assist page. 543 */ 544 if (!*p_hv_pa_pg) 545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 546 547 if (!*p_hv_pa_pg) 548 return -ENOMEM; 549 550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 551 552 evmcs->partition_assist_page = 553 __pa(*p_hv_pa_pg); 554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 556 557 return 0; 558 } 559 560 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 561 562 /* 563 * Comment's format: document - errata name - stepping - processor name. 564 * Refer from 565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 566 */ 567 static u32 vmx_preemption_cpu_tfms[] = { 568 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 569 0x000206E6, 570 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 571 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 572 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 573 0x00020652, 574 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 575 0x00020655, 576 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 577 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 578 /* 579 * 320767.pdf - AAP86 - B1 - 580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 581 */ 582 0x000106E5, 583 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 584 0x000106A0, 585 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 586 0x000106A1, 587 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 588 0x000106A4, 589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 592 0x000106A5, 593 /* Xeon E3-1220 V2 */ 594 0x000306A8, 595 }; 596 597 static inline bool cpu_has_broken_vmx_preemption_timer(void) 598 { 599 u32 eax = cpuid_eax(0x00000001), i; 600 601 /* Clear the reserved bits */ 602 eax &= ~(0x3U << 14 | 0xfU << 28); 603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 604 if (eax == vmx_preemption_cpu_tfms[i]) 605 return true; 606 607 return false; 608 } 609 610 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 611 { 612 return flexpriority_enabled && lapic_in_kernel(vcpu); 613 } 614 615 static inline bool report_flexpriority(void) 616 { 617 return flexpriority_enabled; 618 } 619 620 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 621 { 622 int i; 623 624 for (i = 0; i < vmx->nmsrs; ++i) 625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 626 return i; 627 return -1; 628 } 629 630 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 631 { 632 int i; 633 634 i = __find_msr_index(vmx, msr); 635 if (i >= 0) 636 return &vmx->guest_msrs[i]; 637 return NULL; 638 } 639 640 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 641 { 642 int ret = 0; 643 644 u64 old_msr_data = msr->data; 645 msr->data = data; 646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 647 preempt_disable(); 648 ret = kvm_set_shared_msr(msr->index, msr->data, 649 msr->mask); 650 preempt_enable(); 651 if (ret) 652 msr->data = old_msr_data; 653 } 654 return ret; 655 } 656 657 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 658 { 659 vmcs_clear(loaded_vmcs->vmcs); 660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 661 vmcs_clear(loaded_vmcs->shadow_vmcs); 662 loaded_vmcs->cpu = -1; 663 loaded_vmcs->launched = 0; 664 } 665 666 #ifdef CONFIG_KEXEC_CORE 667 /* 668 * This bitmap is used to indicate whether the vmclear 669 * operation is enabled on all cpus. All disabled by 670 * default. 671 */ 672 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 673 674 static inline void crash_enable_local_vmclear(int cpu) 675 { 676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 677 } 678 679 static inline void crash_disable_local_vmclear(int cpu) 680 { 681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 682 } 683 684 static inline int crash_local_vmclear_enabled(int cpu) 685 { 686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 687 } 688 689 static void crash_vmclear_local_loaded_vmcss(void) 690 { 691 int cpu = raw_smp_processor_id(); 692 struct loaded_vmcs *v; 693 694 if (!crash_local_vmclear_enabled(cpu)) 695 return; 696 697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 698 loaded_vmcss_on_cpu_link) 699 vmcs_clear(v->vmcs); 700 } 701 #else 702 static inline void crash_enable_local_vmclear(int cpu) { } 703 static inline void crash_disable_local_vmclear(int cpu) { } 704 #endif /* CONFIG_KEXEC_CORE */ 705 706 static void __loaded_vmcs_clear(void *arg) 707 { 708 struct loaded_vmcs *loaded_vmcs = arg; 709 int cpu = raw_smp_processor_id(); 710 711 if (loaded_vmcs->cpu != cpu) 712 return; /* vcpu migration can race with cpu offline */ 713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 714 per_cpu(current_vmcs, cpu) = NULL; 715 crash_disable_local_vmclear(cpu); 716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 717 718 /* 719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 720 * is before setting loaded_vmcs->vcpu to -1 which is done in 721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 722 * then adds the vmcs into percpu list before it is deleted. 723 */ 724 smp_wmb(); 725 726 loaded_vmcs_init(loaded_vmcs); 727 crash_enable_local_vmclear(cpu); 728 } 729 730 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 731 { 732 int cpu = loaded_vmcs->cpu; 733 734 if (cpu != -1) 735 smp_call_function_single(cpu, 736 __loaded_vmcs_clear, loaded_vmcs, 1); 737 } 738 739 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 740 unsigned field) 741 { 742 bool ret; 743 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 744 745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 747 vmx->segment_cache.bitmask = 0; 748 } 749 ret = vmx->segment_cache.bitmask & mask; 750 vmx->segment_cache.bitmask |= mask; 751 return ret; 752 } 753 754 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 755 { 756 u16 *p = &vmx->segment_cache.seg[seg].selector; 757 758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 760 return *p; 761 } 762 763 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 764 { 765 ulong *p = &vmx->segment_cache.seg[seg].base; 766 767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 769 return *p; 770 } 771 772 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 773 { 774 u32 *p = &vmx->segment_cache.seg[seg].limit; 775 776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 778 return *p; 779 } 780 781 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 782 { 783 u32 *p = &vmx->segment_cache.seg[seg].ar; 784 785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 787 return *p; 788 } 789 790 void update_exception_bitmap(struct kvm_vcpu *vcpu) 791 { 792 u32 eb; 793 794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 795 (1u << DB_VECTOR) | (1u << AC_VECTOR); 796 /* 797 * Guest access to VMware backdoor ports could legitimately 798 * trigger #GP because of TSS I/O permission bitmap. 799 * We intercept those #GP and allow access to them anyway 800 * as VMware does. 801 */ 802 if (enable_vmware_backdoor) 803 eb |= (1u << GP_VECTOR); 804 if ((vcpu->guest_debug & 805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 807 eb |= 1u << BP_VECTOR; 808 if (to_vmx(vcpu)->rmode.vm86_active) 809 eb = ~0; 810 if (enable_ept) 811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 812 813 /* When we are running a nested L2 guest and L1 specified for it a 814 * certain exception bitmap, we must trap the same exceptions and pass 815 * them to L1. When running L2, we will only handle the exceptions 816 * specified above if L1 did not want them. 817 */ 818 if (is_guest_mode(vcpu)) 819 eb |= get_vmcs12(vcpu)->exception_bitmap; 820 821 vmcs_write32(EXCEPTION_BITMAP, eb); 822 } 823 824 /* 825 * Check if MSR is intercepted for currently loaded MSR bitmap. 826 */ 827 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 828 { 829 unsigned long *msr_bitmap; 830 int f = sizeof(unsigned long); 831 832 if (!cpu_has_vmx_msr_bitmap()) 833 return true; 834 835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 836 837 if (msr <= 0x1fff) { 838 return !!test_bit(msr, msr_bitmap + 0x800 / f); 839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 840 msr &= 0x1fff; 841 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 842 } 843 844 return true; 845 } 846 847 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 848 unsigned long entry, unsigned long exit) 849 { 850 vm_entry_controls_clearbit(vmx, entry); 851 vm_exit_controls_clearbit(vmx, exit); 852 } 853 854 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 855 { 856 unsigned int i; 857 858 for (i = 0; i < m->nr; ++i) { 859 if (m->val[i].index == msr) 860 return i; 861 } 862 return -ENOENT; 863 } 864 865 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 866 { 867 int i; 868 struct msr_autoload *m = &vmx->msr_autoload; 869 870 switch (msr) { 871 case MSR_EFER: 872 if (cpu_has_load_ia32_efer()) { 873 clear_atomic_switch_msr_special(vmx, 874 VM_ENTRY_LOAD_IA32_EFER, 875 VM_EXIT_LOAD_IA32_EFER); 876 return; 877 } 878 break; 879 case MSR_CORE_PERF_GLOBAL_CTRL: 880 if (cpu_has_load_perf_global_ctrl()) { 881 clear_atomic_switch_msr_special(vmx, 882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 884 return; 885 } 886 break; 887 } 888 i = vmx_find_msr_index(&m->guest, msr); 889 if (i < 0) 890 goto skip_guest; 891 --m->guest.nr; 892 m->guest.val[i] = m->guest.val[m->guest.nr]; 893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 894 895 skip_guest: 896 i = vmx_find_msr_index(&m->host, msr); 897 if (i < 0) 898 return; 899 900 --m->host.nr; 901 m->host.val[i] = m->host.val[m->host.nr]; 902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 903 } 904 905 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 906 unsigned long entry, unsigned long exit, 907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 908 u64 guest_val, u64 host_val) 909 { 910 vmcs_write64(guest_val_vmcs, guest_val); 911 if (host_val_vmcs != HOST_IA32_EFER) 912 vmcs_write64(host_val_vmcs, host_val); 913 vm_entry_controls_setbit(vmx, entry); 914 vm_exit_controls_setbit(vmx, exit); 915 } 916 917 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 918 u64 guest_val, u64 host_val, bool entry_only) 919 { 920 int i, j = 0; 921 struct msr_autoload *m = &vmx->msr_autoload; 922 923 switch (msr) { 924 case MSR_EFER: 925 if (cpu_has_load_ia32_efer()) { 926 add_atomic_switch_msr_special(vmx, 927 VM_ENTRY_LOAD_IA32_EFER, 928 VM_EXIT_LOAD_IA32_EFER, 929 GUEST_IA32_EFER, 930 HOST_IA32_EFER, 931 guest_val, host_val); 932 return; 933 } 934 break; 935 case MSR_CORE_PERF_GLOBAL_CTRL: 936 if (cpu_has_load_perf_global_ctrl()) { 937 add_atomic_switch_msr_special(vmx, 938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 940 GUEST_IA32_PERF_GLOBAL_CTRL, 941 HOST_IA32_PERF_GLOBAL_CTRL, 942 guest_val, host_val); 943 return; 944 } 945 break; 946 case MSR_IA32_PEBS_ENABLE: 947 /* PEBS needs a quiescent period after being disabled (to write 948 * a record). Disabling PEBS through VMX MSR swapping doesn't 949 * provide that period, so a CPU could write host's record into 950 * guest's memory. 951 */ 952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 953 } 954 955 i = vmx_find_msr_index(&m->guest, msr); 956 if (!entry_only) 957 j = vmx_find_msr_index(&m->host, msr); 958 959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 961 printk_once(KERN_WARNING "Not enough msr switch entries. " 962 "Can't add msr %x\n", msr); 963 return; 964 } 965 if (i < 0) { 966 i = m->guest.nr++; 967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 968 } 969 m->guest.val[i].index = msr; 970 m->guest.val[i].value = guest_val; 971 972 if (entry_only) 973 return; 974 975 if (j < 0) { 976 j = m->host.nr++; 977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 978 } 979 m->host.val[j].index = msr; 980 m->host.val[j].value = host_val; 981 } 982 983 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 984 { 985 u64 guest_efer = vmx->vcpu.arch.efer; 986 u64 ignore_bits = 0; 987 988 /* Shadow paging assumes NX to be available. */ 989 if (!enable_ept) 990 guest_efer |= EFER_NX; 991 992 /* 993 * LMA and LME handled by hardware; SCE meaningless outside long mode. 994 */ 995 ignore_bits |= EFER_SCE; 996 #ifdef CONFIG_X86_64 997 ignore_bits |= EFER_LMA | EFER_LME; 998 /* SCE is meaningful only in long mode on Intel */ 999 if (guest_efer & EFER_LMA) 1000 ignore_bits &= ~(u64)EFER_SCE; 1001 #endif 1002 1003 /* 1004 * On EPT, we can't emulate NX, so we must switch EFER atomically. 1005 * On CPUs that support "load IA32_EFER", always switch EFER 1006 * atomically, since it's faster than switching it manually. 1007 */ 1008 if (cpu_has_load_ia32_efer() || 1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 1010 if (!(guest_efer & EFER_LMA)) 1011 guest_efer &= ~EFER_LME; 1012 if (guest_efer != host_efer) 1013 add_atomic_switch_msr(vmx, MSR_EFER, 1014 guest_efer, host_efer, false); 1015 else 1016 clear_atomic_switch_msr(vmx, MSR_EFER); 1017 return false; 1018 } else { 1019 clear_atomic_switch_msr(vmx, MSR_EFER); 1020 1021 guest_efer &= ~ignore_bits; 1022 guest_efer |= host_efer & ignore_bits; 1023 1024 vmx->guest_msrs[efer_offset].data = guest_efer; 1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1026 1027 return true; 1028 } 1029 } 1030 1031 #ifdef CONFIG_X86_32 1032 /* 1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1034 * VMCS rather than the segment table. KVM uses this helper to figure 1035 * out the current bases to poke them into the VMCS before entry. 1036 */ 1037 static unsigned long segment_base(u16 selector) 1038 { 1039 struct desc_struct *table; 1040 unsigned long v; 1041 1042 if (!(selector & ~SEGMENT_RPL_MASK)) 1043 return 0; 1044 1045 table = get_current_gdt_ro(); 1046 1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1048 u16 ldt_selector = kvm_read_ldt(); 1049 1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1051 return 0; 1052 1053 table = (struct desc_struct *)segment_base(ldt_selector); 1054 } 1055 v = get_desc_base(&table[selector >> 3]); 1056 return v; 1057 } 1058 #endif 1059 1060 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1061 { 1062 u32 i; 1063 1064 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1065 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1066 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1067 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1068 for (i = 0; i < addr_range; i++) { 1069 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1070 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1071 } 1072 } 1073 1074 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1075 { 1076 u32 i; 1077 1078 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1079 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1080 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1081 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1082 for (i = 0; i < addr_range; i++) { 1083 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1084 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1085 } 1086 } 1087 1088 static void pt_guest_enter(struct vcpu_vmx *vmx) 1089 { 1090 if (pt_mode == PT_MODE_SYSTEM) 1091 return; 1092 1093 /* 1094 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1095 * Save host state before VM entry. 1096 */ 1097 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1098 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1099 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1100 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1101 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1102 } 1103 } 1104 1105 static void pt_guest_exit(struct vcpu_vmx *vmx) 1106 { 1107 if (pt_mode == PT_MODE_SYSTEM) 1108 return; 1109 1110 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1111 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1112 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1113 } 1114 1115 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1116 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1117 } 1118 1119 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1120 unsigned long fs_base, unsigned long gs_base) 1121 { 1122 if (unlikely(fs_sel != host->fs_sel)) { 1123 if (!(fs_sel & 7)) 1124 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1125 else 1126 vmcs_write16(HOST_FS_SELECTOR, 0); 1127 host->fs_sel = fs_sel; 1128 } 1129 if (unlikely(gs_sel != host->gs_sel)) { 1130 if (!(gs_sel & 7)) 1131 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1132 else 1133 vmcs_write16(HOST_GS_SELECTOR, 0); 1134 host->gs_sel = gs_sel; 1135 } 1136 if (unlikely(fs_base != host->fs_base)) { 1137 vmcs_writel(HOST_FS_BASE, fs_base); 1138 host->fs_base = fs_base; 1139 } 1140 if (unlikely(gs_base != host->gs_base)) { 1141 vmcs_writel(HOST_GS_BASE, gs_base); 1142 host->gs_base = gs_base; 1143 } 1144 } 1145 1146 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1147 { 1148 struct vcpu_vmx *vmx = to_vmx(vcpu); 1149 struct vmcs_host_state *host_state; 1150 #ifdef CONFIG_X86_64 1151 int cpu = raw_smp_processor_id(); 1152 #endif 1153 unsigned long fs_base, gs_base; 1154 u16 fs_sel, gs_sel; 1155 int i; 1156 1157 vmx->req_immediate_exit = false; 1158 1159 /* 1160 * Note that guest MSRs to be saved/restored can also be changed 1161 * when guest state is loaded. This happens when guest transitions 1162 * to/from long-mode by setting MSR_EFER.LMA. 1163 */ 1164 if (!vmx->guest_msrs_ready) { 1165 vmx->guest_msrs_ready = true; 1166 for (i = 0; i < vmx->save_nmsrs; ++i) 1167 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1168 vmx->guest_msrs[i].data, 1169 vmx->guest_msrs[i].mask); 1170 1171 } 1172 if (vmx->guest_state_loaded) 1173 return; 1174 1175 host_state = &vmx->loaded_vmcs->host_state; 1176 1177 /* 1178 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1179 * allow segment selectors with cpl > 0 or ti == 1. 1180 */ 1181 host_state->ldt_sel = kvm_read_ldt(); 1182 1183 #ifdef CONFIG_X86_64 1184 savesegment(ds, host_state->ds_sel); 1185 savesegment(es, host_state->es_sel); 1186 1187 gs_base = cpu_kernelmode_gs_base(cpu); 1188 if (likely(is_64bit_mm(current->mm))) { 1189 save_fsgs_for_kvm(); 1190 fs_sel = current->thread.fsindex; 1191 gs_sel = current->thread.gsindex; 1192 fs_base = current->thread.fsbase; 1193 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1194 } else { 1195 savesegment(fs, fs_sel); 1196 savesegment(gs, gs_sel); 1197 fs_base = read_msr(MSR_FS_BASE); 1198 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1199 } 1200 1201 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1202 #else 1203 savesegment(fs, fs_sel); 1204 savesegment(gs, gs_sel); 1205 fs_base = segment_base(fs_sel); 1206 gs_base = segment_base(gs_sel); 1207 #endif 1208 1209 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1210 vmx->guest_state_loaded = true; 1211 } 1212 1213 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1214 { 1215 struct vmcs_host_state *host_state; 1216 1217 if (!vmx->guest_state_loaded) 1218 return; 1219 1220 host_state = &vmx->loaded_vmcs->host_state; 1221 1222 ++vmx->vcpu.stat.host_state_reload; 1223 1224 #ifdef CONFIG_X86_64 1225 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1226 #endif 1227 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1228 kvm_load_ldt(host_state->ldt_sel); 1229 #ifdef CONFIG_X86_64 1230 load_gs_index(host_state->gs_sel); 1231 #else 1232 loadsegment(gs, host_state->gs_sel); 1233 #endif 1234 } 1235 if (host_state->fs_sel & 7) 1236 loadsegment(fs, host_state->fs_sel); 1237 #ifdef CONFIG_X86_64 1238 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1239 loadsegment(ds, host_state->ds_sel); 1240 loadsegment(es, host_state->es_sel); 1241 } 1242 #endif 1243 invalidate_tss_limit(); 1244 #ifdef CONFIG_X86_64 1245 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1246 #endif 1247 load_fixmap_gdt(raw_smp_processor_id()); 1248 vmx->guest_state_loaded = false; 1249 vmx->guest_msrs_ready = false; 1250 } 1251 1252 #ifdef CONFIG_X86_64 1253 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1254 { 1255 preempt_disable(); 1256 if (vmx->guest_state_loaded) 1257 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1258 preempt_enable(); 1259 return vmx->msr_guest_kernel_gs_base; 1260 } 1261 1262 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1263 { 1264 preempt_disable(); 1265 if (vmx->guest_state_loaded) 1266 wrmsrl(MSR_KERNEL_GS_BASE, data); 1267 preempt_enable(); 1268 vmx->msr_guest_kernel_gs_base = data; 1269 } 1270 #endif 1271 1272 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1273 { 1274 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1275 struct pi_desc old, new; 1276 unsigned int dest; 1277 1278 /* 1279 * In case of hot-plug or hot-unplug, we may have to undo 1280 * vmx_vcpu_pi_put even if there is no assigned device. And we 1281 * always keep PI.NDST up to date for simplicity: it makes the 1282 * code easier, and CPU migration is not a fast path. 1283 */ 1284 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1285 return; 1286 1287 /* 1288 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1289 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1290 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1291 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1292 * correctly. 1293 */ 1294 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1295 pi_clear_sn(pi_desc); 1296 goto after_clear_sn; 1297 } 1298 1299 /* The full case. */ 1300 do { 1301 old.control = new.control = pi_desc->control; 1302 1303 dest = cpu_physical_id(cpu); 1304 1305 if (x2apic_enabled()) 1306 new.ndst = dest; 1307 else 1308 new.ndst = (dest << 8) & 0xFF00; 1309 1310 new.sn = 0; 1311 } while (cmpxchg64(&pi_desc->control, old.control, 1312 new.control) != old.control); 1313 1314 after_clear_sn: 1315 1316 /* 1317 * Clear SN before reading the bitmap. The VT-d firmware 1318 * writes the bitmap and reads SN atomically (5.2.3 in the 1319 * spec), so it doesn't really have a memory barrier that 1320 * pairs with this, but we cannot do that and we need one. 1321 */ 1322 smp_mb__after_atomic(); 1323 1324 if (!pi_is_pir_empty(pi_desc)) 1325 pi_set_on(pi_desc); 1326 } 1327 1328 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1329 { 1330 struct vcpu_vmx *vmx = to_vmx(vcpu); 1331 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1332 1333 if (!already_loaded) { 1334 loaded_vmcs_clear(vmx->loaded_vmcs); 1335 local_irq_disable(); 1336 crash_disable_local_vmclear(cpu); 1337 1338 /* 1339 * Read loaded_vmcs->cpu should be before fetching 1340 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1341 * See the comments in __loaded_vmcs_clear(). 1342 */ 1343 smp_rmb(); 1344 1345 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1346 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1347 crash_enable_local_vmclear(cpu); 1348 local_irq_enable(); 1349 } 1350 1351 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1352 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1353 vmcs_load(vmx->loaded_vmcs->vmcs); 1354 indirect_branch_prediction_barrier(); 1355 } 1356 1357 if (!already_loaded) { 1358 void *gdt = get_current_gdt_ro(); 1359 unsigned long sysenter_esp; 1360 1361 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1362 1363 /* 1364 * Linux uses per-cpu TSS and GDT, so set these when switching 1365 * processors. See 22.2.4. 1366 */ 1367 vmcs_writel(HOST_TR_BASE, 1368 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1369 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1370 1371 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1372 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1373 1374 vmx->loaded_vmcs->cpu = cpu; 1375 } 1376 1377 /* Setup TSC multiplier */ 1378 if (kvm_has_tsc_control && 1379 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1380 decache_tsc_multiplier(vmx); 1381 } 1382 1383 /* 1384 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1385 * vcpu mutex is already taken. 1386 */ 1387 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1388 { 1389 struct vcpu_vmx *vmx = to_vmx(vcpu); 1390 1391 vmx_vcpu_load_vmcs(vcpu, cpu); 1392 1393 vmx_vcpu_pi_load(vcpu, cpu); 1394 1395 vmx->host_pkru = read_pkru(); 1396 vmx->host_debugctlmsr = get_debugctlmsr(); 1397 } 1398 1399 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1400 { 1401 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1402 1403 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1404 !irq_remapping_cap(IRQ_POSTING_CAP) || 1405 !kvm_vcpu_apicv_active(vcpu)) 1406 return; 1407 1408 /* Set SN when the vCPU is preempted */ 1409 if (vcpu->preempted) 1410 pi_set_sn(pi_desc); 1411 } 1412 1413 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1414 { 1415 vmx_vcpu_pi_put(vcpu); 1416 1417 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1418 } 1419 1420 static bool emulation_required(struct kvm_vcpu *vcpu) 1421 { 1422 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1423 } 1424 1425 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); 1426 1427 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1428 { 1429 struct vcpu_vmx *vmx = to_vmx(vcpu); 1430 unsigned long rflags, save_rflags; 1431 1432 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1433 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1434 rflags = vmcs_readl(GUEST_RFLAGS); 1435 if (vmx->rmode.vm86_active) { 1436 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1437 save_rflags = vmx->rmode.save_rflags; 1438 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1439 } 1440 vmx->rflags = rflags; 1441 } 1442 return vmx->rflags; 1443 } 1444 1445 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1446 { 1447 struct vcpu_vmx *vmx = to_vmx(vcpu); 1448 unsigned long old_rflags; 1449 1450 if (enable_unrestricted_guest) { 1451 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1452 vmx->rflags = rflags; 1453 vmcs_writel(GUEST_RFLAGS, rflags); 1454 return; 1455 } 1456 1457 old_rflags = vmx_get_rflags(vcpu); 1458 vmx->rflags = rflags; 1459 if (vmx->rmode.vm86_active) { 1460 vmx->rmode.save_rflags = rflags; 1461 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1462 } 1463 vmcs_writel(GUEST_RFLAGS, rflags); 1464 1465 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1466 vmx->emulation_required = emulation_required(vcpu); 1467 } 1468 1469 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1470 { 1471 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1472 int ret = 0; 1473 1474 if (interruptibility & GUEST_INTR_STATE_STI) 1475 ret |= KVM_X86_SHADOW_INT_STI; 1476 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1477 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1478 1479 return ret; 1480 } 1481 1482 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1483 { 1484 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1485 u32 interruptibility = interruptibility_old; 1486 1487 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1488 1489 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1490 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1491 else if (mask & KVM_X86_SHADOW_INT_STI) 1492 interruptibility |= GUEST_INTR_STATE_STI; 1493 1494 if ((interruptibility != interruptibility_old)) 1495 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1496 } 1497 1498 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1499 { 1500 struct vcpu_vmx *vmx = to_vmx(vcpu); 1501 unsigned long value; 1502 1503 /* 1504 * Any MSR write that attempts to change bits marked reserved will 1505 * case a #GP fault. 1506 */ 1507 if (data & vmx->pt_desc.ctl_bitmask) 1508 return 1; 1509 1510 /* 1511 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1512 * result in a #GP unless the same write also clears TraceEn. 1513 */ 1514 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1515 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1516 return 1; 1517 1518 /* 1519 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1520 * and FabricEn would cause #GP, if 1521 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1522 */ 1523 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1524 !(data & RTIT_CTL_FABRIC_EN) && 1525 !intel_pt_validate_cap(vmx->pt_desc.caps, 1526 PT_CAP_single_range_output)) 1527 return 1; 1528 1529 /* 1530 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1531 * utilize encodings marked reserved will casue a #GP fault. 1532 */ 1533 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1534 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1535 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1536 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1537 return 1; 1538 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1539 PT_CAP_cycle_thresholds); 1540 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1541 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1542 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1543 return 1; 1544 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1545 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1546 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1547 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1548 return 1; 1549 1550 /* 1551 * If ADDRx_CFG is reserved or the encodings is >2 will 1552 * cause a #GP fault. 1553 */ 1554 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1555 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1556 return 1; 1557 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1558 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1559 return 1; 1560 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1561 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1562 return 1; 1563 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1564 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1565 return 1; 1566 1567 return 0; 1568 } 1569 1570 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1571 { 1572 unsigned long rip; 1573 1574 /* 1575 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1576 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1577 * set when EPT misconfig occurs. In practice, real hardware updates 1578 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1579 * (namely Hyper-V) don't set it due to it being undefined behavior, 1580 * i.e. we end up advancing IP with some random value. 1581 */ 1582 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1583 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1584 rip = kvm_rip_read(vcpu); 1585 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1586 kvm_rip_write(vcpu, rip); 1587 } else { 1588 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1589 return 0; 1590 } 1591 1592 /* skipping an emulated instruction also counts */ 1593 vmx_set_interrupt_shadow(vcpu, 0); 1594 1595 return 1; 1596 } 1597 1598 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1599 { 1600 /* 1601 * Ensure that we clear the HLT state in the VMCS. We don't need to 1602 * explicitly skip the instruction because if the HLT state is set, 1603 * then the instruction is already executing and RIP has already been 1604 * advanced. 1605 */ 1606 if (kvm_hlt_in_guest(vcpu->kvm) && 1607 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1608 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1609 } 1610 1611 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1612 { 1613 struct vcpu_vmx *vmx = to_vmx(vcpu); 1614 unsigned nr = vcpu->arch.exception.nr; 1615 bool has_error_code = vcpu->arch.exception.has_error_code; 1616 u32 error_code = vcpu->arch.exception.error_code; 1617 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1618 1619 kvm_deliver_exception_payload(vcpu); 1620 1621 if (has_error_code) { 1622 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1623 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1624 } 1625 1626 if (vmx->rmode.vm86_active) { 1627 int inc_eip = 0; 1628 if (kvm_exception_is_soft(nr)) 1629 inc_eip = vcpu->arch.event_exit_inst_len; 1630 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1631 return; 1632 } 1633 1634 WARN_ON_ONCE(vmx->emulation_required); 1635 1636 if (kvm_exception_is_soft(nr)) { 1637 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1638 vmx->vcpu.arch.event_exit_inst_len); 1639 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1640 } else 1641 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1642 1643 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1644 1645 vmx_clear_hlt(vcpu); 1646 } 1647 1648 static bool vmx_rdtscp_supported(void) 1649 { 1650 return cpu_has_vmx_rdtscp(); 1651 } 1652 1653 static bool vmx_invpcid_supported(void) 1654 { 1655 return cpu_has_vmx_invpcid(); 1656 } 1657 1658 /* 1659 * Swap MSR entry in host/guest MSR entry array. 1660 */ 1661 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1662 { 1663 struct shared_msr_entry tmp; 1664 1665 tmp = vmx->guest_msrs[to]; 1666 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1667 vmx->guest_msrs[from] = tmp; 1668 } 1669 1670 /* 1671 * Set up the vmcs to automatically save and restore system 1672 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1673 * mode, as fiddling with msrs is very expensive. 1674 */ 1675 static void setup_msrs(struct vcpu_vmx *vmx) 1676 { 1677 int save_nmsrs, index; 1678 1679 save_nmsrs = 0; 1680 #ifdef CONFIG_X86_64 1681 /* 1682 * The SYSCALL MSRs are only needed on long mode guests, and only 1683 * when EFER.SCE is set. 1684 */ 1685 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1686 index = __find_msr_index(vmx, MSR_STAR); 1687 if (index >= 0) 1688 move_msr_up(vmx, index, save_nmsrs++); 1689 index = __find_msr_index(vmx, MSR_LSTAR); 1690 if (index >= 0) 1691 move_msr_up(vmx, index, save_nmsrs++); 1692 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1693 if (index >= 0) 1694 move_msr_up(vmx, index, save_nmsrs++); 1695 } 1696 #endif 1697 index = __find_msr_index(vmx, MSR_EFER); 1698 if (index >= 0 && update_transition_efer(vmx, index)) 1699 move_msr_up(vmx, index, save_nmsrs++); 1700 index = __find_msr_index(vmx, MSR_TSC_AUX); 1701 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1702 move_msr_up(vmx, index, save_nmsrs++); 1703 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1704 if (index >= 0) 1705 move_msr_up(vmx, index, save_nmsrs++); 1706 1707 vmx->save_nmsrs = save_nmsrs; 1708 vmx->guest_msrs_ready = false; 1709 1710 if (cpu_has_vmx_msr_bitmap()) 1711 vmx_update_msr_bitmap(&vmx->vcpu); 1712 } 1713 1714 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1715 { 1716 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1717 1718 if (is_guest_mode(vcpu) && 1719 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) 1720 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1721 1722 return vcpu->arch.tsc_offset; 1723 } 1724 1725 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1726 { 1727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1728 u64 g_tsc_offset = 0; 1729 1730 /* 1731 * We're here if L1 chose not to trap WRMSR to TSC. According 1732 * to the spec, this should set L1's TSC; The offset that L1 1733 * set for L2 remains unchanged, and still needs to be added 1734 * to the newly set TSC to get L2's TSC. 1735 */ 1736 if (is_guest_mode(vcpu) && 1737 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) 1738 g_tsc_offset = vmcs12->tsc_offset; 1739 1740 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1741 vcpu->arch.tsc_offset - g_tsc_offset, 1742 offset); 1743 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1744 return offset + g_tsc_offset; 1745 } 1746 1747 /* 1748 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1749 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1750 * all guests if the "nested" module option is off, and can also be disabled 1751 * for a single guest by disabling its VMX cpuid bit. 1752 */ 1753 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1754 { 1755 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1756 } 1757 1758 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1759 uint64_t val) 1760 { 1761 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1762 1763 return !(val & ~valid_bits); 1764 } 1765 1766 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1767 { 1768 switch (msr->index) { 1769 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1770 if (!nested) 1771 return 1; 1772 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1773 default: 1774 return 1; 1775 } 1776 1777 return 0; 1778 } 1779 1780 /* 1781 * Reads an msr value (of 'msr_index') into 'pdata'. 1782 * Returns 0 on success, non-0 otherwise. 1783 * Assumes vcpu_load() was already called. 1784 */ 1785 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1786 { 1787 struct vcpu_vmx *vmx = to_vmx(vcpu); 1788 struct shared_msr_entry *msr; 1789 u32 index; 1790 1791 switch (msr_info->index) { 1792 #ifdef CONFIG_X86_64 1793 case MSR_FS_BASE: 1794 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1795 break; 1796 case MSR_GS_BASE: 1797 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1798 break; 1799 case MSR_KERNEL_GS_BASE: 1800 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1801 break; 1802 #endif 1803 case MSR_EFER: 1804 return kvm_get_msr_common(vcpu, msr_info); 1805 case MSR_IA32_TSX_CTRL: 1806 if (!msr_info->host_initiated && 1807 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1808 return 1; 1809 goto find_shared_msr; 1810 case MSR_IA32_UMWAIT_CONTROL: 1811 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1812 return 1; 1813 1814 msr_info->data = vmx->msr_ia32_umwait_control; 1815 break; 1816 case MSR_IA32_SPEC_CTRL: 1817 if (!msr_info->host_initiated && 1818 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1819 return 1; 1820 1821 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1822 break; 1823 case MSR_IA32_SYSENTER_CS: 1824 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1825 break; 1826 case MSR_IA32_SYSENTER_EIP: 1827 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1828 break; 1829 case MSR_IA32_SYSENTER_ESP: 1830 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1831 break; 1832 case MSR_IA32_BNDCFGS: 1833 if (!kvm_mpx_supported() || 1834 (!msr_info->host_initiated && 1835 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1836 return 1; 1837 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1838 break; 1839 case MSR_IA32_MCG_EXT_CTL: 1840 if (!msr_info->host_initiated && 1841 !(vmx->msr_ia32_feature_control & 1842 FEAT_CTL_LMCE_ENABLED)) 1843 return 1; 1844 msr_info->data = vcpu->arch.mcg_ext_ctl; 1845 break; 1846 case MSR_IA32_FEAT_CTL: 1847 msr_info->data = vmx->msr_ia32_feature_control; 1848 break; 1849 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1850 if (!nested_vmx_allowed(vcpu)) 1851 return 1; 1852 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1853 &msr_info->data); 1854 case MSR_IA32_RTIT_CTL: 1855 if (pt_mode != PT_MODE_HOST_GUEST) 1856 return 1; 1857 msr_info->data = vmx->pt_desc.guest.ctl; 1858 break; 1859 case MSR_IA32_RTIT_STATUS: 1860 if (pt_mode != PT_MODE_HOST_GUEST) 1861 return 1; 1862 msr_info->data = vmx->pt_desc.guest.status; 1863 break; 1864 case MSR_IA32_RTIT_CR3_MATCH: 1865 if ((pt_mode != PT_MODE_HOST_GUEST) || 1866 !intel_pt_validate_cap(vmx->pt_desc.caps, 1867 PT_CAP_cr3_filtering)) 1868 return 1; 1869 msr_info->data = vmx->pt_desc.guest.cr3_match; 1870 break; 1871 case MSR_IA32_RTIT_OUTPUT_BASE: 1872 if ((pt_mode != PT_MODE_HOST_GUEST) || 1873 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1874 PT_CAP_topa_output) && 1875 !intel_pt_validate_cap(vmx->pt_desc.caps, 1876 PT_CAP_single_range_output))) 1877 return 1; 1878 msr_info->data = vmx->pt_desc.guest.output_base; 1879 break; 1880 case MSR_IA32_RTIT_OUTPUT_MASK: 1881 if ((pt_mode != PT_MODE_HOST_GUEST) || 1882 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1883 PT_CAP_topa_output) && 1884 !intel_pt_validate_cap(vmx->pt_desc.caps, 1885 PT_CAP_single_range_output))) 1886 return 1; 1887 msr_info->data = vmx->pt_desc.guest.output_mask; 1888 break; 1889 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1890 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1891 if ((pt_mode != PT_MODE_HOST_GUEST) || 1892 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1893 PT_CAP_num_address_ranges))) 1894 return 1; 1895 if (index % 2) 1896 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1897 else 1898 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1899 break; 1900 case MSR_TSC_AUX: 1901 if (!msr_info->host_initiated && 1902 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1903 return 1; 1904 goto find_shared_msr; 1905 default: 1906 find_shared_msr: 1907 msr = find_msr_entry(vmx, msr_info->index); 1908 if (msr) { 1909 msr_info->data = msr->data; 1910 break; 1911 } 1912 return kvm_get_msr_common(vcpu, msr_info); 1913 } 1914 1915 return 0; 1916 } 1917 1918 /* 1919 * Writes msr value into into the appropriate "register". 1920 * Returns 0 on success, non-0 otherwise. 1921 * Assumes vcpu_load() was already called. 1922 */ 1923 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1924 { 1925 struct vcpu_vmx *vmx = to_vmx(vcpu); 1926 struct shared_msr_entry *msr; 1927 int ret = 0; 1928 u32 msr_index = msr_info->index; 1929 u64 data = msr_info->data; 1930 u32 index; 1931 1932 switch (msr_index) { 1933 case MSR_EFER: 1934 ret = kvm_set_msr_common(vcpu, msr_info); 1935 break; 1936 #ifdef CONFIG_X86_64 1937 case MSR_FS_BASE: 1938 vmx_segment_cache_clear(vmx); 1939 vmcs_writel(GUEST_FS_BASE, data); 1940 break; 1941 case MSR_GS_BASE: 1942 vmx_segment_cache_clear(vmx); 1943 vmcs_writel(GUEST_GS_BASE, data); 1944 break; 1945 case MSR_KERNEL_GS_BASE: 1946 vmx_write_guest_kernel_gs_base(vmx, data); 1947 break; 1948 #endif 1949 case MSR_IA32_SYSENTER_CS: 1950 if (is_guest_mode(vcpu)) 1951 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1952 vmcs_write32(GUEST_SYSENTER_CS, data); 1953 break; 1954 case MSR_IA32_SYSENTER_EIP: 1955 if (is_guest_mode(vcpu)) 1956 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1957 vmcs_writel(GUEST_SYSENTER_EIP, data); 1958 break; 1959 case MSR_IA32_SYSENTER_ESP: 1960 if (is_guest_mode(vcpu)) 1961 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1962 vmcs_writel(GUEST_SYSENTER_ESP, data); 1963 break; 1964 case MSR_IA32_DEBUGCTLMSR: 1965 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1966 VM_EXIT_SAVE_DEBUG_CONTROLS) 1967 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1968 1969 ret = kvm_set_msr_common(vcpu, msr_info); 1970 break; 1971 1972 case MSR_IA32_BNDCFGS: 1973 if (!kvm_mpx_supported() || 1974 (!msr_info->host_initiated && 1975 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1976 return 1; 1977 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1978 (data & MSR_IA32_BNDCFGS_RSVD)) 1979 return 1; 1980 vmcs_write64(GUEST_BNDCFGS, data); 1981 break; 1982 case MSR_IA32_UMWAIT_CONTROL: 1983 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1984 return 1; 1985 1986 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 1987 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 1988 return 1; 1989 1990 vmx->msr_ia32_umwait_control = data; 1991 break; 1992 case MSR_IA32_SPEC_CTRL: 1993 if (!msr_info->host_initiated && 1994 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1995 return 1; 1996 1997 /* The STIBP bit doesn't fault even if it's not advertised */ 1998 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) 1999 return 1; 2000 2001 vmx->spec_ctrl = data; 2002 2003 if (!data) 2004 break; 2005 2006 /* 2007 * For non-nested: 2008 * When it's written (to non-zero) for the first time, pass 2009 * it through. 2010 * 2011 * For nested: 2012 * The handling of the MSR bitmap for L2 guests is done in 2013 * nested_vmx_merge_msr_bitmap. We should not touch the 2014 * vmcs02.msr_bitmap here since it gets completely overwritten 2015 * in the merging. We update the vmcs01 here for L1 as well 2016 * since it will end up touching the MSR anyway now. 2017 */ 2018 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2019 MSR_IA32_SPEC_CTRL, 2020 MSR_TYPE_RW); 2021 break; 2022 case MSR_IA32_TSX_CTRL: 2023 if (!msr_info->host_initiated && 2024 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2025 return 1; 2026 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2027 return 1; 2028 goto find_shared_msr; 2029 case MSR_IA32_PRED_CMD: 2030 if (!msr_info->host_initiated && 2031 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2032 return 1; 2033 2034 if (data & ~PRED_CMD_IBPB) 2035 return 1; 2036 2037 if (!data) 2038 break; 2039 2040 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2041 2042 /* 2043 * For non-nested: 2044 * When it's written (to non-zero) for the first time, pass 2045 * it through. 2046 * 2047 * For nested: 2048 * The handling of the MSR bitmap for L2 guests is done in 2049 * nested_vmx_merge_msr_bitmap. We should not touch the 2050 * vmcs02.msr_bitmap here since it gets completely overwritten 2051 * in the merging. 2052 */ 2053 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2054 MSR_TYPE_W); 2055 break; 2056 case MSR_IA32_CR_PAT: 2057 if (!kvm_pat_valid(data)) 2058 return 1; 2059 2060 if (is_guest_mode(vcpu) && 2061 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2062 get_vmcs12(vcpu)->guest_ia32_pat = data; 2063 2064 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2065 vmcs_write64(GUEST_IA32_PAT, data); 2066 vcpu->arch.pat = data; 2067 break; 2068 } 2069 ret = kvm_set_msr_common(vcpu, msr_info); 2070 break; 2071 case MSR_IA32_TSC_ADJUST: 2072 ret = kvm_set_msr_common(vcpu, msr_info); 2073 break; 2074 case MSR_IA32_MCG_EXT_CTL: 2075 if ((!msr_info->host_initiated && 2076 !(to_vmx(vcpu)->msr_ia32_feature_control & 2077 FEAT_CTL_LMCE_ENABLED)) || 2078 (data & ~MCG_EXT_CTL_LMCE_EN)) 2079 return 1; 2080 vcpu->arch.mcg_ext_ctl = data; 2081 break; 2082 case MSR_IA32_FEAT_CTL: 2083 if (!vmx_feature_control_msr_valid(vcpu, data) || 2084 (to_vmx(vcpu)->msr_ia32_feature_control & 2085 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2086 return 1; 2087 vmx->msr_ia32_feature_control = data; 2088 if (msr_info->host_initiated && data == 0) 2089 vmx_leave_nested(vcpu); 2090 break; 2091 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2092 if (!msr_info->host_initiated) 2093 return 1; /* they are read-only */ 2094 if (!nested_vmx_allowed(vcpu)) 2095 return 1; 2096 return vmx_set_vmx_msr(vcpu, msr_index, data); 2097 case MSR_IA32_RTIT_CTL: 2098 if ((pt_mode != PT_MODE_HOST_GUEST) || 2099 vmx_rtit_ctl_check(vcpu, data) || 2100 vmx->nested.vmxon) 2101 return 1; 2102 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2103 vmx->pt_desc.guest.ctl = data; 2104 pt_update_intercept_for_msr(vmx); 2105 break; 2106 case MSR_IA32_RTIT_STATUS: 2107 if ((pt_mode != PT_MODE_HOST_GUEST) || 2108 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2109 (data & MSR_IA32_RTIT_STATUS_MASK)) 2110 return 1; 2111 vmx->pt_desc.guest.status = data; 2112 break; 2113 case MSR_IA32_RTIT_CR3_MATCH: 2114 if ((pt_mode != PT_MODE_HOST_GUEST) || 2115 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2116 !intel_pt_validate_cap(vmx->pt_desc.caps, 2117 PT_CAP_cr3_filtering)) 2118 return 1; 2119 vmx->pt_desc.guest.cr3_match = data; 2120 break; 2121 case MSR_IA32_RTIT_OUTPUT_BASE: 2122 if ((pt_mode != PT_MODE_HOST_GUEST) || 2123 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2124 (!intel_pt_validate_cap(vmx->pt_desc.caps, 2125 PT_CAP_topa_output) && 2126 !intel_pt_validate_cap(vmx->pt_desc.caps, 2127 PT_CAP_single_range_output)) || 2128 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)) 2129 return 1; 2130 vmx->pt_desc.guest.output_base = data; 2131 break; 2132 case MSR_IA32_RTIT_OUTPUT_MASK: 2133 if ((pt_mode != PT_MODE_HOST_GUEST) || 2134 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2135 (!intel_pt_validate_cap(vmx->pt_desc.caps, 2136 PT_CAP_topa_output) && 2137 !intel_pt_validate_cap(vmx->pt_desc.caps, 2138 PT_CAP_single_range_output))) 2139 return 1; 2140 vmx->pt_desc.guest.output_mask = data; 2141 break; 2142 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2143 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2144 if ((pt_mode != PT_MODE_HOST_GUEST) || 2145 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2146 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2147 PT_CAP_num_address_ranges))) 2148 return 1; 2149 if (index % 2) 2150 vmx->pt_desc.guest.addr_b[index / 2] = data; 2151 else 2152 vmx->pt_desc.guest.addr_a[index / 2] = data; 2153 break; 2154 case MSR_TSC_AUX: 2155 if (!msr_info->host_initiated && 2156 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2157 return 1; 2158 /* Check reserved bit, higher 32 bits should be zero */ 2159 if ((data >> 32) != 0) 2160 return 1; 2161 goto find_shared_msr; 2162 2163 default: 2164 find_shared_msr: 2165 msr = find_msr_entry(vmx, msr_index); 2166 if (msr) 2167 ret = vmx_set_guest_msr(vmx, msr, data); 2168 else 2169 ret = kvm_set_msr_common(vcpu, msr_info); 2170 } 2171 2172 return ret; 2173 } 2174 2175 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2176 { 2177 kvm_register_mark_available(vcpu, reg); 2178 2179 switch (reg) { 2180 case VCPU_REGS_RSP: 2181 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2182 break; 2183 case VCPU_REGS_RIP: 2184 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2185 break; 2186 case VCPU_EXREG_PDPTR: 2187 if (enable_ept) 2188 ept_save_pdptrs(vcpu); 2189 break; 2190 case VCPU_EXREG_CR3: 2191 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2192 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2193 break; 2194 default: 2195 WARN_ON_ONCE(1); 2196 break; 2197 } 2198 } 2199 2200 static __init int cpu_has_kvm_support(void) 2201 { 2202 return cpu_has_vmx(); 2203 } 2204 2205 static __init int vmx_disabled_by_bios(void) 2206 { 2207 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2208 !boot_cpu_has(X86_FEATURE_VMX); 2209 } 2210 2211 static void kvm_cpu_vmxon(u64 addr) 2212 { 2213 cr4_set_bits(X86_CR4_VMXE); 2214 intel_pt_handle_vmx(1); 2215 2216 asm volatile ("vmxon %0" : : "m"(addr)); 2217 } 2218 2219 static int hardware_enable(void) 2220 { 2221 int cpu = raw_smp_processor_id(); 2222 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2223 2224 if (cr4_read_shadow() & X86_CR4_VMXE) 2225 return -EBUSY; 2226 2227 /* 2228 * This can happen if we hot-added a CPU but failed to allocate 2229 * VP assist page for it. 2230 */ 2231 if (static_branch_unlikely(&enable_evmcs) && 2232 !hv_get_vp_assist_page(cpu)) 2233 return -EFAULT; 2234 2235 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2236 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2237 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2238 2239 /* 2240 * Now we can enable the vmclear operation in kdump 2241 * since the loaded_vmcss_on_cpu list on this cpu 2242 * has been initialized. 2243 * 2244 * Though the cpu is not in VMX operation now, there 2245 * is no problem to enable the vmclear operation 2246 * for the loaded_vmcss_on_cpu list is empty! 2247 */ 2248 crash_enable_local_vmclear(cpu); 2249 2250 kvm_cpu_vmxon(phys_addr); 2251 if (enable_ept) 2252 ept_sync_global(); 2253 2254 return 0; 2255 } 2256 2257 static void vmclear_local_loaded_vmcss(void) 2258 { 2259 int cpu = raw_smp_processor_id(); 2260 struct loaded_vmcs *v, *n; 2261 2262 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2263 loaded_vmcss_on_cpu_link) 2264 __loaded_vmcs_clear(v); 2265 } 2266 2267 2268 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2269 * tricks. 2270 */ 2271 static void kvm_cpu_vmxoff(void) 2272 { 2273 asm volatile (__ex("vmxoff")); 2274 2275 intel_pt_handle_vmx(0); 2276 cr4_clear_bits(X86_CR4_VMXE); 2277 } 2278 2279 static void hardware_disable(void) 2280 { 2281 vmclear_local_loaded_vmcss(); 2282 kvm_cpu_vmxoff(); 2283 } 2284 2285 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2286 u32 msr, u32 *result) 2287 { 2288 u32 vmx_msr_low, vmx_msr_high; 2289 u32 ctl = ctl_min | ctl_opt; 2290 2291 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2292 2293 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2294 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2295 2296 /* Ensure minimum (required) set of control bits are supported. */ 2297 if (ctl_min & ~ctl) 2298 return -EIO; 2299 2300 *result = ctl; 2301 return 0; 2302 } 2303 2304 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2305 struct vmx_capability *vmx_cap) 2306 { 2307 u32 vmx_msr_low, vmx_msr_high; 2308 u32 min, opt, min2, opt2; 2309 u32 _pin_based_exec_control = 0; 2310 u32 _cpu_based_exec_control = 0; 2311 u32 _cpu_based_2nd_exec_control = 0; 2312 u32 _vmexit_control = 0; 2313 u32 _vmentry_control = 0; 2314 2315 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2316 min = CPU_BASED_HLT_EXITING | 2317 #ifdef CONFIG_X86_64 2318 CPU_BASED_CR8_LOAD_EXITING | 2319 CPU_BASED_CR8_STORE_EXITING | 2320 #endif 2321 CPU_BASED_CR3_LOAD_EXITING | 2322 CPU_BASED_CR3_STORE_EXITING | 2323 CPU_BASED_UNCOND_IO_EXITING | 2324 CPU_BASED_MOV_DR_EXITING | 2325 CPU_BASED_USE_TSC_OFFSETING | 2326 CPU_BASED_MWAIT_EXITING | 2327 CPU_BASED_MONITOR_EXITING | 2328 CPU_BASED_INVLPG_EXITING | 2329 CPU_BASED_RDPMC_EXITING; 2330 2331 opt = CPU_BASED_TPR_SHADOW | 2332 CPU_BASED_USE_MSR_BITMAPS | 2333 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2334 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2335 &_cpu_based_exec_control) < 0) 2336 return -EIO; 2337 #ifdef CONFIG_X86_64 2338 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2339 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2340 ~CPU_BASED_CR8_STORE_EXITING; 2341 #endif 2342 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2343 min2 = 0; 2344 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2345 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2346 SECONDARY_EXEC_WBINVD_EXITING | 2347 SECONDARY_EXEC_ENABLE_VPID | 2348 SECONDARY_EXEC_ENABLE_EPT | 2349 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2350 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2351 SECONDARY_EXEC_DESC | 2352 SECONDARY_EXEC_RDTSCP | 2353 SECONDARY_EXEC_ENABLE_INVPCID | 2354 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2355 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2356 SECONDARY_EXEC_SHADOW_VMCS | 2357 SECONDARY_EXEC_XSAVES | 2358 SECONDARY_EXEC_RDSEED_EXITING | 2359 SECONDARY_EXEC_RDRAND_EXITING | 2360 SECONDARY_EXEC_ENABLE_PML | 2361 SECONDARY_EXEC_TSC_SCALING | 2362 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2363 SECONDARY_EXEC_PT_USE_GPA | 2364 SECONDARY_EXEC_PT_CONCEAL_VMX | 2365 SECONDARY_EXEC_ENABLE_VMFUNC | 2366 SECONDARY_EXEC_ENCLS_EXITING; 2367 if (adjust_vmx_controls(min2, opt2, 2368 MSR_IA32_VMX_PROCBASED_CTLS2, 2369 &_cpu_based_2nd_exec_control) < 0) 2370 return -EIO; 2371 } 2372 #ifndef CONFIG_X86_64 2373 if (!(_cpu_based_2nd_exec_control & 2374 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2375 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2376 #endif 2377 2378 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2379 _cpu_based_2nd_exec_control &= ~( 2380 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2381 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2382 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2383 2384 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2385 &vmx_cap->ept, &vmx_cap->vpid); 2386 2387 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2388 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2389 enabled */ 2390 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2391 CPU_BASED_CR3_STORE_EXITING | 2392 CPU_BASED_INVLPG_EXITING); 2393 } else if (vmx_cap->ept) { 2394 vmx_cap->ept = 0; 2395 pr_warn_once("EPT CAP should not exist if not support " 2396 "1-setting enable EPT VM-execution control\n"); 2397 } 2398 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2399 vmx_cap->vpid) { 2400 vmx_cap->vpid = 0; 2401 pr_warn_once("VPID CAP should not exist if not support " 2402 "1-setting enable VPID VM-execution control\n"); 2403 } 2404 2405 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2406 #ifdef CONFIG_X86_64 2407 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2408 #endif 2409 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2410 VM_EXIT_LOAD_IA32_PAT | 2411 VM_EXIT_LOAD_IA32_EFER | 2412 VM_EXIT_CLEAR_BNDCFGS | 2413 VM_EXIT_PT_CONCEAL_PIP | 2414 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2415 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2416 &_vmexit_control) < 0) 2417 return -EIO; 2418 2419 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2420 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2421 PIN_BASED_VMX_PREEMPTION_TIMER; 2422 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2423 &_pin_based_exec_control) < 0) 2424 return -EIO; 2425 2426 if (cpu_has_broken_vmx_preemption_timer()) 2427 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2428 if (!(_cpu_based_2nd_exec_control & 2429 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2430 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2431 2432 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2433 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2434 VM_ENTRY_LOAD_IA32_PAT | 2435 VM_ENTRY_LOAD_IA32_EFER | 2436 VM_ENTRY_LOAD_BNDCFGS | 2437 VM_ENTRY_PT_CONCEAL_PIP | 2438 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2439 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2440 &_vmentry_control) < 0) 2441 return -EIO; 2442 2443 /* 2444 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2445 * can't be used due to an errata where VM Exit may incorrectly clear 2446 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2447 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2448 */ 2449 if (boot_cpu_data.x86 == 0x6) { 2450 switch (boot_cpu_data.x86_model) { 2451 case 26: /* AAK155 */ 2452 case 30: /* AAP115 */ 2453 case 37: /* AAT100 */ 2454 case 44: /* BC86,AAY89,BD102 */ 2455 case 46: /* BA97 */ 2456 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2457 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2458 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2459 "does not work properly. Using workaround\n"); 2460 break; 2461 default: 2462 break; 2463 } 2464 } 2465 2466 2467 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2468 2469 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2470 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2471 return -EIO; 2472 2473 #ifdef CONFIG_X86_64 2474 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2475 if (vmx_msr_high & (1u<<16)) 2476 return -EIO; 2477 #endif 2478 2479 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2480 if (((vmx_msr_high >> 18) & 15) != 6) 2481 return -EIO; 2482 2483 vmcs_conf->size = vmx_msr_high & 0x1fff; 2484 vmcs_conf->order = get_order(vmcs_conf->size); 2485 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2486 2487 vmcs_conf->revision_id = vmx_msr_low; 2488 2489 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2490 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2491 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2492 vmcs_conf->vmexit_ctrl = _vmexit_control; 2493 vmcs_conf->vmentry_ctrl = _vmentry_control; 2494 2495 if (static_branch_unlikely(&enable_evmcs)) 2496 evmcs_sanitize_exec_ctrls(vmcs_conf); 2497 2498 return 0; 2499 } 2500 2501 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2502 { 2503 int node = cpu_to_node(cpu); 2504 struct page *pages; 2505 struct vmcs *vmcs; 2506 2507 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2508 if (!pages) 2509 return NULL; 2510 vmcs = page_address(pages); 2511 memset(vmcs, 0, vmcs_config.size); 2512 2513 /* KVM supports Enlightened VMCS v1 only */ 2514 if (static_branch_unlikely(&enable_evmcs)) 2515 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2516 else 2517 vmcs->hdr.revision_id = vmcs_config.revision_id; 2518 2519 if (shadow) 2520 vmcs->hdr.shadow_vmcs = 1; 2521 return vmcs; 2522 } 2523 2524 void free_vmcs(struct vmcs *vmcs) 2525 { 2526 free_pages((unsigned long)vmcs, vmcs_config.order); 2527 } 2528 2529 /* 2530 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2531 */ 2532 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2533 { 2534 if (!loaded_vmcs->vmcs) 2535 return; 2536 loaded_vmcs_clear(loaded_vmcs); 2537 free_vmcs(loaded_vmcs->vmcs); 2538 loaded_vmcs->vmcs = NULL; 2539 if (loaded_vmcs->msr_bitmap) 2540 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2541 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2542 } 2543 2544 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2545 { 2546 loaded_vmcs->vmcs = alloc_vmcs(false); 2547 if (!loaded_vmcs->vmcs) 2548 return -ENOMEM; 2549 2550 loaded_vmcs->shadow_vmcs = NULL; 2551 loaded_vmcs->hv_timer_soft_disabled = false; 2552 loaded_vmcs_init(loaded_vmcs); 2553 2554 if (cpu_has_vmx_msr_bitmap()) { 2555 loaded_vmcs->msr_bitmap = (unsigned long *) 2556 __get_free_page(GFP_KERNEL_ACCOUNT); 2557 if (!loaded_vmcs->msr_bitmap) 2558 goto out_vmcs; 2559 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2560 2561 if (IS_ENABLED(CONFIG_HYPERV) && 2562 static_branch_unlikely(&enable_evmcs) && 2563 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2564 struct hv_enlightened_vmcs *evmcs = 2565 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2566 2567 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2568 } 2569 } 2570 2571 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2572 memset(&loaded_vmcs->controls_shadow, 0, 2573 sizeof(struct vmcs_controls_shadow)); 2574 2575 return 0; 2576 2577 out_vmcs: 2578 free_loaded_vmcs(loaded_vmcs); 2579 return -ENOMEM; 2580 } 2581 2582 static void free_kvm_area(void) 2583 { 2584 int cpu; 2585 2586 for_each_possible_cpu(cpu) { 2587 free_vmcs(per_cpu(vmxarea, cpu)); 2588 per_cpu(vmxarea, cpu) = NULL; 2589 } 2590 } 2591 2592 static __init int alloc_kvm_area(void) 2593 { 2594 int cpu; 2595 2596 for_each_possible_cpu(cpu) { 2597 struct vmcs *vmcs; 2598 2599 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2600 if (!vmcs) { 2601 free_kvm_area(); 2602 return -ENOMEM; 2603 } 2604 2605 /* 2606 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2607 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2608 * revision_id reported by MSR_IA32_VMX_BASIC. 2609 * 2610 * However, even though not explicitly documented by 2611 * TLFS, VMXArea passed as VMXON argument should 2612 * still be marked with revision_id reported by 2613 * physical CPU. 2614 */ 2615 if (static_branch_unlikely(&enable_evmcs)) 2616 vmcs->hdr.revision_id = vmcs_config.revision_id; 2617 2618 per_cpu(vmxarea, cpu) = vmcs; 2619 } 2620 return 0; 2621 } 2622 2623 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2624 struct kvm_segment *save) 2625 { 2626 if (!emulate_invalid_guest_state) { 2627 /* 2628 * CS and SS RPL should be equal during guest entry according 2629 * to VMX spec, but in reality it is not always so. Since vcpu 2630 * is in the middle of the transition from real mode to 2631 * protected mode it is safe to assume that RPL 0 is a good 2632 * default value. 2633 */ 2634 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2635 save->selector &= ~SEGMENT_RPL_MASK; 2636 save->dpl = save->selector & SEGMENT_RPL_MASK; 2637 save->s = 1; 2638 } 2639 vmx_set_segment(vcpu, save, seg); 2640 } 2641 2642 static void enter_pmode(struct kvm_vcpu *vcpu) 2643 { 2644 unsigned long flags; 2645 struct vcpu_vmx *vmx = to_vmx(vcpu); 2646 2647 /* 2648 * Update real mode segment cache. It may be not up-to-date if sement 2649 * register was written while vcpu was in a guest mode. 2650 */ 2651 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2652 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2653 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2654 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2655 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2656 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2657 2658 vmx->rmode.vm86_active = 0; 2659 2660 vmx_segment_cache_clear(vmx); 2661 2662 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2663 2664 flags = vmcs_readl(GUEST_RFLAGS); 2665 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2666 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2667 vmcs_writel(GUEST_RFLAGS, flags); 2668 2669 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2670 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2671 2672 update_exception_bitmap(vcpu); 2673 2674 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2675 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2676 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2677 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2678 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2679 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2680 } 2681 2682 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2683 { 2684 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2685 struct kvm_segment var = *save; 2686 2687 var.dpl = 0x3; 2688 if (seg == VCPU_SREG_CS) 2689 var.type = 0x3; 2690 2691 if (!emulate_invalid_guest_state) { 2692 var.selector = var.base >> 4; 2693 var.base = var.base & 0xffff0; 2694 var.limit = 0xffff; 2695 var.g = 0; 2696 var.db = 0; 2697 var.present = 1; 2698 var.s = 1; 2699 var.l = 0; 2700 var.unusable = 0; 2701 var.type = 0x3; 2702 var.avl = 0; 2703 if (save->base & 0xf) 2704 printk_once(KERN_WARNING "kvm: segment base is not " 2705 "paragraph aligned when entering " 2706 "protected mode (seg=%d)", seg); 2707 } 2708 2709 vmcs_write16(sf->selector, var.selector); 2710 vmcs_writel(sf->base, var.base); 2711 vmcs_write32(sf->limit, var.limit); 2712 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2713 } 2714 2715 static void enter_rmode(struct kvm_vcpu *vcpu) 2716 { 2717 unsigned long flags; 2718 struct vcpu_vmx *vmx = to_vmx(vcpu); 2719 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2720 2721 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2722 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2723 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2724 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2725 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2726 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2727 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2728 2729 vmx->rmode.vm86_active = 1; 2730 2731 /* 2732 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2733 * vcpu. Warn the user that an update is overdue. 2734 */ 2735 if (!kvm_vmx->tss_addr) 2736 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2737 "called before entering vcpu\n"); 2738 2739 vmx_segment_cache_clear(vmx); 2740 2741 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2742 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2743 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2744 2745 flags = vmcs_readl(GUEST_RFLAGS); 2746 vmx->rmode.save_rflags = flags; 2747 2748 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2749 2750 vmcs_writel(GUEST_RFLAGS, flags); 2751 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2752 update_exception_bitmap(vcpu); 2753 2754 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2755 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2756 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2757 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2758 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2759 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2760 2761 kvm_mmu_reset_context(vcpu); 2762 } 2763 2764 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2765 { 2766 struct vcpu_vmx *vmx = to_vmx(vcpu); 2767 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2768 2769 if (!msr) 2770 return; 2771 2772 vcpu->arch.efer = efer; 2773 if (efer & EFER_LMA) { 2774 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2775 msr->data = efer; 2776 } else { 2777 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2778 2779 msr->data = efer & ~EFER_LME; 2780 } 2781 setup_msrs(vmx); 2782 } 2783 2784 #ifdef CONFIG_X86_64 2785 2786 static void enter_lmode(struct kvm_vcpu *vcpu) 2787 { 2788 u32 guest_tr_ar; 2789 2790 vmx_segment_cache_clear(to_vmx(vcpu)); 2791 2792 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2793 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2794 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2795 __func__); 2796 vmcs_write32(GUEST_TR_AR_BYTES, 2797 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2798 | VMX_AR_TYPE_BUSY_64_TSS); 2799 } 2800 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2801 } 2802 2803 static void exit_lmode(struct kvm_vcpu *vcpu) 2804 { 2805 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2806 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2807 } 2808 2809 #endif 2810 2811 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2812 { 2813 int vpid = to_vmx(vcpu)->vpid; 2814 2815 if (!vpid_sync_vcpu_addr(vpid, addr)) 2816 vpid_sync_context(vpid); 2817 2818 /* 2819 * If VPIDs are not supported or enabled, then the above is a no-op. 2820 * But we don't really need a TLB flush in that case anyway, because 2821 * each VM entry/exit includes an implicit flush when VPID is 0. 2822 */ 2823 } 2824 2825 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2826 { 2827 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2828 2829 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2830 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2831 } 2832 2833 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2834 { 2835 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2836 2837 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2838 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2839 } 2840 2841 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2842 { 2843 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2844 2845 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2846 return; 2847 2848 if (is_pae_paging(vcpu)) { 2849 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2850 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2851 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2852 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2853 } 2854 } 2855 2856 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2857 { 2858 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2859 2860 if (is_pae_paging(vcpu)) { 2861 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2862 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2863 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2864 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2865 } 2866 2867 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2868 } 2869 2870 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2871 unsigned long cr0, 2872 struct kvm_vcpu *vcpu) 2873 { 2874 struct vcpu_vmx *vmx = to_vmx(vcpu); 2875 2876 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2877 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2878 if (!(cr0 & X86_CR0_PG)) { 2879 /* From paging/starting to nonpaging */ 2880 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2881 CPU_BASED_CR3_STORE_EXITING); 2882 vcpu->arch.cr0 = cr0; 2883 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2884 } else if (!is_paging(vcpu)) { 2885 /* From nonpaging to paging */ 2886 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2887 CPU_BASED_CR3_STORE_EXITING); 2888 vcpu->arch.cr0 = cr0; 2889 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2890 } 2891 2892 if (!(cr0 & X86_CR0_WP)) 2893 *hw_cr0 &= ~X86_CR0_WP; 2894 } 2895 2896 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2897 { 2898 struct vcpu_vmx *vmx = to_vmx(vcpu); 2899 unsigned long hw_cr0; 2900 2901 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2902 if (enable_unrestricted_guest) 2903 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2904 else { 2905 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2906 2907 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2908 enter_pmode(vcpu); 2909 2910 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2911 enter_rmode(vcpu); 2912 } 2913 2914 #ifdef CONFIG_X86_64 2915 if (vcpu->arch.efer & EFER_LME) { 2916 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2917 enter_lmode(vcpu); 2918 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2919 exit_lmode(vcpu); 2920 } 2921 #endif 2922 2923 if (enable_ept && !enable_unrestricted_guest) 2924 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2925 2926 vmcs_writel(CR0_READ_SHADOW, cr0); 2927 vmcs_writel(GUEST_CR0, hw_cr0); 2928 vcpu->arch.cr0 = cr0; 2929 2930 /* depends on vcpu->arch.cr0 to be set to a new value */ 2931 vmx->emulation_required = emulation_required(vcpu); 2932 } 2933 2934 static int get_ept_level(struct kvm_vcpu *vcpu) 2935 { 2936 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2937 return 5; 2938 return 4; 2939 } 2940 2941 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2942 { 2943 u64 eptp = VMX_EPTP_MT_WB; 2944 2945 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2946 2947 if (enable_ept_ad_bits && 2948 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2949 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2950 eptp |= (root_hpa & PAGE_MASK); 2951 2952 return eptp; 2953 } 2954 2955 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 2956 { 2957 struct kvm *kvm = vcpu->kvm; 2958 bool update_guest_cr3 = true; 2959 unsigned long guest_cr3; 2960 u64 eptp; 2961 2962 guest_cr3 = cr3; 2963 if (enable_ept) { 2964 eptp = construct_eptp(vcpu, cr3); 2965 vmcs_write64(EPT_POINTER, eptp); 2966 2967 if (kvm_x86_ops->tlb_remote_flush) { 2968 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2969 to_vmx(vcpu)->ept_pointer = eptp; 2970 to_kvm_vmx(kvm)->ept_pointers_match 2971 = EPT_POINTERS_CHECK; 2972 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2973 } 2974 2975 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 2976 if (is_guest_mode(vcpu)) 2977 update_guest_cr3 = false; 2978 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 2979 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 2980 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 2981 guest_cr3 = vcpu->arch.cr3; 2982 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 2983 update_guest_cr3 = false; 2984 ept_load_pdptrs(vcpu); 2985 } 2986 2987 if (update_guest_cr3) 2988 vmcs_writel(GUEST_CR3, guest_cr3); 2989 } 2990 2991 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 2992 { 2993 struct vcpu_vmx *vmx = to_vmx(vcpu); 2994 /* 2995 * Pass through host's Machine Check Enable value to hw_cr4, which 2996 * is in force while we are in guest mode. Do not let guests control 2997 * this bit, even if host CR4.MCE == 0. 2998 */ 2999 unsigned long hw_cr4; 3000 3001 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3002 if (enable_unrestricted_guest) 3003 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3004 else if (vmx->rmode.vm86_active) 3005 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3006 else 3007 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3008 3009 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3010 if (cr4 & X86_CR4_UMIP) { 3011 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3012 hw_cr4 &= ~X86_CR4_UMIP; 3013 } else if (!is_guest_mode(vcpu) || 3014 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3015 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3016 } 3017 } 3018 3019 if (cr4 & X86_CR4_VMXE) { 3020 /* 3021 * To use VMXON (and later other VMX instructions), a guest 3022 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3023 * So basically the check on whether to allow nested VMX 3024 * is here. We operate under the default treatment of SMM, 3025 * so VMX cannot be enabled under SMM. 3026 */ 3027 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3028 return 1; 3029 } 3030 3031 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3032 return 1; 3033 3034 vcpu->arch.cr4 = cr4; 3035 3036 if (!enable_unrestricted_guest) { 3037 if (enable_ept) { 3038 if (!is_paging(vcpu)) { 3039 hw_cr4 &= ~X86_CR4_PAE; 3040 hw_cr4 |= X86_CR4_PSE; 3041 } else if (!(cr4 & X86_CR4_PAE)) { 3042 hw_cr4 &= ~X86_CR4_PAE; 3043 } 3044 } 3045 3046 /* 3047 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3048 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3049 * to be manually disabled when guest switches to non-paging 3050 * mode. 3051 * 3052 * If !enable_unrestricted_guest, the CPU is always running 3053 * with CR0.PG=1 and CR4 needs to be modified. 3054 * If enable_unrestricted_guest, the CPU automatically 3055 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3056 */ 3057 if (!is_paging(vcpu)) 3058 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3059 } 3060 3061 vmcs_writel(CR4_READ_SHADOW, cr4); 3062 vmcs_writel(GUEST_CR4, hw_cr4); 3063 return 0; 3064 } 3065 3066 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3067 { 3068 struct vcpu_vmx *vmx = to_vmx(vcpu); 3069 u32 ar; 3070 3071 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3072 *var = vmx->rmode.segs[seg]; 3073 if (seg == VCPU_SREG_TR 3074 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3075 return; 3076 var->base = vmx_read_guest_seg_base(vmx, seg); 3077 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3078 return; 3079 } 3080 var->base = vmx_read_guest_seg_base(vmx, seg); 3081 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3082 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3083 ar = vmx_read_guest_seg_ar(vmx, seg); 3084 var->unusable = (ar >> 16) & 1; 3085 var->type = ar & 15; 3086 var->s = (ar >> 4) & 1; 3087 var->dpl = (ar >> 5) & 3; 3088 /* 3089 * Some userspaces do not preserve unusable property. Since usable 3090 * segment has to be present according to VMX spec we can use present 3091 * property to amend userspace bug by making unusable segment always 3092 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3093 * segment as unusable. 3094 */ 3095 var->present = !var->unusable; 3096 var->avl = (ar >> 12) & 1; 3097 var->l = (ar >> 13) & 1; 3098 var->db = (ar >> 14) & 1; 3099 var->g = (ar >> 15) & 1; 3100 } 3101 3102 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3103 { 3104 struct kvm_segment s; 3105 3106 if (to_vmx(vcpu)->rmode.vm86_active) { 3107 vmx_get_segment(vcpu, &s, seg); 3108 return s.base; 3109 } 3110 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3111 } 3112 3113 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3114 { 3115 struct vcpu_vmx *vmx = to_vmx(vcpu); 3116 3117 if (unlikely(vmx->rmode.vm86_active)) 3118 return 0; 3119 else { 3120 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3121 return VMX_AR_DPL(ar); 3122 } 3123 } 3124 3125 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3126 { 3127 u32 ar; 3128 3129 if (var->unusable || !var->present) 3130 ar = 1 << 16; 3131 else { 3132 ar = var->type & 15; 3133 ar |= (var->s & 1) << 4; 3134 ar |= (var->dpl & 3) << 5; 3135 ar |= (var->present & 1) << 7; 3136 ar |= (var->avl & 1) << 12; 3137 ar |= (var->l & 1) << 13; 3138 ar |= (var->db & 1) << 14; 3139 ar |= (var->g & 1) << 15; 3140 } 3141 3142 return ar; 3143 } 3144 3145 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3146 { 3147 struct vcpu_vmx *vmx = to_vmx(vcpu); 3148 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3149 3150 vmx_segment_cache_clear(vmx); 3151 3152 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3153 vmx->rmode.segs[seg] = *var; 3154 if (seg == VCPU_SREG_TR) 3155 vmcs_write16(sf->selector, var->selector); 3156 else if (var->s) 3157 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3158 goto out; 3159 } 3160 3161 vmcs_writel(sf->base, var->base); 3162 vmcs_write32(sf->limit, var->limit); 3163 vmcs_write16(sf->selector, var->selector); 3164 3165 /* 3166 * Fix the "Accessed" bit in AR field of segment registers for older 3167 * qemu binaries. 3168 * IA32 arch specifies that at the time of processor reset the 3169 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3170 * is setting it to 0 in the userland code. This causes invalid guest 3171 * state vmexit when "unrestricted guest" mode is turned on. 3172 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3173 * tree. Newer qemu binaries with that qemu fix would not need this 3174 * kvm hack. 3175 */ 3176 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3177 var->type |= 0x1; /* Accessed */ 3178 3179 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3180 3181 out: 3182 vmx->emulation_required = emulation_required(vcpu); 3183 } 3184 3185 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3186 { 3187 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3188 3189 *db = (ar >> 14) & 1; 3190 *l = (ar >> 13) & 1; 3191 } 3192 3193 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3194 { 3195 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3196 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3197 } 3198 3199 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3200 { 3201 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3202 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3203 } 3204 3205 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3206 { 3207 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3208 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3209 } 3210 3211 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3212 { 3213 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3214 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3215 } 3216 3217 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3218 { 3219 struct kvm_segment var; 3220 u32 ar; 3221 3222 vmx_get_segment(vcpu, &var, seg); 3223 var.dpl = 0x3; 3224 if (seg == VCPU_SREG_CS) 3225 var.type = 0x3; 3226 ar = vmx_segment_access_rights(&var); 3227 3228 if (var.base != (var.selector << 4)) 3229 return false; 3230 if (var.limit != 0xffff) 3231 return false; 3232 if (ar != 0xf3) 3233 return false; 3234 3235 return true; 3236 } 3237 3238 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3239 { 3240 struct kvm_segment cs; 3241 unsigned int cs_rpl; 3242 3243 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3244 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3245 3246 if (cs.unusable) 3247 return false; 3248 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3249 return false; 3250 if (!cs.s) 3251 return false; 3252 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3253 if (cs.dpl > cs_rpl) 3254 return false; 3255 } else { 3256 if (cs.dpl != cs_rpl) 3257 return false; 3258 } 3259 if (!cs.present) 3260 return false; 3261 3262 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3263 return true; 3264 } 3265 3266 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3267 { 3268 struct kvm_segment ss; 3269 unsigned int ss_rpl; 3270 3271 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3272 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3273 3274 if (ss.unusable) 3275 return true; 3276 if (ss.type != 3 && ss.type != 7) 3277 return false; 3278 if (!ss.s) 3279 return false; 3280 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3281 return false; 3282 if (!ss.present) 3283 return false; 3284 3285 return true; 3286 } 3287 3288 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3289 { 3290 struct kvm_segment var; 3291 unsigned int rpl; 3292 3293 vmx_get_segment(vcpu, &var, seg); 3294 rpl = var.selector & SEGMENT_RPL_MASK; 3295 3296 if (var.unusable) 3297 return true; 3298 if (!var.s) 3299 return false; 3300 if (!var.present) 3301 return false; 3302 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3303 if (var.dpl < rpl) /* DPL < RPL */ 3304 return false; 3305 } 3306 3307 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3308 * rights flags 3309 */ 3310 return true; 3311 } 3312 3313 static bool tr_valid(struct kvm_vcpu *vcpu) 3314 { 3315 struct kvm_segment tr; 3316 3317 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3318 3319 if (tr.unusable) 3320 return false; 3321 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3322 return false; 3323 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3324 return false; 3325 if (!tr.present) 3326 return false; 3327 3328 return true; 3329 } 3330 3331 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3332 { 3333 struct kvm_segment ldtr; 3334 3335 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3336 3337 if (ldtr.unusable) 3338 return true; 3339 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3340 return false; 3341 if (ldtr.type != 2) 3342 return false; 3343 if (!ldtr.present) 3344 return false; 3345 3346 return true; 3347 } 3348 3349 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3350 { 3351 struct kvm_segment cs, ss; 3352 3353 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3354 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3355 3356 return ((cs.selector & SEGMENT_RPL_MASK) == 3357 (ss.selector & SEGMENT_RPL_MASK)); 3358 } 3359 3360 /* 3361 * Check if guest state is valid. Returns true if valid, false if 3362 * not. 3363 * We assume that registers are always usable 3364 */ 3365 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3366 { 3367 if (enable_unrestricted_guest) 3368 return true; 3369 3370 /* real mode guest state checks */ 3371 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3372 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3373 return false; 3374 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3375 return false; 3376 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3377 return false; 3378 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3379 return false; 3380 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3381 return false; 3382 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3383 return false; 3384 } else { 3385 /* protected mode guest state checks */ 3386 if (!cs_ss_rpl_check(vcpu)) 3387 return false; 3388 if (!code_segment_valid(vcpu)) 3389 return false; 3390 if (!stack_segment_valid(vcpu)) 3391 return false; 3392 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3393 return false; 3394 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3395 return false; 3396 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3397 return false; 3398 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3399 return false; 3400 if (!tr_valid(vcpu)) 3401 return false; 3402 if (!ldtr_valid(vcpu)) 3403 return false; 3404 } 3405 /* TODO: 3406 * - Add checks on RIP 3407 * - Add checks on RFLAGS 3408 */ 3409 3410 return true; 3411 } 3412 3413 static int init_rmode_tss(struct kvm *kvm) 3414 { 3415 gfn_t fn; 3416 u16 data = 0; 3417 int idx, r; 3418 3419 idx = srcu_read_lock(&kvm->srcu); 3420 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3421 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3422 if (r < 0) 3423 goto out; 3424 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3425 r = kvm_write_guest_page(kvm, fn++, &data, 3426 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3427 if (r < 0) 3428 goto out; 3429 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3430 if (r < 0) 3431 goto out; 3432 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3433 if (r < 0) 3434 goto out; 3435 data = ~0; 3436 r = kvm_write_guest_page(kvm, fn, &data, 3437 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3438 sizeof(u8)); 3439 out: 3440 srcu_read_unlock(&kvm->srcu, idx); 3441 return r; 3442 } 3443 3444 static int init_rmode_identity_map(struct kvm *kvm) 3445 { 3446 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3447 int i, idx, r = 0; 3448 kvm_pfn_t identity_map_pfn; 3449 u32 tmp; 3450 3451 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3452 mutex_lock(&kvm->slots_lock); 3453 3454 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3455 goto out2; 3456 3457 if (!kvm_vmx->ept_identity_map_addr) 3458 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3459 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3460 3461 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3462 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3463 if (r < 0) 3464 goto out2; 3465 3466 idx = srcu_read_lock(&kvm->srcu); 3467 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3468 if (r < 0) 3469 goto out; 3470 /* Set up identity-mapping pagetable for EPT in real mode */ 3471 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3472 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3473 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3474 r = kvm_write_guest_page(kvm, identity_map_pfn, 3475 &tmp, i * sizeof(tmp), sizeof(tmp)); 3476 if (r < 0) 3477 goto out; 3478 } 3479 kvm_vmx->ept_identity_pagetable_done = true; 3480 3481 out: 3482 srcu_read_unlock(&kvm->srcu, idx); 3483 3484 out2: 3485 mutex_unlock(&kvm->slots_lock); 3486 return r; 3487 } 3488 3489 static void seg_setup(int seg) 3490 { 3491 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3492 unsigned int ar; 3493 3494 vmcs_write16(sf->selector, 0); 3495 vmcs_writel(sf->base, 0); 3496 vmcs_write32(sf->limit, 0xffff); 3497 ar = 0x93; 3498 if (seg == VCPU_SREG_CS) 3499 ar |= 0x08; /* code segment */ 3500 3501 vmcs_write32(sf->ar_bytes, ar); 3502 } 3503 3504 static int alloc_apic_access_page(struct kvm *kvm) 3505 { 3506 struct page *page; 3507 int r = 0; 3508 3509 mutex_lock(&kvm->slots_lock); 3510 if (kvm->arch.apic_access_page_done) 3511 goto out; 3512 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3513 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3514 if (r) 3515 goto out; 3516 3517 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3518 if (is_error_page(page)) { 3519 r = -EFAULT; 3520 goto out; 3521 } 3522 3523 /* 3524 * Do not pin the page in memory, so that memory hot-unplug 3525 * is able to migrate it. 3526 */ 3527 put_page(page); 3528 kvm->arch.apic_access_page_done = true; 3529 out: 3530 mutex_unlock(&kvm->slots_lock); 3531 return r; 3532 } 3533 3534 int allocate_vpid(void) 3535 { 3536 int vpid; 3537 3538 if (!enable_vpid) 3539 return 0; 3540 spin_lock(&vmx_vpid_lock); 3541 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3542 if (vpid < VMX_NR_VPIDS) 3543 __set_bit(vpid, vmx_vpid_bitmap); 3544 else 3545 vpid = 0; 3546 spin_unlock(&vmx_vpid_lock); 3547 return vpid; 3548 } 3549 3550 void free_vpid(int vpid) 3551 { 3552 if (!enable_vpid || vpid == 0) 3553 return; 3554 spin_lock(&vmx_vpid_lock); 3555 __clear_bit(vpid, vmx_vpid_bitmap); 3556 spin_unlock(&vmx_vpid_lock); 3557 } 3558 3559 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3560 u32 msr, int type) 3561 { 3562 int f = sizeof(unsigned long); 3563 3564 if (!cpu_has_vmx_msr_bitmap()) 3565 return; 3566 3567 if (static_branch_unlikely(&enable_evmcs)) 3568 evmcs_touch_msr_bitmap(); 3569 3570 /* 3571 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3572 * have the write-low and read-high bitmap offsets the wrong way round. 3573 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3574 */ 3575 if (msr <= 0x1fff) { 3576 if (type & MSR_TYPE_R) 3577 /* read-low */ 3578 __clear_bit(msr, msr_bitmap + 0x000 / f); 3579 3580 if (type & MSR_TYPE_W) 3581 /* write-low */ 3582 __clear_bit(msr, msr_bitmap + 0x800 / f); 3583 3584 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3585 msr &= 0x1fff; 3586 if (type & MSR_TYPE_R) 3587 /* read-high */ 3588 __clear_bit(msr, msr_bitmap + 0x400 / f); 3589 3590 if (type & MSR_TYPE_W) 3591 /* write-high */ 3592 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3593 3594 } 3595 } 3596 3597 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3598 u32 msr, int type) 3599 { 3600 int f = sizeof(unsigned long); 3601 3602 if (!cpu_has_vmx_msr_bitmap()) 3603 return; 3604 3605 if (static_branch_unlikely(&enable_evmcs)) 3606 evmcs_touch_msr_bitmap(); 3607 3608 /* 3609 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3610 * have the write-low and read-high bitmap offsets the wrong way round. 3611 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3612 */ 3613 if (msr <= 0x1fff) { 3614 if (type & MSR_TYPE_R) 3615 /* read-low */ 3616 __set_bit(msr, msr_bitmap + 0x000 / f); 3617 3618 if (type & MSR_TYPE_W) 3619 /* write-low */ 3620 __set_bit(msr, msr_bitmap + 0x800 / f); 3621 3622 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3623 msr &= 0x1fff; 3624 if (type & MSR_TYPE_R) 3625 /* read-high */ 3626 __set_bit(msr, msr_bitmap + 0x400 / f); 3627 3628 if (type & MSR_TYPE_W) 3629 /* write-high */ 3630 __set_bit(msr, msr_bitmap + 0xc00 / f); 3631 3632 } 3633 } 3634 3635 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3636 u32 msr, int type, bool value) 3637 { 3638 if (value) 3639 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3640 else 3641 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3642 } 3643 3644 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3645 { 3646 u8 mode = 0; 3647 3648 if (cpu_has_secondary_exec_ctrls() && 3649 (secondary_exec_controls_get(to_vmx(vcpu)) & 3650 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3651 mode |= MSR_BITMAP_MODE_X2APIC; 3652 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3653 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3654 } 3655 3656 return mode; 3657 } 3658 3659 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3660 u8 mode) 3661 { 3662 int msr; 3663 3664 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3665 unsigned word = msr / BITS_PER_LONG; 3666 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3667 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3668 } 3669 3670 if (mode & MSR_BITMAP_MODE_X2APIC) { 3671 /* 3672 * TPR reads and writes can be virtualized even if virtual interrupt 3673 * delivery is not in use. 3674 */ 3675 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3676 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3677 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3678 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3679 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3680 } 3681 } 3682 } 3683 3684 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3685 { 3686 struct vcpu_vmx *vmx = to_vmx(vcpu); 3687 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3688 u8 mode = vmx_msr_bitmap_mode(vcpu); 3689 u8 changed = mode ^ vmx->msr_bitmap_mode; 3690 3691 if (!changed) 3692 return; 3693 3694 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3695 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3696 3697 vmx->msr_bitmap_mode = mode; 3698 } 3699 3700 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3701 { 3702 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3703 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3704 u32 i; 3705 3706 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3707 MSR_TYPE_RW, flag); 3708 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3709 MSR_TYPE_RW, flag); 3710 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3711 MSR_TYPE_RW, flag); 3712 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3713 MSR_TYPE_RW, flag); 3714 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3715 vmx_set_intercept_for_msr(msr_bitmap, 3716 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3717 vmx_set_intercept_for_msr(msr_bitmap, 3718 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3719 } 3720 } 3721 3722 static bool vmx_get_enable_apicv(struct kvm *kvm) 3723 { 3724 return enable_apicv; 3725 } 3726 3727 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3728 { 3729 struct vcpu_vmx *vmx = to_vmx(vcpu); 3730 void *vapic_page; 3731 u32 vppr; 3732 int rvi; 3733 3734 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3735 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3736 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3737 return false; 3738 3739 rvi = vmx_get_rvi(); 3740 3741 vapic_page = vmx->nested.virtual_apic_map.hva; 3742 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3743 3744 return ((rvi & 0xf0) > (vppr & 0xf0)); 3745 } 3746 3747 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3748 bool nested) 3749 { 3750 #ifdef CONFIG_SMP 3751 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3752 3753 if (vcpu->mode == IN_GUEST_MODE) { 3754 /* 3755 * The vector of interrupt to be delivered to vcpu had 3756 * been set in PIR before this function. 3757 * 3758 * Following cases will be reached in this block, and 3759 * we always send a notification event in all cases as 3760 * explained below. 3761 * 3762 * Case 1: vcpu keeps in non-root mode. Sending a 3763 * notification event posts the interrupt to vcpu. 3764 * 3765 * Case 2: vcpu exits to root mode and is still 3766 * runnable. PIR will be synced to vIRR before the 3767 * next vcpu entry. Sending a notification event in 3768 * this case has no effect, as vcpu is not in root 3769 * mode. 3770 * 3771 * Case 3: vcpu exits to root mode and is blocked. 3772 * vcpu_block() has already synced PIR to vIRR and 3773 * never blocks vcpu if vIRR is not cleared. Therefore, 3774 * a blocked vcpu here does not wait for any requested 3775 * interrupts in PIR, and sending a notification event 3776 * which has no effect is safe here. 3777 */ 3778 3779 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3780 return true; 3781 } 3782 #endif 3783 return false; 3784 } 3785 3786 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3787 int vector) 3788 { 3789 struct vcpu_vmx *vmx = to_vmx(vcpu); 3790 3791 if (is_guest_mode(vcpu) && 3792 vector == vmx->nested.posted_intr_nv) { 3793 /* 3794 * If a posted intr is not recognized by hardware, 3795 * we will accomplish it in the next vmentry. 3796 */ 3797 vmx->nested.pi_pending = true; 3798 kvm_make_request(KVM_REQ_EVENT, vcpu); 3799 /* the PIR and ON have been set by L1. */ 3800 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3801 kvm_vcpu_kick(vcpu); 3802 return 0; 3803 } 3804 return -1; 3805 } 3806 /* 3807 * Send interrupt to vcpu via posted interrupt way. 3808 * 1. If target vcpu is running(non-root mode), send posted interrupt 3809 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3810 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3811 * interrupt from PIR in next vmentry. 3812 */ 3813 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3814 { 3815 struct vcpu_vmx *vmx = to_vmx(vcpu); 3816 int r; 3817 3818 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3819 if (!r) 3820 return; 3821 3822 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3823 return; 3824 3825 /* If a previous notification has sent the IPI, nothing to do. */ 3826 if (pi_test_and_set_on(&vmx->pi_desc)) 3827 return; 3828 3829 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3830 kvm_vcpu_kick(vcpu); 3831 } 3832 3833 /* 3834 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3835 * will not change in the lifetime of the guest. 3836 * Note that host-state that does change is set elsewhere. E.g., host-state 3837 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3838 */ 3839 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3840 { 3841 u32 low32, high32; 3842 unsigned long tmpl; 3843 unsigned long cr0, cr3, cr4; 3844 3845 cr0 = read_cr0(); 3846 WARN_ON(cr0 & X86_CR0_TS); 3847 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3848 3849 /* 3850 * Save the most likely value for this task's CR3 in the VMCS. 3851 * We can't use __get_current_cr3_fast() because we're not atomic. 3852 */ 3853 cr3 = __read_cr3(); 3854 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3855 vmx->loaded_vmcs->host_state.cr3 = cr3; 3856 3857 /* Save the most likely value for this task's CR4 in the VMCS. */ 3858 cr4 = cr4_read_shadow(); 3859 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3860 vmx->loaded_vmcs->host_state.cr4 = cr4; 3861 3862 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3863 #ifdef CONFIG_X86_64 3864 /* 3865 * Load null selectors, so we can avoid reloading them in 3866 * vmx_prepare_switch_to_host(), in case userspace uses 3867 * the null selectors too (the expected case). 3868 */ 3869 vmcs_write16(HOST_DS_SELECTOR, 0); 3870 vmcs_write16(HOST_ES_SELECTOR, 0); 3871 #else 3872 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3873 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3874 #endif 3875 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3876 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3877 3878 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3879 3880 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3881 3882 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3883 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3884 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3885 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3886 3887 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3888 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3889 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3890 } 3891 3892 if (cpu_has_load_ia32_efer()) 3893 vmcs_write64(HOST_IA32_EFER, host_efer); 3894 } 3895 3896 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3897 { 3898 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3899 if (enable_ept) 3900 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3901 if (is_guest_mode(&vmx->vcpu)) 3902 vmx->vcpu.arch.cr4_guest_owned_bits &= 3903 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3904 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3905 } 3906 3907 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3908 { 3909 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3910 3911 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3912 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3913 3914 if (!enable_vnmi) 3915 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3916 3917 if (!enable_preemption_timer) 3918 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3919 3920 return pin_based_exec_ctrl; 3921 } 3922 3923 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3924 { 3925 struct vcpu_vmx *vmx = to_vmx(vcpu); 3926 3927 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3928 if (cpu_has_secondary_exec_ctrls()) { 3929 if (kvm_vcpu_apicv_active(vcpu)) 3930 secondary_exec_controls_setbit(vmx, 3931 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3932 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3933 else 3934 secondary_exec_controls_clearbit(vmx, 3935 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3936 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3937 } 3938 3939 if (cpu_has_vmx_msr_bitmap()) 3940 vmx_update_msr_bitmap(vcpu); 3941 } 3942 3943 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3944 { 3945 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3946 3947 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3948 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3949 3950 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3951 exec_control &= ~CPU_BASED_TPR_SHADOW; 3952 #ifdef CONFIG_X86_64 3953 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3954 CPU_BASED_CR8_LOAD_EXITING; 3955 #endif 3956 } 3957 if (!enable_ept) 3958 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3959 CPU_BASED_CR3_LOAD_EXITING | 3960 CPU_BASED_INVLPG_EXITING; 3961 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3962 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3963 CPU_BASED_MONITOR_EXITING); 3964 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3965 exec_control &= ~CPU_BASED_HLT_EXITING; 3966 return exec_control; 3967 } 3968 3969 3970 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 3971 { 3972 struct kvm_vcpu *vcpu = &vmx->vcpu; 3973 3974 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 3975 3976 if (pt_mode == PT_MODE_SYSTEM) 3977 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 3978 if (!cpu_need_virtualize_apic_accesses(vcpu)) 3979 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 3980 if (vmx->vpid == 0) 3981 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 3982 if (!enable_ept) { 3983 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 3984 enable_unrestricted_guest = 0; 3985 } 3986 if (!enable_unrestricted_guest) 3987 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 3988 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 3989 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 3990 if (!kvm_vcpu_apicv_active(vcpu)) 3991 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 3992 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3993 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 3994 3995 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 3996 * in vmx_set_cr4. */ 3997 exec_control &= ~SECONDARY_EXEC_DESC; 3998 3999 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4000 (handle_vmptrld). 4001 We can NOT enable shadow_vmcs here because we don't have yet 4002 a current VMCS12 4003 */ 4004 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4005 4006 if (!enable_pml) 4007 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4008 4009 if (vmx_xsaves_supported()) { 4010 /* Exposing XSAVES only when XSAVE is exposed */ 4011 bool xsaves_enabled = 4012 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4013 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4014 4015 vcpu->arch.xsaves_enabled = xsaves_enabled; 4016 4017 if (!xsaves_enabled) 4018 exec_control &= ~SECONDARY_EXEC_XSAVES; 4019 4020 if (nested) { 4021 if (xsaves_enabled) 4022 vmx->nested.msrs.secondary_ctls_high |= 4023 SECONDARY_EXEC_XSAVES; 4024 else 4025 vmx->nested.msrs.secondary_ctls_high &= 4026 ~SECONDARY_EXEC_XSAVES; 4027 } 4028 } 4029 4030 if (vmx_rdtscp_supported()) { 4031 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4032 if (!rdtscp_enabled) 4033 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4034 4035 if (nested) { 4036 if (rdtscp_enabled) 4037 vmx->nested.msrs.secondary_ctls_high |= 4038 SECONDARY_EXEC_RDTSCP; 4039 else 4040 vmx->nested.msrs.secondary_ctls_high &= 4041 ~SECONDARY_EXEC_RDTSCP; 4042 } 4043 } 4044 4045 if (vmx_invpcid_supported()) { 4046 /* Exposing INVPCID only when PCID is exposed */ 4047 bool invpcid_enabled = 4048 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4049 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4050 4051 if (!invpcid_enabled) { 4052 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4053 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4054 } 4055 4056 if (nested) { 4057 if (invpcid_enabled) 4058 vmx->nested.msrs.secondary_ctls_high |= 4059 SECONDARY_EXEC_ENABLE_INVPCID; 4060 else 4061 vmx->nested.msrs.secondary_ctls_high &= 4062 ~SECONDARY_EXEC_ENABLE_INVPCID; 4063 } 4064 } 4065 4066 if (vmx_rdrand_supported()) { 4067 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4068 if (rdrand_enabled) 4069 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4070 4071 if (nested) { 4072 if (rdrand_enabled) 4073 vmx->nested.msrs.secondary_ctls_high |= 4074 SECONDARY_EXEC_RDRAND_EXITING; 4075 else 4076 vmx->nested.msrs.secondary_ctls_high &= 4077 ~SECONDARY_EXEC_RDRAND_EXITING; 4078 } 4079 } 4080 4081 if (vmx_rdseed_supported()) { 4082 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4083 if (rdseed_enabled) 4084 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4085 4086 if (nested) { 4087 if (rdseed_enabled) 4088 vmx->nested.msrs.secondary_ctls_high |= 4089 SECONDARY_EXEC_RDSEED_EXITING; 4090 else 4091 vmx->nested.msrs.secondary_ctls_high &= 4092 ~SECONDARY_EXEC_RDSEED_EXITING; 4093 } 4094 } 4095 4096 if (vmx_waitpkg_supported()) { 4097 bool waitpkg_enabled = 4098 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4099 4100 if (!waitpkg_enabled) 4101 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4102 4103 if (nested) { 4104 if (waitpkg_enabled) 4105 vmx->nested.msrs.secondary_ctls_high |= 4106 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4107 else 4108 vmx->nested.msrs.secondary_ctls_high &= 4109 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4110 } 4111 } 4112 4113 vmx->secondary_exec_control = exec_control; 4114 } 4115 4116 static void ept_set_mmio_spte_mask(void) 4117 { 4118 /* 4119 * EPT Misconfigurations can be generated if the value of bits 2:0 4120 * of an EPT paging-structure entry is 110b (write/execute). 4121 */ 4122 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4123 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4124 } 4125 4126 #define VMX_XSS_EXIT_BITMAP 0 4127 4128 /* 4129 * Noting that the initialization of Guest-state Area of VMCS is in 4130 * vmx_vcpu_reset(). 4131 */ 4132 static void init_vmcs(struct vcpu_vmx *vmx) 4133 { 4134 if (nested) 4135 nested_vmx_set_vmcs_shadowing_bitmap(); 4136 4137 if (cpu_has_vmx_msr_bitmap()) 4138 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4139 4140 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4141 4142 /* Control */ 4143 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4144 4145 exec_controls_set(vmx, vmx_exec_control(vmx)); 4146 4147 if (cpu_has_secondary_exec_ctrls()) { 4148 vmx_compute_secondary_exec_control(vmx); 4149 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4150 } 4151 4152 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4153 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4154 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4155 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4156 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4157 4158 vmcs_write16(GUEST_INTR_STATUS, 0); 4159 4160 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4161 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4162 } 4163 4164 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4165 vmcs_write32(PLE_GAP, ple_gap); 4166 vmx->ple_window = ple_window; 4167 vmx->ple_window_dirty = true; 4168 } 4169 4170 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4171 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4172 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4173 4174 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4175 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4176 vmx_set_constant_host_state(vmx); 4177 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4178 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4179 4180 if (cpu_has_vmx_vmfunc()) 4181 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4182 4183 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4184 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4185 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4186 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4187 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4188 4189 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4190 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4191 4192 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4193 4194 /* 22.2.1, 20.8.1 */ 4195 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4196 4197 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4198 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4199 4200 set_cr4_guest_host_mask(vmx); 4201 4202 if (vmx->vpid != 0) 4203 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4204 4205 if (vmx_xsaves_supported()) 4206 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4207 4208 if (enable_pml) { 4209 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4210 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4211 } 4212 4213 if (cpu_has_vmx_encls_vmexit()) 4214 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4215 4216 if (pt_mode == PT_MODE_HOST_GUEST) { 4217 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4218 /* Bit[6~0] are forced to 1, writes are ignored. */ 4219 vmx->pt_desc.guest.output_mask = 0x7F; 4220 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4221 } 4222 } 4223 4224 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4225 { 4226 struct vcpu_vmx *vmx = to_vmx(vcpu); 4227 struct msr_data apic_base_msr; 4228 u64 cr0; 4229 4230 vmx->rmode.vm86_active = 0; 4231 vmx->spec_ctrl = 0; 4232 4233 vmx->msr_ia32_umwait_control = 0; 4234 4235 vcpu->arch.microcode_version = 0x100000000ULL; 4236 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4237 vmx->hv_deadline_tsc = -1; 4238 kvm_set_cr8(vcpu, 0); 4239 4240 if (!init_event) { 4241 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4242 MSR_IA32_APICBASE_ENABLE; 4243 if (kvm_vcpu_is_reset_bsp(vcpu)) 4244 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4245 apic_base_msr.host_initiated = true; 4246 kvm_set_apic_base(vcpu, &apic_base_msr); 4247 } 4248 4249 vmx_segment_cache_clear(vmx); 4250 4251 seg_setup(VCPU_SREG_CS); 4252 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4253 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4254 4255 seg_setup(VCPU_SREG_DS); 4256 seg_setup(VCPU_SREG_ES); 4257 seg_setup(VCPU_SREG_FS); 4258 seg_setup(VCPU_SREG_GS); 4259 seg_setup(VCPU_SREG_SS); 4260 4261 vmcs_write16(GUEST_TR_SELECTOR, 0); 4262 vmcs_writel(GUEST_TR_BASE, 0); 4263 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4264 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4265 4266 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4267 vmcs_writel(GUEST_LDTR_BASE, 0); 4268 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4269 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4270 4271 if (!init_event) { 4272 vmcs_write32(GUEST_SYSENTER_CS, 0); 4273 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4274 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4275 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4276 } 4277 4278 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4279 kvm_rip_write(vcpu, 0xfff0); 4280 4281 vmcs_writel(GUEST_GDTR_BASE, 0); 4282 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4283 4284 vmcs_writel(GUEST_IDTR_BASE, 0); 4285 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4286 4287 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4288 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4289 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4290 if (kvm_mpx_supported()) 4291 vmcs_write64(GUEST_BNDCFGS, 0); 4292 4293 setup_msrs(vmx); 4294 4295 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4296 4297 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4298 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4299 if (cpu_need_tpr_shadow(vcpu)) 4300 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4301 __pa(vcpu->arch.apic->regs)); 4302 vmcs_write32(TPR_THRESHOLD, 0); 4303 } 4304 4305 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4306 4307 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4308 vmx->vcpu.arch.cr0 = cr0; 4309 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4310 vmx_set_cr4(vcpu, 0); 4311 vmx_set_efer(vcpu, 0); 4312 4313 update_exception_bitmap(vcpu); 4314 4315 vpid_sync_context(vmx->vpid); 4316 if (init_event) 4317 vmx_clear_hlt(vcpu); 4318 } 4319 4320 static void enable_irq_window(struct kvm_vcpu *vcpu) 4321 { 4322 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING); 4323 } 4324 4325 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4326 { 4327 if (!enable_vnmi || 4328 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4329 enable_irq_window(vcpu); 4330 return; 4331 } 4332 4333 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING); 4334 } 4335 4336 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4337 { 4338 struct vcpu_vmx *vmx = to_vmx(vcpu); 4339 uint32_t intr; 4340 int irq = vcpu->arch.interrupt.nr; 4341 4342 trace_kvm_inj_virq(irq); 4343 4344 ++vcpu->stat.irq_injections; 4345 if (vmx->rmode.vm86_active) { 4346 int inc_eip = 0; 4347 if (vcpu->arch.interrupt.soft) 4348 inc_eip = vcpu->arch.event_exit_inst_len; 4349 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4350 return; 4351 } 4352 intr = irq | INTR_INFO_VALID_MASK; 4353 if (vcpu->arch.interrupt.soft) { 4354 intr |= INTR_TYPE_SOFT_INTR; 4355 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4356 vmx->vcpu.arch.event_exit_inst_len); 4357 } else 4358 intr |= INTR_TYPE_EXT_INTR; 4359 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4360 4361 vmx_clear_hlt(vcpu); 4362 } 4363 4364 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4365 { 4366 struct vcpu_vmx *vmx = to_vmx(vcpu); 4367 4368 if (!enable_vnmi) { 4369 /* 4370 * Tracking the NMI-blocked state in software is built upon 4371 * finding the next open IRQ window. This, in turn, depends on 4372 * well-behaving guests: They have to keep IRQs disabled at 4373 * least as long as the NMI handler runs. Otherwise we may 4374 * cause NMI nesting, maybe breaking the guest. But as this is 4375 * highly unlikely, we can live with the residual risk. 4376 */ 4377 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4378 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4379 } 4380 4381 ++vcpu->stat.nmi_injections; 4382 vmx->loaded_vmcs->nmi_known_unmasked = false; 4383 4384 if (vmx->rmode.vm86_active) { 4385 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4386 return; 4387 } 4388 4389 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4390 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4391 4392 vmx_clear_hlt(vcpu); 4393 } 4394 4395 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4396 { 4397 struct vcpu_vmx *vmx = to_vmx(vcpu); 4398 bool masked; 4399 4400 if (!enable_vnmi) 4401 return vmx->loaded_vmcs->soft_vnmi_blocked; 4402 if (vmx->loaded_vmcs->nmi_known_unmasked) 4403 return false; 4404 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4405 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4406 return masked; 4407 } 4408 4409 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4410 { 4411 struct vcpu_vmx *vmx = to_vmx(vcpu); 4412 4413 if (!enable_vnmi) { 4414 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4415 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4416 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4417 } 4418 } else { 4419 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4420 if (masked) 4421 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4422 GUEST_INTR_STATE_NMI); 4423 else 4424 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4425 GUEST_INTR_STATE_NMI); 4426 } 4427 } 4428 4429 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4430 { 4431 if (to_vmx(vcpu)->nested.nested_run_pending) 4432 return 0; 4433 4434 if (!enable_vnmi && 4435 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4436 return 0; 4437 4438 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4439 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4440 | GUEST_INTR_STATE_NMI)); 4441 } 4442 4443 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4444 { 4445 return (!to_vmx(vcpu)->nested.nested_run_pending && 4446 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4447 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4448 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4449 } 4450 4451 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4452 { 4453 int ret; 4454 4455 if (enable_unrestricted_guest) 4456 return 0; 4457 4458 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4459 PAGE_SIZE * 3); 4460 if (ret) 4461 return ret; 4462 to_kvm_vmx(kvm)->tss_addr = addr; 4463 return init_rmode_tss(kvm); 4464 } 4465 4466 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4467 { 4468 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4469 return 0; 4470 } 4471 4472 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4473 { 4474 switch (vec) { 4475 case BP_VECTOR: 4476 /* 4477 * Update instruction length as we may reinject the exception 4478 * from user space while in guest debugging mode. 4479 */ 4480 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4481 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4482 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4483 return false; 4484 /* fall through */ 4485 case DB_VECTOR: 4486 if (vcpu->guest_debug & 4487 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4488 return false; 4489 /* fall through */ 4490 case DE_VECTOR: 4491 case OF_VECTOR: 4492 case BR_VECTOR: 4493 case UD_VECTOR: 4494 case DF_VECTOR: 4495 case SS_VECTOR: 4496 case GP_VECTOR: 4497 case MF_VECTOR: 4498 return true; 4499 break; 4500 } 4501 return false; 4502 } 4503 4504 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4505 int vec, u32 err_code) 4506 { 4507 /* 4508 * Instruction with address size override prefix opcode 0x67 4509 * Cause the #SS fault with 0 error code in VM86 mode. 4510 */ 4511 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4512 if (kvm_emulate_instruction(vcpu, 0)) { 4513 if (vcpu->arch.halt_request) { 4514 vcpu->arch.halt_request = 0; 4515 return kvm_vcpu_halt(vcpu); 4516 } 4517 return 1; 4518 } 4519 return 0; 4520 } 4521 4522 /* 4523 * Forward all other exceptions that are valid in real mode. 4524 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4525 * the required debugging infrastructure rework. 4526 */ 4527 kvm_queue_exception(vcpu, vec); 4528 return 1; 4529 } 4530 4531 /* 4532 * Trigger machine check on the host. We assume all the MSRs are already set up 4533 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4534 * We pass a fake environment to the machine check handler because we want 4535 * the guest to be always treated like user space, no matter what context 4536 * it used internally. 4537 */ 4538 static void kvm_machine_check(void) 4539 { 4540 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4541 struct pt_regs regs = { 4542 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4543 .flags = X86_EFLAGS_IF, 4544 }; 4545 4546 do_machine_check(®s, 0); 4547 #endif 4548 } 4549 4550 static int handle_machine_check(struct kvm_vcpu *vcpu) 4551 { 4552 /* handled by vmx_vcpu_run() */ 4553 return 1; 4554 } 4555 4556 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4557 { 4558 struct vcpu_vmx *vmx = to_vmx(vcpu); 4559 struct kvm_run *kvm_run = vcpu->run; 4560 u32 intr_info, ex_no, error_code; 4561 unsigned long cr2, rip, dr6; 4562 u32 vect_info; 4563 4564 vect_info = vmx->idt_vectoring_info; 4565 intr_info = vmx->exit_intr_info; 4566 4567 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4568 return 1; /* handled by handle_exception_nmi_irqoff() */ 4569 4570 if (is_invalid_opcode(intr_info)) 4571 return handle_ud(vcpu); 4572 4573 error_code = 0; 4574 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4575 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4576 4577 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4578 WARN_ON_ONCE(!enable_vmware_backdoor); 4579 4580 /* 4581 * VMware backdoor emulation on #GP interception only handles 4582 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4583 * error code on #GP. 4584 */ 4585 if (error_code) { 4586 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4587 return 1; 4588 } 4589 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4590 } 4591 4592 /* 4593 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4594 * MMIO, it is better to report an internal error. 4595 * See the comments in vmx_handle_exit. 4596 */ 4597 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4598 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4599 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4600 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4601 vcpu->run->internal.ndata = 3; 4602 vcpu->run->internal.data[0] = vect_info; 4603 vcpu->run->internal.data[1] = intr_info; 4604 vcpu->run->internal.data[2] = error_code; 4605 return 0; 4606 } 4607 4608 if (is_page_fault(intr_info)) { 4609 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4610 /* EPT won't cause page fault directly */ 4611 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4612 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4613 } 4614 4615 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4616 4617 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4618 return handle_rmode_exception(vcpu, ex_no, error_code); 4619 4620 switch (ex_no) { 4621 case AC_VECTOR: 4622 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4623 return 1; 4624 case DB_VECTOR: 4625 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4626 if (!(vcpu->guest_debug & 4627 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4628 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4629 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4630 if (is_icebp(intr_info)) 4631 WARN_ON(!skip_emulated_instruction(vcpu)); 4632 4633 kvm_queue_exception(vcpu, DB_VECTOR); 4634 return 1; 4635 } 4636 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4637 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4638 /* fall through */ 4639 case BP_VECTOR: 4640 /* 4641 * Update instruction length as we may reinject #BP from 4642 * user space while in guest debugging mode. Reading it for 4643 * #DB as well causes no harm, it is not used in that case. 4644 */ 4645 vmx->vcpu.arch.event_exit_inst_len = 4646 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4647 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4648 rip = kvm_rip_read(vcpu); 4649 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4650 kvm_run->debug.arch.exception = ex_no; 4651 break; 4652 default: 4653 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4654 kvm_run->ex.exception = ex_no; 4655 kvm_run->ex.error_code = error_code; 4656 break; 4657 } 4658 return 0; 4659 } 4660 4661 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4662 { 4663 ++vcpu->stat.irq_exits; 4664 return 1; 4665 } 4666 4667 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4668 { 4669 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4670 vcpu->mmio_needed = 0; 4671 return 0; 4672 } 4673 4674 static int handle_io(struct kvm_vcpu *vcpu) 4675 { 4676 unsigned long exit_qualification; 4677 int size, in, string; 4678 unsigned port; 4679 4680 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4681 string = (exit_qualification & 16) != 0; 4682 4683 ++vcpu->stat.io_exits; 4684 4685 if (string) 4686 return kvm_emulate_instruction(vcpu, 0); 4687 4688 port = exit_qualification >> 16; 4689 size = (exit_qualification & 7) + 1; 4690 in = (exit_qualification & 8) != 0; 4691 4692 return kvm_fast_pio(vcpu, size, port, in); 4693 } 4694 4695 static void 4696 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4697 { 4698 /* 4699 * Patch in the VMCALL instruction: 4700 */ 4701 hypercall[0] = 0x0f; 4702 hypercall[1] = 0x01; 4703 hypercall[2] = 0xc1; 4704 } 4705 4706 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4707 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4708 { 4709 if (is_guest_mode(vcpu)) { 4710 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4711 unsigned long orig_val = val; 4712 4713 /* 4714 * We get here when L2 changed cr0 in a way that did not change 4715 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4716 * but did change L0 shadowed bits. So we first calculate the 4717 * effective cr0 value that L1 would like to write into the 4718 * hardware. It consists of the L2-owned bits from the new 4719 * value combined with the L1-owned bits from L1's guest_cr0. 4720 */ 4721 val = (val & ~vmcs12->cr0_guest_host_mask) | 4722 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4723 4724 if (!nested_guest_cr0_valid(vcpu, val)) 4725 return 1; 4726 4727 if (kvm_set_cr0(vcpu, val)) 4728 return 1; 4729 vmcs_writel(CR0_READ_SHADOW, orig_val); 4730 return 0; 4731 } else { 4732 if (to_vmx(vcpu)->nested.vmxon && 4733 !nested_host_cr0_valid(vcpu, val)) 4734 return 1; 4735 4736 return kvm_set_cr0(vcpu, val); 4737 } 4738 } 4739 4740 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4741 { 4742 if (is_guest_mode(vcpu)) { 4743 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4744 unsigned long orig_val = val; 4745 4746 /* analogously to handle_set_cr0 */ 4747 val = (val & ~vmcs12->cr4_guest_host_mask) | 4748 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4749 if (kvm_set_cr4(vcpu, val)) 4750 return 1; 4751 vmcs_writel(CR4_READ_SHADOW, orig_val); 4752 return 0; 4753 } else 4754 return kvm_set_cr4(vcpu, val); 4755 } 4756 4757 static int handle_desc(struct kvm_vcpu *vcpu) 4758 { 4759 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4760 return kvm_emulate_instruction(vcpu, 0); 4761 } 4762 4763 static int handle_cr(struct kvm_vcpu *vcpu) 4764 { 4765 unsigned long exit_qualification, val; 4766 int cr; 4767 int reg; 4768 int err; 4769 int ret; 4770 4771 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4772 cr = exit_qualification & 15; 4773 reg = (exit_qualification >> 8) & 15; 4774 switch ((exit_qualification >> 4) & 3) { 4775 case 0: /* mov to cr */ 4776 val = kvm_register_readl(vcpu, reg); 4777 trace_kvm_cr_write(cr, val); 4778 switch (cr) { 4779 case 0: 4780 err = handle_set_cr0(vcpu, val); 4781 return kvm_complete_insn_gp(vcpu, err); 4782 case 3: 4783 WARN_ON_ONCE(enable_unrestricted_guest); 4784 err = kvm_set_cr3(vcpu, val); 4785 return kvm_complete_insn_gp(vcpu, err); 4786 case 4: 4787 err = handle_set_cr4(vcpu, val); 4788 return kvm_complete_insn_gp(vcpu, err); 4789 case 8: { 4790 u8 cr8_prev = kvm_get_cr8(vcpu); 4791 u8 cr8 = (u8)val; 4792 err = kvm_set_cr8(vcpu, cr8); 4793 ret = kvm_complete_insn_gp(vcpu, err); 4794 if (lapic_in_kernel(vcpu)) 4795 return ret; 4796 if (cr8_prev <= cr8) 4797 return ret; 4798 /* 4799 * TODO: we might be squashing a 4800 * KVM_GUESTDBG_SINGLESTEP-triggered 4801 * KVM_EXIT_DEBUG here. 4802 */ 4803 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4804 return 0; 4805 } 4806 } 4807 break; 4808 case 2: /* clts */ 4809 WARN_ONCE(1, "Guest should always own CR0.TS"); 4810 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4811 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4812 return kvm_skip_emulated_instruction(vcpu); 4813 case 1: /*mov from cr*/ 4814 switch (cr) { 4815 case 3: 4816 WARN_ON_ONCE(enable_unrestricted_guest); 4817 val = kvm_read_cr3(vcpu); 4818 kvm_register_write(vcpu, reg, val); 4819 trace_kvm_cr_read(cr, val); 4820 return kvm_skip_emulated_instruction(vcpu); 4821 case 8: 4822 val = kvm_get_cr8(vcpu); 4823 kvm_register_write(vcpu, reg, val); 4824 trace_kvm_cr_read(cr, val); 4825 return kvm_skip_emulated_instruction(vcpu); 4826 } 4827 break; 4828 case 3: /* lmsw */ 4829 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4830 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4831 kvm_lmsw(vcpu, val); 4832 4833 return kvm_skip_emulated_instruction(vcpu); 4834 default: 4835 break; 4836 } 4837 vcpu->run->exit_reason = 0; 4838 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4839 (int)(exit_qualification >> 4) & 3, cr); 4840 return 0; 4841 } 4842 4843 static int handle_dr(struct kvm_vcpu *vcpu) 4844 { 4845 unsigned long exit_qualification; 4846 int dr, dr7, reg; 4847 4848 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4849 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4850 4851 /* First, if DR does not exist, trigger UD */ 4852 if (!kvm_require_dr(vcpu, dr)) 4853 return 1; 4854 4855 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4856 if (!kvm_require_cpl(vcpu, 0)) 4857 return 1; 4858 dr7 = vmcs_readl(GUEST_DR7); 4859 if (dr7 & DR7_GD) { 4860 /* 4861 * As the vm-exit takes precedence over the debug trap, we 4862 * need to emulate the latter, either for the host or the 4863 * guest debugging itself. 4864 */ 4865 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4866 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4867 vcpu->run->debug.arch.dr7 = dr7; 4868 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4869 vcpu->run->debug.arch.exception = DB_VECTOR; 4870 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4871 return 0; 4872 } else { 4873 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4874 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4875 kvm_queue_exception(vcpu, DB_VECTOR); 4876 return 1; 4877 } 4878 } 4879 4880 if (vcpu->guest_debug == 0) { 4881 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4882 4883 /* 4884 * No more DR vmexits; force a reload of the debug registers 4885 * and reenter on this instruction. The next vmexit will 4886 * retrieve the full state of the debug registers. 4887 */ 4888 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4889 return 1; 4890 } 4891 4892 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4893 if (exit_qualification & TYPE_MOV_FROM_DR) { 4894 unsigned long val; 4895 4896 if (kvm_get_dr(vcpu, dr, &val)) 4897 return 1; 4898 kvm_register_write(vcpu, reg, val); 4899 } else 4900 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4901 return 1; 4902 4903 return kvm_skip_emulated_instruction(vcpu); 4904 } 4905 4906 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4907 { 4908 return vcpu->arch.dr6; 4909 } 4910 4911 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4912 { 4913 } 4914 4915 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4916 { 4917 get_debugreg(vcpu->arch.db[0], 0); 4918 get_debugreg(vcpu->arch.db[1], 1); 4919 get_debugreg(vcpu->arch.db[2], 2); 4920 get_debugreg(vcpu->arch.db[3], 3); 4921 get_debugreg(vcpu->arch.dr6, 6); 4922 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4923 4924 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4925 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4926 } 4927 4928 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4929 { 4930 vmcs_writel(GUEST_DR7, val); 4931 } 4932 4933 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4934 { 4935 kvm_apic_update_ppr(vcpu); 4936 return 1; 4937 } 4938 4939 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4940 { 4941 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING); 4942 4943 kvm_make_request(KVM_REQ_EVENT, vcpu); 4944 4945 ++vcpu->stat.irq_window_exits; 4946 return 1; 4947 } 4948 4949 static int handle_vmcall(struct kvm_vcpu *vcpu) 4950 { 4951 return kvm_emulate_hypercall(vcpu); 4952 } 4953 4954 static int handle_invd(struct kvm_vcpu *vcpu) 4955 { 4956 return kvm_emulate_instruction(vcpu, 0); 4957 } 4958 4959 static int handle_invlpg(struct kvm_vcpu *vcpu) 4960 { 4961 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4962 4963 kvm_mmu_invlpg(vcpu, exit_qualification); 4964 return kvm_skip_emulated_instruction(vcpu); 4965 } 4966 4967 static int handle_rdpmc(struct kvm_vcpu *vcpu) 4968 { 4969 int err; 4970 4971 err = kvm_rdpmc(vcpu); 4972 return kvm_complete_insn_gp(vcpu, err); 4973 } 4974 4975 static int handle_wbinvd(struct kvm_vcpu *vcpu) 4976 { 4977 return kvm_emulate_wbinvd(vcpu); 4978 } 4979 4980 static int handle_xsetbv(struct kvm_vcpu *vcpu) 4981 { 4982 u64 new_bv = kvm_read_edx_eax(vcpu); 4983 u32 index = kvm_rcx_read(vcpu); 4984 4985 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 4986 return kvm_skip_emulated_instruction(vcpu); 4987 return 1; 4988 } 4989 4990 static int handle_apic_access(struct kvm_vcpu *vcpu) 4991 { 4992 if (likely(fasteoi)) { 4993 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4994 int access_type, offset; 4995 4996 access_type = exit_qualification & APIC_ACCESS_TYPE; 4997 offset = exit_qualification & APIC_ACCESS_OFFSET; 4998 /* 4999 * Sane guest uses MOV to write EOI, with written value 5000 * not cared. So make a short-circuit here by avoiding 5001 * heavy instruction emulation. 5002 */ 5003 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5004 (offset == APIC_EOI)) { 5005 kvm_lapic_set_eoi(vcpu); 5006 return kvm_skip_emulated_instruction(vcpu); 5007 } 5008 } 5009 return kvm_emulate_instruction(vcpu, 0); 5010 } 5011 5012 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5013 { 5014 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5015 int vector = exit_qualification & 0xff; 5016 5017 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5018 kvm_apic_set_eoi_accelerated(vcpu, vector); 5019 return 1; 5020 } 5021 5022 static int handle_apic_write(struct kvm_vcpu *vcpu) 5023 { 5024 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5025 u32 offset = exit_qualification & 0xfff; 5026 5027 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5028 kvm_apic_write_nodecode(vcpu, offset); 5029 return 1; 5030 } 5031 5032 static int handle_task_switch(struct kvm_vcpu *vcpu) 5033 { 5034 struct vcpu_vmx *vmx = to_vmx(vcpu); 5035 unsigned long exit_qualification; 5036 bool has_error_code = false; 5037 u32 error_code = 0; 5038 u16 tss_selector; 5039 int reason, type, idt_v, idt_index; 5040 5041 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5042 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5043 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5044 5045 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5046 5047 reason = (u32)exit_qualification >> 30; 5048 if (reason == TASK_SWITCH_GATE && idt_v) { 5049 switch (type) { 5050 case INTR_TYPE_NMI_INTR: 5051 vcpu->arch.nmi_injected = false; 5052 vmx_set_nmi_mask(vcpu, true); 5053 break; 5054 case INTR_TYPE_EXT_INTR: 5055 case INTR_TYPE_SOFT_INTR: 5056 kvm_clear_interrupt_queue(vcpu); 5057 break; 5058 case INTR_TYPE_HARD_EXCEPTION: 5059 if (vmx->idt_vectoring_info & 5060 VECTORING_INFO_DELIVER_CODE_MASK) { 5061 has_error_code = true; 5062 error_code = 5063 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5064 } 5065 /* fall through */ 5066 case INTR_TYPE_SOFT_EXCEPTION: 5067 kvm_clear_exception_queue(vcpu); 5068 break; 5069 default: 5070 break; 5071 } 5072 } 5073 tss_selector = exit_qualification; 5074 5075 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5076 type != INTR_TYPE_EXT_INTR && 5077 type != INTR_TYPE_NMI_INTR)) 5078 WARN_ON(!skip_emulated_instruction(vcpu)); 5079 5080 /* 5081 * TODO: What about debug traps on tss switch? 5082 * Are we supposed to inject them and update dr6? 5083 */ 5084 return kvm_task_switch(vcpu, tss_selector, 5085 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5086 reason, has_error_code, error_code); 5087 } 5088 5089 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5090 { 5091 unsigned long exit_qualification; 5092 gpa_t gpa; 5093 u64 error_code; 5094 5095 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5096 5097 /* 5098 * EPT violation happened while executing iret from NMI, 5099 * "blocked by NMI" bit has to be set before next VM entry. 5100 * There are errata that may cause this bit to not be set: 5101 * AAK134, BY25. 5102 */ 5103 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5104 enable_vnmi && 5105 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5106 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5107 5108 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5109 trace_kvm_page_fault(gpa, exit_qualification); 5110 5111 /* Is it a read fault? */ 5112 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5113 ? PFERR_USER_MASK : 0; 5114 /* Is it a write fault? */ 5115 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5116 ? PFERR_WRITE_MASK : 0; 5117 /* Is it a fetch fault? */ 5118 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5119 ? PFERR_FETCH_MASK : 0; 5120 /* ept page table entry is present? */ 5121 error_code |= (exit_qualification & 5122 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5123 EPT_VIOLATION_EXECUTABLE)) 5124 ? PFERR_PRESENT_MASK : 0; 5125 5126 error_code |= (exit_qualification & 0x100) != 0 ? 5127 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5128 5129 vcpu->arch.exit_qualification = exit_qualification; 5130 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5131 } 5132 5133 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5134 { 5135 gpa_t gpa; 5136 5137 /* 5138 * A nested guest cannot optimize MMIO vmexits, because we have an 5139 * nGPA here instead of the required GPA. 5140 */ 5141 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5142 if (!is_guest_mode(vcpu) && 5143 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5144 trace_kvm_fast_mmio(gpa); 5145 return kvm_skip_emulated_instruction(vcpu); 5146 } 5147 5148 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5149 } 5150 5151 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5152 { 5153 WARN_ON_ONCE(!enable_vnmi); 5154 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING); 5155 ++vcpu->stat.nmi_window_exits; 5156 kvm_make_request(KVM_REQ_EVENT, vcpu); 5157 5158 return 1; 5159 } 5160 5161 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5162 { 5163 struct vcpu_vmx *vmx = to_vmx(vcpu); 5164 bool intr_window_requested; 5165 unsigned count = 130; 5166 5167 /* 5168 * We should never reach the point where we are emulating L2 5169 * due to invalid guest state as that means we incorrectly 5170 * allowed a nested VMEntry with an invalid vmcs12. 5171 */ 5172 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5173 5174 intr_window_requested = exec_controls_get(vmx) & 5175 CPU_BASED_VIRTUAL_INTR_PENDING; 5176 5177 while (vmx->emulation_required && count-- != 0) { 5178 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5179 return handle_interrupt_window(&vmx->vcpu); 5180 5181 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5182 return 1; 5183 5184 if (!kvm_emulate_instruction(vcpu, 0)) 5185 return 0; 5186 5187 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5188 vcpu->arch.exception.pending) { 5189 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5190 vcpu->run->internal.suberror = 5191 KVM_INTERNAL_ERROR_EMULATION; 5192 vcpu->run->internal.ndata = 0; 5193 return 0; 5194 } 5195 5196 if (vcpu->arch.halt_request) { 5197 vcpu->arch.halt_request = 0; 5198 return kvm_vcpu_halt(vcpu); 5199 } 5200 5201 /* 5202 * Note, return 1 and not 0, vcpu_run() is responsible for 5203 * morphing the pending signal into the proper return code. 5204 */ 5205 if (signal_pending(current)) 5206 return 1; 5207 5208 if (need_resched()) 5209 schedule(); 5210 } 5211 5212 return 1; 5213 } 5214 5215 static void grow_ple_window(struct kvm_vcpu *vcpu) 5216 { 5217 struct vcpu_vmx *vmx = to_vmx(vcpu); 5218 unsigned int old = vmx->ple_window; 5219 5220 vmx->ple_window = __grow_ple_window(old, ple_window, 5221 ple_window_grow, 5222 ple_window_max); 5223 5224 if (vmx->ple_window != old) { 5225 vmx->ple_window_dirty = true; 5226 trace_kvm_ple_window_update(vcpu->vcpu_id, 5227 vmx->ple_window, old); 5228 } 5229 } 5230 5231 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5232 { 5233 struct vcpu_vmx *vmx = to_vmx(vcpu); 5234 unsigned int old = vmx->ple_window; 5235 5236 vmx->ple_window = __shrink_ple_window(old, ple_window, 5237 ple_window_shrink, 5238 ple_window); 5239 5240 if (vmx->ple_window != old) { 5241 vmx->ple_window_dirty = true; 5242 trace_kvm_ple_window_update(vcpu->vcpu_id, 5243 vmx->ple_window, old); 5244 } 5245 } 5246 5247 /* 5248 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5249 */ 5250 static void wakeup_handler(void) 5251 { 5252 struct kvm_vcpu *vcpu; 5253 int cpu = smp_processor_id(); 5254 5255 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5256 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5257 blocked_vcpu_list) { 5258 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5259 5260 if (pi_test_on(pi_desc) == 1) 5261 kvm_vcpu_kick(vcpu); 5262 } 5263 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5264 } 5265 5266 static void vmx_enable_tdp(void) 5267 { 5268 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5269 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5270 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5271 0ull, VMX_EPT_EXECUTABLE_MASK, 5272 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5273 VMX_EPT_RWX_MASK, 0ull); 5274 5275 ept_set_mmio_spte_mask(); 5276 kvm_enable_tdp(); 5277 } 5278 5279 /* 5280 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5281 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5282 */ 5283 static int handle_pause(struct kvm_vcpu *vcpu) 5284 { 5285 if (!kvm_pause_in_guest(vcpu->kvm)) 5286 grow_ple_window(vcpu); 5287 5288 /* 5289 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5290 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5291 * never set PAUSE_EXITING and just set PLE if supported, 5292 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5293 */ 5294 kvm_vcpu_on_spin(vcpu, true); 5295 return kvm_skip_emulated_instruction(vcpu); 5296 } 5297 5298 static int handle_nop(struct kvm_vcpu *vcpu) 5299 { 5300 return kvm_skip_emulated_instruction(vcpu); 5301 } 5302 5303 static int handle_mwait(struct kvm_vcpu *vcpu) 5304 { 5305 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5306 return handle_nop(vcpu); 5307 } 5308 5309 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5310 { 5311 kvm_queue_exception(vcpu, UD_VECTOR); 5312 return 1; 5313 } 5314 5315 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5316 { 5317 return 1; 5318 } 5319 5320 static int handle_monitor(struct kvm_vcpu *vcpu) 5321 { 5322 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5323 return handle_nop(vcpu); 5324 } 5325 5326 static int handle_invpcid(struct kvm_vcpu *vcpu) 5327 { 5328 u32 vmx_instruction_info; 5329 unsigned long type; 5330 bool pcid_enabled; 5331 gva_t gva; 5332 struct x86_exception e; 5333 unsigned i; 5334 unsigned long roots_to_free = 0; 5335 struct { 5336 u64 pcid; 5337 u64 gla; 5338 } operand; 5339 5340 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5341 kvm_queue_exception(vcpu, UD_VECTOR); 5342 return 1; 5343 } 5344 5345 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5346 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5347 5348 if (type > 3) { 5349 kvm_inject_gp(vcpu, 0); 5350 return 1; 5351 } 5352 5353 /* According to the Intel instruction reference, the memory operand 5354 * is read even if it isn't needed (e.g., for type==all) 5355 */ 5356 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5357 vmx_instruction_info, false, 5358 sizeof(operand), &gva)) 5359 return 1; 5360 5361 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5362 kvm_inject_page_fault(vcpu, &e); 5363 return 1; 5364 } 5365 5366 if (operand.pcid >> 12 != 0) { 5367 kvm_inject_gp(vcpu, 0); 5368 return 1; 5369 } 5370 5371 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5372 5373 switch (type) { 5374 case INVPCID_TYPE_INDIV_ADDR: 5375 if ((!pcid_enabled && (operand.pcid != 0)) || 5376 is_noncanonical_address(operand.gla, vcpu)) { 5377 kvm_inject_gp(vcpu, 0); 5378 return 1; 5379 } 5380 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5381 return kvm_skip_emulated_instruction(vcpu); 5382 5383 case INVPCID_TYPE_SINGLE_CTXT: 5384 if (!pcid_enabled && (operand.pcid != 0)) { 5385 kvm_inject_gp(vcpu, 0); 5386 return 1; 5387 } 5388 5389 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5390 kvm_mmu_sync_roots(vcpu); 5391 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5392 } 5393 5394 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5395 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5396 == operand.pcid) 5397 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5398 5399 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5400 /* 5401 * If neither the current cr3 nor any of the prev_roots use the 5402 * given PCID, then nothing needs to be done here because a 5403 * resync will happen anyway before switching to any other CR3. 5404 */ 5405 5406 return kvm_skip_emulated_instruction(vcpu); 5407 5408 case INVPCID_TYPE_ALL_NON_GLOBAL: 5409 /* 5410 * Currently, KVM doesn't mark global entries in the shadow 5411 * page tables, so a non-global flush just degenerates to a 5412 * global flush. If needed, we could optimize this later by 5413 * keeping track of global entries in shadow page tables. 5414 */ 5415 5416 /* fall-through */ 5417 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5418 kvm_mmu_unload(vcpu); 5419 return kvm_skip_emulated_instruction(vcpu); 5420 5421 default: 5422 BUG(); /* We have already checked above that type <= 3 */ 5423 } 5424 } 5425 5426 static int handle_pml_full(struct kvm_vcpu *vcpu) 5427 { 5428 unsigned long exit_qualification; 5429 5430 trace_kvm_pml_full(vcpu->vcpu_id); 5431 5432 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5433 5434 /* 5435 * PML buffer FULL happened while executing iret from NMI, 5436 * "blocked by NMI" bit has to be set before next VM entry. 5437 */ 5438 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5439 enable_vnmi && 5440 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5441 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5442 GUEST_INTR_STATE_NMI); 5443 5444 /* 5445 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5446 * here.., and there's no userspace involvement needed for PML. 5447 */ 5448 return 1; 5449 } 5450 5451 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5452 { 5453 struct vcpu_vmx *vmx = to_vmx(vcpu); 5454 5455 if (!vmx->req_immediate_exit && 5456 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5457 kvm_lapic_expired_hv_timer(vcpu); 5458 5459 return 1; 5460 } 5461 5462 /* 5463 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5464 * are overwritten by nested_vmx_setup() when nested=1. 5465 */ 5466 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5467 { 5468 kvm_queue_exception(vcpu, UD_VECTOR); 5469 return 1; 5470 } 5471 5472 static int handle_encls(struct kvm_vcpu *vcpu) 5473 { 5474 /* 5475 * SGX virtualization is not yet supported. There is no software 5476 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5477 * to prevent the guest from executing ENCLS. 5478 */ 5479 kvm_queue_exception(vcpu, UD_VECTOR); 5480 return 1; 5481 } 5482 5483 /* 5484 * The exit handlers return 1 if the exit was handled fully and guest execution 5485 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5486 * to be done to userspace and return 0. 5487 */ 5488 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5489 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5490 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5491 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5492 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5493 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5494 [EXIT_REASON_CR_ACCESS] = handle_cr, 5495 [EXIT_REASON_DR_ACCESS] = handle_dr, 5496 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5497 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5498 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5499 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, 5500 [EXIT_REASON_HLT] = kvm_emulate_halt, 5501 [EXIT_REASON_INVD] = handle_invd, 5502 [EXIT_REASON_INVLPG] = handle_invlpg, 5503 [EXIT_REASON_RDPMC] = handle_rdpmc, 5504 [EXIT_REASON_VMCALL] = handle_vmcall, 5505 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5506 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5507 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5508 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5509 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5510 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5511 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5512 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5513 [EXIT_REASON_VMON] = handle_vmx_instruction, 5514 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5515 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5516 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5517 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5518 [EXIT_REASON_WBINVD] = handle_wbinvd, 5519 [EXIT_REASON_XSETBV] = handle_xsetbv, 5520 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5521 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5522 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5523 [EXIT_REASON_LDTR_TR] = handle_desc, 5524 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5525 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5526 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5527 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5528 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5529 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5530 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5531 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5532 [EXIT_REASON_RDRAND] = handle_invalid_op, 5533 [EXIT_REASON_RDSEED] = handle_invalid_op, 5534 [EXIT_REASON_PML_FULL] = handle_pml_full, 5535 [EXIT_REASON_INVPCID] = handle_invpcid, 5536 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5537 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5538 [EXIT_REASON_ENCLS] = handle_encls, 5539 }; 5540 5541 static const int kvm_vmx_max_exit_handlers = 5542 ARRAY_SIZE(kvm_vmx_exit_handlers); 5543 5544 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5545 { 5546 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5547 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5548 } 5549 5550 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5551 { 5552 if (vmx->pml_pg) { 5553 __free_page(vmx->pml_pg); 5554 vmx->pml_pg = NULL; 5555 } 5556 } 5557 5558 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5559 { 5560 struct vcpu_vmx *vmx = to_vmx(vcpu); 5561 u64 *pml_buf; 5562 u16 pml_idx; 5563 5564 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5565 5566 /* Do nothing if PML buffer is empty */ 5567 if (pml_idx == (PML_ENTITY_NUM - 1)) 5568 return; 5569 5570 /* PML index always points to next available PML buffer entity */ 5571 if (pml_idx >= PML_ENTITY_NUM) 5572 pml_idx = 0; 5573 else 5574 pml_idx++; 5575 5576 pml_buf = page_address(vmx->pml_pg); 5577 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5578 u64 gpa; 5579 5580 gpa = pml_buf[pml_idx]; 5581 WARN_ON(gpa & (PAGE_SIZE - 1)); 5582 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5583 } 5584 5585 /* reset PML index */ 5586 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5587 } 5588 5589 /* 5590 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5591 * Called before reporting dirty_bitmap to userspace. 5592 */ 5593 static void kvm_flush_pml_buffers(struct kvm *kvm) 5594 { 5595 int i; 5596 struct kvm_vcpu *vcpu; 5597 /* 5598 * We only need to kick vcpu out of guest mode here, as PML buffer 5599 * is flushed at beginning of all VMEXITs, and it's obvious that only 5600 * vcpus running in guest are possible to have unflushed GPAs in PML 5601 * buffer. 5602 */ 5603 kvm_for_each_vcpu(i, vcpu, kvm) 5604 kvm_vcpu_kick(vcpu); 5605 } 5606 5607 static void vmx_dump_sel(char *name, uint32_t sel) 5608 { 5609 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5610 name, vmcs_read16(sel), 5611 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5612 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5613 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5614 } 5615 5616 static void vmx_dump_dtsel(char *name, uint32_t limit) 5617 { 5618 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5619 name, vmcs_read32(limit), 5620 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5621 } 5622 5623 void dump_vmcs(void) 5624 { 5625 u32 vmentry_ctl, vmexit_ctl; 5626 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5627 unsigned long cr4; 5628 u64 efer; 5629 int i, n; 5630 5631 if (!dump_invalid_vmcs) { 5632 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5633 return; 5634 } 5635 5636 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5637 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5638 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5639 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5640 cr4 = vmcs_readl(GUEST_CR4); 5641 efer = vmcs_read64(GUEST_IA32_EFER); 5642 secondary_exec_control = 0; 5643 if (cpu_has_secondary_exec_ctrls()) 5644 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5645 5646 pr_err("*** Guest State ***\n"); 5647 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5648 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5649 vmcs_readl(CR0_GUEST_HOST_MASK)); 5650 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5651 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5652 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5653 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5654 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5655 { 5656 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5657 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5658 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5659 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5660 } 5661 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5662 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5663 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5664 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5665 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5666 vmcs_readl(GUEST_SYSENTER_ESP), 5667 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5668 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5669 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5670 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5671 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5672 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5673 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5674 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5675 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5676 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5677 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5678 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5679 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5680 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5681 efer, vmcs_read64(GUEST_IA32_PAT)); 5682 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5683 vmcs_read64(GUEST_IA32_DEBUGCTL), 5684 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5685 if (cpu_has_load_perf_global_ctrl() && 5686 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5687 pr_err("PerfGlobCtl = 0x%016llx\n", 5688 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5689 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5690 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5691 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5692 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5693 vmcs_read32(GUEST_ACTIVITY_STATE)); 5694 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5695 pr_err("InterruptStatus = %04x\n", 5696 vmcs_read16(GUEST_INTR_STATUS)); 5697 5698 pr_err("*** Host State ***\n"); 5699 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5700 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5701 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5702 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5703 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5704 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5705 vmcs_read16(HOST_TR_SELECTOR)); 5706 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5707 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5708 vmcs_readl(HOST_TR_BASE)); 5709 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5710 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5711 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5712 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5713 vmcs_readl(HOST_CR4)); 5714 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5715 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5716 vmcs_read32(HOST_IA32_SYSENTER_CS), 5717 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5718 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5719 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5720 vmcs_read64(HOST_IA32_EFER), 5721 vmcs_read64(HOST_IA32_PAT)); 5722 if (cpu_has_load_perf_global_ctrl() && 5723 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5724 pr_err("PerfGlobCtl = 0x%016llx\n", 5725 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5726 5727 pr_err("*** Control State ***\n"); 5728 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5729 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5730 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5731 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5732 vmcs_read32(EXCEPTION_BITMAP), 5733 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5734 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5735 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5736 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5737 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5738 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5739 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5740 vmcs_read32(VM_EXIT_INTR_INFO), 5741 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5742 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5743 pr_err(" reason=%08x qualification=%016lx\n", 5744 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5745 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5746 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5747 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5748 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5749 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5750 pr_err("TSC Multiplier = 0x%016llx\n", 5751 vmcs_read64(TSC_MULTIPLIER)); 5752 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5753 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5754 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5755 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5756 } 5757 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5758 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5759 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5760 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5761 } 5762 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5763 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5764 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5765 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5766 n = vmcs_read32(CR3_TARGET_COUNT); 5767 for (i = 0; i + 1 < n; i += 4) 5768 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5769 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5770 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5771 if (i < n) 5772 pr_err("CR3 target%u=%016lx\n", 5773 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5774 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5775 pr_err("PLE Gap=%08x Window=%08x\n", 5776 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5777 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5778 pr_err("Virtual processor ID = 0x%04x\n", 5779 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5780 } 5781 5782 /* 5783 * The guest has exited. See if we can fix it or if we need userspace 5784 * assistance. 5785 */ 5786 static int vmx_handle_exit(struct kvm_vcpu *vcpu) 5787 { 5788 struct vcpu_vmx *vmx = to_vmx(vcpu); 5789 u32 exit_reason = vmx->exit_reason; 5790 u32 vectoring_info = vmx->idt_vectoring_info; 5791 5792 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5793 5794 /* 5795 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5796 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5797 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5798 * mode as if vcpus is in root mode, the PML buffer must has been 5799 * flushed already. 5800 */ 5801 if (enable_pml) 5802 vmx_flush_pml_buffer(vcpu); 5803 5804 /* If guest state is invalid, start emulating */ 5805 if (vmx->emulation_required) 5806 return handle_invalid_guest_state(vcpu); 5807 5808 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5809 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5810 5811 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5812 dump_vmcs(); 5813 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5814 vcpu->run->fail_entry.hardware_entry_failure_reason 5815 = exit_reason; 5816 return 0; 5817 } 5818 5819 if (unlikely(vmx->fail)) { 5820 dump_vmcs(); 5821 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5822 vcpu->run->fail_entry.hardware_entry_failure_reason 5823 = vmcs_read32(VM_INSTRUCTION_ERROR); 5824 return 0; 5825 } 5826 5827 /* 5828 * Note: 5829 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5830 * delivery event since it indicates guest is accessing MMIO. 5831 * The vm-exit can be triggered again after return to guest that 5832 * will cause infinite loop. 5833 */ 5834 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5835 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5836 exit_reason != EXIT_REASON_EPT_VIOLATION && 5837 exit_reason != EXIT_REASON_PML_FULL && 5838 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5839 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5840 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5841 vcpu->run->internal.ndata = 3; 5842 vcpu->run->internal.data[0] = vectoring_info; 5843 vcpu->run->internal.data[1] = exit_reason; 5844 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5845 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5846 vcpu->run->internal.ndata++; 5847 vcpu->run->internal.data[3] = 5848 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5849 } 5850 return 0; 5851 } 5852 5853 if (unlikely(!enable_vnmi && 5854 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5855 if (vmx_interrupt_allowed(vcpu)) { 5856 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5857 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5858 vcpu->arch.nmi_pending) { 5859 /* 5860 * This CPU don't support us in finding the end of an 5861 * NMI-blocked window if the guest runs with IRQs 5862 * disabled. So we pull the trigger after 1 s of 5863 * futile waiting, but inform the user about this. 5864 */ 5865 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5866 "state on VCPU %d after 1 s timeout\n", 5867 __func__, vcpu->vcpu_id); 5868 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5869 } 5870 } 5871 5872 if (exit_reason < kvm_vmx_max_exit_handlers 5873 && kvm_vmx_exit_handlers[exit_reason]) { 5874 #ifdef CONFIG_RETPOLINE 5875 if (exit_reason == EXIT_REASON_MSR_WRITE) 5876 return kvm_emulate_wrmsr(vcpu); 5877 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5878 return handle_preemption_timer(vcpu); 5879 else if (exit_reason == EXIT_REASON_PENDING_INTERRUPT) 5880 return handle_interrupt_window(vcpu); 5881 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5882 return handle_external_interrupt(vcpu); 5883 else if (exit_reason == EXIT_REASON_HLT) 5884 return kvm_emulate_halt(vcpu); 5885 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5886 return handle_ept_misconfig(vcpu); 5887 #endif 5888 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5889 } else { 5890 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", 5891 exit_reason); 5892 dump_vmcs(); 5893 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5894 vcpu->run->internal.suberror = 5895 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5896 vcpu->run->internal.ndata = 1; 5897 vcpu->run->internal.data[0] = exit_reason; 5898 return 0; 5899 } 5900 } 5901 5902 /* 5903 * Software based L1D cache flush which is used when microcode providing 5904 * the cache control MSR is not loaded. 5905 * 5906 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5907 * flush it is required to read in 64 KiB because the replacement algorithm 5908 * is not exactly LRU. This could be sized at runtime via topology 5909 * information but as all relevant affected CPUs have 32KiB L1D cache size 5910 * there is no point in doing so. 5911 */ 5912 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5913 { 5914 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5915 5916 /* 5917 * This code is only executed when the the flush mode is 'cond' or 5918 * 'always' 5919 */ 5920 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5921 bool flush_l1d; 5922 5923 /* 5924 * Clear the per-vcpu flush bit, it gets set again 5925 * either from vcpu_run() or from one of the unsafe 5926 * VMEXIT handlers. 5927 */ 5928 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5929 vcpu->arch.l1tf_flush_l1d = false; 5930 5931 /* 5932 * Clear the per-cpu flush bit, it gets set again from 5933 * the interrupt handlers. 5934 */ 5935 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 5936 kvm_clear_cpu_l1tf_flush_l1d(); 5937 5938 if (!flush_l1d) 5939 return; 5940 } 5941 5942 vcpu->stat.l1d_flush++; 5943 5944 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 5945 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 5946 return; 5947 } 5948 5949 asm volatile( 5950 /* First ensure the pages are in the TLB */ 5951 "xorl %%eax, %%eax\n" 5952 ".Lpopulate_tlb:\n\t" 5953 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5954 "addl $4096, %%eax\n\t" 5955 "cmpl %%eax, %[size]\n\t" 5956 "jne .Lpopulate_tlb\n\t" 5957 "xorl %%eax, %%eax\n\t" 5958 "cpuid\n\t" 5959 /* Now fill the cache */ 5960 "xorl %%eax, %%eax\n" 5961 ".Lfill_cache:\n" 5962 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5963 "addl $64, %%eax\n\t" 5964 "cmpl %%eax, %[size]\n\t" 5965 "jne .Lfill_cache\n\t" 5966 "lfence\n" 5967 :: [flush_pages] "r" (vmx_l1d_flush_pages), 5968 [size] "r" (size) 5969 : "eax", "ebx", "ecx", "edx"); 5970 } 5971 5972 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 5973 { 5974 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5975 int tpr_threshold; 5976 5977 if (is_guest_mode(vcpu) && 5978 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 5979 return; 5980 5981 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 5982 if (is_guest_mode(vcpu)) 5983 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 5984 else 5985 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 5986 } 5987 5988 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 5989 { 5990 struct vcpu_vmx *vmx = to_vmx(vcpu); 5991 u32 sec_exec_control; 5992 5993 if (!lapic_in_kernel(vcpu)) 5994 return; 5995 5996 if (!flexpriority_enabled && 5997 !cpu_has_vmx_virtualize_x2apic_mode()) 5998 return; 5999 6000 /* Postpone execution until vmcs01 is the current VMCS. */ 6001 if (is_guest_mode(vcpu)) { 6002 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6003 return; 6004 } 6005 6006 sec_exec_control = secondary_exec_controls_get(vmx); 6007 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6008 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6009 6010 switch (kvm_get_apic_mode(vcpu)) { 6011 case LAPIC_MODE_INVALID: 6012 WARN_ONCE(true, "Invalid local APIC state"); 6013 case LAPIC_MODE_DISABLED: 6014 break; 6015 case LAPIC_MODE_XAPIC: 6016 if (flexpriority_enabled) { 6017 sec_exec_control |= 6018 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6019 vmx_flush_tlb(vcpu, true); 6020 } 6021 break; 6022 case LAPIC_MODE_X2APIC: 6023 if (cpu_has_vmx_virtualize_x2apic_mode()) 6024 sec_exec_control |= 6025 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6026 break; 6027 } 6028 secondary_exec_controls_set(vmx, sec_exec_control); 6029 6030 vmx_update_msr_bitmap(vcpu); 6031 } 6032 6033 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6034 { 6035 if (!is_guest_mode(vcpu)) { 6036 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6037 vmx_flush_tlb(vcpu, true); 6038 } 6039 } 6040 6041 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6042 { 6043 u16 status; 6044 u8 old; 6045 6046 if (max_isr == -1) 6047 max_isr = 0; 6048 6049 status = vmcs_read16(GUEST_INTR_STATUS); 6050 old = status >> 8; 6051 if (max_isr != old) { 6052 status &= 0xff; 6053 status |= max_isr << 8; 6054 vmcs_write16(GUEST_INTR_STATUS, status); 6055 } 6056 } 6057 6058 static void vmx_set_rvi(int vector) 6059 { 6060 u16 status; 6061 u8 old; 6062 6063 if (vector == -1) 6064 vector = 0; 6065 6066 status = vmcs_read16(GUEST_INTR_STATUS); 6067 old = (u8)status & 0xff; 6068 if ((u8)vector != old) { 6069 status &= ~0xff; 6070 status |= (u8)vector; 6071 vmcs_write16(GUEST_INTR_STATUS, status); 6072 } 6073 } 6074 6075 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6076 { 6077 /* 6078 * When running L2, updating RVI is only relevant when 6079 * vmcs12 virtual-interrupt-delivery enabled. 6080 * However, it can be enabled only when L1 also 6081 * intercepts external-interrupts and in that case 6082 * we should not update vmcs02 RVI but instead intercept 6083 * interrupt. Therefore, do nothing when running L2. 6084 */ 6085 if (!is_guest_mode(vcpu)) 6086 vmx_set_rvi(max_irr); 6087 } 6088 6089 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6090 { 6091 struct vcpu_vmx *vmx = to_vmx(vcpu); 6092 int max_irr; 6093 bool max_irr_updated; 6094 6095 WARN_ON(!vcpu->arch.apicv_active); 6096 if (pi_test_on(&vmx->pi_desc)) { 6097 pi_clear_on(&vmx->pi_desc); 6098 /* 6099 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6100 * But on x86 this is just a compiler barrier anyway. 6101 */ 6102 smp_mb__after_atomic(); 6103 max_irr_updated = 6104 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6105 6106 /* 6107 * If we are running L2 and L1 has a new pending interrupt 6108 * which can be injected, we should re-evaluate 6109 * what should be done with this new L1 interrupt. 6110 * If L1 intercepts external-interrupts, we should 6111 * exit from L2 to L1. Otherwise, interrupt should be 6112 * delivered directly to L2. 6113 */ 6114 if (is_guest_mode(vcpu) && max_irr_updated) { 6115 if (nested_exit_on_intr(vcpu)) 6116 kvm_vcpu_exiting_guest_mode(vcpu); 6117 else 6118 kvm_make_request(KVM_REQ_EVENT, vcpu); 6119 } 6120 } else { 6121 max_irr = kvm_lapic_find_highest_irr(vcpu); 6122 } 6123 vmx_hwapic_irr_update(vcpu, max_irr); 6124 return max_irr; 6125 } 6126 6127 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6128 { 6129 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6130 6131 return pi_test_on(pi_desc) || 6132 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6133 } 6134 6135 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6136 { 6137 if (!kvm_vcpu_apicv_active(vcpu)) 6138 return; 6139 6140 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6141 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6142 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6143 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6144 } 6145 6146 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6147 { 6148 struct vcpu_vmx *vmx = to_vmx(vcpu); 6149 6150 pi_clear_on(&vmx->pi_desc); 6151 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6152 } 6153 6154 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6155 { 6156 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6157 6158 /* if exit due to PF check for async PF */ 6159 if (is_page_fault(vmx->exit_intr_info)) 6160 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6161 6162 /* Handle machine checks before interrupts are enabled */ 6163 if (is_machine_check(vmx->exit_intr_info)) 6164 kvm_machine_check(); 6165 6166 /* We need to handle NMIs before interrupts are enabled */ 6167 if (is_nmi(vmx->exit_intr_info)) { 6168 kvm_before_interrupt(&vmx->vcpu); 6169 asm("int $2"); 6170 kvm_after_interrupt(&vmx->vcpu); 6171 } 6172 } 6173 6174 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6175 { 6176 unsigned int vector; 6177 unsigned long entry; 6178 #ifdef CONFIG_X86_64 6179 unsigned long tmp; 6180 #endif 6181 gate_desc *desc; 6182 u32 intr_info; 6183 6184 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6185 if (WARN_ONCE(!is_external_intr(intr_info), 6186 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6187 return; 6188 6189 vector = intr_info & INTR_INFO_VECTOR_MASK; 6190 desc = (gate_desc *)host_idt_base + vector; 6191 entry = gate_offset(desc); 6192 6193 kvm_before_interrupt(vcpu); 6194 6195 asm volatile( 6196 #ifdef CONFIG_X86_64 6197 "mov %%" _ASM_SP ", %[sp]\n\t" 6198 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6199 "push $%c[ss]\n\t" 6200 "push %[sp]\n\t" 6201 #endif 6202 "pushf\n\t" 6203 __ASM_SIZE(push) " $%c[cs]\n\t" 6204 CALL_NOSPEC 6205 : 6206 #ifdef CONFIG_X86_64 6207 [sp]"=&r"(tmp), 6208 #endif 6209 ASM_CALL_CONSTRAINT 6210 : 6211 THUNK_TARGET(entry), 6212 [ss]"i"(__KERNEL_DS), 6213 [cs]"i"(__KERNEL_CS) 6214 ); 6215 6216 kvm_after_interrupt(vcpu); 6217 } 6218 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6219 6220 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu) 6221 { 6222 struct vcpu_vmx *vmx = to_vmx(vcpu); 6223 6224 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6225 handle_external_interrupt_irqoff(vcpu); 6226 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6227 handle_exception_nmi_irqoff(vmx); 6228 } 6229 6230 static bool vmx_has_emulated_msr(int index) 6231 { 6232 switch (index) { 6233 case MSR_IA32_SMBASE: 6234 /* 6235 * We cannot do SMM unless we can run the guest in big 6236 * real mode. 6237 */ 6238 return enable_unrestricted_guest || emulate_invalid_guest_state; 6239 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6240 return nested; 6241 case MSR_AMD64_VIRT_SPEC_CTRL: 6242 /* This is AMD only. */ 6243 return false; 6244 default: 6245 return true; 6246 } 6247 } 6248 6249 static bool vmx_pt_supported(void) 6250 { 6251 return pt_mode == PT_MODE_HOST_GUEST; 6252 } 6253 6254 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6255 { 6256 u32 exit_intr_info; 6257 bool unblock_nmi; 6258 u8 vector; 6259 bool idtv_info_valid; 6260 6261 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6262 6263 if (enable_vnmi) { 6264 if (vmx->loaded_vmcs->nmi_known_unmasked) 6265 return; 6266 /* 6267 * Can't use vmx->exit_intr_info since we're not sure what 6268 * the exit reason is. 6269 */ 6270 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6271 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6272 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6273 /* 6274 * SDM 3: 27.7.1.2 (September 2008) 6275 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6276 * a guest IRET fault. 6277 * SDM 3: 23.2.2 (September 2008) 6278 * Bit 12 is undefined in any of the following cases: 6279 * If the VM exit sets the valid bit in the IDT-vectoring 6280 * information field. 6281 * If the VM exit is due to a double fault. 6282 */ 6283 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6284 vector != DF_VECTOR && !idtv_info_valid) 6285 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6286 GUEST_INTR_STATE_NMI); 6287 else 6288 vmx->loaded_vmcs->nmi_known_unmasked = 6289 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6290 & GUEST_INTR_STATE_NMI); 6291 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6292 vmx->loaded_vmcs->vnmi_blocked_time += 6293 ktime_to_ns(ktime_sub(ktime_get(), 6294 vmx->loaded_vmcs->entry_time)); 6295 } 6296 6297 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6298 u32 idt_vectoring_info, 6299 int instr_len_field, 6300 int error_code_field) 6301 { 6302 u8 vector; 6303 int type; 6304 bool idtv_info_valid; 6305 6306 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6307 6308 vcpu->arch.nmi_injected = false; 6309 kvm_clear_exception_queue(vcpu); 6310 kvm_clear_interrupt_queue(vcpu); 6311 6312 if (!idtv_info_valid) 6313 return; 6314 6315 kvm_make_request(KVM_REQ_EVENT, vcpu); 6316 6317 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6318 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6319 6320 switch (type) { 6321 case INTR_TYPE_NMI_INTR: 6322 vcpu->arch.nmi_injected = true; 6323 /* 6324 * SDM 3: 27.7.1.2 (September 2008) 6325 * Clear bit "block by NMI" before VM entry if a NMI 6326 * delivery faulted. 6327 */ 6328 vmx_set_nmi_mask(vcpu, false); 6329 break; 6330 case INTR_TYPE_SOFT_EXCEPTION: 6331 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6332 /* fall through */ 6333 case INTR_TYPE_HARD_EXCEPTION: 6334 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6335 u32 err = vmcs_read32(error_code_field); 6336 kvm_requeue_exception_e(vcpu, vector, err); 6337 } else 6338 kvm_requeue_exception(vcpu, vector); 6339 break; 6340 case INTR_TYPE_SOFT_INTR: 6341 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6342 /* fall through */ 6343 case INTR_TYPE_EXT_INTR: 6344 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6345 break; 6346 default: 6347 break; 6348 } 6349 } 6350 6351 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6352 { 6353 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6354 VM_EXIT_INSTRUCTION_LEN, 6355 IDT_VECTORING_ERROR_CODE); 6356 } 6357 6358 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6359 { 6360 __vmx_complete_interrupts(vcpu, 6361 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6362 VM_ENTRY_INSTRUCTION_LEN, 6363 VM_ENTRY_EXCEPTION_ERROR_CODE); 6364 6365 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6366 } 6367 6368 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6369 { 6370 int i, nr_msrs; 6371 struct perf_guest_switch_msr *msrs; 6372 6373 msrs = perf_guest_get_msrs(&nr_msrs); 6374 6375 if (!msrs) 6376 return; 6377 6378 for (i = 0; i < nr_msrs; i++) 6379 if (msrs[i].host == msrs[i].guest) 6380 clear_atomic_switch_msr(vmx, msrs[i].msr); 6381 else 6382 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6383 msrs[i].host, false); 6384 } 6385 6386 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6387 { 6388 u32 host_umwait_control; 6389 6390 if (!vmx_has_waitpkg(vmx)) 6391 return; 6392 6393 host_umwait_control = get_umwait_control_msr(); 6394 6395 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6396 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6397 vmx->msr_ia32_umwait_control, 6398 host_umwait_control, false); 6399 else 6400 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6401 } 6402 6403 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6404 { 6405 struct vcpu_vmx *vmx = to_vmx(vcpu); 6406 u64 tscl; 6407 u32 delta_tsc; 6408 6409 if (vmx->req_immediate_exit) { 6410 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6411 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6412 } else if (vmx->hv_deadline_tsc != -1) { 6413 tscl = rdtsc(); 6414 if (vmx->hv_deadline_tsc > tscl) 6415 /* set_hv_timer ensures the delta fits in 32-bits */ 6416 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6417 cpu_preemption_timer_multi); 6418 else 6419 delta_tsc = 0; 6420 6421 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6422 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6423 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6424 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6425 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6426 } 6427 } 6428 6429 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6430 { 6431 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6432 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6433 vmcs_writel(HOST_RSP, host_rsp); 6434 } 6435 } 6436 6437 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6438 6439 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6440 { 6441 struct vcpu_vmx *vmx = to_vmx(vcpu); 6442 unsigned long cr3, cr4; 6443 6444 /* Record the guest's net vcpu time for enforced NMI injections. */ 6445 if (unlikely(!enable_vnmi && 6446 vmx->loaded_vmcs->soft_vnmi_blocked)) 6447 vmx->loaded_vmcs->entry_time = ktime_get(); 6448 6449 /* Don't enter VMX if guest state is invalid, let the exit handler 6450 start emulation until we arrive back to a valid state */ 6451 if (vmx->emulation_required) 6452 return; 6453 6454 if (vmx->ple_window_dirty) { 6455 vmx->ple_window_dirty = false; 6456 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6457 } 6458 6459 if (vmx->nested.need_vmcs12_to_shadow_sync) 6460 nested_sync_vmcs12_to_shadow(vcpu); 6461 6462 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6463 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6464 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6465 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6466 6467 cr3 = __get_current_cr3_fast(); 6468 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6469 vmcs_writel(HOST_CR3, cr3); 6470 vmx->loaded_vmcs->host_state.cr3 = cr3; 6471 } 6472 6473 cr4 = cr4_read_shadow(); 6474 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6475 vmcs_writel(HOST_CR4, cr4); 6476 vmx->loaded_vmcs->host_state.cr4 = cr4; 6477 } 6478 6479 /* When single-stepping over STI and MOV SS, we must clear the 6480 * corresponding interruptibility bits in the guest state. Otherwise 6481 * vmentry fails as it then expects bit 14 (BS) in pending debug 6482 * exceptions being set, but that's not correct for the guest debugging 6483 * case. */ 6484 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6485 vmx_set_interrupt_shadow(vcpu, 0); 6486 6487 kvm_load_guest_xsave_state(vcpu); 6488 6489 if (static_cpu_has(X86_FEATURE_PKU) && 6490 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6491 vcpu->arch.pkru != vmx->host_pkru) 6492 __write_pkru(vcpu->arch.pkru); 6493 6494 pt_guest_enter(vmx); 6495 6496 atomic_switch_perf_msrs(vmx); 6497 atomic_switch_umwait_control_msr(vmx); 6498 6499 if (enable_preemption_timer) 6500 vmx_update_hv_timer(vcpu); 6501 6502 if (lapic_in_kernel(vcpu) && 6503 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6504 kvm_wait_lapic_expire(vcpu); 6505 6506 /* 6507 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6508 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6509 * is no need to worry about the conditional branch over the wrmsr 6510 * being speculatively taken. 6511 */ 6512 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6513 6514 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6515 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6516 vmx_l1d_flush(vcpu); 6517 else if (static_branch_unlikely(&mds_user_clear)) 6518 mds_clear_cpu_buffers(); 6519 6520 if (vcpu->arch.cr2 != read_cr2()) 6521 write_cr2(vcpu->arch.cr2); 6522 6523 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6524 vmx->loaded_vmcs->launched); 6525 6526 vcpu->arch.cr2 = read_cr2(); 6527 6528 /* 6529 * We do not use IBRS in the kernel. If this vCPU has used the 6530 * SPEC_CTRL MSR it may have left it on; save the value and 6531 * turn it off. This is much more efficient than blindly adding 6532 * it to the atomic save/restore list. Especially as the former 6533 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6534 * 6535 * For non-nested case: 6536 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6537 * save it. 6538 * 6539 * For nested case: 6540 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6541 * save it. 6542 */ 6543 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6544 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6545 6546 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6547 6548 /* All fields are clean at this point */ 6549 if (static_branch_unlikely(&enable_evmcs)) 6550 current_evmcs->hv_clean_fields |= 6551 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6552 6553 if (static_branch_unlikely(&enable_evmcs)) 6554 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6555 6556 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6557 if (vmx->host_debugctlmsr) 6558 update_debugctlmsr(vmx->host_debugctlmsr); 6559 6560 #ifndef CONFIG_X86_64 6561 /* 6562 * The sysexit path does not restore ds/es, so we must set them to 6563 * a reasonable value ourselves. 6564 * 6565 * We can't defer this to vmx_prepare_switch_to_host() since that 6566 * function may be executed in interrupt context, which saves and 6567 * restore segments around it, nullifying its effect. 6568 */ 6569 loadsegment(ds, __USER_DS); 6570 loadsegment(es, __USER_DS); 6571 #endif 6572 6573 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6574 | (1 << VCPU_EXREG_RFLAGS) 6575 | (1 << VCPU_EXREG_PDPTR) 6576 | (1 << VCPU_EXREG_SEGMENTS) 6577 | (1 << VCPU_EXREG_CR3)); 6578 vcpu->arch.regs_dirty = 0; 6579 6580 pt_guest_exit(vmx); 6581 6582 /* 6583 * eager fpu is enabled if PKEY is supported and CR4 is switched 6584 * back on host, so it is safe to read guest PKRU from current 6585 * XSAVE. 6586 */ 6587 if (static_cpu_has(X86_FEATURE_PKU) && 6588 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6589 vcpu->arch.pkru = rdpkru(); 6590 if (vcpu->arch.pkru != vmx->host_pkru) 6591 __write_pkru(vmx->host_pkru); 6592 } 6593 6594 kvm_load_host_xsave_state(vcpu); 6595 6596 vmx->nested.nested_run_pending = 0; 6597 vmx->idt_vectoring_info = 0; 6598 6599 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6600 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6601 kvm_machine_check(); 6602 6603 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6604 return; 6605 6606 vmx->loaded_vmcs->launched = 1; 6607 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6608 6609 vmx_recover_nmi_blocking(vmx); 6610 vmx_complete_interrupts(vmx); 6611 } 6612 6613 static struct kvm *vmx_vm_alloc(void) 6614 { 6615 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6616 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6617 PAGE_KERNEL); 6618 return &kvm_vmx->kvm; 6619 } 6620 6621 static void vmx_vm_free(struct kvm *kvm) 6622 { 6623 kfree(kvm->arch.hyperv.hv_pa_pg); 6624 vfree(to_kvm_vmx(kvm)); 6625 } 6626 6627 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6628 { 6629 struct vcpu_vmx *vmx = to_vmx(vcpu); 6630 6631 if (enable_pml) 6632 vmx_destroy_pml_buffer(vmx); 6633 free_vpid(vmx->vpid); 6634 nested_vmx_free_vcpu(vcpu); 6635 free_loaded_vmcs(vmx->loaded_vmcs); 6636 kvm_vcpu_uninit(vcpu); 6637 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); 6638 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); 6639 kmem_cache_free(kvm_vcpu_cache, vmx); 6640 } 6641 6642 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) 6643 { 6644 int err; 6645 struct vcpu_vmx *vmx; 6646 unsigned long *msr_bitmap; 6647 int i, cpu; 6648 6649 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0, 6650 "struct kvm_vcpu must be at offset 0 for arch usercopy region"); 6651 6652 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT); 6653 if (!vmx) 6654 return ERR_PTR(-ENOMEM); 6655 6656 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 6657 GFP_KERNEL_ACCOUNT); 6658 if (!vmx->vcpu.arch.user_fpu) { 6659 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n"); 6660 err = -ENOMEM; 6661 goto free_partial_vcpu; 6662 } 6663 6664 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 6665 GFP_KERNEL_ACCOUNT); 6666 if (!vmx->vcpu.arch.guest_fpu) { 6667 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); 6668 err = -ENOMEM; 6669 goto free_user_fpu; 6670 } 6671 6672 vmx->vpid = allocate_vpid(); 6673 6674 err = kvm_vcpu_init(&vmx->vcpu, kvm, id); 6675 if (err) 6676 goto free_vcpu; 6677 6678 err = -ENOMEM; 6679 6680 /* 6681 * If PML is turned on, failure on enabling PML just results in failure 6682 * of creating the vcpu, therefore we can simplify PML logic (by 6683 * avoiding dealing with cases, such as enabling PML partially on vcpus 6684 * for the guest, etc. 6685 */ 6686 if (enable_pml) { 6687 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6688 if (!vmx->pml_pg) 6689 goto uninit_vcpu; 6690 } 6691 6692 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6693 6694 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6695 u32 index = vmx_msr_index[i]; 6696 u32 data_low, data_high; 6697 int j = vmx->nmsrs; 6698 6699 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6700 continue; 6701 if (wrmsr_safe(index, data_low, data_high) < 0) 6702 continue; 6703 6704 vmx->guest_msrs[j].index = i; 6705 vmx->guest_msrs[j].data = 0; 6706 switch (index) { 6707 case MSR_IA32_TSX_CTRL: 6708 /* 6709 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6710 * let's avoid changing CPUID bits under the host 6711 * kernel's feet. 6712 */ 6713 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6714 break; 6715 default: 6716 vmx->guest_msrs[j].mask = -1ull; 6717 break; 6718 } 6719 ++vmx->nmsrs; 6720 } 6721 6722 err = alloc_loaded_vmcs(&vmx->vmcs01); 6723 if (err < 0) 6724 goto free_pml; 6725 6726 msr_bitmap = vmx->vmcs01.msr_bitmap; 6727 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6728 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6729 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6730 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6731 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6732 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6733 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6734 if (kvm_cstate_in_guest(kvm)) { 6735 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6736 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6737 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6738 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6739 } 6740 vmx->msr_bitmap_mode = 0; 6741 6742 vmx->loaded_vmcs = &vmx->vmcs01; 6743 cpu = get_cpu(); 6744 vmx_vcpu_load(&vmx->vcpu, cpu); 6745 vmx->vcpu.cpu = cpu; 6746 init_vmcs(vmx); 6747 vmx_vcpu_put(&vmx->vcpu); 6748 put_cpu(); 6749 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { 6750 err = alloc_apic_access_page(kvm); 6751 if (err) 6752 goto free_vmcs; 6753 } 6754 6755 if (enable_ept && !enable_unrestricted_guest) { 6756 err = init_rmode_identity_map(kvm); 6757 if (err) 6758 goto free_vmcs; 6759 } 6760 6761 if (nested) 6762 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6763 vmx_capability.ept, 6764 kvm_vcpu_apicv_active(&vmx->vcpu)); 6765 else 6766 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6767 6768 vmx->nested.posted_intr_nv = -1; 6769 vmx->nested.current_vmptr = -1ull; 6770 6771 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6772 6773 /* 6774 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6775 * or POSTED_INTR_WAKEUP_VECTOR. 6776 */ 6777 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6778 vmx->pi_desc.sn = 1; 6779 6780 vmx->ept_pointer = INVALID_PAGE; 6781 6782 return &vmx->vcpu; 6783 6784 free_vmcs: 6785 free_loaded_vmcs(vmx->loaded_vmcs); 6786 free_pml: 6787 vmx_destroy_pml_buffer(vmx); 6788 uninit_vcpu: 6789 kvm_vcpu_uninit(&vmx->vcpu); 6790 free_vcpu: 6791 free_vpid(vmx->vpid); 6792 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); 6793 free_user_fpu: 6794 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); 6795 free_partial_vcpu: 6796 kmem_cache_free(kvm_vcpu_cache, vmx); 6797 return ERR_PTR(err); 6798 } 6799 6800 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6801 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6802 6803 static int vmx_vm_init(struct kvm *kvm) 6804 { 6805 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6806 6807 if (!ple_gap) 6808 kvm->arch.pause_in_guest = true; 6809 6810 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6811 switch (l1tf_mitigation) { 6812 case L1TF_MITIGATION_OFF: 6813 case L1TF_MITIGATION_FLUSH_NOWARN: 6814 /* 'I explicitly don't care' is set */ 6815 break; 6816 case L1TF_MITIGATION_FLUSH: 6817 case L1TF_MITIGATION_FLUSH_NOSMT: 6818 case L1TF_MITIGATION_FULL: 6819 /* 6820 * Warn upon starting the first VM in a potentially 6821 * insecure environment. 6822 */ 6823 if (sched_smt_active()) 6824 pr_warn_once(L1TF_MSG_SMT); 6825 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6826 pr_warn_once(L1TF_MSG_L1D); 6827 break; 6828 case L1TF_MITIGATION_FULL_FORCE: 6829 /* Flush is enforced */ 6830 break; 6831 } 6832 } 6833 return 0; 6834 } 6835 6836 static int __init vmx_check_processor_compat(void) 6837 { 6838 struct vmcs_config vmcs_conf; 6839 struct vmx_capability vmx_cap; 6840 6841 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6842 !this_cpu_has(X86_FEATURE_VMX)) { 6843 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6844 return -EIO; 6845 } 6846 6847 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6848 return -EIO; 6849 if (nested) 6850 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept, 6851 enable_apicv); 6852 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6853 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6854 smp_processor_id()); 6855 return -EIO; 6856 } 6857 return 0; 6858 } 6859 6860 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6861 { 6862 u8 cache; 6863 u64 ipat = 0; 6864 6865 /* For VT-d and EPT combination 6866 * 1. MMIO: always map as UC 6867 * 2. EPT with VT-d: 6868 * a. VT-d without snooping control feature: can't guarantee the 6869 * result, try to trust guest. 6870 * b. VT-d with snooping control feature: snooping control feature of 6871 * VT-d engine can guarantee the cache correctness. Just set it 6872 * to WB to keep consistent with host. So the same as item 3. 6873 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6874 * consistent with host MTRR 6875 */ 6876 if (is_mmio) { 6877 cache = MTRR_TYPE_UNCACHABLE; 6878 goto exit; 6879 } 6880 6881 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6882 ipat = VMX_EPT_IPAT_BIT; 6883 cache = MTRR_TYPE_WRBACK; 6884 goto exit; 6885 } 6886 6887 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6888 ipat = VMX_EPT_IPAT_BIT; 6889 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6890 cache = MTRR_TYPE_WRBACK; 6891 else 6892 cache = MTRR_TYPE_UNCACHABLE; 6893 goto exit; 6894 } 6895 6896 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6897 6898 exit: 6899 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6900 } 6901 6902 static int vmx_get_lpage_level(void) 6903 { 6904 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6905 return PT_DIRECTORY_LEVEL; 6906 else 6907 /* For shadow and EPT supported 1GB page */ 6908 return PT_PDPE_LEVEL; 6909 } 6910 6911 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6912 { 6913 /* 6914 * These bits in the secondary execution controls field 6915 * are dynamic, the others are mostly based on the hypervisor 6916 * architecture and the guest's CPUID. Do not touch the 6917 * dynamic bits. 6918 */ 6919 u32 mask = 6920 SECONDARY_EXEC_SHADOW_VMCS | 6921 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6922 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6923 SECONDARY_EXEC_DESC; 6924 6925 u32 new_ctl = vmx->secondary_exec_control; 6926 u32 cur_ctl = secondary_exec_controls_get(vmx); 6927 6928 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6929 } 6930 6931 /* 6932 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6933 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6934 */ 6935 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6936 { 6937 struct vcpu_vmx *vmx = to_vmx(vcpu); 6938 struct kvm_cpuid_entry2 *entry; 6939 6940 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6941 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6942 6943 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6944 if (entry && (entry->_reg & (_cpuid_mask))) \ 6945 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6946 } while (0) 6947 6948 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6949 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); 6950 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); 6951 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); 6952 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); 6953 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); 6954 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); 6955 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); 6956 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); 6957 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); 6958 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); 6959 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); 6960 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); 6961 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); 6962 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); 6963 6964 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6965 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); 6966 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); 6967 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); 6968 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); 6969 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); 6970 cr4_fixed1_update(X86_CR4_LA57, ecx, bit(X86_FEATURE_LA57)); 6971 6972 #undef cr4_fixed1_update 6973 } 6974 6975 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 6976 { 6977 struct vcpu_vmx *vmx = to_vmx(vcpu); 6978 6979 if (kvm_mpx_supported()) { 6980 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 6981 6982 if (mpx_enabled) { 6983 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 6984 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 6985 } else { 6986 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 6987 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 6988 } 6989 } 6990 } 6991 6992 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 6993 { 6994 struct vcpu_vmx *vmx = to_vmx(vcpu); 6995 struct kvm_cpuid_entry2 *best = NULL; 6996 int i; 6997 6998 for (i = 0; i < PT_CPUID_LEAVES; i++) { 6999 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7000 if (!best) 7001 return; 7002 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7003 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7004 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7005 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7006 } 7007 7008 /* Get the number of configurable Address Ranges for filtering */ 7009 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7010 PT_CAP_num_address_ranges); 7011 7012 /* Initialize and clear the no dependency bits */ 7013 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7014 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7015 7016 /* 7017 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7018 * will inject an #GP 7019 */ 7020 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7021 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7022 7023 /* 7024 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7025 * PSBFreq can be set 7026 */ 7027 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7028 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7029 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7030 7031 /* 7032 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7033 * MTCFreq can be set 7034 */ 7035 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7036 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7037 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7038 7039 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7040 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7041 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7042 RTIT_CTL_PTW_EN); 7043 7044 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7045 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7046 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7047 7048 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7049 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7050 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7051 7052 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7053 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7054 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7055 7056 /* unmask address range configure area */ 7057 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7058 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7059 } 7060 7061 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7062 { 7063 struct vcpu_vmx *vmx = to_vmx(vcpu); 7064 7065 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7066 vcpu->arch.xsaves_enabled = false; 7067 7068 if (cpu_has_secondary_exec_ctrls()) { 7069 vmx_compute_secondary_exec_control(vmx); 7070 vmcs_set_secondary_exec_control(vmx); 7071 } 7072 7073 if (nested_vmx_allowed(vcpu)) 7074 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7075 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7076 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7077 else 7078 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7079 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7080 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7081 7082 if (nested_vmx_allowed(vcpu)) { 7083 nested_vmx_cr_fixed1_bits_update(vcpu); 7084 nested_vmx_entry_exit_ctls_update(vcpu); 7085 } 7086 7087 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7088 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7089 update_intel_pt_cfg(vcpu); 7090 7091 if (boot_cpu_has(X86_FEATURE_RTM)) { 7092 struct shared_msr_entry *msr; 7093 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7094 if (msr) { 7095 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7096 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7097 } 7098 } 7099 } 7100 7101 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 7102 { 7103 if (func == 1 && nested) 7104 entry->ecx |= bit(X86_FEATURE_VMX); 7105 } 7106 7107 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7108 { 7109 to_vmx(vcpu)->req_immediate_exit = true; 7110 } 7111 7112 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7113 struct x86_instruction_info *info, 7114 enum x86_intercept_stage stage) 7115 { 7116 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7117 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7118 7119 /* 7120 * RDPID causes #UD if disabled through secondary execution controls. 7121 * Because it is marked as EmulateOnUD, we need to intercept it here. 7122 */ 7123 if (info->intercept == x86_intercept_rdtscp && 7124 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7125 ctxt->exception.vector = UD_VECTOR; 7126 ctxt->exception.error_code_valid = false; 7127 return X86EMUL_PROPAGATE_FAULT; 7128 } 7129 7130 /* TODO: check more intercepts... */ 7131 return X86EMUL_CONTINUE; 7132 } 7133 7134 #ifdef CONFIG_X86_64 7135 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7136 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7137 u64 divisor, u64 *result) 7138 { 7139 u64 low = a << shift, high = a >> (64 - shift); 7140 7141 /* To avoid the overflow on divq */ 7142 if (high >= divisor) 7143 return 1; 7144 7145 /* Low hold the result, high hold rem which is discarded */ 7146 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7147 "rm" (divisor), "0" (low), "1" (high)); 7148 *result = low; 7149 7150 return 0; 7151 } 7152 7153 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7154 bool *expired) 7155 { 7156 struct vcpu_vmx *vmx; 7157 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7158 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7159 7160 if (kvm_mwait_in_guest(vcpu->kvm) || 7161 kvm_can_post_timer_interrupt(vcpu)) 7162 return -EOPNOTSUPP; 7163 7164 vmx = to_vmx(vcpu); 7165 tscl = rdtsc(); 7166 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7167 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7168 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7169 ktimer->timer_advance_ns); 7170 7171 if (delta_tsc > lapic_timer_advance_cycles) 7172 delta_tsc -= lapic_timer_advance_cycles; 7173 else 7174 delta_tsc = 0; 7175 7176 /* Convert to host delta tsc if tsc scaling is enabled */ 7177 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7178 delta_tsc && u64_shl_div_u64(delta_tsc, 7179 kvm_tsc_scaling_ratio_frac_bits, 7180 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7181 return -ERANGE; 7182 7183 /* 7184 * If the delta tsc can't fit in the 32 bit after the multi shift, 7185 * we can't use the preemption timer. 7186 * It's possible that it fits on later vmentries, but checking 7187 * on every vmentry is costly so we just use an hrtimer. 7188 */ 7189 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7190 return -ERANGE; 7191 7192 vmx->hv_deadline_tsc = tscl + delta_tsc; 7193 *expired = !delta_tsc; 7194 return 0; 7195 } 7196 7197 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7198 { 7199 to_vmx(vcpu)->hv_deadline_tsc = -1; 7200 } 7201 #endif 7202 7203 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7204 { 7205 if (!kvm_pause_in_guest(vcpu->kvm)) 7206 shrink_ple_window(vcpu); 7207 } 7208 7209 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7210 struct kvm_memory_slot *slot) 7211 { 7212 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7213 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7214 } 7215 7216 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7217 struct kvm_memory_slot *slot) 7218 { 7219 kvm_mmu_slot_set_dirty(kvm, slot); 7220 } 7221 7222 static void vmx_flush_log_dirty(struct kvm *kvm) 7223 { 7224 kvm_flush_pml_buffers(kvm); 7225 } 7226 7227 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7228 { 7229 struct vmcs12 *vmcs12; 7230 struct vcpu_vmx *vmx = to_vmx(vcpu); 7231 gpa_t gpa, dst; 7232 7233 if (is_guest_mode(vcpu)) { 7234 WARN_ON_ONCE(vmx->nested.pml_full); 7235 7236 /* 7237 * Check if PML is enabled for the nested guest. 7238 * Whether eptp bit 6 is set is already checked 7239 * as part of A/D emulation. 7240 */ 7241 vmcs12 = get_vmcs12(vcpu); 7242 if (!nested_cpu_has_pml(vmcs12)) 7243 return 0; 7244 7245 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7246 vmx->nested.pml_full = true; 7247 return 1; 7248 } 7249 7250 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7251 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7252 7253 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7254 offset_in_page(dst), sizeof(gpa))) 7255 return 0; 7256 7257 vmcs12->guest_pml_index--; 7258 } 7259 7260 return 0; 7261 } 7262 7263 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7264 struct kvm_memory_slot *memslot, 7265 gfn_t offset, unsigned long mask) 7266 { 7267 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7268 } 7269 7270 static void __pi_post_block(struct kvm_vcpu *vcpu) 7271 { 7272 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7273 struct pi_desc old, new; 7274 unsigned int dest; 7275 7276 do { 7277 old.control = new.control = pi_desc->control; 7278 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7279 "Wakeup handler not enabled while the VCPU is blocked\n"); 7280 7281 dest = cpu_physical_id(vcpu->cpu); 7282 7283 if (x2apic_enabled()) 7284 new.ndst = dest; 7285 else 7286 new.ndst = (dest << 8) & 0xFF00; 7287 7288 /* set 'NV' to 'notification vector' */ 7289 new.nv = POSTED_INTR_VECTOR; 7290 } while (cmpxchg64(&pi_desc->control, old.control, 7291 new.control) != old.control); 7292 7293 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7294 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7295 list_del(&vcpu->blocked_vcpu_list); 7296 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7297 vcpu->pre_pcpu = -1; 7298 } 7299 } 7300 7301 /* 7302 * This routine does the following things for vCPU which is going 7303 * to be blocked if VT-d PI is enabled. 7304 * - Store the vCPU to the wakeup list, so when interrupts happen 7305 * we can find the right vCPU to wake up. 7306 * - Change the Posted-interrupt descriptor as below: 7307 * 'NDST' <-- vcpu->pre_pcpu 7308 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7309 * - If 'ON' is set during this process, which means at least one 7310 * interrupt is posted for this vCPU, we cannot block it, in 7311 * this case, return 1, otherwise, return 0. 7312 * 7313 */ 7314 static int pi_pre_block(struct kvm_vcpu *vcpu) 7315 { 7316 unsigned int dest; 7317 struct pi_desc old, new; 7318 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7319 7320 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7321 !irq_remapping_cap(IRQ_POSTING_CAP) || 7322 !kvm_vcpu_apicv_active(vcpu)) 7323 return 0; 7324 7325 WARN_ON(irqs_disabled()); 7326 local_irq_disable(); 7327 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7328 vcpu->pre_pcpu = vcpu->cpu; 7329 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7330 list_add_tail(&vcpu->blocked_vcpu_list, 7331 &per_cpu(blocked_vcpu_on_cpu, 7332 vcpu->pre_pcpu)); 7333 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7334 } 7335 7336 do { 7337 old.control = new.control = pi_desc->control; 7338 7339 WARN((pi_desc->sn == 1), 7340 "Warning: SN field of posted-interrupts " 7341 "is set before blocking\n"); 7342 7343 /* 7344 * Since vCPU can be preempted during this process, 7345 * vcpu->cpu could be different with pre_pcpu, we 7346 * need to set pre_pcpu as the destination of wakeup 7347 * notification event, then we can find the right vCPU 7348 * to wakeup in wakeup handler if interrupts happen 7349 * when the vCPU is in blocked state. 7350 */ 7351 dest = cpu_physical_id(vcpu->pre_pcpu); 7352 7353 if (x2apic_enabled()) 7354 new.ndst = dest; 7355 else 7356 new.ndst = (dest << 8) & 0xFF00; 7357 7358 /* set 'NV' to 'wakeup vector' */ 7359 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7360 } while (cmpxchg64(&pi_desc->control, old.control, 7361 new.control) != old.control); 7362 7363 /* We should not block the vCPU if an interrupt is posted for it. */ 7364 if (pi_test_on(pi_desc) == 1) 7365 __pi_post_block(vcpu); 7366 7367 local_irq_enable(); 7368 return (vcpu->pre_pcpu == -1); 7369 } 7370 7371 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7372 { 7373 if (pi_pre_block(vcpu)) 7374 return 1; 7375 7376 if (kvm_lapic_hv_timer_in_use(vcpu)) 7377 kvm_lapic_switch_to_sw_timer(vcpu); 7378 7379 return 0; 7380 } 7381 7382 static void pi_post_block(struct kvm_vcpu *vcpu) 7383 { 7384 if (vcpu->pre_pcpu == -1) 7385 return; 7386 7387 WARN_ON(irqs_disabled()); 7388 local_irq_disable(); 7389 __pi_post_block(vcpu); 7390 local_irq_enable(); 7391 } 7392 7393 static void vmx_post_block(struct kvm_vcpu *vcpu) 7394 { 7395 if (kvm_x86_ops->set_hv_timer) 7396 kvm_lapic_switch_to_hv_timer(vcpu); 7397 7398 pi_post_block(vcpu); 7399 } 7400 7401 /* 7402 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7403 * 7404 * @kvm: kvm 7405 * @host_irq: host irq of the interrupt 7406 * @guest_irq: gsi of the interrupt 7407 * @set: set or unset PI 7408 * returns 0 on success, < 0 on failure 7409 */ 7410 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7411 uint32_t guest_irq, bool set) 7412 { 7413 struct kvm_kernel_irq_routing_entry *e; 7414 struct kvm_irq_routing_table *irq_rt; 7415 struct kvm_lapic_irq irq; 7416 struct kvm_vcpu *vcpu; 7417 struct vcpu_data vcpu_info; 7418 int idx, ret = 0; 7419 7420 if (!kvm_arch_has_assigned_device(kvm) || 7421 !irq_remapping_cap(IRQ_POSTING_CAP) || 7422 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7423 return 0; 7424 7425 idx = srcu_read_lock(&kvm->irq_srcu); 7426 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7427 if (guest_irq >= irq_rt->nr_rt_entries || 7428 hlist_empty(&irq_rt->map[guest_irq])) { 7429 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7430 guest_irq, irq_rt->nr_rt_entries); 7431 goto out; 7432 } 7433 7434 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7435 if (e->type != KVM_IRQ_ROUTING_MSI) 7436 continue; 7437 /* 7438 * VT-d PI cannot support posting multicast/broadcast 7439 * interrupts to a vCPU, we still use interrupt remapping 7440 * for these kind of interrupts. 7441 * 7442 * For lowest-priority interrupts, we only support 7443 * those with single CPU as the destination, e.g. user 7444 * configures the interrupts via /proc/irq or uses 7445 * irqbalance to make the interrupts single-CPU. 7446 * 7447 * We will support full lowest-priority interrupt later. 7448 * 7449 * In addition, we can only inject generic interrupts using 7450 * the PI mechanism, refuse to route others through it. 7451 */ 7452 7453 kvm_set_msi_irq(kvm, e, &irq); 7454 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7455 !kvm_irq_is_postable(&irq)) { 7456 /* 7457 * Make sure the IRTE is in remapped mode if 7458 * we don't handle it in posted mode. 7459 */ 7460 ret = irq_set_vcpu_affinity(host_irq, NULL); 7461 if (ret < 0) { 7462 printk(KERN_INFO 7463 "failed to back to remapped mode, irq: %u\n", 7464 host_irq); 7465 goto out; 7466 } 7467 7468 continue; 7469 } 7470 7471 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7472 vcpu_info.vector = irq.vector; 7473 7474 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7475 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7476 7477 if (set) 7478 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7479 else 7480 ret = irq_set_vcpu_affinity(host_irq, NULL); 7481 7482 if (ret < 0) { 7483 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7484 __func__); 7485 goto out; 7486 } 7487 } 7488 7489 ret = 0; 7490 out: 7491 srcu_read_unlock(&kvm->irq_srcu, idx); 7492 return ret; 7493 } 7494 7495 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7496 { 7497 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7498 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7499 FEAT_CTL_LMCE_ENABLED; 7500 else 7501 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7502 ~FEAT_CTL_LMCE_ENABLED; 7503 } 7504 7505 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7506 { 7507 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7508 if (to_vmx(vcpu)->nested.nested_run_pending) 7509 return 0; 7510 return 1; 7511 } 7512 7513 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7514 { 7515 struct vcpu_vmx *vmx = to_vmx(vcpu); 7516 7517 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7518 if (vmx->nested.smm.guest_mode) 7519 nested_vmx_vmexit(vcpu, -1, 0, 0); 7520 7521 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7522 vmx->nested.vmxon = false; 7523 vmx_clear_hlt(vcpu); 7524 return 0; 7525 } 7526 7527 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7528 { 7529 struct vcpu_vmx *vmx = to_vmx(vcpu); 7530 int ret; 7531 7532 if (vmx->nested.smm.vmxon) { 7533 vmx->nested.vmxon = true; 7534 vmx->nested.smm.vmxon = false; 7535 } 7536 7537 if (vmx->nested.smm.guest_mode) { 7538 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7539 if (ret) 7540 return ret; 7541 7542 vmx->nested.smm.guest_mode = false; 7543 } 7544 return 0; 7545 } 7546 7547 static int enable_smi_window(struct kvm_vcpu *vcpu) 7548 { 7549 return 0; 7550 } 7551 7552 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7553 { 7554 return false; 7555 } 7556 7557 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7558 { 7559 return to_vmx(vcpu)->nested.vmxon; 7560 } 7561 7562 static __init int hardware_setup(void) 7563 { 7564 unsigned long host_bndcfgs; 7565 struct desc_ptr dt; 7566 int r, i; 7567 7568 rdmsrl_safe(MSR_EFER, &host_efer); 7569 7570 store_idt(&dt); 7571 host_idt_base = dt.address; 7572 7573 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7574 kvm_define_shared_msr(i, vmx_msr_index[i]); 7575 7576 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7577 return -EIO; 7578 7579 if (boot_cpu_has(X86_FEATURE_NX)) 7580 kvm_enable_efer_bits(EFER_NX); 7581 7582 if (boot_cpu_has(X86_FEATURE_MPX)) { 7583 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7584 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7585 } 7586 7587 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7588 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7589 enable_vpid = 0; 7590 7591 if (!cpu_has_vmx_ept() || 7592 !cpu_has_vmx_ept_4levels() || 7593 !cpu_has_vmx_ept_mt_wb() || 7594 !cpu_has_vmx_invept_global()) 7595 enable_ept = 0; 7596 7597 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7598 enable_ept_ad_bits = 0; 7599 7600 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7601 enable_unrestricted_guest = 0; 7602 7603 if (!cpu_has_vmx_flexpriority()) 7604 flexpriority_enabled = 0; 7605 7606 if (!cpu_has_virtual_nmis()) 7607 enable_vnmi = 0; 7608 7609 /* 7610 * set_apic_access_page_addr() is used to reload apic access 7611 * page upon invalidation. No need to do anything if not 7612 * using the APIC_ACCESS_ADDR VMCS field. 7613 */ 7614 if (!flexpriority_enabled) 7615 kvm_x86_ops->set_apic_access_page_addr = NULL; 7616 7617 if (!cpu_has_vmx_tpr_shadow()) 7618 kvm_x86_ops->update_cr8_intercept = NULL; 7619 7620 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7621 kvm_disable_largepages(); 7622 7623 #if IS_ENABLED(CONFIG_HYPERV) 7624 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7625 && enable_ept) { 7626 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7627 kvm_x86_ops->tlb_remote_flush_with_range = 7628 hv_remote_flush_tlb_with_range; 7629 } 7630 #endif 7631 7632 if (!cpu_has_vmx_ple()) { 7633 ple_gap = 0; 7634 ple_window = 0; 7635 ple_window_grow = 0; 7636 ple_window_max = 0; 7637 ple_window_shrink = 0; 7638 } 7639 7640 if (!cpu_has_vmx_apicv()) { 7641 enable_apicv = 0; 7642 kvm_x86_ops->sync_pir_to_irr = NULL; 7643 } 7644 7645 if (cpu_has_vmx_tsc_scaling()) { 7646 kvm_has_tsc_control = true; 7647 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7648 kvm_tsc_scaling_ratio_frac_bits = 48; 7649 } 7650 7651 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7652 7653 if (enable_ept) 7654 vmx_enable_tdp(); 7655 else 7656 kvm_disable_tdp(); 7657 7658 /* 7659 * Only enable PML when hardware supports PML feature, and both EPT 7660 * and EPT A/D bit features are enabled -- PML depends on them to work. 7661 */ 7662 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7663 enable_pml = 0; 7664 7665 if (!enable_pml) { 7666 kvm_x86_ops->slot_enable_log_dirty = NULL; 7667 kvm_x86_ops->slot_disable_log_dirty = NULL; 7668 kvm_x86_ops->flush_log_dirty = NULL; 7669 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7670 } 7671 7672 if (!cpu_has_vmx_preemption_timer()) 7673 enable_preemption_timer = false; 7674 7675 if (enable_preemption_timer) { 7676 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7677 u64 vmx_msr; 7678 7679 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7680 cpu_preemption_timer_multi = 7681 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7682 7683 if (tsc_khz) 7684 use_timer_freq = (u64)tsc_khz * 1000; 7685 use_timer_freq >>= cpu_preemption_timer_multi; 7686 7687 /* 7688 * KVM "disables" the preemption timer by setting it to its max 7689 * value. Don't use the timer if it might cause spurious exits 7690 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7691 */ 7692 if (use_timer_freq > 0xffffffffu / 10) 7693 enable_preemption_timer = false; 7694 } 7695 7696 if (!enable_preemption_timer) { 7697 kvm_x86_ops->set_hv_timer = NULL; 7698 kvm_x86_ops->cancel_hv_timer = NULL; 7699 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7700 } 7701 7702 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7703 7704 kvm_mce_cap_supported |= MCG_LMCE_P; 7705 7706 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7707 return -EINVAL; 7708 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7709 pt_mode = PT_MODE_SYSTEM; 7710 7711 if (nested) { 7712 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7713 vmx_capability.ept, enable_apicv); 7714 7715 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7716 if (r) 7717 return r; 7718 } 7719 7720 r = alloc_kvm_area(); 7721 if (r) 7722 nested_vmx_hardware_unsetup(); 7723 return r; 7724 } 7725 7726 static __exit void hardware_unsetup(void) 7727 { 7728 if (nested) 7729 nested_vmx_hardware_unsetup(); 7730 7731 free_kvm_area(); 7732 } 7733 7734 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7735 .cpu_has_kvm_support = cpu_has_kvm_support, 7736 .disabled_by_bios = vmx_disabled_by_bios, 7737 .hardware_setup = hardware_setup, 7738 .hardware_unsetup = hardware_unsetup, 7739 .check_processor_compatibility = vmx_check_processor_compat, 7740 .hardware_enable = hardware_enable, 7741 .hardware_disable = hardware_disable, 7742 .cpu_has_accelerated_tpr = report_flexpriority, 7743 .has_emulated_msr = vmx_has_emulated_msr, 7744 7745 .vm_init = vmx_vm_init, 7746 .vm_alloc = vmx_vm_alloc, 7747 .vm_free = vmx_vm_free, 7748 7749 .vcpu_create = vmx_create_vcpu, 7750 .vcpu_free = vmx_free_vcpu, 7751 .vcpu_reset = vmx_vcpu_reset, 7752 7753 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7754 .vcpu_load = vmx_vcpu_load, 7755 .vcpu_put = vmx_vcpu_put, 7756 7757 .update_bp_intercept = update_exception_bitmap, 7758 .get_msr_feature = vmx_get_msr_feature, 7759 .get_msr = vmx_get_msr, 7760 .set_msr = vmx_set_msr, 7761 .get_segment_base = vmx_get_segment_base, 7762 .get_segment = vmx_get_segment, 7763 .set_segment = vmx_set_segment, 7764 .get_cpl = vmx_get_cpl, 7765 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7766 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7767 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7768 .set_cr0 = vmx_set_cr0, 7769 .set_cr3 = vmx_set_cr3, 7770 .set_cr4 = vmx_set_cr4, 7771 .set_efer = vmx_set_efer, 7772 .get_idt = vmx_get_idt, 7773 .set_idt = vmx_set_idt, 7774 .get_gdt = vmx_get_gdt, 7775 .set_gdt = vmx_set_gdt, 7776 .get_dr6 = vmx_get_dr6, 7777 .set_dr6 = vmx_set_dr6, 7778 .set_dr7 = vmx_set_dr7, 7779 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7780 .cache_reg = vmx_cache_reg, 7781 .get_rflags = vmx_get_rflags, 7782 .set_rflags = vmx_set_rflags, 7783 7784 .tlb_flush = vmx_flush_tlb, 7785 .tlb_flush_gva = vmx_flush_tlb_gva, 7786 7787 .run = vmx_vcpu_run, 7788 .handle_exit = vmx_handle_exit, 7789 .skip_emulated_instruction = skip_emulated_instruction, 7790 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7791 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7792 .patch_hypercall = vmx_patch_hypercall, 7793 .set_irq = vmx_inject_irq, 7794 .set_nmi = vmx_inject_nmi, 7795 .queue_exception = vmx_queue_exception, 7796 .cancel_injection = vmx_cancel_injection, 7797 .interrupt_allowed = vmx_interrupt_allowed, 7798 .nmi_allowed = vmx_nmi_allowed, 7799 .get_nmi_mask = vmx_get_nmi_mask, 7800 .set_nmi_mask = vmx_set_nmi_mask, 7801 .enable_nmi_window = enable_nmi_window, 7802 .enable_irq_window = enable_irq_window, 7803 .update_cr8_intercept = update_cr8_intercept, 7804 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7805 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7806 .get_enable_apicv = vmx_get_enable_apicv, 7807 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7808 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7809 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7810 .hwapic_irr_update = vmx_hwapic_irr_update, 7811 .hwapic_isr_update = vmx_hwapic_isr_update, 7812 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7813 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7814 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7815 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7816 7817 .set_tss_addr = vmx_set_tss_addr, 7818 .set_identity_map_addr = vmx_set_identity_map_addr, 7819 .get_tdp_level = get_ept_level, 7820 .get_mt_mask = vmx_get_mt_mask, 7821 7822 .get_exit_info = vmx_get_exit_info, 7823 7824 .get_lpage_level = vmx_get_lpage_level, 7825 7826 .cpuid_update = vmx_cpuid_update, 7827 7828 .rdtscp_supported = vmx_rdtscp_supported, 7829 .invpcid_supported = vmx_invpcid_supported, 7830 7831 .set_supported_cpuid = vmx_set_supported_cpuid, 7832 7833 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7834 7835 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7836 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7837 7838 .set_tdp_cr3 = vmx_set_cr3, 7839 7840 .check_intercept = vmx_check_intercept, 7841 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7842 .mpx_supported = vmx_mpx_supported, 7843 .xsaves_supported = vmx_xsaves_supported, 7844 .umip_emulated = vmx_umip_emulated, 7845 .pt_supported = vmx_pt_supported, 7846 7847 .request_immediate_exit = vmx_request_immediate_exit, 7848 7849 .sched_in = vmx_sched_in, 7850 7851 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7852 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7853 .flush_log_dirty = vmx_flush_log_dirty, 7854 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7855 .write_log_dirty = vmx_write_pml_buffer, 7856 7857 .pre_block = vmx_pre_block, 7858 .post_block = vmx_post_block, 7859 7860 .pmu_ops = &intel_pmu_ops, 7861 7862 .update_pi_irte = vmx_update_pi_irte, 7863 7864 #ifdef CONFIG_X86_64 7865 .set_hv_timer = vmx_set_hv_timer, 7866 .cancel_hv_timer = vmx_cancel_hv_timer, 7867 #endif 7868 7869 .setup_mce = vmx_setup_mce, 7870 7871 .smi_allowed = vmx_smi_allowed, 7872 .pre_enter_smm = vmx_pre_enter_smm, 7873 .pre_leave_smm = vmx_pre_leave_smm, 7874 .enable_smi_window = enable_smi_window, 7875 7876 .check_nested_events = NULL, 7877 .get_nested_state = NULL, 7878 .set_nested_state = NULL, 7879 .get_vmcs12_pages = NULL, 7880 .nested_enable_evmcs = NULL, 7881 .nested_get_evmcs_version = NULL, 7882 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7883 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7884 }; 7885 7886 static void vmx_cleanup_l1d_flush(void) 7887 { 7888 if (vmx_l1d_flush_pages) { 7889 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7890 vmx_l1d_flush_pages = NULL; 7891 } 7892 /* Restore state so sysfs ignores VMX */ 7893 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 7894 } 7895 7896 static void vmx_exit(void) 7897 { 7898 #ifdef CONFIG_KEXEC_CORE 7899 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 7900 synchronize_rcu(); 7901 #endif 7902 7903 kvm_exit(); 7904 7905 #if IS_ENABLED(CONFIG_HYPERV) 7906 if (static_branch_unlikely(&enable_evmcs)) { 7907 int cpu; 7908 struct hv_vp_assist_page *vp_ap; 7909 /* 7910 * Reset everything to support using non-enlightened VMCS 7911 * access later (e.g. when we reload the module with 7912 * enlightened_vmcs=0) 7913 */ 7914 for_each_online_cpu(cpu) { 7915 vp_ap = hv_get_vp_assist_page(cpu); 7916 7917 if (!vp_ap) 7918 continue; 7919 7920 vp_ap->nested_control.features.directhypercall = 0; 7921 vp_ap->current_nested_vmcs = 0; 7922 vp_ap->enlighten_vmentry = 0; 7923 } 7924 7925 static_branch_disable(&enable_evmcs); 7926 } 7927 #endif 7928 vmx_cleanup_l1d_flush(); 7929 } 7930 module_exit(vmx_exit); 7931 7932 static int __init vmx_init(void) 7933 { 7934 int r; 7935 7936 #if IS_ENABLED(CONFIG_HYPERV) 7937 /* 7938 * Enlightened VMCS usage should be recommended and the host needs 7939 * to support eVMCS v1 or above. We can also disable eVMCS support 7940 * with module parameter. 7941 */ 7942 if (enlightened_vmcs && 7943 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 7944 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 7945 KVM_EVMCS_VERSION) { 7946 int cpu; 7947 7948 /* Check that we have assist pages on all online CPUs */ 7949 for_each_online_cpu(cpu) { 7950 if (!hv_get_vp_assist_page(cpu)) { 7951 enlightened_vmcs = false; 7952 break; 7953 } 7954 } 7955 7956 if (enlightened_vmcs) { 7957 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 7958 static_branch_enable(&enable_evmcs); 7959 } 7960 7961 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 7962 vmx_x86_ops.enable_direct_tlbflush 7963 = hv_enable_direct_tlbflush; 7964 7965 } else { 7966 enlightened_vmcs = false; 7967 } 7968 #endif 7969 7970 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 7971 __alignof__(struct vcpu_vmx), THIS_MODULE); 7972 if (r) 7973 return r; 7974 7975 /* 7976 * Must be called after kvm_init() so enable_ept is properly set 7977 * up. Hand the parameter mitigation value in which was stored in 7978 * the pre module init parser. If no parameter was given, it will 7979 * contain 'auto' which will be turned into the default 'cond' 7980 * mitigation mode. 7981 */ 7982 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 7983 if (r) { 7984 vmx_exit(); 7985 return r; 7986 } 7987 7988 #ifdef CONFIG_KEXEC_CORE 7989 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 7990 crash_vmclear_local_loaded_vmcss); 7991 #endif 7992 vmx_check_vmcs12_offsets(); 7993 7994 return 0; 7995 } 7996 module_init(vmx_init); 7997