1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/highmem.h> 17 #include <linux/hrtimer.h> 18 #include <linux/kernel.h> 19 #include <linux/kvm_host.h> 20 #include <linux/module.h> 21 #include <linux/moduleparam.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/mm.h> 24 #include <linux/objtool.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 #include <linux/entry-kvm.h> 31 32 #include <asm/apic.h> 33 #include <asm/asm.h> 34 #include <asm/cpu.h> 35 #include <asm/cpu_device_id.h> 36 #include <asm/debugreg.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/io.h> 40 #include <asm/irq_remapping.h> 41 #include <asm/kexec.h> 42 #include <asm/perf_event.h> 43 #include <asm/mce.h> 44 #include <asm/mmu_context.h> 45 #include <asm/mshyperv.h> 46 #include <asm/mwait.h> 47 #include <asm/spec-ctrl.h> 48 #include <asm/virtext.h> 49 #include <asm/vmx.h> 50 51 #include "capabilities.h" 52 #include "cpuid.h" 53 #include "evmcs.h" 54 #include "irq.h" 55 #include "kvm_cache_regs.h" 56 #include "lapic.h" 57 #include "mmu.h" 58 #include "nested.h" 59 #include "pmu.h" 60 #include "trace.h" 61 #include "vmcs.h" 62 #include "vmcs12.h" 63 #include "vmx.h" 64 #include "x86.h" 65 66 MODULE_AUTHOR("Qumranet"); 67 MODULE_LICENSE("GPL"); 68 69 #ifdef MODULE 70 static const struct x86_cpu_id vmx_cpu_id[] = { 71 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL), 72 {} 73 }; 74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 75 #endif 76 77 bool __read_mostly enable_vpid = 1; 78 module_param_named(vpid, enable_vpid, bool, 0444); 79 80 static bool __read_mostly enable_vnmi = 1; 81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 82 83 bool __read_mostly flexpriority_enabled = 1; 84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 85 86 bool __read_mostly enable_ept = 1; 87 module_param_named(ept, enable_ept, bool, S_IRUGO); 88 89 bool __read_mostly enable_unrestricted_guest = 1; 90 module_param_named(unrestricted_guest, 91 enable_unrestricted_guest, bool, S_IRUGO); 92 93 bool __read_mostly enable_ept_ad_bits = 1; 94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 95 96 static bool __read_mostly emulate_invalid_guest_state = true; 97 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 98 99 static bool __read_mostly fasteoi = 1; 100 module_param(fasteoi, bool, S_IRUGO); 101 102 bool __read_mostly enable_apicv = 1; 103 module_param(enable_apicv, bool, S_IRUGO); 104 105 /* 106 * If nested=1, nested virtualization is supported, i.e., guests may use 107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 108 * use VMX instructions. 109 */ 110 static bool __read_mostly nested = 1; 111 module_param(nested, bool, S_IRUGO); 112 113 bool __read_mostly enable_pml = 1; 114 module_param_named(pml, enable_pml, bool, S_IRUGO); 115 116 static bool __read_mostly dump_invalid_vmcs = 0; 117 module_param(dump_invalid_vmcs, bool, 0644); 118 119 #define MSR_BITMAP_MODE_X2APIC 1 120 #define MSR_BITMAP_MODE_X2APIC_APICV 2 121 122 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 123 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 125 static int __read_mostly cpu_preemption_timer_multi; 126 static bool __read_mostly enable_preemption_timer = 1; 127 #ifdef CONFIG_X86_64 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 129 #endif 130 131 extern bool __read_mostly allow_smaller_maxphyaddr; 132 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO); 133 134 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 135 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 136 #define KVM_VM_CR0_ALWAYS_ON \ 137 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 138 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 139 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 143 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 145 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 147 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 148 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 149 RTIT_STATUS_BYTECNT)) 150 151 /* 152 * List of MSRs that can be directly passed to the guest. 153 * In addition to these x2apic and PT MSRs are handled specially. 154 */ 155 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = { 156 MSR_IA32_SPEC_CTRL, 157 MSR_IA32_PRED_CMD, 158 MSR_IA32_TSC, 159 MSR_FS_BASE, 160 MSR_GS_BASE, 161 MSR_KERNEL_GS_BASE, 162 MSR_IA32_SYSENTER_CS, 163 MSR_IA32_SYSENTER_ESP, 164 MSR_IA32_SYSENTER_EIP, 165 MSR_CORE_C1_RES, 166 MSR_CORE_C3_RESIDENCY, 167 MSR_CORE_C6_RESIDENCY, 168 MSR_CORE_C7_RESIDENCY, 169 }; 170 171 /* 172 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 173 * ple_gap: upper bound on the amount of time between two successive 174 * executions of PAUSE in a loop. Also indicate if ple enabled. 175 * According to test, this time is usually smaller than 128 cycles. 176 * ple_window: upper bound on the amount of time a guest is allowed to execute 177 * in a PAUSE loop. Tests indicate that most spinlocks are held for 178 * less than 2^12 cycles 179 * Time is measured based on a counter that runs at the same rate as the TSC, 180 * refer SDM volume 3b section 21.6.13 & 22.1.3. 181 */ 182 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 183 module_param(ple_gap, uint, 0444); 184 185 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 186 module_param(ple_window, uint, 0444); 187 188 /* Default doubles per-vcpu window every exit. */ 189 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 190 module_param(ple_window_grow, uint, 0444); 191 192 /* Default resets per-vcpu window every exit to ple_window. */ 193 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 194 module_param(ple_window_shrink, uint, 0444); 195 196 /* Default is to compute the maximum so we can never overflow. */ 197 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 198 module_param(ple_window_max, uint, 0444); 199 200 /* Default is SYSTEM mode, 1 for host-guest mode */ 201 int __read_mostly pt_mode = PT_MODE_SYSTEM; 202 module_param(pt_mode, int, S_IRUGO); 203 204 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 205 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 206 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 207 208 /* Storage for pre module init parameter parsing */ 209 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 210 211 static const struct { 212 const char *option; 213 bool for_parse; 214 } vmentry_l1d_param[] = { 215 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 216 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 217 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 218 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 219 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 220 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 221 }; 222 223 #define L1D_CACHE_ORDER 4 224 static void *vmx_l1d_flush_pages; 225 226 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 227 { 228 struct page *page; 229 unsigned int i; 230 231 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 232 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 233 return 0; 234 } 235 236 if (!enable_ept) { 237 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 238 return 0; 239 } 240 241 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 242 u64 msr; 243 244 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 245 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 246 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 247 return 0; 248 } 249 } 250 251 /* If set to auto use the default l1tf mitigation method */ 252 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 253 switch (l1tf_mitigation) { 254 case L1TF_MITIGATION_OFF: 255 l1tf = VMENTER_L1D_FLUSH_NEVER; 256 break; 257 case L1TF_MITIGATION_FLUSH_NOWARN: 258 case L1TF_MITIGATION_FLUSH: 259 case L1TF_MITIGATION_FLUSH_NOSMT: 260 l1tf = VMENTER_L1D_FLUSH_COND; 261 break; 262 case L1TF_MITIGATION_FULL: 263 case L1TF_MITIGATION_FULL_FORCE: 264 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 265 break; 266 } 267 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 268 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 269 } 270 271 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 272 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 273 /* 274 * This allocation for vmx_l1d_flush_pages is not tied to a VM 275 * lifetime and so should not be charged to a memcg. 276 */ 277 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 278 if (!page) 279 return -ENOMEM; 280 vmx_l1d_flush_pages = page_address(page); 281 282 /* 283 * Initialize each page with a different pattern in 284 * order to protect against KSM in the nested 285 * virtualization case. 286 */ 287 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 288 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 289 PAGE_SIZE); 290 } 291 } 292 293 l1tf_vmx_mitigation = l1tf; 294 295 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 296 static_branch_enable(&vmx_l1d_should_flush); 297 else 298 static_branch_disable(&vmx_l1d_should_flush); 299 300 if (l1tf == VMENTER_L1D_FLUSH_COND) 301 static_branch_enable(&vmx_l1d_flush_cond); 302 else 303 static_branch_disable(&vmx_l1d_flush_cond); 304 return 0; 305 } 306 307 static int vmentry_l1d_flush_parse(const char *s) 308 { 309 unsigned int i; 310 311 if (s) { 312 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 313 if (vmentry_l1d_param[i].for_parse && 314 sysfs_streq(s, vmentry_l1d_param[i].option)) 315 return i; 316 } 317 } 318 return -EINVAL; 319 } 320 321 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 322 { 323 int l1tf, ret; 324 325 l1tf = vmentry_l1d_flush_parse(s); 326 if (l1tf < 0) 327 return l1tf; 328 329 if (!boot_cpu_has(X86_BUG_L1TF)) 330 return 0; 331 332 /* 333 * Has vmx_init() run already? If not then this is the pre init 334 * parameter parsing. In that case just store the value and let 335 * vmx_init() do the proper setup after enable_ept has been 336 * established. 337 */ 338 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 339 vmentry_l1d_flush_param = l1tf; 340 return 0; 341 } 342 343 mutex_lock(&vmx_l1d_flush_mutex); 344 ret = vmx_setup_l1d_flush(l1tf); 345 mutex_unlock(&vmx_l1d_flush_mutex); 346 return ret; 347 } 348 349 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 350 { 351 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 352 return sprintf(s, "???\n"); 353 354 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 355 } 356 357 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 358 .set = vmentry_l1d_flush_set, 359 .get = vmentry_l1d_flush_get, 360 }; 361 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 362 363 static u32 vmx_segment_access_rights(struct kvm_segment *var); 364 static __always_inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 365 u32 msr, int type); 366 367 void vmx_vmexit(void); 368 369 #define vmx_insn_failed(fmt...) \ 370 do { \ 371 WARN_ONCE(1, fmt); \ 372 pr_warn_ratelimited(fmt); \ 373 } while (0) 374 375 asmlinkage void vmread_error(unsigned long field, bool fault) 376 { 377 if (fault) 378 kvm_spurious_fault(); 379 else 380 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 381 } 382 383 noinline void vmwrite_error(unsigned long field, unsigned long value) 384 { 385 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 386 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 387 } 388 389 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 390 { 391 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 392 } 393 394 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 395 { 396 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 397 } 398 399 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 400 { 401 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 402 ext, vpid, gva); 403 } 404 405 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 406 { 407 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 408 ext, eptp, gpa); 409 } 410 411 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 412 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 413 /* 414 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 415 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 416 */ 417 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 418 419 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 420 static DEFINE_SPINLOCK(vmx_vpid_lock); 421 422 struct vmcs_config vmcs_config; 423 struct vmx_capability vmx_capability; 424 425 #define VMX_SEGMENT_FIELD(seg) \ 426 [VCPU_SREG_##seg] = { \ 427 .selector = GUEST_##seg##_SELECTOR, \ 428 .base = GUEST_##seg##_BASE, \ 429 .limit = GUEST_##seg##_LIMIT, \ 430 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 431 } 432 433 static const struct kvm_vmx_segment_field { 434 unsigned selector; 435 unsigned base; 436 unsigned limit; 437 unsigned ar_bytes; 438 } kvm_vmx_segment_fields[] = { 439 VMX_SEGMENT_FIELD(CS), 440 VMX_SEGMENT_FIELD(DS), 441 VMX_SEGMENT_FIELD(ES), 442 VMX_SEGMENT_FIELD(FS), 443 VMX_SEGMENT_FIELD(GS), 444 VMX_SEGMENT_FIELD(SS), 445 VMX_SEGMENT_FIELD(TR), 446 VMX_SEGMENT_FIELD(LDTR), 447 }; 448 449 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 450 { 451 vmx->segment_cache.bitmask = 0; 452 } 453 454 static unsigned long host_idt_base; 455 456 /* 457 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 458 * will emulate SYSCALL in legacy mode if the vendor string in guest 459 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 460 * support this emulation, IA32_STAR must always be included in 461 * vmx_uret_msrs_list[], even in i386 builds. 462 */ 463 static const u32 vmx_uret_msrs_list[] = { 464 #ifdef CONFIG_X86_64 465 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 466 #endif 467 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 468 MSR_IA32_TSX_CTRL, 469 }; 470 471 #if IS_ENABLED(CONFIG_HYPERV) 472 static bool __read_mostly enlightened_vmcs = true; 473 module_param(enlightened_vmcs, bool, 0444); 474 475 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 476 static void check_ept_pointer_match(struct kvm *kvm) 477 { 478 struct kvm_vcpu *vcpu; 479 u64 tmp_eptp = INVALID_PAGE; 480 int i; 481 482 kvm_for_each_vcpu(i, vcpu, kvm) { 483 if (!VALID_PAGE(tmp_eptp)) { 484 tmp_eptp = to_vmx(vcpu)->ept_pointer; 485 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 486 to_kvm_vmx(kvm)->ept_pointers_match 487 = EPT_POINTERS_MISMATCH; 488 return; 489 } 490 } 491 492 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 493 } 494 495 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 496 void *data) 497 { 498 struct kvm_tlb_range *range = data; 499 500 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 501 range->pages); 502 } 503 504 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 505 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 506 { 507 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 508 509 /* 510 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 511 * of the base of EPT PML4 table, strip off EPT configuration 512 * information. 513 */ 514 if (range) 515 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 516 kvm_fill_hv_flush_list_func, (void *)range); 517 else 518 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 519 } 520 521 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 522 struct kvm_tlb_range *range) 523 { 524 struct kvm_vcpu *vcpu; 525 int ret = 0, i; 526 527 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 528 529 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 530 check_ept_pointer_match(kvm); 531 532 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 533 kvm_for_each_vcpu(i, vcpu, kvm) { 534 /* If ept_pointer is invalid pointer, bypass flush request. */ 535 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 536 ret |= __hv_remote_flush_tlb_with_range( 537 kvm, vcpu, range); 538 } 539 } else { 540 ret = __hv_remote_flush_tlb_with_range(kvm, 541 kvm_get_vcpu(kvm, 0), range); 542 } 543 544 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 545 return ret; 546 } 547 static int hv_remote_flush_tlb(struct kvm *kvm) 548 { 549 return hv_remote_flush_tlb_with_range(kvm, NULL); 550 } 551 552 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 553 { 554 struct hv_enlightened_vmcs *evmcs; 555 struct hv_partition_assist_pg **p_hv_pa_pg = 556 &vcpu->kvm->arch.hyperv.hv_pa_pg; 557 /* 558 * Synthetic VM-Exit is not enabled in current code and so All 559 * evmcs in singe VM shares same assist page. 560 */ 561 if (!*p_hv_pa_pg) 562 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 563 564 if (!*p_hv_pa_pg) 565 return -ENOMEM; 566 567 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 568 569 evmcs->partition_assist_page = 570 __pa(*p_hv_pa_pg); 571 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 572 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 573 574 return 0; 575 } 576 577 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 578 579 /* 580 * Comment's format: document - errata name - stepping - processor name. 581 * Refer from 582 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 583 */ 584 static u32 vmx_preemption_cpu_tfms[] = { 585 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 586 0x000206E6, 587 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 588 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 589 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 590 0x00020652, 591 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 592 0x00020655, 593 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 594 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 595 /* 596 * 320767.pdf - AAP86 - B1 - 597 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 598 */ 599 0x000106E5, 600 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 601 0x000106A0, 602 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 603 0x000106A1, 604 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 605 0x000106A4, 606 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 607 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 608 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 609 0x000106A5, 610 /* Xeon E3-1220 V2 */ 611 0x000306A8, 612 }; 613 614 static inline bool cpu_has_broken_vmx_preemption_timer(void) 615 { 616 u32 eax = cpuid_eax(0x00000001), i; 617 618 /* Clear the reserved bits */ 619 eax &= ~(0x3U << 14 | 0xfU << 28); 620 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 621 if (eax == vmx_preemption_cpu_tfms[i]) 622 return true; 623 624 return false; 625 } 626 627 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 628 { 629 return flexpriority_enabled && lapic_in_kernel(vcpu); 630 } 631 632 static inline bool report_flexpriority(void) 633 { 634 return flexpriority_enabled; 635 } 636 637 static int possible_passthrough_msr_slot(u32 msr) 638 { 639 u32 i; 640 641 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) 642 if (vmx_possible_passthrough_msrs[i] == msr) 643 return i; 644 645 return -ENOENT; 646 } 647 648 static bool is_valid_passthrough_msr(u32 msr) 649 { 650 bool r; 651 652 switch (msr) { 653 case 0x800 ... 0x8ff: 654 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */ 655 return true; 656 case MSR_IA32_RTIT_STATUS: 657 case MSR_IA32_RTIT_OUTPUT_BASE: 658 case MSR_IA32_RTIT_OUTPUT_MASK: 659 case MSR_IA32_RTIT_CR3_MATCH: 660 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 661 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */ 662 return true; 663 } 664 665 r = possible_passthrough_msr_slot(msr) != -ENOENT; 666 667 WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr); 668 669 return r; 670 } 671 672 static inline int __vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr) 673 { 674 int i; 675 676 for (i = 0; i < vmx->nr_uret_msrs; ++i) 677 if (vmx_uret_msrs_list[vmx->guest_uret_msrs[i].slot] == msr) 678 return i; 679 return -1; 680 } 681 682 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr) 683 { 684 int i; 685 686 i = __vmx_find_uret_msr(vmx, msr); 687 if (i >= 0) 688 return &vmx->guest_uret_msrs[i]; 689 return NULL; 690 } 691 692 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx, 693 struct vmx_uret_msr *msr, u64 data) 694 { 695 int ret = 0; 696 697 u64 old_msr_data = msr->data; 698 msr->data = data; 699 if (msr - vmx->guest_uret_msrs < vmx->nr_active_uret_msrs) { 700 preempt_disable(); 701 ret = kvm_set_user_return_msr(msr->slot, msr->data, msr->mask); 702 preempt_enable(); 703 if (ret) 704 msr->data = old_msr_data; 705 } 706 return ret; 707 } 708 709 #ifdef CONFIG_KEXEC_CORE 710 static void crash_vmclear_local_loaded_vmcss(void) 711 { 712 int cpu = raw_smp_processor_id(); 713 struct loaded_vmcs *v; 714 715 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 716 loaded_vmcss_on_cpu_link) 717 vmcs_clear(v->vmcs); 718 } 719 #endif /* CONFIG_KEXEC_CORE */ 720 721 static void __loaded_vmcs_clear(void *arg) 722 { 723 struct loaded_vmcs *loaded_vmcs = arg; 724 int cpu = raw_smp_processor_id(); 725 726 if (loaded_vmcs->cpu != cpu) 727 return; /* vcpu migration can race with cpu offline */ 728 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 729 per_cpu(current_vmcs, cpu) = NULL; 730 731 vmcs_clear(loaded_vmcs->vmcs); 732 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 733 vmcs_clear(loaded_vmcs->shadow_vmcs); 734 735 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 736 737 /* 738 * Ensure all writes to loaded_vmcs, including deleting it from its 739 * current percpu list, complete before setting loaded_vmcs->vcpu to 740 * -1, otherwise a different cpu can see vcpu == -1 first and add 741 * loaded_vmcs to its percpu list before it's deleted from this cpu's 742 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs(). 743 */ 744 smp_wmb(); 745 746 loaded_vmcs->cpu = -1; 747 loaded_vmcs->launched = 0; 748 } 749 750 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 751 { 752 int cpu = loaded_vmcs->cpu; 753 754 if (cpu != -1) 755 smp_call_function_single(cpu, 756 __loaded_vmcs_clear, loaded_vmcs, 1); 757 } 758 759 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 760 unsigned field) 761 { 762 bool ret; 763 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 764 765 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 766 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 767 vmx->segment_cache.bitmask = 0; 768 } 769 ret = vmx->segment_cache.bitmask & mask; 770 vmx->segment_cache.bitmask |= mask; 771 return ret; 772 } 773 774 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 775 { 776 u16 *p = &vmx->segment_cache.seg[seg].selector; 777 778 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 779 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 780 return *p; 781 } 782 783 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 784 { 785 ulong *p = &vmx->segment_cache.seg[seg].base; 786 787 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 788 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 789 return *p; 790 } 791 792 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 793 { 794 u32 *p = &vmx->segment_cache.seg[seg].limit; 795 796 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 797 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 798 return *p; 799 } 800 801 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 802 { 803 u32 *p = &vmx->segment_cache.seg[seg].ar; 804 805 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 806 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 807 return *p; 808 } 809 810 void update_exception_bitmap(struct kvm_vcpu *vcpu) 811 { 812 u32 eb; 813 814 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 815 (1u << DB_VECTOR) | (1u << AC_VECTOR); 816 /* 817 * Guest access to VMware backdoor ports could legitimately 818 * trigger #GP because of TSS I/O permission bitmap. 819 * We intercept those #GP and allow access to them anyway 820 * as VMware does. 821 */ 822 if (enable_vmware_backdoor) 823 eb |= (1u << GP_VECTOR); 824 if ((vcpu->guest_debug & 825 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 826 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 827 eb |= 1u << BP_VECTOR; 828 if (to_vmx(vcpu)->rmode.vm86_active) 829 eb = ~0; 830 if (!vmx_need_pf_intercept(vcpu)) 831 eb &= ~(1u << PF_VECTOR); 832 833 /* When we are running a nested L2 guest and L1 specified for it a 834 * certain exception bitmap, we must trap the same exceptions and pass 835 * them to L1. When running L2, we will only handle the exceptions 836 * specified above if L1 did not want them. 837 */ 838 if (is_guest_mode(vcpu)) 839 eb |= get_vmcs12(vcpu)->exception_bitmap; 840 else { 841 /* 842 * If EPT is enabled, #PF is only trapped if MAXPHYADDR is mismatched 843 * between guest and host. In that case we only care about present 844 * faults. For vmcs02, however, PFEC_MASK and PFEC_MATCH are set in 845 * prepare_vmcs02_rare. 846 */ 847 bool selective_pf_trap = enable_ept && (eb & (1u << PF_VECTOR)); 848 int mask = selective_pf_trap ? PFERR_PRESENT_MASK : 0; 849 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask); 850 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, mask); 851 } 852 853 vmcs_write32(EXCEPTION_BITMAP, eb); 854 } 855 856 /* 857 * Check if MSR is intercepted for currently loaded MSR bitmap. 858 */ 859 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 860 { 861 unsigned long *msr_bitmap; 862 int f = sizeof(unsigned long); 863 864 if (!cpu_has_vmx_msr_bitmap()) 865 return true; 866 867 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 868 869 if (msr <= 0x1fff) { 870 return !!test_bit(msr, msr_bitmap + 0x800 / f); 871 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 872 msr &= 0x1fff; 873 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 874 } 875 876 return true; 877 } 878 879 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 880 unsigned long entry, unsigned long exit) 881 { 882 vm_entry_controls_clearbit(vmx, entry); 883 vm_exit_controls_clearbit(vmx, exit); 884 } 885 886 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr) 887 { 888 unsigned int i; 889 890 for (i = 0; i < m->nr; ++i) { 891 if (m->val[i].index == msr) 892 return i; 893 } 894 return -ENOENT; 895 } 896 897 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 898 { 899 int i; 900 struct msr_autoload *m = &vmx->msr_autoload; 901 902 switch (msr) { 903 case MSR_EFER: 904 if (cpu_has_load_ia32_efer()) { 905 clear_atomic_switch_msr_special(vmx, 906 VM_ENTRY_LOAD_IA32_EFER, 907 VM_EXIT_LOAD_IA32_EFER); 908 return; 909 } 910 break; 911 case MSR_CORE_PERF_GLOBAL_CTRL: 912 if (cpu_has_load_perf_global_ctrl()) { 913 clear_atomic_switch_msr_special(vmx, 914 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 915 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 916 return; 917 } 918 break; 919 } 920 i = vmx_find_loadstore_msr_slot(&m->guest, msr); 921 if (i < 0) 922 goto skip_guest; 923 --m->guest.nr; 924 m->guest.val[i] = m->guest.val[m->guest.nr]; 925 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 926 927 skip_guest: 928 i = vmx_find_loadstore_msr_slot(&m->host, msr); 929 if (i < 0) 930 return; 931 932 --m->host.nr; 933 m->host.val[i] = m->host.val[m->host.nr]; 934 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 935 } 936 937 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 938 unsigned long entry, unsigned long exit, 939 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 940 u64 guest_val, u64 host_val) 941 { 942 vmcs_write64(guest_val_vmcs, guest_val); 943 if (host_val_vmcs != HOST_IA32_EFER) 944 vmcs_write64(host_val_vmcs, host_val); 945 vm_entry_controls_setbit(vmx, entry); 946 vm_exit_controls_setbit(vmx, exit); 947 } 948 949 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 950 u64 guest_val, u64 host_val, bool entry_only) 951 { 952 int i, j = 0; 953 struct msr_autoload *m = &vmx->msr_autoload; 954 955 switch (msr) { 956 case MSR_EFER: 957 if (cpu_has_load_ia32_efer()) { 958 add_atomic_switch_msr_special(vmx, 959 VM_ENTRY_LOAD_IA32_EFER, 960 VM_EXIT_LOAD_IA32_EFER, 961 GUEST_IA32_EFER, 962 HOST_IA32_EFER, 963 guest_val, host_val); 964 return; 965 } 966 break; 967 case MSR_CORE_PERF_GLOBAL_CTRL: 968 if (cpu_has_load_perf_global_ctrl()) { 969 add_atomic_switch_msr_special(vmx, 970 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 971 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 972 GUEST_IA32_PERF_GLOBAL_CTRL, 973 HOST_IA32_PERF_GLOBAL_CTRL, 974 guest_val, host_val); 975 return; 976 } 977 break; 978 case MSR_IA32_PEBS_ENABLE: 979 /* PEBS needs a quiescent period after being disabled (to write 980 * a record). Disabling PEBS through VMX MSR swapping doesn't 981 * provide that period, so a CPU could write host's record into 982 * guest's memory. 983 */ 984 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 985 } 986 987 i = vmx_find_loadstore_msr_slot(&m->guest, msr); 988 if (!entry_only) 989 j = vmx_find_loadstore_msr_slot(&m->host, msr); 990 991 if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) || 992 (j < 0 && m->host.nr == MAX_NR_LOADSTORE_MSRS)) { 993 printk_once(KERN_WARNING "Not enough msr switch entries. " 994 "Can't add msr %x\n", msr); 995 return; 996 } 997 if (i < 0) { 998 i = m->guest.nr++; 999 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 1000 } 1001 m->guest.val[i].index = msr; 1002 m->guest.val[i].value = guest_val; 1003 1004 if (entry_only) 1005 return; 1006 1007 if (j < 0) { 1008 j = m->host.nr++; 1009 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 1010 } 1011 m->host.val[j].index = msr; 1012 m->host.val[j].value = host_val; 1013 } 1014 1015 static bool update_transition_efer(struct vcpu_vmx *vmx) 1016 { 1017 u64 guest_efer = vmx->vcpu.arch.efer; 1018 u64 ignore_bits = 0; 1019 int i; 1020 1021 /* Shadow paging assumes NX to be available. */ 1022 if (!enable_ept) 1023 guest_efer |= EFER_NX; 1024 1025 /* 1026 * LMA and LME handled by hardware; SCE meaningless outside long mode. 1027 */ 1028 ignore_bits |= EFER_SCE; 1029 #ifdef CONFIG_X86_64 1030 ignore_bits |= EFER_LMA | EFER_LME; 1031 /* SCE is meaningful only in long mode on Intel */ 1032 if (guest_efer & EFER_LMA) 1033 ignore_bits &= ~(u64)EFER_SCE; 1034 #endif 1035 1036 /* 1037 * On EPT, we can't emulate NX, so we must switch EFER atomically. 1038 * On CPUs that support "load IA32_EFER", always switch EFER 1039 * atomically, since it's faster than switching it manually. 1040 */ 1041 if (cpu_has_load_ia32_efer() || 1042 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 1043 if (!(guest_efer & EFER_LMA)) 1044 guest_efer &= ~EFER_LME; 1045 if (guest_efer != host_efer) 1046 add_atomic_switch_msr(vmx, MSR_EFER, 1047 guest_efer, host_efer, false); 1048 else 1049 clear_atomic_switch_msr(vmx, MSR_EFER); 1050 return false; 1051 } 1052 1053 i = __vmx_find_uret_msr(vmx, MSR_EFER); 1054 if (i < 0) 1055 return false; 1056 1057 clear_atomic_switch_msr(vmx, MSR_EFER); 1058 1059 guest_efer &= ~ignore_bits; 1060 guest_efer |= host_efer & ignore_bits; 1061 1062 vmx->guest_uret_msrs[i].data = guest_efer; 1063 vmx->guest_uret_msrs[i].mask = ~ignore_bits; 1064 1065 return true; 1066 } 1067 1068 #ifdef CONFIG_X86_32 1069 /* 1070 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1071 * VMCS rather than the segment table. KVM uses this helper to figure 1072 * out the current bases to poke them into the VMCS before entry. 1073 */ 1074 static unsigned long segment_base(u16 selector) 1075 { 1076 struct desc_struct *table; 1077 unsigned long v; 1078 1079 if (!(selector & ~SEGMENT_RPL_MASK)) 1080 return 0; 1081 1082 table = get_current_gdt_ro(); 1083 1084 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1085 u16 ldt_selector = kvm_read_ldt(); 1086 1087 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1088 return 0; 1089 1090 table = (struct desc_struct *)segment_base(ldt_selector); 1091 } 1092 v = get_desc_base(&table[selector >> 3]); 1093 return v; 1094 } 1095 #endif 1096 1097 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1098 { 1099 return vmx_pt_mode_is_host_guest() && 1100 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1101 } 1102 1103 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base) 1104 { 1105 /* The base must be 128-byte aligned and a legal physical address. */ 1106 return !kvm_vcpu_is_illegal_gpa(vcpu, base) && !(base & 0x7f); 1107 } 1108 1109 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1110 { 1111 u32 i; 1112 1113 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1114 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1115 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1116 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1117 for (i = 0; i < addr_range; i++) { 1118 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1119 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1120 } 1121 } 1122 1123 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1124 { 1125 u32 i; 1126 1127 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1128 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1129 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1130 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1131 for (i = 0; i < addr_range; i++) { 1132 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1133 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1134 } 1135 } 1136 1137 static void pt_guest_enter(struct vcpu_vmx *vmx) 1138 { 1139 if (vmx_pt_mode_is_system()) 1140 return; 1141 1142 /* 1143 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1144 * Save host state before VM entry. 1145 */ 1146 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1147 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1148 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1149 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1150 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1151 } 1152 } 1153 1154 static void pt_guest_exit(struct vcpu_vmx *vmx) 1155 { 1156 if (vmx_pt_mode_is_system()) 1157 return; 1158 1159 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1160 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1161 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1162 } 1163 1164 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1165 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1166 } 1167 1168 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1169 unsigned long fs_base, unsigned long gs_base) 1170 { 1171 if (unlikely(fs_sel != host->fs_sel)) { 1172 if (!(fs_sel & 7)) 1173 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1174 else 1175 vmcs_write16(HOST_FS_SELECTOR, 0); 1176 host->fs_sel = fs_sel; 1177 } 1178 if (unlikely(gs_sel != host->gs_sel)) { 1179 if (!(gs_sel & 7)) 1180 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1181 else 1182 vmcs_write16(HOST_GS_SELECTOR, 0); 1183 host->gs_sel = gs_sel; 1184 } 1185 if (unlikely(fs_base != host->fs_base)) { 1186 vmcs_writel(HOST_FS_BASE, fs_base); 1187 host->fs_base = fs_base; 1188 } 1189 if (unlikely(gs_base != host->gs_base)) { 1190 vmcs_writel(HOST_GS_BASE, gs_base); 1191 host->gs_base = gs_base; 1192 } 1193 } 1194 1195 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1196 { 1197 struct vcpu_vmx *vmx = to_vmx(vcpu); 1198 struct vmcs_host_state *host_state; 1199 #ifdef CONFIG_X86_64 1200 int cpu = raw_smp_processor_id(); 1201 #endif 1202 unsigned long fs_base, gs_base; 1203 u16 fs_sel, gs_sel; 1204 int i; 1205 1206 vmx->req_immediate_exit = false; 1207 1208 /* 1209 * Note that guest MSRs to be saved/restored can also be changed 1210 * when guest state is loaded. This happens when guest transitions 1211 * to/from long-mode by setting MSR_EFER.LMA. 1212 */ 1213 if (!vmx->guest_uret_msrs_loaded) { 1214 vmx->guest_uret_msrs_loaded = true; 1215 for (i = 0; i < vmx->nr_active_uret_msrs; ++i) 1216 kvm_set_user_return_msr(vmx->guest_uret_msrs[i].slot, 1217 vmx->guest_uret_msrs[i].data, 1218 vmx->guest_uret_msrs[i].mask); 1219 1220 } 1221 1222 if (vmx->nested.need_vmcs12_to_shadow_sync) 1223 nested_sync_vmcs12_to_shadow(vcpu); 1224 1225 if (vmx->guest_state_loaded) 1226 return; 1227 1228 host_state = &vmx->loaded_vmcs->host_state; 1229 1230 /* 1231 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1232 * allow segment selectors with cpl > 0 or ti == 1. 1233 */ 1234 host_state->ldt_sel = kvm_read_ldt(); 1235 1236 #ifdef CONFIG_X86_64 1237 savesegment(ds, host_state->ds_sel); 1238 savesegment(es, host_state->es_sel); 1239 1240 gs_base = cpu_kernelmode_gs_base(cpu); 1241 if (likely(is_64bit_mm(current->mm))) { 1242 current_save_fsgs(); 1243 fs_sel = current->thread.fsindex; 1244 gs_sel = current->thread.gsindex; 1245 fs_base = current->thread.fsbase; 1246 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1247 } else { 1248 savesegment(fs, fs_sel); 1249 savesegment(gs, gs_sel); 1250 fs_base = read_msr(MSR_FS_BASE); 1251 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1252 } 1253 1254 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1255 #else 1256 savesegment(fs, fs_sel); 1257 savesegment(gs, gs_sel); 1258 fs_base = segment_base(fs_sel); 1259 gs_base = segment_base(gs_sel); 1260 #endif 1261 1262 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1263 vmx->guest_state_loaded = true; 1264 } 1265 1266 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1267 { 1268 struct vmcs_host_state *host_state; 1269 1270 if (!vmx->guest_state_loaded) 1271 return; 1272 1273 host_state = &vmx->loaded_vmcs->host_state; 1274 1275 ++vmx->vcpu.stat.host_state_reload; 1276 1277 #ifdef CONFIG_X86_64 1278 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1279 #endif 1280 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1281 kvm_load_ldt(host_state->ldt_sel); 1282 #ifdef CONFIG_X86_64 1283 load_gs_index(host_state->gs_sel); 1284 #else 1285 loadsegment(gs, host_state->gs_sel); 1286 #endif 1287 } 1288 if (host_state->fs_sel & 7) 1289 loadsegment(fs, host_state->fs_sel); 1290 #ifdef CONFIG_X86_64 1291 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1292 loadsegment(ds, host_state->ds_sel); 1293 loadsegment(es, host_state->es_sel); 1294 } 1295 #endif 1296 invalidate_tss_limit(); 1297 #ifdef CONFIG_X86_64 1298 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1299 #endif 1300 load_fixmap_gdt(raw_smp_processor_id()); 1301 vmx->guest_state_loaded = false; 1302 vmx->guest_uret_msrs_loaded = false; 1303 } 1304 1305 #ifdef CONFIG_X86_64 1306 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1307 { 1308 preempt_disable(); 1309 if (vmx->guest_state_loaded) 1310 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1311 preempt_enable(); 1312 return vmx->msr_guest_kernel_gs_base; 1313 } 1314 1315 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1316 { 1317 preempt_disable(); 1318 if (vmx->guest_state_loaded) 1319 wrmsrl(MSR_KERNEL_GS_BASE, data); 1320 preempt_enable(); 1321 vmx->msr_guest_kernel_gs_base = data; 1322 } 1323 #endif 1324 1325 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, 1326 struct loaded_vmcs *buddy) 1327 { 1328 struct vcpu_vmx *vmx = to_vmx(vcpu); 1329 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1330 struct vmcs *prev; 1331 1332 if (!already_loaded) { 1333 loaded_vmcs_clear(vmx->loaded_vmcs); 1334 local_irq_disable(); 1335 1336 /* 1337 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to 1338 * this cpu's percpu list, otherwise it may not yet be deleted 1339 * from its previous cpu's percpu list. Pairs with the 1340 * smb_wmb() in __loaded_vmcs_clear(). 1341 */ 1342 smp_rmb(); 1343 1344 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1345 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1346 local_irq_enable(); 1347 } 1348 1349 prev = per_cpu(current_vmcs, cpu); 1350 if (prev != vmx->loaded_vmcs->vmcs) { 1351 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1352 vmcs_load(vmx->loaded_vmcs->vmcs); 1353 1354 /* 1355 * No indirect branch prediction barrier needed when switching 1356 * the active VMCS within a guest, e.g. on nested VM-Enter. 1357 * The L1 VMM can protect itself with retpolines, IBPB or IBRS. 1358 */ 1359 if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev)) 1360 indirect_branch_prediction_barrier(); 1361 } 1362 1363 if (!already_loaded) { 1364 void *gdt = get_current_gdt_ro(); 1365 unsigned long sysenter_esp; 1366 1367 /* 1368 * Flush all EPTP/VPID contexts, the new pCPU may have stale 1369 * TLB entries from its previous association with the vCPU. 1370 */ 1371 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1372 1373 /* 1374 * Linux uses per-cpu TSS and GDT, so set these when switching 1375 * processors. See 22.2.4. 1376 */ 1377 vmcs_writel(HOST_TR_BASE, 1378 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1379 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1380 1381 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1382 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1383 1384 vmx->loaded_vmcs->cpu = cpu; 1385 } 1386 1387 /* Setup TSC multiplier */ 1388 if (kvm_has_tsc_control && 1389 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1390 decache_tsc_multiplier(vmx); 1391 } 1392 1393 /* 1394 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1395 * vcpu mutex is already taken. 1396 */ 1397 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1398 { 1399 struct vcpu_vmx *vmx = to_vmx(vcpu); 1400 1401 vmx_vcpu_load_vmcs(vcpu, cpu, NULL); 1402 1403 vmx_vcpu_pi_load(vcpu, cpu); 1404 1405 vmx->host_debugctlmsr = get_debugctlmsr(); 1406 } 1407 1408 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1409 { 1410 vmx_vcpu_pi_put(vcpu); 1411 1412 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1413 } 1414 1415 static bool emulation_required(struct kvm_vcpu *vcpu) 1416 { 1417 return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu); 1418 } 1419 1420 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1421 { 1422 struct vcpu_vmx *vmx = to_vmx(vcpu); 1423 unsigned long rflags, save_rflags; 1424 1425 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1426 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1427 rflags = vmcs_readl(GUEST_RFLAGS); 1428 if (vmx->rmode.vm86_active) { 1429 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1430 save_rflags = vmx->rmode.save_rflags; 1431 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1432 } 1433 vmx->rflags = rflags; 1434 } 1435 return vmx->rflags; 1436 } 1437 1438 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1439 { 1440 struct vcpu_vmx *vmx = to_vmx(vcpu); 1441 unsigned long old_rflags; 1442 1443 if (is_unrestricted_guest(vcpu)) { 1444 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1445 vmx->rflags = rflags; 1446 vmcs_writel(GUEST_RFLAGS, rflags); 1447 return; 1448 } 1449 1450 old_rflags = vmx_get_rflags(vcpu); 1451 vmx->rflags = rflags; 1452 if (vmx->rmode.vm86_active) { 1453 vmx->rmode.save_rflags = rflags; 1454 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1455 } 1456 vmcs_writel(GUEST_RFLAGS, rflags); 1457 1458 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1459 vmx->emulation_required = emulation_required(vcpu); 1460 } 1461 1462 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1463 { 1464 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1465 int ret = 0; 1466 1467 if (interruptibility & GUEST_INTR_STATE_STI) 1468 ret |= KVM_X86_SHADOW_INT_STI; 1469 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1470 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1471 1472 return ret; 1473 } 1474 1475 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1476 { 1477 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1478 u32 interruptibility = interruptibility_old; 1479 1480 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1481 1482 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1483 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1484 else if (mask & KVM_X86_SHADOW_INT_STI) 1485 interruptibility |= GUEST_INTR_STATE_STI; 1486 1487 if ((interruptibility != interruptibility_old)) 1488 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1489 } 1490 1491 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1492 { 1493 struct vcpu_vmx *vmx = to_vmx(vcpu); 1494 unsigned long value; 1495 1496 /* 1497 * Any MSR write that attempts to change bits marked reserved will 1498 * case a #GP fault. 1499 */ 1500 if (data & vmx->pt_desc.ctl_bitmask) 1501 return 1; 1502 1503 /* 1504 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1505 * result in a #GP unless the same write also clears TraceEn. 1506 */ 1507 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1508 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1509 return 1; 1510 1511 /* 1512 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1513 * and FabricEn would cause #GP, if 1514 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1515 */ 1516 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1517 !(data & RTIT_CTL_FABRIC_EN) && 1518 !intel_pt_validate_cap(vmx->pt_desc.caps, 1519 PT_CAP_single_range_output)) 1520 return 1; 1521 1522 /* 1523 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1524 * utilize encodings marked reserved will casue a #GP fault. 1525 */ 1526 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1527 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1528 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1529 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1530 return 1; 1531 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1532 PT_CAP_cycle_thresholds); 1533 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1534 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1535 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1536 return 1; 1537 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1538 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1539 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1540 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1541 return 1; 1542 1543 /* 1544 * If ADDRx_CFG is reserved or the encodings is >2 will 1545 * cause a #GP fault. 1546 */ 1547 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1548 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1549 return 1; 1550 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1551 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1552 return 1; 1553 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1554 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1555 return 1; 1556 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1557 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1558 return 1; 1559 1560 return 0; 1561 } 1562 1563 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len) 1564 { 1565 return true; 1566 } 1567 1568 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1569 { 1570 unsigned long rip, orig_rip; 1571 1572 /* 1573 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1574 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1575 * set when EPT misconfig occurs. In practice, real hardware updates 1576 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1577 * (namely Hyper-V) don't set it due to it being undefined behavior, 1578 * i.e. we end up advancing IP with some random value. 1579 */ 1580 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1581 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1582 orig_rip = kvm_rip_read(vcpu); 1583 rip = orig_rip + vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1584 #ifdef CONFIG_X86_64 1585 /* 1586 * We need to mask out the high 32 bits of RIP if not in 64-bit 1587 * mode, but just finding out that we are in 64-bit mode is 1588 * quite expensive. Only do it if there was a carry. 1589 */ 1590 if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu)) 1591 rip = (u32)rip; 1592 #endif 1593 kvm_rip_write(vcpu, rip); 1594 } else { 1595 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1596 return 0; 1597 } 1598 1599 /* skipping an emulated instruction also counts */ 1600 vmx_set_interrupt_shadow(vcpu, 0); 1601 1602 return 1; 1603 } 1604 1605 /* 1606 * Recognizes a pending MTF VM-exit and records the nested state for later 1607 * delivery. 1608 */ 1609 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu) 1610 { 1611 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1612 struct vcpu_vmx *vmx = to_vmx(vcpu); 1613 1614 if (!is_guest_mode(vcpu)) 1615 return; 1616 1617 /* 1618 * Per the SDM, MTF takes priority over debug-trap exceptions besides 1619 * T-bit traps. As instruction emulation is completed (i.e. at the 1620 * instruction boundary), any #DB exception pending delivery must be a 1621 * debug-trap. Record the pending MTF state to be delivered in 1622 * vmx_check_nested_events(). 1623 */ 1624 if (nested_cpu_has_mtf(vmcs12) && 1625 (!vcpu->arch.exception.pending || 1626 vcpu->arch.exception.nr == DB_VECTOR)) 1627 vmx->nested.mtf_pending = true; 1628 else 1629 vmx->nested.mtf_pending = false; 1630 } 1631 1632 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu) 1633 { 1634 vmx_update_emulated_instruction(vcpu); 1635 return skip_emulated_instruction(vcpu); 1636 } 1637 1638 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1639 { 1640 /* 1641 * Ensure that we clear the HLT state in the VMCS. We don't need to 1642 * explicitly skip the instruction because if the HLT state is set, 1643 * then the instruction is already executing and RIP has already been 1644 * advanced. 1645 */ 1646 if (kvm_hlt_in_guest(vcpu->kvm) && 1647 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1648 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1649 } 1650 1651 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1652 { 1653 struct vcpu_vmx *vmx = to_vmx(vcpu); 1654 unsigned nr = vcpu->arch.exception.nr; 1655 bool has_error_code = vcpu->arch.exception.has_error_code; 1656 u32 error_code = vcpu->arch.exception.error_code; 1657 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1658 1659 kvm_deliver_exception_payload(vcpu); 1660 1661 if (has_error_code) { 1662 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1663 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1664 } 1665 1666 if (vmx->rmode.vm86_active) { 1667 int inc_eip = 0; 1668 if (kvm_exception_is_soft(nr)) 1669 inc_eip = vcpu->arch.event_exit_inst_len; 1670 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1671 return; 1672 } 1673 1674 WARN_ON_ONCE(vmx->emulation_required); 1675 1676 if (kvm_exception_is_soft(nr)) { 1677 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1678 vmx->vcpu.arch.event_exit_inst_len); 1679 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1680 } else 1681 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1682 1683 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1684 1685 vmx_clear_hlt(vcpu); 1686 } 1687 1688 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr) 1689 { 1690 struct vmx_uret_msr tmp; 1691 int from, to; 1692 1693 from = __vmx_find_uret_msr(vmx, msr); 1694 if (from < 0) 1695 return; 1696 to = vmx->nr_active_uret_msrs++; 1697 1698 tmp = vmx->guest_uret_msrs[to]; 1699 vmx->guest_uret_msrs[to] = vmx->guest_uret_msrs[from]; 1700 vmx->guest_uret_msrs[from] = tmp; 1701 } 1702 1703 /* 1704 * Set up the vmcs to automatically save and restore system 1705 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1706 * mode, as fiddling with msrs is very expensive. 1707 */ 1708 static void setup_msrs(struct vcpu_vmx *vmx) 1709 { 1710 vmx->guest_uret_msrs_loaded = false; 1711 vmx->nr_active_uret_msrs = 0; 1712 #ifdef CONFIG_X86_64 1713 /* 1714 * The SYSCALL MSRs are only needed on long mode guests, and only 1715 * when EFER.SCE is set. 1716 */ 1717 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1718 vmx_setup_uret_msr(vmx, MSR_STAR); 1719 vmx_setup_uret_msr(vmx, MSR_LSTAR); 1720 vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK); 1721 } 1722 #endif 1723 if (update_transition_efer(vmx)) 1724 vmx_setup_uret_msr(vmx, MSR_EFER); 1725 1726 if (guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1727 vmx_setup_uret_msr(vmx, MSR_TSC_AUX); 1728 1729 vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL); 1730 1731 if (cpu_has_vmx_msr_bitmap()) 1732 vmx_update_msr_bitmap(&vmx->vcpu); 1733 } 1734 1735 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1736 { 1737 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1738 u64 g_tsc_offset = 0; 1739 1740 /* 1741 * We're here if L1 chose not to trap WRMSR to TSC. According 1742 * to the spec, this should set L1's TSC; The offset that L1 1743 * set for L2 remains unchanged, and still needs to be added 1744 * to the newly set TSC to get L2's TSC. 1745 */ 1746 if (is_guest_mode(vcpu) && 1747 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1748 g_tsc_offset = vmcs12->tsc_offset; 1749 1750 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1751 vcpu->arch.tsc_offset - g_tsc_offset, 1752 offset); 1753 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1754 return offset + g_tsc_offset; 1755 } 1756 1757 /* 1758 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1759 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1760 * all guests if the "nested" module option is off, and can also be disabled 1761 * for a single guest by disabling its VMX cpuid bit. 1762 */ 1763 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1764 { 1765 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1766 } 1767 1768 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1769 uint64_t val) 1770 { 1771 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1772 1773 return !(val & ~valid_bits); 1774 } 1775 1776 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1777 { 1778 switch (msr->index) { 1779 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1780 if (!nested) 1781 return 1; 1782 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1783 case MSR_IA32_PERF_CAPABILITIES: 1784 msr->data = vmx_get_perf_capabilities(); 1785 return 0; 1786 default: 1787 return KVM_MSR_RET_INVALID; 1788 } 1789 } 1790 1791 /* 1792 * Reads an msr value (of 'msr_index') into 'pdata'. 1793 * Returns 0 on success, non-0 otherwise. 1794 * Assumes vcpu_load() was already called. 1795 */ 1796 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1797 { 1798 struct vcpu_vmx *vmx = to_vmx(vcpu); 1799 struct vmx_uret_msr *msr; 1800 u32 index; 1801 1802 switch (msr_info->index) { 1803 #ifdef CONFIG_X86_64 1804 case MSR_FS_BASE: 1805 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1806 break; 1807 case MSR_GS_BASE: 1808 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1809 break; 1810 case MSR_KERNEL_GS_BASE: 1811 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1812 break; 1813 #endif 1814 case MSR_EFER: 1815 return kvm_get_msr_common(vcpu, msr_info); 1816 case MSR_IA32_TSX_CTRL: 1817 if (!msr_info->host_initiated && 1818 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1819 return 1; 1820 goto find_uret_msr; 1821 case MSR_IA32_UMWAIT_CONTROL: 1822 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1823 return 1; 1824 1825 msr_info->data = vmx->msr_ia32_umwait_control; 1826 break; 1827 case MSR_IA32_SPEC_CTRL: 1828 if (!msr_info->host_initiated && 1829 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1830 return 1; 1831 1832 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1833 break; 1834 case MSR_IA32_SYSENTER_CS: 1835 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1836 break; 1837 case MSR_IA32_SYSENTER_EIP: 1838 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1839 break; 1840 case MSR_IA32_SYSENTER_ESP: 1841 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1842 break; 1843 case MSR_IA32_BNDCFGS: 1844 if (!kvm_mpx_supported() || 1845 (!msr_info->host_initiated && 1846 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1847 return 1; 1848 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1849 break; 1850 case MSR_IA32_MCG_EXT_CTL: 1851 if (!msr_info->host_initiated && 1852 !(vmx->msr_ia32_feature_control & 1853 FEAT_CTL_LMCE_ENABLED)) 1854 return 1; 1855 msr_info->data = vcpu->arch.mcg_ext_ctl; 1856 break; 1857 case MSR_IA32_FEAT_CTL: 1858 msr_info->data = vmx->msr_ia32_feature_control; 1859 break; 1860 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1861 if (!nested_vmx_allowed(vcpu)) 1862 return 1; 1863 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1864 &msr_info->data)) 1865 return 1; 1866 /* 1867 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1868 * Hyper-V versions are still trying to use corresponding 1869 * features when they are exposed. Filter out the essential 1870 * minimum. 1871 */ 1872 if (!msr_info->host_initiated && 1873 vmx->nested.enlightened_vmcs_enabled) 1874 nested_evmcs_filter_control_msr(msr_info->index, 1875 &msr_info->data); 1876 break; 1877 case MSR_IA32_RTIT_CTL: 1878 if (!vmx_pt_mode_is_host_guest()) 1879 return 1; 1880 msr_info->data = vmx->pt_desc.guest.ctl; 1881 break; 1882 case MSR_IA32_RTIT_STATUS: 1883 if (!vmx_pt_mode_is_host_guest()) 1884 return 1; 1885 msr_info->data = vmx->pt_desc.guest.status; 1886 break; 1887 case MSR_IA32_RTIT_CR3_MATCH: 1888 if (!vmx_pt_mode_is_host_guest() || 1889 !intel_pt_validate_cap(vmx->pt_desc.caps, 1890 PT_CAP_cr3_filtering)) 1891 return 1; 1892 msr_info->data = vmx->pt_desc.guest.cr3_match; 1893 break; 1894 case MSR_IA32_RTIT_OUTPUT_BASE: 1895 if (!vmx_pt_mode_is_host_guest() || 1896 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1897 PT_CAP_topa_output) && 1898 !intel_pt_validate_cap(vmx->pt_desc.caps, 1899 PT_CAP_single_range_output))) 1900 return 1; 1901 msr_info->data = vmx->pt_desc.guest.output_base; 1902 break; 1903 case MSR_IA32_RTIT_OUTPUT_MASK: 1904 if (!vmx_pt_mode_is_host_guest() || 1905 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1906 PT_CAP_topa_output) && 1907 !intel_pt_validate_cap(vmx->pt_desc.caps, 1908 PT_CAP_single_range_output))) 1909 return 1; 1910 msr_info->data = vmx->pt_desc.guest.output_mask; 1911 break; 1912 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1913 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1914 if (!vmx_pt_mode_is_host_guest() || 1915 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1916 PT_CAP_num_address_ranges))) 1917 return 1; 1918 if (index % 2) 1919 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1920 else 1921 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1922 break; 1923 case MSR_TSC_AUX: 1924 if (!msr_info->host_initiated && 1925 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1926 return 1; 1927 goto find_uret_msr; 1928 default: 1929 find_uret_msr: 1930 msr = vmx_find_uret_msr(vmx, msr_info->index); 1931 if (msr) { 1932 msr_info->data = msr->data; 1933 break; 1934 } 1935 return kvm_get_msr_common(vcpu, msr_info); 1936 } 1937 1938 return 0; 1939 } 1940 1941 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu, 1942 u64 data) 1943 { 1944 #ifdef CONFIG_X86_64 1945 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1946 return (u32)data; 1947 #endif 1948 return (unsigned long)data; 1949 } 1950 1951 /* 1952 * Writes msr value into the appropriate "register". 1953 * Returns 0 on success, non-0 otherwise. 1954 * Assumes vcpu_load() was already called. 1955 */ 1956 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1957 { 1958 struct vcpu_vmx *vmx = to_vmx(vcpu); 1959 struct vmx_uret_msr *msr; 1960 int ret = 0; 1961 u32 msr_index = msr_info->index; 1962 u64 data = msr_info->data; 1963 u32 index; 1964 1965 switch (msr_index) { 1966 case MSR_EFER: 1967 ret = kvm_set_msr_common(vcpu, msr_info); 1968 break; 1969 #ifdef CONFIG_X86_64 1970 case MSR_FS_BASE: 1971 vmx_segment_cache_clear(vmx); 1972 vmcs_writel(GUEST_FS_BASE, data); 1973 break; 1974 case MSR_GS_BASE: 1975 vmx_segment_cache_clear(vmx); 1976 vmcs_writel(GUEST_GS_BASE, data); 1977 break; 1978 case MSR_KERNEL_GS_BASE: 1979 vmx_write_guest_kernel_gs_base(vmx, data); 1980 break; 1981 #endif 1982 case MSR_IA32_SYSENTER_CS: 1983 if (is_guest_mode(vcpu)) 1984 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1985 vmcs_write32(GUEST_SYSENTER_CS, data); 1986 break; 1987 case MSR_IA32_SYSENTER_EIP: 1988 if (is_guest_mode(vcpu)) { 1989 data = nested_vmx_truncate_sysenter_addr(vcpu, data); 1990 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1991 } 1992 vmcs_writel(GUEST_SYSENTER_EIP, data); 1993 break; 1994 case MSR_IA32_SYSENTER_ESP: 1995 if (is_guest_mode(vcpu)) { 1996 data = nested_vmx_truncate_sysenter_addr(vcpu, data); 1997 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1998 } 1999 vmcs_writel(GUEST_SYSENTER_ESP, data); 2000 break; 2001 case MSR_IA32_DEBUGCTLMSR: 2002 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 2003 VM_EXIT_SAVE_DEBUG_CONTROLS) 2004 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 2005 2006 ret = kvm_set_msr_common(vcpu, msr_info); 2007 break; 2008 2009 case MSR_IA32_BNDCFGS: 2010 if (!kvm_mpx_supported() || 2011 (!msr_info->host_initiated && 2012 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 2013 return 1; 2014 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 2015 (data & MSR_IA32_BNDCFGS_RSVD)) 2016 return 1; 2017 vmcs_write64(GUEST_BNDCFGS, data); 2018 break; 2019 case MSR_IA32_UMWAIT_CONTROL: 2020 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 2021 return 1; 2022 2023 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 2024 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 2025 return 1; 2026 2027 vmx->msr_ia32_umwait_control = data; 2028 break; 2029 case MSR_IA32_SPEC_CTRL: 2030 if (!msr_info->host_initiated && 2031 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2032 return 1; 2033 2034 if (kvm_spec_ctrl_test_value(data)) 2035 return 1; 2036 2037 vmx->spec_ctrl = data; 2038 if (!data) 2039 break; 2040 2041 /* 2042 * For non-nested: 2043 * When it's written (to non-zero) for the first time, pass 2044 * it through. 2045 * 2046 * For nested: 2047 * The handling of the MSR bitmap for L2 guests is done in 2048 * nested_vmx_prepare_msr_bitmap. We should not touch the 2049 * vmcs02.msr_bitmap here since it gets completely overwritten 2050 * in the merging. We update the vmcs01 here for L1 as well 2051 * since it will end up touching the MSR anyway now. 2052 */ 2053 vmx_disable_intercept_for_msr(vcpu, 2054 MSR_IA32_SPEC_CTRL, 2055 MSR_TYPE_RW); 2056 break; 2057 case MSR_IA32_TSX_CTRL: 2058 if (!msr_info->host_initiated && 2059 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2060 return 1; 2061 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2062 return 1; 2063 goto find_uret_msr; 2064 case MSR_IA32_PRED_CMD: 2065 if (!msr_info->host_initiated && 2066 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2067 return 1; 2068 2069 if (data & ~PRED_CMD_IBPB) 2070 return 1; 2071 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2072 return 1; 2073 if (!data) 2074 break; 2075 2076 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2077 2078 /* 2079 * For non-nested: 2080 * When it's written (to non-zero) for the first time, pass 2081 * it through. 2082 * 2083 * For nested: 2084 * The handling of the MSR bitmap for L2 guests is done in 2085 * nested_vmx_prepare_msr_bitmap. We should not touch the 2086 * vmcs02.msr_bitmap here since it gets completely overwritten 2087 * in the merging. 2088 */ 2089 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W); 2090 break; 2091 case MSR_IA32_CR_PAT: 2092 if (!kvm_pat_valid(data)) 2093 return 1; 2094 2095 if (is_guest_mode(vcpu) && 2096 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2097 get_vmcs12(vcpu)->guest_ia32_pat = data; 2098 2099 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2100 vmcs_write64(GUEST_IA32_PAT, data); 2101 vcpu->arch.pat = data; 2102 break; 2103 } 2104 ret = kvm_set_msr_common(vcpu, msr_info); 2105 break; 2106 case MSR_IA32_TSC_ADJUST: 2107 ret = kvm_set_msr_common(vcpu, msr_info); 2108 break; 2109 case MSR_IA32_MCG_EXT_CTL: 2110 if ((!msr_info->host_initiated && 2111 !(to_vmx(vcpu)->msr_ia32_feature_control & 2112 FEAT_CTL_LMCE_ENABLED)) || 2113 (data & ~MCG_EXT_CTL_LMCE_EN)) 2114 return 1; 2115 vcpu->arch.mcg_ext_ctl = data; 2116 break; 2117 case MSR_IA32_FEAT_CTL: 2118 if (!vmx_feature_control_msr_valid(vcpu, data) || 2119 (to_vmx(vcpu)->msr_ia32_feature_control & 2120 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2121 return 1; 2122 vmx->msr_ia32_feature_control = data; 2123 if (msr_info->host_initiated && data == 0) 2124 vmx_leave_nested(vcpu); 2125 break; 2126 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2127 if (!msr_info->host_initiated) 2128 return 1; /* they are read-only */ 2129 if (!nested_vmx_allowed(vcpu)) 2130 return 1; 2131 return vmx_set_vmx_msr(vcpu, msr_index, data); 2132 case MSR_IA32_RTIT_CTL: 2133 if (!vmx_pt_mode_is_host_guest() || 2134 vmx_rtit_ctl_check(vcpu, data) || 2135 vmx->nested.vmxon) 2136 return 1; 2137 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2138 vmx->pt_desc.guest.ctl = data; 2139 pt_update_intercept_for_msr(vcpu); 2140 break; 2141 case MSR_IA32_RTIT_STATUS: 2142 if (!pt_can_write_msr(vmx)) 2143 return 1; 2144 if (data & MSR_IA32_RTIT_STATUS_MASK) 2145 return 1; 2146 vmx->pt_desc.guest.status = data; 2147 break; 2148 case MSR_IA32_RTIT_CR3_MATCH: 2149 if (!pt_can_write_msr(vmx)) 2150 return 1; 2151 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2152 PT_CAP_cr3_filtering)) 2153 return 1; 2154 vmx->pt_desc.guest.cr3_match = data; 2155 break; 2156 case MSR_IA32_RTIT_OUTPUT_BASE: 2157 if (!pt_can_write_msr(vmx)) 2158 return 1; 2159 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2160 PT_CAP_topa_output) && 2161 !intel_pt_validate_cap(vmx->pt_desc.caps, 2162 PT_CAP_single_range_output)) 2163 return 1; 2164 if (!pt_output_base_valid(vcpu, data)) 2165 return 1; 2166 vmx->pt_desc.guest.output_base = data; 2167 break; 2168 case MSR_IA32_RTIT_OUTPUT_MASK: 2169 if (!pt_can_write_msr(vmx)) 2170 return 1; 2171 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2172 PT_CAP_topa_output) && 2173 !intel_pt_validate_cap(vmx->pt_desc.caps, 2174 PT_CAP_single_range_output)) 2175 return 1; 2176 vmx->pt_desc.guest.output_mask = data; 2177 break; 2178 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2179 if (!pt_can_write_msr(vmx)) 2180 return 1; 2181 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2182 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2183 PT_CAP_num_address_ranges)) 2184 return 1; 2185 if (is_noncanonical_address(data, vcpu)) 2186 return 1; 2187 if (index % 2) 2188 vmx->pt_desc.guest.addr_b[index / 2] = data; 2189 else 2190 vmx->pt_desc.guest.addr_a[index / 2] = data; 2191 break; 2192 case MSR_TSC_AUX: 2193 if (!msr_info->host_initiated && 2194 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2195 return 1; 2196 /* Check reserved bit, higher 32 bits should be zero */ 2197 if ((data >> 32) != 0) 2198 return 1; 2199 goto find_uret_msr; 2200 2201 default: 2202 find_uret_msr: 2203 msr = vmx_find_uret_msr(vmx, msr_index); 2204 if (msr) 2205 ret = vmx_set_guest_uret_msr(vmx, msr, data); 2206 else 2207 ret = kvm_set_msr_common(vcpu, msr_info); 2208 } 2209 2210 return ret; 2211 } 2212 2213 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2214 { 2215 unsigned long guest_owned_bits; 2216 2217 kvm_register_mark_available(vcpu, reg); 2218 2219 switch (reg) { 2220 case VCPU_REGS_RSP: 2221 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2222 break; 2223 case VCPU_REGS_RIP: 2224 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2225 break; 2226 case VCPU_EXREG_PDPTR: 2227 if (enable_ept) 2228 ept_save_pdptrs(vcpu); 2229 break; 2230 case VCPU_EXREG_CR0: 2231 guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2232 2233 vcpu->arch.cr0 &= ~guest_owned_bits; 2234 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits; 2235 break; 2236 case VCPU_EXREG_CR3: 2237 if (is_unrestricted_guest(vcpu) || 2238 (enable_ept && is_paging(vcpu))) 2239 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2240 break; 2241 case VCPU_EXREG_CR4: 2242 guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2243 2244 vcpu->arch.cr4 &= ~guest_owned_bits; 2245 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits; 2246 break; 2247 default: 2248 WARN_ON_ONCE(1); 2249 break; 2250 } 2251 } 2252 2253 static __init int cpu_has_kvm_support(void) 2254 { 2255 return cpu_has_vmx(); 2256 } 2257 2258 static __init int vmx_disabled_by_bios(void) 2259 { 2260 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2261 !boot_cpu_has(X86_FEATURE_VMX); 2262 } 2263 2264 static int kvm_cpu_vmxon(u64 vmxon_pointer) 2265 { 2266 u64 msr; 2267 2268 cr4_set_bits(X86_CR4_VMXE); 2269 intel_pt_handle_vmx(1); 2270 2271 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t" 2272 _ASM_EXTABLE(1b, %l[fault]) 2273 : : [vmxon_pointer] "m"(vmxon_pointer) 2274 : : fault); 2275 return 0; 2276 2277 fault: 2278 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n", 2279 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); 2280 intel_pt_handle_vmx(0); 2281 cr4_clear_bits(X86_CR4_VMXE); 2282 2283 return -EFAULT; 2284 } 2285 2286 static int hardware_enable(void) 2287 { 2288 int cpu = raw_smp_processor_id(); 2289 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2290 int r; 2291 2292 if (cr4_read_shadow() & X86_CR4_VMXE) 2293 return -EBUSY; 2294 2295 /* 2296 * This can happen if we hot-added a CPU but failed to allocate 2297 * VP assist page for it. 2298 */ 2299 if (static_branch_unlikely(&enable_evmcs) && 2300 !hv_get_vp_assist_page(cpu)) 2301 return -EFAULT; 2302 2303 r = kvm_cpu_vmxon(phys_addr); 2304 if (r) 2305 return r; 2306 2307 if (enable_ept) 2308 ept_sync_global(); 2309 2310 return 0; 2311 } 2312 2313 static void vmclear_local_loaded_vmcss(void) 2314 { 2315 int cpu = raw_smp_processor_id(); 2316 struct loaded_vmcs *v, *n; 2317 2318 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2319 loaded_vmcss_on_cpu_link) 2320 __loaded_vmcs_clear(v); 2321 } 2322 2323 2324 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2325 * tricks. 2326 */ 2327 static void kvm_cpu_vmxoff(void) 2328 { 2329 asm volatile (__ex("vmxoff")); 2330 2331 intel_pt_handle_vmx(0); 2332 cr4_clear_bits(X86_CR4_VMXE); 2333 } 2334 2335 static void hardware_disable(void) 2336 { 2337 vmclear_local_loaded_vmcss(); 2338 kvm_cpu_vmxoff(); 2339 } 2340 2341 /* 2342 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID 2343 * directly instead of going through cpu_has(), to ensure KVM is trapping 2344 * ENCLS whenever it's supported in hardware. It does not matter whether 2345 * the host OS supports or has enabled SGX. 2346 */ 2347 static bool cpu_has_sgx(void) 2348 { 2349 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0)); 2350 } 2351 2352 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2353 u32 msr, u32 *result) 2354 { 2355 u32 vmx_msr_low, vmx_msr_high; 2356 u32 ctl = ctl_min | ctl_opt; 2357 2358 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2359 2360 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2361 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2362 2363 /* Ensure minimum (required) set of control bits are supported. */ 2364 if (ctl_min & ~ctl) 2365 return -EIO; 2366 2367 *result = ctl; 2368 return 0; 2369 } 2370 2371 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2372 struct vmx_capability *vmx_cap) 2373 { 2374 u32 vmx_msr_low, vmx_msr_high; 2375 u32 min, opt, min2, opt2; 2376 u32 _pin_based_exec_control = 0; 2377 u32 _cpu_based_exec_control = 0; 2378 u32 _cpu_based_2nd_exec_control = 0; 2379 u32 _vmexit_control = 0; 2380 u32 _vmentry_control = 0; 2381 2382 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2383 min = CPU_BASED_HLT_EXITING | 2384 #ifdef CONFIG_X86_64 2385 CPU_BASED_CR8_LOAD_EXITING | 2386 CPU_BASED_CR8_STORE_EXITING | 2387 #endif 2388 CPU_BASED_CR3_LOAD_EXITING | 2389 CPU_BASED_CR3_STORE_EXITING | 2390 CPU_BASED_UNCOND_IO_EXITING | 2391 CPU_BASED_MOV_DR_EXITING | 2392 CPU_BASED_USE_TSC_OFFSETTING | 2393 CPU_BASED_MWAIT_EXITING | 2394 CPU_BASED_MONITOR_EXITING | 2395 CPU_BASED_INVLPG_EXITING | 2396 CPU_BASED_RDPMC_EXITING; 2397 2398 opt = CPU_BASED_TPR_SHADOW | 2399 CPU_BASED_USE_MSR_BITMAPS | 2400 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2401 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2402 &_cpu_based_exec_control) < 0) 2403 return -EIO; 2404 #ifdef CONFIG_X86_64 2405 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2406 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2407 ~CPU_BASED_CR8_STORE_EXITING; 2408 #endif 2409 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2410 min2 = 0; 2411 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2412 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2413 SECONDARY_EXEC_WBINVD_EXITING | 2414 SECONDARY_EXEC_ENABLE_VPID | 2415 SECONDARY_EXEC_ENABLE_EPT | 2416 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2417 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2418 SECONDARY_EXEC_DESC | 2419 SECONDARY_EXEC_ENABLE_RDTSCP | 2420 SECONDARY_EXEC_ENABLE_INVPCID | 2421 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2422 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2423 SECONDARY_EXEC_SHADOW_VMCS | 2424 SECONDARY_EXEC_XSAVES | 2425 SECONDARY_EXEC_RDSEED_EXITING | 2426 SECONDARY_EXEC_RDRAND_EXITING | 2427 SECONDARY_EXEC_ENABLE_PML | 2428 SECONDARY_EXEC_TSC_SCALING | 2429 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2430 SECONDARY_EXEC_PT_USE_GPA | 2431 SECONDARY_EXEC_PT_CONCEAL_VMX | 2432 SECONDARY_EXEC_ENABLE_VMFUNC; 2433 if (cpu_has_sgx()) 2434 opt2 |= SECONDARY_EXEC_ENCLS_EXITING; 2435 if (adjust_vmx_controls(min2, opt2, 2436 MSR_IA32_VMX_PROCBASED_CTLS2, 2437 &_cpu_based_2nd_exec_control) < 0) 2438 return -EIO; 2439 } 2440 #ifndef CONFIG_X86_64 2441 if (!(_cpu_based_2nd_exec_control & 2442 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2443 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2444 #endif 2445 2446 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2447 _cpu_based_2nd_exec_control &= ~( 2448 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2449 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2450 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2451 2452 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2453 &vmx_cap->ept, &vmx_cap->vpid); 2454 2455 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2456 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2457 enabled */ 2458 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2459 CPU_BASED_CR3_STORE_EXITING | 2460 CPU_BASED_INVLPG_EXITING); 2461 } else if (vmx_cap->ept) { 2462 vmx_cap->ept = 0; 2463 pr_warn_once("EPT CAP should not exist if not support " 2464 "1-setting enable EPT VM-execution control\n"); 2465 } 2466 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2467 vmx_cap->vpid) { 2468 vmx_cap->vpid = 0; 2469 pr_warn_once("VPID CAP should not exist if not support " 2470 "1-setting enable VPID VM-execution control\n"); 2471 } 2472 2473 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2474 #ifdef CONFIG_X86_64 2475 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2476 #endif 2477 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2478 VM_EXIT_LOAD_IA32_PAT | 2479 VM_EXIT_LOAD_IA32_EFER | 2480 VM_EXIT_CLEAR_BNDCFGS | 2481 VM_EXIT_PT_CONCEAL_PIP | 2482 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2483 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2484 &_vmexit_control) < 0) 2485 return -EIO; 2486 2487 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2488 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2489 PIN_BASED_VMX_PREEMPTION_TIMER; 2490 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2491 &_pin_based_exec_control) < 0) 2492 return -EIO; 2493 2494 if (cpu_has_broken_vmx_preemption_timer()) 2495 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2496 if (!(_cpu_based_2nd_exec_control & 2497 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2498 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2499 2500 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2501 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2502 VM_ENTRY_LOAD_IA32_PAT | 2503 VM_ENTRY_LOAD_IA32_EFER | 2504 VM_ENTRY_LOAD_BNDCFGS | 2505 VM_ENTRY_PT_CONCEAL_PIP | 2506 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2507 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2508 &_vmentry_control) < 0) 2509 return -EIO; 2510 2511 /* 2512 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2513 * can't be used due to an errata where VM Exit may incorrectly clear 2514 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2515 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2516 */ 2517 if (boot_cpu_data.x86 == 0x6) { 2518 switch (boot_cpu_data.x86_model) { 2519 case 26: /* AAK155 */ 2520 case 30: /* AAP115 */ 2521 case 37: /* AAT100 */ 2522 case 44: /* BC86,AAY89,BD102 */ 2523 case 46: /* BA97 */ 2524 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2525 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2526 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2527 "does not work properly. Using workaround\n"); 2528 break; 2529 default: 2530 break; 2531 } 2532 } 2533 2534 2535 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2536 2537 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2538 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2539 return -EIO; 2540 2541 #ifdef CONFIG_X86_64 2542 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2543 if (vmx_msr_high & (1u<<16)) 2544 return -EIO; 2545 #endif 2546 2547 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2548 if (((vmx_msr_high >> 18) & 15) != 6) 2549 return -EIO; 2550 2551 vmcs_conf->size = vmx_msr_high & 0x1fff; 2552 vmcs_conf->order = get_order(vmcs_conf->size); 2553 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2554 2555 vmcs_conf->revision_id = vmx_msr_low; 2556 2557 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2558 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2559 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2560 vmcs_conf->vmexit_ctrl = _vmexit_control; 2561 vmcs_conf->vmentry_ctrl = _vmentry_control; 2562 2563 #if IS_ENABLED(CONFIG_HYPERV) 2564 if (enlightened_vmcs) 2565 evmcs_sanitize_exec_ctrls(vmcs_conf); 2566 #endif 2567 2568 return 0; 2569 } 2570 2571 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2572 { 2573 int node = cpu_to_node(cpu); 2574 struct page *pages; 2575 struct vmcs *vmcs; 2576 2577 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2578 if (!pages) 2579 return NULL; 2580 vmcs = page_address(pages); 2581 memset(vmcs, 0, vmcs_config.size); 2582 2583 /* KVM supports Enlightened VMCS v1 only */ 2584 if (static_branch_unlikely(&enable_evmcs)) 2585 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2586 else 2587 vmcs->hdr.revision_id = vmcs_config.revision_id; 2588 2589 if (shadow) 2590 vmcs->hdr.shadow_vmcs = 1; 2591 return vmcs; 2592 } 2593 2594 void free_vmcs(struct vmcs *vmcs) 2595 { 2596 free_pages((unsigned long)vmcs, vmcs_config.order); 2597 } 2598 2599 /* 2600 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2601 */ 2602 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2603 { 2604 if (!loaded_vmcs->vmcs) 2605 return; 2606 loaded_vmcs_clear(loaded_vmcs); 2607 free_vmcs(loaded_vmcs->vmcs); 2608 loaded_vmcs->vmcs = NULL; 2609 if (loaded_vmcs->msr_bitmap) 2610 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2611 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2612 } 2613 2614 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2615 { 2616 loaded_vmcs->vmcs = alloc_vmcs(false); 2617 if (!loaded_vmcs->vmcs) 2618 return -ENOMEM; 2619 2620 vmcs_clear(loaded_vmcs->vmcs); 2621 2622 loaded_vmcs->shadow_vmcs = NULL; 2623 loaded_vmcs->hv_timer_soft_disabled = false; 2624 loaded_vmcs->cpu = -1; 2625 loaded_vmcs->launched = 0; 2626 2627 if (cpu_has_vmx_msr_bitmap()) { 2628 loaded_vmcs->msr_bitmap = (unsigned long *) 2629 __get_free_page(GFP_KERNEL_ACCOUNT); 2630 if (!loaded_vmcs->msr_bitmap) 2631 goto out_vmcs; 2632 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2633 2634 if (IS_ENABLED(CONFIG_HYPERV) && 2635 static_branch_unlikely(&enable_evmcs) && 2636 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2637 struct hv_enlightened_vmcs *evmcs = 2638 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2639 2640 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2641 } 2642 } 2643 2644 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2645 memset(&loaded_vmcs->controls_shadow, 0, 2646 sizeof(struct vmcs_controls_shadow)); 2647 2648 return 0; 2649 2650 out_vmcs: 2651 free_loaded_vmcs(loaded_vmcs); 2652 return -ENOMEM; 2653 } 2654 2655 static void free_kvm_area(void) 2656 { 2657 int cpu; 2658 2659 for_each_possible_cpu(cpu) { 2660 free_vmcs(per_cpu(vmxarea, cpu)); 2661 per_cpu(vmxarea, cpu) = NULL; 2662 } 2663 } 2664 2665 static __init int alloc_kvm_area(void) 2666 { 2667 int cpu; 2668 2669 for_each_possible_cpu(cpu) { 2670 struct vmcs *vmcs; 2671 2672 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2673 if (!vmcs) { 2674 free_kvm_area(); 2675 return -ENOMEM; 2676 } 2677 2678 /* 2679 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2680 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2681 * revision_id reported by MSR_IA32_VMX_BASIC. 2682 * 2683 * However, even though not explicitly documented by 2684 * TLFS, VMXArea passed as VMXON argument should 2685 * still be marked with revision_id reported by 2686 * physical CPU. 2687 */ 2688 if (static_branch_unlikely(&enable_evmcs)) 2689 vmcs->hdr.revision_id = vmcs_config.revision_id; 2690 2691 per_cpu(vmxarea, cpu) = vmcs; 2692 } 2693 return 0; 2694 } 2695 2696 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2697 struct kvm_segment *save) 2698 { 2699 if (!emulate_invalid_guest_state) { 2700 /* 2701 * CS and SS RPL should be equal during guest entry according 2702 * to VMX spec, but in reality it is not always so. Since vcpu 2703 * is in the middle of the transition from real mode to 2704 * protected mode it is safe to assume that RPL 0 is a good 2705 * default value. 2706 */ 2707 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2708 save->selector &= ~SEGMENT_RPL_MASK; 2709 save->dpl = save->selector & SEGMENT_RPL_MASK; 2710 save->s = 1; 2711 } 2712 vmx_set_segment(vcpu, save, seg); 2713 } 2714 2715 static void enter_pmode(struct kvm_vcpu *vcpu) 2716 { 2717 unsigned long flags; 2718 struct vcpu_vmx *vmx = to_vmx(vcpu); 2719 2720 /* 2721 * Update real mode segment cache. It may be not up-to-date if sement 2722 * register was written while vcpu was in a guest mode. 2723 */ 2724 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2725 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2726 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2727 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2728 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2729 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2730 2731 vmx->rmode.vm86_active = 0; 2732 2733 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2734 2735 flags = vmcs_readl(GUEST_RFLAGS); 2736 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2737 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2738 vmcs_writel(GUEST_RFLAGS, flags); 2739 2740 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2741 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2742 2743 update_exception_bitmap(vcpu); 2744 2745 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2746 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2747 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2748 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2749 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2750 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2751 } 2752 2753 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2754 { 2755 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2756 struct kvm_segment var = *save; 2757 2758 var.dpl = 0x3; 2759 if (seg == VCPU_SREG_CS) 2760 var.type = 0x3; 2761 2762 if (!emulate_invalid_guest_state) { 2763 var.selector = var.base >> 4; 2764 var.base = var.base & 0xffff0; 2765 var.limit = 0xffff; 2766 var.g = 0; 2767 var.db = 0; 2768 var.present = 1; 2769 var.s = 1; 2770 var.l = 0; 2771 var.unusable = 0; 2772 var.type = 0x3; 2773 var.avl = 0; 2774 if (save->base & 0xf) 2775 printk_once(KERN_WARNING "kvm: segment base is not " 2776 "paragraph aligned when entering " 2777 "protected mode (seg=%d)", seg); 2778 } 2779 2780 vmcs_write16(sf->selector, var.selector); 2781 vmcs_writel(sf->base, var.base); 2782 vmcs_write32(sf->limit, var.limit); 2783 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2784 } 2785 2786 static void enter_rmode(struct kvm_vcpu *vcpu) 2787 { 2788 unsigned long flags; 2789 struct vcpu_vmx *vmx = to_vmx(vcpu); 2790 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2791 2792 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2793 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2794 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2795 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2796 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2797 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2798 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2799 2800 vmx->rmode.vm86_active = 1; 2801 2802 /* 2803 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2804 * vcpu. Warn the user that an update is overdue. 2805 */ 2806 if (!kvm_vmx->tss_addr) 2807 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2808 "called before entering vcpu\n"); 2809 2810 vmx_segment_cache_clear(vmx); 2811 2812 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2813 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2814 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2815 2816 flags = vmcs_readl(GUEST_RFLAGS); 2817 vmx->rmode.save_rflags = flags; 2818 2819 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2820 2821 vmcs_writel(GUEST_RFLAGS, flags); 2822 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2823 update_exception_bitmap(vcpu); 2824 2825 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2826 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2827 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2828 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2829 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2830 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2831 2832 kvm_mmu_reset_context(vcpu); 2833 } 2834 2835 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2836 { 2837 struct vcpu_vmx *vmx = to_vmx(vcpu); 2838 struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER); 2839 2840 /* Nothing to do if hardware doesn't support EFER. */ 2841 if (!msr) 2842 return 0; 2843 2844 vcpu->arch.efer = efer; 2845 if (efer & EFER_LMA) { 2846 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2847 msr->data = efer; 2848 } else { 2849 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2850 2851 msr->data = efer & ~EFER_LME; 2852 } 2853 setup_msrs(vmx); 2854 return 0; 2855 } 2856 2857 #ifdef CONFIG_X86_64 2858 2859 static void enter_lmode(struct kvm_vcpu *vcpu) 2860 { 2861 u32 guest_tr_ar; 2862 2863 vmx_segment_cache_clear(to_vmx(vcpu)); 2864 2865 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2866 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2867 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2868 __func__); 2869 vmcs_write32(GUEST_TR_AR_BYTES, 2870 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2871 | VMX_AR_TYPE_BUSY_64_TSS); 2872 } 2873 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2874 } 2875 2876 static void exit_lmode(struct kvm_vcpu *vcpu) 2877 { 2878 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2879 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2880 } 2881 2882 #endif 2883 2884 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu) 2885 { 2886 struct vcpu_vmx *vmx = to_vmx(vcpu); 2887 2888 /* 2889 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as 2890 * the CPU is not required to invalidate guest-physical mappings on 2891 * VM-Entry, even if VPID is disabled. Guest-physical mappings are 2892 * associated with the root EPT structure and not any particular VPID 2893 * (INVVPID also isn't required to invalidate guest-physical mappings). 2894 */ 2895 if (enable_ept) { 2896 ept_sync_global(); 2897 } else if (enable_vpid) { 2898 if (cpu_has_vmx_invvpid_global()) { 2899 vpid_sync_vcpu_global(); 2900 } else { 2901 vpid_sync_vcpu_single(vmx->vpid); 2902 vpid_sync_vcpu_single(vmx->nested.vpid02); 2903 } 2904 } 2905 } 2906 2907 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu) 2908 { 2909 struct kvm_mmu *mmu = vcpu->arch.mmu; 2910 u64 root_hpa = mmu->root_hpa; 2911 2912 /* No flush required if the current context is invalid. */ 2913 if (!VALID_PAGE(root_hpa)) 2914 return; 2915 2916 if (enable_ept) 2917 ept_sync_context(construct_eptp(vcpu, root_hpa, 2918 mmu->shadow_root_level)); 2919 else if (!is_guest_mode(vcpu)) 2920 vpid_sync_context(to_vmx(vcpu)->vpid); 2921 else 2922 vpid_sync_context(nested_get_vpid02(vcpu)); 2923 } 2924 2925 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2926 { 2927 /* 2928 * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in 2929 * vmx_flush_tlb_guest() for an explanation of why this is ok. 2930 */ 2931 vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr); 2932 } 2933 2934 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu) 2935 { 2936 /* 2937 * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0 2938 * or a vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit 2939 * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is 2940 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed), 2941 * i.e. no explicit INVVPID is necessary. 2942 */ 2943 vpid_sync_context(to_vmx(vcpu)->vpid); 2944 } 2945 2946 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu) 2947 { 2948 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2949 2950 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2951 return; 2952 2953 if (is_pae_paging(vcpu)) { 2954 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2955 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2956 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2957 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2958 } 2959 } 2960 2961 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2962 { 2963 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2964 2965 if (WARN_ON_ONCE(!is_pae_paging(vcpu))) 2966 return; 2967 2968 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2969 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2970 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2971 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2972 2973 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2974 } 2975 2976 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2977 unsigned long cr0, 2978 struct kvm_vcpu *vcpu) 2979 { 2980 struct vcpu_vmx *vmx = to_vmx(vcpu); 2981 2982 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2983 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2984 if (!(cr0 & X86_CR0_PG)) { 2985 /* From paging/starting to nonpaging */ 2986 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2987 CPU_BASED_CR3_STORE_EXITING); 2988 vcpu->arch.cr0 = cr0; 2989 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2990 } else if (!is_paging(vcpu)) { 2991 /* From nonpaging to paging */ 2992 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2993 CPU_BASED_CR3_STORE_EXITING); 2994 vcpu->arch.cr0 = cr0; 2995 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2996 } 2997 2998 if (!(cr0 & X86_CR0_WP)) 2999 *hw_cr0 &= ~X86_CR0_WP; 3000 } 3001 3002 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 3003 { 3004 struct vcpu_vmx *vmx = to_vmx(vcpu); 3005 unsigned long hw_cr0; 3006 3007 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 3008 if (is_unrestricted_guest(vcpu)) 3009 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 3010 else { 3011 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 3012 3013 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 3014 enter_pmode(vcpu); 3015 3016 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 3017 enter_rmode(vcpu); 3018 } 3019 3020 #ifdef CONFIG_X86_64 3021 if (vcpu->arch.efer & EFER_LME) { 3022 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 3023 enter_lmode(vcpu); 3024 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 3025 exit_lmode(vcpu); 3026 } 3027 #endif 3028 3029 if (enable_ept && !is_unrestricted_guest(vcpu)) 3030 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 3031 3032 vmcs_writel(CR0_READ_SHADOW, cr0); 3033 vmcs_writel(GUEST_CR0, hw_cr0); 3034 vcpu->arch.cr0 = cr0; 3035 kvm_register_mark_available(vcpu, VCPU_EXREG_CR0); 3036 3037 /* depends on vcpu->arch.cr0 to be set to a new value */ 3038 vmx->emulation_required = emulation_required(vcpu); 3039 } 3040 3041 static int vmx_get_max_tdp_level(void) 3042 { 3043 if (cpu_has_vmx_ept_5levels()) 3044 return 5; 3045 return 4; 3046 } 3047 3048 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa, 3049 int root_level) 3050 { 3051 u64 eptp = VMX_EPTP_MT_WB; 3052 3053 eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 3054 3055 if (enable_ept_ad_bits && 3056 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 3057 eptp |= VMX_EPTP_AD_ENABLE_BIT; 3058 eptp |= (root_hpa & PAGE_MASK); 3059 3060 return eptp; 3061 } 3062 3063 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd, 3064 int pgd_level) 3065 { 3066 struct kvm *kvm = vcpu->kvm; 3067 bool update_guest_cr3 = true; 3068 unsigned long guest_cr3; 3069 u64 eptp; 3070 3071 if (enable_ept) { 3072 eptp = construct_eptp(vcpu, pgd, pgd_level); 3073 vmcs_write64(EPT_POINTER, eptp); 3074 3075 if (kvm_x86_ops.tlb_remote_flush) { 3076 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3077 to_vmx(vcpu)->ept_pointer = eptp; 3078 to_kvm_vmx(kvm)->ept_pointers_match 3079 = EPT_POINTERS_CHECK; 3080 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3081 } 3082 3083 if (!enable_unrestricted_guest && !is_paging(vcpu)) 3084 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3085 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 3086 guest_cr3 = vcpu->arch.cr3; 3087 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3088 update_guest_cr3 = false; 3089 vmx_ept_load_pdptrs(vcpu); 3090 } else { 3091 guest_cr3 = pgd; 3092 } 3093 3094 if (update_guest_cr3) 3095 vmcs_writel(GUEST_CR3, guest_cr3); 3096 } 3097 3098 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3099 { 3100 struct vcpu_vmx *vmx = to_vmx(vcpu); 3101 /* 3102 * Pass through host's Machine Check Enable value to hw_cr4, which 3103 * is in force while we are in guest mode. Do not let guests control 3104 * this bit, even if host CR4.MCE == 0. 3105 */ 3106 unsigned long hw_cr4; 3107 3108 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3109 if (is_unrestricted_guest(vcpu)) 3110 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3111 else if (vmx->rmode.vm86_active) 3112 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3113 else 3114 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3115 3116 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3117 if (cr4 & X86_CR4_UMIP) { 3118 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3119 hw_cr4 &= ~X86_CR4_UMIP; 3120 } else if (!is_guest_mode(vcpu) || 3121 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3122 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3123 } 3124 } 3125 3126 if (cr4 & X86_CR4_VMXE) { 3127 /* 3128 * To use VMXON (and later other VMX instructions), a guest 3129 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3130 * So basically the check on whether to allow nested VMX 3131 * is here. We operate under the default treatment of SMM, 3132 * so VMX cannot be enabled under SMM. 3133 */ 3134 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3135 return 1; 3136 } 3137 3138 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3139 return 1; 3140 3141 vcpu->arch.cr4 = cr4; 3142 kvm_register_mark_available(vcpu, VCPU_EXREG_CR4); 3143 3144 if (!is_unrestricted_guest(vcpu)) { 3145 if (enable_ept) { 3146 if (!is_paging(vcpu)) { 3147 hw_cr4 &= ~X86_CR4_PAE; 3148 hw_cr4 |= X86_CR4_PSE; 3149 } else if (!(cr4 & X86_CR4_PAE)) { 3150 hw_cr4 &= ~X86_CR4_PAE; 3151 } 3152 } 3153 3154 /* 3155 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3156 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3157 * to be manually disabled when guest switches to non-paging 3158 * mode. 3159 * 3160 * If !enable_unrestricted_guest, the CPU is always running 3161 * with CR0.PG=1 and CR4 needs to be modified. 3162 * If enable_unrestricted_guest, the CPU automatically 3163 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3164 */ 3165 if (!is_paging(vcpu)) 3166 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3167 } 3168 3169 vmcs_writel(CR4_READ_SHADOW, cr4); 3170 vmcs_writel(GUEST_CR4, hw_cr4); 3171 return 0; 3172 } 3173 3174 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3175 { 3176 struct vcpu_vmx *vmx = to_vmx(vcpu); 3177 u32 ar; 3178 3179 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3180 *var = vmx->rmode.segs[seg]; 3181 if (seg == VCPU_SREG_TR 3182 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3183 return; 3184 var->base = vmx_read_guest_seg_base(vmx, seg); 3185 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3186 return; 3187 } 3188 var->base = vmx_read_guest_seg_base(vmx, seg); 3189 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3190 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3191 ar = vmx_read_guest_seg_ar(vmx, seg); 3192 var->unusable = (ar >> 16) & 1; 3193 var->type = ar & 15; 3194 var->s = (ar >> 4) & 1; 3195 var->dpl = (ar >> 5) & 3; 3196 /* 3197 * Some userspaces do not preserve unusable property. Since usable 3198 * segment has to be present according to VMX spec we can use present 3199 * property to amend userspace bug by making unusable segment always 3200 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3201 * segment as unusable. 3202 */ 3203 var->present = !var->unusable; 3204 var->avl = (ar >> 12) & 1; 3205 var->l = (ar >> 13) & 1; 3206 var->db = (ar >> 14) & 1; 3207 var->g = (ar >> 15) & 1; 3208 } 3209 3210 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3211 { 3212 struct kvm_segment s; 3213 3214 if (to_vmx(vcpu)->rmode.vm86_active) { 3215 vmx_get_segment(vcpu, &s, seg); 3216 return s.base; 3217 } 3218 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3219 } 3220 3221 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3222 { 3223 struct vcpu_vmx *vmx = to_vmx(vcpu); 3224 3225 if (unlikely(vmx->rmode.vm86_active)) 3226 return 0; 3227 else { 3228 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3229 return VMX_AR_DPL(ar); 3230 } 3231 } 3232 3233 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3234 { 3235 u32 ar; 3236 3237 if (var->unusable || !var->present) 3238 ar = 1 << 16; 3239 else { 3240 ar = var->type & 15; 3241 ar |= (var->s & 1) << 4; 3242 ar |= (var->dpl & 3) << 5; 3243 ar |= (var->present & 1) << 7; 3244 ar |= (var->avl & 1) << 12; 3245 ar |= (var->l & 1) << 13; 3246 ar |= (var->db & 1) << 14; 3247 ar |= (var->g & 1) << 15; 3248 } 3249 3250 return ar; 3251 } 3252 3253 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3254 { 3255 struct vcpu_vmx *vmx = to_vmx(vcpu); 3256 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3257 3258 vmx_segment_cache_clear(vmx); 3259 3260 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3261 vmx->rmode.segs[seg] = *var; 3262 if (seg == VCPU_SREG_TR) 3263 vmcs_write16(sf->selector, var->selector); 3264 else if (var->s) 3265 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3266 goto out; 3267 } 3268 3269 vmcs_writel(sf->base, var->base); 3270 vmcs_write32(sf->limit, var->limit); 3271 vmcs_write16(sf->selector, var->selector); 3272 3273 /* 3274 * Fix the "Accessed" bit in AR field of segment registers for older 3275 * qemu binaries. 3276 * IA32 arch specifies that at the time of processor reset the 3277 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3278 * is setting it to 0 in the userland code. This causes invalid guest 3279 * state vmexit when "unrestricted guest" mode is turned on. 3280 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3281 * tree. Newer qemu binaries with that qemu fix would not need this 3282 * kvm hack. 3283 */ 3284 if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR)) 3285 var->type |= 0x1; /* Accessed */ 3286 3287 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3288 3289 out: 3290 vmx->emulation_required = emulation_required(vcpu); 3291 } 3292 3293 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3294 { 3295 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3296 3297 *db = (ar >> 14) & 1; 3298 *l = (ar >> 13) & 1; 3299 } 3300 3301 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3302 { 3303 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3304 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3305 } 3306 3307 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3308 { 3309 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3310 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3311 } 3312 3313 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3314 { 3315 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3316 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3317 } 3318 3319 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3320 { 3321 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3322 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3323 } 3324 3325 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3326 { 3327 struct kvm_segment var; 3328 u32 ar; 3329 3330 vmx_get_segment(vcpu, &var, seg); 3331 var.dpl = 0x3; 3332 if (seg == VCPU_SREG_CS) 3333 var.type = 0x3; 3334 ar = vmx_segment_access_rights(&var); 3335 3336 if (var.base != (var.selector << 4)) 3337 return false; 3338 if (var.limit != 0xffff) 3339 return false; 3340 if (ar != 0xf3) 3341 return false; 3342 3343 return true; 3344 } 3345 3346 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3347 { 3348 struct kvm_segment cs; 3349 unsigned int cs_rpl; 3350 3351 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3352 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3353 3354 if (cs.unusable) 3355 return false; 3356 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3357 return false; 3358 if (!cs.s) 3359 return false; 3360 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3361 if (cs.dpl > cs_rpl) 3362 return false; 3363 } else { 3364 if (cs.dpl != cs_rpl) 3365 return false; 3366 } 3367 if (!cs.present) 3368 return false; 3369 3370 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3371 return true; 3372 } 3373 3374 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3375 { 3376 struct kvm_segment ss; 3377 unsigned int ss_rpl; 3378 3379 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3380 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3381 3382 if (ss.unusable) 3383 return true; 3384 if (ss.type != 3 && ss.type != 7) 3385 return false; 3386 if (!ss.s) 3387 return false; 3388 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3389 return false; 3390 if (!ss.present) 3391 return false; 3392 3393 return true; 3394 } 3395 3396 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3397 { 3398 struct kvm_segment var; 3399 unsigned int rpl; 3400 3401 vmx_get_segment(vcpu, &var, seg); 3402 rpl = var.selector & SEGMENT_RPL_MASK; 3403 3404 if (var.unusable) 3405 return true; 3406 if (!var.s) 3407 return false; 3408 if (!var.present) 3409 return false; 3410 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3411 if (var.dpl < rpl) /* DPL < RPL */ 3412 return false; 3413 } 3414 3415 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3416 * rights flags 3417 */ 3418 return true; 3419 } 3420 3421 static bool tr_valid(struct kvm_vcpu *vcpu) 3422 { 3423 struct kvm_segment tr; 3424 3425 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3426 3427 if (tr.unusable) 3428 return false; 3429 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3430 return false; 3431 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3432 return false; 3433 if (!tr.present) 3434 return false; 3435 3436 return true; 3437 } 3438 3439 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3440 { 3441 struct kvm_segment ldtr; 3442 3443 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3444 3445 if (ldtr.unusable) 3446 return true; 3447 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3448 return false; 3449 if (ldtr.type != 2) 3450 return false; 3451 if (!ldtr.present) 3452 return false; 3453 3454 return true; 3455 } 3456 3457 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3458 { 3459 struct kvm_segment cs, ss; 3460 3461 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3462 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3463 3464 return ((cs.selector & SEGMENT_RPL_MASK) == 3465 (ss.selector & SEGMENT_RPL_MASK)); 3466 } 3467 3468 /* 3469 * Check if guest state is valid. Returns true if valid, false if 3470 * not. 3471 * We assume that registers are always usable 3472 */ 3473 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu) 3474 { 3475 /* real mode guest state checks */ 3476 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3477 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3478 return false; 3479 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3480 return false; 3481 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3482 return false; 3483 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3484 return false; 3485 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3486 return false; 3487 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3488 return false; 3489 } else { 3490 /* protected mode guest state checks */ 3491 if (!cs_ss_rpl_check(vcpu)) 3492 return false; 3493 if (!code_segment_valid(vcpu)) 3494 return false; 3495 if (!stack_segment_valid(vcpu)) 3496 return false; 3497 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3498 return false; 3499 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3500 return false; 3501 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3502 return false; 3503 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3504 return false; 3505 if (!tr_valid(vcpu)) 3506 return false; 3507 if (!ldtr_valid(vcpu)) 3508 return false; 3509 } 3510 /* TODO: 3511 * - Add checks on RIP 3512 * - Add checks on RFLAGS 3513 */ 3514 3515 return true; 3516 } 3517 3518 static int init_rmode_tss(struct kvm *kvm) 3519 { 3520 gfn_t fn; 3521 u16 data = 0; 3522 int idx, r; 3523 3524 idx = srcu_read_lock(&kvm->srcu); 3525 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3526 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3527 if (r < 0) 3528 goto out; 3529 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3530 r = kvm_write_guest_page(kvm, fn++, &data, 3531 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3532 if (r < 0) 3533 goto out; 3534 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3535 if (r < 0) 3536 goto out; 3537 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3538 if (r < 0) 3539 goto out; 3540 data = ~0; 3541 r = kvm_write_guest_page(kvm, fn, &data, 3542 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3543 sizeof(u8)); 3544 out: 3545 srcu_read_unlock(&kvm->srcu, idx); 3546 return r; 3547 } 3548 3549 static int init_rmode_identity_map(struct kvm *kvm) 3550 { 3551 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3552 int i, r = 0; 3553 kvm_pfn_t identity_map_pfn; 3554 u32 tmp; 3555 3556 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3557 mutex_lock(&kvm->slots_lock); 3558 3559 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3560 goto out; 3561 3562 if (!kvm_vmx->ept_identity_map_addr) 3563 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3564 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3565 3566 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3567 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3568 if (r < 0) 3569 goto out; 3570 3571 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3572 if (r < 0) 3573 goto out; 3574 /* Set up identity-mapping pagetable for EPT in real mode */ 3575 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3576 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3577 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3578 r = kvm_write_guest_page(kvm, identity_map_pfn, 3579 &tmp, i * sizeof(tmp), sizeof(tmp)); 3580 if (r < 0) 3581 goto out; 3582 } 3583 kvm_vmx->ept_identity_pagetable_done = true; 3584 3585 out: 3586 mutex_unlock(&kvm->slots_lock); 3587 return r; 3588 } 3589 3590 static void seg_setup(int seg) 3591 { 3592 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3593 unsigned int ar; 3594 3595 vmcs_write16(sf->selector, 0); 3596 vmcs_writel(sf->base, 0); 3597 vmcs_write32(sf->limit, 0xffff); 3598 ar = 0x93; 3599 if (seg == VCPU_SREG_CS) 3600 ar |= 0x08; /* code segment */ 3601 3602 vmcs_write32(sf->ar_bytes, ar); 3603 } 3604 3605 static int alloc_apic_access_page(struct kvm *kvm) 3606 { 3607 struct page *page; 3608 int r = 0; 3609 3610 mutex_lock(&kvm->slots_lock); 3611 if (kvm->arch.apic_access_page_done) 3612 goto out; 3613 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3614 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3615 if (r) 3616 goto out; 3617 3618 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3619 if (is_error_page(page)) { 3620 r = -EFAULT; 3621 goto out; 3622 } 3623 3624 /* 3625 * Do not pin the page in memory, so that memory hot-unplug 3626 * is able to migrate it. 3627 */ 3628 put_page(page); 3629 kvm->arch.apic_access_page_done = true; 3630 out: 3631 mutex_unlock(&kvm->slots_lock); 3632 return r; 3633 } 3634 3635 int allocate_vpid(void) 3636 { 3637 int vpid; 3638 3639 if (!enable_vpid) 3640 return 0; 3641 spin_lock(&vmx_vpid_lock); 3642 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3643 if (vpid < VMX_NR_VPIDS) 3644 __set_bit(vpid, vmx_vpid_bitmap); 3645 else 3646 vpid = 0; 3647 spin_unlock(&vmx_vpid_lock); 3648 return vpid; 3649 } 3650 3651 void free_vpid(int vpid) 3652 { 3653 if (!enable_vpid || vpid == 0) 3654 return; 3655 spin_lock(&vmx_vpid_lock); 3656 __clear_bit(vpid, vmx_vpid_bitmap); 3657 spin_unlock(&vmx_vpid_lock); 3658 } 3659 3660 static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr) 3661 { 3662 int f = sizeof(unsigned long); 3663 3664 if (msr <= 0x1fff) 3665 __clear_bit(msr, msr_bitmap + 0x000 / f); 3666 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) 3667 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f); 3668 } 3669 3670 static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr) 3671 { 3672 int f = sizeof(unsigned long); 3673 3674 if (msr <= 0x1fff) 3675 __clear_bit(msr, msr_bitmap + 0x800 / f); 3676 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) 3677 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f); 3678 } 3679 3680 static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr) 3681 { 3682 int f = sizeof(unsigned long); 3683 3684 if (msr <= 0x1fff) 3685 __set_bit(msr, msr_bitmap + 0x000 / f); 3686 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) 3687 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f); 3688 } 3689 3690 static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr) 3691 { 3692 int f = sizeof(unsigned long); 3693 3694 if (msr <= 0x1fff) 3695 __set_bit(msr, msr_bitmap + 0x800 / f); 3696 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) 3697 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f); 3698 } 3699 3700 static __always_inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 3701 u32 msr, int type) 3702 { 3703 struct vcpu_vmx *vmx = to_vmx(vcpu); 3704 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3705 3706 if (!cpu_has_vmx_msr_bitmap()) 3707 return; 3708 3709 if (static_branch_unlikely(&enable_evmcs)) 3710 evmcs_touch_msr_bitmap(); 3711 3712 /* 3713 * Mark the desired intercept state in shadow bitmap, this is needed 3714 * for resync when the MSR filters change. 3715 */ 3716 if (is_valid_passthrough_msr(msr)) { 3717 int idx = possible_passthrough_msr_slot(msr); 3718 3719 if (idx != -ENOENT) { 3720 if (type & MSR_TYPE_R) 3721 clear_bit(idx, vmx->shadow_msr_intercept.read); 3722 if (type & MSR_TYPE_W) 3723 clear_bit(idx, vmx->shadow_msr_intercept.write); 3724 } 3725 } 3726 3727 if ((type & MSR_TYPE_R) && 3728 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) { 3729 vmx_set_msr_bitmap_read(msr_bitmap, msr); 3730 type &= ~MSR_TYPE_R; 3731 } 3732 3733 if ((type & MSR_TYPE_W) && 3734 !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) { 3735 vmx_set_msr_bitmap_write(msr_bitmap, msr); 3736 type &= ~MSR_TYPE_W; 3737 } 3738 3739 if (type & MSR_TYPE_R) 3740 vmx_clear_msr_bitmap_read(msr_bitmap, msr); 3741 3742 if (type & MSR_TYPE_W) 3743 vmx_clear_msr_bitmap_write(msr_bitmap, msr); 3744 } 3745 3746 static __always_inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, 3747 u32 msr, int type) 3748 { 3749 struct vcpu_vmx *vmx = to_vmx(vcpu); 3750 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3751 3752 if (!cpu_has_vmx_msr_bitmap()) 3753 return; 3754 3755 if (static_branch_unlikely(&enable_evmcs)) 3756 evmcs_touch_msr_bitmap(); 3757 3758 /* 3759 * Mark the desired intercept state in shadow bitmap, this is needed 3760 * for resync when the MSR filter changes. 3761 */ 3762 if (is_valid_passthrough_msr(msr)) { 3763 int idx = possible_passthrough_msr_slot(msr); 3764 3765 if (idx != -ENOENT) { 3766 if (type & MSR_TYPE_R) 3767 set_bit(idx, vmx->shadow_msr_intercept.read); 3768 if (type & MSR_TYPE_W) 3769 set_bit(idx, vmx->shadow_msr_intercept.write); 3770 } 3771 } 3772 3773 if (type & MSR_TYPE_R) 3774 vmx_set_msr_bitmap_read(msr_bitmap, msr); 3775 3776 if (type & MSR_TYPE_W) 3777 vmx_set_msr_bitmap_write(msr_bitmap, msr); 3778 } 3779 3780 static __always_inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, 3781 u32 msr, int type, bool value) 3782 { 3783 if (value) 3784 vmx_enable_intercept_for_msr(vcpu, msr, type); 3785 else 3786 vmx_disable_intercept_for_msr(vcpu, msr, type); 3787 } 3788 3789 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3790 { 3791 u8 mode = 0; 3792 3793 if (cpu_has_secondary_exec_ctrls() && 3794 (secondary_exec_controls_get(to_vmx(vcpu)) & 3795 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3796 mode |= MSR_BITMAP_MODE_X2APIC; 3797 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3798 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3799 } 3800 3801 return mode; 3802 } 3803 3804 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode) 3805 { 3806 unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap; 3807 unsigned long read_intercept; 3808 int msr; 3809 3810 read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3811 3812 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3813 unsigned int read_idx = msr / BITS_PER_LONG; 3814 unsigned int write_idx = read_idx + (0x800 / sizeof(long)); 3815 3816 msr_bitmap[read_idx] = read_intercept; 3817 msr_bitmap[write_idx] = ~0ul; 3818 } 3819 } 3820 3821 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu, u8 mode) 3822 { 3823 if (!cpu_has_vmx_msr_bitmap()) 3824 return; 3825 3826 vmx_reset_x2apic_msrs(vcpu, mode); 3827 3828 /* 3829 * TPR reads and writes can be virtualized even if virtual interrupt 3830 * delivery is not in use. 3831 */ 3832 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW, 3833 !(mode & MSR_BITMAP_MODE_X2APIC)); 3834 3835 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3836 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW); 3837 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3838 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3839 } 3840 } 3841 3842 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3843 { 3844 struct vcpu_vmx *vmx = to_vmx(vcpu); 3845 u8 mode = vmx_msr_bitmap_mode(vcpu); 3846 u8 changed = mode ^ vmx->msr_bitmap_mode; 3847 3848 if (!changed) 3849 return; 3850 3851 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3852 vmx_update_msr_bitmap_x2apic(vcpu, mode); 3853 3854 vmx->msr_bitmap_mode = mode; 3855 } 3856 3857 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu) 3858 { 3859 struct vcpu_vmx *vmx = to_vmx(vcpu); 3860 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3861 u32 i; 3862 3863 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag); 3864 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag); 3865 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag); 3866 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag); 3867 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3868 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3869 vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3870 } 3871 } 3872 3873 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3874 { 3875 struct vcpu_vmx *vmx = to_vmx(vcpu); 3876 void *vapic_page; 3877 u32 vppr; 3878 int rvi; 3879 3880 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3881 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3882 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3883 return false; 3884 3885 rvi = vmx_get_rvi(); 3886 3887 vapic_page = vmx->nested.virtual_apic_map.hva; 3888 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3889 3890 return ((rvi & 0xf0) > (vppr & 0xf0)); 3891 } 3892 3893 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu) 3894 { 3895 struct vcpu_vmx *vmx = to_vmx(vcpu); 3896 u32 i; 3897 3898 /* 3899 * Set intercept permissions for all potentially passed through MSRs 3900 * again. They will automatically get filtered through the MSR filter, 3901 * so we are back in sync after this. 3902 */ 3903 for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) { 3904 u32 msr = vmx_possible_passthrough_msrs[i]; 3905 bool read = test_bit(i, vmx->shadow_msr_intercept.read); 3906 bool write = test_bit(i, vmx->shadow_msr_intercept.write); 3907 3908 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read); 3909 vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write); 3910 } 3911 3912 pt_update_intercept_for_msr(vcpu); 3913 vmx_update_msr_bitmap_x2apic(vcpu, vmx_msr_bitmap_mode(vcpu)); 3914 } 3915 3916 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3917 bool nested) 3918 { 3919 #ifdef CONFIG_SMP 3920 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3921 3922 if (vcpu->mode == IN_GUEST_MODE) { 3923 /* 3924 * The vector of interrupt to be delivered to vcpu had 3925 * been set in PIR before this function. 3926 * 3927 * Following cases will be reached in this block, and 3928 * we always send a notification event in all cases as 3929 * explained below. 3930 * 3931 * Case 1: vcpu keeps in non-root mode. Sending a 3932 * notification event posts the interrupt to vcpu. 3933 * 3934 * Case 2: vcpu exits to root mode and is still 3935 * runnable. PIR will be synced to vIRR before the 3936 * next vcpu entry. Sending a notification event in 3937 * this case has no effect, as vcpu is not in root 3938 * mode. 3939 * 3940 * Case 3: vcpu exits to root mode and is blocked. 3941 * vcpu_block() has already synced PIR to vIRR and 3942 * never blocks vcpu if vIRR is not cleared. Therefore, 3943 * a blocked vcpu here does not wait for any requested 3944 * interrupts in PIR, and sending a notification event 3945 * which has no effect is safe here. 3946 */ 3947 3948 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3949 return true; 3950 } 3951 #endif 3952 return false; 3953 } 3954 3955 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3956 int vector) 3957 { 3958 struct vcpu_vmx *vmx = to_vmx(vcpu); 3959 3960 if (is_guest_mode(vcpu) && 3961 vector == vmx->nested.posted_intr_nv) { 3962 /* 3963 * If a posted intr is not recognized by hardware, 3964 * we will accomplish it in the next vmentry. 3965 */ 3966 vmx->nested.pi_pending = true; 3967 kvm_make_request(KVM_REQ_EVENT, vcpu); 3968 /* the PIR and ON have been set by L1. */ 3969 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3970 kvm_vcpu_kick(vcpu); 3971 return 0; 3972 } 3973 return -1; 3974 } 3975 /* 3976 * Send interrupt to vcpu via posted interrupt way. 3977 * 1. If target vcpu is running(non-root mode), send posted interrupt 3978 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3979 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3980 * interrupt from PIR in next vmentry. 3981 */ 3982 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3983 { 3984 struct vcpu_vmx *vmx = to_vmx(vcpu); 3985 int r; 3986 3987 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3988 if (!r) 3989 return 0; 3990 3991 if (!vcpu->arch.apicv_active) 3992 return -1; 3993 3994 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3995 return 0; 3996 3997 /* If a previous notification has sent the IPI, nothing to do. */ 3998 if (pi_test_and_set_on(&vmx->pi_desc)) 3999 return 0; 4000 4001 if (vcpu != kvm_get_running_vcpu() && 4002 !kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 4003 kvm_vcpu_kick(vcpu); 4004 4005 return 0; 4006 } 4007 4008 /* 4009 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 4010 * will not change in the lifetime of the guest. 4011 * Note that host-state that does change is set elsewhere. E.g., host-state 4012 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 4013 */ 4014 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 4015 { 4016 u32 low32, high32; 4017 unsigned long tmpl; 4018 unsigned long cr0, cr3, cr4; 4019 4020 cr0 = read_cr0(); 4021 WARN_ON(cr0 & X86_CR0_TS); 4022 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 4023 4024 /* 4025 * Save the most likely value for this task's CR3 in the VMCS. 4026 * We can't use __get_current_cr3_fast() because we're not atomic. 4027 */ 4028 cr3 = __read_cr3(); 4029 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 4030 vmx->loaded_vmcs->host_state.cr3 = cr3; 4031 4032 /* Save the most likely value for this task's CR4 in the VMCS. */ 4033 cr4 = cr4_read_shadow(); 4034 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 4035 vmx->loaded_vmcs->host_state.cr4 = cr4; 4036 4037 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 4038 #ifdef CONFIG_X86_64 4039 /* 4040 * Load null selectors, so we can avoid reloading them in 4041 * vmx_prepare_switch_to_host(), in case userspace uses 4042 * the null selectors too (the expected case). 4043 */ 4044 vmcs_write16(HOST_DS_SELECTOR, 0); 4045 vmcs_write16(HOST_ES_SELECTOR, 0); 4046 #else 4047 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 4048 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 4049 #endif 4050 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 4051 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 4052 4053 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 4054 4055 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 4056 4057 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 4058 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 4059 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 4060 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 4061 4062 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 4063 rdmsr(MSR_IA32_CR_PAT, low32, high32); 4064 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 4065 } 4066 4067 if (cpu_has_load_ia32_efer()) 4068 vmcs_write64(HOST_IA32_EFER, host_efer); 4069 } 4070 4071 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 4072 { 4073 struct kvm_vcpu *vcpu = &vmx->vcpu; 4074 4075 vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS & 4076 ~vcpu->arch.cr4_guest_rsvd_bits; 4077 if (!enable_ept) 4078 vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE; 4079 if (is_guest_mode(&vmx->vcpu)) 4080 vcpu->arch.cr4_guest_owned_bits &= 4081 ~get_vmcs12(vcpu)->cr4_guest_host_mask; 4082 vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits); 4083 } 4084 4085 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 4086 { 4087 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 4088 4089 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 4090 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 4091 4092 if (!enable_vnmi) 4093 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 4094 4095 if (!enable_preemption_timer) 4096 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 4097 4098 return pin_based_exec_ctrl; 4099 } 4100 4101 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 4102 { 4103 struct vcpu_vmx *vmx = to_vmx(vcpu); 4104 4105 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4106 if (cpu_has_secondary_exec_ctrls()) { 4107 if (kvm_vcpu_apicv_active(vcpu)) 4108 secondary_exec_controls_setbit(vmx, 4109 SECONDARY_EXEC_APIC_REGISTER_VIRT | 4110 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4111 else 4112 secondary_exec_controls_clearbit(vmx, 4113 SECONDARY_EXEC_APIC_REGISTER_VIRT | 4114 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4115 } 4116 4117 if (cpu_has_vmx_msr_bitmap()) 4118 vmx_update_msr_bitmap(vcpu); 4119 } 4120 4121 u32 vmx_exec_control(struct vcpu_vmx *vmx) 4122 { 4123 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 4124 4125 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 4126 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 4127 4128 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 4129 exec_control &= ~CPU_BASED_TPR_SHADOW; 4130 #ifdef CONFIG_X86_64 4131 exec_control |= CPU_BASED_CR8_STORE_EXITING | 4132 CPU_BASED_CR8_LOAD_EXITING; 4133 #endif 4134 } 4135 if (!enable_ept) 4136 exec_control |= CPU_BASED_CR3_STORE_EXITING | 4137 CPU_BASED_CR3_LOAD_EXITING | 4138 CPU_BASED_INVLPG_EXITING; 4139 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 4140 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 4141 CPU_BASED_MONITOR_EXITING); 4142 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 4143 exec_control &= ~CPU_BASED_HLT_EXITING; 4144 return exec_control; 4145 } 4146 4147 /* 4148 * Adjust a single secondary execution control bit to intercept/allow an 4149 * instruction in the guest. This is usually done based on whether or not a 4150 * feature has been exposed to the guest in order to correctly emulate faults. 4151 */ 4152 static inline void 4153 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control, 4154 u32 control, bool enabled, bool exiting) 4155 { 4156 /* 4157 * If the control is for an opt-in feature, clear the control if the 4158 * feature is not exposed to the guest, i.e. not enabled. If the 4159 * control is opt-out, i.e. an exiting control, clear the control if 4160 * the feature _is_ exposed to the guest, i.e. exiting/interception is 4161 * disabled for the associated instruction. Note, the caller is 4162 * responsible presetting exec_control to set all supported bits. 4163 */ 4164 if (enabled == exiting) 4165 *exec_control &= ~control; 4166 4167 /* 4168 * Update the nested MSR settings so that a nested VMM can/can't set 4169 * controls for features that are/aren't exposed to the guest. 4170 */ 4171 if (nested) { 4172 if (enabled) 4173 vmx->nested.msrs.secondary_ctls_high |= control; 4174 else 4175 vmx->nested.msrs.secondary_ctls_high &= ~control; 4176 } 4177 } 4178 4179 /* 4180 * Wrapper macro for the common case of adjusting a secondary execution control 4181 * based on a single guest CPUID bit, with a dedicated feature bit. This also 4182 * verifies that the control is actually supported by KVM and hardware. 4183 */ 4184 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \ 4185 ({ \ 4186 bool __enabled; \ 4187 \ 4188 if (cpu_has_vmx_##name()) { \ 4189 __enabled = guest_cpuid_has(&(vmx)->vcpu, \ 4190 X86_FEATURE_##feat_name); \ 4191 vmx_adjust_secondary_exec_control(vmx, exec_control, \ 4192 SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \ 4193 } \ 4194 }) 4195 4196 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */ 4197 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \ 4198 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false) 4199 4200 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \ 4201 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true) 4202 4203 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 4204 { 4205 struct kvm_vcpu *vcpu = &vmx->vcpu; 4206 4207 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 4208 4209 if (vmx_pt_mode_is_system()) 4210 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 4211 if (!cpu_need_virtualize_apic_accesses(vcpu)) 4212 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4213 if (vmx->vpid == 0) 4214 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4215 if (!enable_ept) { 4216 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4217 enable_unrestricted_guest = 0; 4218 } 4219 if (!enable_unrestricted_guest) 4220 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4221 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4222 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4223 if (!kvm_vcpu_apicv_active(vcpu)) 4224 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4225 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4226 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4227 4228 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4229 * in vmx_set_cr4. */ 4230 exec_control &= ~SECONDARY_EXEC_DESC; 4231 4232 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4233 (handle_vmptrld). 4234 We can NOT enable shadow_vmcs here because we don't have yet 4235 a current VMCS12 4236 */ 4237 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4238 4239 if (!enable_pml) 4240 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4241 4242 if (cpu_has_vmx_xsaves()) { 4243 /* Exposing XSAVES only when XSAVE is exposed */ 4244 bool xsaves_enabled = 4245 boot_cpu_has(X86_FEATURE_XSAVE) && 4246 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4247 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4248 4249 vcpu->arch.xsaves_enabled = xsaves_enabled; 4250 4251 vmx_adjust_secondary_exec_control(vmx, &exec_control, 4252 SECONDARY_EXEC_XSAVES, 4253 xsaves_enabled, false); 4254 } 4255 4256 vmx_adjust_sec_exec_feature(vmx, &exec_control, rdtscp, RDTSCP); 4257 4258 /* 4259 * Expose INVPCID if and only if PCID is also exposed to the guest. 4260 * INVPCID takes a #UD when it's disabled in the VMCS, but a #GP or #PF 4261 * if CR4.PCIDE=0. Enumerating CPUID.INVPCID=1 would lead to incorrect 4262 * behavior from the guest perspective (it would expect #GP or #PF). 4263 */ 4264 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 4265 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4266 vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID); 4267 4268 4269 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND); 4270 vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED); 4271 4272 vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG, 4273 ENABLE_USR_WAIT_PAUSE, false); 4274 4275 vmx->secondary_exec_control = exec_control; 4276 } 4277 4278 static void ept_set_mmio_spte_mask(void) 4279 { 4280 /* 4281 * EPT Misconfigurations can be generated if the value of bits 2:0 4282 * of an EPT paging-structure entry is 110b (write/execute). 4283 */ 4284 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 0); 4285 } 4286 4287 #define VMX_XSS_EXIT_BITMAP 0 4288 4289 /* 4290 * Noting that the initialization of Guest-state Area of VMCS is in 4291 * vmx_vcpu_reset(). 4292 */ 4293 static void init_vmcs(struct vcpu_vmx *vmx) 4294 { 4295 if (nested) 4296 nested_vmx_set_vmcs_shadowing_bitmap(); 4297 4298 if (cpu_has_vmx_msr_bitmap()) 4299 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4300 4301 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4302 4303 /* Control */ 4304 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4305 4306 exec_controls_set(vmx, vmx_exec_control(vmx)); 4307 4308 if (cpu_has_secondary_exec_ctrls()) { 4309 vmx_compute_secondary_exec_control(vmx); 4310 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4311 } 4312 4313 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4314 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4315 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4316 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4317 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4318 4319 vmcs_write16(GUEST_INTR_STATUS, 0); 4320 4321 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4322 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4323 } 4324 4325 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4326 vmcs_write32(PLE_GAP, ple_gap); 4327 vmx->ple_window = ple_window; 4328 vmx->ple_window_dirty = true; 4329 } 4330 4331 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4332 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4333 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4334 4335 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4336 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4337 vmx_set_constant_host_state(vmx); 4338 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4339 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4340 4341 if (cpu_has_vmx_vmfunc()) 4342 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4343 4344 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4345 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4346 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4347 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4348 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4349 4350 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4351 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4352 4353 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4354 4355 /* 22.2.1, 20.8.1 */ 4356 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4357 4358 vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS; 4359 vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits); 4360 4361 set_cr4_guest_host_mask(vmx); 4362 4363 if (vmx->vpid != 0) 4364 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4365 4366 if (cpu_has_vmx_xsaves()) 4367 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4368 4369 if (enable_pml) { 4370 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4371 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4372 } 4373 4374 if (cpu_has_vmx_encls_vmexit()) 4375 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4376 4377 if (vmx_pt_mode_is_host_guest()) { 4378 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4379 /* Bit[6~0] are forced to 1, writes are ignored. */ 4380 vmx->pt_desc.guest.output_mask = 0x7F; 4381 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4382 } 4383 } 4384 4385 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4386 { 4387 struct vcpu_vmx *vmx = to_vmx(vcpu); 4388 struct msr_data apic_base_msr; 4389 u64 cr0; 4390 4391 vmx->rmode.vm86_active = 0; 4392 vmx->spec_ctrl = 0; 4393 4394 vmx->msr_ia32_umwait_control = 0; 4395 4396 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4397 vmx->hv_deadline_tsc = -1; 4398 kvm_set_cr8(vcpu, 0); 4399 4400 if (!init_event) { 4401 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4402 MSR_IA32_APICBASE_ENABLE; 4403 if (kvm_vcpu_is_reset_bsp(vcpu)) 4404 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4405 apic_base_msr.host_initiated = true; 4406 kvm_set_apic_base(vcpu, &apic_base_msr); 4407 } 4408 4409 vmx_segment_cache_clear(vmx); 4410 4411 seg_setup(VCPU_SREG_CS); 4412 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4413 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4414 4415 seg_setup(VCPU_SREG_DS); 4416 seg_setup(VCPU_SREG_ES); 4417 seg_setup(VCPU_SREG_FS); 4418 seg_setup(VCPU_SREG_GS); 4419 seg_setup(VCPU_SREG_SS); 4420 4421 vmcs_write16(GUEST_TR_SELECTOR, 0); 4422 vmcs_writel(GUEST_TR_BASE, 0); 4423 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4424 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4425 4426 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4427 vmcs_writel(GUEST_LDTR_BASE, 0); 4428 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4429 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4430 4431 if (!init_event) { 4432 vmcs_write32(GUEST_SYSENTER_CS, 0); 4433 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4434 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4435 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4436 } 4437 4438 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4439 kvm_rip_write(vcpu, 0xfff0); 4440 4441 vmcs_writel(GUEST_GDTR_BASE, 0); 4442 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4443 4444 vmcs_writel(GUEST_IDTR_BASE, 0); 4445 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4446 4447 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4448 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4449 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4450 if (kvm_mpx_supported()) 4451 vmcs_write64(GUEST_BNDCFGS, 0); 4452 4453 setup_msrs(vmx); 4454 4455 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4456 4457 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4458 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4459 if (cpu_need_tpr_shadow(vcpu)) 4460 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4461 __pa(vcpu->arch.apic->regs)); 4462 vmcs_write32(TPR_THRESHOLD, 0); 4463 } 4464 4465 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4466 4467 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4468 vmx->vcpu.arch.cr0 = cr0; 4469 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4470 vmx_set_cr4(vcpu, 0); 4471 vmx_set_efer(vcpu, 0); 4472 4473 update_exception_bitmap(vcpu); 4474 4475 vpid_sync_context(vmx->vpid); 4476 if (init_event) 4477 vmx_clear_hlt(vcpu); 4478 } 4479 4480 static void enable_irq_window(struct kvm_vcpu *vcpu) 4481 { 4482 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4483 } 4484 4485 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4486 { 4487 if (!enable_vnmi || 4488 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4489 enable_irq_window(vcpu); 4490 return; 4491 } 4492 4493 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4494 } 4495 4496 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4497 { 4498 struct vcpu_vmx *vmx = to_vmx(vcpu); 4499 uint32_t intr; 4500 int irq = vcpu->arch.interrupt.nr; 4501 4502 trace_kvm_inj_virq(irq); 4503 4504 ++vcpu->stat.irq_injections; 4505 if (vmx->rmode.vm86_active) { 4506 int inc_eip = 0; 4507 if (vcpu->arch.interrupt.soft) 4508 inc_eip = vcpu->arch.event_exit_inst_len; 4509 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4510 return; 4511 } 4512 intr = irq | INTR_INFO_VALID_MASK; 4513 if (vcpu->arch.interrupt.soft) { 4514 intr |= INTR_TYPE_SOFT_INTR; 4515 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4516 vmx->vcpu.arch.event_exit_inst_len); 4517 } else 4518 intr |= INTR_TYPE_EXT_INTR; 4519 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4520 4521 vmx_clear_hlt(vcpu); 4522 } 4523 4524 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4525 { 4526 struct vcpu_vmx *vmx = to_vmx(vcpu); 4527 4528 if (!enable_vnmi) { 4529 /* 4530 * Tracking the NMI-blocked state in software is built upon 4531 * finding the next open IRQ window. This, in turn, depends on 4532 * well-behaving guests: They have to keep IRQs disabled at 4533 * least as long as the NMI handler runs. Otherwise we may 4534 * cause NMI nesting, maybe breaking the guest. But as this is 4535 * highly unlikely, we can live with the residual risk. 4536 */ 4537 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4538 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4539 } 4540 4541 ++vcpu->stat.nmi_injections; 4542 vmx->loaded_vmcs->nmi_known_unmasked = false; 4543 4544 if (vmx->rmode.vm86_active) { 4545 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4546 return; 4547 } 4548 4549 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4550 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4551 4552 vmx_clear_hlt(vcpu); 4553 } 4554 4555 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4556 { 4557 struct vcpu_vmx *vmx = to_vmx(vcpu); 4558 bool masked; 4559 4560 if (!enable_vnmi) 4561 return vmx->loaded_vmcs->soft_vnmi_blocked; 4562 if (vmx->loaded_vmcs->nmi_known_unmasked) 4563 return false; 4564 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4565 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4566 return masked; 4567 } 4568 4569 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4570 { 4571 struct vcpu_vmx *vmx = to_vmx(vcpu); 4572 4573 if (!enable_vnmi) { 4574 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4575 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4576 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4577 } 4578 } else { 4579 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4580 if (masked) 4581 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4582 GUEST_INTR_STATE_NMI); 4583 else 4584 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4585 GUEST_INTR_STATE_NMI); 4586 } 4587 } 4588 4589 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu) 4590 { 4591 if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu)) 4592 return false; 4593 4594 if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4595 return true; 4596 4597 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4598 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | 4599 GUEST_INTR_STATE_NMI)); 4600 } 4601 4602 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection) 4603 { 4604 if (to_vmx(vcpu)->nested.nested_run_pending) 4605 return -EBUSY; 4606 4607 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */ 4608 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu)) 4609 return -EBUSY; 4610 4611 return !vmx_nmi_blocked(vcpu); 4612 } 4613 4614 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu) 4615 { 4616 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) 4617 return false; 4618 4619 return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) || 4620 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4621 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4622 } 4623 4624 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection) 4625 { 4626 if (to_vmx(vcpu)->nested.nested_run_pending) 4627 return -EBUSY; 4628 4629 /* 4630 * An IRQ must not be injected into L2 if it's supposed to VM-Exit, 4631 * e.g. if the IRQ arrived asynchronously after checking nested events. 4632 */ 4633 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) 4634 return -EBUSY; 4635 4636 return !vmx_interrupt_blocked(vcpu); 4637 } 4638 4639 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4640 { 4641 int ret; 4642 4643 if (enable_unrestricted_guest) 4644 return 0; 4645 4646 mutex_lock(&kvm->slots_lock); 4647 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4648 PAGE_SIZE * 3); 4649 mutex_unlock(&kvm->slots_lock); 4650 4651 if (ret) 4652 return ret; 4653 to_kvm_vmx(kvm)->tss_addr = addr; 4654 return init_rmode_tss(kvm); 4655 } 4656 4657 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4658 { 4659 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4660 return 0; 4661 } 4662 4663 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4664 { 4665 switch (vec) { 4666 case BP_VECTOR: 4667 /* 4668 * Update instruction length as we may reinject the exception 4669 * from user space while in guest debugging mode. 4670 */ 4671 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4672 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4673 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4674 return false; 4675 fallthrough; 4676 case DB_VECTOR: 4677 return !(vcpu->guest_debug & 4678 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)); 4679 case DE_VECTOR: 4680 case OF_VECTOR: 4681 case BR_VECTOR: 4682 case UD_VECTOR: 4683 case DF_VECTOR: 4684 case SS_VECTOR: 4685 case GP_VECTOR: 4686 case MF_VECTOR: 4687 return true; 4688 } 4689 return false; 4690 } 4691 4692 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4693 int vec, u32 err_code) 4694 { 4695 /* 4696 * Instruction with address size override prefix opcode 0x67 4697 * Cause the #SS fault with 0 error code in VM86 mode. 4698 */ 4699 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4700 if (kvm_emulate_instruction(vcpu, 0)) { 4701 if (vcpu->arch.halt_request) { 4702 vcpu->arch.halt_request = 0; 4703 return kvm_vcpu_halt(vcpu); 4704 } 4705 return 1; 4706 } 4707 return 0; 4708 } 4709 4710 /* 4711 * Forward all other exceptions that are valid in real mode. 4712 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4713 * the required debugging infrastructure rework. 4714 */ 4715 kvm_queue_exception(vcpu, vec); 4716 return 1; 4717 } 4718 4719 /* 4720 * Trigger machine check on the host. We assume all the MSRs are already set up 4721 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4722 * We pass a fake environment to the machine check handler because we want 4723 * the guest to be always treated like user space, no matter what context 4724 * it used internally. 4725 */ 4726 static void kvm_machine_check(void) 4727 { 4728 #if defined(CONFIG_X86_MCE) 4729 struct pt_regs regs = { 4730 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4731 .flags = X86_EFLAGS_IF, 4732 }; 4733 4734 do_machine_check(®s); 4735 #endif 4736 } 4737 4738 static int handle_machine_check(struct kvm_vcpu *vcpu) 4739 { 4740 /* handled by vmx_vcpu_run() */ 4741 return 1; 4742 } 4743 4744 /* 4745 * If the host has split lock detection disabled, then #AC is 4746 * unconditionally injected into the guest, which is the pre split lock 4747 * detection behaviour. 4748 * 4749 * If the host has split lock detection enabled then #AC is 4750 * only injected into the guest when: 4751 * - Guest CPL == 3 (user mode) 4752 * - Guest has #AC detection enabled in CR0 4753 * - Guest EFLAGS has AC bit set 4754 */ 4755 static inline bool guest_inject_ac(struct kvm_vcpu *vcpu) 4756 { 4757 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 4758 return true; 4759 4760 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) && 4761 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC); 4762 } 4763 4764 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4765 { 4766 struct vcpu_vmx *vmx = to_vmx(vcpu); 4767 struct kvm_run *kvm_run = vcpu->run; 4768 u32 intr_info, ex_no, error_code; 4769 unsigned long cr2, rip, dr6; 4770 u32 vect_info; 4771 4772 vect_info = vmx->idt_vectoring_info; 4773 intr_info = vmx_get_intr_info(vcpu); 4774 4775 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4776 return 1; /* handled by handle_exception_nmi_irqoff() */ 4777 4778 if (is_invalid_opcode(intr_info)) 4779 return handle_ud(vcpu); 4780 4781 error_code = 0; 4782 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4783 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4784 4785 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4786 WARN_ON_ONCE(!enable_vmware_backdoor); 4787 4788 /* 4789 * VMware backdoor emulation on #GP interception only handles 4790 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4791 * error code on #GP. 4792 */ 4793 if (error_code) { 4794 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4795 return 1; 4796 } 4797 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4798 } 4799 4800 /* 4801 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4802 * MMIO, it is better to report an internal error. 4803 * See the comments in vmx_handle_exit. 4804 */ 4805 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4806 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4807 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4808 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4809 vcpu->run->internal.ndata = 4; 4810 vcpu->run->internal.data[0] = vect_info; 4811 vcpu->run->internal.data[1] = intr_info; 4812 vcpu->run->internal.data[2] = error_code; 4813 vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu; 4814 return 0; 4815 } 4816 4817 if (is_page_fault(intr_info)) { 4818 cr2 = vmx_get_exit_qual(vcpu); 4819 if (enable_ept && !vcpu->arch.apf.host_apf_flags) { 4820 /* 4821 * EPT will cause page fault only if we need to 4822 * detect illegal GPAs. 4823 */ 4824 WARN_ON_ONCE(!allow_smaller_maxphyaddr); 4825 kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code); 4826 return 1; 4827 } else 4828 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4829 } 4830 4831 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4832 4833 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4834 return handle_rmode_exception(vcpu, ex_no, error_code); 4835 4836 switch (ex_no) { 4837 case DB_VECTOR: 4838 dr6 = vmx_get_exit_qual(vcpu); 4839 if (!(vcpu->guest_debug & 4840 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4841 if (is_icebp(intr_info)) 4842 WARN_ON(!skip_emulated_instruction(vcpu)); 4843 4844 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 4845 return 1; 4846 } 4847 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 4848 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4849 fallthrough; 4850 case BP_VECTOR: 4851 /* 4852 * Update instruction length as we may reinject #BP from 4853 * user space while in guest debugging mode. Reading it for 4854 * #DB as well causes no harm, it is not used in that case. 4855 */ 4856 vmx->vcpu.arch.event_exit_inst_len = 4857 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4858 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4859 rip = kvm_rip_read(vcpu); 4860 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4861 kvm_run->debug.arch.exception = ex_no; 4862 break; 4863 case AC_VECTOR: 4864 if (guest_inject_ac(vcpu)) { 4865 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4866 return 1; 4867 } 4868 4869 /* 4870 * Handle split lock. Depending on detection mode this will 4871 * either warn and disable split lock detection for this 4872 * task or force SIGBUS on it. 4873 */ 4874 if (handle_guest_split_lock(kvm_rip_read(vcpu))) 4875 return 1; 4876 fallthrough; 4877 default: 4878 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4879 kvm_run->ex.exception = ex_no; 4880 kvm_run->ex.error_code = error_code; 4881 break; 4882 } 4883 return 0; 4884 } 4885 4886 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4887 { 4888 ++vcpu->stat.irq_exits; 4889 return 1; 4890 } 4891 4892 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4893 { 4894 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4895 vcpu->mmio_needed = 0; 4896 return 0; 4897 } 4898 4899 static int handle_io(struct kvm_vcpu *vcpu) 4900 { 4901 unsigned long exit_qualification; 4902 int size, in, string; 4903 unsigned port; 4904 4905 exit_qualification = vmx_get_exit_qual(vcpu); 4906 string = (exit_qualification & 16) != 0; 4907 4908 ++vcpu->stat.io_exits; 4909 4910 if (string) 4911 return kvm_emulate_instruction(vcpu, 0); 4912 4913 port = exit_qualification >> 16; 4914 size = (exit_qualification & 7) + 1; 4915 in = (exit_qualification & 8) != 0; 4916 4917 return kvm_fast_pio(vcpu, size, port, in); 4918 } 4919 4920 static void 4921 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4922 { 4923 /* 4924 * Patch in the VMCALL instruction: 4925 */ 4926 hypercall[0] = 0x0f; 4927 hypercall[1] = 0x01; 4928 hypercall[2] = 0xc1; 4929 } 4930 4931 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4932 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4933 { 4934 if (is_guest_mode(vcpu)) { 4935 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4936 unsigned long orig_val = val; 4937 4938 /* 4939 * We get here when L2 changed cr0 in a way that did not change 4940 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4941 * but did change L0 shadowed bits. So we first calculate the 4942 * effective cr0 value that L1 would like to write into the 4943 * hardware. It consists of the L2-owned bits from the new 4944 * value combined with the L1-owned bits from L1's guest_cr0. 4945 */ 4946 val = (val & ~vmcs12->cr0_guest_host_mask) | 4947 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4948 4949 if (!nested_guest_cr0_valid(vcpu, val)) 4950 return 1; 4951 4952 if (kvm_set_cr0(vcpu, val)) 4953 return 1; 4954 vmcs_writel(CR0_READ_SHADOW, orig_val); 4955 return 0; 4956 } else { 4957 if (to_vmx(vcpu)->nested.vmxon && 4958 !nested_host_cr0_valid(vcpu, val)) 4959 return 1; 4960 4961 return kvm_set_cr0(vcpu, val); 4962 } 4963 } 4964 4965 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4966 { 4967 if (is_guest_mode(vcpu)) { 4968 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4969 unsigned long orig_val = val; 4970 4971 /* analogously to handle_set_cr0 */ 4972 val = (val & ~vmcs12->cr4_guest_host_mask) | 4973 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4974 if (kvm_set_cr4(vcpu, val)) 4975 return 1; 4976 vmcs_writel(CR4_READ_SHADOW, orig_val); 4977 return 0; 4978 } else 4979 return kvm_set_cr4(vcpu, val); 4980 } 4981 4982 static int handle_desc(struct kvm_vcpu *vcpu) 4983 { 4984 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4985 return kvm_emulate_instruction(vcpu, 0); 4986 } 4987 4988 static int handle_cr(struct kvm_vcpu *vcpu) 4989 { 4990 unsigned long exit_qualification, val; 4991 int cr; 4992 int reg; 4993 int err; 4994 int ret; 4995 4996 exit_qualification = vmx_get_exit_qual(vcpu); 4997 cr = exit_qualification & 15; 4998 reg = (exit_qualification >> 8) & 15; 4999 switch ((exit_qualification >> 4) & 3) { 5000 case 0: /* mov to cr */ 5001 val = kvm_register_readl(vcpu, reg); 5002 trace_kvm_cr_write(cr, val); 5003 switch (cr) { 5004 case 0: 5005 err = handle_set_cr0(vcpu, val); 5006 return kvm_complete_insn_gp(vcpu, err); 5007 case 3: 5008 WARN_ON_ONCE(enable_unrestricted_guest); 5009 err = kvm_set_cr3(vcpu, val); 5010 return kvm_complete_insn_gp(vcpu, err); 5011 case 4: 5012 err = handle_set_cr4(vcpu, val); 5013 return kvm_complete_insn_gp(vcpu, err); 5014 case 8: { 5015 u8 cr8_prev = kvm_get_cr8(vcpu); 5016 u8 cr8 = (u8)val; 5017 err = kvm_set_cr8(vcpu, cr8); 5018 ret = kvm_complete_insn_gp(vcpu, err); 5019 if (lapic_in_kernel(vcpu)) 5020 return ret; 5021 if (cr8_prev <= cr8) 5022 return ret; 5023 /* 5024 * TODO: we might be squashing a 5025 * KVM_GUESTDBG_SINGLESTEP-triggered 5026 * KVM_EXIT_DEBUG here. 5027 */ 5028 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 5029 return 0; 5030 } 5031 } 5032 break; 5033 case 2: /* clts */ 5034 WARN_ONCE(1, "Guest should always own CR0.TS"); 5035 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 5036 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 5037 return kvm_skip_emulated_instruction(vcpu); 5038 case 1: /*mov from cr*/ 5039 switch (cr) { 5040 case 3: 5041 WARN_ON_ONCE(enable_unrestricted_guest); 5042 val = kvm_read_cr3(vcpu); 5043 kvm_register_write(vcpu, reg, val); 5044 trace_kvm_cr_read(cr, val); 5045 return kvm_skip_emulated_instruction(vcpu); 5046 case 8: 5047 val = kvm_get_cr8(vcpu); 5048 kvm_register_write(vcpu, reg, val); 5049 trace_kvm_cr_read(cr, val); 5050 return kvm_skip_emulated_instruction(vcpu); 5051 } 5052 break; 5053 case 3: /* lmsw */ 5054 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 5055 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 5056 kvm_lmsw(vcpu, val); 5057 5058 return kvm_skip_emulated_instruction(vcpu); 5059 default: 5060 break; 5061 } 5062 vcpu->run->exit_reason = 0; 5063 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 5064 (int)(exit_qualification >> 4) & 3, cr); 5065 return 0; 5066 } 5067 5068 static int handle_dr(struct kvm_vcpu *vcpu) 5069 { 5070 unsigned long exit_qualification; 5071 int dr, dr7, reg; 5072 5073 exit_qualification = vmx_get_exit_qual(vcpu); 5074 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 5075 5076 /* First, if DR does not exist, trigger UD */ 5077 if (!kvm_require_dr(vcpu, dr)) 5078 return 1; 5079 5080 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 5081 if (!kvm_require_cpl(vcpu, 0)) 5082 return 1; 5083 dr7 = vmcs_readl(GUEST_DR7); 5084 if (dr7 & DR7_GD) { 5085 /* 5086 * As the vm-exit takes precedence over the debug trap, we 5087 * need to emulate the latter, either for the host or the 5088 * guest debugging itself. 5089 */ 5090 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 5091 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1; 5092 vcpu->run->debug.arch.dr7 = dr7; 5093 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 5094 vcpu->run->debug.arch.exception = DB_VECTOR; 5095 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 5096 return 0; 5097 } else { 5098 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD); 5099 return 1; 5100 } 5101 } 5102 5103 if (vcpu->guest_debug == 0) { 5104 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 5105 5106 /* 5107 * No more DR vmexits; force a reload of the debug registers 5108 * and reenter on this instruction. The next vmexit will 5109 * retrieve the full state of the debug registers. 5110 */ 5111 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 5112 return 1; 5113 } 5114 5115 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 5116 if (exit_qualification & TYPE_MOV_FROM_DR) { 5117 unsigned long val; 5118 5119 if (kvm_get_dr(vcpu, dr, &val)) 5120 return 1; 5121 kvm_register_write(vcpu, reg, val); 5122 } else 5123 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 5124 return 1; 5125 5126 return kvm_skip_emulated_instruction(vcpu); 5127 } 5128 5129 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 5130 { 5131 get_debugreg(vcpu->arch.db[0], 0); 5132 get_debugreg(vcpu->arch.db[1], 1); 5133 get_debugreg(vcpu->arch.db[2], 2); 5134 get_debugreg(vcpu->arch.db[3], 3); 5135 get_debugreg(vcpu->arch.dr6, 6); 5136 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 5137 5138 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 5139 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 5140 } 5141 5142 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 5143 { 5144 vmcs_writel(GUEST_DR7, val); 5145 } 5146 5147 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 5148 { 5149 kvm_apic_update_ppr(vcpu); 5150 return 1; 5151 } 5152 5153 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 5154 { 5155 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 5156 5157 kvm_make_request(KVM_REQ_EVENT, vcpu); 5158 5159 ++vcpu->stat.irq_window_exits; 5160 return 1; 5161 } 5162 5163 static int handle_vmcall(struct kvm_vcpu *vcpu) 5164 { 5165 return kvm_emulate_hypercall(vcpu); 5166 } 5167 5168 static int handle_invd(struct kvm_vcpu *vcpu) 5169 { 5170 /* Treat an INVD instruction as a NOP and just skip it. */ 5171 return kvm_skip_emulated_instruction(vcpu); 5172 } 5173 5174 static int handle_invlpg(struct kvm_vcpu *vcpu) 5175 { 5176 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5177 5178 kvm_mmu_invlpg(vcpu, exit_qualification); 5179 return kvm_skip_emulated_instruction(vcpu); 5180 } 5181 5182 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5183 { 5184 int err; 5185 5186 err = kvm_rdpmc(vcpu); 5187 return kvm_complete_insn_gp(vcpu, err); 5188 } 5189 5190 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5191 { 5192 return kvm_emulate_wbinvd(vcpu); 5193 } 5194 5195 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5196 { 5197 u64 new_bv = kvm_read_edx_eax(vcpu); 5198 u32 index = kvm_rcx_read(vcpu); 5199 5200 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5201 return kvm_skip_emulated_instruction(vcpu); 5202 return 1; 5203 } 5204 5205 static int handle_apic_access(struct kvm_vcpu *vcpu) 5206 { 5207 if (likely(fasteoi)) { 5208 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5209 int access_type, offset; 5210 5211 access_type = exit_qualification & APIC_ACCESS_TYPE; 5212 offset = exit_qualification & APIC_ACCESS_OFFSET; 5213 /* 5214 * Sane guest uses MOV to write EOI, with written value 5215 * not cared. So make a short-circuit here by avoiding 5216 * heavy instruction emulation. 5217 */ 5218 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5219 (offset == APIC_EOI)) { 5220 kvm_lapic_set_eoi(vcpu); 5221 return kvm_skip_emulated_instruction(vcpu); 5222 } 5223 } 5224 return kvm_emulate_instruction(vcpu, 0); 5225 } 5226 5227 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5228 { 5229 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5230 int vector = exit_qualification & 0xff; 5231 5232 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5233 kvm_apic_set_eoi_accelerated(vcpu, vector); 5234 return 1; 5235 } 5236 5237 static int handle_apic_write(struct kvm_vcpu *vcpu) 5238 { 5239 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5240 u32 offset = exit_qualification & 0xfff; 5241 5242 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5243 kvm_apic_write_nodecode(vcpu, offset); 5244 return 1; 5245 } 5246 5247 static int handle_task_switch(struct kvm_vcpu *vcpu) 5248 { 5249 struct vcpu_vmx *vmx = to_vmx(vcpu); 5250 unsigned long exit_qualification; 5251 bool has_error_code = false; 5252 u32 error_code = 0; 5253 u16 tss_selector; 5254 int reason, type, idt_v, idt_index; 5255 5256 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5257 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5258 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5259 5260 exit_qualification = vmx_get_exit_qual(vcpu); 5261 5262 reason = (u32)exit_qualification >> 30; 5263 if (reason == TASK_SWITCH_GATE && idt_v) { 5264 switch (type) { 5265 case INTR_TYPE_NMI_INTR: 5266 vcpu->arch.nmi_injected = false; 5267 vmx_set_nmi_mask(vcpu, true); 5268 break; 5269 case INTR_TYPE_EXT_INTR: 5270 case INTR_TYPE_SOFT_INTR: 5271 kvm_clear_interrupt_queue(vcpu); 5272 break; 5273 case INTR_TYPE_HARD_EXCEPTION: 5274 if (vmx->idt_vectoring_info & 5275 VECTORING_INFO_DELIVER_CODE_MASK) { 5276 has_error_code = true; 5277 error_code = 5278 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5279 } 5280 fallthrough; 5281 case INTR_TYPE_SOFT_EXCEPTION: 5282 kvm_clear_exception_queue(vcpu); 5283 break; 5284 default: 5285 break; 5286 } 5287 } 5288 tss_selector = exit_qualification; 5289 5290 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5291 type != INTR_TYPE_EXT_INTR && 5292 type != INTR_TYPE_NMI_INTR)) 5293 WARN_ON(!skip_emulated_instruction(vcpu)); 5294 5295 /* 5296 * TODO: What about debug traps on tss switch? 5297 * Are we supposed to inject them and update dr6? 5298 */ 5299 return kvm_task_switch(vcpu, tss_selector, 5300 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5301 reason, has_error_code, error_code); 5302 } 5303 5304 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5305 { 5306 unsigned long exit_qualification; 5307 gpa_t gpa; 5308 u64 error_code; 5309 5310 exit_qualification = vmx_get_exit_qual(vcpu); 5311 5312 /* 5313 * EPT violation happened while executing iret from NMI, 5314 * "blocked by NMI" bit has to be set before next VM entry. 5315 * There are errata that may cause this bit to not be set: 5316 * AAK134, BY25. 5317 */ 5318 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5319 enable_vnmi && 5320 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5321 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5322 5323 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5324 trace_kvm_page_fault(gpa, exit_qualification); 5325 5326 /* Is it a read fault? */ 5327 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5328 ? PFERR_USER_MASK : 0; 5329 /* Is it a write fault? */ 5330 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5331 ? PFERR_WRITE_MASK : 0; 5332 /* Is it a fetch fault? */ 5333 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5334 ? PFERR_FETCH_MASK : 0; 5335 /* ept page table entry is present? */ 5336 error_code |= (exit_qualification & 5337 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5338 EPT_VIOLATION_EXECUTABLE)) 5339 ? PFERR_PRESENT_MASK : 0; 5340 5341 error_code |= (exit_qualification & 0x100) != 0 ? 5342 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5343 5344 vcpu->arch.exit_qualification = exit_qualification; 5345 5346 /* 5347 * Check that the GPA doesn't exceed physical memory limits, as that is 5348 * a guest page fault. We have to emulate the instruction here, because 5349 * if the illegal address is that of a paging structure, then 5350 * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we 5351 * would also use advanced VM-exit information for EPT violations to 5352 * reconstruct the page fault error code. 5353 */ 5354 if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa))) 5355 return kvm_emulate_instruction(vcpu, 0); 5356 5357 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5358 } 5359 5360 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5361 { 5362 gpa_t gpa; 5363 5364 /* 5365 * A nested guest cannot optimize MMIO vmexits, because we have an 5366 * nGPA here instead of the required GPA. 5367 */ 5368 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5369 if (!is_guest_mode(vcpu) && 5370 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5371 trace_kvm_fast_mmio(gpa); 5372 return kvm_skip_emulated_instruction(vcpu); 5373 } 5374 5375 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5376 } 5377 5378 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5379 { 5380 WARN_ON_ONCE(!enable_vnmi); 5381 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5382 ++vcpu->stat.nmi_window_exits; 5383 kvm_make_request(KVM_REQ_EVENT, vcpu); 5384 5385 return 1; 5386 } 5387 5388 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5389 { 5390 struct vcpu_vmx *vmx = to_vmx(vcpu); 5391 bool intr_window_requested; 5392 unsigned count = 130; 5393 5394 intr_window_requested = exec_controls_get(vmx) & 5395 CPU_BASED_INTR_WINDOW_EXITING; 5396 5397 while (vmx->emulation_required && count-- != 0) { 5398 if (intr_window_requested && !vmx_interrupt_blocked(vcpu)) 5399 return handle_interrupt_window(&vmx->vcpu); 5400 5401 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5402 return 1; 5403 5404 if (!kvm_emulate_instruction(vcpu, 0)) 5405 return 0; 5406 5407 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5408 vcpu->arch.exception.pending) { 5409 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5410 vcpu->run->internal.suberror = 5411 KVM_INTERNAL_ERROR_EMULATION; 5412 vcpu->run->internal.ndata = 0; 5413 return 0; 5414 } 5415 5416 if (vcpu->arch.halt_request) { 5417 vcpu->arch.halt_request = 0; 5418 return kvm_vcpu_halt(vcpu); 5419 } 5420 5421 /* 5422 * Note, return 1 and not 0, vcpu_run() will invoke 5423 * xfer_to_guest_mode() which will create a proper return 5424 * code. 5425 */ 5426 if (__xfer_to_guest_mode_work_pending()) 5427 return 1; 5428 } 5429 5430 return 1; 5431 } 5432 5433 static void grow_ple_window(struct kvm_vcpu *vcpu) 5434 { 5435 struct vcpu_vmx *vmx = to_vmx(vcpu); 5436 unsigned int old = vmx->ple_window; 5437 5438 vmx->ple_window = __grow_ple_window(old, ple_window, 5439 ple_window_grow, 5440 ple_window_max); 5441 5442 if (vmx->ple_window != old) { 5443 vmx->ple_window_dirty = true; 5444 trace_kvm_ple_window_update(vcpu->vcpu_id, 5445 vmx->ple_window, old); 5446 } 5447 } 5448 5449 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5450 { 5451 struct vcpu_vmx *vmx = to_vmx(vcpu); 5452 unsigned int old = vmx->ple_window; 5453 5454 vmx->ple_window = __shrink_ple_window(old, ple_window, 5455 ple_window_shrink, 5456 ple_window); 5457 5458 if (vmx->ple_window != old) { 5459 vmx->ple_window_dirty = true; 5460 trace_kvm_ple_window_update(vcpu->vcpu_id, 5461 vmx->ple_window, old); 5462 } 5463 } 5464 5465 static void vmx_enable_tdp(void) 5466 { 5467 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5468 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5469 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5470 0ull, VMX_EPT_EXECUTABLE_MASK, 5471 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5472 VMX_EPT_RWX_MASK, 0ull); 5473 5474 ept_set_mmio_spte_mask(); 5475 } 5476 5477 /* 5478 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5479 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5480 */ 5481 static int handle_pause(struct kvm_vcpu *vcpu) 5482 { 5483 if (!kvm_pause_in_guest(vcpu->kvm)) 5484 grow_ple_window(vcpu); 5485 5486 /* 5487 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5488 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5489 * never set PAUSE_EXITING and just set PLE if supported, 5490 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5491 */ 5492 kvm_vcpu_on_spin(vcpu, true); 5493 return kvm_skip_emulated_instruction(vcpu); 5494 } 5495 5496 static int handle_nop(struct kvm_vcpu *vcpu) 5497 { 5498 return kvm_skip_emulated_instruction(vcpu); 5499 } 5500 5501 static int handle_mwait(struct kvm_vcpu *vcpu) 5502 { 5503 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5504 return handle_nop(vcpu); 5505 } 5506 5507 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5508 { 5509 kvm_queue_exception(vcpu, UD_VECTOR); 5510 return 1; 5511 } 5512 5513 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5514 { 5515 return 1; 5516 } 5517 5518 static int handle_monitor(struct kvm_vcpu *vcpu) 5519 { 5520 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5521 return handle_nop(vcpu); 5522 } 5523 5524 static int handle_invpcid(struct kvm_vcpu *vcpu) 5525 { 5526 u32 vmx_instruction_info; 5527 unsigned long type; 5528 gva_t gva; 5529 struct { 5530 u64 pcid; 5531 u64 gla; 5532 } operand; 5533 5534 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5535 kvm_queue_exception(vcpu, UD_VECTOR); 5536 return 1; 5537 } 5538 5539 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5540 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5541 5542 if (type > 3) { 5543 kvm_inject_gp(vcpu, 0); 5544 return 1; 5545 } 5546 5547 /* According to the Intel instruction reference, the memory operand 5548 * is read even if it isn't needed (e.g., for type==all) 5549 */ 5550 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), 5551 vmx_instruction_info, false, 5552 sizeof(operand), &gva)) 5553 return 1; 5554 5555 return kvm_handle_invpcid(vcpu, type, gva); 5556 } 5557 5558 static int handle_pml_full(struct kvm_vcpu *vcpu) 5559 { 5560 unsigned long exit_qualification; 5561 5562 trace_kvm_pml_full(vcpu->vcpu_id); 5563 5564 exit_qualification = vmx_get_exit_qual(vcpu); 5565 5566 /* 5567 * PML buffer FULL happened while executing iret from NMI, 5568 * "blocked by NMI" bit has to be set before next VM entry. 5569 */ 5570 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5571 enable_vnmi && 5572 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5573 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5574 GUEST_INTR_STATE_NMI); 5575 5576 /* 5577 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5578 * here.., and there's no userspace involvement needed for PML. 5579 */ 5580 return 1; 5581 } 5582 5583 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu) 5584 { 5585 struct vcpu_vmx *vmx = to_vmx(vcpu); 5586 5587 if (!vmx->req_immediate_exit && 5588 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) { 5589 kvm_lapic_expired_hv_timer(vcpu); 5590 return EXIT_FASTPATH_REENTER_GUEST; 5591 } 5592 5593 return EXIT_FASTPATH_NONE; 5594 } 5595 5596 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5597 { 5598 handle_fastpath_preemption_timer(vcpu); 5599 return 1; 5600 } 5601 5602 /* 5603 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5604 * are overwritten by nested_vmx_setup() when nested=1. 5605 */ 5606 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5607 { 5608 kvm_queue_exception(vcpu, UD_VECTOR); 5609 return 1; 5610 } 5611 5612 static int handle_encls(struct kvm_vcpu *vcpu) 5613 { 5614 /* 5615 * SGX virtualization is not yet supported. There is no software 5616 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5617 * to prevent the guest from executing ENCLS. 5618 */ 5619 kvm_queue_exception(vcpu, UD_VECTOR); 5620 return 1; 5621 } 5622 5623 /* 5624 * The exit handlers return 1 if the exit was handled fully and guest execution 5625 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5626 * to be done to userspace and return 0. 5627 */ 5628 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5629 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5630 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5631 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5632 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5633 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5634 [EXIT_REASON_CR_ACCESS] = handle_cr, 5635 [EXIT_REASON_DR_ACCESS] = handle_dr, 5636 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5637 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5638 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5639 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5640 [EXIT_REASON_HLT] = kvm_emulate_halt, 5641 [EXIT_REASON_INVD] = handle_invd, 5642 [EXIT_REASON_INVLPG] = handle_invlpg, 5643 [EXIT_REASON_RDPMC] = handle_rdpmc, 5644 [EXIT_REASON_VMCALL] = handle_vmcall, 5645 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5646 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5647 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5648 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5649 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5650 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5651 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5652 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5653 [EXIT_REASON_VMON] = handle_vmx_instruction, 5654 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5655 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5656 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5657 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5658 [EXIT_REASON_WBINVD] = handle_wbinvd, 5659 [EXIT_REASON_XSETBV] = handle_xsetbv, 5660 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5661 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5662 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5663 [EXIT_REASON_LDTR_TR] = handle_desc, 5664 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5665 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5666 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5667 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5668 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5669 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5670 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5671 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5672 [EXIT_REASON_RDRAND] = handle_invalid_op, 5673 [EXIT_REASON_RDSEED] = handle_invalid_op, 5674 [EXIT_REASON_PML_FULL] = handle_pml_full, 5675 [EXIT_REASON_INVPCID] = handle_invpcid, 5676 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5677 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5678 [EXIT_REASON_ENCLS] = handle_encls, 5679 }; 5680 5681 static const int kvm_vmx_max_exit_handlers = 5682 ARRAY_SIZE(kvm_vmx_exit_handlers); 5683 5684 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2, 5685 u32 *intr_info, u32 *error_code) 5686 { 5687 struct vcpu_vmx *vmx = to_vmx(vcpu); 5688 5689 *info1 = vmx_get_exit_qual(vcpu); 5690 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { 5691 *info2 = vmx->idt_vectoring_info; 5692 *intr_info = vmx_get_intr_info(vcpu); 5693 if (is_exception_with_error_code(*intr_info)) 5694 *error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 5695 else 5696 *error_code = 0; 5697 } else { 5698 *info2 = 0; 5699 *intr_info = 0; 5700 *error_code = 0; 5701 } 5702 } 5703 5704 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5705 { 5706 if (vmx->pml_pg) { 5707 __free_page(vmx->pml_pg); 5708 vmx->pml_pg = NULL; 5709 } 5710 } 5711 5712 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5713 { 5714 struct vcpu_vmx *vmx = to_vmx(vcpu); 5715 u64 *pml_buf; 5716 u16 pml_idx; 5717 5718 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5719 5720 /* Do nothing if PML buffer is empty */ 5721 if (pml_idx == (PML_ENTITY_NUM - 1)) 5722 return; 5723 5724 /* PML index always points to next available PML buffer entity */ 5725 if (pml_idx >= PML_ENTITY_NUM) 5726 pml_idx = 0; 5727 else 5728 pml_idx++; 5729 5730 pml_buf = page_address(vmx->pml_pg); 5731 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5732 u64 gpa; 5733 5734 gpa = pml_buf[pml_idx]; 5735 WARN_ON(gpa & (PAGE_SIZE - 1)); 5736 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5737 } 5738 5739 /* reset PML index */ 5740 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5741 } 5742 5743 /* 5744 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5745 * Called before reporting dirty_bitmap to userspace. 5746 */ 5747 static void kvm_flush_pml_buffers(struct kvm *kvm) 5748 { 5749 int i; 5750 struct kvm_vcpu *vcpu; 5751 /* 5752 * We only need to kick vcpu out of guest mode here, as PML buffer 5753 * is flushed at beginning of all VMEXITs, and it's obvious that only 5754 * vcpus running in guest are possible to have unflushed GPAs in PML 5755 * buffer. 5756 */ 5757 kvm_for_each_vcpu(i, vcpu, kvm) 5758 kvm_vcpu_kick(vcpu); 5759 } 5760 5761 static void vmx_dump_sel(char *name, uint32_t sel) 5762 { 5763 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5764 name, vmcs_read16(sel), 5765 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5766 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5767 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5768 } 5769 5770 static void vmx_dump_dtsel(char *name, uint32_t limit) 5771 { 5772 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5773 name, vmcs_read32(limit), 5774 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5775 } 5776 5777 void dump_vmcs(void) 5778 { 5779 u32 vmentry_ctl, vmexit_ctl; 5780 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5781 unsigned long cr4; 5782 u64 efer; 5783 5784 if (!dump_invalid_vmcs) { 5785 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5786 return; 5787 } 5788 5789 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5790 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5791 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5792 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5793 cr4 = vmcs_readl(GUEST_CR4); 5794 efer = vmcs_read64(GUEST_IA32_EFER); 5795 secondary_exec_control = 0; 5796 if (cpu_has_secondary_exec_ctrls()) 5797 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5798 5799 pr_err("*** Guest State ***\n"); 5800 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5801 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5802 vmcs_readl(CR0_GUEST_HOST_MASK)); 5803 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5804 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5805 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5806 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5807 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5808 { 5809 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5810 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5811 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5812 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5813 } 5814 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5815 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5816 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5817 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5818 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5819 vmcs_readl(GUEST_SYSENTER_ESP), 5820 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5821 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5822 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5823 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5824 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5825 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5826 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5827 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5828 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5829 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5830 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5831 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5832 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5833 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5834 efer, vmcs_read64(GUEST_IA32_PAT)); 5835 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5836 vmcs_read64(GUEST_IA32_DEBUGCTL), 5837 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5838 if (cpu_has_load_perf_global_ctrl() && 5839 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5840 pr_err("PerfGlobCtl = 0x%016llx\n", 5841 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5842 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5843 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5844 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5845 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5846 vmcs_read32(GUEST_ACTIVITY_STATE)); 5847 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5848 pr_err("InterruptStatus = %04x\n", 5849 vmcs_read16(GUEST_INTR_STATUS)); 5850 5851 pr_err("*** Host State ***\n"); 5852 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5853 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5854 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5855 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5856 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5857 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5858 vmcs_read16(HOST_TR_SELECTOR)); 5859 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5860 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5861 vmcs_readl(HOST_TR_BASE)); 5862 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5863 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5864 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5865 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5866 vmcs_readl(HOST_CR4)); 5867 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5868 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5869 vmcs_read32(HOST_IA32_SYSENTER_CS), 5870 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5871 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5872 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5873 vmcs_read64(HOST_IA32_EFER), 5874 vmcs_read64(HOST_IA32_PAT)); 5875 if (cpu_has_load_perf_global_ctrl() && 5876 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5877 pr_err("PerfGlobCtl = 0x%016llx\n", 5878 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5879 5880 pr_err("*** Control State ***\n"); 5881 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5882 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5883 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5884 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5885 vmcs_read32(EXCEPTION_BITMAP), 5886 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5887 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5888 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5889 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5890 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5891 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5892 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5893 vmcs_read32(VM_EXIT_INTR_INFO), 5894 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5895 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5896 pr_err(" reason=%08x qualification=%016lx\n", 5897 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5898 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5899 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5900 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5901 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5902 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5903 pr_err("TSC Multiplier = 0x%016llx\n", 5904 vmcs_read64(TSC_MULTIPLIER)); 5905 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5906 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5907 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5908 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5909 } 5910 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5911 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5912 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5913 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5914 } 5915 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5916 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5917 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5918 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5919 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5920 pr_err("PLE Gap=%08x Window=%08x\n", 5921 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5922 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5923 pr_err("Virtual processor ID = 0x%04x\n", 5924 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5925 } 5926 5927 /* 5928 * The guest has exited. See if we can fix it or if we need userspace 5929 * assistance. 5930 */ 5931 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath) 5932 { 5933 struct vcpu_vmx *vmx = to_vmx(vcpu); 5934 u32 exit_reason = vmx->exit_reason; 5935 u32 vectoring_info = vmx->idt_vectoring_info; 5936 5937 /* 5938 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5939 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5940 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5941 * mode as if vcpus is in root mode, the PML buffer must has been 5942 * flushed already. 5943 */ 5944 if (enable_pml) 5945 vmx_flush_pml_buffer(vcpu); 5946 5947 /* 5948 * We should never reach this point with a pending nested VM-Enter, and 5949 * more specifically emulation of L2 due to invalid guest state (see 5950 * below) should never happen as that means we incorrectly allowed a 5951 * nested VM-Enter with an invalid vmcs12. 5952 */ 5953 WARN_ON_ONCE(vmx->nested.nested_run_pending); 5954 5955 /* If guest state is invalid, start emulating */ 5956 if (vmx->emulation_required) 5957 return handle_invalid_guest_state(vcpu); 5958 5959 if (is_guest_mode(vcpu)) { 5960 /* 5961 * The host physical addresses of some pages of guest memory 5962 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC 5963 * Page). The CPU may write to these pages via their host 5964 * physical address while L2 is running, bypassing any 5965 * address-translation-based dirty tracking (e.g. EPT write 5966 * protection). 5967 * 5968 * Mark them dirty on every exit from L2 to prevent them from 5969 * getting out of sync with dirty tracking. 5970 */ 5971 nested_mark_vmcs12_pages_dirty(vcpu); 5972 5973 if (nested_vmx_reflect_vmexit(vcpu)) 5974 return 1; 5975 } 5976 5977 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5978 dump_vmcs(); 5979 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5980 vcpu->run->fail_entry.hardware_entry_failure_reason 5981 = exit_reason; 5982 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu; 5983 return 0; 5984 } 5985 5986 if (unlikely(vmx->fail)) { 5987 dump_vmcs(); 5988 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5989 vcpu->run->fail_entry.hardware_entry_failure_reason 5990 = vmcs_read32(VM_INSTRUCTION_ERROR); 5991 vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu; 5992 return 0; 5993 } 5994 5995 /* 5996 * Note: 5997 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5998 * delivery event since it indicates guest is accessing MMIO. 5999 * The vm-exit can be triggered again after return to guest that 6000 * will cause infinite loop. 6001 */ 6002 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 6003 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 6004 exit_reason != EXIT_REASON_EPT_VIOLATION && 6005 exit_reason != EXIT_REASON_PML_FULL && 6006 exit_reason != EXIT_REASON_APIC_ACCESS && 6007 exit_reason != EXIT_REASON_TASK_SWITCH)) { 6008 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6009 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 6010 vcpu->run->internal.ndata = 3; 6011 vcpu->run->internal.data[0] = vectoring_info; 6012 vcpu->run->internal.data[1] = exit_reason; 6013 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 6014 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 6015 vcpu->run->internal.ndata++; 6016 vcpu->run->internal.data[3] = 6017 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 6018 } 6019 vcpu->run->internal.data[vcpu->run->internal.ndata++] = 6020 vcpu->arch.last_vmentry_cpu; 6021 return 0; 6022 } 6023 6024 if (unlikely(!enable_vnmi && 6025 vmx->loaded_vmcs->soft_vnmi_blocked)) { 6026 if (!vmx_interrupt_blocked(vcpu)) { 6027 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 6028 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 6029 vcpu->arch.nmi_pending) { 6030 /* 6031 * This CPU don't support us in finding the end of an 6032 * NMI-blocked window if the guest runs with IRQs 6033 * disabled. So we pull the trigger after 1 s of 6034 * futile waiting, but inform the user about this. 6035 */ 6036 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 6037 "state on VCPU %d after 1 s timeout\n", 6038 __func__, vcpu->vcpu_id); 6039 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 6040 } 6041 } 6042 6043 if (exit_fastpath != EXIT_FASTPATH_NONE) 6044 return 1; 6045 6046 if (exit_reason >= kvm_vmx_max_exit_handlers) 6047 goto unexpected_vmexit; 6048 #ifdef CONFIG_RETPOLINE 6049 if (exit_reason == EXIT_REASON_MSR_WRITE) 6050 return kvm_emulate_wrmsr(vcpu); 6051 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 6052 return handle_preemption_timer(vcpu); 6053 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 6054 return handle_interrupt_window(vcpu); 6055 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6056 return handle_external_interrupt(vcpu); 6057 else if (exit_reason == EXIT_REASON_HLT) 6058 return kvm_emulate_halt(vcpu); 6059 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 6060 return handle_ept_misconfig(vcpu); 6061 #endif 6062 6063 exit_reason = array_index_nospec(exit_reason, 6064 kvm_vmx_max_exit_handlers); 6065 if (!kvm_vmx_exit_handlers[exit_reason]) 6066 goto unexpected_vmexit; 6067 6068 return kvm_vmx_exit_handlers[exit_reason](vcpu); 6069 6070 unexpected_vmexit: 6071 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 6072 dump_vmcs(); 6073 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6074 vcpu->run->internal.suberror = 6075 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 6076 vcpu->run->internal.ndata = 2; 6077 vcpu->run->internal.data[0] = exit_reason; 6078 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu; 6079 return 0; 6080 } 6081 6082 /* 6083 * Software based L1D cache flush which is used when microcode providing 6084 * the cache control MSR is not loaded. 6085 * 6086 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 6087 * flush it is required to read in 64 KiB because the replacement algorithm 6088 * is not exactly LRU. This could be sized at runtime via topology 6089 * information but as all relevant affected CPUs have 32KiB L1D cache size 6090 * there is no point in doing so. 6091 */ 6092 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu) 6093 { 6094 int size = PAGE_SIZE << L1D_CACHE_ORDER; 6095 6096 /* 6097 * This code is only executed when the the flush mode is 'cond' or 6098 * 'always' 6099 */ 6100 if (static_branch_likely(&vmx_l1d_flush_cond)) { 6101 bool flush_l1d; 6102 6103 /* 6104 * Clear the per-vcpu flush bit, it gets set again 6105 * either from vcpu_run() or from one of the unsafe 6106 * VMEXIT handlers. 6107 */ 6108 flush_l1d = vcpu->arch.l1tf_flush_l1d; 6109 vcpu->arch.l1tf_flush_l1d = false; 6110 6111 /* 6112 * Clear the per-cpu flush bit, it gets set again from 6113 * the interrupt handlers. 6114 */ 6115 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 6116 kvm_clear_cpu_l1tf_flush_l1d(); 6117 6118 if (!flush_l1d) 6119 return; 6120 } 6121 6122 vcpu->stat.l1d_flush++; 6123 6124 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 6125 native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6126 return; 6127 } 6128 6129 asm volatile( 6130 /* First ensure the pages are in the TLB */ 6131 "xorl %%eax, %%eax\n" 6132 ".Lpopulate_tlb:\n\t" 6133 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6134 "addl $4096, %%eax\n\t" 6135 "cmpl %%eax, %[size]\n\t" 6136 "jne .Lpopulate_tlb\n\t" 6137 "xorl %%eax, %%eax\n\t" 6138 "cpuid\n\t" 6139 /* Now fill the cache */ 6140 "xorl %%eax, %%eax\n" 6141 ".Lfill_cache:\n" 6142 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6143 "addl $64, %%eax\n\t" 6144 "cmpl %%eax, %[size]\n\t" 6145 "jne .Lfill_cache\n\t" 6146 "lfence\n" 6147 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6148 [size] "r" (size) 6149 : "eax", "ebx", "ecx", "edx"); 6150 } 6151 6152 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6153 { 6154 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6155 int tpr_threshold; 6156 6157 if (is_guest_mode(vcpu) && 6158 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6159 return; 6160 6161 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6162 if (is_guest_mode(vcpu)) 6163 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6164 else 6165 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6166 } 6167 6168 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6169 { 6170 struct vcpu_vmx *vmx = to_vmx(vcpu); 6171 u32 sec_exec_control; 6172 6173 if (!lapic_in_kernel(vcpu)) 6174 return; 6175 6176 if (!flexpriority_enabled && 6177 !cpu_has_vmx_virtualize_x2apic_mode()) 6178 return; 6179 6180 /* Postpone execution until vmcs01 is the current VMCS. */ 6181 if (is_guest_mode(vcpu)) { 6182 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6183 return; 6184 } 6185 6186 sec_exec_control = secondary_exec_controls_get(vmx); 6187 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6188 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6189 6190 switch (kvm_get_apic_mode(vcpu)) { 6191 case LAPIC_MODE_INVALID: 6192 WARN_ONCE(true, "Invalid local APIC state"); 6193 case LAPIC_MODE_DISABLED: 6194 break; 6195 case LAPIC_MODE_XAPIC: 6196 if (flexpriority_enabled) { 6197 sec_exec_control |= 6198 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6199 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 6200 6201 /* 6202 * Flush the TLB, reloading the APIC access page will 6203 * only do so if its physical address has changed, but 6204 * the guest may have inserted a non-APIC mapping into 6205 * the TLB while the APIC access page was disabled. 6206 */ 6207 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 6208 } 6209 break; 6210 case LAPIC_MODE_X2APIC: 6211 if (cpu_has_vmx_virtualize_x2apic_mode()) 6212 sec_exec_control |= 6213 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6214 break; 6215 } 6216 secondary_exec_controls_set(vmx, sec_exec_control); 6217 6218 vmx_update_msr_bitmap(vcpu); 6219 } 6220 6221 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu) 6222 { 6223 struct page *page; 6224 6225 /* Defer reload until vmcs01 is the current VMCS. */ 6226 if (is_guest_mode(vcpu)) { 6227 to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true; 6228 return; 6229 } 6230 6231 if (!(secondary_exec_controls_get(to_vmx(vcpu)) & 6232 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 6233 return; 6234 6235 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6236 if (is_error_page(page)) 6237 return; 6238 6239 vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page)); 6240 vmx_flush_tlb_current(vcpu); 6241 6242 /* 6243 * Do not pin apic access page in memory, the MMU notifier 6244 * will call us again if it is migrated or swapped out. 6245 */ 6246 put_page(page); 6247 } 6248 6249 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6250 { 6251 u16 status; 6252 u8 old; 6253 6254 if (max_isr == -1) 6255 max_isr = 0; 6256 6257 status = vmcs_read16(GUEST_INTR_STATUS); 6258 old = status >> 8; 6259 if (max_isr != old) { 6260 status &= 0xff; 6261 status |= max_isr << 8; 6262 vmcs_write16(GUEST_INTR_STATUS, status); 6263 } 6264 } 6265 6266 static void vmx_set_rvi(int vector) 6267 { 6268 u16 status; 6269 u8 old; 6270 6271 if (vector == -1) 6272 vector = 0; 6273 6274 status = vmcs_read16(GUEST_INTR_STATUS); 6275 old = (u8)status & 0xff; 6276 if ((u8)vector != old) { 6277 status &= ~0xff; 6278 status |= (u8)vector; 6279 vmcs_write16(GUEST_INTR_STATUS, status); 6280 } 6281 } 6282 6283 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6284 { 6285 /* 6286 * When running L2, updating RVI is only relevant when 6287 * vmcs12 virtual-interrupt-delivery enabled. 6288 * However, it can be enabled only when L1 also 6289 * intercepts external-interrupts and in that case 6290 * we should not update vmcs02 RVI but instead intercept 6291 * interrupt. Therefore, do nothing when running L2. 6292 */ 6293 if (!is_guest_mode(vcpu)) 6294 vmx_set_rvi(max_irr); 6295 } 6296 6297 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6298 { 6299 struct vcpu_vmx *vmx = to_vmx(vcpu); 6300 int max_irr; 6301 bool max_irr_updated; 6302 6303 WARN_ON(!vcpu->arch.apicv_active); 6304 if (pi_test_on(&vmx->pi_desc)) { 6305 pi_clear_on(&vmx->pi_desc); 6306 /* 6307 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6308 * But on x86 this is just a compiler barrier anyway. 6309 */ 6310 smp_mb__after_atomic(); 6311 max_irr_updated = 6312 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6313 6314 /* 6315 * If we are running L2 and L1 has a new pending interrupt 6316 * which can be injected, we should re-evaluate 6317 * what should be done with this new L1 interrupt. 6318 * If L1 intercepts external-interrupts, we should 6319 * exit from L2 to L1. Otherwise, interrupt should be 6320 * delivered directly to L2. 6321 */ 6322 if (is_guest_mode(vcpu) && max_irr_updated) { 6323 if (nested_exit_on_intr(vcpu)) 6324 kvm_vcpu_exiting_guest_mode(vcpu); 6325 else 6326 kvm_make_request(KVM_REQ_EVENT, vcpu); 6327 } 6328 } else { 6329 max_irr = kvm_lapic_find_highest_irr(vcpu); 6330 } 6331 vmx_hwapic_irr_update(vcpu, max_irr); 6332 return max_irr; 6333 } 6334 6335 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6336 { 6337 if (!kvm_vcpu_apicv_active(vcpu)) 6338 return; 6339 6340 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6341 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6342 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6343 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6344 } 6345 6346 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6347 { 6348 struct vcpu_vmx *vmx = to_vmx(vcpu); 6349 6350 pi_clear_on(&vmx->pi_desc); 6351 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6352 } 6353 6354 void vmx_do_interrupt_nmi_irqoff(unsigned long entry); 6355 6356 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu, u32 intr_info) 6357 { 6358 unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK; 6359 gate_desc *desc = (gate_desc *)host_idt_base + vector; 6360 6361 kvm_before_interrupt(vcpu); 6362 vmx_do_interrupt_nmi_irqoff(gate_offset(desc)); 6363 kvm_after_interrupt(vcpu); 6364 } 6365 6366 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6367 { 6368 u32 intr_info = vmx_get_intr_info(&vmx->vcpu); 6369 6370 /* if exit due to PF check for async PF */ 6371 if (is_page_fault(intr_info)) 6372 vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags(); 6373 /* Handle machine checks before interrupts are enabled */ 6374 else if (is_machine_check(intr_info)) 6375 kvm_machine_check(); 6376 /* We need to handle NMIs before interrupts are enabled */ 6377 else if (is_nmi(intr_info)) 6378 handle_interrupt_nmi_irqoff(&vmx->vcpu, intr_info); 6379 } 6380 6381 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6382 { 6383 u32 intr_info = vmx_get_intr_info(vcpu); 6384 6385 if (WARN_ONCE(!is_external_intr(intr_info), 6386 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6387 return; 6388 6389 handle_interrupt_nmi_irqoff(vcpu, intr_info); 6390 } 6391 6392 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu) 6393 { 6394 struct vcpu_vmx *vmx = to_vmx(vcpu); 6395 6396 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6397 handle_external_interrupt_irqoff(vcpu); 6398 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6399 handle_exception_nmi_irqoff(vmx); 6400 } 6401 6402 static bool vmx_has_emulated_msr(u32 index) 6403 { 6404 switch (index) { 6405 case MSR_IA32_SMBASE: 6406 /* 6407 * We cannot do SMM unless we can run the guest in big 6408 * real mode. 6409 */ 6410 return enable_unrestricted_guest || emulate_invalid_guest_state; 6411 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6412 return nested; 6413 case MSR_AMD64_VIRT_SPEC_CTRL: 6414 /* This is AMD only. */ 6415 return false; 6416 default: 6417 return true; 6418 } 6419 } 6420 6421 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6422 { 6423 u32 exit_intr_info; 6424 bool unblock_nmi; 6425 u8 vector; 6426 bool idtv_info_valid; 6427 6428 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6429 6430 if (enable_vnmi) { 6431 if (vmx->loaded_vmcs->nmi_known_unmasked) 6432 return; 6433 6434 exit_intr_info = vmx_get_intr_info(&vmx->vcpu); 6435 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6436 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6437 /* 6438 * SDM 3: 27.7.1.2 (September 2008) 6439 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6440 * a guest IRET fault. 6441 * SDM 3: 23.2.2 (September 2008) 6442 * Bit 12 is undefined in any of the following cases: 6443 * If the VM exit sets the valid bit in the IDT-vectoring 6444 * information field. 6445 * If the VM exit is due to a double fault. 6446 */ 6447 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6448 vector != DF_VECTOR && !idtv_info_valid) 6449 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6450 GUEST_INTR_STATE_NMI); 6451 else 6452 vmx->loaded_vmcs->nmi_known_unmasked = 6453 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6454 & GUEST_INTR_STATE_NMI); 6455 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6456 vmx->loaded_vmcs->vnmi_blocked_time += 6457 ktime_to_ns(ktime_sub(ktime_get(), 6458 vmx->loaded_vmcs->entry_time)); 6459 } 6460 6461 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6462 u32 idt_vectoring_info, 6463 int instr_len_field, 6464 int error_code_field) 6465 { 6466 u8 vector; 6467 int type; 6468 bool idtv_info_valid; 6469 6470 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6471 6472 vcpu->arch.nmi_injected = false; 6473 kvm_clear_exception_queue(vcpu); 6474 kvm_clear_interrupt_queue(vcpu); 6475 6476 if (!idtv_info_valid) 6477 return; 6478 6479 kvm_make_request(KVM_REQ_EVENT, vcpu); 6480 6481 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6482 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6483 6484 switch (type) { 6485 case INTR_TYPE_NMI_INTR: 6486 vcpu->arch.nmi_injected = true; 6487 /* 6488 * SDM 3: 27.7.1.2 (September 2008) 6489 * Clear bit "block by NMI" before VM entry if a NMI 6490 * delivery faulted. 6491 */ 6492 vmx_set_nmi_mask(vcpu, false); 6493 break; 6494 case INTR_TYPE_SOFT_EXCEPTION: 6495 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6496 fallthrough; 6497 case INTR_TYPE_HARD_EXCEPTION: 6498 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6499 u32 err = vmcs_read32(error_code_field); 6500 kvm_requeue_exception_e(vcpu, vector, err); 6501 } else 6502 kvm_requeue_exception(vcpu, vector); 6503 break; 6504 case INTR_TYPE_SOFT_INTR: 6505 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6506 fallthrough; 6507 case INTR_TYPE_EXT_INTR: 6508 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6509 break; 6510 default: 6511 break; 6512 } 6513 } 6514 6515 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6516 { 6517 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6518 VM_EXIT_INSTRUCTION_LEN, 6519 IDT_VECTORING_ERROR_CODE); 6520 } 6521 6522 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6523 { 6524 __vmx_complete_interrupts(vcpu, 6525 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6526 VM_ENTRY_INSTRUCTION_LEN, 6527 VM_ENTRY_EXCEPTION_ERROR_CODE); 6528 6529 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6530 } 6531 6532 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6533 { 6534 int i, nr_msrs; 6535 struct perf_guest_switch_msr *msrs; 6536 6537 msrs = perf_guest_get_msrs(&nr_msrs); 6538 6539 if (!msrs) 6540 return; 6541 6542 for (i = 0; i < nr_msrs; i++) 6543 if (msrs[i].host == msrs[i].guest) 6544 clear_atomic_switch_msr(vmx, msrs[i].msr); 6545 else 6546 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6547 msrs[i].host, false); 6548 } 6549 6550 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6551 { 6552 struct vcpu_vmx *vmx = to_vmx(vcpu); 6553 u64 tscl; 6554 u32 delta_tsc; 6555 6556 if (vmx->req_immediate_exit) { 6557 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6558 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6559 } else if (vmx->hv_deadline_tsc != -1) { 6560 tscl = rdtsc(); 6561 if (vmx->hv_deadline_tsc > tscl) 6562 /* set_hv_timer ensures the delta fits in 32-bits */ 6563 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6564 cpu_preemption_timer_multi); 6565 else 6566 delta_tsc = 0; 6567 6568 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6569 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6570 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6571 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6572 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6573 } 6574 } 6575 6576 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6577 { 6578 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6579 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6580 vmcs_writel(HOST_RSP, host_rsp); 6581 } 6582 } 6583 6584 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu) 6585 { 6586 switch (to_vmx(vcpu)->exit_reason) { 6587 case EXIT_REASON_MSR_WRITE: 6588 return handle_fastpath_set_msr_irqoff(vcpu); 6589 case EXIT_REASON_PREEMPTION_TIMER: 6590 return handle_fastpath_preemption_timer(vcpu); 6591 default: 6592 return EXIT_FASTPATH_NONE; 6593 } 6594 } 6595 6596 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6597 6598 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu, 6599 struct vcpu_vmx *vmx) 6600 { 6601 /* 6602 * VMENTER enables interrupts (host state), but the kernel state is 6603 * interrupts disabled when this is invoked. Also tell RCU about 6604 * it. This is the same logic as for exit_to_user_mode(). 6605 * 6606 * This ensures that e.g. latency analysis on the host observes 6607 * guest mode as interrupt enabled. 6608 * 6609 * guest_enter_irqoff() informs context tracking about the 6610 * transition to guest mode and if enabled adjusts RCU state 6611 * accordingly. 6612 */ 6613 instrumentation_begin(); 6614 trace_hardirqs_on_prepare(); 6615 lockdep_hardirqs_on_prepare(CALLER_ADDR0); 6616 instrumentation_end(); 6617 6618 guest_enter_irqoff(); 6619 lockdep_hardirqs_on(CALLER_ADDR0); 6620 6621 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6622 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6623 vmx_l1d_flush(vcpu); 6624 else if (static_branch_unlikely(&mds_user_clear)) 6625 mds_clear_cpu_buffers(); 6626 6627 if (vcpu->arch.cr2 != native_read_cr2()) 6628 native_write_cr2(vcpu->arch.cr2); 6629 6630 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6631 vmx->loaded_vmcs->launched); 6632 6633 vcpu->arch.cr2 = native_read_cr2(); 6634 6635 /* 6636 * VMEXIT disables interrupts (host state), but tracing and lockdep 6637 * have them in state 'on' as recorded before entering guest mode. 6638 * Same as enter_from_user_mode(). 6639 * 6640 * guest_exit_irqoff() restores host context and reinstates RCU if 6641 * enabled and required. 6642 * 6643 * This needs to be done before the below as native_read_msr() 6644 * contains a tracepoint and x86_spec_ctrl_restore_host() calls 6645 * into world and some more. 6646 */ 6647 lockdep_hardirqs_off(CALLER_ADDR0); 6648 guest_exit_irqoff(); 6649 6650 instrumentation_begin(); 6651 trace_hardirqs_off_finish(); 6652 instrumentation_end(); 6653 } 6654 6655 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu) 6656 { 6657 fastpath_t exit_fastpath; 6658 struct vcpu_vmx *vmx = to_vmx(vcpu); 6659 unsigned long cr3, cr4; 6660 6661 reenter_guest: 6662 /* Record the guest's net vcpu time for enforced NMI injections. */ 6663 if (unlikely(!enable_vnmi && 6664 vmx->loaded_vmcs->soft_vnmi_blocked)) 6665 vmx->loaded_vmcs->entry_time = ktime_get(); 6666 6667 /* Don't enter VMX if guest state is invalid, let the exit handler 6668 start emulation until we arrive back to a valid state */ 6669 if (vmx->emulation_required) 6670 return EXIT_FASTPATH_NONE; 6671 6672 if (vmx->ple_window_dirty) { 6673 vmx->ple_window_dirty = false; 6674 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6675 } 6676 6677 /* 6678 * We did this in prepare_switch_to_guest, because it needs to 6679 * be within srcu_read_lock. 6680 */ 6681 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync); 6682 6683 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6684 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6685 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6686 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6687 6688 cr3 = __get_current_cr3_fast(); 6689 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6690 vmcs_writel(HOST_CR3, cr3); 6691 vmx->loaded_vmcs->host_state.cr3 = cr3; 6692 } 6693 6694 cr4 = cr4_read_shadow(); 6695 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6696 vmcs_writel(HOST_CR4, cr4); 6697 vmx->loaded_vmcs->host_state.cr4 = cr4; 6698 } 6699 6700 /* When single-stepping over STI and MOV SS, we must clear the 6701 * corresponding interruptibility bits in the guest state. Otherwise 6702 * vmentry fails as it then expects bit 14 (BS) in pending debug 6703 * exceptions being set, but that's not correct for the guest debugging 6704 * case. */ 6705 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6706 vmx_set_interrupt_shadow(vcpu, 0); 6707 6708 kvm_load_guest_xsave_state(vcpu); 6709 6710 pt_guest_enter(vmx); 6711 6712 atomic_switch_perf_msrs(vmx); 6713 6714 if (enable_preemption_timer) 6715 vmx_update_hv_timer(vcpu); 6716 6717 kvm_wait_lapic_expire(vcpu); 6718 6719 /* 6720 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6721 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6722 * is no need to worry about the conditional branch over the wrmsr 6723 * being speculatively taken. 6724 */ 6725 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6726 6727 /* The actual VMENTER/EXIT is in the .noinstr.text section. */ 6728 vmx_vcpu_enter_exit(vcpu, vmx); 6729 6730 /* 6731 * We do not use IBRS in the kernel. If this vCPU has used the 6732 * SPEC_CTRL MSR it may have left it on; save the value and 6733 * turn it off. This is much more efficient than blindly adding 6734 * it to the atomic save/restore list. Especially as the former 6735 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6736 * 6737 * For non-nested case: 6738 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6739 * save it. 6740 * 6741 * For nested case: 6742 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6743 * save it. 6744 */ 6745 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6746 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6747 6748 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6749 6750 /* All fields are clean at this point */ 6751 if (static_branch_unlikely(&enable_evmcs)) 6752 current_evmcs->hv_clean_fields |= 6753 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6754 6755 if (static_branch_unlikely(&enable_evmcs)) 6756 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6757 6758 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6759 if (vmx->host_debugctlmsr) 6760 update_debugctlmsr(vmx->host_debugctlmsr); 6761 6762 #ifndef CONFIG_X86_64 6763 /* 6764 * The sysexit path does not restore ds/es, so we must set them to 6765 * a reasonable value ourselves. 6766 * 6767 * We can't defer this to vmx_prepare_switch_to_host() since that 6768 * function may be executed in interrupt context, which saves and 6769 * restore segments around it, nullifying its effect. 6770 */ 6771 loadsegment(ds, __USER_DS); 6772 loadsegment(es, __USER_DS); 6773 #endif 6774 6775 vmx_register_cache_reset(vcpu); 6776 6777 pt_guest_exit(vmx); 6778 6779 kvm_load_host_xsave_state(vcpu); 6780 6781 vmx->nested.nested_run_pending = 0; 6782 vmx->idt_vectoring_info = 0; 6783 6784 if (unlikely(vmx->fail)) { 6785 vmx->exit_reason = 0xdead; 6786 return EXIT_FASTPATH_NONE; 6787 } 6788 6789 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); 6790 if (unlikely((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)) 6791 kvm_machine_check(); 6792 6793 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX); 6794 6795 if (unlikely(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6796 return EXIT_FASTPATH_NONE; 6797 6798 vmx->loaded_vmcs->launched = 1; 6799 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6800 6801 vmx_recover_nmi_blocking(vmx); 6802 vmx_complete_interrupts(vmx); 6803 6804 if (is_guest_mode(vcpu)) 6805 return EXIT_FASTPATH_NONE; 6806 6807 exit_fastpath = vmx_exit_handlers_fastpath(vcpu); 6808 if (exit_fastpath == EXIT_FASTPATH_REENTER_GUEST) { 6809 if (!kvm_vcpu_exit_request(vcpu)) { 6810 /* 6811 * FIXME: this goto should be a loop in vcpu_enter_guest, 6812 * but it would incur the cost of a retpoline for now. 6813 * Revisit once static calls are available. 6814 */ 6815 if (vcpu->arch.apicv_active) 6816 vmx_sync_pir_to_irr(vcpu); 6817 goto reenter_guest; 6818 } 6819 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 6820 } 6821 6822 return exit_fastpath; 6823 } 6824 6825 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6826 { 6827 struct vcpu_vmx *vmx = to_vmx(vcpu); 6828 6829 if (enable_pml) 6830 vmx_destroy_pml_buffer(vmx); 6831 free_vpid(vmx->vpid); 6832 nested_vmx_free_vcpu(vcpu); 6833 free_loaded_vmcs(vmx->loaded_vmcs); 6834 } 6835 6836 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6837 { 6838 struct vcpu_vmx *vmx; 6839 int i, cpu, err; 6840 6841 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6842 vmx = to_vmx(vcpu); 6843 6844 err = -ENOMEM; 6845 6846 vmx->vpid = allocate_vpid(); 6847 6848 /* 6849 * If PML is turned on, failure on enabling PML just results in failure 6850 * of creating the vcpu, therefore we can simplify PML logic (by 6851 * avoiding dealing with cases, such as enabling PML partially on vcpus 6852 * for the guest), etc. 6853 */ 6854 if (enable_pml) { 6855 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6856 if (!vmx->pml_pg) 6857 goto free_vpid; 6858 } 6859 6860 BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS); 6861 6862 for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i) { 6863 u32 index = vmx_uret_msrs_list[i]; 6864 u32 data_low, data_high; 6865 int j = vmx->nr_uret_msrs; 6866 6867 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6868 continue; 6869 if (wrmsr_safe(index, data_low, data_high) < 0) 6870 continue; 6871 6872 vmx->guest_uret_msrs[j].slot = i; 6873 vmx->guest_uret_msrs[j].data = 0; 6874 switch (index) { 6875 case MSR_IA32_TSX_CTRL: 6876 /* 6877 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6878 * let's avoid changing CPUID bits under the host 6879 * kernel's feet. 6880 */ 6881 vmx->guest_uret_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6882 break; 6883 default: 6884 vmx->guest_uret_msrs[j].mask = -1ull; 6885 break; 6886 } 6887 ++vmx->nr_uret_msrs; 6888 } 6889 6890 err = alloc_loaded_vmcs(&vmx->vmcs01); 6891 if (err < 0) 6892 goto free_pml; 6893 6894 /* The MSR bitmap starts with all ones */ 6895 bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS); 6896 bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS); 6897 6898 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R); 6899 vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW); 6900 vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW); 6901 vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6902 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6903 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6904 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6905 if (kvm_cstate_in_guest(vcpu->kvm)) { 6906 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R); 6907 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6908 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6909 vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6910 } 6911 vmx->msr_bitmap_mode = 0; 6912 6913 vmx->loaded_vmcs = &vmx->vmcs01; 6914 cpu = get_cpu(); 6915 vmx_vcpu_load(vcpu, cpu); 6916 vcpu->cpu = cpu; 6917 init_vmcs(vmx); 6918 vmx_vcpu_put(vcpu); 6919 put_cpu(); 6920 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6921 err = alloc_apic_access_page(vcpu->kvm); 6922 if (err) 6923 goto free_vmcs; 6924 } 6925 6926 if (enable_ept && !enable_unrestricted_guest) { 6927 err = init_rmode_identity_map(vcpu->kvm); 6928 if (err) 6929 goto free_vmcs; 6930 } 6931 6932 if (nested) 6933 memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs)); 6934 else 6935 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6936 6937 vmx->nested.posted_intr_nv = -1; 6938 vmx->nested.current_vmptr = -1ull; 6939 6940 vcpu->arch.microcode_version = 0x100000000ULL; 6941 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6942 6943 /* 6944 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6945 * or POSTED_INTR_WAKEUP_VECTOR. 6946 */ 6947 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6948 vmx->pi_desc.sn = 1; 6949 6950 vmx->ept_pointer = INVALID_PAGE; 6951 6952 return 0; 6953 6954 free_vmcs: 6955 free_loaded_vmcs(vmx->loaded_vmcs); 6956 free_pml: 6957 vmx_destroy_pml_buffer(vmx); 6958 free_vpid: 6959 free_vpid(vmx->vpid); 6960 return err; 6961 } 6962 6963 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6964 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6965 6966 static int vmx_vm_init(struct kvm *kvm) 6967 { 6968 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6969 6970 if (!ple_gap) 6971 kvm->arch.pause_in_guest = true; 6972 6973 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6974 switch (l1tf_mitigation) { 6975 case L1TF_MITIGATION_OFF: 6976 case L1TF_MITIGATION_FLUSH_NOWARN: 6977 /* 'I explicitly don't care' is set */ 6978 break; 6979 case L1TF_MITIGATION_FLUSH: 6980 case L1TF_MITIGATION_FLUSH_NOSMT: 6981 case L1TF_MITIGATION_FULL: 6982 /* 6983 * Warn upon starting the first VM in a potentially 6984 * insecure environment. 6985 */ 6986 if (sched_smt_active()) 6987 pr_warn_once(L1TF_MSG_SMT); 6988 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6989 pr_warn_once(L1TF_MSG_L1D); 6990 break; 6991 case L1TF_MITIGATION_FULL_FORCE: 6992 /* Flush is enforced */ 6993 break; 6994 } 6995 } 6996 kvm_apicv_init(kvm, enable_apicv); 6997 return 0; 6998 } 6999 7000 static int __init vmx_check_processor_compat(void) 7001 { 7002 struct vmcs_config vmcs_conf; 7003 struct vmx_capability vmx_cap; 7004 7005 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 7006 !this_cpu_has(X86_FEATURE_VMX)) { 7007 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 7008 return -EIO; 7009 } 7010 7011 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 7012 return -EIO; 7013 if (nested) 7014 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept); 7015 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 7016 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 7017 smp_processor_id()); 7018 return -EIO; 7019 } 7020 return 0; 7021 } 7022 7023 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 7024 { 7025 u8 cache; 7026 u64 ipat = 0; 7027 7028 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in 7029 * memory aliases with conflicting memory types and sometimes MCEs. 7030 * We have to be careful as to what are honored and when. 7031 * 7032 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to 7033 * UC. The effective memory type is UC or WC depending on guest PAT. 7034 * This was historically the source of MCEs and we want to be 7035 * conservative. 7036 * 7037 * When there is no need to deal with noncoherent DMA (e.g., no VT-d 7038 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The 7039 * EPT memory type is set to WB. The effective memory type is forced 7040 * WB. 7041 * 7042 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The 7043 * EPT memory type is used to emulate guest CD/MTRR. 7044 */ 7045 7046 if (is_mmio) { 7047 cache = MTRR_TYPE_UNCACHABLE; 7048 goto exit; 7049 } 7050 7051 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 7052 ipat = VMX_EPT_IPAT_BIT; 7053 cache = MTRR_TYPE_WRBACK; 7054 goto exit; 7055 } 7056 7057 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 7058 ipat = VMX_EPT_IPAT_BIT; 7059 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 7060 cache = MTRR_TYPE_WRBACK; 7061 else 7062 cache = MTRR_TYPE_UNCACHABLE; 7063 goto exit; 7064 } 7065 7066 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 7067 7068 exit: 7069 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 7070 } 7071 7072 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 7073 { 7074 /* 7075 * These bits in the secondary execution controls field 7076 * are dynamic, the others are mostly based on the hypervisor 7077 * architecture and the guest's CPUID. Do not touch the 7078 * dynamic bits. 7079 */ 7080 u32 mask = 7081 SECONDARY_EXEC_SHADOW_VMCS | 7082 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 7083 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 7084 SECONDARY_EXEC_DESC; 7085 7086 u32 new_ctl = vmx->secondary_exec_control; 7087 u32 cur_ctl = secondary_exec_controls_get(vmx); 7088 7089 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 7090 } 7091 7092 /* 7093 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 7094 * (indicating "allowed-1") if they are supported in the guest's CPUID. 7095 */ 7096 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 7097 { 7098 struct vcpu_vmx *vmx = to_vmx(vcpu); 7099 struct kvm_cpuid_entry2 *entry; 7100 7101 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 7102 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 7103 7104 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 7105 if (entry && (entry->_reg & (_cpuid_mask))) \ 7106 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 7107 } while (0) 7108 7109 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 7110 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 7111 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 7112 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 7113 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 7114 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 7115 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 7116 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 7117 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 7118 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 7119 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 7120 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 7121 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 7122 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 7123 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 7124 7125 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 7126 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 7127 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 7128 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 7129 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 7130 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 7131 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 7132 7133 #undef cr4_fixed1_update 7134 } 7135 7136 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 7137 { 7138 struct vcpu_vmx *vmx = to_vmx(vcpu); 7139 7140 if (kvm_mpx_supported()) { 7141 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 7142 7143 if (mpx_enabled) { 7144 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 7145 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 7146 } else { 7147 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 7148 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 7149 } 7150 } 7151 } 7152 7153 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7154 { 7155 struct vcpu_vmx *vmx = to_vmx(vcpu); 7156 struct kvm_cpuid_entry2 *best = NULL; 7157 int i; 7158 7159 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7160 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7161 if (!best) 7162 return; 7163 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7164 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7165 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7166 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7167 } 7168 7169 /* Get the number of configurable Address Ranges for filtering */ 7170 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7171 PT_CAP_num_address_ranges); 7172 7173 /* Initialize and clear the no dependency bits */ 7174 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7175 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7176 7177 /* 7178 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7179 * will inject an #GP 7180 */ 7181 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7182 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7183 7184 /* 7185 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7186 * PSBFreq can be set 7187 */ 7188 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7189 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7190 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7191 7192 /* 7193 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7194 * MTCFreq can be set 7195 */ 7196 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7197 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7198 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7199 7200 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7201 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7202 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7203 RTIT_CTL_PTW_EN); 7204 7205 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7206 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7207 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7208 7209 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7210 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7211 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7212 7213 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7214 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7215 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7216 7217 /* unmask address range configure area */ 7218 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7219 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7220 } 7221 7222 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 7223 { 7224 struct vcpu_vmx *vmx = to_vmx(vcpu); 7225 7226 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7227 vcpu->arch.xsaves_enabled = false; 7228 7229 if (cpu_has_secondary_exec_ctrls()) { 7230 vmx_compute_secondary_exec_control(vmx); 7231 vmcs_set_secondary_exec_control(vmx); 7232 } 7233 7234 if (nested_vmx_allowed(vcpu)) 7235 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7236 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7237 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7238 else 7239 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7240 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7241 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7242 7243 if (nested_vmx_allowed(vcpu)) { 7244 nested_vmx_cr_fixed1_bits_update(vcpu); 7245 nested_vmx_entry_exit_ctls_update(vcpu); 7246 } 7247 7248 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7249 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7250 update_intel_pt_cfg(vcpu); 7251 7252 if (boot_cpu_has(X86_FEATURE_RTM)) { 7253 struct vmx_uret_msr *msr; 7254 msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL); 7255 if (msr) { 7256 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7257 vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7258 } 7259 } 7260 7261 set_cr4_guest_host_mask(vmx); 7262 7263 /* Refresh #PF interception to account for MAXPHYADDR changes. */ 7264 update_exception_bitmap(vcpu); 7265 } 7266 7267 static __init void vmx_set_cpu_caps(void) 7268 { 7269 kvm_set_cpu_caps(); 7270 7271 /* CPUID 0x1 */ 7272 if (nested) 7273 kvm_cpu_cap_set(X86_FEATURE_VMX); 7274 7275 /* CPUID 0x7 */ 7276 if (kvm_mpx_supported()) 7277 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX); 7278 if (cpu_has_vmx_invpcid()) 7279 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID); 7280 if (vmx_pt_mode_is_host_guest()) 7281 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT); 7282 7283 if (vmx_umip_emulated()) 7284 kvm_cpu_cap_set(X86_FEATURE_UMIP); 7285 7286 /* CPUID 0xD.1 */ 7287 supported_xss = 0; 7288 if (!cpu_has_vmx_xsaves()) 7289 kvm_cpu_cap_clear(X86_FEATURE_XSAVES); 7290 7291 /* CPUID 0x80000001 */ 7292 if (!cpu_has_vmx_rdtscp()) 7293 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 7294 7295 if (cpu_has_vmx_waitpkg()) 7296 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG); 7297 } 7298 7299 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7300 { 7301 to_vmx(vcpu)->req_immediate_exit = true; 7302 } 7303 7304 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, 7305 struct x86_instruction_info *info) 7306 { 7307 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7308 unsigned short port; 7309 bool intercept; 7310 int size; 7311 7312 if (info->intercept == x86_intercept_in || 7313 info->intercept == x86_intercept_ins) { 7314 port = info->src_val; 7315 size = info->dst_bytes; 7316 } else { 7317 port = info->dst_val; 7318 size = info->src_bytes; 7319 } 7320 7321 /* 7322 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction 7323 * VM-exits depend on the 'unconditional IO exiting' VM-execution 7324 * control. 7325 * 7326 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. 7327 */ 7328 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 7329 intercept = nested_cpu_has(vmcs12, 7330 CPU_BASED_UNCOND_IO_EXITING); 7331 else 7332 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); 7333 7334 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7335 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 7336 } 7337 7338 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7339 struct x86_instruction_info *info, 7340 enum x86_intercept_stage stage, 7341 struct x86_exception *exception) 7342 { 7343 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7344 7345 switch (info->intercept) { 7346 /* 7347 * RDPID causes #UD if disabled through secondary execution controls. 7348 * Because it is marked as EmulateOnUD, we need to intercept it here. 7349 */ 7350 case x86_intercept_rdtscp: 7351 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) { 7352 exception->vector = UD_VECTOR; 7353 exception->error_code_valid = false; 7354 return X86EMUL_PROPAGATE_FAULT; 7355 } 7356 break; 7357 7358 case x86_intercept_in: 7359 case x86_intercept_ins: 7360 case x86_intercept_out: 7361 case x86_intercept_outs: 7362 return vmx_check_intercept_io(vcpu, info); 7363 7364 case x86_intercept_lgdt: 7365 case x86_intercept_lidt: 7366 case x86_intercept_lldt: 7367 case x86_intercept_ltr: 7368 case x86_intercept_sgdt: 7369 case x86_intercept_sidt: 7370 case x86_intercept_sldt: 7371 case x86_intercept_str: 7372 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC)) 7373 return X86EMUL_CONTINUE; 7374 7375 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7376 break; 7377 7378 /* TODO: check more intercepts... */ 7379 default: 7380 break; 7381 } 7382 7383 return X86EMUL_UNHANDLEABLE; 7384 } 7385 7386 #ifdef CONFIG_X86_64 7387 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7388 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7389 u64 divisor, u64 *result) 7390 { 7391 u64 low = a << shift, high = a >> (64 - shift); 7392 7393 /* To avoid the overflow on divq */ 7394 if (high >= divisor) 7395 return 1; 7396 7397 /* Low hold the result, high hold rem which is discarded */ 7398 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7399 "rm" (divisor), "0" (low), "1" (high)); 7400 *result = low; 7401 7402 return 0; 7403 } 7404 7405 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7406 bool *expired) 7407 { 7408 struct vcpu_vmx *vmx; 7409 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7410 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7411 7412 vmx = to_vmx(vcpu); 7413 tscl = rdtsc(); 7414 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7415 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7416 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7417 ktimer->timer_advance_ns); 7418 7419 if (delta_tsc > lapic_timer_advance_cycles) 7420 delta_tsc -= lapic_timer_advance_cycles; 7421 else 7422 delta_tsc = 0; 7423 7424 /* Convert to host delta tsc if tsc scaling is enabled */ 7425 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7426 delta_tsc && u64_shl_div_u64(delta_tsc, 7427 kvm_tsc_scaling_ratio_frac_bits, 7428 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7429 return -ERANGE; 7430 7431 /* 7432 * If the delta tsc can't fit in the 32 bit after the multi shift, 7433 * we can't use the preemption timer. 7434 * It's possible that it fits on later vmentries, but checking 7435 * on every vmentry is costly so we just use an hrtimer. 7436 */ 7437 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7438 return -ERANGE; 7439 7440 vmx->hv_deadline_tsc = tscl + delta_tsc; 7441 *expired = !delta_tsc; 7442 return 0; 7443 } 7444 7445 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7446 { 7447 to_vmx(vcpu)->hv_deadline_tsc = -1; 7448 } 7449 #endif 7450 7451 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7452 { 7453 if (!kvm_pause_in_guest(vcpu->kvm)) 7454 shrink_ple_window(vcpu); 7455 } 7456 7457 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7458 struct kvm_memory_slot *slot) 7459 { 7460 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 7461 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7462 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7463 } 7464 7465 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7466 struct kvm_memory_slot *slot) 7467 { 7468 kvm_mmu_slot_set_dirty(kvm, slot); 7469 } 7470 7471 static void vmx_flush_log_dirty(struct kvm *kvm) 7472 { 7473 kvm_flush_pml_buffers(kvm); 7474 } 7475 7476 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7477 struct kvm_memory_slot *memslot, 7478 gfn_t offset, unsigned long mask) 7479 { 7480 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7481 } 7482 7483 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7484 { 7485 if (pi_pre_block(vcpu)) 7486 return 1; 7487 7488 if (kvm_lapic_hv_timer_in_use(vcpu)) 7489 kvm_lapic_switch_to_sw_timer(vcpu); 7490 7491 return 0; 7492 } 7493 7494 static void vmx_post_block(struct kvm_vcpu *vcpu) 7495 { 7496 if (kvm_x86_ops.set_hv_timer) 7497 kvm_lapic_switch_to_hv_timer(vcpu); 7498 7499 pi_post_block(vcpu); 7500 } 7501 7502 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7503 { 7504 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7505 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7506 FEAT_CTL_LMCE_ENABLED; 7507 else 7508 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7509 ~FEAT_CTL_LMCE_ENABLED; 7510 } 7511 7512 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection) 7513 { 7514 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7515 if (to_vmx(vcpu)->nested.nested_run_pending) 7516 return -EBUSY; 7517 return !is_smm(vcpu); 7518 } 7519 7520 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7521 { 7522 struct vcpu_vmx *vmx = to_vmx(vcpu); 7523 7524 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7525 if (vmx->nested.smm.guest_mode) 7526 nested_vmx_vmexit(vcpu, -1, 0, 0); 7527 7528 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7529 vmx->nested.vmxon = false; 7530 vmx_clear_hlt(vcpu); 7531 return 0; 7532 } 7533 7534 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7535 { 7536 struct vcpu_vmx *vmx = to_vmx(vcpu); 7537 int ret; 7538 7539 if (vmx->nested.smm.vmxon) { 7540 vmx->nested.vmxon = true; 7541 vmx->nested.smm.vmxon = false; 7542 } 7543 7544 if (vmx->nested.smm.guest_mode) { 7545 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7546 if (ret) 7547 return ret; 7548 7549 vmx->nested.smm.guest_mode = false; 7550 } 7551 return 0; 7552 } 7553 7554 static void enable_smi_window(struct kvm_vcpu *vcpu) 7555 { 7556 /* RSM will cause a vmexit anyway. */ 7557 } 7558 7559 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7560 { 7561 return to_vmx(vcpu)->nested.vmxon; 7562 } 7563 7564 static void vmx_migrate_timers(struct kvm_vcpu *vcpu) 7565 { 7566 if (is_guest_mode(vcpu)) { 7567 struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer; 7568 7569 if (hrtimer_try_to_cancel(timer) == 1) 7570 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); 7571 } 7572 } 7573 7574 static void hardware_unsetup(void) 7575 { 7576 if (nested) 7577 nested_vmx_hardware_unsetup(); 7578 7579 free_kvm_area(); 7580 } 7581 7582 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7583 { 7584 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7585 BIT(APICV_INHIBIT_REASON_HYPERV); 7586 7587 return supported & BIT(bit); 7588 } 7589 7590 static struct kvm_x86_ops vmx_x86_ops __initdata = { 7591 .hardware_unsetup = hardware_unsetup, 7592 7593 .hardware_enable = hardware_enable, 7594 .hardware_disable = hardware_disable, 7595 .cpu_has_accelerated_tpr = report_flexpriority, 7596 .has_emulated_msr = vmx_has_emulated_msr, 7597 7598 .vm_size = sizeof(struct kvm_vmx), 7599 .vm_init = vmx_vm_init, 7600 7601 .vcpu_create = vmx_create_vcpu, 7602 .vcpu_free = vmx_free_vcpu, 7603 .vcpu_reset = vmx_vcpu_reset, 7604 7605 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7606 .vcpu_load = vmx_vcpu_load, 7607 .vcpu_put = vmx_vcpu_put, 7608 7609 .update_exception_bitmap = update_exception_bitmap, 7610 .get_msr_feature = vmx_get_msr_feature, 7611 .get_msr = vmx_get_msr, 7612 .set_msr = vmx_set_msr, 7613 .get_segment_base = vmx_get_segment_base, 7614 .get_segment = vmx_get_segment, 7615 .set_segment = vmx_set_segment, 7616 .get_cpl = vmx_get_cpl, 7617 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7618 .set_cr0 = vmx_set_cr0, 7619 .set_cr4 = vmx_set_cr4, 7620 .set_efer = vmx_set_efer, 7621 .get_idt = vmx_get_idt, 7622 .set_idt = vmx_set_idt, 7623 .get_gdt = vmx_get_gdt, 7624 .set_gdt = vmx_set_gdt, 7625 .set_dr7 = vmx_set_dr7, 7626 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7627 .cache_reg = vmx_cache_reg, 7628 .get_rflags = vmx_get_rflags, 7629 .set_rflags = vmx_set_rflags, 7630 7631 .tlb_flush_all = vmx_flush_tlb_all, 7632 .tlb_flush_current = vmx_flush_tlb_current, 7633 .tlb_flush_gva = vmx_flush_tlb_gva, 7634 .tlb_flush_guest = vmx_flush_tlb_guest, 7635 7636 .run = vmx_vcpu_run, 7637 .handle_exit = vmx_handle_exit, 7638 .skip_emulated_instruction = vmx_skip_emulated_instruction, 7639 .update_emulated_instruction = vmx_update_emulated_instruction, 7640 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7641 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7642 .patch_hypercall = vmx_patch_hypercall, 7643 .set_irq = vmx_inject_irq, 7644 .set_nmi = vmx_inject_nmi, 7645 .queue_exception = vmx_queue_exception, 7646 .cancel_injection = vmx_cancel_injection, 7647 .interrupt_allowed = vmx_interrupt_allowed, 7648 .nmi_allowed = vmx_nmi_allowed, 7649 .get_nmi_mask = vmx_get_nmi_mask, 7650 .set_nmi_mask = vmx_set_nmi_mask, 7651 .enable_nmi_window = enable_nmi_window, 7652 .enable_irq_window = enable_irq_window, 7653 .update_cr8_intercept = update_cr8_intercept, 7654 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7655 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7656 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7657 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7658 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7659 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7660 .hwapic_irr_update = vmx_hwapic_irr_update, 7661 .hwapic_isr_update = vmx_hwapic_isr_update, 7662 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7663 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7664 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7665 .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt, 7666 7667 .set_tss_addr = vmx_set_tss_addr, 7668 .set_identity_map_addr = vmx_set_identity_map_addr, 7669 .get_mt_mask = vmx_get_mt_mask, 7670 7671 .get_exit_info = vmx_get_exit_info, 7672 7673 .vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid, 7674 7675 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7676 7677 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7678 7679 .load_mmu_pgd = vmx_load_mmu_pgd, 7680 7681 .check_intercept = vmx_check_intercept, 7682 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7683 7684 .request_immediate_exit = vmx_request_immediate_exit, 7685 7686 .sched_in = vmx_sched_in, 7687 7688 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7689 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7690 .flush_log_dirty = vmx_flush_log_dirty, 7691 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7692 7693 .pre_block = vmx_pre_block, 7694 .post_block = vmx_post_block, 7695 7696 .pmu_ops = &intel_pmu_ops, 7697 .nested_ops = &vmx_nested_ops, 7698 7699 .update_pi_irte = pi_update_irte, 7700 7701 #ifdef CONFIG_X86_64 7702 .set_hv_timer = vmx_set_hv_timer, 7703 .cancel_hv_timer = vmx_cancel_hv_timer, 7704 #endif 7705 7706 .setup_mce = vmx_setup_mce, 7707 7708 .smi_allowed = vmx_smi_allowed, 7709 .pre_enter_smm = vmx_pre_enter_smm, 7710 .pre_leave_smm = vmx_pre_leave_smm, 7711 .enable_smi_window = enable_smi_window, 7712 7713 .can_emulate_instruction = vmx_can_emulate_instruction, 7714 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7715 .migrate_timers = vmx_migrate_timers, 7716 7717 .msr_filter_changed = vmx_msr_filter_changed, 7718 }; 7719 7720 static __init int hardware_setup(void) 7721 { 7722 unsigned long host_bndcfgs; 7723 struct desc_ptr dt; 7724 int r, i, ept_lpage_level; 7725 7726 store_idt(&dt); 7727 host_idt_base = dt.address; 7728 7729 for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i) 7730 kvm_define_user_return_msr(i, vmx_uret_msrs_list[i]); 7731 7732 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7733 return -EIO; 7734 7735 if (boot_cpu_has(X86_FEATURE_NX)) 7736 kvm_enable_efer_bits(EFER_NX); 7737 7738 if (boot_cpu_has(X86_FEATURE_MPX)) { 7739 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7740 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7741 } 7742 7743 if (!cpu_has_vmx_mpx()) 7744 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | 7745 XFEATURE_MASK_BNDCSR); 7746 7747 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7748 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7749 enable_vpid = 0; 7750 7751 if (!cpu_has_vmx_ept() || 7752 !cpu_has_vmx_ept_4levels() || 7753 !cpu_has_vmx_ept_mt_wb() || 7754 !cpu_has_vmx_invept_global()) 7755 enable_ept = 0; 7756 7757 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7758 enable_ept_ad_bits = 0; 7759 7760 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7761 enable_unrestricted_guest = 0; 7762 7763 if (!cpu_has_vmx_flexpriority()) 7764 flexpriority_enabled = 0; 7765 7766 if (!cpu_has_virtual_nmis()) 7767 enable_vnmi = 0; 7768 7769 /* 7770 * set_apic_access_page_addr() is used to reload apic access 7771 * page upon invalidation. No need to do anything if not 7772 * using the APIC_ACCESS_ADDR VMCS field. 7773 */ 7774 if (!flexpriority_enabled) 7775 vmx_x86_ops.set_apic_access_page_addr = NULL; 7776 7777 if (!cpu_has_vmx_tpr_shadow()) 7778 vmx_x86_ops.update_cr8_intercept = NULL; 7779 7780 #if IS_ENABLED(CONFIG_HYPERV) 7781 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7782 && enable_ept) { 7783 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb; 7784 vmx_x86_ops.tlb_remote_flush_with_range = 7785 hv_remote_flush_tlb_with_range; 7786 } 7787 #endif 7788 7789 if (!cpu_has_vmx_ple()) { 7790 ple_gap = 0; 7791 ple_window = 0; 7792 ple_window_grow = 0; 7793 ple_window_max = 0; 7794 ple_window_shrink = 0; 7795 } 7796 7797 if (!cpu_has_vmx_apicv()) { 7798 enable_apicv = 0; 7799 vmx_x86_ops.sync_pir_to_irr = NULL; 7800 } 7801 7802 if (cpu_has_vmx_tsc_scaling()) { 7803 kvm_has_tsc_control = true; 7804 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7805 kvm_tsc_scaling_ratio_frac_bits = 48; 7806 } 7807 7808 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7809 7810 if (enable_ept) 7811 vmx_enable_tdp(); 7812 7813 if (!enable_ept) 7814 ept_lpage_level = 0; 7815 else if (cpu_has_vmx_ept_1g_page()) 7816 ept_lpage_level = PG_LEVEL_1G; 7817 else if (cpu_has_vmx_ept_2m_page()) 7818 ept_lpage_level = PG_LEVEL_2M; 7819 else 7820 ept_lpage_level = PG_LEVEL_4K; 7821 kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level); 7822 7823 /* 7824 * Only enable PML when hardware supports PML feature, and both EPT 7825 * and EPT A/D bit features are enabled -- PML depends on them to work. 7826 */ 7827 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7828 enable_pml = 0; 7829 7830 if (!enable_pml) { 7831 vmx_x86_ops.slot_enable_log_dirty = NULL; 7832 vmx_x86_ops.slot_disable_log_dirty = NULL; 7833 vmx_x86_ops.flush_log_dirty = NULL; 7834 vmx_x86_ops.enable_log_dirty_pt_masked = NULL; 7835 } 7836 7837 if (!cpu_has_vmx_preemption_timer()) 7838 enable_preemption_timer = false; 7839 7840 if (enable_preemption_timer) { 7841 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7842 u64 vmx_msr; 7843 7844 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7845 cpu_preemption_timer_multi = 7846 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7847 7848 if (tsc_khz) 7849 use_timer_freq = (u64)tsc_khz * 1000; 7850 use_timer_freq >>= cpu_preemption_timer_multi; 7851 7852 /* 7853 * KVM "disables" the preemption timer by setting it to its max 7854 * value. Don't use the timer if it might cause spurious exits 7855 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7856 */ 7857 if (use_timer_freq > 0xffffffffu / 10) 7858 enable_preemption_timer = false; 7859 } 7860 7861 if (!enable_preemption_timer) { 7862 vmx_x86_ops.set_hv_timer = NULL; 7863 vmx_x86_ops.cancel_hv_timer = NULL; 7864 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit; 7865 } 7866 7867 kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler); 7868 7869 kvm_mce_cap_supported |= MCG_LMCE_P; 7870 7871 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7872 return -EINVAL; 7873 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7874 pt_mode = PT_MODE_SYSTEM; 7875 7876 if (nested) { 7877 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7878 vmx_capability.ept); 7879 7880 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7881 if (r) 7882 return r; 7883 } 7884 7885 vmx_set_cpu_caps(); 7886 7887 r = alloc_kvm_area(); 7888 if (r) 7889 nested_vmx_hardware_unsetup(); 7890 return r; 7891 } 7892 7893 static struct kvm_x86_init_ops vmx_init_ops __initdata = { 7894 .cpu_has_kvm_support = cpu_has_kvm_support, 7895 .disabled_by_bios = vmx_disabled_by_bios, 7896 .check_processor_compatibility = vmx_check_processor_compat, 7897 .hardware_setup = hardware_setup, 7898 7899 .runtime_ops = &vmx_x86_ops, 7900 }; 7901 7902 static void vmx_cleanup_l1d_flush(void) 7903 { 7904 if (vmx_l1d_flush_pages) { 7905 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7906 vmx_l1d_flush_pages = NULL; 7907 } 7908 /* Restore state so sysfs ignores VMX */ 7909 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 7910 } 7911 7912 static void vmx_exit(void) 7913 { 7914 #ifdef CONFIG_KEXEC_CORE 7915 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 7916 synchronize_rcu(); 7917 #endif 7918 7919 kvm_exit(); 7920 7921 #if IS_ENABLED(CONFIG_HYPERV) 7922 if (static_branch_unlikely(&enable_evmcs)) { 7923 int cpu; 7924 struct hv_vp_assist_page *vp_ap; 7925 /* 7926 * Reset everything to support using non-enlightened VMCS 7927 * access later (e.g. when we reload the module with 7928 * enlightened_vmcs=0) 7929 */ 7930 for_each_online_cpu(cpu) { 7931 vp_ap = hv_get_vp_assist_page(cpu); 7932 7933 if (!vp_ap) 7934 continue; 7935 7936 vp_ap->nested_control.features.directhypercall = 0; 7937 vp_ap->current_nested_vmcs = 0; 7938 vp_ap->enlighten_vmentry = 0; 7939 } 7940 7941 static_branch_disable(&enable_evmcs); 7942 } 7943 #endif 7944 vmx_cleanup_l1d_flush(); 7945 } 7946 module_exit(vmx_exit); 7947 7948 static int __init vmx_init(void) 7949 { 7950 int r, cpu; 7951 7952 #if IS_ENABLED(CONFIG_HYPERV) 7953 /* 7954 * Enlightened VMCS usage should be recommended and the host needs 7955 * to support eVMCS v1 or above. We can also disable eVMCS support 7956 * with module parameter. 7957 */ 7958 if (enlightened_vmcs && 7959 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 7960 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 7961 KVM_EVMCS_VERSION) { 7962 int cpu; 7963 7964 /* Check that we have assist pages on all online CPUs */ 7965 for_each_online_cpu(cpu) { 7966 if (!hv_get_vp_assist_page(cpu)) { 7967 enlightened_vmcs = false; 7968 break; 7969 } 7970 } 7971 7972 if (enlightened_vmcs) { 7973 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 7974 static_branch_enable(&enable_evmcs); 7975 } 7976 7977 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 7978 vmx_x86_ops.enable_direct_tlbflush 7979 = hv_enable_direct_tlbflush; 7980 7981 } else { 7982 enlightened_vmcs = false; 7983 } 7984 #endif 7985 7986 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx), 7987 __alignof__(struct vcpu_vmx), THIS_MODULE); 7988 if (r) 7989 return r; 7990 7991 /* 7992 * Must be called after kvm_init() so enable_ept is properly set 7993 * up. Hand the parameter mitigation value in which was stored in 7994 * the pre module init parser. If no parameter was given, it will 7995 * contain 'auto' which will be turned into the default 'cond' 7996 * mitigation mode. 7997 */ 7998 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 7999 if (r) { 8000 vmx_exit(); 8001 return r; 8002 } 8003 8004 for_each_possible_cpu(cpu) { 8005 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 8006 8007 pi_init_cpu(cpu); 8008 } 8009 8010 #ifdef CONFIG_KEXEC_CORE 8011 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 8012 crash_vmclear_local_loaded_vmcss); 8013 #endif 8014 vmx_check_vmcs12_offsets(); 8015 8016 /* 8017 * Shadow paging doesn't have a (further) performance penalty 8018 * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it 8019 * by default 8020 */ 8021 if (!enable_ept) 8022 allow_smaller_maxphyaddr = true; 8023 8024 return 0; 8025 } 8026 module_init(vmx_init); 8027