1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/debugreg.h> 36 #include <asm/desc.h> 37 #include <asm/fpu/internal.h> 38 #include <asm/io.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/kexec.h> 41 #include <asm/perf_event.h> 42 #include <asm/mce.h> 43 #include <asm/mmu_context.h> 44 #include <asm/mshyperv.h> 45 #include <asm/mwait.h> 46 #include <asm/spec-ctrl.h> 47 #include <asm/virtext.h> 48 #include <asm/vmx.h> 49 50 #include "capabilities.h" 51 #include "cpuid.h" 52 #include "evmcs.h" 53 #include "irq.h" 54 #include "kvm_cache_regs.h" 55 #include "lapic.h" 56 #include "mmu.h" 57 #include "nested.h" 58 #include "ops.h" 59 #include "pmu.h" 60 #include "trace.h" 61 #include "vmcs.h" 62 #include "vmcs12.h" 63 #include "vmx.h" 64 #include "x86.h" 65 66 MODULE_AUTHOR("Qumranet"); 67 MODULE_LICENSE("GPL"); 68 69 #ifdef MODULE 70 static const struct x86_cpu_id vmx_cpu_id[] = { 71 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL), 72 {} 73 }; 74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 75 #endif 76 77 bool __read_mostly enable_vpid = 1; 78 module_param_named(vpid, enable_vpid, bool, 0444); 79 80 static bool __read_mostly enable_vnmi = 1; 81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 82 83 bool __read_mostly flexpriority_enabled = 1; 84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 85 86 bool __read_mostly enable_ept = 1; 87 module_param_named(ept, enable_ept, bool, S_IRUGO); 88 89 bool __read_mostly enable_unrestricted_guest = 1; 90 module_param_named(unrestricted_guest, 91 enable_unrestricted_guest, bool, S_IRUGO); 92 93 bool __read_mostly enable_ept_ad_bits = 1; 94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 95 96 static bool __read_mostly emulate_invalid_guest_state = true; 97 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 98 99 static bool __read_mostly fasteoi = 1; 100 module_param(fasteoi, bool, S_IRUGO); 101 102 bool __read_mostly enable_apicv = 1; 103 module_param(enable_apicv, bool, S_IRUGO); 104 105 /* 106 * If nested=1, nested virtualization is supported, i.e., guests may use 107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 108 * use VMX instructions. 109 */ 110 static bool __read_mostly nested = 1; 111 module_param(nested, bool, S_IRUGO); 112 113 bool __read_mostly enable_pml = 1; 114 module_param_named(pml, enable_pml, bool, S_IRUGO); 115 116 static bool __read_mostly dump_invalid_vmcs = 0; 117 module_param(dump_invalid_vmcs, bool, 0644); 118 119 #define MSR_BITMAP_MODE_X2APIC 1 120 #define MSR_BITMAP_MODE_X2APIC_APICV 2 121 122 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 123 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 125 static int __read_mostly cpu_preemption_timer_multi; 126 static bool __read_mostly enable_preemption_timer = 1; 127 #ifdef CONFIG_X86_64 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 129 #endif 130 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 133 #define KVM_VM_CR0_ALWAYS_ON \ 134 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 135 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 136 #define KVM_CR4_GUEST_OWNED_BITS \ 137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 138 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 139 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 143 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 145 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 147 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 148 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 149 RTIT_STATUS_BYTECNT)) 150 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 152 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 153 154 /* 155 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 156 * ple_gap: upper bound on the amount of time between two successive 157 * executions of PAUSE in a loop. Also indicate if ple enabled. 158 * According to test, this time is usually smaller than 128 cycles. 159 * ple_window: upper bound on the amount of time a guest is allowed to execute 160 * in a PAUSE loop. Tests indicate that most spinlocks are held for 161 * less than 2^12 cycles 162 * Time is measured based on a counter that runs at the same rate as the TSC, 163 * refer SDM volume 3b section 21.6.13 & 22.1.3. 164 */ 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 166 module_param(ple_gap, uint, 0444); 167 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 169 module_param(ple_window, uint, 0444); 170 171 /* Default doubles per-vcpu window every exit. */ 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 173 module_param(ple_window_grow, uint, 0444); 174 175 /* Default resets per-vcpu window every exit to ple_window. */ 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 177 module_param(ple_window_shrink, uint, 0444); 178 179 /* Default is to compute the maximum so we can never overflow. */ 180 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 181 module_param(ple_window_max, uint, 0444); 182 183 /* Default is SYSTEM mode, 1 for host-guest mode */ 184 int __read_mostly pt_mode = PT_MODE_SYSTEM; 185 module_param(pt_mode, int, S_IRUGO); 186 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 190 191 /* Storage for pre module init parameter parsing */ 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 193 194 static const struct { 195 const char *option; 196 bool for_parse; 197 } vmentry_l1d_param[] = { 198 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 199 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 200 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 201 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 202 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 203 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 204 }; 205 206 #define L1D_CACHE_ORDER 4 207 static void *vmx_l1d_flush_pages; 208 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 210 { 211 struct page *page; 212 unsigned int i; 213 214 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 215 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 216 return 0; 217 } 218 219 if (!enable_ept) { 220 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 221 return 0; 222 } 223 224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 225 u64 msr; 226 227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 228 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 229 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 230 return 0; 231 } 232 } 233 234 /* If set to auto use the default l1tf mitigation method */ 235 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 236 switch (l1tf_mitigation) { 237 case L1TF_MITIGATION_OFF: 238 l1tf = VMENTER_L1D_FLUSH_NEVER; 239 break; 240 case L1TF_MITIGATION_FLUSH_NOWARN: 241 case L1TF_MITIGATION_FLUSH: 242 case L1TF_MITIGATION_FLUSH_NOSMT: 243 l1tf = VMENTER_L1D_FLUSH_COND; 244 break; 245 case L1TF_MITIGATION_FULL: 246 case L1TF_MITIGATION_FULL_FORCE: 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 break; 249 } 250 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 251 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 252 } 253 254 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 256 /* 257 * This allocation for vmx_l1d_flush_pages is not tied to a VM 258 * lifetime and so should not be charged to a memcg. 259 */ 260 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 261 if (!page) 262 return -ENOMEM; 263 vmx_l1d_flush_pages = page_address(page); 264 265 /* 266 * Initialize each page with a different pattern in 267 * order to protect against KSM in the nested 268 * virtualization case. 269 */ 270 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 271 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 272 PAGE_SIZE); 273 } 274 } 275 276 l1tf_vmx_mitigation = l1tf; 277 278 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 279 static_branch_enable(&vmx_l1d_should_flush); 280 else 281 static_branch_disable(&vmx_l1d_should_flush); 282 283 if (l1tf == VMENTER_L1D_FLUSH_COND) 284 static_branch_enable(&vmx_l1d_flush_cond); 285 else 286 static_branch_disable(&vmx_l1d_flush_cond); 287 return 0; 288 } 289 290 static int vmentry_l1d_flush_parse(const char *s) 291 { 292 unsigned int i; 293 294 if (s) { 295 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 296 if (vmentry_l1d_param[i].for_parse && 297 sysfs_streq(s, vmentry_l1d_param[i].option)) 298 return i; 299 } 300 } 301 return -EINVAL; 302 } 303 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 305 { 306 int l1tf, ret; 307 308 l1tf = vmentry_l1d_flush_parse(s); 309 if (l1tf < 0) 310 return l1tf; 311 312 if (!boot_cpu_has(X86_BUG_L1TF)) 313 return 0; 314 315 /* 316 * Has vmx_init() run already? If not then this is the pre init 317 * parameter parsing. In that case just store the value and let 318 * vmx_init() do the proper setup after enable_ept has been 319 * established. 320 */ 321 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 322 vmentry_l1d_flush_param = l1tf; 323 return 0; 324 } 325 326 mutex_lock(&vmx_l1d_flush_mutex); 327 ret = vmx_setup_l1d_flush(l1tf); 328 mutex_unlock(&vmx_l1d_flush_mutex); 329 return ret; 330 } 331 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 333 { 334 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 335 return sprintf(s, "???\n"); 336 337 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 338 } 339 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 341 .set = vmentry_l1d_flush_set, 342 .get = vmentry_l1d_flush_get, 343 }; 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 345 346 static bool guest_state_valid(struct kvm_vcpu *vcpu); 347 static u32 vmx_segment_access_rights(struct kvm_segment *var); 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 349 u32 msr, int type); 350 351 void vmx_vmexit(void); 352 353 #define vmx_insn_failed(fmt...) \ 354 do { \ 355 WARN_ONCE(1, fmt); \ 356 pr_warn_ratelimited(fmt); \ 357 } while (0) 358 359 asmlinkage void vmread_error(unsigned long field, bool fault) 360 { 361 if (fault) 362 kvm_spurious_fault(); 363 else 364 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 365 } 366 367 noinline void vmwrite_error(unsigned long field, unsigned long value) 368 { 369 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 370 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 371 } 372 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 374 { 375 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 376 } 377 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 379 { 380 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 381 } 382 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 384 { 385 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 386 ext, vpid, gva); 387 } 388 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 390 { 391 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 392 ext, eptp, gpa); 393 } 394 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 397 /* 398 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 399 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 400 */ 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 402 403 /* 404 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 405 * can find which vCPU should be waken up. 406 */ 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 409 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 411 static DEFINE_SPINLOCK(vmx_vpid_lock); 412 413 struct vmcs_config vmcs_config; 414 struct vmx_capability vmx_capability; 415 416 #define VMX_SEGMENT_FIELD(seg) \ 417 [VCPU_SREG_##seg] = { \ 418 .selector = GUEST_##seg##_SELECTOR, \ 419 .base = GUEST_##seg##_BASE, \ 420 .limit = GUEST_##seg##_LIMIT, \ 421 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 422 } 423 424 static const struct kvm_vmx_segment_field { 425 unsigned selector; 426 unsigned base; 427 unsigned limit; 428 unsigned ar_bytes; 429 } kvm_vmx_segment_fields[] = { 430 VMX_SEGMENT_FIELD(CS), 431 VMX_SEGMENT_FIELD(DS), 432 VMX_SEGMENT_FIELD(ES), 433 VMX_SEGMENT_FIELD(FS), 434 VMX_SEGMENT_FIELD(GS), 435 VMX_SEGMENT_FIELD(SS), 436 VMX_SEGMENT_FIELD(TR), 437 VMX_SEGMENT_FIELD(LDTR), 438 }; 439 440 static unsigned long host_idt_base; 441 442 /* 443 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 444 * will emulate SYSCALL in legacy mode if the vendor string in guest 445 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 446 * support this emulation, IA32_STAR must always be included in 447 * vmx_msr_index[], even in i386 builds. 448 */ 449 const u32 vmx_msr_index[] = { 450 #ifdef CONFIG_X86_64 451 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 452 #endif 453 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 454 MSR_IA32_TSX_CTRL, 455 }; 456 457 #if IS_ENABLED(CONFIG_HYPERV) 458 static bool __read_mostly enlightened_vmcs = true; 459 module_param(enlightened_vmcs, bool, 0444); 460 461 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 462 static void check_ept_pointer_match(struct kvm *kvm) 463 { 464 struct kvm_vcpu *vcpu; 465 u64 tmp_eptp = INVALID_PAGE; 466 int i; 467 468 kvm_for_each_vcpu(i, vcpu, kvm) { 469 if (!VALID_PAGE(tmp_eptp)) { 470 tmp_eptp = to_vmx(vcpu)->ept_pointer; 471 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 472 to_kvm_vmx(kvm)->ept_pointers_match 473 = EPT_POINTERS_MISMATCH; 474 return; 475 } 476 } 477 478 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 479 } 480 481 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 482 void *data) 483 { 484 struct kvm_tlb_range *range = data; 485 486 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 487 range->pages); 488 } 489 490 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 491 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 492 { 493 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 494 495 /* 496 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 497 * of the base of EPT PML4 table, strip off EPT configuration 498 * information. 499 */ 500 if (range) 501 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 502 kvm_fill_hv_flush_list_func, (void *)range); 503 else 504 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 505 } 506 507 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 508 struct kvm_tlb_range *range) 509 { 510 struct kvm_vcpu *vcpu; 511 int ret = 0, i; 512 513 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 514 515 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 516 check_ept_pointer_match(kvm); 517 518 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 519 kvm_for_each_vcpu(i, vcpu, kvm) { 520 /* If ept_pointer is invalid pointer, bypass flush request. */ 521 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 522 ret |= __hv_remote_flush_tlb_with_range( 523 kvm, vcpu, range); 524 } 525 } else { 526 ret = __hv_remote_flush_tlb_with_range(kvm, 527 kvm_get_vcpu(kvm, 0), range); 528 } 529 530 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 531 return ret; 532 } 533 static int hv_remote_flush_tlb(struct kvm *kvm) 534 { 535 return hv_remote_flush_tlb_with_range(kvm, NULL); 536 } 537 538 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 539 { 540 struct hv_enlightened_vmcs *evmcs; 541 struct hv_partition_assist_pg **p_hv_pa_pg = 542 &vcpu->kvm->arch.hyperv.hv_pa_pg; 543 /* 544 * Synthetic VM-Exit is not enabled in current code and so All 545 * evmcs in singe VM shares same assist page. 546 */ 547 if (!*p_hv_pa_pg) 548 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 549 550 if (!*p_hv_pa_pg) 551 return -ENOMEM; 552 553 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 554 555 evmcs->partition_assist_page = 556 __pa(*p_hv_pa_pg); 557 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 558 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 559 560 return 0; 561 } 562 563 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 564 565 /* 566 * Comment's format: document - errata name - stepping - processor name. 567 * Refer from 568 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 569 */ 570 static u32 vmx_preemption_cpu_tfms[] = { 571 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 572 0x000206E6, 573 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 574 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 575 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 576 0x00020652, 577 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 578 0x00020655, 579 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 580 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 581 /* 582 * 320767.pdf - AAP86 - B1 - 583 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 584 */ 585 0x000106E5, 586 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 587 0x000106A0, 588 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 589 0x000106A1, 590 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 591 0x000106A4, 592 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 593 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 594 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 595 0x000106A5, 596 /* Xeon E3-1220 V2 */ 597 0x000306A8, 598 }; 599 600 static inline bool cpu_has_broken_vmx_preemption_timer(void) 601 { 602 u32 eax = cpuid_eax(0x00000001), i; 603 604 /* Clear the reserved bits */ 605 eax &= ~(0x3U << 14 | 0xfU << 28); 606 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 607 if (eax == vmx_preemption_cpu_tfms[i]) 608 return true; 609 610 return false; 611 } 612 613 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 614 { 615 return flexpriority_enabled && lapic_in_kernel(vcpu); 616 } 617 618 static inline bool report_flexpriority(void) 619 { 620 return flexpriority_enabled; 621 } 622 623 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 624 { 625 int i; 626 627 for (i = 0; i < vmx->nmsrs; ++i) 628 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 629 return i; 630 return -1; 631 } 632 633 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 634 { 635 int i; 636 637 i = __find_msr_index(vmx, msr); 638 if (i >= 0) 639 return &vmx->guest_msrs[i]; 640 return NULL; 641 } 642 643 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 644 { 645 int ret = 0; 646 647 u64 old_msr_data = msr->data; 648 msr->data = data; 649 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 650 preempt_disable(); 651 ret = kvm_set_shared_msr(msr->index, msr->data, 652 msr->mask); 653 preempt_enable(); 654 if (ret) 655 msr->data = old_msr_data; 656 } 657 return ret; 658 } 659 660 #ifdef CONFIG_KEXEC_CORE 661 static void crash_vmclear_local_loaded_vmcss(void) 662 { 663 int cpu = raw_smp_processor_id(); 664 struct loaded_vmcs *v; 665 666 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 667 loaded_vmcss_on_cpu_link) 668 vmcs_clear(v->vmcs); 669 } 670 #endif /* CONFIG_KEXEC_CORE */ 671 672 static void __loaded_vmcs_clear(void *arg) 673 { 674 struct loaded_vmcs *loaded_vmcs = arg; 675 int cpu = raw_smp_processor_id(); 676 677 if (loaded_vmcs->cpu != cpu) 678 return; /* vcpu migration can race with cpu offline */ 679 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 680 per_cpu(current_vmcs, cpu) = NULL; 681 682 vmcs_clear(loaded_vmcs->vmcs); 683 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 684 vmcs_clear(loaded_vmcs->shadow_vmcs); 685 686 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 687 688 /* 689 * Ensure all writes to loaded_vmcs, including deleting it from its 690 * current percpu list, complete before setting loaded_vmcs->vcpu to 691 * -1, otherwise a different cpu can see vcpu == -1 first and add 692 * loaded_vmcs to its percpu list before it's deleted from this cpu's 693 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs(). 694 */ 695 smp_wmb(); 696 697 loaded_vmcs->cpu = -1; 698 loaded_vmcs->launched = 0; 699 } 700 701 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 702 { 703 int cpu = loaded_vmcs->cpu; 704 705 if (cpu != -1) 706 smp_call_function_single(cpu, 707 __loaded_vmcs_clear, loaded_vmcs, 1); 708 } 709 710 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 711 unsigned field) 712 { 713 bool ret; 714 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 715 716 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 717 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 718 vmx->segment_cache.bitmask = 0; 719 } 720 ret = vmx->segment_cache.bitmask & mask; 721 vmx->segment_cache.bitmask |= mask; 722 return ret; 723 } 724 725 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 726 { 727 u16 *p = &vmx->segment_cache.seg[seg].selector; 728 729 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 730 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 731 return *p; 732 } 733 734 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 735 { 736 ulong *p = &vmx->segment_cache.seg[seg].base; 737 738 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 739 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 740 return *p; 741 } 742 743 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 744 { 745 u32 *p = &vmx->segment_cache.seg[seg].limit; 746 747 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 748 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 749 return *p; 750 } 751 752 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 753 { 754 u32 *p = &vmx->segment_cache.seg[seg].ar; 755 756 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 757 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 758 return *p; 759 } 760 761 void update_exception_bitmap(struct kvm_vcpu *vcpu) 762 { 763 u32 eb; 764 765 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 766 (1u << DB_VECTOR) | (1u << AC_VECTOR); 767 /* 768 * Guest access to VMware backdoor ports could legitimately 769 * trigger #GP because of TSS I/O permission bitmap. 770 * We intercept those #GP and allow access to them anyway 771 * as VMware does. 772 */ 773 if (enable_vmware_backdoor) 774 eb |= (1u << GP_VECTOR); 775 if ((vcpu->guest_debug & 776 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 777 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 778 eb |= 1u << BP_VECTOR; 779 if (to_vmx(vcpu)->rmode.vm86_active) 780 eb = ~0; 781 if (enable_ept) 782 eb &= ~(1u << PF_VECTOR); 783 784 /* When we are running a nested L2 guest and L1 specified for it a 785 * certain exception bitmap, we must trap the same exceptions and pass 786 * them to L1. When running L2, we will only handle the exceptions 787 * specified above if L1 did not want them. 788 */ 789 if (is_guest_mode(vcpu)) 790 eb |= get_vmcs12(vcpu)->exception_bitmap; 791 792 vmcs_write32(EXCEPTION_BITMAP, eb); 793 } 794 795 /* 796 * Check if MSR is intercepted for currently loaded MSR bitmap. 797 */ 798 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 799 { 800 unsigned long *msr_bitmap; 801 int f = sizeof(unsigned long); 802 803 if (!cpu_has_vmx_msr_bitmap()) 804 return true; 805 806 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 807 808 if (msr <= 0x1fff) { 809 return !!test_bit(msr, msr_bitmap + 0x800 / f); 810 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 811 msr &= 0x1fff; 812 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 813 } 814 815 return true; 816 } 817 818 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 819 unsigned long entry, unsigned long exit) 820 { 821 vm_entry_controls_clearbit(vmx, entry); 822 vm_exit_controls_clearbit(vmx, exit); 823 } 824 825 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 826 { 827 unsigned int i; 828 829 for (i = 0; i < m->nr; ++i) { 830 if (m->val[i].index == msr) 831 return i; 832 } 833 return -ENOENT; 834 } 835 836 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 837 { 838 int i; 839 struct msr_autoload *m = &vmx->msr_autoload; 840 841 switch (msr) { 842 case MSR_EFER: 843 if (cpu_has_load_ia32_efer()) { 844 clear_atomic_switch_msr_special(vmx, 845 VM_ENTRY_LOAD_IA32_EFER, 846 VM_EXIT_LOAD_IA32_EFER); 847 return; 848 } 849 break; 850 case MSR_CORE_PERF_GLOBAL_CTRL: 851 if (cpu_has_load_perf_global_ctrl()) { 852 clear_atomic_switch_msr_special(vmx, 853 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 854 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 855 return; 856 } 857 break; 858 } 859 i = vmx_find_msr_index(&m->guest, msr); 860 if (i < 0) 861 goto skip_guest; 862 --m->guest.nr; 863 m->guest.val[i] = m->guest.val[m->guest.nr]; 864 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 865 866 skip_guest: 867 i = vmx_find_msr_index(&m->host, msr); 868 if (i < 0) 869 return; 870 871 --m->host.nr; 872 m->host.val[i] = m->host.val[m->host.nr]; 873 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 874 } 875 876 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 877 unsigned long entry, unsigned long exit, 878 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 879 u64 guest_val, u64 host_val) 880 { 881 vmcs_write64(guest_val_vmcs, guest_val); 882 if (host_val_vmcs != HOST_IA32_EFER) 883 vmcs_write64(host_val_vmcs, host_val); 884 vm_entry_controls_setbit(vmx, entry); 885 vm_exit_controls_setbit(vmx, exit); 886 } 887 888 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 889 u64 guest_val, u64 host_val, bool entry_only) 890 { 891 int i, j = 0; 892 struct msr_autoload *m = &vmx->msr_autoload; 893 894 switch (msr) { 895 case MSR_EFER: 896 if (cpu_has_load_ia32_efer()) { 897 add_atomic_switch_msr_special(vmx, 898 VM_ENTRY_LOAD_IA32_EFER, 899 VM_EXIT_LOAD_IA32_EFER, 900 GUEST_IA32_EFER, 901 HOST_IA32_EFER, 902 guest_val, host_val); 903 return; 904 } 905 break; 906 case MSR_CORE_PERF_GLOBAL_CTRL: 907 if (cpu_has_load_perf_global_ctrl()) { 908 add_atomic_switch_msr_special(vmx, 909 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 910 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 911 GUEST_IA32_PERF_GLOBAL_CTRL, 912 HOST_IA32_PERF_GLOBAL_CTRL, 913 guest_val, host_val); 914 return; 915 } 916 break; 917 case MSR_IA32_PEBS_ENABLE: 918 /* PEBS needs a quiescent period after being disabled (to write 919 * a record). Disabling PEBS through VMX MSR swapping doesn't 920 * provide that period, so a CPU could write host's record into 921 * guest's memory. 922 */ 923 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 924 } 925 926 i = vmx_find_msr_index(&m->guest, msr); 927 if (!entry_only) 928 j = vmx_find_msr_index(&m->host, msr); 929 930 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 931 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 932 printk_once(KERN_WARNING "Not enough msr switch entries. " 933 "Can't add msr %x\n", msr); 934 return; 935 } 936 if (i < 0) { 937 i = m->guest.nr++; 938 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 939 } 940 m->guest.val[i].index = msr; 941 m->guest.val[i].value = guest_val; 942 943 if (entry_only) 944 return; 945 946 if (j < 0) { 947 j = m->host.nr++; 948 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 949 } 950 m->host.val[j].index = msr; 951 m->host.val[j].value = host_val; 952 } 953 954 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 955 { 956 u64 guest_efer = vmx->vcpu.arch.efer; 957 u64 ignore_bits = 0; 958 959 /* Shadow paging assumes NX to be available. */ 960 if (!enable_ept) 961 guest_efer |= EFER_NX; 962 963 /* 964 * LMA and LME handled by hardware; SCE meaningless outside long mode. 965 */ 966 ignore_bits |= EFER_SCE; 967 #ifdef CONFIG_X86_64 968 ignore_bits |= EFER_LMA | EFER_LME; 969 /* SCE is meaningful only in long mode on Intel */ 970 if (guest_efer & EFER_LMA) 971 ignore_bits &= ~(u64)EFER_SCE; 972 #endif 973 974 /* 975 * On EPT, we can't emulate NX, so we must switch EFER atomically. 976 * On CPUs that support "load IA32_EFER", always switch EFER 977 * atomically, since it's faster than switching it manually. 978 */ 979 if (cpu_has_load_ia32_efer() || 980 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 981 if (!(guest_efer & EFER_LMA)) 982 guest_efer &= ~EFER_LME; 983 if (guest_efer != host_efer) 984 add_atomic_switch_msr(vmx, MSR_EFER, 985 guest_efer, host_efer, false); 986 else 987 clear_atomic_switch_msr(vmx, MSR_EFER); 988 return false; 989 } else { 990 clear_atomic_switch_msr(vmx, MSR_EFER); 991 992 guest_efer &= ~ignore_bits; 993 guest_efer |= host_efer & ignore_bits; 994 995 vmx->guest_msrs[efer_offset].data = guest_efer; 996 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 997 998 return true; 999 } 1000 } 1001 1002 #ifdef CONFIG_X86_32 1003 /* 1004 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1005 * VMCS rather than the segment table. KVM uses this helper to figure 1006 * out the current bases to poke them into the VMCS before entry. 1007 */ 1008 static unsigned long segment_base(u16 selector) 1009 { 1010 struct desc_struct *table; 1011 unsigned long v; 1012 1013 if (!(selector & ~SEGMENT_RPL_MASK)) 1014 return 0; 1015 1016 table = get_current_gdt_ro(); 1017 1018 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1019 u16 ldt_selector = kvm_read_ldt(); 1020 1021 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1022 return 0; 1023 1024 table = (struct desc_struct *)segment_base(ldt_selector); 1025 } 1026 v = get_desc_base(&table[selector >> 3]); 1027 return v; 1028 } 1029 #endif 1030 1031 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1032 { 1033 return vmx_pt_mode_is_host_guest() && 1034 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1035 } 1036 1037 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1038 { 1039 u32 i; 1040 1041 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1042 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1043 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1044 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1045 for (i = 0; i < addr_range; i++) { 1046 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1047 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1048 } 1049 } 1050 1051 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1052 { 1053 u32 i; 1054 1055 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1056 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1057 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1058 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1059 for (i = 0; i < addr_range; i++) { 1060 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1061 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1062 } 1063 } 1064 1065 static void pt_guest_enter(struct vcpu_vmx *vmx) 1066 { 1067 if (vmx_pt_mode_is_system()) 1068 return; 1069 1070 /* 1071 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1072 * Save host state before VM entry. 1073 */ 1074 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1075 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1076 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1077 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1078 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1079 } 1080 } 1081 1082 static void pt_guest_exit(struct vcpu_vmx *vmx) 1083 { 1084 if (vmx_pt_mode_is_system()) 1085 return; 1086 1087 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1088 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1089 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1090 } 1091 1092 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1093 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1094 } 1095 1096 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1097 unsigned long fs_base, unsigned long gs_base) 1098 { 1099 if (unlikely(fs_sel != host->fs_sel)) { 1100 if (!(fs_sel & 7)) 1101 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1102 else 1103 vmcs_write16(HOST_FS_SELECTOR, 0); 1104 host->fs_sel = fs_sel; 1105 } 1106 if (unlikely(gs_sel != host->gs_sel)) { 1107 if (!(gs_sel & 7)) 1108 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1109 else 1110 vmcs_write16(HOST_GS_SELECTOR, 0); 1111 host->gs_sel = gs_sel; 1112 } 1113 if (unlikely(fs_base != host->fs_base)) { 1114 vmcs_writel(HOST_FS_BASE, fs_base); 1115 host->fs_base = fs_base; 1116 } 1117 if (unlikely(gs_base != host->gs_base)) { 1118 vmcs_writel(HOST_GS_BASE, gs_base); 1119 host->gs_base = gs_base; 1120 } 1121 } 1122 1123 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1124 { 1125 struct vcpu_vmx *vmx = to_vmx(vcpu); 1126 struct vmcs_host_state *host_state; 1127 #ifdef CONFIG_X86_64 1128 int cpu = raw_smp_processor_id(); 1129 #endif 1130 unsigned long fs_base, gs_base; 1131 u16 fs_sel, gs_sel; 1132 int i; 1133 1134 vmx->req_immediate_exit = false; 1135 1136 /* 1137 * Note that guest MSRs to be saved/restored can also be changed 1138 * when guest state is loaded. This happens when guest transitions 1139 * to/from long-mode by setting MSR_EFER.LMA. 1140 */ 1141 if (!vmx->guest_msrs_ready) { 1142 vmx->guest_msrs_ready = true; 1143 for (i = 0; i < vmx->save_nmsrs; ++i) 1144 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1145 vmx->guest_msrs[i].data, 1146 vmx->guest_msrs[i].mask); 1147 1148 } 1149 1150 if (vmx->nested.need_vmcs12_to_shadow_sync) 1151 nested_sync_vmcs12_to_shadow(vcpu); 1152 1153 if (vmx->guest_state_loaded) 1154 return; 1155 1156 host_state = &vmx->loaded_vmcs->host_state; 1157 1158 /* 1159 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1160 * allow segment selectors with cpl > 0 or ti == 1. 1161 */ 1162 host_state->ldt_sel = kvm_read_ldt(); 1163 1164 #ifdef CONFIG_X86_64 1165 savesegment(ds, host_state->ds_sel); 1166 savesegment(es, host_state->es_sel); 1167 1168 gs_base = cpu_kernelmode_gs_base(cpu); 1169 if (likely(is_64bit_mm(current->mm))) { 1170 save_fsgs_for_kvm(); 1171 fs_sel = current->thread.fsindex; 1172 gs_sel = current->thread.gsindex; 1173 fs_base = current->thread.fsbase; 1174 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1175 } else { 1176 savesegment(fs, fs_sel); 1177 savesegment(gs, gs_sel); 1178 fs_base = read_msr(MSR_FS_BASE); 1179 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1180 } 1181 1182 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1183 #else 1184 savesegment(fs, fs_sel); 1185 savesegment(gs, gs_sel); 1186 fs_base = segment_base(fs_sel); 1187 gs_base = segment_base(gs_sel); 1188 #endif 1189 1190 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1191 vmx->guest_state_loaded = true; 1192 } 1193 1194 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1195 { 1196 struct vmcs_host_state *host_state; 1197 1198 if (!vmx->guest_state_loaded) 1199 return; 1200 1201 host_state = &vmx->loaded_vmcs->host_state; 1202 1203 ++vmx->vcpu.stat.host_state_reload; 1204 1205 #ifdef CONFIG_X86_64 1206 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1207 #endif 1208 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1209 kvm_load_ldt(host_state->ldt_sel); 1210 #ifdef CONFIG_X86_64 1211 load_gs_index(host_state->gs_sel); 1212 #else 1213 loadsegment(gs, host_state->gs_sel); 1214 #endif 1215 } 1216 if (host_state->fs_sel & 7) 1217 loadsegment(fs, host_state->fs_sel); 1218 #ifdef CONFIG_X86_64 1219 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1220 loadsegment(ds, host_state->ds_sel); 1221 loadsegment(es, host_state->es_sel); 1222 } 1223 #endif 1224 invalidate_tss_limit(); 1225 #ifdef CONFIG_X86_64 1226 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1227 #endif 1228 load_fixmap_gdt(raw_smp_processor_id()); 1229 vmx->guest_state_loaded = false; 1230 vmx->guest_msrs_ready = false; 1231 } 1232 1233 #ifdef CONFIG_X86_64 1234 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1235 { 1236 preempt_disable(); 1237 if (vmx->guest_state_loaded) 1238 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1239 preempt_enable(); 1240 return vmx->msr_guest_kernel_gs_base; 1241 } 1242 1243 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1244 { 1245 preempt_disable(); 1246 if (vmx->guest_state_loaded) 1247 wrmsrl(MSR_KERNEL_GS_BASE, data); 1248 preempt_enable(); 1249 vmx->msr_guest_kernel_gs_base = data; 1250 } 1251 #endif 1252 1253 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1254 { 1255 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1256 struct pi_desc old, new; 1257 unsigned int dest; 1258 1259 /* 1260 * In case of hot-plug or hot-unplug, we may have to undo 1261 * vmx_vcpu_pi_put even if there is no assigned device. And we 1262 * always keep PI.NDST up to date for simplicity: it makes the 1263 * code easier, and CPU migration is not a fast path. 1264 */ 1265 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1266 return; 1267 1268 /* 1269 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1270 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1271 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1272 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1273 * correctly. 1274 */ 1275 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1276 pi_clear_sn(pi_desc); 1277 goto after_clear_sn; 1278 } 1279 1280 /* The full case. */ 1281 do { 1282 old.control = new.control = pi_desc->control; 1283 1284 dest = cpu_physical_id(cpu); 1285 1286 if (x2apic_enabled()) 1287 new.ndst = dest; 1288 else 1289 new.ndst = (dest << 8) & 0xFF00; 1290 1291 new.sn = 0; 1292 } while (cmpxchg64(&pi_desc->control, old.control, 1293 new.control) != old.control); 1294 1295 after_clear_sn: 1296 1297 /* 1298 * Clear SN before reading the bitmap. The VT-d firmware 1299 * writes the bitmap and reads SN atomically (5.2.3 in the 1300 * spec), so it doesn't really have a memory barrier that 1301 * pairs with this, but we cannot do that and we need one. 1302 */ 1303 smp_mb__after_atomic(); 1304 1305 if (!pi_is_pir_empty(pi_desc)) 1306 pi_set_on(pi_desc); 1307 } 1308 1309 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1310 { 1311 struct vcpu_vmx *vmx = to_vmx(vcpu); 1312 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1313 1314 if (!already_loaded) { 1315 loaded_vmcs_clear(vmx->loaded_vmcs); 1316 local_irq_disable(); 1317 1318 /* 1319 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to 1320 * this cpu's percpu list, otherwise it may not yet be deleted 1321 * from its previous cpu's percpu list. Pairs with the 1322 * smb_wmb() in __loaded_vmcs_clear(). 1323 */ 1324 smp_rmb(); 1325 1326 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1327 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1328 local_irq_enable(); 1329 } 1330 1331 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1332 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1333 vmcs_load(vmx->loaded_vmcs->vmcs); 1334 indirect_branch_prediction_barrier(); 1335 } 1336 1337 if (!already_loaded) { 1338 void *gdt = get_current_gdt_ro(); 1339 unsigned long sysenter_esp; 1340 1341 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1342 1343 /* 1344 * Linux uses per-cpu TSS and GDT, so set these when switching 1345 * processors. See 22.2.4. 1346 */ 1347 vmcs_writel(HOST_TR_BASE, 1348 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1349 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1350 1351 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1352 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1353 1354 vmx->loaded_vmcs->cpu = cpu; 1355 } 1356 1357 /* Setup TSC multiplier */ 1358 if (kvm_has_tsc_control && 1359 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1360 decache_tsc_multiplier(vmx); 1361 } 1362 1363 /* 1364 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1365 * vcpu mutex is already taken. 1366 */ 1367 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1368 { 1369 struct vcpu_vmx *vmx = to_vmx(vcpu); 1370 1371 vmx_vcpu_load_vmcs(vcpu, cpu); 1372 1373 vmx_vcpu_pi_load(vcpu, cpu); 1374 1375 vmx->host_debugctlmsr = get_debugctlmsr(); 1376 } 1377 1378 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1379 { 1380 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1381 1382 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1383 !irq_remapping_cap(IRQ_POSTING_CAP) || 1384 !kvm_vcpu_apicv_active(vcpu)) 1385 return; 1386 1387 /* Set SN when the vCPU is preempted */ 1388 if (vcpu->preempted) 1389 pi_set_sn(pi_desc); 1390 } 1391 1392 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1393 { 1394 vmx_vcpu_pi_put(vcpu); 1395 1396 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1397 } 1398 1399 static bool emulation_required(struct kvm_vcpu *vcpu) 1400 { 1401 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1402 } 1403 1404 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1405 { 1406 struct vcpu_vmx *vmx = to_vmx(vcpu); 1407 unsigned long rflags, save_rflags; 1408 1409 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1410 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1411 rflags = vmcs_readl(GUEST_RFLAGS); 1412 if (vmx->rmode.vm86_active) { 1413 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1414 save_rflags = vmx->rmode.save_rflags; 1415 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1416 } 1417 vmx->rflags = rflags; 1418 } 1419 return vmx->rflags; 1420 } 1421 1422 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1423 { 1424 struct vcpu_vmx *vmx = to_vmx(vcpu); 1425 unsigned long old_rflags; 1426 1427 if (enable_unrestricted_guest) { 1428 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1429 vmx->rflags = rflags; 1430 vmcs_writel(GUEST_RFLAGS, rflags); 1431 return; 1432 } 1433 1434 old_rflags = vmx_get_rflags(vcpu); 1435 vmx->rflags = rflags; 1436 if (vmx->rmode.vm86_active) { 1437 vmx->rmode.save_rflags = rflags; 1438 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1439 } 1440 vmcs_writel(GUEST_RFLAGS, rflags); 1441 1442 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1443 vmx->emulation_required = emulation_required(vcpu); 1444 } 1445 1446 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1447 { 1448 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1449 int ret = 0; 1450 1451 if (interruptibility & GUEST_INTR_STATE_STI) 1452 ret |= KVM_X86_SHADOW_INT_STI; 1453 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1454 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1455 1456 return ret; 1457 } 1458 1459 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1460 { 1461 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1462 u32 interruptibility = interruptibility_old; 1463 1464 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1465 1466 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1467 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1468 else if (mask & KVM_X86_SHADOW_INT_STI) 1469 interruptibility |= GUEST_INTR_STATE_STI; 1470 1471 if ((interruptibility != interruptibility_old)) 1472 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1473 } 1474 1475 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1476 { 1477 struct vcpu_vmx *vmx = to_vmx(vcpu); 1478 unsigned long value; 1479 1480 /* 1481 * Any MSR write that attempts to change bits marked reserved will 1482 * case a #GP fault. 1483 */ 1484 if (data & vmx->pt_desc.ctl_bitmask) 1485 return 1; 1486 1487 /* 1488 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1489 * result in a #GP unless the same write also clears TraceEn. 1490 */ 1491 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1492 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1493 return 1; 1494 1495 /* 1496 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1497 * and FabricEn would cause #GP, if 1498 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1499 */ 1500 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1501 !(data & RTIT_CTL_FABRIC_EN) && 1502 !intel_pt_validate_cap(vmx->pt_desc.caps, 1503 PT_CAP_single_range_output)) 1504 return 1; 1505 1506 /* 1507 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1508 * utilize encodings marked reserved will casue a #GP fault. 1509 */ 1510 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1511 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1512 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1513 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1514 return 1; 1515 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1516 PT_CAP_cycle_thresholds); 1517 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1518 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1519 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1520 return 1; 1521 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1522 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1523 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1524 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1525 return 1; 1526 1527 /* 1528 * If ADDRx_CFG is reserved or the encodings is >2 will 1529 * cause a #GP fault. 1530 */ 1531 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1532 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1533 return 1; 1534 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1535 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1536 return 1; 1537 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1538 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1539 return 1; 1540 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1541 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1542 return 1; 1543 1544 return 0; 1545 } 1546 1547 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1548 { 1549 unsigned long rip; 1550 1551 /* 1552 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1553 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1554 * set when EPT misconfig occurs. In practice, real hardware updates 1555 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1556 * (namely Hyper-V) don't set it due to it being undefined behavior, 1557 * i.e. we end up advancing IP with some random value. 1558 */ 1559 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1560 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1561 rip = kvm_rip_read(vcpu); 1562 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1563 kvm_rip_write(vcpu, rip); 1564 } else { 1565 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1566 return 0; 1567 } 1568 1569 /* skipping an emulated instruction also counts */ 1570 vmx_set_interrupt_shadow(vcpu, 0); 1571 1572 return 1; 1573 } 1574 1575 1576 /* 1577 * Recognizes a pending MTF VM-exit and records the nested state for later 1578 * delivery. 1579 */ 1580 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu) 1581 { 1582 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1583 struct vcpu_vmx *vmx = to_vmx(vcpu); 1584 1585 if (!is_guest_mode(vcpu)) 1586 return; 1587 1588 /* 1589 * Per the SDM, MTF takes priority over debug-trap exceptions besides 1590 * T-bit traps. As instruction emulation is completed (i.e. at the 1591 * instruction boundary), any #DB exception pending delivery must be a 1592 * debug-trap. Record the pending MTF state to be delivered in 1593 * vmx_check_nested_events(). 1594 */ 1595 if (nested_cpu_has_mtf(vmcs12) && 1596 (!vcpu->arch.exception.pending || 1597 vcpu->arch.exception.nr == DB_VECTOR)) 1598 vmx->nested.mtf_pending = true; 1599 else 1600 vmx->nested.mtf_pending = false; 1601 } 1602 1603 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu) 1604 { 1605 vmx_update_emulated_instruction(vcpu); 1606 return skip_emulated_instruction(vcpu); 1607 } 1608 1609 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1610 { 1611 /* 1612 * Ensure that we clear the HLT state in the VMCS. We don't need to 1613 * explicitly skip the instruction because if the HLT state is set, 1614 * then the instruction is already executing and RIP has already been 1615 * advanced. 1616 */ 1617 if (kvm_hlt_in_guest(vcpu->kvm) && 1618 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1619 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1620 } 1621 1622 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1623 { 1624 struct vcpu_vmx *vmx = to_vmx(vcpu); 1625 unsigned nr = vcpu->arch.exception.nr; 1626 bool has_error_code = vcpu->arch.exception.has_error_code; 1627 u32 error_code = vcpu->arch.exception.error_code; 1628 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1629 1630 kvm_deliver_exception_payload(vcpu); 1631 1632 if (has_error_code) { 1633 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1634 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1635 } 1636 1637 if (vmx->rmode.vm86_active) { 1638 int inc_eip = 0; 1639 if (kvm_exception_is_soft(nr)) 1640 inc_eip = vcpu->arch.event_exit_inst_len; 1641 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1642 return; 1643 } 1644 1645 WARN_ON_ONCE(vmx->emulation_required); 1646 1647 if (kvm_exception_is_soft(nr)) { 1648 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1649 vmx->vcpu.arch.event_exit_inst_len); 1650 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1651 } else 1652 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1653 1654 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1655 1656 vmx_clear_hlt(vcpu); 1657 } 1658 1659 /* 1660 * Swap MSR entry in host/guest MSR entry array. 1661 */ 1662 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1663 { 1664 struct shared_msr_entry tmp; 1665 1666 tmp = vmx->guest_msrs[to]; 1667 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1668 vmx->guest_msrs[from] = tmp; 1669 } 1670 1671 /* 1672 * Set up the vmcs to automatically save and restore system 1673 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1674 * mode, as fiddling with msrs is very expensive. 1675 */ 1676 static void setup_msrs(struct vcpu_vmx *vmx) 1677 { 1678 int save_nmsrs, index; 1679 1680 save_nmsrs = 0; 1681 #ifdef CONFIG_X86_64 1682 /* 1683 * The SYSCALL MSRs are only needed on long mode guests, and only 1684 * when EFER.SCE is set. 1685 */ 1686 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1687 index = __find_msr_index(vmx, MSR_STAR); 1688 if (index >= 0) 1689 move_msr_up(vmx, index, save_nmsrs++); 1690 index = __find_msr_index(vmx, MSR_LSTAR); 1691 if (index >= 0) 1692 move_msr_up(vmx, index, save_nmsrs++); 1693 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1694 if (index >= 0) 1695 move_msr_up(vmx, index, save_nmsrs++); 1696 } 1697 #endif 1698 index = __find_msr_index(vmx, MSR_EFER); 1699 if (index >= 0 && update_transition_efer(vmx, index)) 1700 move_msr_up(vmx, index, save_nmsrs++); 1701 index = __find_msr_index(vmx, MSR_TSC_AUX); 1702 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1703 move_msr_up(vmx, index, save_nmsrs++); 1704 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1705 if (index >= 0) 1706 move_msr_up(vmx, index, save_nmsrs++); 1707 1708 vmx->save_nmsrs = save_nmsrs; 1709 vmx->guest_msrs_ready = false; 1710 1711 if (cpu_has_vmx_msr_bitmap()) 1712 vmx_update_msr_bitmap(&vmx->vcpu); 1713 } 1714 1715 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1716 { 1717 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1718 1719 if (is_guest_mode(vcpu) && 1720 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1721 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1722 1723 return vcpu->arch.tsc_offset; 1724 } 1725 1726 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1727 { 1728 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1729 u64 g_tsc_offset = 0; 1730 1731 /* 1732 * We're here if L1 chose not to trap WRMSR to TSC. According 1733 * to the spec, this should set L1's TSC; The offset that L1 1734 * set for L2 remains unchanged, and still needs to be added 1735 * to the newly set TSC to get L2's TSC. 1736 */ 1737 if (is_guest_mode(vcpu) && 1738 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1739 g_tsc_offset = vmcs12->tsc_offset; 1740 1741 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1742 vcpu->arch.tsc_offset - g_tsc_offset, 1743 offset); 1744 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1745 return offset + g_tsc_offset; 1746 } 1747 1748 /* 1749 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1750 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1751 * all guests if the "nested" module option is off, and can also be disabled 1752 * for a single guest by disabling its VMX cpuid bit. 1753 */ 1754 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1755 { 1756 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1757 } 1758 1759 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1760 uint64_t val) 1761 { 1762 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1763 1764 return !(val & ~valid_bits); 1765 } 1766 1767 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1768 { 1769 switch (msr->index) { 1770 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1771 if (!nested) 1772 return 1; 1773 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1774 default: 1775 return 1; 1776 } 1777 } 1778 1779 /* 1780 * Reads an msr value (of 'msr_index') into 'pdata'. 1781 * Returns 0 on success, non-0 otherwise. 1782 * Assumes vcpu_load() was already called. 1783 */ 1784 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1785 { 1786 struct vcpu_vmx *vmx = to_vmx(vcpu); 1787 struct shared_msr_entry *msr; 1788 u32 index; 1789 1790 switch (msr_info->index) { 1791 #ifdef CONFIG_X86_64 1792 case MSR_FS_BASE: 1793 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1794 break; 1795 case MSR_GS_BASE: 1796 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1797 break; 1798 case MSR_KERNEL_GS_BASE: 1799 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1800 break; 1801 #endif 1802 case MSR_EFER: 1803 return kvm_get_msr_common(vcpu, msr_info); 1804 case MSR_IA32_TSX_CTRL: 1805 if (!msr_info->host_initiated && 1806 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1807 return 1; 1808 goto find_shared_msr; 1809 case MSR_IA32_UMWAIT_CONTROL: 1810 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1811 return 1; 1812 1813 msr_info->data = vmx->msr_ia32_umwait_control; 1814 break; 1815 case MSR_IA32_SPEC_CTRL: 1816 if (!msr_info->host_initiated && 1817 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1818 return 1; 1819 1820 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1821 break; 1822 case MSR_IA32_SYSENTER_CS: 1823 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1824 break; 1825 case MSR_IA32_SYSENTER_EIP: 1826 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1827 break; 1828 case MSR_IA32_SYSENTER_ESP: 1829 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1830 break; 1831 case MSR_IA32_BNDCFGS: 1832 if (!kvm_mpx_supported() || 1833 (!msr_info->host_initiated && 1834 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1835 return 1; 1836 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1837 break; 1838 case MSR_IA32_MCG_EXT_CTL: 1839 if (!msr_info->host_initiated && 1840 !(vmx->msr_ia32_feature_control & 1841 FEAT_CTL_LMCE_ENABLED)) 1842 return 1; 1843 msr_info->data = vcpu->arch.mcg_ext_ctl; 1844 break; 1845 case MSR_IA32_FEAT_CTL: 1846 msr_info->data = vmx->msr_ia32_feature_control; 1847 break; 1848 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1849 if (!nested_vmx_allowed(vcpu)) 1850 return 1; 1851 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1852 &msr_info->data)) 1853 return 1; 1854 /* 1855 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1856 * Hyper-V versions are still trying to use corresponding 1857 * features when they are exposed. Filter out the essential 1858 * minimum. 1859 */ 1860 if (!msr_info->host_initiated && 1861 vmx->nested.enlightened_vmcs_enabled) 1862 nested_evmcs_filter_control_msr(msr_info->index, 1863 &msr_info->data); 1864 break; 1865 case MSR_IA32_RTIT_CTL: 1866 if (!vmx_pt_mode_is_host_guest()) 1867 return 1; 1868 msr_info->data = vmx->pt_desc.guest.ctl; 1869 break; 1870 case MSR_IA32_RTIT_STATUS: 1871 if (!vmx_pt_mode_is_host_guest()) 1872 return 1; 1873 msr_info->data = vmx->pt_desc.guest.status; 1874 break; 1875 case MSR_IA32_RTIT_CR3_MATCH: 1876 if (!vmx_pt_mode_is_host_guest() || 1877 !intel_pt_validate_cap(vmx->pt_desc.caps, 1878 PT_CAP_cr3_filtering)) 1879 return 1; 1880 msr_info->data = vmx->pt_desc.guest.cr3_match; 1881 break; 1882 case MSR_IA32_RTIT_OUTPUT_BASE: 1883 if (!vmx_pt_mode_is_host_guest() || 1884 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1885 PT_CAP_topa_output) && 1886 !intel_pt_validate_cap(vmx->pt_desc.caps, 1887 PT_CAP_single_range_output))) 1888 return 1; 1889 msr_info->data = vmx->pt_desc.guest.output_base; 1890 break; 1891 case MSR_IA32_RTIT_OUTPUT_MASK: 1892 if (!vmx_pt_mode_is_host_guest() || 1893 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1894 PT_CAP_topa_output) && 1895 !intel_pt_validate_cap(vmx->pt_desc.caps, 1896 PT_CAP_single_range_output))) 1897 return 1; 1898 msr_info->data = vmx->pt_desc.guest.output_mask; 1899 break; 1900 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1901 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1902 if (!vmx_pt_mode_is_host_guest() || 1903 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1904 PT_CAP_num_address_ranges))) 1905 return 1; 1906 if (index % 2) 1907 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1908 else 1909 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1910 break; 1911 case MSR_TSC_AUX: 1912 if (!msr_info->host_initiated && 1913 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1914 return 1; 1915 goto find_shared_msr; 1916 default: 1917 find_shared_msr: 1918 msr = find_msr_entry(vmx, msr_info->index); 1919 if (msr) { 1920 msr_info->data = msr->data; 1921 break; 1922 } 1923 return kvm_get_msr_common(vcpu, msr_info); 1924 } 1925 1926 return 0; 1927 } 1928 1929 /* 1930 * Writes msr value into the appropriate "register". 1931 * Returns 0 on success, non-0 otherwise. 1932 * Assumes vcpu_load() was already called. 1933 */ 1934 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1935 { 1936 struct vcpu_vmx *vmx = to_vmx(vcpu); 1937 struct shared_msr_entry *msr; 1938 int ret = 0; 1939 u32 msr_index = msr_info->index; 1940 u64 data = msr_info->data; 1941 u32 index; 1942 1943 switch (msr_index) { 1944 case MSR_EFER: 1945 ret = kvm_set_msr_common(vcpu, msr_info); 1946 break; 1947 #ifdef CONFIG_X86_64 1948 case MSR_FS_BASE: 1949 vmx_segment_cache_clear(vmx); 1950 vmcs_writel(GUEST_FS_BASE, data); 1951 break; 1952 case MSR_GS_BASE: 1953 vmx_segment_cache_clear(vmx); 1954 vmcs_writel(GUEST_GS_BASE, data); 1955 break; 1956 case MSR_KERNEL_GS_BASE: 1957 vmx_write_guest_kernel_gs_base(vmx, data); 1958 break; 1959 #endif 1960 case MSR_IA32_SYSENTER_CS: 1961 if (is_guest_mode(vcpu)) 1962 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1963 vmcs_write32(GUEST_SYSENTER_CS, data); 1964 break; 1965 case MSR_IA32_SYSENTER_EIP: 1966 if (is_guest_mode(vcpu)) 1967 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1968 vmcs_writel(GUEST_SYSENTER_EIP, data); 1969 break; 1970 case MSR_IA32_SYSENTER_ESP: 1971 if (is_guest_mode(vcpu)) 1972 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1973 vmcs_writel(GUEST_SYSENTER_ESP, data); 1974 break; 1975 case MSR_IA32_DEBUGCTLMSR: 1976 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1977 VM_EXIT_SAVE_DEBUG_CONTROLS) 1978 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1979 1980 ret = kvm_set_msr_common(vcpu, msr_info); 1981 break; 1982 1983 case MSR_IA32_BNDCFGS: 1984 if (!kvm_mpx_supported() || 1985 (!msr_info->host_initiated && 1986 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1987 return 1; 1988 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1989 (data & MSR_IA32_BNDCFGS_RSVD)) 1990 return 1; 1991 vmcs_write64(GUEST_BNDCFGS, data); 1992 break; 1993 case MSR_IA32_UMWAIT_CONTROL: 1994 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1995 return 1; 1996 1997 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 1998 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 1999 return 1; 2000 2001 vmx->msr_ia32_umwait_control = data; 2002 break; 2003 case MSR_IA32_SPEC_CTRL: 2004 if (!msr_info->host_initiated && 2005 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2006 return 1; 2007 2008 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2009 return 1; 2010 2011 vmx->spec_ctrl = data; 2012 if (!data) 2013 break; 2014 2015 /* 2016 * For non-nested: 2017 * When it's written (to non-zero) for the first time, pass 2018 * it through. 2019 * 2020 * For nested: 2021 * The handling of the MSR bitmap for L2 guests is done in 2022 * nested_vmx_prepare_msr_bitmap. We should not touch the 2023 * vmcs02.msr_bitmap here since it gets completely overwritten 2024 * in the merging. We update the vmcs01 here for L1 as well 2025 * since it will end up touching the MSR anyway now. 2026 */ 2027 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2028 MSR_IA32_SPEC_CTRL, 2029 MSR_TYPE_RW); 2030 break; 2031 case MSR_IA32_TSX_CTRL: 2032 if (!msr_info->host_initiated && 2033 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2034 return 1; 2035 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2036 return 1; 2037 goto find_shared_msr; 2038 case MSR_IA32_PRED_CMD: 2039 if (!msr_info->host_initiated && 2040 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2041 return 1; 2042 2043 if (data & ~PRED_CMD_IBPB) 2044 return 1; 2045 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2046 return 1; 2047 if (!data) 2048 break; 2049 2050 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2051 2052 /* 2053 * For non-nested: 2054 * When it's written (to non-zero) for the first time, pass 2055 * it through. 2056 * 2057 * For nested: 2058 * The handling of the MSR bitmap for L2 guests is done in 2059 * nested_vmx_prepare_msr_bitmap. We should not touch the 2060 * vmcs02.msr_bitmap here since it gets completely overwritten 2061 * in the merging. 2062 */ 2063 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2064 MSR_TYPE_W); 2065 break; 2066 case MSR_IA32_CR_PAT: 2067 if (!kvm_pat_valid(data)) 2068 return 1; 2069 2070 if (is_guest_mode(vcpu) && 2071 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2072 get_vmcs12(vcpu)->guest_ia32_pat = data; 2073 2074 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2075 vmcs_write64(GUEST_IA32_PAT, data); 2076 vcpu->arch.pat = data; 2077 break; 2078 } 2079 ret = kvm_set_msr_common(vcpu, msr_info); 2080 break; 2081 case MSR_IA32_TSC_ADJUST: 2082 ret = kvm_set_msr_common(vcpu, msr_info); 2083 break; 2084 case MSR_IA32_MCG_EXT_CTL: 2085 if ((!msr_info->host_initiated && 2086 !(to_vmx(vcpu)->msr_ia32_feature_control & 2087 FEAT_CTL_LMCE_ENABLED)) || 2088 (data & ~MCG_EXT_CTL_LMCE_EN)) 2089 return 1; 2090 vcpu->arch.mcg_ext_ctl = data; 2091 break; 2092 case MSR_IA32_FEAT_CTL: 2093 if (!vmx_feature_control_msr_valid(vcpu, data) || 2094 (to_vmx(vcpu)->msr_ia32_feature_control & 2095 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2096 return 1; 2097 vmx->msr_ia32_feature_control = data; 2098 if (msr_info->host_initiated && data == 0) 2099 vmx_leave_nested(vcpu); 2100 break; 2101 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2102 if (!msr_info->host_initiated) 2103 return 1; /* they are read-only */ 2104 if (!nested_vmx_allowed(vcpu)) 2105 return 1; 2106 return vmx_set_vmx_msr(vcpu, msr_index, data); 2107 case MSR_IA32_RTIT_CTL: 2108 if (!vmx_pt_mode_is_host_guest() || 2109 vmx_rtit_ctl_check(vcpu, data) || 2110 vmx->nested.vmxon) 2111 return 1; 2112 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2113 vmx->pt_desc.guest.ctl = data; 2114 pt_update_intercept_for_msr(vmx); 2115 break; 2116 case MSR_IA32_RTIT_STATUS: 2117 if (!pt_can_write_msr(vmx)) 2118 return 1; 2119 if (data & MSR_IA32_RTIT_STATUS_MASK) 2120 return 1; 2121 vmx->pt_desc.guest.status = data; 2122 break; 2123 case MSR_IA32_RTIT_CR3_MATCH: 2124 if (!pt_can_write_msr(vmx)) 2125 return 1; 2126 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2127 PT_CAP_cr3_filtering)) 2128 return 1; 2129 vmx->pt_desc.guest.cr3_match = data; 2130 break; 2131 case MSR_IA32_RTIT_OUTPUT_BASE: 2132 if (!pt_can_write_msr(vmx)) 2133 return 1; 2134 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2135 PT_CAP_topa_output) && 2136 !intel_pt_validate_cap(vmx->pt_desc.caps, 2137 PT_CAP_single_range_output)) 2138 return 1; 2139 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2140 return 1; 2141 vmx->pt_desc.guest.output_base = data; 2142 break; 2143 case MSR_IA32_RTIT_OUTPUT_MASK: 2144 if (!pt_can_write_msr(vmx)) 2145 return 1; 2146 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2147 PT_CAP_topa_output) && 2148 !intel_pt_validate_cap(vmx->pt_desc.caps, 2149 PT_CAP_single_range_output)) 2150 return 1; 2151 vmx->pt_desc.guest.output_mask = data; 2152 break; 2153 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2154 if (!pt_can_write_msr(vmx)) 2155 return 1; 2156 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2157 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2158 PT_CAP_num_address_ranges)) 2159 return 1; 2160 if (is_noncanonical_address(data, vcpu)) 2161 return 1; 2162 if (index % 2) 2163 vmx->pt_desc.guest.addr_b[index / 2] = data; 2164 else 2165 vmx->pt_desc.guest.addr_a[index / 2] = data; 2166 break; 2167 case MSR_TSC_AUX: 2168 if (!msr_info->host_initiated && 2169 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2170 return 1; 2171 /* Check reserved bit, higher 32 bits should be zero */ 2172 if ((data >> 32) != 0) 2173 return 1; 2174 goto find_shared_msr; 2175 2176 default: 2177 find_shared_msr: 2178 msr = find_msr_entry(vmx, msr_index); 2179 if (msr) 2180 ret = vmx_set_guest_msr(vmx, msr, data); 2181 else 2182 ret = kvm_set_msr_common(vcpu, msr_info); 2183 } 2184 2185 return ret; 2186 } 2187 2188 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2189 { 2190 kvm_register_mark_available(vcpu, reg); 2191 2192 switch (reg) { 2193 case VCPU_REGS_RSP: 2194 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2195 break; 2196 case VCPU_REGS_RIP: 2197 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2198 break; 2199 case VCPU_EXREG_PDPTR: 2200 if (enable_ept) 2201 ept_save_pdptrs(vcpu); 2202 break; 2203 case VCPU_EXREG_CR3: 2204 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2205 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2206 break; 2207 default: 2208 WARN_ON_ONCE(1); 2209 break; 2210 } 2211 } 2212 2213 static __init int cpu_has_kvm_support(void) 2214 { 2215 return cpu_has_vmx(); 2216 } 2217 2218 static __init int vmx_disabled_by_bios(void) 2219 { 2220 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2221 !boot_cpu_has(X86_FEATURE_VMX); 2222 } 2223 2224 static int kvm_cpu_vmxon(u64 vmxon_pointer) 2225 { 2226 u64 msr; 2227 2228 cr4_set_bits(X86_CR4_VMXE); 2229 intel_pt_handle_vmx(1); 2230 2231 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t" 2232 _ASM_EXTABLE(1b, %l[fault]) 2233 : : [vmxon_pointer] "m"(vmxon_pointer) 2234 : : fault); 2235 return 0; 2236 2237 fault: 2238 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n", 2239 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); 2240 intel_pt_handle_vmx(0); 2241 cr4_clear_bits(X86_CR4_VMXE); 2242 2243 return -EFAULT; 2244 } 2245 2246 static int hardware_enable(void) 2247 { 2248 int cpu = raw_smp_processor_id(); 2249 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2250 int r; 2251 2252 if (cr4_read_shadow() & X86_CR4_VMXE) 2253 return -EBUSY; 2254 2255 /* 2256 * This can happen if we hot-added a CPU but failed to allocate 2257 * VP assist page for it. 2258 */ 2259 if (static_branch_unlikely(&enable_evmcs) && 2260 !hv_get_vp_assist_page(cpu)) 2261 return -EFAULT; 2262 2263 r = kvm_cpu_vmxon(phys_addr); 2264 if (r) 2265 return r; 2266 2267 if (enable_ept) 2268 ept_sync_global(); 2269 2270 return 0; 2271 } 2272 2273 static void vmclear_local_loaded_vmcss(void) 2274 { 2275 int cpu = raw_smp_processor_id(); 2276 struct loaded_vmcs *v, *n; 2277 2278 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2279 loaded_vmcss_on_cpu_link) 2280 __loaded_vmcs_clear(v); 2281 } 2282 2283 2284 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2285 * tricks. 2286 */ 2287 static void kvm_cpu_vmxoff(void) 2288 { 2289 asm volatile (__ex("vmxoff")); 2290 2291 intel_pt_handle_vmx(0); 2292 cr4_clear_bits(X86_CR4_VMXE); 2293 } 2294 2295 static void hardware_disable(void) 2296 { 2297 vmclear_local_loaded_vmcss(); 2298 kvm_cpu_vmxoff(); 2299 } 2300 2301 /* 2302 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID 2303 * directly instead of going through cpu_has(), to ensure KVM is trapping 2304 * ENCLS whenever it's supported in hardware. It does not matter whether 2305 * the host OS supports or has enabled SGX. 2306 */ 2307 static bool cpu_has_sgx(void) 2308 { 2309 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0)); 2310 } 2311 2312 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2313 u32 msr, u32 *result) 2314 { 2315 u32 vmx_msr_low, vmx_msr_high; 2316 u32 ctl = ctl_min | ctl_opt; 2317 2318 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2319 2320 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2321 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2322 2323 /* Ensure minimum (required) set of control bits are supported. */ 2324 if (ctl_min & ~ctl) 2325 return -EIO; 2326 2327 *result = ctl; 2328 return 0; 2329 } 2330 2331 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2332 struct vmx_capability *vmx_cap) 2333 { 2334 u32 vmx_msr_low, vmx_msr_high; 2335 u32 min, opt, min2, opt2; 2336 u32 _pin_based_exec_control = 0; 2337 u32 _cpu_based_exec_control = 0; 2338 u32 _cpu_based_2nd_exec_control = 0; 2339 u32 _vmexit_control = 0; 2340 u32 _vmentry_control = 0; 2341 2342 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2343 min = CPU_BASED_HLT_EXITING | 2344 #ifdef CONFIG_X86_64 2345 CPU_BASED_CR8_LOAD_EXITING | 2346 CPU_BASED_CR8_STORE_EXITING | 2347 #endif 2348 CPU_BASED_CR3_LOAD_EXITING | 2349 CPU_BASED_CR3_STORE_EXITING | 2350 CPU_BASED_UNCOND_IO_EXITING | 2351 CPU_BASED_MOV_DR_EXITING | 2352 CPU_BASED_USE_TSC_OFFSETTING | 2353 CPU_BASED_MWAIT_EXITING | 2354 CPU_BASED_MONITOR_EXITING | 2355 CPU_BASED_INVLPG_EXITING | 2356 CPU_BASED_RDPMC_EXITING; 2357 2358 opt = CPU_BASED_TPR_SHADOW | 2359 CPU_BASED_USE_MSR_BITMAPS | 2360 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2361 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2362 &_cpu_based_exec_control) < 0) 2363 return -EIO; 2364 #ifdef CONFIG_X86_64 2365 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2366 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2367 ~CPU_BASED_CR8_STORE_EXITING; 2368 #endif 2369 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2370 min2 = 0; 2371 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2372 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2373 SECONDARY_EXEC_WBINVD_EXITING | 2374 SECONDARY_EXEC_ENABLE_VPID | 2375 SECONDARY_EXEC_ENABLE_EPT | 2376 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2377 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2378 SECONDARY_EXEC_DESC | 2379 SECONDARY_EXEC_RDTSCP | 2380 SECONDARY_EXEC_ENABLE_INVPCID | 2381 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2382 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2383 SECONDARY_EXEC_SHADOW_VMCS | 2384 SECONDARY_EXEC_XSAVES | 2385 SECONDARY_EXEC_RDSEED_EXITING | 2386 SECONDARY_EXEC_RDRAND_EXITING | 2387 SECONDARY_EXEC_ENABLE_PML | 2388 SECONDARY_EXEC_TSC_SCALING | 2389 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2390 SECONDARY_EXEC_PT_USE_GPA | 2391 SECONDARY_EXEC_PT_CONCEAL_VMX | 2392 SECONDARY_EXEC_ENABLE_VMFUNC; 2393 if (cpu_has_sgx()) 2394 opt2 |= SECONDARY_EXEC_ENCLS_EXITING; 2395 if (adjust_vmx_controls(min2, opt2, 2396 MSR_IA32_VMX_PROCBASED_CTLS2, 2397 &_cpu_based_2nd_exec_control) < 0) 2398 return -EIO; 2399 } 2400 #ifndef CONFIG_X86_64 2401 if (!(_cpu_based_2nd_exec_control & 2402 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2403 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2404 #endif 2405 2406 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2407 _cpu_based_2nd_exec_control &= ~( 2408 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2409 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2410 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2411 2412 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2413 &vmx_cap->ept, &vmx_cap->vpid); 2414 2415 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2416 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2417 enabled */ 2418 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2419 CPU_BASED_CR3_STORE_EXITING | 2420 CPU_BASED_INVLPG_EXITING); 2421 } else if (vmx_cap->ept) { 2422 vmx_cap->ept = 0; 2423 pr_warn_once("EPT CAP should not exist if not support " 2424 "1-setting enable EPT VM-execution control\n"); 2425 } 2426 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2427 vmx_cap->vpid) { 2428 vmx_cap->vpid = 0; 2429 pr_warn_once("VPID CAP should not exist if not support " 2430 "1-setting enable VPID VM-execution control\n"); 2431 } 2432 2433 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2434 #ifdef CONFIG_X86_64 2435 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2436 #endif 2437 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2438 VM_EXIT_LOAD_IA32_PAT | 2439 VM_EXIT_LOAD_IA32_EFER | 2440 VM_EXIT_CLEAR_BNDCFGS | 2441 VM_EXIT_PT_CONCEAL_PIP | 2442 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2443 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2444 &_vmexit_control) < 0) 2445 return -EIO; 2446 2447 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2448 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2449 PIN_BASED_VMX_PREEMPTION_TIMER; 2450 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2451 &_pin_based_exec_control) < 0) 2452 return -EIO; 2453 2454 if (cpu_has_broken_vmx_preemption_timer()) 2455 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2456 if (!(_cpu_based_2nd_exec_control & 2457 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2458 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2459 2460 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2461 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2462 VM_ENTRY_LOAD_IA32_PAT | 2463 VM_ENTRY_LOAD_IA32_EFER | 2464 VM_ENTRY_LOAD_BNDCFGS | 2465 VM_ENTRY_PT_CONCEAL_PIP | 2466 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2467 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2468 &_vmentry_control) < 0) 2469 return -EIO; 2470 2471 /* 2472 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2473 * can't be used due to an errata where VM Exit may incorrectly clear 2474 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2475 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2476 */ 2477 if (boot_cpu_data.x86 == 0x6) { 2478 switch (boot_cpu_data.x86_model) { 2479 case 26: /* AAK155 */ 2480 case 30: /* AAP115 */ 2481 case 37: /* AAT100 */ 2482 case 44: /* BC86,AAY89,BD102 */ 2483 case 46: /* BA97 */ 2484 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2485 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2486 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2487 "does not work properly. Using workaround\n"); 2488 break; 2489 default: 2490 break; 2491 } 2492 } 2493 2494 2495 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2496 2497 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2498 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2499 return -EIO; 2500 2501 #ifdef CONFIG_X86_64 2502 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2503 if (vmx_msr_high & (1u<<16)) 2504 return -EIO; 2505 #endif 2506 2507 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2508 if (((vmx_msr_high >> 18) & 15) != 6) 2509 return -EIO; 2510 2511 vmcs_conf->size = vmx_msr_high & 0x1fff; 2512 vmcs_conf->order = get_order(vmcs_conf->size); 2513 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2514 2515 vmcs_conf->revision_id = vmx_msr_low; 2516 2517 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2518 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2519 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2520 vmcs_conf->vmexit_ctrl = _vmexit_control; 2521 vmcs_conf->vmentry_ctrl = _vmentry_control; 2522 2523 if (static_branch_unlikely(&enable_evmcs)) 2524 evmcs_sanitize_exec_ctrls(vmcs_conf); 2525 2526 return 0; 2527 } 2528 2529 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2530 { 2531 int node = cpu_to_node(cpu); 2532 struct page *pages; 2533 struct vmcs *vmcs; 2534 2535 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2536 if (!pages) 2537 return NULL; 2538 vmcs = page_address(pages); 2539 memset(vmcs, 0, vmcs_config.size); 2540 2541 /* KVM supports Enlightened VMCS v1 only */ 2542 if (static_branch_unlikely(&enable_evmcs)) 2543 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2544 else 2545 vmcs->hdr.revision_id = vmcs_config.revision_id; 2546 2547 if (shadow) 2548 vmcs->hdr.shadow_vmcs = 1; 2549 return vmcs; 2550 } 2551 2552 void free_vmcs(struct vmcs *vmcs) 2553 { 2554 free_pages((unsigned long)vmcs, vmcs_config.order); 2555 } 2556 2557 /* 2558 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2559 */ 2560 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2561 { 2562 if (!loaded_vmcs->vmcs) 2563 return; 2564 loaded_vmcs_clear(loaded_vmcs); 2565 free_vmcs(loaded_vmcs->vmcs); 2566 loaded_vmcs->vmcs = NULL; 2567 if (loaded_vmcs->msr_bitmap) 2568 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2569 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2570 } 2571 2572 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2573 { 2574 loaded_vmcs->vmcs = alloc_vmcs(false); 2575 if (!loaded_vmcs->vmcs) 2576 return -ENOMEM; 2577 2578 vmcs_clear(loaded_vmcs->vmcs); 2579 2580 loaded_vmcs->shadow_vmcs = NULL; 2581 loaded_vmcs->hv_timer_soft_disabled = false; 2582 loaded_vmcs->cpu = -1; 2583 loaded_vmcs->launched = 0; 2584 2585 if (cpu_has_vmx_msr_bitmap()) { 2586 loaded_vmcs->msr_bitmap = (unsigned long *) 2587 __get_free_page(GFP_KERNEL_ACCOUNT); 2588 if (!loaded_vmcs->msr_bitmap) 2589 goto out_vmcs; 2590 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2591 2592 if (IS_ENABLED(CONFIG_HYPERV) && 2593 static_branch_unlikely(&enable_evmcs) && 2594 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2595 struct hv_enlightened_vmcs *evmcs = 2596 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2597 2598 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2599 } 2600 } 2601 2602 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2603 memset(&loaded_vmcs->controls_shadow, 0, 2604 sizeof(struct vmcs_controls_shadow)); 2605 2606 return 0; 2607 2608 out_vmcs: 2609 free_loaded_vmcs(loaded_vmcs); 2610 return -ENOMEM; 2611 } 2612 2613 static void free_kvm_area(void) 2614 { 2615 int cpu; 2616 2617 for_each_possible_cpu(cpu) { 2618 free_vmcs(per_cpu(vmxarea, cpu)); 2619 per_cpu(vmxarea, cpu) = NULL; 2620 } 2621 } 2622 2623 static __init int alloc_kvm_area(void) 2624 { 2625 int cpu; 2626 2627 for_each_possible_cpu(cpu) { 2628 struct vmcs *vmcs; 2629 2630 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2631 if (!vmcs) { 2632 free_kvm_area(); 2633 return -ENOMEM; 2634 } 2635 2636 /* 2637 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2638 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2639 * revision_id reported by MSR_IA32_VMX_BASIC. 2640 * 2641 * However, even though not explicitly documented by 2642 * TLFS, VMXArea passed as VMXON argument should 2643 * still be marked with revision_id reported by 2644 * physical CPU. 2645 */ 2646 if (static_branch_unlikely(&enable_evmcs)) 2647 vmcs->hdr.revision_id = vmcs_config.revision_id; 2648 2649 per_cpu(vmxarea, cpu) = vmcs; 2650 } 2651 return 0; 2652 } 2653 2654 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2655 struct kvm_segment *save) 2656 { 2657 if (!emulate_invalid_guest_state) { 2658 /* 2659 * CS and SS RPL should be equal during guest entry according 2660 * to VMX spec, but in reality it is not always so. Since vcpu 2661 * is in the middle of the transition from real mode to 2662 * protected mode it is safe to assume that RPL 0 is a good 2663 * default value. 2664 */ 2665 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2666 save->selector &= ~SEGMENT_RPL_MASK; 2667 save->dpl = save->selector & SEGMENT_RPL_MASK; 2668 save->s = 1; 2669 } 2670 vmx_set_segment(vcpu, save, seg); 2671 } 2672 2673 static void enter_pmode(struct kvm_vcpu *vcpu) 2674 { 2675 unsigned long flags; 2676 struct vcpu_vmx *vmx = to_vmx(vcpu); 2677 2678 /* 2679 * Update real mode segment cache. It may be not up-to-date if sement 2680 * register was written while vcpu was in a guest mode. 2681 */ 2682 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2683 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2684 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2685 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2686 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2687 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2688 2689 vmx->rmode.vm86_active = 0; 2690 2691 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2692 2693 flags = vmcs_readl(GUEST_RFLAGS); 2694 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2695 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2696 vmcs_writel(GUEST_RFLAGS, flags); 2697 2698 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2699 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2700 2701 update_exception_bitmap(vcpu); 2702 2703 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2704 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2705 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2706 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2707 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2708 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2709 } 2710 2711 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2712 { 2713 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2714 struct kvm_segment var = *save; 2715 2716 var.dpl = 0x3; 2717 if (seg == VCPU_SREG_CS) 2718 var.type = 0x3; 2719 2720 if (!emulate_invalid_guest_state) { 2721 var.selector = var.base >> 4; 2722 var.base = var.base & 0xffff0; 2723 var.limit = 0xffff; 2724 var.g = 0; 2725 var.db = 0; 2726 var.present = 1; 2727 var.s = 1; 2728 var.l = 0; 2729 var.unusable = 0; 2730 var.type = 0x3; 2731 var.avl = 0; 2732 if (save->base & 0xf) 2733 printk_once(KERN_WARNING "kvm: segment base is not " 2734 "paragraph aligned when entering " 2735 "protected mode (seg=%d)", seg); 2736 } 2737 2738 vmcs_write16(sf->selector, var.selector); 2739 vmcs_writel(sf->base, var.base); 2740 vmcs_write32(sf->limit, var.limit); 2741 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2742 } 2743 2744 static void enter_rmode(struct kvm_vcpu *vcpu) 2745 { 2746 unsigned long flags; 2747 struct vcpu_vmx *vmx = to_vmx(vcpu); 2748 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2749 2750 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2751 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2752 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2753 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2754 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2757 2758 vmx->rmode.vm86_active = 1; 2759 2760 /* 2761 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2762 * vcpu. Warn the user that an update is overdue. 2763 */ 2764 if (!kvm_vmx->tss_addr) 2765 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2766 "called before entering vcpu\n"); 2767 2768 vmx_segment_cache_clear(vmx); 2769 2770 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2771 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2772 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2773 2774 flags = vmcs_readl(GUEST_RFLAGS); 2775 vmx->rmode.save_rflags = flags; 2776 2777 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2778 2779 vmcs_writel(GUEST_RFLAGS, flags); 2780 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2781 update_exception_bitmap(vcpu); 2782 2783 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2784 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2785 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2786 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2787 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2788 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2789 2790 kvm_mmu_reset_context(vcpu); 2791 } 2792 2793 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2794 { 2795 struct vcpu_vmx *vmx = to_vmx(vcpu); 2796 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2797 2798 if (!msr) 2799 return; 2800 2801 vcpu->arch.efer = efer; 2802 if (efer & EFER_LMA) { 2803 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2804 msr->data = efer; 2805 } else { 2806 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2807 2808 msr->data = efer & ~EFER_LME; 2809 } 2810 setup_msrs(vmx); 2811 } 2812 2813 #ifdef CONFIG_X86_64 2814 2815 static void enter_lmode(struct kvm_vcpu *vcpu) 2816 { 2817 u32 guest_tr_ar; 2818 2819 vmx_segment_cache_clear(to_vmx(vcpu)); 2820 2821 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2822 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2823 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2824 __func__); 2825 vmcs_write32(GUEST_TR_AR_BYTES, 2826 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2827 | VMX_AR_TYPE_BUSY_64_TSS); 2828 } 2829 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2830 } 2831 2832 static void exit_lmode(struct kvm_vcpu *vcpu) 2833 { 2834 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2835 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2836 } 2837 2838 #endif 2839 2840 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2841 { 2842 int vpid = to_vmx(vcpu)->vpid; 2843 2844 if (!vpid_sync_vcpu_addr(vpid, addr)) 2845 vpid_sync_context(vpid); 2846 2847 /* 2848 * If VPIDs are not supported or enabled, then the above is a no-op. 2849 * But we don't really need a TLB flush in that case anyway, because 2850 * each VM entry/exit includes an implicit flush when VPID is 0. 2851 */ 2852 } 2853 2854 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2855 { 2856 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2857 2858 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2859 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2860 } 2861 2862 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2863 { 2864 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2865 2866 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2867 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2868 } 2869 2870 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2871 { 2872 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2873 2874 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2875 return; 2876 2877 if (is_pae_paging(vcpu)) { 2878 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2879 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2880 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2881 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2882 } 2883 } 2884 2885 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2886 { 2887 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2888 2889 if (is_pae_paging(vcpu)) { 2890 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2891 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2892 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2893 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2894 } 2895 2896 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2897 } 2898 2899 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2900 unsigned long cr0, 2901 struct kvm_vcpu *vcpu) 2902 { 2903 struct vcpu_vmx *vmx = to_vmx(vcpu); 2904 2905 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2906 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2907 if (!(cr0 & X86_CR0_PG)) { 2908 /* From paging/starting to nonpaging */ 2909 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2910 CPU_BASED_CR3_STORE_EXITING); 2911 vcpu->arch.cr0 = cr0; 2912 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2913 } else if (!is_paging(vcpu)) { 2914 /* From nonpaging to paging */ 2915 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2916 CPU_BASED_CR3_STORE_EXITING); 2917 vcpu->arch.cr0 = cr0; 2918 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2919 } 2920 2921 if (!(cr0 & X86_CR0_WP)) 2922 *hw_cr0 &= ~X86_CR0_WP; 2923 } 2924 2925 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2926 { 2927 struct vcpu_vmx *vmx = to_vmx(vcpu); 2928 unsigned long hw_cr0; 2929 2930 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2931 if (enable_unrestricted_guest) 2932 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2933 else { 2934 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2935 2936 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2937 enter_pmode(vcpu); 2938 2939 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2940 enter_rmode(vcpu); 2941 } 2942 2943 #ifdef CONFIG_X86_64 2944 if (vcpu->arch.efer & EFER_LME) { 2945 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2946 enter_lmode(vcpu); 2947 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2948 exit_lmode(vcpu); 2949 } 2950 #endif 2951 2952 if (enable_ept && !enable_unrestricted_guest) 2953 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2954 2955 vmcs_writel(CR0_READ_SHADOW, cr0); 2956 vmcs_writel(GUEST_CR0, hw_cr0); 2957 vcpu->arch.cr0 = cr0; 2958 2959 /* depends on vcpu->arch.cr0 to be set to a new value */ 2960 vmx->emulation_required = emulation_required(vcpu); 2961 } 2962 2963 static int get_ept_level(struct kvm_vcpu *vcpu) 2964 { 2965 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu))) 2966 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu)); 2967 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2968 return 5; 2969 return 4; 2970 } 2971 2972 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2973 { 2974 u64 eptp = VMX_EPTP_MT_WB; 2975 2976 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2977 2978 if (enable_ept_ad_bits && 2979 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2980 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2981 eptp |= (root_hpa & PAGE_MASK); 2982 2983 return eptp; 2984 } 2985 2986 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long cr3) 2987 { 2988 struct kvm *kvm = vcpu->kvm; 2989 bool update_guest_cr3 = true; 2990 unsigned long guest_cr3; 2991 u64 eptp; 2992 2993 guest_cr3 = cr3; 2994 if (enable_ept) { 2995 eptp = construct_eptp(vcpu, cr3); 2996 vmcs_write64(EPT_POINTER, eptp); 2997 2998 if (kvm_x86_ops.tlb_remote_flush) { 2999 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3000 to_vmx(vcpu)->ept_pointer = eptp; 3001 to_kvm_vmx(kvm)->ept_pointers_match 3002 = EPT_POINTERS_CHECK; 3003 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3004 } 3005 3006 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 3007 if (is_guest_mode(vcpu)) 3008 update_guest_cr3 = false; 3009 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 3010 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3011 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 3012 guest_cr3 = vcpu->arch.cr3; 3013 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3014 update_guest_cr3 = false; 3015 ept_load_pdptrs(vcpu); 3016 } 3017 3018 if (update_guest_cr3) 3019 vmcs_writel(GUEST_CR3, guest_cr3); 3020 } 3021 3022 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3023 { 3024 struct vcpu_vmx *vmx = to_vmx(vcpu); 3025 /* 3026 * Pass through host's Machine Check Enable value to hw_cr4, which 3027 * is in force while we are in guest mode. Do not let guests control 3028 * this bit, even if host CR4.MCE == 0. 3029 */ 3030 unsigned long hw_cr4; 3031 3032 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3033 if (enable_unrestricted_guest) 3034 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3035 else if (vmx->rmode.vm86_active) 3036 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3037 else 3038 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3039 3040 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3041 if (cr4 & X86_CR4_UMIP) { 3042 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3043 hw_cr4 &= ~X86_CR4_UMIP; 3044 } else if (!is_guest_mode(vcpu) || 3045 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3046 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3047 } 3048 } 3049 3050 if (cr4 & X86_CR4_VMXE) { 3051 /* 3052 * To use VMXON (and later other VMX instructions), a guest 3053 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3054 * So basically the check on whether to allow nested VMX 3055 * is here. We operate under the default treatment of SMM, 3056 * so VMX cannot be enabled under SMM. 3057 */ 3058 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3059 return 1; 3060 } 3061 3062 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3063 return 1; 3064 3065 vcpu->arch.cr4 = cr4; 3066 3067 if (!enable_unrestricted_guest) { 3068 if (enable_ept) { 3069 if (!is_paging(vcpu)) { 3070 hw_cr4 &= ~X86_CR4_PAE; 3071 hw_cr4 |= X86_CR4_PSE; 3072 } else if (!(cr4 & X86_CR4_PAE)) { 3073 hw_cr4 &= ~X86_CR4_PAE; 3074 } 3075 } 3076 3077 /* 3078 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3079 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3080 * to be manually disabled when guest switches to non-paging 3081 * mode. 3082 * 3083 * If !enable_unrestricted_guest, the CPU is always running 3084 * with CR0.PG=1 and CR4 needs to be modified. 3085 * If enable_unrestricted_guest, the CPU automatically 3086 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3087 */ 3088 if (!is_paging(vcpu)) 3089 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3090 } 3091 3092 vmcs_writel(CR4_READ_SHADOW, cr4); 3093 vmcs_writel(GUEST_CR4, hw_cr4); 3094 return 0; 3095 } 3096 3097 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3098 { 3099 struct vcpu_vmx *vmx = to_vmx(vcpu); 3100 u32 ar; 3101 3102 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3103 *var = vmx->rmode.segs[seg]; 3104 if (seg == VCPU_SREG_TR 3105 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3106 return; 3107 var->base = vmx_read_guest_seg_base(vmx, seg); 3108 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3109 return; 3110 } 3111 var->base = vmx_read_guest_seg_base(vmx, seg); 3112 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3113 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3114 ar = vmx_read_guest_seg_ar(vmx, seg); 3115 var->unusable = (ar >> 16) & 1; 3116 var->type = ar & 15; 3117 var->s = (ar >> 4) & 1; 3118 var->dpl = (ar >> 5) & 3; 3119 /* 3120 * Some userspaces do not preserve unusable property. Since usable 3121 * segment has to be present according to VMX spec we can use present 3122 * property to amend userspace bug by making unusable segment always 3123 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3124 * segment as unusable. 3125 */ 3126 var->present = !var->unusable; 3127 var->avl = (ar >> 12) & 1; 3128 var->l = (ar >> 13) & 1; 3129 var->db = (ar >> 14) & 1; 3130 var->g = (ar >> 15) & 1; 3131 } 3132 3133 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3134 { 3135 struct kvm_segment s; 3136 3137 if (to_vmx(vcpu)->rmode.vm86_active) { 3138 vmx_get_segment(vcpu, &s, seg); 3139 return s.base; 3140 } 3141 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3142 } 3143 3144 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3145 { 3146 struct vcpu_vmx *vmx = to_vmx(vcpu); 3147 3148 if (unlikely(vmx->rmode.vm86_active)) 3149 return 0; 3150 else { 3151 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3152 return VMX_AR_DPL(ar); 3153 } 3154 } 3155 3156 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3157 { 3158 u32 ar; 3159 3160 if (var->unusable || !var->present) 3161 ar = 1 << 16; 3162 else { 3163 ar = var->type & 15; 3164 ar |= (var->s & 1) << 4; 3165 ar |= (var->dpl & 3) << 5; 3166 ar |= (var->present & 1) << 7; 3167 ar |= (var->avl & 1) << 12; 3168 ar |= (var->l & 1) << 13; 3169 ar |= (var->db & 1) << 14; 3170 ar |= (var->g & 1) << 15; 3171 } 3172 3173 return ar; 3174 } 3175 3176 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3177 { 3178 struct vcpu_vmx *vmx = to_vmx(vcpu); 3179 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3180 3181 vmx_segment_cache_clear(vmx); 3182 3183 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3184 vmx->rmode.segs[seg] = *var; 3185 if (seg == VCPU_SREG_TR) 3186 vmcs_write16(sf->selector, var->selector); 3187 else if (var->s) 3188 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3189 goto out; 3190 } 3191 3192 vmcs_writel(sf->base, var->base); 3193 vmcs_write32(sf->limit, var->limit); 3194 vmcs_write16(sf->selector, var->selector); 3195 3196 /* 3197 * Fix the "Accessed" bit in AR field of segment registers for older 3198 * qemu binaries. 3199 * IA32 arch specifies that at the time of processor reset the 3200 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3201 * is setting it to 0 in the userland code. This causes invalid guest 3202 * state vmexit when "unrestricted guest" mode is turned on. 3203 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3204 * tree. Newer qemu binaries with that qemu fix would not need this 3205 * kvm hack. 3206 */ 3207 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3208 var->type |= 0x1; /* Accessed */ 3209 3210 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3211 3212 out: 3213 vmx->emulation_required = emulation_required(vcpu); 3214 } 3215 3216 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3217 { 3218 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3219 3220 *db = (ar >> 14) & 1; 3221 *l = (ar >> 13) & 1; 3222 } 3223 3224 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3225 { 3226 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3227 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3228 } 3229 3230 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3231 { 3232 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3233 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3234 } 3235 3236 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3237 { 3238 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3239 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3240 } 3241 3242 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3243 { 3244 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3245 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3246 } 3247 3248 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3249 { 3250 struct kvm_segment var; 3251 u32 ar; 3252 3253 vmx_get_segment(vcpu, &var, seg); 3254 var.dpl = 0x3; 3255 if (seg == VCPU_SREG_CS) 3256 var.type = 0x3; 3257 ar = vmx_segment_access_rights(&var); 3258 3259 if (var.base != (var.selector << 4)) 3260 return false; 3261 if (var.limit != 0xffff) 3262 return false; 3263 if (ar != 0xf3) 3264 return false; 3265 3266 return true; 3267 } 3268 3269 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3270 { 3271 struct kvm_segment cs; 3272 unsigned int cs_rpl; 3273 3274 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3275 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3276 3277 if (cs.unusable) 3278 return false; 3279 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3280 return false; 3281 if (!cs.s) 3282 return false; 3283 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3284 if (cs.dpl > cs_rpl) 3285 return false; 3286 } else { 3287 if (cs.dpl != cs_rpl) 3288 return false; 3289 } 3290 if (!cs.present) 3291 return false; 3292 3293 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3294 return true; 3295 } 3296 3297 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3298 { 3299 struct kvm_segment ss; 3300 unsigned int ss_rpl; 3301 3302 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3303 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3304 3305 if (ss.unusable) 3306 return true; 3307 if (ss.type != 3 && ss.type != 7) 3308 return false; 3309 if (!ss.s) 3310 return false; 3311 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3312 return false; 3313 if (!ss.present) 3314 return false; 3315 3316 return true; 3317 } 3318 3319 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3320 { 3321 struct kvm_segment var; 3322 unsigned int rpl; 3323 3324 vmx_get_segment(vcpu, &var, seg); 3325 rpl = var.selector & SEGMENT_RPL_MASK; 3326 3327 if (var.unusable) 3328 return true; 3329 if (!var.s) 3330 return false; 3331 if (!var.present) 3332 return false; 3333 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3334 if (var.dpl < rpl) /* DPL < RPL */ 3335 return false; 3336 } 3337 3338 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3339 * rights flags 3340 */ 3341 return true; 3342 } 3343 3344 static bool tr_valid(struct kvm_vcpu *vcpu) 3345 { 3346 struct kvm_segment tr; 3347 3348 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3349 3350 if (tr.unusable) 3351 return false; 3352 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3353 return false; 3354 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3355 return false; 3356 if (!tr.present) 3357 return false; 3358 3359 return true; 3360 } 3361 3362 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3363 { 3364 struct kvm_segment ldtr; 3365 3366 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3367 3368 if (ldtr.unusable) 3369 return true; 3370 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3371 return false; 3372 if (ldtr.type != 2) 3373 return false; 3374 if (!ldtr.present) 3375 return false; 3376 3377 return true; 3378 } 3379 3380 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3381 { 3382 struct kvm_segment cs, ss; 3383 3384 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3385 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3386 3387 return ((cs.selector & SEGMENT_RPL_MASK) == 3388 (ss.selector & SEGMENT_RPL_MASK)); 3389 } 3390 3391 /* 3392 * Check if guest state is valid. Returns true if valid, false if 3393 * not. 3394 * We assume that registers are always usable 3395 */ 3396 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3397 { 3398 if (enable_unrestricted_guest) 3399 return true; 3400 3401 /* real mode guest state checks */ 3402 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3403 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3404 return false; 3405 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3406 return false; 3407 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3408 return false; 3409 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3410 return false; 3411 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3412 return false; 3413 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3414 return false; 3415 } else { 3416 /* protected mode guest state checks */ 3417 if (!cs_ss_rpl_check(vcpu)) 3418 return false; 3419 if (!code_segment_valid(vcpu)) 3420 return false; 3421 if (!stack_segment_valid(vcpu)) 3422 return false; 3423 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3424 return false; 3425 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3426 return false; 3427 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3428 return false; 3429 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3430 return false; 3431 if (!tr_valid(vcpu)) 3432 return false; 3433 if (!ldtr_valid(vcpu)) 3434 return false; 3435 } 3436 /* TODO: 3437 * - Add checks on RIP 3438 * - Add checks on RFLAGS 3439 */ 3440 3441 return true; 3442 } 3443 3444 static int init_rmode_tss(struct kvm *kvm) 3445 { 3446 gfn_t fn; 3447 u16 data = 0; 3448 int idx, r; 3449 3450 idx = srcu_read_lock(&kvm->srcu); 3451 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3452 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3453 if (r < 0) 3454 goto out; 3455 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3456 r = kvm_write_guest_page(kvm, fn++, &data, 3457 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3458 if (r < 0) 3459 goto out; 3460 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3461 if (r < 0) 3462 goto out; 3463 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3464 if (r < 0) 3465 goto out; 3466 data = ~0; 3467 r = kvm_write_guest_page(kvm, fn, &data, 3468 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3469 sizeof(u8)); 3470 out: 3471 srcu_read_unlock(&kvm->srcu, idx); 3472 return r; 3473 } 3474 3475 static int init_rmode_identity_map(struct kvm *kvm) 3476 { 3477 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3478 int i, r = 0; 3479 kvm_pfn_t identity_map_pfn; 3480 u32 tmp; 3481 3482 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3483 mutex_lock(&kvm->slots_lock); 3484 3485 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3486 goto out; 3487 3488 if (!kvm_vmx->ept_identity_map_addr) 3489 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3490 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3491 3492 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3493 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3494 if (r < 0) 3495 goto out; 3496 3497 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3498 if (r < 0) 3499 goto out; 3500 /* Set up identity-mapping pagetable for EPT in real mode */ 3501 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3502 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3503 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3504 r = kvm_write_guest_page(kvm, identity_map_pfn, 3505 &tmp, i * sizeof(tmp), sizeof(tmp)); 3506 if (r < 0) 3507 goto out; 3508 } 3509 kvm_vmx->ept_identity_pagetable_done = true; 3510 3511 out: 3512 mutex_unlock(&kvm->slots_lock); 3513 return r; 3514 } 3515 3516 static void seg_setup(int seg) 3517 { 3518 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3519 unsigned int ar; 3520 3521 vmcs_write16(sf->selector, 0); 3522 vmcs_writel(sf->base, 0); 3523 vmcs_write32(sf->limit, 0xffff); 3524 ar = 0x93; 3525 if (seg == VCPU_SREG_CS) 3526 ar |= 0x08; /* code segment */ 3527 3528 vmcs_write32(sf->ar_bytes, ar); 3529 } 3530 3531 static int alloc_apic_access_page(struct kvm *kvm) 3532 { 3533 struct page *page; 3534 int r = 0; 3535 3536 mutex_lock(&kvm->slots_lock); 3537 if (kvm->arch.apic_access_page_done) 3538 goto out; 3539 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3540 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3541 if (r) 3542 goto out; 3543 3544 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3545 if (is_error_page(page)) { 3546 r = -EFAULT; 3547 goto out; 3548 } 3549 3550 /* 3551 * Do not pin the page in memory, so that memory hot-unplug 3552 * is able to migrate it. 3553 */ 3554 put_page(page); 3555 kvm->arch.apic_access_page_done = true; 3556 out: 3557 mutex_unlock(&kvm->slots_lock); 3558 return r; 3559 } 3560 3561 int allocate_vpid(void) 3562 { 3563 int vpid; 3564 3565 if (!enable_vpid) 3566 return 0; 3567 spin_lock(&vmx_vpid_lock); 3568 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3569 if (vpid < VMX_NR_VPIDS) 3570 __set_bit(vpid, vmx_vpid_bitmap); 3571 else 3572 vpid = 0; 3573 spin_unlock(&vmx_vpid_lock); 3574 return vpid; 3575 } 3576 3577 void free_vpid(int vpid) 3578 { 3579 if (!enable_vpid || vpid == 0) 3580 return; 3581 spin_lock(&vmx_vpid_lock); 3582 __clear_bit(vpid, vmx_vpid_bitmap); 3583 spin_unlock(&vmx_vpid_lock); 3584 } 3585 3586 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3587 u32 msr, int type) 3588 { 3589 int f = sizeof(unsigned long); 3590 3591 if (!cpu_has_vmx_msr_bitmap()) 3592 return; 3593 3594 if (static_branch_unlikely(&enable_evmcs)) 3595 evmcs_touch_msr_bitmap(); 3596 3597 /* 3598 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3599 * have the write-low and read-high bitmap offsets the wrong way round. 3600 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3601 */ 3602 if (msr <= 0x1fff) { 3603 if (type & MSR_TYPE_R) 3604 /* read-low */ 3605 __clear_bit(msr, msr_bitmap + 0x000 / f); 3606 3607 if (type & MSR_TYPE_W) 3608 /* write-low */ 3609 __clear_bit(msr, msr_bitmap + 0x800 / f); 3610 3611 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3612 msr &= 0x1fff; 3613 if (type & MSR_TYPE_R) 3614 /* read-high */ 3615 __clear_bit(msr, msr_bitmap + 0x400 / f); 3616 3617 if (type & MSR_TYPE_W) 3618 /* write-high */ 3619 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3620 3621 } 3622 } 3623 3624 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3625 u32 msr, int type) 3626 { 3627 int f = sizeof(unsigned long); 3628 3629 if (!cpu_has_vmx_msr_bitmap()) 3630 return; 3631 3632 if (static_branch_unlikely(&enable_evmcs)) 3633 evmcs_touch_msr_bitmap(); 3634 3635 /* 3636 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3637 * have the write-low and read-high bitmap offsets the wrong way round. 3638 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3639 */ 3640 if (msr <= 0x1fff) { 3641 if (type & MSR_TYPE_R) 3642 /* read-low */ 3643 __set_bit(msr, msr_bitmap + 0x000 / f); 3644 3645 if (type & MSR_TYPE_W) 3646 /* write-low */ 3647 __set_bit(msr, msr_bitmap + 0x800 / f); 3648 3649 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3650 msr &= 0x1fff; 3651 if (type & MSR_TYPE_R) 3652 /* read-high */ 3653 __set_bit(msr, msr_bitmap + 0x400 / f); 3654 3655 if (type & MSR_TYPE_W) 3656 /* write-high */ 3657 __set_bit(msr, msr_bitmap + 0xc00 / f); 3658 3659 } 3660 } 3661 3662 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3663 u32 msr, int type, bool value) 3664 { 3665 if (value) 3666 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3667 else 3668 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3669 } 3670 3671 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3672 { 3673 u8 mode = 0; 3674 3675 if (cpu_has_secondary_exec_ctrls() && 3676 (secondary_exec_controls_get(to_vmx(vcpu)) & 3677 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3678 mode |= MSR_BITMAP_MODE_X2APIC; 3679 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3680 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3681 } 3682 3683 return mode; 3684 } 3685 3686 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3687 u8 mode) 3688 { 3689 int msr; 3690 3691 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3692 unsigned word = msr / BITS_PER_LONG; 3693 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3694 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3695 } 3696 3697 if (mode & MSR_BITMAP_MODE_X2APIC) { 3698 /* 3699 * TPR reads and writes can be virtualized even if virtual interrupt 3700 * delivery is not in use. 3701 */ 3702 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3703 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3704 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3705 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3706 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3707 } 3708 } 3709 } 3710 3711 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3712 { 3713 struct vcpu_vmx *vmx = to_vmx(vcpu); 3714 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3715 u8 mode = vmx_msr_bitmap_mode(vcpu); 3716 u8 changed = mode ^ vmx->msr_bitmap_mode; 3717 3718 if (!changed) 3719 return; 3720 3721 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3722 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3723 3724 vmx->msr_bitmap_mode = mode; 3725 } 3726 3727 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3728 { 3729 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3730 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3731 u32 i; 3732 3733 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3734 MSR_TYPE_RW, flag); 3735 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3736 MSR_TYPE_RW, flag); 3737 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3738 MSR_TYPE_RW, flag); 3739 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3740 MSR_TYPE_RW, flag); 3741 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3742 vmx_set_intercept_for_msr(msr_bitmap, 3743 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3744 vmx_set_intercept_for_msr(msr_bitmap, 3745 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3746 } 3747 } 3748 3749 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3750 { 3751 struct vcpu_vmx *vmx = to_vmx(vcpu); 3752 void *vapic_page; 3753 u32 vppr; 3754 int rvi; 3755 3756 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3757 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3758 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3759 return false; 3760 3761 rvi = vmx_get_rvi(); 3762 3763 vapic_page = vmx->nested.virtual_apic_map.hva; 3764 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3765 3766 return ((rvi & 0xf0) > (vppr & 0xf0)); 3767 } 3768 3769 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3770 bool nested) 3771 { 3772 #ifdef CONFIG_SMP 3773 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3774 3775 if (vcpu->mode == IN_GUEST_MODE) { 3776 /* 3777 * The vector of interrupt to be delivered to vcpu had 3778 * been set in PIR before this function. 3779 * 3780 * Following cases will be reached in this block, and 3781 * we always send a notification event in all cases as 3782 * explained below. 3783 * 3784 * Case 1: vcpu keeps in non-root mode. Sending a 3785 * notification event posts the interrupt to vcpu. 3786 * 3787 * Case 2: vcpu exits to root mode and is still 3788 * runnable. PIR will be synced to vIRR before the 3789 * next vcpu entry. Sending a notification event in 3790 * this case has no effect, as vcpu is not in root 3791 * mode. 3792 * 3793 * Case 3: vcpu exits to root mode and is blocked. 3794 * vcpu_block() has already synced PIR to vIRR and 3795 * never blocks vcpu if vIRR is not cleared. Therefore, 3796 * a blocked vcpu here does not wait for any requested 3797 * interrupts in PIR, and sending a notification event 3798 * which has no effect is safe here. 3799 */ 3800 3801 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3802 return true; 3803 } 3804 #endif 3805 return false; 3806 } 3807 3808 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3809 int vector) 3810 { 3811 struct vcpu_vmx *vmx = to_vmx(vcpu); 3812 3813 if (is_guest_mode(vcpu) && 3814 vector == vmx->nested.posted_intr_nv) { 3815 /* 3816 * If a posted intr is not recognized by hardware, 3817 * we will accomplish it in the next vmentry. 3818 */ 3819 vmx->nested.pi_pending = true; 3820 kvm_make_request(KVM_REQ_EVENT, vcpu); 3821 /* the PIR and ON have been set by L1. */ 3822 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3823 kvm_vcpu_kick(vcpu); 3824 return 0; 3825 } 3826 return -1; 3827 } 3828 /* 3829 * Send interrupt to vcpu via posted interrupt way. 3830 * 1. If target vcpu is running(non-root mode), send posted interrupt 3831 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3832 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3833 * interrupt from PIR in next vmentry. 3834 */ 3835 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3836 { 3837 struct vcpu_vmx *vmx = to_vmx(vcpu); 3838 int r; 3839 3840 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3841 if (!r) 3842 return 0; 3843 3844 if (!vcpu->arch.apicv_active) 3845 return -1; 3846 3847 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3848 return 0; 3849 3850 /* If a previous notification has sent the IPI, nothing to do. */ 3851 if (pi_test_and_set_on(&vmx->pi_desc)) 3852 return 0; 3853 3854 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3855 kvm_vcpu_kick(vcpu); 3856 3857 return 0; 3858 } 3859 3860 /* 3861 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3862 * will not change in the lifetime of the guest. 3863 * Note that host-state that does change is set elsewhere. E.g., host-state 3864 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3865 */ 3866 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3867 { 3868 u32 low32, high32; 3869 unsigned long tmpl; 3870 unsigned long cr0, cr3, cr4; 3871 3872 cr0 = read_cr0(); 3873 WARN_ON(cr0 & X86_CR0_TS); 3874 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3875 3876 /* 3877 * Save the most likely value for this task's CR3 in the VMCS. 3878 * We can't use __get_current_cr3_fast() because we're not atomic. 3879 */ 3880 cr3 = __read_cr3(); 3881 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3882 vmx->loaded_vmcs->host_state.cr3 = cr3; 3883 3884 /* Save the most likely value for this task's CR4 in the VMCS. */ 3885 cr4 = cr4_read_shadow(); 3886 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3887 vmx->loaded_vmcs->host_state.cr4 = cr4; 3888 3889 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3890 #ifdef CONFIG_X86_64 3891 /* 3892 * Load null selectors, so we can avoid reloading them in 3893 * vmx_prepare_switch_to_host(), in case userspace uses 3894 * the null selectors too (the expected case). 3895 */ 3896 vmcs_write16(HOST_DS_SELECTOR, 0); 3897 vmcs_write16(HOST_ES_SELECTOR, 0); 3898 #else 3899 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3900 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3901 #endif 3902 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3903 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3904 3905 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3906 3907 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3908 3909 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3910 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3911 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3912 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3913 3914 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3915 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3916 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3917 } 3918 3919 if (cpu_has_load_ia32_efer()) 3920 vmcs_write64(HOST_IA32_EFER, host_efer); 3921 } 3922 3923 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3924 { 3925 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3926 if (enable_ept) 3927 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3928 if (is_guest_mode(&vmx->vcpu)) 3929 vmx->vcpu.arch.cr4_guest_owned_bits &= 3930 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3931 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3932 } 3933 3934 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3935 { 3936 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3937 3938 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3939 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3940 3941 if (!enable_vnmi) 3942 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3943 3944 if (!enable_preemption_timer) 3945 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3946 3947 return pin_based_exec_ctrl; 3948 } 3949 3950 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3951 { 3952 struct vcpu_vmx *vmx = to_vmx(vcpu); 3953 3954 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3955 if (cpu_has_secondary_exec_ctrls()) { 3956 if (kvm_vcpu_apicv_active(vcpu)) 3957 secondary_exec_controls_setbit(vmx, 3958 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3959 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3960 else 3961 secondary_exec_controls_clearbit(vmx, 3962 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3963 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3964 } 3965 3966 if (cpu_has_vmx_msr_bitmap()) 3967 vmx_update_msr_bitmap(vcpu); 3968 } 3969 3970 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3971 { 3972 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3973 3974 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3975 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3976 3977 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3978 exec_control &= ~CPU_BASED_TPR_SHADOW; 3979 #ifdef CONFIG_X86_64 3980 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3981 CPU_BASED_CR8_LOAD_EXITING; 3982 #endif 3983 } 3984 if (!enable_ept) 3985 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3986 CPU_BASED_CR3_LOAD_EXITING | 3987 CPU_BASED_INVLPG_EXITING; 3988 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3989 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3990 CPU_BASED_MONITOR_EXITING); 3991 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3992 exec_control &= ~CPU_BASED_HLT_EXITING; 3993 return exec_control; 3994 } 3995 3996 3997 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 3998 { 3999 struct kvm_vcpu *vcpu = &vmx->vcpu; 4000 4001 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 4002 4003 if (vmx_pt_mode_is_system()) 4004 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 4005 if (!cpu_need_virtualize_apic_accesses(vcpu)) 4006 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4007 if (vmx->vpid == 0) 4008 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4009 if (!enable_ept) { 4010 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4011 enable_unrestricted_guest = 0; 4012 } 4013 if (!enable_unrestricted_guest) 4014 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4015 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4016 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4017 if (!kvm_vcpu_apicv_active(vcpu)) 4018 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4019 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4020 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4021 4022 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4023 * in vmx_set_cr4. */ 4024 exec_control &= ~SECONDARY_EXEC_DESC; 4025 4026 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4027 (handle_vmptrld). 4028 We can NOT enable shadow_vmcs here because we don't have yet 4029 a current VMCS12 4030 */ 4031 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4032 4033 if (!enable_pml) 4034 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4035 4036 if (vmx_xsaves_supported()) { 4037 /* Exposing XSAVES only when XSAVE is exposed */ 4038 bool xsaves_enabled = 4039 boot_cpu_has(X86_FEATURE_XSAVE) && 4040 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4041 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4042 4043 vcpu->arch.xsaves_enabled = xsaves_enabled; 4044 4045 if (!xsaves_enabled) 4046 exec_control &= ~SECONDARY_EXEC_XSAVES; 4047 4048 if (nested) { 4049 if (xsaves_enabled) 4050 vmx->nested.msrs.secondary_ctls_high |= 4051 SECONDARY_EXEC_XSAVES; 4052 else 4053 vmx->nested.msrs.secondary_ctls_high &= 4054 ~SECONDARY_EXEC_XSAVES; 4055 } 4056 } 4057 4058 if (cpu_has_vmx_rdtscp()) { 4059 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4060 if (!rdtscp_enabled) 4061 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4062 4063 if (nested) { 4064 if (rdtscp_enabled) 4065 vmx->nested.msrs.secondary_ctls_high |= 4066 SECONDARY_EXEC_RDTSCP; 4067 else 4068 vmx->nested.msrs.secondary_ctls_high &= 4069 ~SECONDARY_EXEC_RDTSCP; 4070 } 4071 } 4072 4073 if (cpu_has_vmx_invpcid()) { 4074 /* Exposing INVPCID only when PCID is exposed */ 4075 bool invpcid_enabled = 4076 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4077 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4078 4079 if (!invpcid_enabled) { 4080 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4081 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4082 } 4083 4084 if (nested) { 4085 if (invpcid_enabled) 4086 vmx->nested.msrs.secondary_ctls_high |= 4087 SECONDARY_EXEC_ENABLE_INVPCID; 4088 else 4089 vmx->nested.msrs.secondary_ctls_high &= 4090 ~SECONDARY_EXEC_ENABLE_INVPCID; 4091 } 4092 } 4093 4094 if (vmx_rdrand_supported()) { 4095 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4096 if (rdrand_enabled) 4097 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4098 4099 if (nested) { 4100 if (rdrand_enabled) 4101 vmx->nested.msrs.secondary_ctls_high |= 4102 SECONDARY_EXEC_RDRAND_EXITING; 4103 else 4104 vmx->nested.msrs.secondary_ctls_high &= 4105 ~SECONDARY_EXEC_RDRAND_EXITING; 4106 } 4107 } 4108 4109 if (vmx_rdseed_supported()) { 4110 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4111 if (rdseed_enabled) 4112 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4113 4114 if (nested) { 4115 if (rdseed_enabled) 4116 vmx->nested.msrs.secondary_ctls_high |= 4117 SECONDARY_EXEC_RDSEED_EXITING; 4118 else 4119 vmx->nested.msrs.secondary_ctls_high &= 4120 ~SECONDARY_EXEC_RDSEED_EXITING; 4121 } 4122 } 4123 4124 if (vmx_waitpkg_supported()) { 4125 bool waitpkg_enabled = 4126 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4127 4128 if (!waitpkg_enabled) 4129 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4130 4131 if (nested) { 4132 if (waitpkg_enabled) 4133 vmx->nested.msrs.secondary_ctls_high |= 4134 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4135 else 4136 vmx->nested.msrs.secondary_ctls_high &= 4137 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4138 } 4139 } 4140 4141 vmx->secondary_exec_control = exec_control; 4142 } 4143 4144 static void ept_set_mmio_spte_mask(void) 4145 { 4146 /* 4147 * EPT Misconfigurations can be generated if the value of bits 2:0 4148 * of an EPT paging-structure entry is 110b (write/execute). 4149 */ 4150 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4151 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4152 } 4153 4154 #define VMX_XSS_EXIT_BITMAP 0 4155 4156 /* 4157 * Noting that the initialization of Guest-state Area of VMCS is in 4158 * vmx_vcpu_reset(). 4159 */ 4160 static void init_vmcs(struct vcpu_vmx *vmx) 4161 { 4162 if (nested) 4163 nested_vmx_set_vmcs_shadowing_bitmap(); 4164 4165 if (cpu_has_vmx_msr_bitmap()) 4166 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4167 4168 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4169 4170 /* Control */ 4171 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4172 4173 exec_controls_set(vmx, vmx_exec_control(vmx)); 4174 4175 if (cpu_has_secondary_exec_ctrls()) { 4176 vmx_compute_secondary_exec_control(vmx); 4177 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4178 } 4179 4180 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4181 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4182 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4183 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4184 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4185 4186 vmcs_write16(GUEST_INTR_STATUS, 0); 4187 4188 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4189 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4190 } 4191 4192 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4193 vmcs_write32(PLE_GAP, ple_gap); 4194 vmx->ple_window = ple_window; 4195 vmx->ple_window_dirty = true; 4196 } 4197 4198 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4199 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4200 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4201 4202 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4203 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4204 vmx_set_constant_host_state(vmx); 4205 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4206 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4207 4208 if (cpu_has_vmx_vmfunc()) 4209 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4210 4211 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4212 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4213 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4214 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4215 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4216 4217 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4218 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4219 4220 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4221 4222 /* 22.2.1, 20.8.1 */ 4223 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4224 4225 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4226 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4227 4228 set_cr4_guest_host_mask(vmx); 4229 4230 if (vmx->vpid != 0) 4231 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4232 4233 if (vmx_xsaves_supported()) 4234 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4235 4236 if (enable_pml) { 4237 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4238 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4239 } 4240 4241 if (cpu_has_vmx_encls_vmexit()) 4242 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4243 4244 if (vmx_pt_mode_is_host_guest()) { 4245 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4246 /* Bit[6~0] are forced to 1, writes are ignored. */ 4247 vmx->pt_desc.guest.output_mask = 0x7F; 4248 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4249 } 4250 } 4251 4252 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4253 { 4254 struct vcpu_vmx *vmx = to_vmx(vcpu); 4255 struct msr_data apic_base_msr; 4256 u64 cr0; 4257 4258 vmx->rmode.vm86_active = 0; 4259 vmx->spec_ctrl = 0; 4260 4261 vmx->msr_ia32_umwait_control = 0; 4262 4263 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4264 vmx->hv_deadline_tsc = -1; 4265 kvm_set_cr8(vcpu, 0); 4266 4267 if (!init_event) { 4268 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4269 MSR_IA32_APICBASE_ENABLE; 4270 if (kvm_vcpu_is_reset_bsp(vcpu)) 4271 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4272 apic_base_msr.host_initiated = true; 4273 kvm_set_apic_base(vcpu, &apic_base_msr); 4274 } 4275 4276 vmx_segment_cache_clear(vmx); 4277 4278 seg_setup(VCPU_SREG_CS); 4279 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4280 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4281 4282 seg_setup(VCPU_SREG_DS); 4283 seg_setup(VCPU_SREG_ES); 4284 seg_setup(VCPU_SREG_FS); 4285 seg_setup(VCPU_SREG_GS); 4286 seg_setup(VCPU_SREG_SS); 4287 4288 vmcs_write16(GUEST_TR_SELECTOR, 0); 4289 vmcs_writel(GUEST_TR_BASE, 0); 4290 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4291 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4292 4293 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4294 vmcs_writel(GUEST_LDTR_BASE, 0); 4295 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4296 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4297 4298 if (!init_event) { 4299 vmcs_write32(GUEST_SYSENTER_CS, 0); 4300 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4301 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4302 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4303 } 4304 4305 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4306 kvm_rip_write(vcpu, 0xfff0); 4307 4308 vmcs_writel(GUEST_GDTR_BASE, 0); 4309 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4310 4311 vmcs_writel(GUEST_IDTR_BASE, 0); 4312 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4313 4314 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4315 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4316 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4317 if (kvm_mpx_supported()) 4318 vmcs_write64(GUEST_BNDCFGS, 0); 4319 4320 setup_msrs(vmx); 4321 4322 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4323 4324 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4325 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4326 if (cpu_need_tpr_shadow(vcpu)) 4327 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4328 __pa(vcpu->arch.apic->regs)); 4329 vmcs_write32(TPR_THRESHOLD, 0); 4330 } 4331 4332 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4333 4334 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4335 vmx->vcpu.arch.cr0 = cr0; 4336 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4337 vmx_set_cr4(vcpu, 0); 4338 vmx_set_efer(vcpu, 0); 4339 4340 update_exception_bitmap(vcpu); 4341 4342 vpid_sync_context(vmx->vpid); 4343 if (init_event) 4344 vmx_clear_hlt(vcpu); 4345 } 4346 4347 static void enable_irq_window(struct kvm_vcpu *vcpu) 4348 { 4349 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4350 } 4351 4352 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4353 { 4354 if (!enable_vnmi || 4355 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4356 enable_irq_window(vcpu); 4357 return; 4358 } 4359 4360 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4361 } 4362 4363 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4364 { 4365 struct vcpu_vmx *vmx = to_vmx(vcpu); 4366 uint32_t intr; 4367 int irq = vcpu->arch.interrupt.nr; 4368 4369 trace_kvm_inj_virq(irq); 4370 4371 ++vcpu->stat.irq_injections; 4372 if (vmx->rmode.vm86_active) { 4373 int inc_eip = 0; 4374 if (vcpu->arch.interrupt.soft) 4375 inc_eip = vcpu->arch.event_exit_inst_len; 4376 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4377 return; 4378 } 4379 intr = irq | INTR_INFO_VALID_MASK; 4380 if (vcpu->arch.interrupt.soft) { 4381 intr |= INTR_TYPE_SOFT_INTR; 4382 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4383 vmx->vcpu.arch.event_exit_inst_len); 4384 } else 4385 intr |= INTR_TYPE_EXT_INTR; 4386 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4387 4388 vmx_clear_hlt(vcpu); 4389 } 4390 4391 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4392 { 4393 struct vcpu_vmx *vmx = to_vmx(vcpu); 4394 4395 if (!enable_vnmi) { 4396 /* 4397 * Tracking the NMI-blocked state in software is built upon 4398 * finding the next open IRQ window. This, in turn, depends on 4399 * well-behaving guests: They have to keep IRQs disabled at 4400 * least as long as the NMI handler runs. Otherwise we may 4401 * cause NMI nesting, maybe breaking the guest. But as this is 4402 * highly unlikely, we can live with the residual risk. 4403 */ 4404 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4405 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4406 } 4407 4408 ++vcpu->stat.nmi_injections; 4409 vmx->loaded_vmcs->nmi_known_unmasked = false; 4410 4411 if (vmx->rmode.vm86_active) { 4412 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4413 return; 4414 } 4415 4416 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4417 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4418 4419 vmx_clear_hlt(vcpu); 4420 } 4421 4422 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4423 { 4424 struct vcpu_vmx *vmx = to_vmx(vcpu); 4425 bool masked; 4426 4427 if (!enable_vnmi) 4428 return vmx->loaded_vmcs->soft_vnmi_blocked; 4429 if (vmx->loaded_vmcs->nmi_known_unmasked) 4430 return false; 4431 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4432 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4433 return masked; 4434 } 4435 4436 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4437 { 4438 struct vcpu_vmx *vmx = to_vmx(vcpu); 4439 4440 if (!enable_vnmi) { 4441 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4442 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4443 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4444 } 4445 } else { 4446 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4447 if (masked) 4448 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4449 GUEST_INTR_STATE_NMI); 4450 else 4451 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4452 GUEST_INTR_STATE_NMI); 4453 } 4454 } 4455 4456 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4457 { 4458 if (to_vmx(vcpu)->nested.nested_run_pending) 4459 return 0; 4460 4461 if (!enable_vnmi && 4462 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4463 return 0; 4464 4465 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4466 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4467 | GUEST_INTR_STATE_NMI)); 4468 } 4469 4470 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4471 { 4472 if (to_vmx(vcpu)->nested.nested_run_pending) 4473 return false; 4474 4475 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) 4476 return true; 4477 4478 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4479 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4480 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4481 } 4482 4483 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4484 { 4485 int ret; 4486 4487 if (enable_unrestricted_guest) 4488 return 0; 4489 4490 mutex_lock(&kvm->slots_lock); 4491 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4492 PAGE_SIZE * 3); 4493 mutex_unlock(&kvm->slots_lock); 4494 4495 if (ret) 4496 return ret; 4497 to_kvm_vmx(kvm)->tss_addr = addr; 4498 return init_rmode_tss(kvm); 4499 } 4500 4501 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4502 { 4503 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4504 return 0; 4505 } 4506 4507 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4508 { 4509 switch (vec) { 4510 case BP_VECTOR: 4511 /* 4512 * Update instruction length as we may reinject the exception 4513 * from user space while in guest debugging mode. 4514 */ 4515 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4516 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4517 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4518 return false; 4519 /* fall through */ 4520 case DB_VECTOR: 4521 if (vcpu->guest_debug & 4522 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4523 return false; 4524 /* fall through */ 4525 case DE_VECTOR: 4526 case OF_VECTOR: 4527 case BR_VECTOR: 4528 case UD_VECTOR: 4529 case DF_VECTOR: 4530 case SS_VECTOR: 4531 case GP_VECTOR: 4532 case MF_VECTOR: 4533 return true; 4534 } 4535 return false; 4536 } 4537 4538 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4539 int vec, u32 err_code) 4540 { 4541 /* 4542 * Instruction with address size override prefix opcode 0x67 4543 * Cause the #SS fault with 0 error code in VM86 mode. 4544 */ 4545 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4546 if (kvm_emulate_instruction(vcpu, 0)) { 4547 if (vcpu->arch.halt_request) { 4548 vcpu->arch.halt_request = 0; 4549 return kvm_vcpu_halt(vcpu); 4550 } 4551 return 1; 4552 } 4553 return 0; 4554 } 4555 4556 /* 4557 * Forward all other exceptions that are valid in real mode. 4558 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4559 * the required debugging infrastructure rework. 4560 */ 4561 kvm_queue_exception(vcpu, vec); 4562 return 1; 4563 } 4564 4565 /* 4566 * Trigger machine check on the host. We assume all the MSRs are already set up 4567 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4568 * We pass a fake environment to the machine check handler because we want 4569 * the guest to be always treated like user space, no matter what context 4570 * it used internally. 4571 */ 4572 static void kvm_machine_check(void) 4573 { 4574 #if defined(CONFIG_X86_MCE) 4575 struct pt_regs regs = { 4576 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4577 .flags = X86_EFLAGS_IF, 4578 }; 4579 4580 do_machine_check(®s, 0); 4581 #endif 4582 } 4583 4584 static int handle_machine_check(struct kvm_vcpu *vcpu) 4585 { 4586 /* handled by vmx_vcpu_run() */ 4587 return 1; 4588 } 4589 4590 /* 4591 * If the host has split lock detection disabled, then #AC is 4592 * unconditionally injected into the guest, which is the pre split lock 4593 * detection behaviour. 4594 * 4595 * If the host has split lock detection enabled then #AC is 4596 * only injected into the guest when: 4597 * - Guest CPL == 3 (user mode) 4598 * - Guest has #AC detection enabled in CR0 4599 * - Guest EFLAGS has AC bit set 4600 */ 4601 static inline bool guest_inject_ac(struct kvm_vcpu *vcpu) 4602 { 4603 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 4604 return true; 4605 4606 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) && 4607 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC); 4608 } 4609 4610 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4611 { 4612 struct vcpu_vmx *vmx = to_vmx(vcpu); 4613 struct kvm_run *kvm_run = vcpu->run; 4614 u32 intr_info, ex_no, error_code; 4615 unsigned long cr2, rip, dr6; 4616 u32 vect_info; 4617 4618 vect_info = vmx->idt_vectoring_info; 4619 intr_info = vmx->exit_intr_info; 4620 4621 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4622 return 1; /* handled by handle_exception_nmi_irqoff() */ 4623 4624 if (is_invalid_opcode(intr_info)) 4625 return handle_ud(vcpu); 4626 4627 error_code = 0; 4628 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4629 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4630 4631 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4632 WARN_ON_ONCE(!enable_vmware_backdoor); 4633 4634 /* 4635 * VMware backdoor emulation on #GP interception only handles 4636 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4637 * error code on #GP. 4638 */ 4639 if (error_code) { 4640 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4641 return 1; 4642 } 4643 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4644 } 4645 4646 /* 4647 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4648 * MMIO, it is better to report an internal error. 4649 * See the comments in vmx_handle_exit. 4650 */ 4651 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4652 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4653 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4654 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4655 vcpu->run->internal.ndata = 3; 4656 vcpu->run->internal.data[0] = vect_info; 4657 vcpu->run->internal.data[1] = intr_info; 4658 vcpu->run->internal.data[2] = error_code; 4659 return 0; 4660 } 4661 4662 if (is_page_fault(intr_info)) { 4663 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4664 /* EPT won't cause page fault directly */ 4665 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4666 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4667 } 4668 4669 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4670 4671 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4672 return handle_rmode_exception(vcpu, ex_no, error_code); 4673 4674 switch (ex_no) { 4675 case DB_VECTOR: 4676 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4677 if (!(vcpu->guest_debug & 4678 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4679 if (is_icebp(intr_info)) 4680 WARN_ON(!skip_emulated_instruction(vcpu)); 4681 4682 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 4683 return 1; 4684 } 4685 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 4686 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4687 /* fall through */ 4688 case BP_VECTOR: 4689 /* 4690 * Update instruction length as we may reinject #BP from 4691 * user space while in guest debugging mode. Reading it for 4692 * #DB as well causes no harm, it is not used in that case. 4693 */ 4694 vmx->vcpu.arch.event_exit_inst_len = 4695 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4696 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4697 rip = kvm_rip_read(vcpu); 4698 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4699 kvm_run->debug.arch.exception = ex_no; 4700 break; 4701 case AC_VECTOR: 4702 if (guest_inject_ac(vcpu)) { 4703 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4704 return 1; 4705 } 4706 4707 /* 4708 * Handle split lock. Depending on detection mode this will 4709 * either warn and disable split lock detection for this 4710 * task or force SIGBUS on it. 4711 */ 4712 if (handle_guest_split_lock(kvm_rip_read(vcpu))) 4713 return 1; 4714 fallthrough; 4715 default: 4716 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4717 kvm_run->ex.exception = ex_no; 4718 kvm_run->ex.error_code = error_code; 4719 break; 4720 } 4721 return 0; 4722 } 4723 4724 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4725 { 4726 ++vcpu->stat.irq_exits; 4727 return 1; 4728 } 4729 4730 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4731 { 4732 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4733 vcpu->mmio_needed = 0; 4734 return 0; 4735 } 4736 4737 static int handle_io(struct kvm_vcpu *vcpu) 4738 { 4739 unsigned long exit_qualification; 4740 int size, in, string; 4741 unsigned port; 4742 4743 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4744 string = (exit_qualification & 16) != 0; 4745 4746 ++vcpu->stat.io_exits; 4747 4748 if (string) 4749 return kvm_emulate_instruction(vcpu, 0); 4750 4751 port = exit_qualification >> 16; 4752 size = (exit_qualification & 7) + 1; 4753 in = (exit_qualification & 8) != 0; 4754 4755 return kvm_fast_pio(vcpu, size, port, in); 4756 } 4757 4758 static void 4759 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4760 { 4761 /* 4762 * Patch in the VMCALL instruction: 4763 */ 4764 hypercall[0] = 0x0f; 4765 hypercall[1] = 0x01; 4766 hypercall[2] = 0xc1; 4767 } 4768 4769 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4770 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4771 { 4772 if (is_guest_mode(vcpu)) { 4773 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4774 unsigned long orig_val = val; 4775 4776 /* 4777 * We get here when L2 changed cr0 in a way that did not change 4778 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4779 * but did change L0 shadowed bits. So we first calculate the 4780 * effective cr0 value that L1 would like to write into the 4781 * hardware. It consists of the L2-owned bits from the new 4782 * value combined with the L1-owned bits from L1's guest_cr0. 4783 */ 4784 val = (val & ~vmcs12->cr0_guest_host_mask) | 4785 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4786 4787 if (!nested_guest_cr0_valid(vcpu, val)) 4788 return 1; 4789 4790 if (kvm_set_cr0(vcpu, val)) 4791 return 1; 4792 vmcs_writel(CR0_READ_SHADOW, orig_val); 4793 return 0; 4794 } else { 4795 if (to_vmx(vcpu)->nested.vmxon && 4796 !nested_host_cr0_valid(vcpu, val)) 4797 return 1; 4798 4799 return kvm_set_cr0(vcpu, val); 4800 } 4801 } 4802 4803 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4804 { 4805 if (is_guest_mode(vcpu)) { 4806 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4807 unsigned long orig_val = val; 4808 4809 /* analogously to handle_set_cr0 */ 4810 val = (val & ~vmcs12->cr4_guest_host_mask) | 4811 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4812 if (kvm_set_cr4(vcpu, val)) 4813 return 1; 4814 vmcs_writel(CR4_READ_SHADOW, orig_val); 4815 return 0; 4816 } else 4817 return kvm_set_cr4(vcpu, val); 4818 } 4819 4820 static int handle_desc(struct kvm_vcpu *vcpu) 4821 { 4822 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4823 return kvm_emulate_instruction(vcpu, 0); 4824 } 4825 4826 static int handle_cr(struct kvm_vcpu *vcpu) 4827 { 4828 unsigned long exit_qualification, val; 4829 int cr; 4830 int reg; 4831 int err; 4832 int ret; 4833 4834 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4835 cr = exit_qualification & 15; 4836 reg = (exit_qualification >> 8) & 15; 4837 switch ((exit_qualification >> 4) & 3) { 4838 case 0: /* mov to cr */ 4839 val = kvm_register_readl(vcpu, reg); 4840 trace_kvm_cr_write(cr, val); 4841 switch (cr) { 4842 case 0: 4843 err = handle_set_cr0(vcpu, val); 4844 return kvm_complete_insn_gp(vcpu, err); 4845 case 3: 4846 WARN_ON_ONCE(enable_unrestricted_guest); 4847 err = kvm_set_cr3(vcpu, val); 4848 return kvm_complete_insn_gp(vcpu, err); 4849 case 4: 4850 err = handle_set_cr4(vcpu, val); 4851 return kvm_complete_insn_gp(vcpu, err); 4852 case 8: { 4853 u8 cr8_prev = kvm_get_cr8(vcpu); 4854 u8 cr8 = (u8)val; 4855 err = kvm_set_cr8(vcpu, cr8); 4856 ret = kvm_complete_insn_gp(vcpu, err); 4857 if (lapic_in_kernel(vcpu)) 4858 return ret; 4859 if (cr8_prev <= cr8) 4860 return ret; 4861 /* 4862 * TODO: we might be squashing a 4863 * KVM_GUESTDBG_SINGLESTEP-triggered 4864 * KVM_EXIT_DEBUG here. 4865 */ 4866 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4867 return 0; 4868 } 4869 } 4870 break; 4871 case 2: /* clts */ 4872 WARN_ONCE(1, "Guest should always own CR0.TS"); 4873 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4874 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4875 return kvm_skip_emulated_instruction(vcpu); 4876 case 1: /*mov from cr*/ 4877 switch (cr) { 4878 case 3: 4879 WARN_ON_ONCE(enable_unrestricted_guest); 4880 val = kvm_read_cr3(vcpu); 4881 kvm_register_write(vcpu, reg, val); 4882 trace_kvm_cr_read(cr, val); 4883 return kvm_skip_emulated_instruction(vcpu); 4884 case 8: 4885 val = kvm_get_cr8(vcpu); 4886 kvm_register_write(vcpu, reg, val); 4887 trace_kvm_cr_read(cr, val); 4888 return kvm_skip_emulated_instruction(vcpu); 4889 } 4890 break; 4891 case 3: /* lmsw */ 4892 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4893 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4894 kvm_lmsw(vcpu, val); 4895 4896 return kvm_skip_emulated_instruction(vcpu); 4897 default: 4898 break; 4899 } 4900 vcpu->run->exit_reason = 0; 4901 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4902 (int)(exit_qualification >> 4) & 3, cr); 4903 return 0; 4904 } 4905 4906 static int handle_dr(struct kvm_vcpu *vcpu) 4907 { 4908 unsigned long exit_qualification; 4909 int dr, dr7, reg; 4910 4911 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4912 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4913 4914 /* First, if DR does not exist, trigger UD */ 4915 if (!kvm_require_dr(vcpu, dr)) 4916 return 1; 4917 4918 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4919 if (!kvm_require_cpl(vcpu, 0)) 4920 return 1; 4921 dr7 = vmcs_readl(GUEST_DR7); 4922 if (dr7 & DR7_GD) { 4923 /* 4924 * As the vm-exit takes precedence over the debug trap, we 4925 * need to emulate the latter, either for the host or the 4926 * guest debugging itself. 4927 */ 4928 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4929 vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1; 4930 vcpu->run->debug.arch.dr7 = dr7; 4931 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4932 vcpu->run->debug.arch.exception = DB_VECTOR; 4933 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4934 return 0; 4935 } else { 4936 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD); 4937 return 1; 4938 } 4939 } 4940 4941 if (vcpu->guest_debug == 0) { 4942 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4943 4944 /* 4945 * No more DR vmexits; force a reload of the debug registers 4946 * and reenter on this instruction. The next vmexit will 4947 * retrieve the full state of the debug registers. 4948 */ 4949 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4950 return 1; 4951 } 4952 4953 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4954 if (exit_qualification & TYPE_MOV_FROM_DR) { 4955 unsigned long val; 4956 4957 if (kvm_get_dr(vcpu, dr, &val)) 4958 return 1; 4959 kvm_register_write(vcpu, reg, val); 4960 } else 4961 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4962 return 1; 4963 4964 return kvm_skip_emulated_instruction(vcpu); 4965 } 4966 4967 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4968 { 4969 get_debugreg(vcpu->arch.db[0], 0); 4970 get_debugreg(vcpu->arch.db[1], 1); 4971 get_debugreg(vcpu->arch.db[2], 2); 4972 get_debugreg(vcpu->arch.db[3], 3); 4973 get_debugreg(vcpu->arch.dr6, 6); 4974 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4975 4976 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4977 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4978 } 4979 4980 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4981 { 4982 vmcs_writel(GUEST_DR7, val); 4983 } 4984 4985 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4986 { 4987 kvm_apic_update_ppr(vcpu); 4988 return 1; 4989 } 4990 4991 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4992 { 4993 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4994 4995 kvm_make_request(KVM_REQ_EVENT, vcpu); 4996 4997 ++vcpu->stat.irq_window_exits; 4998 return 1; 4999 } 5000 5001 static int handle_vmcall(struct kvm_vcpu *vcpu) 5002 { 5003 return kvm_emulate_hypercall(vcpu); 5004 } 5005 5006 static int handle_invd(struct kvm_vcpu *vcpu) 5007 { 5008 return kvm_emulate_instruction(vcpu, 0); 5009 } 5010 5011 static int handle_invlpg(struct kvm_vcpu *vcpu) 5012 { 5013 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5014 5015 kvm_mmu_invlpg(vcpu, exit_qualification); 5016 return kvm_skip_emulated_instruction(vcpu); 5017 } 5018 5019 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5020 { 5021 int err; 5022 5023 err = kvm_rdpmc(vcpu); 5024 return kvm_complete_insn_gp(vcpu, err); 5025 } 5026 5027 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5028 { 5029 return kvm_emulate_wbinvd(vcpu); 5030 } 5031 5032 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5033 { 5034 u64 new_bv = kvm_read_edx_eax(vcpu); 5035 u32 index = kvm_rcx_read(vcpu); 5036 5037 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5038 return kvm_skip_emulated_instruction(vcpu); 5039 return 1; 5040 } 5041 5042 static int handle_apic_access(struct kvm_vcpu *vcpu) 5043 { 5044 if (likely(fasteoi)) { 5045 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5046 int access_type, offset; 5047 5048 access_type = exit_qualification & APIC_ACCESS_TYPE; 5049 offset = exit_qualification & APIC_ACCESS_OFFSET; 5050 /* 5051 * Sane guest uses MOV to write EOI, with written value 5052 * not cared. So make a short-circuit here by avoiding 5053 * heavy instruction emulation. 5054 */ 5055 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5056 (offset == APIC_EOI)) { 5057 kvm_lapic_set_eoi(vcpu); 5058 return kvm_skip_emulated_instruction(vcpu); 5059 } 5060 } 5061 return kvm_emulate_instruction(vcpu, 0); 5062 } 5063 5064 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5065 { 5066 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5067 int vector = exit_qualification & 0xff; 5068 5069 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5070 kvm_apic_set_eoi_accelerated(vcpu, vector); 5071 return 1; 5072 } 5073 5074 static int handle_apic_write(struct kvm_vcpu *vcpu) 5075 { 5076 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5077 u32 offset = exit_qualification & 0xfff; 5078 5079 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5080 kvm_apic_write_nodecode(vcpu, offset); 5081 return 1; 5082 } 5083 5084 static int handle_task_switch(struct kvm_vcpu *vcpu) 5085 { 5086 struct vcpu_vmx *vmx = to_vmx(vcpu); 5087 unsigned long exit_qualification; 5088 bool has_error_code = false; 5089 u32 error_code = 0; 5090 u16 tss_selector; 5091 int reason, type, idt_v, idt_index; 5092 5093 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5094 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5095 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5096 5097 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5098 5099 reason = (u32)exit_qualification >> 30; 5100 if (reason == TASK_SWITCH_GATE && idt_v) { 5101 switch (type) { 5102 case INTR_TYPE_NMI_INTR: 5103 vcpu->arch.nmi_injected = false; 5104 vmx_set_nmi_mask(vcpu, true); 5105 break; 5106 case INTR_TYPE_EXT_INTR: 5107 case INTR_TYPE_SOFT_INTR: 5108 kvm_clear_interrupt_queue(vcpu); 5109 break; 5110 case INTR_TYPE_HARD_EXCEPTION: 5111 if (vmx->idt_vectoring_info & 5112 VECTORING_INFO_DELIVER_CODE_MASK) { 5113 has_error_code = true; 5114 error_code = 5115 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5116 } 5117 /* fall through */ 5118 case INTR_TYPE_SOFT_EXCEPTION: 5119 kvm_clear_exception_queue(vcpu); 5120 break; 5121 default: 5122 break; 5123 } 5124 } 5125 tss_selector = exit_qualification; 5126 5127 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5128 type != INTR_TYPE_EXT_INTR && 5129 type != INTR_TYPE_NMI_INTR)) 5130 WARN_ON(!skip_emulated_instruction(vcpu)); 5131 5132 /* 5133 * TODO: What about debug traps on tss switch? 5134 * Are we supposed to inject them and update dr6? 5135 */ 5136 return kvm_task_switch(vcpu, tss_selector, 5137 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5138 reason, has_error_code, error_code); 5139 } 5140 5141 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5142 { 5143 unsigned long exit_qualification; 5144 gpa_t gpa; 5145 u64 error_code; 5146 5147 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5148 5149 /* 5150 * EPT violation happened while executing iret from NMI, 5151 * "blocked by NMI" bit has to be set before next VM entry. 5152 * There are errata that may cause this bit to not be set: 5153 * AAK134, BY25. 5154 */ 5155 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5156 enable_vnmi && 5157 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5158 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5159 5160 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5161 trace_kvm_page_fault(gpa, exit_qualification); 5162 5163 /* Is it a read fault? */ 5164 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5165 ? PFERR_USER_MASK : 0; 5166 /* Is it a write fault? */ 5167 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5168 ? PFERR_WRITE_MASK : 0; 5169 /* Is it a fetch fault? */ 5170 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5171 ? PFERR_FETCH_MASK : 0; 5172 /* ept page table entry is present? */ 5173 error_code |= (exit_qualification & 5174 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5175 EPT_VIOLATION_EXECUTABLE)) 5176 ? PFERR_PRESENT_MASK : 0; 5177 5178 error_code |= (exit_qualification & 0x100) != 0 ? 5179 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5180 5181 vcpu->arch.exit_qualification = exit_qualification; 5182 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5183 } 5184 5185 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5186 { 5187 gpa_t gpa; 5188 5189 /* 5190 * A nested guest cannot optimize MMIO vmexits, because we have an 5191 * nGPA here instead of the required GPA. 5192 */ 5193 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5194 if (!is_guest_mode(vcpu) && 5195 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5196 trace_kvm_fast_mmio(gpa); 5197 return kvm_skip_emulated_instruction(vcpu); 5198 } 5199 5200 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5201 } 5202 5203 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5204 { 5205 WARN_ON_ONCE(!enable_vnmi); 5206 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5207 ++vcpu->stat.nmi_window_exits; 5208 kvm_make_request(KVM_REQ_EVENT, vcpu); 5209 5210 return 1; 5211 } 5212 5213 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5214 { 5215 struct vcpu_vmx *vmx = to_vmx(vcpu); 5216 bool intr_window_requested; 5217 unsigned count = 130; 5218 5219 /* 5220 * We should never reach the point where we are emulating L2 5221 * due to invalid guest state as that means we incorrectly 5222 * allowed a nested VMEntry with an invalid vmcs12. 5223 */ 5224 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5225 5226 intr_window_requested = exec_controls_get(vmx) & 5227 CPU_BASED_INTR_WINDOW_EXITING; 5228 5229 while (vmx->emulation_required && count-- != 0) { 5230 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5231 return handle_interrupt_window(&vmx->vcpu); 5232 5233 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5234 return 1; 5235 5236 if (!kvm_emulate_instruction(vcpu, 0)) 5237 return 0; 5238 5239 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5240 vcpu->arch.exception.pending) { 5241 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5242 vcpu->run->internal.suberror = 5243 KVM_INTERNAL_ERROR_EMULATION; 5244 vcpu->run->internal.ndata = 0; 5245 return 0; 5246 } 5247 5248 if (vcpu->arch.halt_request) { 5249 vcpu->arch.halt_request = 0; 5250 return kvm_vcpu_halt(vcpu); 5251 } 5252 5253 /* 5254 * Note, return 1 and not 0, vcpu_run() is responsible for 5255 * morphing the pending signal into the proper return code. 5256 */ 5257 if (signal_pending(current)) 5258 return 1; 5259 5260 if (need_resched()) 5261 schedule(); 5262 } 5263 5264 return 1; 5265 } 5266 5267 static void grow_ple_window(struct kvm_vcpu *vcpu) 5268 { 5269 struct vcpu_vmx *vmx = to_vmx(vcpu); 5270 unsigned int old = vmx->ple_window; 5271 5272 vmx->ple_window = __grow_ple_window(old, ple_window, 5273 ple_window_grow, 5274 ple_window_max); 5275 5276 if (vmx->ple_window != old) { 5277 vmx->ple_window_dirty = true; 5278 trace_kvm_ple_window_update(vcpu->vcpu_id, 5279 vmx->ple_window, old); 5280 } 5281 } 5282 5283 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5284 { 5285 struct vcpu_vmx *vmx = to_vmx(vcpu); 5286 unsigned int old = vmx->ple_window; 5287 5288 vmx->ple_window = __shrink_ple_window(old, ple_window, 5289 ple_window_shrink, 5290 ple_window); 5291 5292 if (vmx->ple_window != old) { 5293 vmx->ple_window_dirty = true; 5294 trace_kvm_ple_window_update(vcpu->vcpu_id, 5295 vmx->ple_window, old); 5296 } 5297 } 5298 5299 /* 5300 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5301 */ 5302 static void wakeup_handler(void) 5303 { 5304 struct kvm_vcpu *vcpu; 5305 int cpu = smp_processor_id(); 5306 5307 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5308 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5309 blocked_vcpu_list) { 5310 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5311 5312 if (pi_test_on(pi_desc) == 1) 5313 kvm_vcpu_kick(vcpu); 5314 } 5315 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5316 } 5317 5318 static void vmx_enable_tdp(void) 5319 { 5320 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5321 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5322 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5323 0ull, VMX_EPT_EXECUTABLE_MASK, 5324 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5325 VMX_EPT_RWX_MASK, 0ull); 5326 5327 ept_set_mmio_spte_mask(); 5328 } 5329 5330 /* 5331 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5332 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5333 */ 5334 static int handle_pause(struct kvm_vcpu *vcpu) 5335 { 5336 if (!kvm_pause_in_guest(vcpu->kvm)) 5337 grow_ple_window(vcpu); 5338 5339 /* 5340 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5341 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5342 * never set PAUSE_EXITING and just set PLE if supported, 5343 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5344 */ 5345 kvm_vcpu_on_spin(vcpu, true); 5346 return kvm_skip_emulated_instruction(vcpu); 5347 } 5348 5349 static int handle_nop(struct kvm_vcpu *vcpu) 5350 { 5351 return kvm_skip_emulated_instruction(vcpu); 5352 } 5353 5354 static int handle_mwait(struct kvm_vcpu *vcpu) 5355 { 5356 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5357 return handle_nop(vcpu); 5358 } 5359 5360 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5361 { 5362 kvm_queue_exception(vcpu, UD_VECTOR); 5363 return 1; 5364 } 5365 5366 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5367 { 5368 return 1; 5369 } 5370 5371 static int handle_monitor(struct kvm_vcpu *vcpu) 5372 { 5373 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5374 return handle_nop(vcpu); 5375 } 5376 5377 static int handle_invpcid(struct kvm_vcpu *vcpu) 5378 { 5379 u32 vmx_instruction_info; 5380 unsigned long type; 5381 bool pcid_enabled; 5382 gva_t gva; 5383 struct x86_exception e; 5384 unsigned i; 5385 unsigned long roots_to_free = 0; 5386 struct { 5387 u64 pcid; 5388 u64 gla; 5389 } operand; 5390 5391 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5392 kvm_queue_exception(vcpu, UD_VECTOR); 5393 return 1; 5394 } 5395 5396 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5397 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5398 5399 if (type > 3) { 5400 kvm_inject_gp(vcpu, 0); 5401 return 1; 5402 } 5403 5404 /* According to the Intel instruction reference, the memory operand 5405 * is read even if it isn't needed (e.g., for type==all) 5406 */ 5407 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5408 vmx_instruction_info, false, 5409 sizeof(operand), &gva)) 5410 return 1; 5411 5412 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5413 kvm_inject_page_fault(vcpu, &e); 5414 return 1; 5415 } 5416 5417 if (operand.pcid >> 12 != 0) { 5418 kvm_inject_gp(vcpu, 0); 5419 return 1; 5420 } 5421 5422 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5423 5424 switch (type) { 5425 case INVPCID_TYPE_INDIV_ADDR: 5426 if ((!pcid_enabled && (operand.pcid != 0)) || 5427 is_noncanonical_address(operand.gla, vcpu)) { 5428 kvm_inject_gp(vcpu, 0); 5429 return 1; 5430 } 5431 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5432 return kvm_skip_emulated_instruction(vcpu); 5433 5434 case INVPCID_TYPE_SINGLE_CTXT: 5435 if (!pcid_enabled && (operand.pcid != 0)) { 5436 kvm_inject_gp(vcpu, 0); 5437 return 1; 5438 } 5439 5440 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5441 kvm_mmu_sync_roots(vcpu); 5442 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5443 } 5444 5445 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5446 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5447 == operand.pcid) 5448 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5449 5450 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5451 /* 5452 * If neither the current cr3 nor any of the prev_roots use the 5453 * given PCID, then nothing needs to be done here because a 5454 * resync will happen anyway before switching to any other CR3. 5455 */ 5456 5457 return kvm_skip_emulated_instruction(vcpu); 5458 5459 case INVPCID_TYPE_ALL_NON_GLOBAL: 5460 /* 5461 * Currently, KVM doesn't mark global entries in the shadow 5462 * page tables, so a non-global flush just degenerates to a 5463 * global flush. If needed, we could optimize this later by 5464 * keeping track of global entries in shadow page tables. 5465 */ 5466 5467 /* fall-through */ 5468 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5469 kvm_mmu_unload(vcpu); 5470 return kvm_skip_emulated_instruction(vcpu); 5471 5472 default: 5473 BUG(); /* We have already checked above that type <= 3 */ 5474 } 5475 } 5476 5477 static int handle_pml_full(struct kvm_vcpu *vcpu) 5478 { 5479 unsigned long exit_qualification; 5480 5481 trace_kvm_pml_full(vcpu->vcpu_id); 5482 5483 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5484 5485 /* 5486 * PML buffer FULL happened while executing iret from NMI, 5487 * "blocked by NMI" bit has to be set before next VM entry. 5488 */ 5489 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5490 enable_vnmi && 5491 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5492 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5493 GUEST_INTR_STATE_NMI); 5494 5495 /* 5496 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5497 * here.., and there's no userspace involvement needed for PML. 5498 */ 5499 return 1; 5500 } 5501 5502 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5503 { 5504 struct vcpu_vmx *vmx = to_vmx(vcpu); 5505 5506 if (!vmx->req_immediate_exit && 5507 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5508 kvm_lapic_expired_hv_timer(vcpu); 5509 5510 return 1; 5511 } 5512 5513 /* 5514 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5515 * are overwritten by nested_vmx_setup() when nested=1. 5516 */ 5517 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5518 { 5519 kvm_queue_exception(vcpu, UD_VECTOR); 5520 return 1; 5521 } 5522 5523 static int handle_encls(struct kvm_vcpu *vcpu) 5524 { 5525 /* 5526 * SGX virtualization is not yet supported. There is no software 5527 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5528 * to prevent the guest from executing ENCLS. 5529 */ 5530 kvm_queue_exception(vcpu, UD_VECTOR); 5531 return 1; 5532 } 5533 5534 /* 5535 * The exit handlers return 1 if the exit was handled fully and guest execution 5536 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5537 * to be done to userspace and return 0. 5538 */ 5539 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5540 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5541 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5542 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5543 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5544 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5545 [EXIT_REASON_CR_ACCESS] = handle_cr, 5546 [EXIT_REASON_DR_ACCESS] = handle_dr, 5547 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5548 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5549 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5550 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5551 [EXIT_REASON_HLT] = kvm_emulate_halt, 5552 [EXIT_REASON_INVD] = handle_invd, 5553 [EXIT_REASON_INVLPG] = handle_invlpg, 5554 [EXIT_REASON_RDPMC] = handle_rdpmc, 5555 [EXIT_REASON_VMCALL] = handle_vmcall, 5556 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5557 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5558 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5559 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5560 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5561 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5562 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5563 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5564 [EXIT_REASON_VMON] = handle_vmx_instruction, 5565 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5566 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5567 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5568 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5569 [EXIT_REASON_WBINVD] = handle_wbinvd, 5570 [EXIT_REASON_XSETBV] = handle_xsetbv, 5571 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5572 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5573 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5574 [EXIT_REASON_LDTR_TR] = handle_desc, 5575 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5576 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5577 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5578 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5579 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5580 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5581 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5582 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5583 [EXIT_REASON_RDRAND] = handle_invalid_op, 5584 [EXIT_REASON_RDSEED] = handle_invalid_op, 5585 [EXIT_REASON_PML_FULL] = handle_pml_full, 5586 [EXIT_REASON_INVPCID] = handle_invpcid, 5587 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5588 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5589 [EXIT_REASON_ENCLS] = handle_encls, 5590 }; 5591 5592 static const int kvm_vmx_max_exit_handlers = 5593 ARRAY_SIZE(kvm_vmx_exit_handlers); 5594 5595 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5596 { 5597 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5598 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5599 } 5600 5601 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5602 { 5603 if (vmx->pml_pg) { 5604 __free_page(vmx->pml_pg); 5605 vmx->pml_pg = NULL; 5606 } 5607 } 5608 5609 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5610 { 5611 struct vcpu_vmx *vmx = to_vmx(vcpu); 5612 u64 *pml_buf; 5613 u16 pml_idx; 5614 5615 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5616 5617 /* Do nothing if PML buffer is empty */ 5618 if (pml_idx == (PML_ENTITY_NUM - 1)) 5619 return; 5620 5621 /* PML index always points to next available PML buffer entity */ 5622 if (pml_idx >= PML_ENTITY_NUM) 5623 pml_idx = 0; 5624 else 5625 pml_idx++; 5626 5627 pml_buf = page_address(vmx->pml_pg); 5628 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5629 u64 gpa; 5630 5631 gpa = pml_buf[pml_idx]; 5632 WARN_ON(gpa & (PAGE_SIZE - 1)); 5633 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5634 } 5635 5636 /* reset PML index */ 5637 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5638 } 5639 5640 /* 5641 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5642 * Called before reporting dirty_bitmap to userspace. 5643 */ 5644 static void kvm_flush_pml_buffers(struct kvm *kvm) 5645 { 5646 int i; 5647 struct kvm_vcpu *vcpu; 5648 /* 5649 * We only need to kick vcpu out of guest mode here, as PML buffer 5650 * is flushed at beginning of all VMEXITs, and it's obvious that only 5651 * vcpus running in guest are possible to have unflushed GPAs in PML 5652 * buffer. 5653 */ 5654 kvm_for_each_vcpu(i, vcpu, kvm) 5655 kvm_vcpu_kick(vcpu); 5656 } 5657 5658 static void vmx_dump_sel(char *name, uint32_t sel) 5659 { 5660 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5661 name, vmcs_read16(sel), 5662 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5663 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5664 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5665 } 5666 5667 static void vmx_dump_dtsel(char *name, uint32_t limit) 5668 { 5669 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5670 name, vmcs_read32(limit), 5671 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5672 } 5673 5674 void dump_vmcs(void) 5675 { 5676 u32 vmentry_ctl, vmexit_ctl; 5677 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5678 unsigned long cr4; 5679 u64 efer; 5680 int i, n; 5681 5682 if (!dump_invalid_vmcs) { 5683 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5684 return; 5685 } 5686 5687 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5688 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5689 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5690 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5691 cr4 = vmcs_readl(GUEST_CR4); 5692 efer = vmcs_read64(GUEST_IA32_EFER); 5693 secondary_exec_control = 0; 5694 if (cpu_has_secondary_exec_ctrls()) 5695 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5696 5697 pr_err("*** Guest State ***\n"); 5698 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5699 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5700 vmcs_readl(CR0_GUEST_HOST_MASK)); 5701 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5702 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5703 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5704 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5705 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5706 { 5707 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5708 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5709 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5710 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5711 } 5712 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5713 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5714 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5715 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5716 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5717 vmcs_readl(GUEST_SYSENTER_ESP), 5718 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5719 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5720 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5721 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5722 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5723 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5724 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5725 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5726 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5727 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5728 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5729 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5730 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5731 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5732 efer, vmcs_read64(GUEST_IA32_PAT)); 5733 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5734 vmcs_read64(GUEST_IA32_DEBUGCTL), 5735 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5736 if (cpu_has_load_perf_global_ctrl() && 5737 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5738 pr_err("PerfGlobCtl = 0x%016llx\n", 5739 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5740 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5741 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5742 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5743 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5744 vmcs_read32(GUEST_ACTIVITY_STATE)); 5745 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5746 pr_err("InterruptStatus = %04x\n", 5747 vmcs_read16(GUEST_INTR_STATUS)); 5748 5749 pr_err("*** Host State ***\n"); 5750 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5751 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5752 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5753 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5754 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5755 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5756 vmcs_read16(HOST_TR_SELECTOR)); 5757 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5758 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5759 vmcs_readl(HOST_TR_BASE)); 5760 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5761 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5762 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5763 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5764 vmcs_readl(HOST_CR4)); 5765 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5766 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5767 vmcs_read32(HOST_IA32_SYSENTER_CS), 5768 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5769 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5770 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5771 vmcs_read64(HOST_IA32_EFER), 5772 vmcs_read64(HOST_IA32_PAT)); 5773 if (cpu_has_load_perf_global_ctrl() && 5774 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5775 pr_err("PerfGlobCtl = 0x%016llx\n", 5776 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5777 5778 pr_err("*** Control State ***\n"); 5779 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5780 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5781 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5782 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5783 vmcs_read32(EXCEPTION_BITMAP), 5784 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5785 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5786 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5787 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5788 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5789 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5790 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5791 vmcs_read32(VM_EXIT_INTR_INFO), 5792 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5793 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5794 pr_err(" reason=%08x qualification=%016lx\n", 5795 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5796 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5797 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5798 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5799 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5800 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5801 pr_err("TSC Multiplier = 0x%016llx\n", 5802 vmcs_read64(TSC_MULTIPLIER)); 5803 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5804 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5805 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5806 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5807 } 5808 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5809 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5810 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5811 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5812 } 5813 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5814 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5815 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5816 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5817 n = vmcs_read32(CR3_TARGET_COUNT); 5818 for (i = 0; i + 1 < n; i += 4) 5819 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5820 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5821 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5822 if (i < n) 5823 pr_err("CR3 target%u=%016lx\n", 5824 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5825 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5826 pr_err("PLE Gap=%08x Window=%08x\n", 5827 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5828 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5829 pr_err("Virtual processor ID = 0x%04x\n", 5830 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5831 } 5832 5833 /* 5834 * The guest has exited. See if we can fix it or if we need userspace 5835 * assistance. 5836 */ 5837 static int vmx_handle_exit(struct kvm_vcpu *vcpu, 5838 enum exit_fastpath_completion exit_fastpath) 5839 { 5840 struct vcpu_vmx *vmx = to_vmx(vcpu); 5841 u32 exit_reason = vmx->exit_reason; 5842 u32 vectoring_info = vmx->idt_vectoring_info; 5843 5844 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5845 5846 /* 5847 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5848 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5849 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5850 * mode as if vcpus is in root mode, the PML buffer must has been 5851 * flushed already. 5852 */ 5853 if (enable_pml) 5854 vmx_flush_pml_buffer(vcpu); 5855 5856 /* If guest state is invalid, start emulating */ 5857 if (vmx->emulation_required) 5858 return handle_invalid_guest_state(vcpu); 5859 5860 if (is_guest_mode(vcpu)) { 5861 /* 5862 * The host physical addresses of some pages of guest memory 5863 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC 5864 * Page). The CPU may write to these pages via their host 5865 * physical address while L2 is running, bypassing any 5866 * address-translation-based dirty tracking (e.g. EPT write 5867 * protection). 5868 * 5869 * Mark them dirty on every exit from L2 to prevent them from 5870 * getting out of sync with dirty tracking. 5871 */ 5872 nested_mark_vmcs12_pages_dirty(vcpu); 5873 5874 if (nested_vmx_exit_reflected(vcpu, exit_reason)) 5875 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5876 } 5877 5878 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5879 dump_vmcs(); 5880 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5881 vcpu->run->fail_entry.hardware_entry_failure_reason 5882 = exit_reason; 5883 return 0; 5884 } 5885 5886 if (unlikely(vmx->fail)) { 5887 dump_vmcs(); 5888 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5889 vcpu->run->fail_entry.hardware_entry_failure_reason 5890 = vmcs_read32(VM_INSTRUCTION_ERROR); 5891 return 0; 5892 } 5893 5894 /* 5895 * Note: 5896 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5897 * delivery event since it indicates guest is accessing MMIO. 5898 * The vm-exit can be triggered again after return to guest that 5899 * will cause infinite loop. 5900 */ 5901 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5902 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5903 exit_reason != EXIT_REASON_EPT_VIOLATION && 5904 exit_reason != EXIT_REASON_PML_FULL && 5905 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5906 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5907 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5908 vcpu->run->internal.ndata = 3; 5909 vcpu->run->internal.data[0] = vectoring_info; 5910 vcpu->run->internal.data[1] = exit_reason; 5911 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5912 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5913 vcpu->run->internal.ndata++; 5914 vcpu->run->internal.data[3] = 5915 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5916 } 5917 return 0; 5918 } 5919 5920 if (unlikely(!enable_vnmi && 5921 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5922 if (vmx_interrupt_allowed(vcpu)) { 5923 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5924 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5925 vcpu->arch.nmi_pending) { 5926 /* 5927 * This CPU don't support us in finding the end of an 5928 * NMI-blocked window if the guest runs with IRQs 5929 * disabled. So we pull the trigger after 1 s of 5930 * futile waiting, but inform the user about this. 5931 */ 5932 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5933 "state on VCPU %d after 1 s timeout\n", 5934 __func__, vcpu->vcpu_id); 5935 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5936 } 5937 } 5938 5939 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { 5940 kvm_skip_emulated_instruction(vcpu); 5941 return 1; 5942 } 5943 5944 if (exit_reason >= kvm_vmx_max_exit_handlers) 5945 goto unexpected_vmexit; 5946 #ifdef CONFIG_RETPOLINE 5947 if (exit_reason == EXIT_REASON_MSR_WRITE) 5948 return kvm_emulate_wrmsr(vcpu); 5949 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5950 return handle_preemption_timer(vcpu); 5951 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 5952 return handle_interrupt_window(vcpu); 5953 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5954 return handle_external_interrupt(vcpu); 5955 else if (exit_reason == EXIT_REASON_HLT) 5956 return kvm_emulate_halt(vcpu); 5957 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5958 return handle_ept_misconfig(vcpu); 5959 #endif 5960 5961 exit_reason = array_index_nospec(exit_reason, 5962 kvm_vmx_max_exit_handlers); 5963 if (!kvm_vmx_exit_handlers[exit_reason]) 5964 goto unexpected_vmexit; 5965 5966 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5967 5968 unexpected_vmexit: 5969 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 5970 dump_vmcs(); 5971 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5972 vcpu->run->internal.suberror = 5973 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5974 vcpu->run->internal.ndata = 1; 5975 vcpu->run->internal.data[0] = exit_reason; 5976 return 0; 5977 } 5978 5979 /* 5980 * Software based L1D cache flush which is used when microcode providing 5981 * the cache control MSR is not loaded. 5982 * 5983 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5984 * flush it is required to read in 64 KiB because the replacement algorithm 5985 * is not exactly LRU. This could be sized at runtime via topology 5986 * information but as all relevant affected CPUs have 32KiB L1D cache size 5987 * there is no point in doing so. 5988 */ 5989 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5990 { 5991 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5992 5993 /* 5994 * This code is only executed when the the flush mode is 'cond' or 5995 * 'always' 5996 */ 5997 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5998 bool flush_l1d; 5999 6000 /* 6001 * Clear the per-vcpu flush bit, it gets set again 6002 * either from vcpu_run() or from one of the unsafe 6003 * VMEXIT handlers. 6004 */ 6005 flush_l1d = vcpu->arch.l1tf_flush_l1d; 6006 vcpu->arch.l1tf_flush_l1d = false; 6007 6008 /* 6009 * Clear the per-cpu flush bit, it gets set again from 6010 * the interrupt handlers. 6011 */ 6012 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 6013 kvm_clear_cpu_l1tf_flush_l1d(); 6014 6015 if (!flush_l1d) 6016 return; 6017 } 6018 6019 vcpu->stat.l1d_flush++; 6020 6021 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 6022 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6023 return; 6024 } 6025 6026 asm volatile( 6027 /* First ensure the pages are in the TLB */ 6028 "xorl %%eax, %%eax\n" 6029 ".Lpopulate_tlb:\n\t" 6030 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6031 "addl $4096, %%eax\n\t" 6032 "cmpl %%eax, %[size]\n\t" 6033 "jne .Lpopulate_tlb\n\t" 6034 "xorl %%eax, %%eax\n\t" 6035 "cpuid\n\t" 6036 /* Now fill the cache */ 6037 "xorl %%eax, %%eax\n" 6038 ".Lfill_cache:\n" 6039 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6040 "addl $64, %%eax\n\t" 6041 "cmpl %%eax, %[size]\n\t" 6042 "jne .Lfill_cache\n\t" 6043 "lfence\n" 6044 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6045 [size] "r" (size) 6046 : "eax", "ebx", "ecx", "edx"); 6047 } 6048 6049 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6050 { 6051 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6052 int tpr_threshold; 6053 6054 if (is_guest_mode(vcpu) && 6055 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6056 return; 6057 6058 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6059 if (is_guest_mode(vcpu)) 6060 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6061 else 6062 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6063 } 6064 6065 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6066 { 6067 struct vcpu_vmx *vmx = to_vmx(vcpu); 6068 u32 sec_exec_control; 6069 6070 if (!lapic_in_kernel(vcpu)) 6071 return; 6072 6073 if (!flexpriority_enabled && 6074 !cpu_has_vmx_virtualize_x2apic_mode()) 6075 return; 6076 6077 /* Postpone execution until vmcs01 is the current VMCS. */ 6078 if (is_guest_mode(vcpu)) { 6079 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6080 return; 6081 } 6082 6083 sec_exec_control = secondary_exec_controls_get(vmx); 6084 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6085 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6086 6087 switch (kvm_get_apic_mode(vcpu)) { 6088 case LAPIC_MODE_INVALID: 6089 WARN_ONCE(true, "Invalid local APIC state"); 6090 case LAPIC_MODE_DISABLED: 6091 break; 6092 case LAPIC_MODE_XAPIC: 6093 if (flexpriority_enabled) { 6094 sec_exec_control |= 6095 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6096 vmx_flush_tlb(vcpu, true); 6097 } 6098 break; 6099 case LAPIC_MODE_X2APIC: 6100 if (cpu_has_vmx_virtualize_x2apic_mode()) 6101 sec_exec_control |= 6102 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6103 break; 6104 } 6105 secondary_exec_controls_set(vmx, sec_exec_control); 6106 6107 vmx_update_msr_bitmap(vcpu); 6108 } 6109 6110 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6111 { 6112 if (!is_guest_mode(vcpu)) { 6113 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6114 vmx_flush_tlb(vcpu, true); 6115 } 6116 } 6117 6118 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6119 { 6120 u16 status; 6121 u8 old; 6122 6123 if (max_isr == -1) 6124 max_isr = 0; 6125 6126 status = vmcs_read16(GUEST_INTR_STATUS); 6127 old = status >> 8; 6128 if (max_isr != old) { 6129 status &= 0xff; 6130 status |= max_isr << 8; 6131 vmcs_write16(GUEST_INTR_STATUS, status); 6132 } 6133 } 6134 6135 static void vmx_set_rvi(int vector) 6136 { 6137 u16 status; 6138 u8 old; 6139 6140 if (vector == -1) 6141 vector = 0; 6142 6143 status = vmcs_read16(GUEST_INTR_STATUS); 6144 old = (u8)status & 0xff; 6145 if ((u8)vector != old) { 6146 status &= ~0xff; 6147 status |= (u8)vector; 6148 vmcs_write16(GUEST_INTR_STATUS, status); 6149 } 6150 } 6151 6152 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6153 { 6154 /* 6155 * When running L2, updating RVI is only relevant when 6156 * vmcs12 virtual-interrupt-delivery enabled. 6157 * However, it can be enabled only when L1 also 6158 * intercepts external-interrupts and in that case 6159 * we should not update vmcs02 RVI but instead intercept 6160 * interrupt. Therefore, do nothing when running L2. 6161 */ 6162 if (!is_guest_mode(vcpu)) 6163 vmx_set_rvi(max_irr); 6164 } 6165 6166 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6167 { 6168 struct vcpu_vmx *vmx = to_vmx(vcpu); 6169 int max_irr; 6170 bool max_irr_updated; 6171 6172 WARN_ON(!vcpu->arch.apicv_active); 6173 if (pi_test_on(&vmx->pi_desc)) { 6174 pi_clear_on(&vmx->pi_desc); 6175 /* 6176 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6177 * But on x86 this is just a compiler barrier anyway. 6178 */ 6179 smp_mb__after_atomic(); 6180 max_irr_updated = 6181 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6182 6183 /* 6184 * If we are running L2 and L1 has a new pending interrupt 6185 * which can be injected, we should re-evaluate 6186 * what should be done with this new L1 interrupt. 6187 * If L1 intercepts external-interrupts, we should 6188 * exit from L2 to L1. Otherwise, interrupt should be 6189 * delivered directly to L2. 6190 */ 6191 if (is_guest_mode(vcpu) && max_irr_updated) { 6192 if (nested_exit_on_intr(vcpu)) 6193 kvm_vcpu_exiting_guest_mode(vcpu); 6194 else 6195 kvm_make_request(KVM_REQ_EVENT, vcpu); 6196 } 6197 } else { 6198 max_irr = kvm_lapic_find_highest_irr(vcpu); 6199 } 6200 vmx_hwapic_irr_update(vcpu, max_irr); 6201 return max_irr; 6202 } 6203 6204 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6205 { 6206 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6207 6208 return pi_test_on(pi_desc) || 6209 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6210 } 6211 6212 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6213 { 6214 if (!kvm_vcpu_apicv_active(vcpu)) 6215 return; 6216 6217 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6218 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6219 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6220 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6221 } 6222 6223 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6224 { 6225 struct vcpu_vmx *vmx = to_vmx(vcpu); 6226 6227 pi_clear_on(&vmx->pi_desc); 6228 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6229 } 6230 6231 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6232 { 6233 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6234 6235 /* if exit due to PF check for async PF */ 6236 if (is_page_fault(vmx->exit_intr_info)) { 6237 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6238 /* Handle machine checks before interrupts are enabled */ 6239 } else if (is_machine_check(vmx->exit_intr_info)) { 6240 kvm_machine_check(); 6241 /* We need to handle NMIs before interrupts are enabled */ 6242 } else if (is_nmi(vmx->exit_intr_info)) { 6243 kvm_before_interrupt(&vmx->vcpu); 6244 asm("int $2"); 6245 kvm_after_interrupt(&vmx->vcpu); 6246 } 6247 } 6248 6249 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6250 { 6251 unsigned int vector; 6252 unsigned long entry; 6253 #ifdef CONFIG_X86_64 6254 unsigned long tmp; 6255 #endif 6256 gate_desc *desc; 6257 u32 intr_info; 6258 6259 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6260 if (WARN_ONCE(!is_external_intr(intr_info), 6261 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6262 return; 6263 6264 vector = intr_info & INTR_INFO_VECTOR_MASK; 6265 desc = (gate_desc *)host_idt_base + vector; 6266 entry = gate_offset(desc); 6267 6268 kvm_before_interrupt(vcpu); 6269 6270 asm volatile( 6271 #ifdef CONFIG_X86_64 6272 "mov %%" _ASM_SP ", %[sp]\n\t" 6273 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6274 "push $%c[ss]\n\t" 6275 "push %[sp]\n\t" 6276 #endif 6277 "pushf\n\t" 6278 __ASM_SIZE(push) " $%c[cs]\n\t" 6279 CALL_NOSPEC 6280 : 6281 #ifdef CONFIG_X86_64 6282 [sp]"=&r"(tmp), 6283 #endif 6284 ASM_CALL_CONSTRAINT 6285 : 6286 [thunk_target]"r"(entry), 6287 [ss]"i"(__KERNEL_DS), 6288 [cs]"i"(__KERNEL_CS) 6289 ); 6290 6291 kvm_after_interrupt(vcpu); 6292 } 6293 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6294 6295 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu, 6296 enum exit_fastpath_completion *exit_fastpath) 6297 { 6298 struct vcpu_vmx *vmx = to_vmx(vcpu); 6299 6300 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6301 handle_external_interrupt_irqoff(vcpu); 6302 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6303 handle_exception_nmi_irqoff(vmx); 6304 else if (!is_guest_mode(vcpu) && 6305 vmx->exit_reason == EXIT_REASON_MSR_WRITE) 6306 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); 6307 } 6308 6309 static bool vmx_has_emulated_msr(int index) 6310 { 6311 switch (index) { 6312 case MSR_IA32_SMBASE: 6313 /* 6314 * We cannot do SMM unless we can run the guest in big 6315 * real mode. 6316 */ 6317 return enable_unrestricted_guest || emulate_invalid_guest_state; 6318 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6319 return nested; 6320 case MSR_AMD64_VIRT_SPEC_CTRL: 6321 /* This is AMD only. */ 6322 return false; 6323 default: 6324 return true; 6325 } 6326 } 6327 6328 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6329 { 6330 u32 exit_intr_info; 6331 bool unblock_nmi; 6332 u8 vector; 6333 bool idtv_info_valid; 6334 6335 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6336 6337 if (enable_vnmi) { 6338 if (vmx->loaded_vmcs->nmi_known_unmasked) 6339 return; 6340 /* 6341 * Can't use vmx->exit_intr_info since we're not sure what 6342 * the exit reason is. 6343 */ 6344 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6345 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6346 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6347 /* 6348 * SDM 3: 27.7.1.2 (September 2008) 6349 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6350 * a guest IRET fault. 6351 * SDM 3: 23.2.2 (September 2008) 6352 * Bit 12 is undefined in any of the following cases: 6353 * If the VM exit sets the valid bit in the IDT-vectoring 6354 * information field. 6355 * If the VM exit is due to a double fault. 6356 */ 6357 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6358 vector != DF_VECTOR && !idtv_info_valid) 6359 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6360 GUEST_INTR_STATE_NMI); 6361 else 6362 vmx->loaded_vmcs->nmi_known_unmasked = 6363 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6364 & GUEST_INTR_STATE_NMI); 6365 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6366 vmx->loaded_vmcs->vnmi_blocked_time += 6367 ktime_to_ns(ktime_sub(ktime_get(), 6368 vmx->loaded_vmcs->entry_time)); 6369 } 6370 6371 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6372 u32 idt_vectoring_info, 6373 int instr_len_field, 6374 int error_code_field) 6375 { 6376 u8 vector; 6377 int type; 6378 bool idtv_info_valid; 6379 6380 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6381 6382 vcpu->arch.nmi_injected = false; 6383 kvm_clear_exception_queue(vcpu); 6384 kvm_clear_interrupt_queue(vcpu); 6385 6386 if (!idtv_info_valid) 6387 return; 6388 6389 kvm_make_request(KVM_REQ_EVENT, vcpu); 6390 6391 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6392 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6393 6394 switch (type) { 6395 case INTR_TYPE_NMI_INTR: 6396 vcpu->arch.nmi_injected = true; 6397 /* 6398 * SDM 3: 27.7.1.2 (September 2008) 6399 * Clear bit "block by NMI" before VM entry if a NMI 6400 * delivery faulted. 6401 */ 6402 vmx_set_nmi_mask(vcpu, false); 6403 break; 6404 case INTR_TYPE_SOFT_EXCEPTION: 6405 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6406 /* fall through */ 6407 case INTR_TYPE_HARD_EXCEPTION: 6408 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6409 u32 err = vmcs_read32(error_code_field); 6410 kvm_requeue_exception_e(vcpu, vector, err); 6411 } else 6412 kvm_requeue_exception(vcpu, vector); 6413 break; 6414 case INTR_TYPE_SOFT_INTR: 6415 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6416 /* fall through */ 6417 case INTR_TYPE_EXT_INTR: 6418 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6419 break; 6420 default: 6421 break; 6422 } 6423 } 6424 6425 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6426 { 6427 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6428 VM_EXIT_INSTRUCTION_LEN, 6429 IDT_VECTORING_ERROR_CODE); 6430 } 6431 6432 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6433 { 6434 __vmx_complete_interrupts(vcpu, 6435 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6436 VM_ENTRY_INSTRUCTION_LEN, 6437 VM_ENTRY_EXCEPTION_ERROR_CODE); 6438 6439 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6440 } 6441 6442 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6443 { 6444 int i, nr_msrs; 6445 struct perf_guest_switch_msr *msrs; 6446 6447 msrs = perf_guest_get_msrs(&nr_msrs); 6448 6449 if (!msrs) 6450 return; 6451 6452 for (i = 0; i < nr_msrs; i++) 6453 if (msrs[i].host == msrs[i].guest) 6454 clear_atomic_switch_msr(vmx, msrs[i].msr); 6455 else 6456 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6457 msrs[i].host, false); 6458 } 6459 6460 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6461 { 6462 u32 host_umwait_control; 6463 6464 if (!vmx_has_waitpkg(vmx)) 6465 return; 6466 6467 host_umwait_control = get_umwait_control_msr(); 6468 6469 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6470 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6471 vmx->msr_ia32_umwait_control, 6472 host_umwait_control, false); 6473 else 6474 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6475 } 6476 6477 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6478 { 6479 struct vcpu_vmx *vmx = to_vmx(vcpu); 6480 u64 tscl; 6481 u32 delta_tsc; 6482 6483 if (vmx->req_immediate_exit) { 6484 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6485 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6486 } else if (vmx->hv_deadline_tsc != -1) { 6487 tscl = rdtsc(); 6488 if (vmx->hv_deadline_tsc > tscl) 6489 /* set_hv_timer ensures the delta fits in 32-bits */ 6490 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6491 cpu_preemption_timer_multi); 6492 else 6493 delta_tsc = 0; 6494 6495 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6496 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6497 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6498 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6499 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6500 } 6501 } 6502 6503 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6504 { 6505 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6506 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6507 vmcs_writel(HOST_RSP, host_rsp); 6508 } 6509 } 6510 6511 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6512 6513 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6514 { 6515 struct vcpu_vmx *vmx = to_vmx(vcpu); 6516 unsigned long cr3, cr4; 6517 6518 /* Record the guest's net vcpu time for enforced NMI injections. */ 6519 if (unlikely(!enable_vnmi && 6520 vmx->loaded_vmcs->soft_vnmi_blocked)) 6521 vmx->loaded_vmcs->entry_time = ktime_get(); 6522 6523 /* Don't enter VMX if guest state is invalid, let the exit handler 6524 start emulation until we arrive back to a valid state */ 6525 if (vmx->emulation_required) 6526 return; 6527 6528 if (vmx->ple_window_dirty) { 6529 vmx->ple_window_dirty = false; 6530 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6531 } 6532 6533 /* 6534 * We did this in prepare_switch_to_guest, because it needs to 6535 * be within srcu_read_lock. 6536 */ 6537 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync); 6538 6539 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6540 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6541 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6542 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6543 6544 cr3 = __get_current_cr3_fast(); 6545 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6546 vmcs_writel(HOST_CR3, cr3); 6547 vmx->loaded_vmcs->host_state.cr3 = cr3; 6548 } 6549 6550 cr4 = cr4_read_shadow(); 6551 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6552 vmcs_writel(HOST_CR4, cr4); 6553 vmx->loaded_vmcs->host_state.cr4 = cr4; 6554 } 6555 6556 /* When single-stepping over STI and MOV SS, we must clear the 6557 * corresponding interruptibility bits in the guest state. Otherwise 6558 * vmentry fails as it then expects bit 14 (BS) in pending debug 6559 * exceptions being set, but that's not correct for the guest debugging 6560 * case. */ 6561 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6562 vmx_set_interrupt_shadow(vcpu, 0); 6563 6564 kvm_load_guest_xsave_state(vcpu); 6565 6566 pt_guest_enter(vmx); 6567 6568 if (vcpu_to_pmu(vcpu)->version) 6569 atomic_switch_perf_msrs(vmx); 6570 atomic_switch_umwait_control_msr(vmx); 6571 6572 if (enable_preemption_timer) 6573 vmx_update_hv_timer(vcpu); 6574 6575 if (lapic_in_kernel(vcpu) && 6576 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6577 kvm_wait_lapic_expire(vcpu); 6578 6579 /* 6580 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6581 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6582 * is no need to worry about the conditional branch over the wrmsr 6583 * being speculatively taken. 6584 */ 6585 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6586 6587 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6588 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6589 vmx_l1d_flush(vcpu); 6590 else if (static_branch_unlikely(&mds_user_clear)) 6591 mds_clear_cpu_buffers(); 6592 6593 if (vcpu->arch.cr2 != read_cr2()) 6594 write_cr2(vcpu->arch.cr2); 6595 6596 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6597 vmx->loaded_vmcs->launched); 6598 6599 vcpu->arch.cr2 = read_cr2(); 6600 6601 /* 6602 * We do not use IBRS in the kernel. If this vCPU has used the 6603 * SPEC_CTRL MSR it may have left it on; save the value and 6604 * turn it off. This is much more efficient than blindly adding 6605 * it to the atomic save/restore list. Especially as the former 6606 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6607 * 6608 * For non-nested case: 6609 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6610 * save it. 6611 * 6612 * For nested case: 6613 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6614 * save it. 6615 */ 6616 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6617 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6618 6619 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6620 6621 /* All fields are clean at this point */ 6622 if (static_branch_unlikely(&enable_evmcs)) 6623 current_evmcs->hv_clean_fields |= 6624 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6625 6626 if (static_branch_unlikely(&enable_evmcs)) 6627 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6628 6629 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6630 if (vmx->host_debugctlmsr) 6631 update_debugctlmsr(vmx->host_debugctlmsr); 6632 6633 #ifndef CONFIG_X86_64 6634 /* 6635 * The sysexit path does not restore ds/es, so we must set them to 6636 * a reasonable value ourselves. 6637 * 6638 * We can't defer this to vmx_prepare_switch_to_host() since that 6639 * function may be executed in interrupt context, which saves and 6640 * restore segments around it, nullifying its effect. 6641 */ 6642 loadsegment(ds, __USER_DS); 6643 loadsegment(es, __USER_DS); 6644 #endif 6645 6646 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6647 | (1 << VCPU_EXREG_RFLAGS) 6648 | (1 << VCPU_EXREG_PDPTR) 6649 | (1 << VCPU_EXREG_SEGMENTS) 6650 | (1 << VCPU_EXREG_CR3)); 6651 vcpu->arch.regs_dirty = 0; 6652 6653 pt_guest_exit(vmx); 6654 6655 kvm_load_host_xsave_state(vcpu); 6656 6657 vmx->nested.nested_run_pending = 0; 6658 vmx->idt_vectoring_info = 0; 6659 6660 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6661 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6662 kvm_machine_check(); 6663 6664 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6665 return; 6666 6667 vmx->loaded_vmcs->launched = 1; 6668 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6669 6670 vmx_recover_nmi_blocking(vmx); 6671 vmx_complete_interrupts(vmx); 6672 } 6673 6674 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6675 { 6676 struct vcpu_vmx *vmx = to_vmx(vcpu); 6677 6678 if (enable_pml) 6679 vmx_destroy_pml_buffer(vmx); 6680 free_vpid(vmx->vpid); 6681 nested_vmx_free_vcpu(vcpu); 6682 free_loaded_vmcs(vmx->loaded_vmcs); 6683 } 6684 6685 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6686 { 6687 struct vcpu_vmx *vmx; 6688 unsigned long *msr_bitmap; 6689 int i, cpu, err; 6690 6691 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6692 vmx = to_vmx(vcpu); 6693 6694 err = -ENOMEM; 6695 6696 vmx->vpid = allocate_vpid(); 6697 6698 /* 6699 * If PML is turned on, failure on enabling PML just results in failure 6700 * of creating the vcpu, therefore we can simplify PML logic (by 6701 * avoiding dealing with cases, such as enabling PML partially on vcpus 6702 * for the guest), etc. 6703 */ 6704 if (enable_pml) { 6705 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6706 if (!vmx->pml_pg) 6707 goto free_vpid; 6708 } 6709 6710 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6711 6712 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6713 u32 index = vmx_msr_index[i]; 6714 u32 data_low, data_high; 6715 int j = vmx->nmsrs; 6716 6717 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6718 continue; 6719 if (wrmsr_safe(index, data_low, data_high) < 0) 6720 continue; 6721 6722 vmx->guest_msrs[j].index = i; 6723 vmx->guest_msrs[j].data = 0; 6724 switch (index) { 6725 case MSR_IA32_TSX_CTRL: 6726 /* 6727 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6728 * let's avoid changing CPUID bits under the host 6729 * kernel's feet. 6730 */ 6731 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6732 break; 6733 default: 6734 vmx->guest_msrs[j].mask = -1ull; 6735 break; 6736 } 6737 ++vmx->nmsrs; 6738 } 6739 6740 err = alloc_loaded_vmcs(&vmx->vmcs01); 6741 if (err < 0) 6742 goto free_pml; 6743 6744 msr_bitmap = vmx->vmcs01.msr_bitmap; 6745 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6746 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6747 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6748 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6749 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6750 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6751 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6752 if (kvm_cstate_in_guest(vcpu->kvm)) { 6753 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6754 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6755 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6756 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6757 } 6758 vmx->msr_bitmap_mode = 0; 6759 6760 vmx->loaded_vmcs = &vmx->vmcs01; 6761 cpu = get_cpu(); 6762 vmx_vcpu_load(vcpu, cpu); 6763 vcpu->cpu = cpu; 6764 init_vmcs(vmx); 6765 vmx_vcpu_put(vcpu); 6766 put_cpu(); 6767 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6768 err = alloc_apic_access_page(vcpu->kvm); 6769 if (err) 6770 goto free_vmcs; 6771 } 6772 6773 if (enable_ept && !enable_unrestricted_guest) { 6774 err = init_rmode_identity_map(vcpu->kvm); 6775 if (err) 6776 goto free_vmcs; 6777 } 6778 6779 if (nested) 6780 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6781 vmx_capability.ept); 6782 else 6783 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6784 6785 vmx->nested.posted_intr_nv = -1; 6786 vmx->nested.current_vmptr = -1ull; 6787 6788 vcpu->arch.microcode_version = 0x100000000ULL; 6789 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6790 6791 /* 6792 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6793 * or POSTED_INTR_WAKEUP_VECTOR. 6794 */ 6795 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6796 vmx->pi_desc.sn = 1; 6797 6798 vmx->ept_pointer = INVALID_PAGE; 6799 6800 return 0; 6801 6802 free_vmcs: 6803 free_loaded_vmcs(vmx->loaded_vmcs); 6804 free_pml: 6805 vmx_destroy_pml_buffer(vmx); 6806 free_vpid: 6807 free_vpid(vmx->vpid); 6808 return err; 6809 } 6810 6811 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6812 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6813 6814 static int vmx_vm_init(struct kvm *kvm) 6815 { 6816 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6817 6818 if (!ple_gap) 6819 kvm->arch.pause_in_guest = true; 6820 6821 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6822 switch (l1tf_mitigation) { 6823 case L1TF_MITIGATION_OFF: 6824 case L1TF_MITIGATION_FLUSH_NOWARN: 6825 /* 'I explicitly don't care' is set */ 6826 break; 6827 case L1TF_MITIGATION_FLUSH: 6828 case L1TF_MITIGATION_FLUSH_NOSMT: 6829 case L1TF_MITIGATION_FULL: 6830 /* 6831 * Warn upon starting the first VM in a potentially 6832 * insecure environment. 6833 */ 6834 if (sched_smt_active()) 6835 pr_warn_once(L1TF_MSG_SMT); 6836 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6837 pr_warn_once(L1TF_MSG_L1D); 6838 break; 6839 case L1TF_MITIGATION_FULL_FORCE: 6840 /* Flush is enforced */ 6841 break; 6842 } 6843 } 6844 kvm_apicv_init(kvm, enable_apicv); 6845 return 0; 6846 } 6847 6848 static int __init vmx_check_processor_compat(void) 6849 { 6850 struct vmcs_config vmcs_conf; 6851 struct vmx_capability vmx_cap; 6852 6853 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6854 !this_cpu_has(X86_FEATURE_VMX)) { 6855 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6856 return -EIO; 6857 } 6858 6859 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6860 return -EIO; 6861 if (nested) 6862 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept); 6863 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6864 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6865 smp_processor_id()); 6866 return -EIO; 6867 } 6868 return 0; 6869 } 6870 6871 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6872 { 6873 u8 cache; 6874 u64 ipat = 0; 6875 6876 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in 6877 * memory aliases with conflicting memory types and sometimes MCEs. 6878 * We have to be careful as to what are honored and when. 6879 * 6880 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to 6881 * UC. The effective memory type is UC or WC depending on guest PAT. 6882 * This was historically the source of MCEs and we want to be 6883 * conservative. 6884 * 6885 * When there is no need to deal with noncoherent DMA (e.g., no VT-d 6886 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The 6887 * EPT memory type is set to WB. The effective memory type is forced 6888 * WB. 6889 * 6890 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The 6891 * EPT memory type is used to emulate guest CD/MTRR. 6892 */ 6893 6894 if (is_mmio) { 6895 cache = MTRR_TYPE_UNCACHABLE; 6896 goto exit; 6897 } 6898 6899 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6900 ipat = VMX_EPT_IPAT_BIT; 6901 cache = MTRR_TYPE_WRBACK; 6902 goto exit; 6903 } 6904 6905 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6906 ipat = VMX_EPT_IPAT_BIT; 6907 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6908 cache = MTRR_TYPE_WRBACK; 6909 else 6910 cache = MTRR_TYPE_UNCACHABLE; 6911 goto exit; 6912 } 6913 6914 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6915 6916 exit: 6917 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6918 } 6919 6920 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6921 { 6922 /* 6923 * These bits in the secondary execution controls field 6924 * are dynamic, the others are mostly based on the hypervisor 6925 * architecture and the guest's CPUID. Do not touch the 6926 * dynamic bits. 6927 */ 6928 u32 mask = 6929 SECONDARY_EXEC_SHADOW_VMCS | 6930 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6931 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6932 SECONDARY_EXEC_DESC; 6933 6934 u32 new_ctl = vmx->secondary_exec_control; 6935 u32 cur_ctl = secondary_exec_controls_get(vmx); 6936 6937 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6938 } 6939 6940 /* 6941 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6942 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6943 */ 6944 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6945 { 6946 struct vcpu_vmx *vmx = to_vmx(vcpu); 6947 struct kvm_cpuid_entry2 *entry; 6948 6949 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6950 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6951 6952 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6953 if (entry && (entry->_reg & (_cpuid_mask))) \ 6954 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6955 } while (0) 6956 6957 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6958 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 6959 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 6960 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 6961 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 6962 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 6963 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 6964 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 6965 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 6966 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 6967 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 6968 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 6969 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 6970 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 6971 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 6972 6973 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6974 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 6975 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 6976 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 6977 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 6978 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 6979 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 6980 6981 #undef cr4_fixed1_update 6982 } 6983 6984 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 6985 { 6986 struct vcpu_vmx *vmx = to_vmx(vcpu); 6987 6988 if (kvm_mpx_supported()) { 6989 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 6990 6991 if (mpx_enabled) { 6992 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 6993 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 6994 } else { 6995 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 6996 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 6997 } 6998 } 6999 } 7000 7001 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7002 { 7003 struct vcpu_vmx *vmx = to_vmx(vcpu); 7004 struct kvm_cpuid_entry2 *best = NULL; 7005 int i; 7006 7007 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7008 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7009 if (!best) 7010 return; 7011 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7012 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7013 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7014 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7015 } 7016 7017 /* Get the number of configurable Address Ranges for filtering */ 7018 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7019 PT_CAP_num_address_ranges); 7020 7021 /* Initialize and clear the no dependency bits */ 7022 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7023 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7024 7025 /* 7026 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7027 * will inject an #GP 7028 */ 7029 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7030 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7031 7032 /* 7033 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7034 * PSBFreq can be set 7035 */ 7036 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7037 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7038 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7039 7040 /* 7041 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7042 * MTCFreq can be set 7043 */ 7044 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7045 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7046 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7047 7048 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7049 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7050 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7051 RTIT_CTL_PTW_EN); 7052 7053 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7054 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7055 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7056 7057 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7058 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7059 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7060 7061 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7062 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7063 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7064 7065 /* unmask address range configure area */ 7066 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7067 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7068 } 7069 7070 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7071 { 7072 struct vcpu_vmx *vmx = to_vmx(vcpu); 7073 7074 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7075 vcpu->arch.xsaves_enabled = false; 7076 7077 if (cpu_has_secondary_exec_ctrls()) { 7078 vmx_compute_secondary_exec_control(vmx); 7079 vmcs_set_secondary_exec_control(vmx); 7080 } 7081 7082 if (nested_vmx_allowed(vcpu)) 7083 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7084 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7085 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7086 else 7087 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7088 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7089 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7090 7091 if (nested_vmx_allowed(vcpu)) { 7092 nested_vmx_cr_fixed1_bits_update(vcpu); 7093 nested_vmx_entry_exit_ctls_update(vcpu); 7094 } 7095 7096 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7097 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7098 update_intel_pt_cfg(vcpu); 7099 7100 if (boot_cpu_has(X86_FEATURE_RTM)) { 7101 struct shared_msr_entry *msr; 7102 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7103 if (msr) { 7104 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7105 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7106 } 7107 } 7108 } 7109 7110 static __init void vmx_set_cpu_caps(void) 7111 { 7112 kvm_set_cpu_caps(); 7113 7114 /* CPUID 0x1 */ 7115 if (nested) 7116 kvm_cpu_cap_set(X86_FEATURE_VMX); 7117 7118 /* CPUID 0x7 */ 7119 if (kvm_mpx_supported()) 7120 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX); 7121 if (cpu_has_vmx_invpcid()) 7122 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID); 7123 if (vmx_pt_mode_is_host_guest()) 7124 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT); 7125 7126 /* PKU is not yet implemented for shadow paging. */ 7127 if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE)) 7128 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU); 7129 7130 if (vmx_umip_emulated()) 7131 kvm_cpu_cap_set(X86_FEATURE_UMIP); 7132 7133 /* CPUID 0xD.1 */ 7134 supported_xss = 0; 7135 if (!vmx_xsaves_supported()) 7136 kvm_cpu_cap_clear(X86_FEATURE_XSAVES); 7137 7138 /* CPUID 0x80000001 */ 7139 if (!cpu_has_vmx_rdtscp()) 7140 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 7141 } 7142 7143 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7144 { 7145 to_vmx(vcpu)->req_immediate_exit = true; 7146 } 7147 7148 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, 7149 struct x86_instruction_info *info) 7150 { 7151 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7152 unsigned short port; 7153 bool intercept; 7154 int size; 7155 7156 if (info->intercept == x86_intercept_in || 7157 info->intercept == x86_intercept_ins) { 7158 port = info->src_val; 7159 size = info->dst_bytes; 7160 } else { 7161 port = info->dst_val; 7162 size = info->src_bytes; 7163 } 7164 7165 /* 7166 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction 7167 * VM-exits depend on the 'unconditional IO exiting' VM-execution 7168 * control. 7169 * 7170 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. 7171 */ 7172 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 7173 intercept = nested_cpu_has(vmcs12, 7174 CPU_BASED_UNCOND_IO_EXITING); 7175 else 7176 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); 7177 7178 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7179 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 7180 } 7181 7182 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7183 struct x86_instruction_info *info, 7184 enum x86_intercept_stage stage, 7185 struct x86_exception *exception) 7186 { 7187 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7188 7189 switch (info->intercept) { 7190 /* 7191 * RDPID causes #UD if disabled through secondary execution controls. 7192 * Because it is marked as EmulateOnUD, we need to intercept it here. 7193 */ 7194 case x86_intercept_rdtscp: 7195 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7196 exception->vector = UD_VECTOR; 7197 exception->error_code_valid = false; 7198 return X86EMUL_PROPAGATE_FAULT; 7199 } 7200 break; 7201 7202 case x86_intercept_in: 7203 case x86_intercept_ins: 7204 case x86_intercept_out: 7205 case x86_intercept_outs: 7206 return vmx_check_intercept_io(vcpu, info); 7207 7208 case x86_intercept_lgdt: 7209 case x86_intercept_lidt: 7210 case x86_intercept_lldt: 7211 case x86_intercept_ltr: 7212 case x86_intercept_sgdt: 7213 case x86_intercept_sidt: 7214 case x86_intercept_sldt: 7215 case x86_intercept_str: 7216 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC)) 7217 return X86EMUL_CONTINUE; 7218 7219 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7220 break; 7221 7222 /* TODO: check more intercepts... */ 7223 default: 7224 break; 7225 } 7226 7227 return X86EMUL_UNHANDLEABLE; 7228 } 7229 7230 #ifdef CONFIG_X86_64 7231 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7232 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7233 u64 divisor, u64 *result) 7234 { 7235 u64 low = a << shift, high = a >> (64 - shift); 7236 7237 /* To avoid the overflow on divq */ 7238 if (high >= divisor) 7239 return 1; 7240 7241 /* Low hold the result, high hold rem which is discarded */ 7242 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7243 "rm" (divisor), "0" (low), "1" (high)); 7244 *result = low; 7245 7246 return 0; 7247 } 7248 7249 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7250 bool *expired) 7251 { 7252 struct vcpu_vmx *vmx; 7253 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7254 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7255 7256 if (kvm_mwait_in_guest(vcpu->kvm) || 7257 kvm_can_post_timer_interrupt(vcpu)) 7258 return -EOPNOTSUPP; 7259 7260 vmx = to_vmx(vcpu); 7261 tscl = rdtsc(); 7262 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7263 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7264 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7265 ktimer->timer_advance_ns); 7266 7267 if (delta_tsc > lapic_timer_advance_cycles) 7268 delta_tsc -= lapic_timer_advance_cycles; 7269 else 7270 delta_tsc = 0; 7271 7272 /* Convert to host delta tsc if tsc scaling is enabled */ 7273 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7274 delta_tsc && u64_shl_div_u64(delta_tsc, 7275 kvm_tsc_scaling_ratio_frac_bits, 7276 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7277 return -ERANGE; 7278 7279 /* 7280 * If the delta tsc can't fit in the 32 bit after the multi shift, 7281 * we can't use the preemption timer. 7282 * It's possible that it fits on later vmentries, but checking 7283 * on every vmentry is costly so we just use an hrtimer. 7284 */ 7285 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7286 return -ERANGE; 7287 7288 vmx->hv_deadline_tsc = tscl + delta_tsc; 7289 *expired = !delta_tsc; 7290 return 0; 7291 } 7292 7293 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7294 { 7295 to_vmx(vcpu)->hv_deadline_tsc = -1; 7296 } 7297 #endif 7298 7299 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7300 { 7301 if (!kvm_pause_in_guest(vcpu->kvm)) 7302 shrink_ple_window(vcpu); 7303 } 7304 7305 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7306 struct kvm_memory_slot *slot) 7307 { 7308 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 7309 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7310 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7311 } 7312 7313 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7314 struct kvm_memory_slot *slot) 7315 { 7316 kvm_mmu_slot_set_dirty(kvm, slot); 7317 } 7318 7319 static void vmx_flush_log_dirty(struct kvm *kvm) 7320 { 7321 kvm_flush_pml_buffers(kvm); 7322 } 7323 7324 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7325 { 7326 struct vmcs12 *vmcs12; 7327 struct vcpu_vmx *vmx = to_vmx(vcpu); 7328 gpa_t gpa, dst; 7329 7330 if (is_guest_mode(vcpu)) { 7331 WARN_ON_ONCE(vmx->nested.pml_full); 7332 7333 /* 7334 * Check if PML is enabled for the nested guest. 7335 * Whether eptp bit 6 is set is already checked 7336 * as part of A/D emulation. 7337 */ 7338 vmcs12 = get_vmcs12(vcpu); 7339 if (!nested_cpu_has_pml(vmcs12)) 7340 return 0; 7341 7342 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7343 vmx->nested.pml_full = true; 7344 return 1; 7345 } 7346 7347 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7348 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7349 7350 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7351 offset_in_page(dst), sizeof(gpa))) 7352 return 0; 7353 7354 vmcs12->guest_pml_index--; 7355 } 7356 7357 return 0; 7358 } 7359 7360 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7361 struct kvm_memory_slot *memslot, 7362 gfn_t offset, unsigned long mask) 7363 { 7364 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7365 } 7366 7367 static void __pi_post_block(struct kvm_vcpu *vcpu) 7368 { 7369 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7370 struct pi_desc old, new; 7371 unsigned int dest; 7372 7373 do { 7374 old.control = new.control = pi_desc->control; 7375 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7376 "Wakeup handler not enabled while the VCPU is blocked\n"); 7377 7378 dest = cpu_physical_id(vcpu->cpu); 7379 7380 if (x2apic_enabled()) 7381 new.ndst = dest; 7382 else 7383 new.ndst = (dest << 8) & 0xFF00; 7384 7385 /* set 'NV' to 'notification vector' */ 7386 new.nv = POSTED_INTR_VECTOR; 7387 } while (cmpxchg64(&pi_desc->control, old.control, 7388 new.control) != old.control); 7389 7390 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7391 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7392 list_del(&vcpu->blocked_vcpu_list); 7393 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7394 vcpu->pre_pcpu = -1; 7395 } 7396 } 7397 7398 /* 7399 * This routine does the following things for vCPU which is going 7400 * to be blocked if VT-d PI is enabled. 7401 * - Store the vCPU to the wakeup list, so when interrupts happen 7402 * we can find the right vCPU to wake up. 7403 * - Change the Posted-interrupt descriptor as below: 7404 * 'NDST' <-- vcpu->pre_pcpu 7405 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7406 * - If 'ON' is set during this process, which means at least one 7407 * interrupt is posted for this vCPU, we cannot block it, in 7408 * this case, return 1, otherwise, return 0. 7409 * 7410 */ 7411 static int pi_pre_block(struct kvm_vcpu *vcpu) 7412 { 7413 unsigned int dest; 7414 struct pi_desc old, new; 7415 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7416 7417 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7418 !irq_remapping_cap(IRQ_POSTING_CAP) || 7419 !kvm_vcpu_apicv_active(vcpu)) 7420 return 0; 7421 7422 WARN_ON(irqs_disabled()); 7423 local_irq_disable(); 7424 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7425 vcpu->pre_pcpu = vcpu->cpu; 7426 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7427 list_add_tail(&vcpu->blocked_vcpu_list, 7428 &per_cpu(blocked_vcpu_on_cpu, 7429 vcpu->pre_pcpu)); 7430 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7431 } 7432 7433 do { 7434 old.control = new.control = pi_desc->control; 7435 7436 WARN((pi_desc->sn == 1), 7437 "Warning: SN field of posted-interrupts " 7438 "is set before blocking\n"); 7439 7440 /* 7441 * Since vCPU can be preempted during this process, 7442 * vcpu->cpu could be different with pre_pcpu, we 7443 * need to set pre_pcpu as the destination of wakeup 7444 * notification event, then we can find the right vCPU 7445 * to wakeup in wakeup handler if interrupts happen 7446 * when the vCPU is in blocked state. 7447 */ 7448 dest = cpu_physical_id(vcpu->pre_pcpu); 7449 7450 if (x2apic_enabled()) 7451 new.ndst = dest; 7452 else 7453 new.ndst = (dest << 8) & 0xFF00; 7454 7455 /* set 'NV' to 'wakeup vector' */ 7456 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7457 } while (cmpxchg64(&pi_desc->control, old.control, 7458 new.control) != old.control); 7459 7460 /* We should not block the vCPU if an interrupt is posted for it. */ 7461 if (pi_test_on(pi_desc) == 1) 7462 __pi_post_block(vcpu); 7463 7464 local_irq_enable(); 7465 return (vcpu->pre_pcpu == -1); 7466 } 7467 7468 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7469 { 7470 if (pi_pre_block(vcpu)) 7471 return 1; 7472 7473 if (kvm_lapic_hv_timer_in_use(vcpu)) 7474 kvm_lapic_switch_to_sw_timer(vcpu); 7475 7476 return 0; 7477 } 7478 7479 static void pi_post_block(struct kvm_vcpu *vcpu) 7480 { 7481 if (vcpu->pre_pcpu == -1) 7482 return; 7483 7484 WARN_ON(irqs_disabled()); 7485 local_irq_disable(); 7486 __pi_post_block(vcpu); 7487 local_irq_enable(); 7488 } 7489 7490 static void vmx_post_block(struct kvm_vcpu *vcpu) 7491 { 7492 if (kvm_x86_ops.set_hv_timer) 7493 kvm_lapic_switch_to_hv_timer(vcpu); 7494 7495 pi_post_block(vcpu); 7496 } 7497 7498 /* 7499 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7500 * 7501 * @kvm: kvm 7502 * @host_irq: host irq of the interrupt 7503 * @guest_irq: gsi of the interrupt 7504 * @set: set or unset PI 7505 * returns 0 on success, < 0 on failure 7506 */ 7507 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7508 uint32_t guest_irq, bool set) 7509 { 7510 struct kvm_kernel_irq_routing_entry *e; 7511 struct kvm_irq_routing_table *irq_rt; 7512 struct kvm_lapic_irq irq; 7513 struct kvm_vcpu *vcpu; 7514 struct vcpu_data vcpu_info; 7515 int idx, ret = 0; 7516 7517 if (!kvm_arch_has_assigned_device(kvm) || 7518 !irq_remapping_cap(IRQ_POSTING_CAP) || 7519 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7520 return 0; 7521 7522 idx = srcu_read_lock(&kvm->irq_srcu); 7523 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7524 if (guest_irq >= irq_rt->nr_rt_entries || 7525 hlist_empty(&irq_rt->map[guest_irq])) { 7526 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7527 guest_irq, irq_rt->nr_rt_entries); 7528 goto out; 7529 } 7530 7531 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7532 if (e->type != KVM_IRQ_ROUTING_MSI) 7533 continue; 7534 /* 7535 * VT-d PI cannot support posting multicast/broadcast 7536 * interrupts to a vCPU, we still use interrupt remapping 7537 * for these kind of interrupts. 7538 * 7539 * For lowest-priority interrupts, we only support 7540 * those with single CPU as the destination, e.g. user 7541 * configures the interrupts via /proc/irq or uses 7542 * irqbalance to make the interrupts single-CPU. 7543 * 7544 * We will support full lowest-priority interrupt later. 7545 * 7546 * In addition, we can only inject generic interrupts using 7547 * the PI mechanism, refuse to route others through it. 7548 */ 7549 7550 kvm_set_msi_irq(kvm, e, &irq); 7551 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7552 !kvm_irq_is_postable(&irq)) { 7553 /* 7554 * Make sure the IRTE is in remapped mode if 7555 * we don't handle it in posted mode. 7556 */ 7557 ret = irq_set_vcpu_affinity(host_irq, NULL); 7558 if (ret < 0) { 7559 printk(KERN_INFO 7560 "failed to back to remapped mode, irq: %u\n", 7561 host_irq); 7562 goto out; 7563 } 7564 7565 continue; 7566 } 7567 7568 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7569 vcpu_info.vector = irq.vector; 7570 7571 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7572 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7573 7574 if (set) 7575 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7576 else 7577 ret = irq_set_vcpu_affinity(host_irq, NULL); 7578 7579 if (ret < 0) { 7580 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7581 __func__); 7582 goto out; 7583 } 7584 } 7585 7586 ret = 0; 7587 out: 7588 srcu_read_unlock(&kvm->irq_srcu, idx); 7589 return ret; 7590 } 7591 7592 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7593 { 7594 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7595 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7596 FEAT_CTL_LMCE_ENABLED; 7597 else 7598 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7599 ~FEAT_CTL_LMCE_ENABLED; 7600 } 7601 7602 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7603 { 7604 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7605 if (to_vmx(vcpu)->nested.nested_run_pending) 7606 return 0; 7607 return 1; 7608 } 7609 7610 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7611 { 7612 struct vcpu_vmx *vmx = to_vmx(vcpu); 7613 7614 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7615 if (vmx->nested.smm.guest_mode) 7616 nested_vmx_vmexit(vcpu, -1, 0, 0); 7617 7618 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7619 vmx->nested.vmxon = false; 7620 vmx_clear_hlt(vcpu); 7621 return 0; 7622 } 7623 7624 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7625 { 7626 struct vcpu_vmx *vmx = to_vmx(vcpu); 7627 int ret; 7628 7629 if (vmx->nested.smm.vmxon) { 7630 vmx->nested.vmxon = true; 7631 vmx->nested.smm.vmxon = false; 7632 } 7633 7634 if (vmx->nested.smm.guest_mode) { 7635 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7636 if (ret) 7637 return ret; 7638 7639 vmx->nested.smm.guest_mode = false; 7640 } 7641 return 0; 7642 } 7643 7644 static int enable_smi_window(struct kvm_vcpu *vcpu) 7645 { 7646 return 0; 7647 } 7648 7649 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7650 { 7651 return false; 7652 } 7653 7654 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7655 { 7656 return to_vmx(vcpu)->nested.vmxon; 7657 } 7658 7659 static void hardware_unsetup(void) 7660 { 7661 if (nested) 7662 nested_vmx_hardware_unsetup(); 7663 7664 free_kvm_area(); 7665 } 7666 7667 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7668 { 7669 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7670 BIT(APICV_INHIBIT_REASON_HYPERV); 7671 7672 return supported & BIT(bit); 7673 } 7674 7675 static struct kvm_x86_ops vmx_x86_ops __initdata = { 7676 .hardware_unsetup = hardware_unsetup, 7677 7678 .hardware_enable = hardware_enable, 7679 .hardware_disable = hardware_disable, 7680 .cpu_has_accelerated_tpr = report_flexpriority, 7681 .has_emulated_msr = vmx_has_emulated_msr, 7682 7683 .vm_size = sizeof(struct kvm_vmx), 7684 .vm_init = vmx_vm_init, 7685 7686 .vcpu_create = vmx_create_vcpu, 7687 .vcpu_free = vmx_free_vcpu, 7688 .vcpu_reset = vmx_vcpu_reset, 7689 7690 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7691 .vcpu_load = vmx_vcpu_load, 7692 .vcpu_put = vmx_vcpu_put, 7693 7694 .update_bp_intercept = update_exception_bitmap, 7695 .get_msr_feature = vmx_get_msr_feature, 7696 .get_msr = vmx_get_msr, 7697 .set_msr = vmx_set_msr, 7698 .get_segment_base = vmx_get_segment_base, 7699 .get_segment = vmx_get_segment, 7700 .set_segment = vmx_set_segment, 7701 .get_cpl = vmx_get_cpl, 7702 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7703 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7704 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7705 .set_cr0 = vmx_set_cr0, 7706 .set_cr4 = vmx_set_cr4, 7707 .set_efer = vmx_set_efer, 7708 .get_idt = vmx_get_idt, 7709 .set_idt = vmx_set_idt, 7710 .get_gdt = vmx_get_gdt, 7711 .set_gdt = vmx_set_gdt, 7712 .set_dr7 = vmx_set_dr7, 7713 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7714 .cache_reg = vmx_cache_reg, 7715 .get_rflags = vmx_get_rflags, 7716 .set_rflags = vmx_set_rflags, 7717 7718 .tlb_flush = vmx_flush_tlb, 7719 .tlb_flush_gva = vmx_flush_tlb_gva, 7720 7721 .run = vmx_vcpu_run, 7722 .handle_exit = vmx_handle_exit, 7723 .skip_emulated_instruction = vmx_skip_emulated_instruction, 7724 .update_emulated_instruction = vmx_update_emulated_instruction, 7725 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7726 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7727 .patch_hypercall = vmx_patch_hypercall, 7728 .set_irq = vmx_inject_irq, 7729 .set_nmi = vmx_inject_nmi, 7730 .queue_exception = vmx_queue_exception, 7731 .cancel_injection = vmx_cancel_injection, 7732 .interrupt_allowed = vmx_interrupt_allowed, 7733 .nmi_allowed = vmx_nmi_allowed, 7734 .get_nmi_mask = vmx_get_nmi_mask, 7735 .set_nmi_mask = vmx_set_nmi_mask, 7736 .enable_nmi_window = enable_nmi_window, 7737 .enable_irq_window = enable_irq_window, 7738 .update_cr8_intercept = update_cr8_intercept, 7739 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7740 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7741 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7742 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7743 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7744 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7745 .hwapic_irr_update = vmx_hwapic_irr_update, 7746 .hwapic_isr_update = vmx_hwapic_isr_update, 7747 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7748 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7749 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7750 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7751 7752 .set_tss_addr = vmx_set_tss_addr, 7753 .set_identity_map_addr = vmx_set_identity_map_addr, 7754 .get_tdp_level = get_ept_level, 7755 .get_mt_mask = vmx_get_mt_mask, 7756 7757 .get_exit_info = vmx_get_exit_info, 7758 7759 .cpuid_update = vmx_cpuid_update, 7760 7761 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7762 7763 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7764 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7765 7766 .load_mmu_pgd = vmx_load_mmu_pgd, 7767 7768 .check_intercept = vmx_check_intercept, 7769 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7770 7771 .request_immediate_exit = vmx_request_immediate_exit, 7772 7773 .sched_in = vmx_sched_in, 7774 7775 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7776 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7777 .flush_log_dirty = vmx_flush_log_dirty, 7778 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7779 .write_log_dirty = vmx_write_pml_buffer, 7780 7781 .pre_block = vmx_pre_block, 7782 .post_block = vmx_post_block, 7783 7784 .pmu_ops = &intel_pmu_ops, 7785 7786 .update_pi_irte = vmx_update_pi_irte, 7787 7788 #ifdef CONFIG_X86_64 7789 .set_hv_timer = vmx_set_hv_timer, 7790 .cancel_hv_timer = vmx_cancel_hv_timer, 7791 #endif 7792 7793 .setup_mce = vmx_setup_mce, 7794 7795 .smi_allowed = vmx_smi_allowed, 7796 .pre_enter_smm = vmx_pre_enter_smm, 7797 .pre_leave_smm = vmx_pre_leave_smm, 7798 .enable_smi_window = enable_smi_window, 7799 7800 .check_nested_events = NULL, 7801 .get_nested_state = NULL, 7802 .set_nested_state = NULL, 7803 .get_vmcs12_pages = NULL, 7804 .nested_enable_evmcs = NULL, 7805 .nested_get_evmcs_version = NULL, 7806 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7807 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7808 }; 7809 7810 static __init int hardware_setup(void) 7811 { 7812 unsigned long host_bndcfgs; 7813 struct desc_ptr dt; 7814 int r, i, ept_lpage_level; 7815 7816 store_idt(&dt); 7817 host_idt_base = dt.address; 7818 7819 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7820 kvm_define_shared_msr(i, vmx_msr_index[i]); 7821 7822 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7823 return -EIO; 7824 7825 if (boot_cpu_has(X86_FEATURE_NX)) 7826 kvm_enable_efer_bits(EFER_NX); 7827 7828 if (boot_cpu_has(X86_FEATURE_MPX)) { 7829 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7830 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7831 } 7832 7833 if (!cpu_has_vmx_mpx()) 7834 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | 7835 XFEATURE_MASK_BNDCSR); 7836 7837 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7838 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7839 enable_vpid = 0; 7840 7841 if (!cpu_has_vmx_ept() || 7842 !cpu_has_vmx_ept_4levels() || 7843 !cpu_has_vmx_ept_mt_wb() || 7844 !cpu_has_vmx_invept_global()) 7845 enable_ept = 0; 7846 7847 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7848 enable_ept_ad_bits = 0; 7849 7850 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7851 enable_unrestricted_guest = 0; 7852 7853 if (!cpu_has_vmx_flexpriority()) 7854 flexpriority_enabled = 0; 7855 7856 if (!cpu_has_virtual_nmis()) 7857 enable_vnmi = 0; 7858 7859 /* 7860 * set_apic_access_page_addr() is used to reload apic access 7861 * page upon invalidation. No need to do anything if not 7862 * using the APIC_ACCESS_ADDR VMCS field. 7863 */ 7864 if (!flexpriority_enabled) 7865 vmx_x86_ops.set_apic_access_page_addr = NULL; 7866 7867 if (!cpu_has_vmx_tpr_shadow()) 7868 vmx_x86_ops.update_cr8_intercept = NULL; 7869 7870 #if IS_ENABLED(CONFIG_HYPERV) 7871 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7872 && enable_ept) { 7873 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb; 7874 vmx_x86_ops.tlb_remote_flush_with_range = 7875 hv_remote_flush_tlb_with_range; 7876 } 7877 #endif 7878 7879 if (!cpu_has_vmx_ple()) { 7880 ple_gap = 0; 7881 ple_window = 0; 7882 ple_window_grow = 0; 7883 ple_window_max = 0; 7884 ple_window_shrink = 0; 7885 } 7886 7887 if (!cpu_has_vmx_apicv()) { 7888 enable_apicv = 0; 7889 vmx_x86_ops.sync_pir_to_irr = NULL; 7890 } 7891 7892 if (cpu_has_vmx_tsc_scaling()) { 7893 kvm_has_tsc_control = true; 7894 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7895 kvm_tsc_scaling_ratio_frac_bits = 48; 7896 } 7897 7898 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7899 7900 if (enable_ept) 7901 vmx_enable_tdp(); 7902 7903 if (!enable_ept) 7904 ept_lpage_level = 0; 7905 else if (cpu_has_vmx_ept_1g_page()) 7906 ept_lpage_level = PT_PDPE_LEVEL; 7907 else if (cpu_has_vmx_ept_2m_page()) 7908 ept_lpage_level = PT_DIRECTORY_LEVEL; 7909 else 7910 ept_lpage_level = PT_PAGE_TABLE_LEVEL; 7911 kvm_configure_mmu(enable_ept, ept_lpage_level); 7912 7913 /* 7914 * Only enable PML when hardware supports PML feature, and both EPT 7915 * and EPT A/D bit features are enabled -- PML depends on them to work. 7916 */ 7917 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7918 enable_pml = 0; 7919 7920 if (!enable_pml) { 7921 vmx_x86_ops.slot_enable_log_dirty = NULL; 7922 vmx_x86_ops.slot_disable_log_dirty = NULL; 7923 vmx_x86_ops.flush_log_dirty = NULL; 7924 vmx_x86_ops.enable_log_dirty_pt_masked = NULL; 7925 } 7926 7927 if (!cpu_has_vmx_preemption_timer()) 7928 enable_preemption_timer = false; 7929 7930 if (enable_preemption_timer) { 7931 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7932 u64 vmx_msr; 7933 7934 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7935 cpu_preemption_timer_multi = 7936 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7937 7938 if (tsc_khz) 7939 use_timer_freq = (u64)tsc_khz * 1000; 7940 use_timer_freq >>= cpu_preemption_timer_multi; 7941 7942 /* 7943 * KVM "disables" the preemption timer by setting it to its max 7944 * value. Don't use the timer if it might cause spurious exits 7945 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7946 */ 7947 if (use_timer_freq > 0xffffffffu / 10) 7948 enable_preemption_timer = false; 7949 } 7950 7951 if (!enable_preemption_timer) { 7952 vmx_x86_ops.set_hv_timer = NULL; 7953 vmx_x86_ops.cancel_hv_timer = NULL; 7954 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit; 7955 } 7956 7957 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7958 7959 kvm_mce_cap_supported |= MCG_LMCE_P; 7960 7961 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7962 return -EINVAL; 7963 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7964 pt_mode = PT_MODE_SYSTEM; 7965 7966 if (nested) { 7967 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7968 vmx_capability.ept); 7969 7970 r = nested_vmx_hardware_setup(&vmx_x86_ops, 7971 kvm_vmx_exit_handlers); 7972 if (r) 7973 return r; 7974 } 7975 7976 vmx_set_cpu_caps(); 7977 7978 r = alloc_kvm_area(); 7979 if (r) 7980 nested_vmx_hardware_unsetup(); 7981 return r; 7982 } 7983 7984 static struct kvm_x86_init_ops vmx_init_ops __initdata = { 7985 .cpu_has_kvm_support = cpu_has_kvm_support, 7986 .disabled_by_bios = vmx_disabled_by_bios, 7987 .check_processor_compatibility = vmx_check_processor_compat, 7988 .hardware_setup = hardware_setup, 7989 7990 .runtime_ops = &vmx_x86_ops, 7991 }; 7992 7993 static void vmx_cleanup_l1d_flush(void) 7994 { 7995 if (vmx_l1d_flush_pages) { 7996 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7997 vmx_l1d_flush_pages = NULL; 7998 } 7999 /* Restore state so sysfs ignores VMX */ 8000 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 8001 } 8002 8003 static void vmx_exit(void) 8004 { 8005 #ifdef CONFIG_KEXEC_CORE 8006 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 8007 synchronize_rcu(); 8008 #endif 8009 8010 kvm_exit(); 8011 8012 #if IS_ENABLED(CONFIG_HYPERV) 8013 if (static_branch_unlikely(&enable_evmcs)) { 8014 int cpu; 8015 struct hv_vp_assist_page *vp_ap; 8016 /* 8017 * Reset everything to support using non-enlightened VMCS 8018 * access later (e.g. when we reload the module with 8019 * enlightened_vmcs=0) 8020 */ 8021 for_each_online_cpu(cpu) { 8022 vp_ap = hv_get_vp_assist_page(cpu); 8023 8024 if (!vp_ap) 8025 continue; 8026 8027 vp_ap->nested_control.features.directhypercall = 0; 8028 vp_ap->current_nested_vmcs = 0; 8029 vp_ap->enlighten_vmentry = 0; 8030 } 8031 8032 static_branch_disable(&enable_evmcs); 8033 } 8034 #endif 8035 vmx_cleanup_l1d_flush(); 8036 } 8037 module_exit(vmx_exit); 8038 8039 static int __init vmx_init(void) 8040 { 8041 int r, cpu; 8042 8043 #if IS_ENABLED(CONFIG_HYPERV) 8044 /* 8045 * Enlightened VMCS usage should be recommended and the host needs 8046 * to support eVMCS v1 or above. We can also disable eVMCS support 8047 * with module parameter. 8048 */ 8049 if (enlightened_vmcs && 8050 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 8051 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 8052 KVM_EVMCS_VERSION) { 8053 int cpu; 8054 8055 /* Check that we have assist pages on all online CPUs */ 8056 for_each_online_cpu(cpu) { 8057 if (!hv_get_vp_assist_page(cpu)) { 8058 enlightened_vmcs = false; 8059 break; 8060 } 8061 } 8062 8063 if (enlightened_vmcs) { 8064 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 8065 static_branch_enable(&enable_evmcs); 8066 } 8067 8068 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 8069 vmx_x86_ops.enable_direct_tlbflush 8070 = hv_enable_direct_tlbflush; 8071 8072 } else { 8073 enlightened_vmcs = false; 8074 } 8075 #endif 8076 8077 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx), 8078 __alignof__(struct vcpu_vmx), THIS_MODULE); 8079 if (r) 8080 return r; 8081 8082 /* 8083 * Must be called after kvm_init() so enable_ept is properly set 8084 * up. Hand the parameter mitigation value in which was stored in 8085 * the pre module init parser. If no parameter was given, it will 8086 * contain 'auto' which will be turned into the default 'cond' 8087 * mitigation mode. 8088 */ 8089 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 8090 if (r) { 8091 vmx_exit(); 8092 return r; 8093 } 8094 8095 for_each_possible_cpu(cpu) { 8096 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 8097 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 8098 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 8099 } 8100 8101 #ifdef CONFIG_KEXEC_CORE 8102 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 8103 crash_vmclear_local_loaded_vmcss); 8104 #endif 8105 vmx_check_vmcs12_offsets(); 8106 8107 return 0; 8108 } 8109 module_init(vmx_init); 8110