xref: /openbmc/linux/arch/x86/kvm/vmx/vmx.c (revision 45fe9262)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Kernel-based Virtual Machine driver for Linux
4  *
5  * This module enables machines with Intel VT-x extensions to run virtual
6  * machines without emulation or binary translation.
7  *
8  * Copyright (C) 2006 Qumranet, Inc.
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  */
15 
16 #include <linux/highmem.h>
17 #include <linux/hrtimer.h>
18 #include <linux/kernel.h>
19 #include <linux/kvm_host.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/mm.h>
24 #include <linux/objtool.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
31 
32 #include <asm/apic.h>
33 #include <asm/asm.h>
34 #include <asm/cpu.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
37 #include <asm/desc.h>
38 #include <asm/fpu/internal.h>
39 #include <asm/io.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/kexec.h>
42 #include <asm/perf_event.h>
43 #include <asm/mmu_context.h>
44 #include <asm/mshyperv.h>
45 #include <asm/mwait.h>
46 #include <asm/spec-ctrl.h>
47 #include <asm/virtext.h>
48 #include <asm/vmx.h>
49 
50 #include "capabilities.h"
51 #include "cpuid.h"
52 #include "evmcs.h"
53 #include "irq.h"
54 #include "kvm_cache_regs.h"
55 #include "lapic.h"
56 #include "mmu.h"
57 #include "nested.h"
58 #include "pmu.h"
59 #include "trace.h"
60 #include "vmcs.h"
61 #include "vmcs12.h"
62 #include "vmx.h"
63 #include "x86.h"
64 
65 MODULE_AUTHOR("Qumranet");
66 MODULE_LICENSE("GPL");
67 
68 #ifdef MODULE
69 static const struct x86_cpu_id vmx_cpu_id[] = {
70 	X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL),
71 	{}
72 };
73 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
74 #endif
75 
76 bool __read_mostly enable_vpid = 1;
77 module_param_named(vpid, enable_vpid, bool, 0444);
78 
79 static bool __read_mostly enable_vnmi = 1;
80 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
81 
82 bool __read_mostly flexpriority_enabled = 1;
83 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
84 
85 bool __read_mostly enable_ept = 1;
86 module_param_named(ept, enable_ept, bool, S_IRUGO);
87 
88 bool __read_mostly enable_unrestricted_guest = 1;
89 module_param_named(unrestricted_guest,
90 			enable_unrestricted_guest, bool, S_IRUGO);
91 
92 bool __read_mostly enable_ept_ad_bits = 1;
93 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
94 
95 static bool __read_mostly emulate_invalid_guest_state = true;
96 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
97 
98 static bool __read_mostly fasteoi = 1;
99 module_param(fasteoi, bool, S_IRUGO);
100 
101 bool __read_mostly enable_apicv = 1;
102 module_param(enable_apicv, bool, S_IRUGO);
103 
104 /*
105  * If nested=1, nested virtualization is supported, i.e., guests may use
106  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
107  * use VMX instructions.
108  */
109 static bool __read_mostly nested = 1;
110 module_param(nested, bool, S_IRUGO);
111 
112 bool __read_mostly enable_pml = 1;
113 module_param_named(pml, enable_pml, bool, S_IRUGO);
114 
115 static bool __read_mostly dump_invalid_vmcs = 0;
116 module_param(dump_invalid_vmcs, bool, 0644);
117 
118 #define MSR_BITMAP_MODE_X2APIC		1
119 #define MSR_BITMAP_MODE_X2APIC_APICV	2
120 
121 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
122 
123 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
124 static int __read_mostly cpu_preemption_timer_multi;
125 static bool __read_mostly enable_preemption_timer = 1;
126 #ifdef CONFIG_X86_64
127 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
128 #endif
129 
130 extern bool __read_mostly allow_smaller_maxphyaddr;
131 module_param(allow_smaller_maxphyaddr, bool, S_IRUGO);
132 
133 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
134 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
135 #define KVM_VM_CR0_ALWAYS_ON				\
136 	(KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | 	\
137 	 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
138 
139 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
140 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
141 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 
143 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 
145 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
146 	RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
147 	RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
148 	RTIT_STATUS_BYTECNT))
149 
150 /*
151  * List of MSRs that can be directly passed to the guest.
152  * In addition to these x2apic and PT MSRs are handled specially.
153  */
154 static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = {
155 	MSR_IA32_SPEC_CTRL,
156 	MSR_IA32_PRED_CMD,
157 	MSR_IA32_TSC,
158 	MSR_FS_BASE,
159 	MSR_GS_BASE,
160 	MSR_KERNEL_GS_BASE,
161 	MSR_IA32_SYSENTER_CS,
162 	MSR_IA32_SYSENTER_ESP,
163 	MSR_IA32_SYSENTER_EIP,
164 	MSR_CORE_C1_RES,
165 	MSR_CORE_C3_RESIDENCY,
166 	MSR_CORE_C6_RESIDENCY,
167 	MSR_CORE_C7_RESIDENCY,
168 };
169 
170 /*
171  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
172  * ple_gap:    upper bound on the amount of time between two successive
173  *             executions of PAUSE in a loop. Also indicate if ple enabled.
174  *             According to test, this time is usually smaller than 128 cycles.
175  * ple_window: upper bound on the amount of time a guest is allowed to execute
176  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
177  *             less than 2^12 cycles
178  * Time is measured based on a counter that runs at the same rate as the TSC,
179  * refer SDM volume 3b section 21.6.13 & 22.1.3.
180  */
181 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
182 module_param(ple_gap, uint, 0444);
183 
184 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
185 module_param(ple_window, uint, 0444);
186 
187 /* Default doubles per-vcpu window every exit. */
188 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
189 module_param(ple_window_grow, uint, 0444);
190 
191 /* Default resets per-vcpu window every exit to ple_window. */
192 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
193 module_param(ple_window_shrink, uint, 0444);
194 
195 /* Default is to compute the maximum so we can never overflow. */
196 static unsigned int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
197 module_param(ple_window_max, uint, 0444);
198 
199 /* Default is SYSTEM mode, 1 for host-guest mode */
200 int __read_mostly pt_mode = PT_MODE_SYSTEM;
201 module_param(pt_mode, int, S_IRUGO);
202 
203 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
204 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
205 static DEFINE_MUTEX(vmx_l1d_flush_mutex);
206 
207 /* Storage for pre module init parameter parsing */
208 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
209 
210 static const struct {
211 	const char *option;
212 	bool for_parse;
213 } vmentry_l1d_param[] = {
214 	[VMENTER_L1D_FLUSH_AUTO]	 = {"auto", true},
215 	[VMENTER_L1D_FLUSH_NEVER]	 = {"never", true},
216 	[VMENTER_L1D_FLUSH_COND]	 = {"cond", true},
217 	[VMENTER_L1D_FLUSH_ALWAYS]	 = {"always", true},
218 	[VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
219 	[VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
220 };
221 
222 #define L1D_CACHE_ORDER 4
223 static void *vmx_l1d_flush_pages;
224 
225 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
226 {
227 	struct page *page;
228 	unsigned int i;
229 
230 	if (!boot_cpu_has_bug(X86_BUG_L1TF)) {
231 		l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
232 		return 0;
233 	}
234 
235 	if (!enable_ept) {
236 		l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
237 		return 0;
238 	}
239 
240 	if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
241 		u64 msr;
242 
243 		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
244 		if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
245 			l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
246 			return 0;
247 		}
248 	}
249 
250 	/* If set to auto use the default l1tf mitigation method */
251 	if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
252 		switch (l1tf_mitigation) {
253 		case L1TF_MITIGATION_OFF:
254 			l1tf = VMENTER_L1D_FLUSH_NEVER;
255 			break;
256 		case L1TF_MITIGATION_FLUSH_NOWARN:
257 		case L1TF_MITIGATION_FLUSH:
258 		case L1TF_MITIGATION_FLUSH_NOSMT:
259 			l1tf = VMENTER_L1D_FLUSH_COND;
260 			break;
261 		case L1TF_MITIGATION_FULL:
262 		case L1TF_MITIGATION_FULL_FORCE:
263 			l1tf = VMENTER_L1D_FLUSH_ALWAYS;
264 			break;
265 		}
266 	} else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
267 		l1tf = VMENTER_L1D_FLUSH_ALWAYS;
268 	}
269 
270 	if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
271 	    !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
272 		/*
273 		 * This allocation for vmx_l1d_flush_pages is not tied to a VM
274 		 * lifetime and so should not be charged to a memcg.
275 		 */
276 		page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
277 		if (!page)
278 			return -ENOMEM;
279 		vmx_l1d_flush_pages = page_address(page);
280 
281 		/*
282 		 * Initialize each page with a different pattern in
283 		 * order to protect against KSM in the nested
284 		 * virtualization case.
285 		 */
286 		for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
287 			memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
288 			       PAGE_SIZE);
289 		}
290 	}
291 
292 	l1tf_vmx_mitigation = l1tf;
293 
294 	if (l1tf != VMENTER_L1D_FLUSH_NEVER)
295 		static_branch_enable(&vmx_l1d_should_flush);
296 	else
297 		static_branch_disable(&vmx_l1d_should_flush);
298 
299 	if (l1tf == VMENTER_L1D_FLUSH_COND)
300 		static_branch_enable(&vmx_l1d_flush_cond);
301 	else
302 		static_branch_disable(&vmx_l1d_flush_cond);
303 	return 0;
304 }
305 
306 static int vmentry_l1d_flush_parse(const char *s)
307 {
308 	unsigned int i;
309 
310 	if (s) {
311 		for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
312 			if (vmentry_l1d_param[i].for_parse &&
313 			    sysfs_streq(s, vmentry_l1d_param[i].option))
314 				return i;
315 		}
316 	}
317 	return -EINVAL;
318 }
319 
320 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
321 {
322 	int l1tf, ret;
323 
324 	l1tf = vmentry_l1d_flush_parse(s);
325 	if (l1tf < 0)
326 		return l1tf;
327 
328 	if (!boot_cpu_has(X86_BUG_L1TF))
329 		return 0;
330 
331 	/*
332 	 * Has vmx_init() run already? If not then this is the pre init
333 	 * parameter parsing. In that case just store the value and let
334 	 * vmx_init() do the proper setup after enable_ept has been
335 	 * established.
336 	 */
337 	if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
338 		vmentry_l1d_flush_param = l1tf;
339 		return 0;
340 	}
341 
342 	mutex_lock(&vmx_l1d_flush_mutex);
343 	ret = vmx_setup_l1d_flush(l1tf);
344 	mutex_unlock(&vmx_l1d_flush_mutex);
345 	return ret;
346 }
347 
348 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
349 {
350 	if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
351 		return sprintf(s, "???\n");
352 
353 	return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
354 }
355 
356 static const struct kernel_param_ops vmentry_l1d_flush_ops = {
357 	.set = vmentry_l1d_flush_set,
358 	.get = vmentry_l1d_flush_get,
359 };
360 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
361 
362 static u32 vmx_segment_access_rights(struct kvm_segment *var);
363 static __always_inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu,
364 							  u32 msr, int type);
365 
366 void vmx_vmexit(void);
367 
368 #define vmx_insn_failed(fmt...)		\
369 do {					\
370 	WARN_ONCE(1, fmt);		\
371 	pr_warn_ratelimited(fmt);	\
372 } while (0)
373 
374 asmlinkage void vmread_error(unsigned long field, bool fault)
375 {
376 	if (fault)
377 		kvm_spurious_fault();
378 	else
379 		vmx_insn_failed("kvm: vmread failed: field=%lx\n", field);
380 }
381 
382 noinline void vmwrite_error(unsigned long field, unsigned long value)
383 {
384 	vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
385 			field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
386 }
387 
388 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr)
389 {
390 	vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr);
391 }
392 
393 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr)
394 {
395 	vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr);
396 }
397 
398 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva)
399 {
400 	vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
401 			ext, vpid, gva);
402 }
403 
404 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa)
405 {
406 	vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
407 			ext, eptp, gpa);
408 }
409 
410 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
411 DEFINE_PER_CPU(struct vmcs *, current_vmcs);
412 /*
413  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
414  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
415  */
416 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
417 
418 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
419 static DEFINE_SPINLOCK(vmx_vpid_lock);
420 
421 struct vmcs_config vmcs_config;
422 struct vmx_capability vmx_capability;
423 
424 #define VMX_SEGMENT_FIELD(seg)					\
425 	[VCPU_SREG_##seg] = {                                   \
426 		.selector = GUEST_##seg##_SELECTOR,		\
427 		.base = GUEST_##seg##_BASE,		   	\
428 		.limit = GUEST_##seg##_LIMIT,		   	\
429 		.ar_bytes = GUEST_##seg##_AR_BYTES,	   	\
430 	}
431 
432 static const struct kvm_vmx_segment_field {
433 	unsigned selector;
434 	unsigned base;
435 	unsigned limit;
436 	unsigned ar_bytes;
437 } kvm_vmx_segment_fields[] = {
438 	VMX_SEGMENT_FIELD(CS),
439 	VMX_SEGMENT_FIELD(DS),
440 	VMX_SEGMENT_FIELD(ES),
441 	VMX_SEGMENT_FIELD(FS),
442 	VMX_SEGMENT_FIELD(GS),
443 	VMX_SEGMENT_FIELD(SS),
444 	VMX_SEGMENT_FIELD(TR),
445 	VMX_SEGMENT_FIELD(LDTR),
446 };
447 
448 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
449 {
450 	vmx->segment_cache.bitmask = 0;
451 }
452 
453 static unsigned long host_idt_base;
454 
455 /*
456  * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
457  * will emulate SYSCALL in legacy mode if the vendor string in guest
458  * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
459  * support this emulation, IA32_STAR must always be included in
460  * vmx_uret_msrs_list[], even in i386 builds.
461  */
462 static const u32 vmx_uret_msrs_list[] = {
463 #ifdef CONFIG_X86_64
464 	MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
465 #endif
466 	MSR_EFER, MSR_TSC_AUX, MSR_STAR,
467 	MSR_IA32_TSX_CTRL,
468 };
469 
470 #if IS_ENABLED(CONFIG_HYPERV)
471 static bool __read_mostly enlightened_vmcs = true;
472 module_param(enlightened_vmcs, bool, 0444);
473 
474 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
475 static void check_ept_pointer_match(struct kvm *kvm)
476 {
477 	struct kvm_vcpu *vcpu;
478 	u64 tmp_eptp = INVALID_PAGE;
479 	int i;
480 
481 	kvm_for_each_vcpu(i, vcpu, kvm) {
482 		if (!VALID_PAGE(tmp_eptp)) {
483 			tmp_eptp = to_vmx(vcpu)->ept_pointer;
484 		} else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
485 			to_kvm_vmx(kvm)->ept_pointers_match
486 				= EPT_POINTERS_MISMATCH;
487 			return;
488 		}
489 	}
490 
491 	to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
492 }
493 
494 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush,
495 		void *data)
496 {
497 	struct kvm_tlb_range *range = data;
498 
499 	return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn,
500 			range->pages);
501 }
502 
503 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm,
504 		struct kvm_vcpu *vcpu, struct kvm_tlb_range *range)
505 {
506 	u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
507 
508 	/*
509 	 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address
510 	 * of the base of EPT PML4 table, strip off EPT configuration
511 	 * information.
512 	 */
513 	if (range)
514 		return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK,
515 				kvm_fill_hv_flush_list_func, (void *)range);
516 	else
517 		return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK);
518 }
519 
520 static int hv_remote_flush_tlb_with_range(struct kvm *kvm,
521 		struct kvm_tlb_range *range)
522 {
523 	struct kvm_vcpu *vcpu;
524 	int ret = 0, i;
525 
526 	spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
527 
528 	if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
529 		check_ept_pointer_match(kvm);
530 
531 	if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
532 		kvm_for_each_vcpu(i, vcpu, kvm) {
533 			/* If ept_pointer is invalid pointer, bypass flush request. */
534 			if (VALID_PAGE(to_vmx(vcpu)->ept_pointer))
535 				ret |= __hv_remote_flush_tlb_with_range(
536 					kvm, vcpu, range);
537 		}
538 	} else {
539 		ret = __hv_remote_flush_tlb_with_range(kvm,
540 				kvm_get_vcpu(kvm, 0), range);
541 	}
542 
543 	spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
544 	return ret;
545 }
546 static int hv_remote_flush_tlb(struct kvm *kvm)
547 {
548 	return hv_remote_flush_tlb_with_range(kvm, NULL);
549 }
550 
551 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu)
552 {
553 	struct hv_enlightened_vmcs *evmcs;
554 	struct hv_partition_assist_pg **p_hv_pa_pg =
555 			&vcpu->kvm->arch.hyperv.hv_pa_pg;
556 	/*
557 	 * Synthetic VM-Exit is not enabled in current code and so All
558 	 * evmcs in singe VM shares same assist page.
559 	 */
560 	if (!*p_hv_pa_pg)
561 		*p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL);
562 
563 	if (!*p_hv_pa_pg)
564 		return -ENOMEM;
565 
566 	evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs;
567 
568 	evmcs->partition_assist_page =
569 		__pa(*p_hv_pa_pg);
570 	evmcs->hv_vm_id = (unsigned long)vcpu->kvm;
571 	evmcs->hv_enlightenments_control.nested_flush_hypercall = 1;
572 
573 	return 0;
574 }
575 
576 #endif /* IS_ENABLED(CONFIG_HYPERV) */
577 
578 /*
579  * Comment's format: document - errata name - stepping - processor name.
580  * Refer from
581  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
582  */
583 static u32 vmx_preemption_cpu_tfms[] = {
584 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
585 0x000206E6,
586 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
587 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
588 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
589 0x00020652,
590 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
591 0x00020655,
592 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
593 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
594 /*
595  * 320767.pdf - AAP86  - B1 -
596  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
597  */
598 0x000106E5,
599 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
600 0x000106A0,
601 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
602 0x000106A1,
603 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
604 0x000106A4,
605  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
606  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
607  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
608 0x000106A5,
609  /* Xeon E3-1220 V2 */
610 0x000306A8,
611 };
612 
613 static inline bool cpu_has_broken_vmx_preemption_timer(void)
614 {
615 	u32 eax = cpuid_eax(0x00000001), i;
616 
617 	/* Clear the reserved bits */
618 	eax &= ~(0x3U << 14 | 0xfU << 28);
619 	for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
620 		if (eax == vmx_preemption_cpu_tfms[i])
621 			return true;
622 
623 	return false;
624 }
625 
626 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
627 {
628 	return flexpriority_enabled && lapic_in_kernel(vcpu);
629 }
630 
631 static inline bool report_flexpriority(void)
632 {
633 	return flexpriority_enabled;
634 }
635 
636 static int possible_passthrough_msr_slot(u32 msr)
637 {
638 	u32 i;
639 
640 	for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++)
641 		if (vmx_possible_passthrough_msrs[i] == msr)
642 			return i;
643 
644 	return -ENOENT;
645 }
646 
647 static bool is_valid_passthrough_msr(u32 msr)
648 {
649 	bool r;
650 
651 	switch (msr) {
652 	case 0x800 ... 0x8ff:
653 		/* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
654 		return true;
655 	case MSR_IA32_RTIT_STATUS:
656 	case MSR_IA32_RTIT_OUTPUT_BASE:
657 	case MSR_IA32_RTIT_OUTPUT_MASK:
658 	case MSR_IA32_RTIT_CR3_MATCH:
659 	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
660 		/* PT MSRs. These are handled in pt_update_intercept_for_msr() */
661 		return true;
662 	}
663 
664 	r = possible_passthrough_msr_slot(msr) != -ENOENT;
665 
666 	WARN(!r, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr);
667 
668 	return r;
669 }
670 
671 static inline int __vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
672 {
673 	int i;
674 
675 	for (i = 0; i < vmx->nr_uret_msrs; ++i)
676 		if (vmx_uret_msrs_list[vmx->guest_uret_msrs[i].slot] == msr)
677 			return i;
678 	return -1;
679 }
680 
681 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr)
682 {
683 	int i;
684 
685 	i = __vmx_find_uret_msr(vmx, msr);
686 	if (i >= 0)
687 		return &vmx->guest_uret_msrs[i];
688 	return NULL;
689 }
690 
691 static int vmx_set_guest_uret_msr(struct vcpu_vmx *vmx,
692 				  struct vmx_uret_msr *msr, u64 data)
693 {
694 	int ret = 0;
695 
696 	u64 old_msr_data = msr->data;
697 	msr->data = data;
698 	if (msr - vmx->guest_uret_msrs < vmx->nr_active_uret_msrs) {
699 		preempt_disable();
700 		ret = kvm_set_user_return_msr(msr->slot, msr->data, msr->mask);
701 		preempt_enable();
702 		if (ret)
703 			msr->data = old_msr_data;
704 	}
705 	return ret;
706 }
707 
708 #ifdef CONFIG_KEXEC_CORE
709 static void crash_vmclear_local_loaded_vmcss(void)
710 {
711 	int cpu = raw_smp_processor_id();
712 	struct loaded_vmcs *v;
713 
714 	list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
715 			    loaded_vmcss_on_cpu_link)
716 		vmcs_clear(v->vmcs);
717 }
718 #endif /* CONFIG_KEXEC_CORE */
719 
720 static void __loaded_vmcs_clear(void *arg)
721 {
722 	struct loaded_vmcs *loaded_vmcs = arg;
723 	int cpu = raw_smp_processor_id();
724 
725 	if (loaded_vmcs->cpu != cpu)
726 		return; /* vcpu migration can race with cpu offline */
727 	if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
728 		per_cpu(current_vmcs, cpu) = NULL;
729 
730 	vmcs_clear(loaded_vmcs->vmcs);
731 	if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
732 		vmcs_clear(loaded_vmcs->shadow_vmcs);
733 
734 	list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
735 
736 	/*
737 	 * Ensure all writes to loaded_vmcs, including deleting it from its
738 	 * current percpu list, complete before setting loaded_vmcs->vcpu to
739 	 * -1, otherwise a different cpu can see vcpu == -1 first and add
740 	 * loaded_vmcs to its percpu list before it's deleted from this cpu's
741 	 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
742 	 */
743 	smp_wmb();
744 
745 	loaded_vmcs->cpu = -1;
746 	loaded_vmcs->launched = 0;
747 }
748 
749 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
750 {
751 	int cpu = loaded_vmcs->cpu;
752 
753 	if (cpu != -1)
754 		smp_call_function_single(cpu,
755 			 __loaded_vmcs_clear, loaded_vmcs, 1);
756 }
757 
758 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
759 				       unsigned field)
760 {
761 	bool ret;
762 	u32 mask = 1 << (seg * SEG_FIELD_NR + field);
763 
764 	if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) {
765 		kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS);
766 		vmx->segment_cache.bitmask = 0;
767 	}
768 	ret = vmx->segment_cache.bitmask & mask;
769 	vmx->segment_cache.bitmask |= mask;
770 	return ret;
771 }
772 
773 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
774 {
775 	u16 *p = &vmx->segment_cache.seg[seg].selector;
776 
777 	if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
778 		*p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
779 	return *p;
780 }
781 
782 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
783 {
784 	ulong *p = &vmx->segment_cache.seg[seg].base;
785 
786 	if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
787 		*p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
788 	return *p;
789 }
790 
791 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
792 {
793 	u32 *p = &vmx->segment_cache.seg[seg].limit;
794 
795 	if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
796 		*p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
797 	return *p;
798 }
799 
800 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
801 {
802 	u32 *p = &vmx->segment_cache.seg[seg].ar;
803 
804 	if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
805 		*p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
806 	return *p;
807 }
808 
809 void update_exception_bitmap(struct kvm_vcpu *vcpu)
810 {
811 	u32 eb;
812 
813 	eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
814 	     (1u << DB_VECTOR) | (1u << AC_VECTOR);
815 	/*
816 	 * Guest access to VMware backdoor ports could legitimately
817 	 * trigger #GP because of TSS I/O permission bitmap.
818 	 * We intercept those #GP and allow access to them anyway
819 	 * as VMware does.
820 	 */
821 	if (enable_vmware_backdoor)
822 		eb |= (1u << GP_VECTOR);
823 	if ((vcpu->guest_debug &
824 	     (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
825 	    (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
826 		eb |= 1u << BP_VECTOR;
827 	if (to_vmx(vcpu)->rmode.vm86_active)
828 		eb = ~0;
829 	if (!vmx_need_pf_intercept(vcpu))
830 		eb &= ~(1u << PF_VECTOR);
831 
832 	/* When we are running a nested L2 guest and L1 specified for it a
833 	 * certain exception bitmap, we must trap the same exceptions and pass
834 	 * them to L1. When running L2, we will only handle the exceptions
835 	 * specified above if L1 did not want them.
836 	 */
837 	if (is_guest_mode(vcpu))
838 		eb |= get_vmcs12(vcpu)->exception_bitmap;
839         else {
840 		/*
841 		 * If EPT is enabled, #PF is only trapped if MAXPHYADDR is mismatched
842 		 * between guest and host.  In that case we only care about present
843 		 * faults.  For vmcs02, however, PFEC_MASK and PFEC_MATCH are set in
844 		 * prepare_vmcs02_rare.
845 		 */
846 		bool selective_pf_trap = enable_ept && (eb & (1u << PF_VECTOR));
847 		int mask = selective_pf_trap ? PFERR_PRESENT_MASK : 0;
848 		vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
849 		vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, mask);
850 	}
851 
852 	vmcs_write32(EXCEPTION_BITMAP, eb);
853 }
854 
855 /*
856  * Check if MSR is intercepted for currently loaded MSR bitmap.
857  */
858 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
859 {
860 	unsigned long *msr_bitmap;
861 	int f = sizeof(unsigned long);
862 
863 	if (!cpu_has_vmx_msr_bitmap())
864 		return true;
865 
866 	msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
867 
868 	if (msr <= 0x1fff) {
869 		return !!test_bit(msr, msr_bitmap + 0x800 / f);
870 	} else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
871 		msr &= 0x1fff;
872 		return !!test_bit(msr, msr_bitmap + 0xc00 / f);
873 	}
874 
875 	return true;
876 }
877 
878 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
879 		unsigned long entry, unsigned long exit)
880 {
881 	vm_entry_controls_clearbit(vmx, entry);
882 	vm_exit_controls_clearbit(vmx, exit);
883 }
884 
885 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr)
886 {
887 	unsigned int i;
888 
889 	for (i = 0; i < m->nr; ++i) {
890 		if (m->val[i].index == msr)
891 			return i;
892 	}
893 	return -ENOENT;
894 }
895 
896 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
897 {
898 	int i;
899 	struct msr_autoload *m = &vmx->msr_autoload;
900 
901 	switch (msr) {
902 	case MSR_EFER:
903 		if (cpu_has_load_ia32_efer()) {
904 			clear_atomic_switch_msr_special(vmx,
905 					VM_ENTRY_LOAD_IA32_EFER,
906 					VM_EXIT_LOAD_IA32_EFER);
907 			return;
908 		}
909 		break;
910 	case MSR_CORE_PERF_GLOBAL_CTRL:
911 		if (cpu_has_load_perf_global_ctrl()) {
912 			clear_atomic_switch_msr_special(vmx,
913 					VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
914 					VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
915 			return;
916 		}
917 		break;
918 	}
919 	i = vmx_find_loadstore_msr_slot(&m->guest, msr);
920 	if (i < 0)
921 		goto skip_guest;
922 	--m->guest.nr;
923 	m->guest.val[i] = m->guest.val[m->guest.nr];
924 	vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
925 
926 skip_guest:
927 	i = vmx_find_loadstore_msr_slot(&m->host, msr);
928 	if (i < 0)
929 		return;
930 
931 	--m->host.nr;
932 	m->host.val[i] = m->host.val[m->host.nr];
933 	vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
934 }
935 
936 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
937 		unsigned long entry, unsigned long exit,
938 		unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
939 		u64 guest_val, u64 host_val)
940 {
941 	vmcs_write64(guest_val_vmcs, guest_val);
942 	if (host_val_vmcs != HOST_IA32_EFER)
943 		vmcs_write64(host_val_vmcs, host_val);
944 	vm_entry_controls_setbit(vmx, entry);
945 	vm_exit_controls_setbit(vmx, exit);
946 }
947 
948 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
949 				  u64 guest_val, u64 host_val, bool entry_only)
950 {
951 	int i, j = 0;
952 	struct msr_autoload *m = &vmx->msr_autoload;
953 
954 	switch (msr) {
955 	case MSR_EFER:
956 		if (cpu_has_load_ia32_efer()) {
957 			add_atomic_switch_msr_special(vmx,
958 					VM_ENTRY_LOAD_IA32_EFER,
959 					VM_EXIT_LOAD_IA32_EFER,
960 					GUEST_IA32_EFER,
961 					HOST_IA32_EFER,
962 					guest_val, host_val);
963 			return;
964 		}
965 		break;
966 	case MSR_CORE_PERF_GLOBAL_CTRL:
967 		if (cpu_has_load_perf_global_ctrl()) {
968 			add_atomic_switch_msr_special(vmx,
969 					VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
970 					VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
971 					GUEST_IA32_PERF_GLOBAL_CTRL,
972 					HOST_IA32_PERF_GLOBAL_CTRL,
973 					guest_val, host_val);
974 			return;
975 		}
976 		break;
977 	case MSR_IA32_PEBS_ENABLE:
978 		/* PEBS needs a quiescent period after being disabled (to write
979 		 * a record).  Disabling PEBS through VMX MSR swapping doesn't
980 		 * provide that period, so a CPU could write host's record into
981 		 * guest's memory.
982 		 */
983 		wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
984 	}
985 
986 	i = vmx_find_loadstore_msr_slot(&m->guest, msr);
987 	if (!entry_only)
988 		j = vmx_find_loadstore_msr_slot(&m->host, msr);
989 
990 	if ((i < 0 && m->guest.nr == MAX_NR_LOADSTORE_MSRS) ||
991 	    (j < 0 &&  m->host.nr == MAX_NR_LOADSTORE_MSRS)) {
992 		printk_once(KERN_WARNING "Not enough msr switch entries. "
993 				"Can't add msr %x\n", msr);
994 		return;
995 	}
996 	if (i < 0) {
997 		i = m->guest.nr++;
998 		vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
999 	}
1000 	m->guest.val[i].index = msr;
1001 	m->guest.val[i].value = guest_val;
1002 
1003 	if (entry_only)
1004 		return;
1005 
1006 	if (j < 0) {
1007 		j = m->host.nr++;
1008 		vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
1009 	}
1010 	m->host.val[j].index = msr;
1011 	m->host.val[j].value = host_val;
1012 }
1013 
1014 static bool update_transition_efer(struct vcpu_vmx *vmx)
1015 {
1016 	u64 guest_efer = vmx->vcpu.arch.efer;
1017 	u64 ignore_bits = 0;
1018 	int i;
1019 
1020 	/* Shadow paging assumes NX to be available.  */
1021 	if (!enable_ept)
1022 		guest_efer |= EFER_NX;
1023 
1024 	/*
1025 	 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1026 	 */
1027 	ignore_bits |= EFER_SCE;
1028 #ifdef CONFIG_X86_64
1029 	ignore_bits |= EFER_LMA | EFER_LME;
1030 	/* SCE is meaningful only in long mode on Intel */
1031 	if (guest_efer & EFER_LMA)
1032 		ignore_bits &= ~(u64)EFER_SCE;
1033 #endif
1034 
1035 	/*
1036 	 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1037 	 * On CPUs that support "load IA32_EFER", always switch EFER
1038 	 * atomically, since it's faster than switching it manually.
1039 	 */
1040 	if (cpu_has_load_ia32_efer() ||
1041 	    (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1042 		if (!(guest_efer & EFER_LMA))
1043 			guest_efer &= ~EFER_LME;
1044 		if (guest_efer != host_efer)
1045 			add_atomic_switch_msr(vmx, MSR_EFER,
1046 					      guest_efer, host_efer, false);
1047 		else
1048 			clear_atomic_switch_msr(vmx, MSR_EFER);
1049 		return false;
1050 	}
1051 
1052 	i = __vmx_find_uret_msr(vmx, MSR_EFER);
1053 	if (i < 0)
1054 		return false;
1055 
1056 	clear_atomic_switch_msr(vmx, MSR_EFER);
1057 
1058 	guest_efer &= ~ignore_bits;
1059 	guest_efer |= host_efer & ignore_bits;
1060 
1061 	vmx->guest_uret_msrs[i].data = guest_efer;
1062 	vmx->guest_uret_msrs[i].mask = ~ignore_bits;
1063 
1064 	return true;
1065 }
1066 
1067 #ifdef CONFIG_X86_32
1068 /*
1069  * On 32-bit kernels, VM exits still load the FS and GS bases from the
1070  * VMCS rather than the segment table.  KVM uses this helper to figure
1071  * out the current bases to poke them into the VMCS before entry.
1072  */
1073 static unsigned long segment_base(u16 selector)
1074 {
1075 	struct desc_struct *table;
1076 	unsigned long v;
1077 
1078 	if (!(selector & ~SEGMENT_RPL_MASK))
1079 		return 0;
1080 
1081 	table = get_current_gdt_ro();
1082 
1083 	if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1084 		u16 ldt_selector = kvm_read_ldt();
1085 
1086 		if (!(ldt_selector & ~SEGMENT_RPL_MASK))
1087 			return 0;
1088 
1089 		table = (struct desc_struct *)segment_base(ldt_selector);
1090 	}
1091 	v = get_desc_base(&table[selector >> 3]);
1092 	return v;
1093 }
1094 #endif
1095 
1096 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx)
1097 {
1098 	return vmx_pt_mode_is_host_guest() &&
1099 	       !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
1100 }
1101 
1102 static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base)
1103 {
1104 	/* The base must be 128-byte aligned and a legal physical address. */
1105 	return !kvm_vcpu_is_illegal_gpa(vcpu, base) && !(base & 0x7f);
1106 }
1107 
1108 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range)
1109 {
1110 	u32 i;
1111 
1112 	wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1113 	wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1114 	wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1115 	wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1116 	for (i = 0; i < addr_range; i++) {
1117 		wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1118 		wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1119 	}
1120 }
1121 
1122 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range)
1123 {
1124 	u32 i;
1125 
1126 	rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status);
1127 	rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base);
1128 	rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask);
1129 	rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match);
1130 	for (i = 0; i < addr_range; i++) {
1131 		rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]);
1132 		rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]);
1133 	}
1134 }
1135 
1136 static void pt_guest_enter(struct vcpu_vmx *vmx)
1137 {
1138 	if (vmx_pt_mode_is_system())
1139 		return;
1140 
1141 	/*
1142 	 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1143 	 * Save host state before VM entry.
1144 	 */
1145 	rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1146 	if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1147 		wrmsrl(MSR_IA32_RTIT_CTL, 0);
1148 		pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1149 		pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1150 	}
1151 }
1152 
1153 static void pt_guest_exit(struct vcpu_vmx *vmx)
1154 {
1155 	if (vmx_pt_mode_is_system())
1156 		return;
1157 
1158 	if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) {
1159 		pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range);
1160 		pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range);
1161 	}
1162 
1163 	/* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1164 	wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
1165 }
1166 
1167 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
1168 			unsigned long fs_base, unsigned long gs_base)
1169 {
1170 	if (unlikely(fs_sel != host->fs_sel)) {
1171 		if (!(fs_sel & 7))
1172 			vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1173 		else
1174 			vmcs_write16(HOST_FS_SELECTOR, 0);
1175 		host->fs_sel = fs_sel;
1176 	}
1177 	if (unlikely(gs_sel != host->gs_sel)) {
1178 		if (!(gs_sel & 7))
1179 			vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1180 		else
1181 			vmcs_write16(HOST_GS_SELECTOR, 0);
1182 		host->gs_sel = gs_sel;
1183 	}
1184 	if (unlikely(fs_base != host->fs_base)) {
1185 		vmcs_writel(HOST_FS_BASE, fs_base);
1186 		host->fs_base = fs_base;
1187 	}
1188 	if (unlikely(gs_base != host->gs_base)) {
1189 		vmcs_writel(HOST_GS_BASE, gs_base);
1190 		host->gs_base = gs_base;
1191 	}
1192 }
1193 
1194 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1195 {
1196 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1197 	struct vmcs_host_state *host_state;
1198 #ifdef CONFIG_X86_64
1199 	int cpu = raw_smp_processor_id();
1200 #endif
1201 	unsigned long fs_base, gs_base;
1202 	u16 fs_sel, gs_sel;
1203 	int i;
1204 
1205 	vmx->req_immediate_exit = false;
1206 
1207 	/*
1208 	 * Note that guest MSRs to be saved/restored can also be changed
1209 	 * when guest state is loaded. This happens when guest transitions
1210 	 * to/from long-mode by setting MSR_EFER.LMA.
1211 	 */
1212 	if (!vmx->guest_uret_msrs_loaded) {
1213 		vmx->guest_uret_msrs_loaded = true;
1214 		for (i = 0; i < vmx->nr_active_uret_msrs; ++i)
1215 			kvm_set_user_return_msr(vmx->guest_uret_msrs[i].slot,
1216 						vmx->guest_uret_msrs[i].data,
1217 						vmx->guest_uret_msrs[i].mask);
1218 
1219 	}
1220 
1221     	if (vmx->nested.need_vmcs12_to_shadow_sync)
1222 		nested_sync_vmcs12_to_shadow(vcpu);
1223 
1224 	if (vmx->guest_state_loaded)
1225 		return;
1226 
1227 	host_state = &vmx->loaded_vmcs->host_state;
1228 
1229 	/*
1230 	 * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1231 	 * allow segment selectors with cpl > 0 or ti == 1.
1232 	 */
1233 	host_state->ldt_sel = kvm_read_ldt();
1234 
1235 #ifdef CONFIG_X86_64
1236 	savesegment(ds, host_state->ds_sel);
1237 	savesegment(es, host_state->es_sel);
1238 
1239 	gs_base = cpu_kernelmode_gs_base(cpu);
1240 	if (likely(is_64bit_mm(current->mm))) {
1241 		current_save_fsgs();
1242 		fs_sel = current->thread.fsindex;
1243 		gs_sel = current->thread.gsindex;
1244 		fs_base = current->thread.fsbase;
1245 		vmx->msr_host_kernel_gs_base = current->thread.gsbase;
1246 	} else {
1247 		savesegment(fs, fs_sel);
1248 		savesegment(gs, gs_sel);
1249 		fs_base = read_msr(MSR_FS_BASE);
1250 		vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
1251 	}
1252 
1253 	wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1254 #else
1255 	savesegment(fs, fs_sel);
1256 	savesegment(gs, gs_sel);
1257 	fs_base = segment_base(fs_sel);
1258 	gs_base = segment_base(gs_sel);
1259 #endif
1260 
1261 	vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
1262 	vmx->guest_state_loaded = true;
1263 }
1264 
1265 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
1266 {
1267 	struct vmcs_host_state *host_state;
1268 
1269 	if (!vmx->guest_state_loaded)
1270 		return;
1271 
1272 	host_state = &vmx->loaded_vmcs->host_state;
1273 
1274 	++vmx->vcpu.stat.host_state_reload;
1275 
1276 #ifdef CONFIG_X86_64
1277 	rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1278 #endif
1279 	if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1280 		kvm_load_ldt(host_state->ldt_sel);
1281 #ifdef CONFIG_X86_64
1282 		load_gs_index(host_state->gs_sel);
1283 #else
1284 		loadsegment(gs, host_state->gs_sel);
1285 #endif
1286 	}
1287 	if (host_state->fs_sel & 7)
1288 		loadsegment(fs, host_state->fs_sel);
1289 #ifdef CONFIG_X86_64
1290 	if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1291 		loadsegment(ds, host_state->ds_sel);
1292 		loadsegment(es, host_state->es_sel);
1293 	}
1294 #endif
1295 	invalidate_tss_limit();
1296 #ifdef CONFIG_X86_64
1297 	wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1298 #endif
1299 	load_fixmap_gdt(raw_smp_processor_id());
1300 	vmx->guest_state_loaded = false;
1301 	vmx->guest_uret_msrs_loaded = false;
1302 }
1303 
1304 #ifdef CONFIG_X86_64
1305 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
1306 {
1307 	preempt_disable();
1308 	if (vmx->guest_state_loaded)
1309 		rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1310 	preempt_enable();
1311 	return vmx->msr_guest_kernel_gs_base;
1312 }
1313 
1314 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1315 {
1316 	preempt_disable();
1317 	if (vmx->guest_state_loaded)
1318 		wrmsrl(MSR_KERNEL_GS_BASE, data);
1319 	preempt_enable();
1320 	vmx->msr_guest_kernel_gs_base = data;
1321 }
1322 #endif
1323 
1324 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
1325 			struct loaded_vmcs *buddy)
1326 {
1327 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1328 	bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
1329 	struct vmcs *prev;
1330 
1331 	if (!already_loaded) {
1332 		loaded_vmcs_clear(vmx->loaded_vmcs);
1333 		local_irq_disable();
1334 
1335 		/*
1336 		 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1337 		 * this cpu's percpu list, otherwise it may not yet be deleted
1338 		 * from its previous cpu's percpu list.  Pairs with the
1339 		 * smb_wmb() in __loaded_vmcs_clear().
1340 		 */
1341 		smp_rmb();
1342 
1343 		list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1344 			 &per_cpu(loaded_vmcss_on_cpu, cpu));
1345 		local_irq_enable();
1346 	}
1347 
1348 	prev = per_cpu(current_vmcs, cpu);
1349 	if (prev != vmx->loaded_vmcs->vmcs) {
1350 		per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1351 		vmcs_load(vmx->loaded_vmcs->vmcs);
1352 
1353 		/*
1354 		 * No indirect branch prediction barrier needed when switching
1355 		 * the active VMCS within a guest, e.g. on nested VM-Enter.
1356 		 * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1357 		 */
1358 		if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
1359 			indirect_branch_prediction_barrier();
1360 	}
1361 
1362 	if (!already_loaded) {
1363 		void *gdt = get_current_gdt_ro();
1364 		unsigned long sysenter_esp;
1365 
1366 		/*
1367 		 * Flush all EPTP/VPID contexts, the new pCPU may have stale
1368 		 * TLB entries from its previous association with the vCPU.
1369 		 */
1370 		kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1371 
1372 		/*
1373 		 * Linux uses per-cpu TSS and GDT, so set these when switching
1374 		 * processors.  See 22.2.4.
1375 		 */
1376 		vmcs_writel(HOST_TR_BASE,
1377 			    (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
1378 		vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
1379 
1380 		rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1381 		vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1382 
1383 		vmx->loaded_vmcs->cpu = cpu;
1384 	}
1385 
1386 	/* Setup TSC multiplier */
1387 	if (kvm_has_tsc_control &&
1388 	    vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1389 		decache_tsc_multiplier(vmx);
1390 }
1391 
1392 /*
1393  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1394  * vcpu mutex is already taken.
1395  */
1396 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1397 {
1398 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1399 
1400 	vmx_vcpu_load_vmcs(vcpu, cpu, NULL);
1401 
1402 	vmx_vcpu_pi_load(vcpu, cpu);
1403 
1404 	vmx->host_debugctlmsr = get_debugctlmsr();
1405 }
1406 
1407 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1408 {
1409 	vmx_vcpu_pi_put(vcpu);
1410 
1411 	vmx_prepare_switch_to_host(to_vmx(vcpu));
1412 }
1413 
1414 static bool emulation_required(struct kvm_vcpu *vcpu)
1415 {
1416 	return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
1417 }
1418 
1419 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1420 {
1421 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1422 	unsigned long rflags, save_rflags;
1423 
1424 	if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
1425 		kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1426 		rflags = vmcs_readl(GUEST_RFLAGS);
1427 		if (vmx->rmode.vm86_active) {
1428 			rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1429 			save_rflags = vmx->rmode.save_rflags;
1430 			rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1431 		}
1432 		vmx->rflags = rflags;
1433 	}
1434 	return vmx->rflags;
1435 }
1436 
1437 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1438 {
1439 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1440 	unsigned long old_rflags;
1441 
1442 	if (is_unrestricted_guest(vcpu)) {
1443 		kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
1444 		vmx->rflags = rflags;
1445 		vmcs_writel(GUEST_RFLAGS, rflags);
1446 		return;
1447 	}
1448 
1449 	old_rflags = vmx_get_rflags(vcpu);
1450 	vmx->rflags = rflags;
1451 	if (vmx->rmode.vm86_active) {
1452 		vmx->rmode.save_rflags = rflags;
1453 		rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1454 	}
1455 	vmcs_writel(GUEST_RFLAGS, rflags);
1456 
1457 	if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
1458 		vmx->emulation_required = emulation_required(vcpu);
1459 }
1460 
1461 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1462 {
1463 	u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1464 	int ret = 0;
1465 
1466 	if (interruptibility & GUEST_INTR_STATE_STI)
1467 		ret |= KVM_X86_SHADOW_INT_STI;
1468 	if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1469 		ret |= KVM_X86_SHADOW_INT_MOV_SS;
1470 
1471 	return ret;
1472 }
1473 
1474 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1475 {
1476 	u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1477 	u32 interruptibility = interruptibility_old;
1478 
1479 	interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1480 
1481 	if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1482 		interruptibility |= GUEST_INTR_STATE_MOV_SS;
1483 	else if (mask & KVM_X86_SHADOW_INT_STI)
1484 		interruptibility |= GUEST_INTR_STATE_STI;
1485 
1486 	if ((interruptibility != interruptibility_old))
1487 		vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1488 }
1489 
1490 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
1491 {
1492 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1493 	unsigned long value;
1494 
1495 	/*
1496 	 * Any MSR write that attempts to change bits marked reserved will
1497 	 * case a #GP fault.
1498 	 */
1499 	if (data & vmx->pt_desc.ctl_bitmask)
1500 		return 1;
1501 
1502 	/*
1503 	 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1504 	 * result in a #GP unless the same write also clears TraceEn.
1505 	 */
1506 	if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
1507 		((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
1508 		return 1;
1509 
1510 	/*
1511 	 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1512 	 * and FabricEn would cause #GP, if
1513 	 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1514 	 */
1515 	if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
1516 		!(data & RTIT_CTL_FABRIC_EN) &&
1517 		!intel_pt_validate_cap(vmx->pt_desc.caps,
1518 					PT_CAP_single_range_output))
1519 		return 1;
1520 
1521 	/*
1522 	 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1523 	 * utilize encodings marked reserved will casue a #GP fault.
1524 	 */
1525 	value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
1526 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
1527 			!test_bit((data & RTIT_CTL_MTC_RANGE) >>
1528 			RTIT_CTL_MTC_RANGE_OFFSET, &value))
1529 		return 1;
1530 	value = intel_pt_validate_cap(vmx->pt_desc.caps,
1531 						PT_CAP_cycle_thresholds);
1532 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1533 			!test_bit((data & RTIT_CTL_CYC_THRESH) >>
1534 			RTIT_CTL_CYC_THRESH_OFFSET, &value))
1535 		return 1;
1536 	value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
1537 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
1538 			!test_bit((data & RTIT_CTL_PSB_FREQ) >>
1539 			RTIT_CTL_PSB_FREQ_OFFSET, &value))
1540 		return 1;
1541 
1542 	/*
1543 	 * If ADDRx_CFG is reserved or the encodings is >2 will
1544 	 * cause a #GP fault.
1545 	 */
1546 	value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
1547 	if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
1548 		return 1;
1549 	value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
1550 	if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
1551 		return 1;
1552 	value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
1553 	if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
1554 		return 1;
1555 	value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
1556 	if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
1557 		return 1;
1558 
1559 	return 0;
1560 }
1561 
1562 static bool vmx_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
1563 {
1564 	return true;
1565 }
1566 
1567 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
1568 {
1569 	unsigned long rip, orig_rip;
1570 
1571 	/*
1572 	 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1573 	 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1574 	 * set when EPT misconfig occurs.  In practice, real hardware updates
1575 	 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1576 	 * (namely Hyper-V) don't set it due to it being undefined behavior,
1577 	 * i.e. we end up advancing IP with some random value.
1578 	 */
1579 	if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
1580 	    to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) {
1581 		orig_rip = kvm_rip_read(vcpu);
1582 		rip = orig_rip + vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1583 #ifdef CONFIG_X86_64
1584 		/*
1585 		 * We need to mask out the high 32 bits of RIP if not in 64-bit
1586 		 * mode, but just finding out that we are in 64-bit mode is
1587 		 * quite expensive.  Only do it if there was a carry.
1588 		 */
1589 		if (unlikely(((rip ^ orig_rip) >> 31) == 3) && !is_64_bit_mode(vcpu))
1590 			rip = (u32)rip;
1591 #endif
1592 		kvm_rip_write(vcpu, rip);
1593 	} else {
1594 		if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
1595 			return 0;
1596 	}
1597 
1598 	/* skipping an emulated instruction also counts */
1599 	vmx_set_interrupt_shadow(vcpu, 0);
1600 
1601 	return 1;
1602 }
1603 
1604 /*
1605  * Recognizes a pending MTF VM-exit and records the nested state for later
1606  * delivery.
1607  */
1608 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu)
1609 {
1610 	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1611 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1612 
1613 	if (!is_guest_mode(vcpu))
1614 		return;
1615 
1616 	/*
1617 	 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1618 	 * T-bit traps. As instruction emulation is completed (i.e. at the
1619 	 * instruction boundary), any #DB exception pending delivery must be a
1620 	 * debug-trap. Record the pending MTF state to be delivered in
1621 	 * vmx_check_nested_events().
1622 	 */
1623 	if (nested_cpu_has_mtf(vmcs12) &&
1624 	    (!vcpu->arch.exception.pending ||
1625 	     vcpu->arch.exception.nr == DB_VECTOR))
1626 		vmx->nested.mtf_pending = true;
1627 	else
1628 		vmx->nested.mtf_pending = false;
1629 }
1630 
1631 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu)
1632 {
1633 	vmx_update_emulated_instruction(vcpu);
1634 	return skip_emulated_instruction(vcpu);
1635 }
1636 
1637 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1638 {
1639 	/*
1640 	 * Ensure that we clear the HLT state in the VMCS.  We don't need to
1641 	 * explicitly skip the instruction because if the HLT state is set,
1642 	 * then the instruction is already executing and RIP has already been
1643 	 * advanced.
1644 	 */
1645 	if (kvm_hlt_in_guest(vcpu->kvm) &&
1646 			vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1647 		vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1648 }
1649 
1650 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
1651 {
1652 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1653 	unsigned nr = vcpu->arch.exception.nr;
1654 	bool has_error_code = vcpu->arch.exception.has_error_code;
1655 	u32 error_code = vcpu->arch.exception.error_code;
1656 	u32 intr_info = nr | INTR_INFO_VALID_MASK;
1657 
1658 	kvm_deliver_exception_payload(vcpu);
1659 
1660 	if (has_error_code) {
1661 		vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1662 		intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1663 	}
1664 
1665 	if (vmx->rmode.vm86_active) {
1666 		int inc_eip = 0;
1667 		if (kvm_exception_is_soft(nr))
1668 			inc_eip = vcpu->arch.event_exit_inst_len;
1669 		kvm_inject_realmode_interrupt(vcpu, nr, inc_eip);
1670 		return;
1671 	}
1672 
1673 	WARN_ON_ONCE(vmx->emulation_required);
1674 
1675 	if (kvm_exception_is_soft(nr)) {
1676 		vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1677 			     vmx->vcpu.arch.event_exit_inst_len);
1678 		intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1679 	} else
1680 		intr_info |= INTR_TYPE_HARD_EXCEPTION;
1681 
1682 	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1683 
1684 	vmx_clear_hlt(vcpu);
1685 }
1686 
1687 static void vmx_setup_uret_msr(struct vcpu_vmx *vmx, unsigned int msr)
1688 {
1689 	struct vmx_uret_msr tmp;
1690 	int from, to;
1691 
1692 	from = __vmx_find_uret_msr(vmx, msr);
1693 	if (from < 0)
1694 		return;
1695 	to = vmx->nr_active_uret_msrs++;
1696 
1697 	tmp = vmx->guest_uret_msrs[to];
1698 	vmx->guest_uret_msrs[to] = vmx->guest_uret_msrs[from];
1699 	vmx->guest_uret_msrs[from] = tmp;
1700 }
1701 
1702 /*
1703  * Set up the vmcs to automatically save and restore system
1704  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1705  * mode, as fiddling with msrs is very expensive.
1706  */
1707 static void setup_msrs(struct vcpu_vmx *vmx)
1708 {
1709 	vmx->guest_uret_msrs_loaded = false;
1710 	vmx->nr_active_uret_msrs = 0;
1711 #ifdef CONFIG_X86_64
1712 	/*
1713 	 * The SYSCALL MSRs are only needed on long mode guests, and only
1714 	 * when EFER.SCE is set.
1715 	 */
1716 	if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1717 		vmx_setup_uret_msr(vmx, MSR_STAR);
1718 		vmx_setup_uret_msr(vmx, MSR_LSTAR);
1719 		vmx_setup_uret_msr(vmx, MSR_SYSCALL_MASK);
1720 	}
1721 #endif
1722 	if (update_transition_efer(vmx))
1723 		vmx_setup_uret_msr(vmx, MSR_EFER);
1724 
1725 	if (guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1726 		vmx_setup_uret_msr(vmx, MSR_TSC_AUX);
1727 
1728 	vmx_setup_uret_msr(vmx, MSR_IA32_TSX_CTRL);
1729 
1730 	if (cpu_has_vmx_msr_bitmap())
1731 		vmx_update_msr_bitmap(&vmx->vcpu);
1732 }
1733 
1734 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1735 {
1736 	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1737 	u64 g_tsc_offset = 0;
1738 
1739 	/*
1740 	 * We're here if L1 chose not to trap WRMSR to TSC. According
1741 	 * to the spec, this should set L1's TSC; The offset that L1
1742 	 * set for L2 remains unchanged, and still needs to be added
1743 	 * to the newly set TSC to get L2's TSC.
1744 	 */
1745 	if (is_guest_mode(vcpu) &&
1746 	    (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
1747 		g_tsc_offset = vmcs12->tsc_offset;
1748 
1749 	trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1750 				   vcpu->arch.tsc_offset - g_tsc_offset,
1751 				   offset);
1752 	vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1753 	return offset + g_tsc_offset;
1754 }
1755 
1756 /*
1757  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1758  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1759  * all guests if the "nested" module option is off, and can also be disabled
1760  * for a single guest by disabling its VMX cpuid bit.
1761  */
1762 bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1763 {
1764 	return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
1765 }
1766 
1767 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1768 						 uint64_t val)
1769 {
1770 	uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
1771 
1772 	return !(val & ~valid_bits);
1773 }
1774 
1775 static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
1776 {
1777 	switch (msr->index) {
1778 	case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1779 		if (!nested)
1780 			return 1;
1781 		return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1782 	case MSR_IA32_PERF_CAPABILITIES:
1783 		msr->data = vmx_get_perf_capabilities();
1784 		return 0;
1785 	default:
1786 		return KVM_MSR_RET_INVALID;
1787 	}
1788 }
1789 
1790 /*
1791  * Reads an msr value (of 'msr_index') into 'pdata'.
1792  * Returns 0 on success, non-0 otherwise.
1793  * Assumes vcpu_load() was already called.
1794  */
1795 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1796 {
1797 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1798 	struct vmx_uret_msr *msr;
1799 	u32 index;
1800 
1801 	switch (msr_info->index) {
1802 #ifdef CONFIG_X86_64
1803 	case MSR_FS_BASE:
1804 		msr_info->data = vmcs_readl(GUEST_FS_BASE);
1805 		break;
1806 	case MSR_GS_BASE:
1807 		msr_info->data = vmcs_readl(GUEST_GS_BASE);
1808 		break;
1809 	case MSR_KERNEL_GS_BASE:
1810 		msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
1811 		break;
1812 #endif
1813 	case MSR_EFER:
1814 		return kvm_get_msr_common(vcpu, msr_info);
1815 	case MSR_IA32_TSX_CTRL:
1816 		if (!msr_info->host_initiated &&
1817 		    !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
1818 			return 1;
1819 		goto find_uret_msr;
1820 	case MSR_IA32_UMWAIT_CONTROL:
1821 		if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
1822 			return 1;
1823 
1824 		msr_info->data = vmx->msr_ia32_umwait_control;
1825 		break;
1826 	case MSR_IA32_SPEC_CTRL:
1827 		if (!msr_info->host_initiated &&
1828 		    !guest_has_spec_ctrl_msr(vcpu))
1829 			return 1;
1830 
1831 		msr_info->data = to_vmx(vcpu)->spec_ctrl;
1832 		break;
1833 	case MSR_IA32_SYSENTER_CS:
1834 		msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
1835 		break;
1836 	case MSR_IA32_SYSENTER_EIP:
1837 		msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
1838 		break;
1839 	case MSR_IA32_SYSENTER_ESP:
1840 		msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
1841 		break;
1842 	case MSR_IA32_BNDCFGS:
1843 		if (!kvm_mpx_supported() ||
1844 		    (!msr_info->host_initiated &&
1845 		     !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
1846 			return 1;
1847 		msr_info->data = vmcs_read64(GUEST_BNDCFGS);
1848 		break;
1849 	case MSR_IA32_MCG_EXT_CTL:
1850 		if (!msr_info->host_initiated &&
1851 		    !(vmx->msr_ia32_feature_control &
1852 		      FEAT_CTL_LMCE_ENABLED))
1853 			return 1;
1854 		msr_info->data = vcpu->arch.mcg_ext_ctl;
1855 		break;
1856 	case MSR_IA32_FEAT_CTL:
1857 		msr_info->data = vmx->msr_ia32_feature_control;
1858 		break;
1859 	case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1860 		if (!nested_vmx_allowed(vcpu))
1861 			return 1;
1862 		if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1863 				    &msr_info->data))
1864 			return 1;
1865 		/*
1866 		 * Enlightened VMCS v1 doesn't have certain fields, but buggy
1867 		 * Hyper-V versions are still trying to use corresponding
1868 		 * features when they are exposed. Filter out the essential
1869 		 * minimum.
1870 		 */
1871 		if (!msr_info->host_initiated &&
1872 		    vmx->nested.enlightened_vmcs_enabled)
1873 			nested_evmcs_filter_control_msr(msr_info->index,
1874 							&msr_info->data);
1875 		break;
1876 	case MSR_IA32_RTIT_CTL:
1877 		if (!vmx_pt_mode_is_host_guest())
1878 			return 1;
1879 		msr_info->data = vmx->pt_desc.guest.ctl;
1880 		break;
1881 	case MSR_IA32_RTIT_STATUS:
1882 		if (!vmx_pt_mode_is_host_guest())
1883 			return 1;
1884 		msr_info->data = vmx->pt_desc.guest.status;
1885 		break;
1886 	case MSR_IA32_RTIT_CR3_MATCH:
1887 		if (!vmx_pt_mode_is_host_guest() ||
1888 			!intel_pt_validate_cap(vmx->pt_desc.caps,
1889 						PT_CAP_cr3_filtering))
1890 			return 1;
1891 		msr_info->data = vmx->pt_desc.guest.cr3_match;
1892 		break;
1893 	case MSR_IA32_RTIT_OUTPUT_BASE:
1894 		if (!vmx_pt_mode_is_host_guest() ||
1895 			(!intel_pt_validate_cap(vmx->pt_desc.caps,
1896 					PT_CAP_topa_output) &&
1897 			 !intel_pt_validate_cap(vmx->pt_desc.caps,
1898 					PT_CAP_single_range_output)))
1899 			return 1;
1900 		msr_info->data = vmx->pt_desc.guest.output_base;
1901 		break;
1902 	case MSR_IA32_RTIT_OUTPUT_MASK:
1903 		if (!vmx_pt_mode_is_host_guest() ||
1904 			(!intel_pt_validate_cap(vmx->pt_desc.caps,
1905 					PT_CAP_topa_output) &&
1906 			 !intel_pt_validate_cap(vmx->pt_desc.caps,
1907 					PT_CAP_single_range_output)))
1908 			return 1;
1909 		msr_info->data = vmx->pt_desc.guest.output_mask;
1910 		break;
1911 	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
1912 		index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
1913 		if (!vmx_pt_mode_is_host_guest() ||
1914 			(index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
1915 					PT_CAP_num_address_ranges)))
1916 			return 1;
1917 		if (index % 2)
1918 			msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
1919 		else
1920 			msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
1921 		break;
1922 	case MSR_TSC_AUX:
1923 		if (!msr_info->host_initiated &&
1924 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1925 			return 1;
1926 		goto find_uret_msr;
1927 	default:
1928 	find_uret_msr:
1929 		msr = vmx_find_uret_msr(vmx, msr_info->index);
1930 		if (msr) {
1931 			msr_info->data = msr->data;
1932 			break;
1933 		}
1934 		return kvm_get_msr_common(vcpu, msr_info);
1935 	}
1936 
1937 	return 0;
1938 }
1939 
1940 static u64 nested_vmx_truncate_sysenter_addr(struct kvm_vcpu *vcpu,
1941 						    u64 data)
1942 {
1943 #ifdef CONFIG_X86_64
1944 	if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
1945 		return (u32)data;
1946 #endif
1947 	return (unsigned long)data;
1948 }
1949 
1950 /*
1951  * Writes msr value into the appropriate "register".
1952  * Returns 0 on success, non-0 otherwise.
1953  * Assumes vcpu_load() was already called.
1954  */
1955 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1956 {
1957 	struct vcpu_vmx *vmx = to_vmx(vcpu);
1958 	struct vmx_uret_msr *msr;
1959 	int ret = 0;
1960 	u32 msr_index = msr_info->index;
1961 	u64 data = msr_info->data;
1962 	u32 index;
1963 
1964 	switch (msr_index) {
1965 	case MSR_EFER:
1966 		ret = kvm_set_msr_common(vcpu, msr_info);
1967 		break;
1968 #ifdef CONFIG_X86_64
1969 	case MSR_FS_BASE:
1970 		vmx_segment_cache_clear(vmx);
1971 		vmcs_writel(GUEST_FS_BASE, data);
1972 		break;
1973 	case MSR_GS_BASE:
1974 		vmx_segment_cache_clear(vmx);
1975 		vmcs_writel(GUEST_GS_BASE, data);
1976 		break;
1977 	case MSR_KERNEL_GS_BASE:
1978 		vmx_write_guest_kernel_gs_base(vmx, data);
1979 		break;
1980 #endif
1981 	case MSR_IA32_SYSENTER_CS:
1982 		if (is_guest_mode(vcpu))
1983 			get_vmcs12(vcpu)->guest_sysenter_cs = data;
1984 		vmcs_write32(GUEST_SYSENTER_CS, data);
1985 		break;
1986 	case MSR_IA32_SYSENTER_EIP:
1987 		if (is_guest_mode(vcpu)) {
1988 			data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1989 			get_vmcs12(vcpu)->guest_sysenter_eip = data;
1990 		}
1991 		vmcs_writel(GUEST_SYSENTER_EIP, data);
1992 		break;
1993 	case MSR_IA32_SYSENTER_ESP:
1994 		if (is_guest_mode(vcpu)) {
1995 			data = nested_vmx_truncate_sysenter_addr(vcpu, data);
1996 			get_vmcs12(vcpu)->guest_sysenter_esp = data;
1997 		}
1998 		vmcs_writel(GUEST_SYSENTER_ESP, data);
1999 		break;
2000 	case MSR_IA32_DEBUGCTLMSR:
2001 		if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls &
2002 						VM_EXIT_SAVE_DEBUG_CONTROLS)
2003 			get_vmcs12(vcpu)->guest_ia32_debugctl = data;
2004 
2005 		ret = kvm_set_msr_common(vcpu, msr_info);
2006 		break;
2007 
2008 	case MSR_IA32_BNDCFGS:
2009 		if (!kvm_mpx_supported() ||
2010 		    (!msr_info->host_initiated &&
2011 		     !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
2012 			return 1;
2013 		if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
2014 		    (data & MSR_IA32_BNDCFGS_RSVD))
2015 			return 1;
2016 		vmcs_write64(GUEST_BNDCFGS, data);
2017 		break;
2018 	case MSR_IA32_UMWAIT_CONTROL:
2019 		if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx))
2020 			return 1;
2021 
2022 		/* The reserved bit 1 and non-32 bit [63:32] should be zero */
2023 		if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2024 			return 1;
2025 
2026 		vmx->msr_ia32_umwait_control = data;
2027 		break;
2028 	case MSR_IA32_SPEC_CTRL:
2029 		if (!msr_info->host_initiated &&
2030 		    !guest_has_spec_ctrl_msr(vcpu))
2031 			return 1;
2032 
2033 		if (kvm_spec_ctrl_test_value(data))
2034 			return 1;
2035 
2036 		vmx->spec_ctrl = data;
2037 		if (!data)
2038 			break;
2039 
2040 		/*
2041 		 * For non-nested:
2042 		 * When it's written (to non-zero) for the first time, pass
2043 		 * it through.
2044 		 *
2045 		 * For nested:
2046 		 * The handling of the MSR bitmap for L2 guests is done in
2047 		 * nested_vmx_prepare_msr_bitmap. We should not touch the
2048 		 * vmcs02.msr_bitmap here since it gets completely overwritten
2049 		 * in the merging. We update the vmcs01 here for L1 as well
2050 		 * since it will end up touching the MSR anyway now.
2051 		 */
2052 		vmx_disable_intercept_for_msr(vcpu,
2053 					      MSR_IA32_SPEC_CTRL,
2054 					      MSR_TYPE_RW);
2055 		break;
2056 	case MSR_IA32_TSX_CTRL:
2057 		if (!msr_info->host_initiated &&
2058 		    !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR))
2059 			return 1;
2060 		if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR))
2061 			return 1;
2062 		goto find_uret_msr;
2063 	case MSR_IA32_PRED_CMD:
2064 		if (!msr_info->host_initiated &&
2065 		    !guest_has_pred_cmd_msr(vcpu))
2066 			return 1;
2067 
2068 		if (data & ~PRED_CMD_IBPB)
2069 			return 1;
2070 		if (!boot_cpu_has(X86_FEATURE_IBPB))
2071 			return 1;
2072 		if (!data)
2073 			break;
2074 
2075 		wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2076 
2077 		/*
2078 		 * For non-nested:
2079 		 * When it's written (to non-zero) for the first time, pass
2080 		 * it through.
2081 		 *
2082 		 * For nested:
2083 		 * The handling of the MSR bitmap for L2 guests is done in
2084 		 * nested_vmx_prepare_msr_bitmap. We should not touch the
2085 		 * vmcs02.msr_bitmap here since it gets completely overwritten
2086 		 * in the merging.
2087 		 */
2088 		vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
2089 		break;
2090 	case MSR_IA32_CR_PAT:
2091 		if (!kvm_pat_valid(data))
2092 			return 1;
2093 
2094 		if (is_guest_mode(vcpu) &&
2095 		    get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
2096 			get_vmcs12(vcpu)->guest_ia32_pat = data;
2097 
2098 		if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2099 			vmcs_write64(GUEST_IA32_PAT, data);
2100 			vcpu->arch.pat = data;
2101 			break;
2102 		}
2103 		ret = kvm_set_msr_common(vcpu, msr_info);
2104 		break;
2105 	case MSR_IA32_TSC_ADJUST:
2106 		ret = kvm_set_msr_common(vcpu, msr_info);
2107 		break;
2108 	case MSR_IA32_MCG_EXT_CTL:
2109 		if ((!msr_info->host_initiated &&
2110 		     !(to_vmx(vcpu)->msr_ia32_feature_control &
2111 		       FEAT_CTL_LMCE_ENABLED)) ||
2112 		    (data & ~MCG_EXT_CTL_LMCE_EN))
2113 			return 1;
2114 		vcpu->arch.mcg_ext_ctl = data;
2115 		break;
2116 	case MSR_IA32_FEAT_CTL:
2117 		if (!vmx_feature_control_msr_valid(vcpu, data) ||
2118 		    (to_vmx(vcpu)->msr_ia32_feature_control &
2119 		     FEAT_CTL_LOCKED && !msr_info->host_initiated))
2120 			return 1;
2121 		vmx->msr_ia32_feature_control = data;
2122 		if (msr_info->host_initiated && data == 0)
2123 			vmx_leave_nested(vcpu);
2124 		break;
2125 	case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2126 		if (!msr_info->host_initiated)
2127 			return 1; /* they are read-only */
2128 		if (!nested_vmx_allowed(vcpu))
2129 			return 1;
2130 		return vmx_set_vmx_msr(vcpu, msr_index, data);
2131 	case MSR_IA32_RTIT_CTL:
2132 		if (!vmx_pt_mode_is_host_guest() ||
2133 			vmx_rtit_ctl_check(vcpu, data) ||
2134 			vmx->nested.vmxon)
2135 			return 1;
2136 		vmcs_write64(GUEST_IA32_RTIT_CTL, data);
2137 		vmx->pt_desc.guest.ctl = data;
2138 		pt_update_intercept_for_msr(vcpu);
2139 		break;
2140 	case MSR_IA32_RTIT_STATUS:
2141 		if (!pt_can_write_msr(vmx))
2142 			return 1;
2143 		if (data & MSR_IA32_RTIT_STATUS_MASK)
2144 			return 1;
2145 		vmx->pt_desc.guest.status = data;
2146 		break;
2147 	case MSR_IA32_RTIT_CR3_MATCH:
2148 		if (!pt_can_write_msr(vmx))
2149 			return 1;
2150 		if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2151 					   PT_CAP_cr3_filtering))
2152 			return 1;
2153 		vmx->pt_desc.guest.cr3_match = data;
2154 		break;
2155 	case MSR_IA32_RTIT_OUTPUT_BASE:
2156 		if (!pt_can_write_msr(vmx))
2157 			return 1;
2158 		if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2159 					   PT_CAP_topa_output) &&
2160 		    !intel_pt_validate_cap(vmx->pt_desc.caps,
2161 					   PT_CAP_single_range_output))
2162 			return 1;
2163 		if (!pt_output_base_valid(vcpu, data))
2164 			return 1;
2165 		vmx->pt_desc.guest.output_base = data;
2166 		break;
2167 	case MSR_IA32_RTIT_OUTPUT_MASK:
2168 		if (!pt_can_write_msr(vmx))
2169 			return 1;
2170 		if (!intel_pt_validate_cap(vmx->pt_desc.caps,
2171 					   PT_CAP_topa_output) &&
2172 		    !intel_pt_validate_cap(vmx->pt_desc.caps,
2173 					   PT_CAP_single_range_output))
2174 			return 1;
2175 		vmx->pt_desc.guest.output_mask = data;
2176 		break;
2177 	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2178 		if (!pt_can_write_msr(vmx))
2179 			return 1;
2180 		index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
2181 		if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
2182 						       PT_CAP_num_address_ranges))
2183 			return 1;
2184 		if (is_noncanonical_address(data, vcpu))
2185 			return 1;
2186 		if (index % 2)
2187 			vmx->pt_desc.guest.addr_b[index / 2] = data;
2188 		else
2189 			vmx->pt_desc.guest.addr_a[index / 2] = data;
2190 		break;
2191 	case MSR_TSC_AUX:
2192 		if (!msr_info->host_initiated &&
2193 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
2194 			return 1;
2195 		/* Check reserved bit, higher 32 bits should be zero */
2196 		if ((data >> 32) != 0)
2197 			return 1;
2198 		goto find_uret_msr;
2199 
2200 	default:
2201 	find_uret_msr:
2202 		msr = vmx_find_uret_msr(vmx, msr_index);
2203 		if (msr)
2204 			ret = vmx_set_guest_uret_msr(vmx, msr, data);
2205 		else
2206 			ret = kvm_set_msr_common(vcpu, msr_info);
2207 	}
2208 
2209 	return ret;
2210 }
2211 
2212 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2213 {
2214 	unsigned long guest_owned_bits;
2215 
2216 	kvm_register_mark_available(vcpu, reg);
2217 
2218 	switch (reg) {
2219 	case VCPU_REGS_RSP:
2220 		vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2221 		break;
2222 	case VCPU_REGS_RIP:
2223 		vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2224 		break;
2225 	case VCPU_EXREG_PDPTR:
2226 		if (enable_ept)
2227 			ept_save_pdptrs(vcpu);
2228 		break;
2229 	case VCPU_EXREG_CR0:
2230 		guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2231 
2232 		vcpu->arch.cr0 &= ~guest_owned_bits;
2233 		vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
2234 		break;
2235 	case VCPU_EXREG_CR3:
2236 		if (is_unrestricted_guest(vcpu) ||
2237 		    (enable_ept && is_paging(vcpu)))
2238 			vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2239 		break;
2240 	case VCPU_EXREG_CR4:
2241 		guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2242 
2243 		vcpu->arch.cr4 &= ~guest_owned_bits;
2244 		vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
2245 		break;
2246 	default:
2247 		WARN_ON_ONCE(1);
2248 		break;
2249 	}
2250 }
2251 
2252 static __init int cpu_has_kvm_support(void)
2253 {
2254 	return cpu_has_vmx();
2255 }
2256 
2257 static __init int vmx_disabled_by_bios(void)
2258 {
2259 	return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2260 	       !boot_cpu_has(X86_FEATURE_VMX);
2261 }
2262 
2263 static int kvm_cpu_vmxon(u64 vmxon_pointer)
2264 {
2265 	u64 msr;
2266 
2267 	cr4_set_bits(X86_CR4_VMXE);
2268 	intel_pt_handle_vmx(1);
2269 
2270 	asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2271 			  _ASM_EXTABLE(1b, %l[fault])
2272 			  : : [vmxon_pointer] "m"(vmxon_pointer)
2273 			  : : fault);
2274 	return 0;
2275 
2276 fault:
2277 	WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2278 		  rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr);
2279 	intel_pt_handle_vmx(0);
2280 	cr4_clear_bits(X86_CR4_VMXE);
2281 
2282 	return -EFAULT;
2283 }
2284 
2285 static int hardware_enable(void)
2286 {
2287 	int cpu = raw_smp_processor_id();
2288 	u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2289 	int r;
2290 
2291 	if (cr4_read_shadow() & X86_CR4_VMXE)
2292 		return -EBUSY;
2293 
2294 	/*
2295 	 * This can happen if we hot-added a CPU but failed to allocate
2296 	 * VP assist page for it.
2297 	 */
2298 	if (static_branch_unlikely(&enable_evmcs) &&
2299 	    !hv_get_vp_assist_page(cpu))
2300 		return -EFAULT;
2301 
2302 	r = kvm_cpu_vmxon(phys_addr);
2303 	if (r)
2304 		return r;
2305 
2306 	if (enable_ept)
2307 		ept_sync_global();
2308 
2309 	return 0;
2310 }
2311 
2312 static void vmclear_local_loaded_vmcss(void)
2313 {
2314 	int cpu = raw_smp_processor_id();
2315 	struct loaded_vmcs *v, *n;
2316 
2317 	list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2318 				 loaded_vmcss_on_cpu_link)
2319 		__loaded_vmcs_clear(v);
2320 }
2321 
2322 
2323 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2324  * tricks.
2325  */
2326 static void kvm_cpu_vmxoff(void)
2327 {
2328 	asm volatile (__ex("vmxoff"));
2329 
2330 	intel_pt_handle_vmx(0);
2331 	cr4_clear_bits(X86_CR4_VMXE);
2332 }
2333 
2334 static void hardware_disable(void)
2335 {
2336 	vmclear_local_loaded_vmcss();
2337 	kvm_cpu_vmxoff();
2338 }
2339 
2340 /*
2341  * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2342  * directly instead of going through cpu_has(), to ensure KVM is trapping
2343  * ENCLS whenever it's supported in hardware.  It does not matter whether
2344  * the host OS supports or has enabled SGX.
2345  */
2346 static bool cpu_has_sgx(void)
2347 {
2348 	return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2349 }
2350 
2351 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2352 				      u32 msr, u32 *result)
2353 {
2354 	u32 vmx_msr_low, vmx_msr_high;
2355 	u32 ctl = ctl_min | ctl_opt;
2356 
2357 	rdmsr(msr, vmx_msr_low, vmx_msr_high);
2358 
2359 	ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2360 	ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2361 
2362 	/* Ensure minimum (required) set of control bits are supported. */
2363 	if (ctl_min & ~ctl)
2364 		return -EIO;
2365 
2366 	*result = ctl;
2367 	return 0;
2368 }
2369 
2370 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
2371 				    struct vmx_capability *vmx_cap)
2372 {
2373 	u32 vmx_msr_low, vmx_msr_high;
2374 	u32 min, opt, min2, opt2;
2375 	u32 _pin_based_exec_control = 0;
2376 	u32 _cpu_based_exec_control = 0;
2377 	u32 _cpu_based_2nd_exec_control = 0;
2378 	u32 _vmexit_control = 0;
2379 	u32 _vmentry_control = 0;
2380 
2381 	memset(vmcs_conf, 0, sizeof(*vmcs_conf));
2382 	min = CPU_BASED_HLT_EXITING |
2383 #ifdef CONFIG_X86_64
2384 	      CPU_BASED_CR8_LOAD_EXITING |
2385 	      CPU_BASED_CR8_STORE_EXITING |
2386 #endif
2387 	      CPU_BASED_CR3_LOAD_EXITING |
2388 	      CPU_BASED_CR3_STORE_EXITING |
2389 	      CPU_BASED_UNCOND_IO_EXITING |
2390 	      CPU_BASED_MOV_DR_EXITING |
2391 	      CPU_BASED_USE_TSC_OFFSETTING |
2392 	      CPU_BASED_MWAIT_EXITING |
2393 	      CPU_BASED_MONITOR_EXITING |
2394 	      CPU_BASED_INVLPG_EXITING |
2395 	      CPU_BASED_RDPMC_EXITING;
2396 
2397 	opt = CPU_BASED_TPR_SHADOW |
2398 	      CPU_BASED_USE_MSR_BITMAPS |
2399 	      CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2400 	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2401 				&_cpu_based_exec_control) < 0)
2402 		return -EIO;
2403 #ifdef CONFIG_X86_64
2404 	if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2405 		_cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2406 					   ~CPU_BASED_CR8_STORE_EXITING;
2407 #endif
2408 	if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2409 		min2 = 0;
2410 		opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2411 			SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2412 			SECONDARY_EXEC_WBINVD_EXITING |
2413 			SECONDARY_EXEC_ENABLE_VPID |
2414 			SECONDARY_EXEC_ENABLE_EPT |
2415 			SECONDARY_EXEC_UNRESTRICTED_GUEST |
2416 			SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2417 			SECONDARY_EXEC_DESC |
2418 			SECONDARY_EXEC_ENABLE_RDTSCP |
2419 			SECONDARY_EXEC_ENABLE_INVPCID |
2420 			SECONDARY_EXEC_APIC_REGISTER_VIRT |
2421 			SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2422 			SECONDARY_EXEC_SHADOW_VMCS |
2423 			SECONDARY_EXEC_XSAVES |
2424 			SECONDARY_EXEC_RDSEED_EXITING |
2425 			SECONDARY_EXEC_RDRAND_EXITING |
2426 			SECONDARY_EXEC_ENABLE_PML |
2427 			SECONDARY_EXEC_TSC_SCALING |
2428 			SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |
2429 			SECONDARY_EXEC_PT_USE_GPA |
2430 			SECONDARY_EXEC_PT_CONCEAL_VMX |
2431 			SECONDARY_EXEC_ENABLE_VMFUNC;
2432 		if (cpu_has_sgx())
2433 			opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
2434 		if (adjust_vmx_controls(min2, opt2,
2435 					MSR_IA32_VMX_PROCBASED_CTLS2,
2436 					&_cpu_based_2nd_exec_control) < 0)
2437 			return -EIO;
2438 	}
2439 #ifndef CONFIG_X86_64
2440 	if (!(_cpu_based_2nd_exec_control &
2441 				SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2442 		_cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2443 #endif
2444 
2445 	if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2446 		_cpu_based_2nd_exec_control &= ~(
2447 				SECONDARY_EXEC_APIC_REGISTER_VIRT |
2448 				SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2449 				SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2450 
2451 	rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
2452 		&vmx_cap->ept, &vmx_cap->vpid);
2453 
2454 	if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2455 		/* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2456 		   enabled */
2457 		_cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2458 					     CPU_BASED_CR3_STORE_EXITING |
2459 					     CPU_BASED_INVLPG_EXITING);
2460 	} else if (vmx_cap->ept) {
2461 		vmx_cap->ept = 0;
2462 		pr_warn_once("EPT CAP should not exist if not support "
2463 				"1-setting enable EPT VM-execution control\n");
2464 	}
2465 	if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
2466 		vmx_cap->vpid) {
2467 		vmx_cap->vpid = 0;
2468 		pr_warn_once("VPID CAP should not exist if not support "
2469 				"1-setting enable VPID VM-execution control\n");
2470 	}
2471 
2472 	min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
2473 #ifdef CONFIG_X86_64
2474 	min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2475 #endif
2476 	opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2477 	      VM_EXIT_LOAD_IA32_PAT |
2478 	      VM_EXIT_LOAD_IA32_EFER |
2479 	      VM_EXIT_CLEAR_BNDCFGS |
2480 	      VM_EXIT_PT_CONCEAL_PIP |
2481 	      VM_EXIT_CLEAR_IA32_RTIT_CTL;
2482 	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2483 				&_vmexit_control) < 0)
2484 		return -EIO;
2485 
2486 	min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2487 	opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2488 		 PIN_BASED_VMX_PREEMPTION_TIMER;
2489 	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2490 				&_pin_based_exec_control) < 0)
2491 		return -EIO;
2492 
2493 	if (cpu_has_broken_vmx_preemption_timer())
2494 		_pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2495 	if (!(_cpu_based_2nd_exec_control &
2496 		SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
2497 		_pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2498 
2499 	min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2500 	opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2501 	      VM_ENTRY_LOAD_IA32_PAT |
2502 	      VM_ENTRY_LOAD_IA32_EFER |
2503 	      VM_ENTRY_LOAD_BNDCFGS |
2504 	      VM_ENTRY_PT_CONCEAL_PIP |
2505 	      VM_ENTRY_LOAD_IA32_RTIT_CTL;
2506 	if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2507 				&_vmentry_control) < 0)
2508 		return -EIO;
2509 
2510 	/*
2511 	 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2512 	 * can't be used due to an errata where VM Exit may incorrectly clear
2513 	 * IA32_PERF_GLOBAL_CTRL[34:32].  Workaround the errata by using the
2514 	 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2515 	 */
2516 	if (boot_cpu_data.x86 == 0x6) {
2517 		switch (boot_cpu_data.x86_model) {
2518 		case 26: /* AAK155 */
2519 		case 30: /* AAP115 */
2520 		case 37: /* AAT100 */
2521 		case 44: /* BC86,AAY89,BD102 */
2522 		case 46: /* BA97 */
2523 			_vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2524 			_vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2525 			pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2526 					"does not work properly. Using workaround\n");
2527 			break;
2528 		default:
2529 			break;
2530 		}
2531 	}
2532 
2533 
2534 	rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2535 
2536 	/* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2537 	if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2538 		return -EIO;
2539 
2540 #ifdef CONFIG_X86_64
2541 	/* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2542 	if (vmx_msr_high & (1u<<16))
2543 		return -EIO;
2544 #endif
2545 
2546 	/* Require Write-Back (WB) memory type for VMCS accesses. */
2547 	if (((vmx_msr_high >> 18) & 15) != 6)
2548 		return -EIO;
2549 
2550 	vmcs_conf->size = vmx_msr_high & 0x1fff;
2551 	vmcs_conf->order = get_order(vmcs_conf->size);
2552 	vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
2553 
2554 	vmcs_conf->revision_id = vmx_msr_low;
2555 
2556 	vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2557 	vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2558 	vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2559 	vmcs_conf->vmexit_ctrl         = _vmexit_control;
2560 	vmcs_conf->vmentry_ctrl        = _vmentry_control;
2561 
2562 #if IS_ENABLED(CONFIG_HYPERV)
2563 	if (enlightened_vmcs)
2564 		evmcs_sanitize_exec_ctrls(vmcs_conf);
2565 #endif
2566 
2567 	return 0;
2568 }
2569 
2570 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags)
2571 {
2572 	int node = cpu_to_node(cpu);
2573 	struct page *pages;
2574 	struct vmcs *vmcs;
2575 
2576 	pages = __alloc_pages_node(node, flags, vmcs_config.order);
2577 	if (!pages)
2578 		return NULL;
2579 	vmcs = page_address(pages);
2580 	memset(vmcs, 0, vmcs_config.size);
2581 
2582 	/* KVM supports Enlightened VMCS v1 only */
2583 	if (static_branch_unlikely(&enable_evmcs))
2584 		vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2585 	else
2586 		vmcs->hdr.revision_id = vmcs_config.revision_id;
2587 
2588 	if (shadow)
2589 		vmcs->hdr.shadow_vmcs = 1;
2590 	return vmcs;
2591 }
2592 
2593 void free_vmcs(struct vmcs *vmcs)
2594 {
2595 	free_pages((unsigned long)vmcs, vmcs_config.order);
2596 }
2597 
2598 /*
2599  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2600  */
2601 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2602 {
2603 	if (!loaded_vmcs->vmcs)
2604 		return;
2605 	loaded_vmcs_clear(loaded_vmcs);
2606 	free_vmcs(loaded_vmcs->vmcs);
2607 	loaded_vmcs->vmcs = NULL;
2608 	if (loaded_vmcs->msr_bitmap)
2609 		free_page((unsigned long)loaded_vmcs->msr_bitmap);
2610 	WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
2611 }
2612 
2613 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2614 {
2615 	loaded_vmcs->vmcs = alloc_vmcs(false);
2616 	if (!loaded_vmcs->vmcs)
2617 		return -ENOMEM;
2618 
2619 	vmcs_clear(loaded_vmcs->vmcs);
2620 
2621 	loaded_vmcs->shadow_vmcs = NULL;
2622 	loaded_vmcs->hv_timer_soft_disabled = false;
2623 	loaded_vmcs->cpu = -1;
2624 	loaded_vmcs->launched = 0;
2625 
2626 	if (cpu_has_vmx_msr_bitmap()) {
2627 		loaded_vmcs->msr_bitmap = (unsigned long *)
2628 				__get_free_page(GFP_KERNEL_ACCOUNT);
2629 		if (!loaded_vmcs->msr_bitmap)
2630 			goto out_vmcs;
2631 		memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
2632 
2633 		if (IS_ENABLED(CONFIG_HYPERV) &&
2634 		    static_branch_unlikely(&enable_evmcs) &&
2635 		    (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2636 			struct hv_enlightened_vmcs *evmcs =
2637 				(struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2638 
2639 			evmcs->hv_enlightenments_control.msr_bitmap = 1;
2640 		}
2641 	}
2642 
2643 	memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2644 	memset(&loaded_vmcs->controls_shadow, 0,
2645 		sizeof(struct vmcs_controls_shadow));
2646 
2647 	return 0;
2648 
2649 out_vmcs:
2650 	free_loaded_vmcs(loaded_vmcs);
2651 	return -ENOMEM;
2652 }
2653 
2654 static void free_kvm_area(void)
2655 {
2656 	int cpu;
2657 
2658 	for_each_possible_cpu(cpu) {
2659 		free_vmcs(per_cpu(vmxarea, cpu));
2660 		per_cpu(vmxarea, cpu) = NULL;
2661 	}
2662 }
2663 
2664 static __init int alloc_kvm_area(void)
2665 {
2666 	int cpu;
2667 
2668 	for_each_possible_cpu(cpu) {
2669 		struct vmcs *vmcs;
2670 
2671 		vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL);
2672 		if (!vmcs) {
2673 			free_kvm_area();
2674 			return -ENOMEM;
2675 		}
2676 
2677 		/*
2678 		 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2679 		 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2680 		 * revision_id reported by MSR_IA32_VMX_BASIC.
2681 		 *
2682 		 * However, even though not explicitly documented by
2683 		 * TLFS, VMXArea passed as VMXON argument should
2684 		 * still be marked with revision_id reported by
2685 		 * physical CPU.
2686 		 */
2687 		if (static_branch_unlikely(&enable_evmcs))
2688 			vmcs->hdr.revision_id = vmcs_config.revision_id;
2689 
2690 		per_cpu(vmxarea, cpu) = vmcs;
2691 	}
2692 	return 0;
2693 }
2694 
2695 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2696 		struct kvm_segment *save)
2697 {
2698 	if (!emulate_invalid_guest_state) {
2699 		/*
2700 		 * CS and SS RPL should be equal during guest entry according
2701 		 * to VMX spec, but in reality it is not always so. Since vcpu
2702 		 * is in the middle of the transition from real mode to
2703 		 * protected mode it is safe to assume that RPL 0 is a good
2704 		 * default value.
2705 		 */
2706 		if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2707 			save->selector &= ~SEGMENT_RPL_MASK;
2708 		save->dpl = save->selector & SEGMENT_RPL_MASK;
2709 		save->s = 1;
2710 	}
2711 	vmx_set_segment(vcpu, save, seg);
2712 }
2713 
2714 static void enter_pmode(struct kvm_vcpu *vcpu)
2715 {
2716 	unsigned long flags;
2717 	struct vcpu_vmx *vmx = to_vmx(vcpu);
2718 
2719 	/*
2720 	 * Update real mode segment cache. It may be not up-to-date if sement
2721 	 * register was written while vcpu was in a guest mode.
2722 	 */
2723 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2724 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2725 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2726 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2727 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2728 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2729 
2730 	vmx->rmode.vm86_active = 0;
2731 
2732 	vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2733 
2734 	flags = vmcs_readl(GUEST_RFLAGS);
2735 	flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2736 	flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2737 	vmcs_writel(GUEST_RFLAGS, flags);
2738 
2739 	vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2740 			(vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2741 
2742 	update_exception_bitmap(vcpu);
2743 
2744 	fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2745 	fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2746 	fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2747 	fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2748 	fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2749 	fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2750 }
2751 
2752 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2753 {
2754 	const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2755 	struct kvm_segment var = *save;
2756 
2757 	var.dpl = 0x3;
2758 	if (seg == VCPU_SREG_CS)
2759 		var.type = 0x3;
2760 
2761 	if (!emulate_invalid_guest_state) {
2762 		var.selector = var.base >> 4;
2763 		var.base = var.base & 0xffff0;
2764 		var.limit = 0xffff;
2765 		var.g = 0;
2766 		var.db = 0;
2767 		var.present = 1;
2768 		var.s = 1;
2769 		var.l = 0;
2770 		var.unusable = 0;
2771 		var.type = 0x3;
2772 		var.avl = 0;
2773 		if (save->base & 0xf)
2774 			printk_once(KERN_WARNING "kvm: segment base is not "
2775 					"paragraph aligned when entering "
2776 					"protected mode (seg=%d)", seg);
2777 	}
2778 
2779 	vmcs_write16(sf->selector, var.selector);
2780 	vmcs_writel(sf->base, var.base);
2781 	vmcs_write32(sf->limit, var.limit);
2782 	vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2783 }
2784 
2785 static void enter_rmode(struct kvm_vcpu *vcpu)
2786 {
2787 	unsigned long flags;
2788 	struct vcpu_vmx *vmx = to_vmx(vcpu);
2789 	struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
2790 
2791 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2792 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2793 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2794 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2795 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2796 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2797 	vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2798 
2799 	vmx->rmode.vm86_active = 1;
2800 
2801 	/*
2802 	 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2803 	 * vcpu. Warn the user that an update is overdue.
2804 	 */
2805 	if (!kvm_vmx->tss_addr)
2806 		printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2807 			     "called before entering vcpu\n");
2808 
2809 	vmx_segment_cache_clear(vmx);
2810 
2811 	vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
2812 	vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2813 	vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2814 
2815 	flags = vmcs_readl(GUEST_RFLAGS);
2816 	vmx->rmode.save_rflags = flags;
2817 
2818 	flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2819 
2820 	vmcs_writel(GUEST_RFLAGS, flags);
2821 	vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2822 	update_exception_bitmap(vcpu);
2823 
2824 	fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2825 	fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2826 	fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2827 	fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2828 	fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2829 	fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2830 
2831 	kvm_mmu_reset_context(vcpu);
2832 }
2833 
2834 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2835 {
2836 	struct vcpu_vmx *vmx = to_vmx(vcpu);
2837 	struct vmx_uret_msr *msr = vmx_find_uret_msr(vmx, MSR_EFER);
2838 
2839 	/* Nothing to do if hardware doesn't support EFER. */
2840 	if (!msr)
2841 		return 0;
2842 
2843 	vcpu->arch.efer = efer;
2844 	if (efer & EFER_LMA) {
2845 		vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2846 		msr->data = efer;
2847 	} else {
2848 		vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2849 
2850 		msr->data = efer & ~EFER_LME;
2851 	}
2852 	setup_msrs(vmx);
2853 	return 0;
2854 }
2855 
2856 #ifdef CONFIG_X86_64
2857 
2858 static void enter_lmode(struct kvm_vcpu *vcpu)
2859 {
2860 	u32 guest_tr_ar;
2861 
2862 	vmx_segment_cache_clear(to_vmx(vcpu));
2863 
2864 	guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2865 	if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
2866 		pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2867 				     __func__);
2868 		vmcs_write32(GUEST_TR_AR_BYTES,
2869 			     (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2870 			     | VMX_AR_TYPE_BUSY_64_TSS);
2871 	}
2872 	vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2873 }
2874 
2875 static void exit_lmode(struct kvm_vcpu *vcpu)
2876 {
2877 	vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
2878 	vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2879 }
2880 
2881 #endif
2882 
2883 static void vmx_flush_tlb_all(struct kvm_vcpu *vcpu)
2884 {
2885 	struct vcpu_vmx *vmx = to_vmx(vcpu);
2886 
2887 	/*
2888 	 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2889 	 * the CPU is not required to invalidate guest-physical mappings on
2890 	 * VM-Entry, even if VPID is disabled.  Guest-physical mappings are
2891 	 * associated with the root EPT structure and not any particular VPID
2892 	 * (INVVPID also isn't required to invalidate guest-physical mappings).
2893 	 */
2894 	if (enable_ept) {
2895 		ept_sync_global();
2896 	} else if (enable_vpid) {
2897 		if (cpu_has_vmx_invvpid_global()) {
2898 			vpid_sync_vcpu_global();
2899 		} else {
2900 			vpid_sync_vcpu_single(vmx->vpid);
2901 			vpid_sync_vcpu_single(vmx->nested.vpid02);
2902 		}
2903 	}
2904 }
2905 
2906 static void vmx_flush_tlb_current(struct kvm_vcpu *vcpu)
2907 {
2908 	struct kvm_mmu *mmu = vcpu->arch.mmu;
2909 	u64 root_hpa = mmu->root_hpa;
2910 
2911 	/* No flush required if the current context is invalid. */
2912 	if (!VALID_PAGE(root_hpa))
2913 		return;
2914 
2915 	if (enable_ept)
2916 		ept_sync_context(construct_eptp(vcpu, root_hpa,
2917 						mmu->shadow_root_level));
2918 	else if (!is_guest_mode(vcpu))
2919 		vpid_sync_context(to_vmx(vcpu)->vpid);
2920 	else
2921 		vpid_sync_context(nested_get_vpid02(vcpu));
2922 }
2923 
2924 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2925 {
2926 	/*
2927 	 * vpid_sync_vcpu_addr() is a nop if vmx->vpid==0, see the comment in
2928 	 * vmx_flush_tlb_guest() for an explanation of why this is ok.
2929 	 */
2930 	vpid_sync_vcpu_addr(to_vmx(vcpu)->vpid, addr);
2931 }
2932 
2933 static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
2934 {
2935 	/*
2936 	 * vpid_sync_context() is a nop if vmx->vpid==0, e.g. if enable_vpid==0
2937 	 * or a vpid couldn't be allocated for this vCPU.  VM-Enter and VM-Exit
2938 	 * are required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2939 	 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2940 	 * i.e. no explicit INVVPID is necessary.
2941 	 */
2942 	vpid_sync_context(to_vmx(vcpu)->vpid);
2943 }
2944 
2945 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu)
2946 {
2947 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2948 
2949 	if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
2950 		return;
2951 
2952 	if (is_pae_paging(vcpu)) {
2953 		vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2954 		vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2955 		vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2956 		vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
2957 	}
2958 }
2959 
2960 void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2961 {
2962 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2963 
2964 	if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
2965 		return;
2966 
2967 	mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2968 	mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2969 	mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2970 	mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2971 
2972 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
2973 }
2974 
2975 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2976 					unsigned long cr0,
2977 					struct kvm_vcpu *vcpu)
2978 {
2979 	struct vcpu_vmx *vmx = to_vmx(vcpu);
2980 
2981 	if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
2982 		vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
2983 	if (!(cr0 & X86_CR0_PG)) {
2984 		/* From paging/starting to nonpaging */
2985 		exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2986 					  CPU_BASED_CR3_STORE_EXITING);
2987 		vcpu->arch.cr0 = cr0;
2988 		vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2989 	} else if (!is_paging(vcpu)) {
2990 		/* From nonpaging to paging */
2991 		exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING |
2992 					    CPU_BASED_CR3_STORE_EXITING);
2993 		vcpu->arch.cr0 = cr0;
2994 		vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2995 	}
2996 
2997 	if (!(cr0 & X86_CR0_WP))
2998 		*hw_cr0 &= ~X86_CR0_WP;
2999 }
3000 
3001 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3002 {
3003 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3004 	unsigned long hw_cr0;
3005 
3006 	hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3007 	if (is_unrestricted_guest(vcpu))
3008 		hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3009 	else {
3010 		hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3011 
3012 		if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3013 			enter_pmode(vcpu);
3014 
3015 		if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3016 			enter_rmode(vcpu);
3017 	}
3018 
3019 #ifdef CONFIG_X86_64
3020 	if (vcpu->arch.efer & EFER_LME) {
3021 		if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3022 			enter_lmode(vcpu);
3023 		if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3024 			exit_lmode(vcpu);
3025 	}
3026 #endif
3027 
3028 	if (enable_ept && !is_unrestricted_guest(vcpu))
3029 		ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3030 
3031 	vmcs_writel(CR0_READ_SHADOW, cr0);
3032 	vmcs_writel(GUEST_CR0, hw_cr0);
3033 	vcpu->arch.cr0 = cr0;
3034 	kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
3035 
3036 	/* depends on vcpu->arch.cr0 to be set to a new value */
3037 	vmx->emulation_required = emulation_required(vcpu);
3038 }
3039 
3040 static int vmx_get_max_tdp_level(void)
3041 {
3042 	if (cpu_has_vmx_ept_5levels())
3043 		return 5;
3044 	return 4;
3045 }
3046 
3047 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
3048 		   int root_level)
3049 {
3050 	u64 eptp = VMX_EPTP_MT_WB;
3051 
3052 	eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
3053 
3054 	if (enable_ept_ad_bits &&
3055 	    (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
3056 		eptp |= VMX_EPTP_AD_ENABLE_BIT;
3057 	eptp |= (root_hpa & PAGE_MASK);
3058 
3059 	return eptp;
3060 }
3061 
3062 static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long pgd,
3063 			     int pgd_level)
3064 {
3065 	struct kvm *kvm = vcpu->kvm;
3066 	bool update_guest_cr3 = true;
3067 	unsigned long guest_cr3;
3068 	u64 eptp;
3069 
3070 	if (enable_ept) {
3071 		eptp = construct_eptp(vcpu, pgd, pgd_level);
3072 		vmcs_write64(EPT_POINTER, eptp);
3073 
3074 		if (kvm_x86_ops.tlb_remote_flush) {
3075 			spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3076 			to_vmx(vcpu)->ept_pointer = eptp;
3077 			to_kvm_vmx(kvm)->ept_pointers_match
3078 				= EPT_POINTERS_CHECK;
3079 			spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
3080 		}
3081 
3082 		if (!enable_unrestricted_guest && !is_paging(vcpu))
3083 			guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
3084 		else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3085 			guest_cr3 = vcpu->arch.cr3;
3086 		else /* vmcs01.GUEST_CR3 is already up-to-date. */
3087 			update_guest_cr3 = false;
3088 		vmx_ept_load_pdptrs(vcpu);
3089 	} else {
3090 		guest_cr3 = pgd;
3091 	}
3092 
3093 	if (update_guest_cr3)
3094 		vmcs_writel(GUEST_CR3, guest_cr3);
3095 }
3096 
3097 static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3098 {
3099 	/*
3100 	 * We operate under the default treatment of SMM, so VMX cannot be
3101 	 * enabled under SMM.  Note, whether or not VMXE is allowed at all is
3102 	 * handled by kvm_is_valid_cr4().
3103 	 */
3104 	if ((cr4 & X86_CR4_VMXE) && is_smm(vcpu))
3105 		return false;
3106 
3107 	if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
3108 		return false;
3109 
3110 	return true;
3111 }
3112 
3113 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3114 {
3115 	unsigned long old_cr4 = vcpu->arch.cr4;
3116 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3117 	/*
3118 	 * Pass through host's Machine Check Enable value to hw_cr4, which
3119 	 * is in force while we are in guest mode.  Do not let guests control
3120 	 * this bit, even if host CR4.MCE == 0.
3121 	 */
3122 	unsigned long hw_cr4;
3123 
3124 	hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
3125 	if (is_unrestricted_guest(vcpu))
3126 		hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
3127 	else if (vmx->rmode.vm86_active)
3128 		hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
3129 	else
3130 		hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
3131 
3132 	if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
3133 		if (cr4 & X86_CR4_UMIP) {
3134 			secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
3135 			hw_cr4 &= ~X86_CR4_UMIP;
3136 		} else if (!is_guest_mode(vcpu) ||
3137 			!nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
3138 			secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
3139 		}
3140 	}
3141 
3142 	vcpu->arch.cr4 = cr4;
3143 	kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
3144 
3145 	if (!is_unrestricted_guest(vcpu)) {
3146 		if (enable_ept) {
3147 			if (!is_paging(vcpu)) {
3148 				hw_cr4 &= ~X86_CR4_PAE;
3149 				hw_cr4 |= X86_CR4_PSE;
3150 			} else if (!(cr4 & X86_CR4_PAE)) {
3151 				hw_cr4 &= ~X86_CR4_PAE;
3152 			}
3153 		}
3154 
3155 		/*
3156 		 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3157 		 * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3158 		 * to be manually disabled when guest switches to non-paging
3159 		 * mode.
3160 		 *
3161 		 * If !enable_unrestricted_guest, the CPU is always running
3162 		 * with CR0.PG=1 and CR4 needs to be modified.
3163 		 * If enable_unrestricted_guest, the CPU automatically
3164 		 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3165 		 */
3166 		if (!is_paging(vcpu))
3167 			hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3168 	}
3169 
3170 	vmcs_writel(CR4_READ_SHADOW, cr4);
3171 	vmcs_writel(GUEST_CR4, hw_cr4);
3172 
3173 	if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
3174 		kvm_update_cpuid_runtime(vcpu);
3175 }
3176 
3177 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3178 {
3179 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3180 	u32 ar;
3181 
3182 	if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3183 		*var = vmx->rmode.segs[seg];
3184 		if (seg == VCPU_SREG_TR
3185 		    || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3186 			return;
3187 		var->base = vmx_read_guest_seg_base(vmx, seg);
3188 		var->selector = vmx_read_guest_seg_selector(vmx, seg);
3189 		return;
3190 	}
3191 	var->base = vmx_read_guest_seg_base(vmx, seg);
3192 	var->limit = vmx_read_guest_seg_limit(vmx, seg);
3193 	var->selector = vmx_read_guest_seg_selector(vmx, seg);
3194 	ar = vmx_read_guest_seg_ar(vmx, seg);
3195 	var->unusable = (ar >> 16) & 1;
3196 	var->type = ar & 15;
3197 	var->s = (ar >> 4) & 1;
3198 	var->dpl = (ar >> 5) & 3;
3199 	/*
3200 	 * Some userspaces do not preserve unusable property. Since usable
3201 	 * segment has to be present according to VMX spec we can use present
3202 	 * property to amend userspace bug by making unusable segment always
3203 	 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3204 	 * segment as unusable.
3205 	 */
3206 	var->present = !var->unusable;
3207 	var->avl = (ar >> 12) & 1;
3208 	var->l = (ar >> 13) & 1;
3209 	var->db = (ar >> 14) & 1;
3210 	var->g = (ar >> 15) & 1;
3211 }
3212 
3213 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3214 {
3215 	struct kvm_segment s;
3216 
3217 	if (to_vmx(vcpu)->rmode.vm86_active) {
3218 		vmx_get_segment(vcpu, &s, seg);
3219 		return s.base;
3220 	}
3221 	return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3222 }
3223 
3224 int vmx_get_cpl(struct kvm_vcpu *vcpu)
3225 {
3226 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3227 
3228 	if (unlikely(vmx->rmode.vm86_active))
3229 		return 0;
3230 	else {
3231 		int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3232 		return VMX_AR_DPL(ar);
3233 	}
3234 }
3235 
3236 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3237 {
3238 	u32 ar;
3239 
3240 	if (var->unusable || !var->present)
3241 		ar = 1 << 16;
3242 	else {
3243 		ar = var->type & 15;
3244 		ar |= (var->s & 1) << 4;
3245 		ar |= (var->dpl & 3) << 5;
3246 		ar |= (var->present & 1) << 7;
3247 		ar |= (var->avl & 1) << 12;
3248 		ar |= (var->l & 1) << 13;
3249 		ar |= (var->db & 1) << 14;
3250 		ar |= (var->g & 1) << 15;
3251 	}
3252 
3253 	return ar;
3254 }
3255 
3256 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
3257 {
3258 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3259 	const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3260 
3261 	vmx_segment_cache_clear(vmx);
3262 
3263 	if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3264 		vmx->rmode.segs[seg] = *var;
3265 		if (seg == VCPU_SREG_TR)
3266 			vmcs_write16(sf->selector, var->selector);
3267 		else if (var->s)
3268 			fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3269 		goto out;
3270 	}
3271 
3272 	vmcs_writel(sf->base, var->base);
3273 	vmcs_write32(sf->limit, var->limit);
3274 	vmcs_write16(sf->selector, var->selector);
3275 
3276 	/*
3277 	 *   Fix the "Accessed" bit in AR field of segment registers for older
3278 	 * qemu binaries.
3279 	 *   IA32 arch specifies that at the time of processor reset the
3280 	 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3281 	 * is setting it to 0 in the userland code. This causes invalid guest
3282 	 * state vmexit when "unrestricted guest" mode is turned on.
3283 	 *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3284 	 * tree. Newer qemu binaries with that qemu fix would not need this
3285 	 * kvm hack.
3286 	 */
3287 	if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
3288 		var->type |= 0x1; /* Accessed */
3289 
3290 	vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3291 
3292 out:
3293 	vmx->emulation_required = emulation_required(vcpu);
3294 }
3295 
3296 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3297 {
3298 	u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3299 
3300 	*db = (ar >> 14) & 1;
3301 	*l = (ar >> 13) & 1;
3302 }
3303 
3304 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3305 {
3306 	dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3307 	dt->address = vmcs_readl(GUEST_IDTR_BASE);
3308 }
3309 
3310 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3311 {
3312 	vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3313 	vmcs_writel(GUEST_IDTR_BASE, dt->address);
3314 }
3315 
3316 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3317 {
3318 	dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3319 	dt->address = vmcs_readl(GUEST_GDTR_BASE);
3320 }
3321 
3322 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3323 {
3324 	vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3325 	vmcs_writel(GUEST_GDTR_BASE, dt->address);
3326 }
3327 
3328 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3329 {
3330 	struct kvm_segment var;
3331 	u32 ar;
3332 
3333 	vmx_get_segment(vcpu, &var, seg);
3334 	var.dpl = 0x3;
3335 	if (seg == VCPU_SREG_CS)
3336 		var.type = 0x3;
3337 	ar = vmx_segment_access_rights(&var);
3338 
3339 	if (var.base != (var.selector << 4))
3340 		return false;
3341 	if (var.limit != 0xffff)
3342 		return false;
3343 	if (ar != 0xf3)
3344 		return false;
3345 
3346 	return true;
3347 }
3348 
3349 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3350 {
3351 	struct kvm_segment cs;
3352 	unsigned int cs_rpl;
3353 
3354 	vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3355 	cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3356 
3357 	if (cs.unusable)
3358 		return false;
3359 	if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3360 		return false;
3361 	if (!cs.s)
3362 		return false;
3363 	if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3364 		if (cs.dpl > cs_rpl)
3365 			return false;
3366 	} else {
3367 		if (cs.dpl != cs_rpl)
3368 			return false;
3369 	}
3370 	if (!cs.present)
3371 		return false;
3372 
3373 	/* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3374 	return true;
3375 }
3376 
3377 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3378 {
3379 	struct kvm_segment ss;
3380 	unsigned int ss_rpl;
3381 
3382 	vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3383 	ss_rpl = ss.selector & SEGMENT_RPL_MASK;
3384 
3385 	if (ss.unusable)
3386 		return true;
3387 	if (ss.type != 3 && ss.type != 7)
3388 		return false;
3389 	if (!ss.s)
3390 		return false;
3391 	if (ss.dpl != ss_rpl) /* DPL != RPL */
3392 		return false;
3393 	if (!ss.present)
3394 		return false;
3395 
3396 	return true;
3397 }
3398 
3399 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3400 {
3401 	struct kvm_segment var;
3402 	unsigned int rpl;
3403 
3404 	vmx_get_segment(vcpu, &var, seg);
3405 	rpl = var.selector & SEGMENT_RPL_MASK;
3406 
3407 	if (var.unusable)
3408 		return true;
3409 	if (!var.s)
3410 		return false;
3411 	if (!var.present)
3412 		return false;
3413 	if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
3414 		if (var.dpl < rpl) /* DPL < RPL */
3415 			return false;
3416 	}
3417 
3418 	/* TODO: Add other members to kvm_segment_field to allow checking for other access
3419 	 * rights flags
3420 	 */
3421 	return true;
3422 }
3423 
3424 static bool tr_valid(struct kvm_vcpu *vcpu)
3425 {
3426 	struct kvm_segment tr;
3427 
3428 	vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3429 
3430 	if (tr.unusable)
3431 		return false;
3432 	if (tr.selector & SEGMENT_TI_MASK)	/* TI = 1 */
3433 		return false;
3434 	if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3435 		return false;
3436 	if (!tr.present)
3437 		return false;
3438 
3439 	return true;
3440 }
3441 
3442 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3443 {
3444 	struct kvm_segment ldtr;
3445 
3446 	vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3447 
3448 	if (ldtr.unusable)
3449 		return true;
3450 	if (ldtr.selector & SEGMENT_TI_MASK)	/* TI = 1 */
3451 		return false;
3452 	if (ldtr.type != 2)
3453 		return false;
3454 	if (!ldtr.present)
3455 		return false;
3456 
3457 	return true;
3458 }
3459 
3460 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3461 {
3462 	struct kvm_segment cs, ss;
3463 
3464 	vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3465 	vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3466 
3467 	return ((cs.selector & SEGMENT_RPL_MASK) ==
3468 		 (ss.selector & SEGMENT_RPL_MASK));
3469 }
3470 
3471 /*
3472  * Check if guest state is valid. Returns true if valid, false if
3473  * not.
3474  * We assume that registers are always usable
3475  */
3476 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu)
3477 {
3478 	/* real mode guest state checks */
3479 	if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3480 		if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3481 			return false;
3482 		if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3483 			return false;
3484 		if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3485 			return false;
3486 		if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3487 			return false;
3488 		if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3489 			return false;
3490 		if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3491 			return false;
3492 	} else {
3493 	/* protected mode guest state checks */
3494 		if (!cs_ss_rpl_check(vcpu))
3495 			return false;
3496 		if (!code_segment_valid(vcpu))
3497 			return false;
3498 		if (!stack_segment_valid(vcpu))
3499 			return false;
3500 		if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3501 			return false;
3502 		if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3503 			return false;
3504 		if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3505 			return false;
3506 		if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3507 			return false;
3508 		if (!tr_valid(vcpu))
3509 			return false;
3510 		if (!ldtr_valid(vcpu))
3511 			return false;
3512 	}
3513 	/* TODO:
3514 	 * - Add checks on RIP
3515 	 * - Add checks on RFLAGS
3516 	 */
3517 
3518 	return true;
3519 }
3520 
3521 static int init_rmode_tss(struct kvm *kvm, void __user *ua)
3522 {
3523 	const void *zero_page = (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3524 	u16 data;
3525 	int i;
3526 
3527 	for (i = 0; i < 3; i++) {
3528 		if (__copy_to_user(ua + PAGE_SIZE * i, zero_page, PAGE_SIZE))
3529 			return -EFAULT;
3530 	}
3531 
3532 	data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3533 	if (__copy_to_user(ua + TSS_IOPB_BASE_OFFSET, &data, sizeof(u16)))
3534 		return -EFAULT;
3535 
3536 	data = ~0;
3537 	if (__copy_to_user(ua + RMODE_TSS_SIZE - 1, &data, sizeof(u8)))
3538 		return -EFAULT;
3539 
3540 	return 0;
3541 }
3542 
3543 static int init_rmode_identity_map(struct kvm *kvm)
3544 {
3545 	struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
3546 	int i, r = 0;
3547 	void __user *uaddr;
3548 	u32 tmp;
3549 
3550 	/* Protect kvm_vmx->ept_identity_pagetable_done. */
3551 	mutex_lock(&kvm->slots_lock);
3552 
3553 	if (likely(kvm_vmx->ept_identity_pagetable_done))
3554 		goto out;
3555 
3556 	if (!kvm_vmx->ept_identity_map_addr)
3557 		kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3558 
3559 	uaddr = __x86_set_memory_region(kvm,
3560 					IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
3561 					kvm_vmx->ept_identity_map_addr,
3562 					PAGE_SIZE);
3563 	if (IS_ERR(uaddr)) {
3564 		r = PTR_ERR(uaddr);
3565 		goto out;
3566 	}
3567 
3568 	/* Set up identity-mapping pagetable for EPT in real mode */
3569 	for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3570 		tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3571 			_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3572 		if (__copy_to_user(uaddr + i * sizeof(tmp), &tmp, sizeof(tmp))) {
3573 			r = -EFAULT;
3574 			goto out;
3575 		}
3576 	}
3577 	kvm_vmx->ept_identity_pagetable_done = true;
3578 
3579 out:
3580 	mutex_unlock(&kvm->slots_lock);
3581 	return r;
3582 }
3583 
3584 static void seg_setup(int seg)
3585 {
3586 	const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3587 	unsigned int ar;
3588 
3589 	vmcs_write16(sf->selector, 0);
3590 	vmcs_writel(sf->base, 0);
3591 	vmcs_write32(sf->limit, 0xffff);
3592 	ar = 0x93;
3593 	if (seg == VCPU_SREG_CS)
3594 		ar |= 0x08; /* code segment */
3595 
3596 	vmcs_write32(sf->ar_bytes, ar);
3597 }
3598 
3599 static int alloc_apic_access_page(struct kvm *kvm)
3600 {
3601 	struct page *page;
3602 	void __user *hva;
3603 	int ret = 0;
3604 
3605 	mutex_lock(&kvm->slots_lock);
3606 	if (kvm->arch.apic_access_page_done)
3607 		goto out;
3608 	hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3609 				      APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
3610 	if (IS_ERR(hva)) {
3611 		ret = PTR_ERR(hva);
3612 		goto out;
3613 	}
3614 
3615 	page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3616 	if (is_error_page(page)) {
3617 		ret = -EFAULT;
3618 		goto out;
3619 	}
3620 
3621 	/*
3622 	 * Do not pin the page in memory, so that memory hot-unplug
3623 	 * is able to migrate it.
3624 	 */
3625 	put_page(page);
3626 	kvm->arch.apic_access_page_done = true;
3627 out:
3628 	mutex_unlock(&kvm->slots_lock);
3629 	return ret;
3630 }
3631 
3632 int allocate_vpid(void)
3633 {
3634 	int vpid;
3635 
3636 	if (!enable_vpid)
3637 		return 0;
3638 	spin_lock(&vmx_vpid_lock);
3639 	vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3640 	if (vpid < VMX_NR_VPIDS)
3641 		__set_bit(vpid, vmx_vpid_bitmap);
3642 	else
3643 		vpid = 0;
3644 	spin_unlock(&vmx_vpid_lock);
3645 	return vpid;
3646 }
3647 
3648 void free_vpid(int vpid)
3649 {
3650 	if (!enable_vpid || vpid == 0)
3651 		return;
3652 	spin_lock(&vmx_vpid_lock);
3653 	__clear_bit(vpid, vmx_vpid_bitmap);
3654 	spin_unlock(&vmx_vpid_lock);
3655 }
3656 
3657 static void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3658 {
3659 	int f = sizeof(unsigned long);
3660 
3661 	if (msr <= 0x1fff)
3662 		__clear_bit(msr, msr_bitmap + 0x000 / f);
3663 	else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3664 		__clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3665 }
3666 
3667 static void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3668 {
3669 	int f = sizeof(unsigned long);
3670 
3671 	if (msr <= 0x1fff)
3672 		__clear_bit(msr, msr_bitmap + 0x800 / f);
3673 	else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3674 		__clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3675 }
3676 
3677 static void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
3678 {
3679 	int f = sizeof(unsigned long);
3680 
3681 	if (msr <= 0x1fff)
3682 		__set_bit(msr, msr_bitmap + 0x000 / f);
3683 	else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3684 		__set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
3685 }
3686 
3687 static void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
3688 {
3689 	int f = sizeof(unsigned long);
3690 
3691 	if (msr <= 0x1fff)
3692 		__set_bit(msr, msr_bitmap + 0x800 / f);
3693 	else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
3694 		__set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
3695 }
3696 
3697 static __always_inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu,
3698 							  u32 msr, int type)
3699 {
3700 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3701 	unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3702 
3703 	if (!cpu_has_vmx_msr_bitmap())
3704 		return;
3705 
3706 	if (static_branch_unlikely(&enable_evmcs))
3707 		evmcs_touch_msr_bitmap();
3708 
3709 	/*
3710 	 * Mark the desired intercept state in shadow bitmap, this is needed
3711 	 * for resync when the MSR filters change.
3712 	*/
3713 	if (is_valid_passthrough_msr(msr)) {
3714 		int idx = possible_passthrough_msr_slot(msr);
3715 
3716 		if (idx != -ENOENT) {
3717 			if (type & MSR_TYPE_R)
3718 				clear_bit(idx, vmx->shadow_msr_intercept.read);
3719 			if (type & MSR_TYPE_W)
3720 				clear_bit(idx, vmx->shadow_msr_intercept.write);
3721 		}
3722 	}
3723 
3724 	if ((type & MSR_TYPE_R) &&
3725 	    !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
3726 		vmx_set_msr_bitmap_read(msr_bitmap, msr);
3727 		type &= ~MSR_TYPE_R;
3728 	}
3729 
3730 	if ((type & MSR_TYPE_W) &&
3731 	    !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
3732 		vmx_set_msr_bitmap_write(msr_bitmap, msr);
3733 		type &= ~MSR_TYPE_W;
3734 	}
3735 
3736 	if (type & MSR_TYPE_R)
3737 		vmx_clear_msr_bitmap_read(msr_bitmap, msr);
3738 
3739 	if (type & MSR_TYPE_W)
3740 		vmx_clear_msr_bitmap_write(msr_bitmap, msr);
3741 }
3742 
3743 static __always_inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu,
3744 							 u32 msr, int type)
3745 {
3746 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3747 	unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3748 
3749 	if (!cpu_has_vmx_msr_bitmap())
3750 		return;
3751 
3752 	if (static_branch_unlikely(&enable_evmcs))
3753 		evmcs_touch_msr_bitmap();
3754 
3755 	/*
3756 	 * Mark the desired intercept state in shadow bitmap, this is needed
3757 	 * for resync when the MSR filter changes.
3758 	*/
3759 	if (is_valid_passthrough_msr(msr)) {
3760 		int idx = possible_passthrough_msr_slot(msr);
3761 
3762 		if (idx != -ENOENT) {
3763 			if (type & MSR_TYPE_R)
3764 				set_bit(idx, vmx->shadow_msr_intercept.read);
3765 			if (type & MSR_TYPE_W)
3766 				set_bit(idx, vmx->shadow_msr_intercept.write);
3767 		}
3768 	}
3769 
3770 	if (type & MSR_TYPE_R)
3771 		vmx_set_msr_bitmap_read(msr_bitmap, msr);
3772 
3773 	if (type & MSR_TYPE_W)
3774 		vmx_set_msr_bitmap_write(msr_bitmap, msr);
3775 }
3776 
3777 static __always_inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu,
3778 						      u32 msr, int type, bool value)
3779 {
3780 	if (value)
3781 		vmx_enable_intercept_for_msr(vcpu, msr, type);
3782 	else
3783 		vmx_disable_intercept_for_msr(vcpu, msr, type);
3784 }
3785 
3786 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
3787 {
3788 	u8 mode = 0;
3789 
3790 	if (cpu_has_secondary_exec_ctrls() &&
3791 	    (secondary_exec_controls_get(to_vmx(vcpu)) &
3792 	     SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3793 		mode |= MSR_BITMAP_MODE_X2APIC;
3794 		if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3795 			mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3796 	}
3797 
3798 	return mode;
3799 }
3800 
3801 static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
3802 {
3803 	unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
3804 	unsigned long read_intercept;
3805 	int msr;
3806 
3807 	read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3808 
3809 	for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3810 		unsigned int read_idx = msr / BITS_PER_LONG;
3811 		unsigned int write_idx = read_idx + (0x800 / sizeof(long));
3812 
3813 		msr_bitmap[read_idx] = read_intercept;
3814 		msr_bitmap[write_idx] = ~0ul;
3815 	}
3816 }
3817 
3818 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu, u8 mode)
3819 {
3820 	if (!cpu_has_vmx_msr_bitmap())
3821 		return;
3822 
3823 	vmx_reset_x2apic_msrs(vcpu, mode);
3824 
3825 	/*
3826 	 * TPR reads and writes can be virtualized even if virtual interrupt
3827 	 * delivery is not in use.
3828 	 */
3829 	vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
3830 				  !(mode & MSR_BITMAP_MODE_X2APIC));
3831 
3832 	if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3833 		vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW);
3834 		vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3835 		vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3836 	}
3837 }
3838 
3839 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
3840 {
3841 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3842 	u8 mode = vmx_msr_bitmap_mode(vcpu);
3843 	u8 changed = mode ^ vmx->msr_bitmap_mode;
3844 
3845 	if (!changed)
3846 		return;
3847 
3848 	if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3849 		vmx_update_msr_bitmap_x2apic(vcpu, mode);
3850 
3851 	vmx->msr_bitmap_mode = mode;
3852 }
3853 
3854 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu)
3855 {
3856 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3857 	bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
3858 	u32 i;
3859 
3860 	vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
3861 	vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
3862 	vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
3863 	vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
3864 	for (i = 0; i < vmx->pt_desc.addr_range; i++) {
3865 		vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
3866 		vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
3867 	}
3868 }
3869 
3870 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3871 {
3872 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3873 	void *vapic_page;
3874 	u32 vppr;
3875 	int rvi;
3876 
3877 	if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3878 		!nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3879 		WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn))
3880 		return false;
3881 
3882 	rvi = vmx_get_rvi();
3883 
3884 	vapic_page = vmx->nested.virtual_apic_map.hva;
3885 	vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3886 
3887 	return ((rvi & 0xf0) > (vppr & 0xf0));
3888 }
3889 
3890 static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
3891 {
3892 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3893 	u32 i;
3894 
3895 	/*
3896 	 * Set intercept permissions for all potentially passed through MSRs
3897 	 * again. They will automatically get filtered through the MSR filter,
3898 	 * so we are back in sync after this.
3899 	 */
3900 	for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
3901 		u32 msr = vmx_possible_passthrough_msrs[i];
3902 		bool read = test_bit(i, vmx->shadow_msr_intercept.read);
3903 		bool write = test_bit(i, vmx->shadow_msr_intercept.write);
3904 
3905 		vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
3906 		vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
3907 	}
3908 
3909 	pt_update_intercept_for_msr(vcpu);
3910 	vmx_update_msr_bitmap_x2apic(vcpu, vmx_msr_bitmap_mode(vcpu));
3911 }
3912 
3913 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3914 						     bool nested)
3915 {
3916 #ifdef CONFIG_SMP
3917 	int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3918 
3919 	if (vcpu->mode == IN_GUEST_MODE) {
3920 		/*
3921 		 * The vector of interrupt to be delivered to vcpu had
3922 		 * been set in PIR before this function.
3923 		 *
3924 		 * Following cases will be reached in this block, and
3925 		 * we always send a notification event in all cases as
3926 		 * explained below.
3927 		 *
3928 		 * Case 1: vcpu keeps in non-root mode. Sending a
3929 		 * notification event posts the interrupt to vcpu.
3930 		 *
3931 		 * Case 2: vcpu exits to root mode and is still
3932 		 * runnable. PIR will be synced to vIRR before the
3933 		 * next vcpu entry. Sending a notification event in
3934 		 * this case has no effect, as vcpu is not in root
3935 		 * mode.
3936 		 *
3937 		 * Case 3: vcpu exits to root mode and is blocked.
3938 		 * vcpu_block() has already synced PIR to vIRR and
3939 		 * never blocks vcpu if vIRR is not cleared. Therefore,
3940 		 * a blocked vcpu here does not wait for any requested
3941 		 * interrupts in PIR, and sending a notification event
3942 		 * which has no effect is safe here.
3943 		 */
3944 
3945 		apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
3946 		return true;
3947 	}
3948 #endif
3949 	return false;
3950 }
3951 
3952 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3953 						int vector)
3954 {
3955 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3956 
3957 	if (is_guest_mode(vcpu) &&
3958 	    vector == vmx->nested.posted_intr_nv) {
3959 		/*
3960 		 * If a posted intr is not recognized by hardware,
3961 		 * we will accomplish it in the next vmentry.
3962 		 */
3963 		vmx->nested.pi_pending = true;
3964 		kvm_make_request(KVM_REQ_EVENT, vcpu);
3965 		/* the PIR and ON have been set by L1. */
3966 		if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3967 			kvm_vcpu_kick(vcpu);
3968 		return 0;
3969 	}
3970 	return -1;
3971 }
3972 /*
3973  * Send interrupt to vcpu via posted interrupt way.
3974  * 1. If target vcpu is running(non-root mode), send posted interrupt
3975  * notification to vcpu and hardware will sync PIR to vIRR atomically.
3976  * 2. If target vcpu isn't running(root mode), kick it to pick up the
3977  * interrupt from PIR in next vmentry.
3978  */
3979 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3980 {
3981 	struct vcpu_vmx *vmx = to_vmx(vcpu);
3982 	int r;
3983 
3984 	r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3985 	if (!r)
3986 		return 0;
3987 
3988 	if (!vcpu->arch.apicv_active)
3989 		return -1;
3990 
3991 	if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3992 		return 0;
3993 
3994 	/* If a previous notification has sent the IPI, nothing to do.  */
3995 	if (pi_test_and_set_on(&vmx->pi_desc))
3996 		return 0;
3997 
3998 	if (vcpu != kvm_get_running_vcpu() &&
3999 	    !kvm_vcpu_trigger_posted_interrupt(vcpu, false))
4000 		kvm_vcpu_kick(vcpu);
4001 
4002 	return 0;
4003 }
4004 
4005 /*
4006  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4007  * will not change in the lifetime of the guest.
4008  * Note that host-state that does change is set elsewhere. E.g., host-state
4009  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4010  */
4011 void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4012 {
4013 	u32 low32, high32;
4014 	unsigned long tmpl;
4015 	unsigned long cr0, cr3, cr4;
4016 
4017 	cr0 = read_cr0();
4018 	WARN_ON(cr0 & X86_CR0_TS);
4019 	vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
4020 
4021 	/*
4022 	 * Save the most likely value for this task's CR3 in the VMCS.
4023 	 * We can't use __get_current_cr3_fast() because we're not atomic.
4024 	 */
4025 	cr3 = __read_cr3();
4026 	vmcs_writel(HOST_CR3, cr3);		/* 22.2.3  FIXME: shadow tables */
4027 	vmx->loaded_vmcs->host_state.cr3 = cr3;
4028 
4029 	/* Save the most likely value for this task's CR4 in the VMCS. */
4030 	cr4 = cr4_read_shadow();
4031 	vmcs_writel(HOST_CR4, cr4);			/* 22.2.3, 22.2.5 */
4032 	vmx->loaded_vmcs->host_state.cr4 = cr4;
4033 
4034 	vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4035 #ifdef CONFIG_X86_64
4036 	/*
4037 	 * Load null selectors, so we can avoid reloading them in
4038 	 * vmx_prepare_switch_to_host(), in case userspace uses
4039 	 * the null selectors too (the expected case).
4040 	 */
4041 	vmcs_write16(HOST_DS_SELECTOR, 0);
4042 	vmcs_write16(HOST_ES_SELECTOR, 0);
4043 #else
4044 	vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4045 	vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4046 #endif
4047 	vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4048 	vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4049 
4050 	vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
4051 
4052 	vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
4053 
4054 	rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4055 	vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4056 	rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4057 	vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4058 
4059 	if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4060 		rdmsr(MSR_IA32_CR_PAT, low32, high32);
4061 		vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4062 	}
4063 
4064 	if (cpu_has_load_ia32_efer())
4065 		vmcs_write64(HOST_IA32_EFER, host_efer);
4066 }
4067 
4068 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4069 {
4070 	struct kvm_vcpu *vcpu = &vmx->vcpu;
4071 
4072 	vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
4073 					  ~vcpu->arch.cr4_guest_rsvd_bits;
4074 	if (!enable_ept)
4075 		vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PGE;
4076 	if (is_guest_mode(&vmx->vcpu))
4077 		vcpu->arch.cr4_guest_owned_bits &=
4078 			~get_vmcs12(vcpu)->cr4_guest_host_mask;
4079 	vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
4080 }
4081 
4082 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4083 {
4084 	u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4085 
4086 	if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4087 		pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4088 
4089 	if (!enable_vnmi)
4090 		pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
4091 
4092 	if (!enable_preemption_timer)
4093 		pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4094 
4095 	return pin_based_exec_ctrl;
4096 }
4097 
4098 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4099 {
4100 	struct vcpu_vmx *vmx = to_vmx(vcpu);
4101 
4102 	pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4103 	if (cpu_has_secondary_exec_ctrls()) {
4104 		if (kvm_vcpu_apicv_active(vcpu))
4105 			secondary_exec_controls_setbit(vmx,
4106 				      SECONDARY_EXEC_APIC_REGISTER_VIRT |
4107 				      SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4108 		else
4109 			secondary_exec_controls_clearbit(vmx,
4110 					SECONDARY_EXEC_APIC_REGISTER_VIRT |
4111 					SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4112 	}
4113 
4114 	if (cpu_has_vmx_msr_bitmap())
4115 		vmx_update_msr_bitmap(vcpu);
4116 }
4117 
4118 u32 vmx_exec_control(struct vcpu_vmx *vmx)
4119 {
4120 	u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4121 
4122 	if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4123 		exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4124 
4125 	if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4126 		exec_control &= ~CPU_BASED_TPR_SHADOW;
4127 #ifdef CONFIG_X86_64
4128 		exec_control |= CPU_BASED_CR8_STORE_EXITING |
4129 				CPU_BASED_CR8_LOAD_EXITING;
4130 #endif
4131 	}
4132 	if (!enable_ept)
4133 		exec_control |= CPU_BASED_CR3_STORE_EXITING |
4134 				CPU_BASED_CR3_LOAD_EXITING  |
4135 				CPU_BASED_INVLPG_EXITING;
4136 	if (kvm_mwait_in_guest(vmx->vcpu.kvm))
4137 		exec_control &= ~(CPU_BASED_MWAIT_EXITING |
4138 				CPU_BASED_MONITOR_EXITING);
4139 	if (kvm_hlt_in_guest(vmx->vcpu.kvm))
4140 		exec_control &= ~CPU_BASED_HLT_EXITING;
4141 	return exec_control;
4142 }
4143 
4144 /*
4145  * Adjust a single secondary execution control bit to intercept/allow an
4146  * instruction in the guest.  This is usually done based on whether or not a
4147  * feature has been exposed to the guest in order to correctly emulate faults.
4148  */
4149 static inline void
4150 vmx_adjust_secondary_exec_control(struct vcpu_vmx *vmx, u32 *exec_control,
4151 				  u32 control, bool enabled, bool exiting)
4152 {
4153 	/*
4154 	 * If the control is for an opt-in feature, clear the control if the
4155 	 * feature is not exposed to the guest, i.e. not enabled.  If the
4156 	 * control is opt-out, i.e. an exiting control, clear the control if
4157 	 * the feature _is_ exposed to the guest, i.e. exiting/interception is
4158 	 * disabled for the associated instruction.  Note, the caller is
4159 	 * responsible presetting exec_control to set all supported bits.
4160 	 */
4161 	if (enabled == exiting)
4162 		*exec_control &= ~control;
4163 
4164 	/*
4165 	 * Update the nested MSR settings so that a nested VMM can/can't set
4166 	 * controls for features that are/aren't exposed to the guest.
4167 	 */
4168 	if (nested) {
4169 		if (enabled)
4170 			vmx->nested.msrs.secondary_ctls_high |= control;
4171 		else
4172 			vmx->nested.msrs.secondary_ctls_high &= ~control;
4173 	}
4174 }
4175 
4176 /*
4177  * Wrapper macro for the common case of adjusting a secondary execution control
4178  * based on a single guest CPUID bit, with a dedicated feature bit.  This also
4179  * verifies that the control is actually supported by KVM and hardware.
4180  */
4181 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4182 ({									 \
4183 	bool __enabled;							 \
4184 									 \
4185 	if (cpu_has_vmx_##name()) {					 \
4186 		__enabled = guest_cpuid_has(&(vmx)->vcpu,		 \
4187 					    X86_FEATURE_##feat_name);	 \
4188 		vmx_adjust_secondary_exec_control(vmx, exec_control,	 \
4189 			SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4190 	}								 \
4191 })
4192 
4193 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4194 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4195 	vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4196 
4197 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4198 	vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4199 
4200 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
4201 {
4202 	struct kvm_vcpu *vcpu = &vmx->vcpu;
4203 
4204 	u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4205 
4206 	if (vmx_pt_mode_is_system())
4207 		exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX);
4208 	if (!cpu_need_virtualize_apic_accesses(vcpu))
4209 		exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4210 	if (vmx->vpid == 0)
4211 		exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4212 	if (!enable_ept) {
4213 		exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4214 		enable_unrestricted_guest = 0;
4215 	}
4216 	if (!enable_unrestricted_guest)
4217 		exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4218 	if (kvm_pause_in_guest(vmx->vcpu.kvm))
4219 		exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4220 	if (!kvm_vcpu_apicv_active(vcpu))
4221 		exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4222 				  SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4223 	exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4224 
4225 	/* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4226 	 * in vmx_set_cr4.  */
4227 	exec_control &= ~SECONDARY_EXEC_DESC;
4228 
4229 	/* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4230 	   (handle_vmptrld).
4231 	   We can NOT enable shadow_vmcs here because we don't have yet
4232 	   a current VMCS12
4233 	*/
4234 	exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4235 
4236 	if (!enable_pml)
4237 		exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4238 
4239 	if (cpu_has_vmx_xsaves()) {
4240 		/* Exposing XSAVES only when XSAVE is exposed */
4241 		bool xsaves_enabled =
4242 			boot_cpu_has(X86_FEATURE_XSAVE) &&
4243 			guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4244 			guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
4245 
4246 		vcpu->arch.xsaves_enabled = xsaves_enabled;
4247 
4248 		vmx_adjust_secondary_exec_control(vmx, &exec_control,
4249 						  SECONDARY_EXEC_XSAVES,
4250 						  xsaves_enabled, false);
4251 	}
4252 
4253 	vmx_adjust_sec_exec_feature(vmx, &exec_control, rdtscp, RDTSCP);
4254 
4255 	/*
4256 	 * Expose INVPCID if and only if PCID is also exposed to the guest.
4257 	 * INVPCID takes a #UD when it's disabled in the VMCS, but a #GP or #PF
4258 	 * if CR4.PCIDE=0.  Enumerating CPUID.INVPCID=1 would lead to incorrect
4259 	 * behavior from the guest perspective (it would expect #GP or #PF).
4260 	 */
4261 	if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
4262 		guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
4263 	vmx_adjust_sec_exec_feature(vmx, &exec_control, invpcid, INVPCID);
4264 
4265 
4266 	vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdrand, RDRAND);
4267 	vmx_adjust_sec_exec_exiting(vmx, &exec_control, rdseed, RDSEED);
4268 
4269 	vmx_adjust_sec_exec_control(vmx, &exec_control, waitpkg, WAITPKG,
4270 				    ENABLE_USR_WAIT_PAUSE, false);
4271 
4272 	vmx->secondary_exec_control = exec_control;
4273 }
4274 
4275 static void ept_set_mmio_spte_mask(void)
4276 {
4277 	/*
4278 	 * EPT Misconfigurations can be generated if the value of bits 2:0
4279 	 * of an EPT paging-structure entry is 110b (write/execute).
4280 	 */
4281 	kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 0);
4282 }
4283 
4284 #define VMX_XSS_EXIT_BITMAP 0
4285 
4286 /*
4287  * Noting that the initialization of Guest-state Area of VMCS is in
4288  * vmx_vcpu_reset().
4289  */
4290 static void init_vmcs(struct vcpu_vmx *vmx)
4291 {
4292 	if (nested)
4293 		nested_vmx_set_vmcs_shadowing_bitmap();
4294 
4295 	if (cpu_has_vmx_msr_bitmap())
4296 		vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
4297 
4298 	vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4299 
4300 	/* Control */
4301 	pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx));
4302 
4303 	exec_controls_set(vmx, vmx_exec_control(vmx));
4304 
4305 	if (cpu_has_secondary_exec_ctrls()) {
4306 		vmx_compute_secondary_exec_control(vmx);
4307 		secondary_exec_controls_set(vmx, vmx->secondary_exec_control);
4308 	}
4309 
4310 	if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4311 		vmcs_write64(EOI_EXIT_BITMAP0, 0);
4312 		vmcs_write64(EOI_EXIT_BITMAP1, 0);
4313 		vmcs_write64(EOI_EXIT_BITMAP2, 0);
4314 		vmcs_write64(EOI_EXIT_BITMAP3, 0);
4315 
4316 		vmcs_write16(GUEST_INTR_STATUS, 0);
4317 
4318 		vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4319 		vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4320 	}
4321 
4322 	if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4323 		vmcs_write32(PLE_GAP, ple_gap);
4324 		vmx->ple_window = ple_window;
4325 		vmx->ple_window_dirty = true;
4326 	}
4327 
4328 	vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4329 	vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4330 	vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4331 
4332 	vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4333 	vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4334 	vmx_set_constant_host_state(vmx);
4335 	vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4336 	vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4337 
4338 	if (cpu_has_vmx_vmfunc())
4339 		vmcs_write64(VM_FUNCTION_CONTROL, 0);
4340 
4341 	vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4342 	vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4343 	vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
4344 	vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4345 	vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
4346 
4347 	if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4348 		vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4349 
4350 	vm_exit_controls_set(vmx, vmx_vmexit_ctrl());
4351 
4352 	/* 22.2.1, 20.8.1 */
4353 	vm_entry_controls_set(vmx, vmx_vmentry_ctrl());
4354 
4355 	vmx->vcpu.arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS;
4356 	vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits);
4357 
4358 	set_cr4_guest_host_mask(vmx);
4359 
4360 	if (vmx->vpid != 0)
4361 		vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4362 
4363 	if (cpu_has_vmx_xsaves())
4364 		vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4365 
4366 	if (enable_pml) {
4367 		vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4368 		vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4369 	}
4370 
4371 	if (cpu_has_vmx_encls_vmexit())
4372 		vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
4373 
4374 	if (vmx_pt_mode_is_host_guest()) {
4375 		memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc));
4376 		/* Bit[6~0] are forced to 1, writes are ignored. */
4377 		vmx->pt_desc.guest.output_mask = 0x7F;
4378 		vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
4379 	}
4380 }
4381 
4382 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4383 {
4384 	struct vcpu_vmx *vmx = to_vmx(vcpu);
4385 	struct msr_data apic_base_msr;
4386 	u64 cr0;
4387 
4388 	vmx->rmode.vm86_active = 0;
4389 	vmx->spec_ctrl = 0;
4390 
4391 	vmx->msr_ia32_umwait_control = 0;
4392 
4393 	vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4394 	vmx->hv_deadline_tsc = -1;
4395 	kvm_set_cr8(vcpu, 0);
4396 
4397 	if (!init_event) {
4398 		apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4399 				     MSR_IA32_APICBASE_ENABLE;
4400 		if (kvm_vcpu_is_reset_bsp(vcpu))
4401 			apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4402 		apic_base_msr.host_initiated = true;
4403 		kvm_set_apic_base(vcpu, &apic_base_msr);
4404 	}
4405 
4406 	vmx_segment_cache_clear(vmx);
4407 
4408 	seg_setup(VCPU_SREG_CS);
4409 	vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4410 	vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4411 
4412 	seg_setup(VCPU_SREG_DS);
4413 	seg_setup(VCPU_SREG_ES);
4414 	seg_setup(VCPU_SREG_FS);
4415 	seg_setup(VCPU_SREG_GS);
4416 	seg_setup(VCPU_SREG_SS);
4417 
4418 	vmcs_write16(GUEST_TR_SELECTOR, 0);
4419 	vmcs_writel(GUEST_TR_BASE, 0);
4420 	vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4421 	vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4422 
4423 	vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4424 	vmcs_writel(GUEST_LDTR_BASE, 0);
4425 	vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4426 	vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4427 
4428 	if (!init_event) {
4429 		vmcs_write32(GUEST_SYSENTER_CS, 0);
4430 		vmcs_writel(GUEST_SYSENTER_ESP, 0);
4431 		vmcs_writel(GUEST_SYSENTER_EIP, 0);
4432 		vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4433 	}
4434 
4435 	kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
4436 	kvm_rip_write(vcpu, 0xfff0);
4437 
4438 	vmcs_writel(GUEST_GDTR_BASE, 0);
4439 	vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4440 
4441 	vmcs_writel(GUEST_IDTR_BASE, 0);
4442 	vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4443 
4444 	vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4445 	vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4446 	vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4447 	if (kvm_mpx_supported())
4448 		vmcs_write64(GUEST_BNDCFGS, 0);
4449 
4450 	setup_msrs(vmx);
4451 
4452 	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4453 
4454 	if (cpu_has_vmx_tpr_shadow() && !init_event) {
4455 		vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4456 		if (cpu_need_tpr_shadow(vcpu))
4457 			vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4458 				     __pa(vcpu->arch.apic->regs));
4459 		vmcs_write32(TPR_THRESHOLD, 0);
4460 	}
4461 
4462 	kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4463 
4464 	cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4465 	vmx->vcpu.arch.cr0 = cr0;
4466 	vmx_set_cr0(vcpu, cr0); /* enter rmode */
4467 	vmx_set_cr4(vcpu, 0);
4468 	vmx_set_efer(vcpu, 0);
4469 
4470 	update_exception_bitmap(vcpu);
4471 
4472 	vpid_sync_context(vmx->vpid);
4473 	if (init_event)
4474 		vmx_clear_hlt(vcpu);
4475 }
4476 
4477 static void enable_irq_window(struct kvm_vcpu *vcpu)
4478 {
4479 	exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
4480 }
4481 
4482 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4483 {
4484 	if (!enable_vnmi ||
4485 	    vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4486 		enable_irq_window(vcpu);
4487 		return;
4488 	}
4489 
4490 	exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
4491 }
4492 
4493 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4494 {
4495 	struct vcpu_vmx *vmx = to_vmx(vcpu);
4496 	uint32_t intr;
4497 	int irq = vcpu->arch.interrupt.nr;
4498 
4499 	trace_kvm_inj_virq(irq);
4500 
4501 	++vcpu->stat.irq_injections;
4502 	if (vmx->rmode.vm86_active) {
4503 		int inc_eip = 0;
4504 		if (vcpu->arch.interrupt.soft)
4505 			inc_eip = vcpu->arch.event_exit_inst_len;
4506 		kvm_inject_realmode_interrupt(vcpu, irq, inc_eip);
4507 		return;
4508 	}
4509 	intr = irq | INTR_INFO_VALID_MASK;
4510 	if (vcpu->arch.interrupt.soft) {
4511 		intr |= INTR_TYPE_SOFT_INTR;
4512 		vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4513 			     vmx->vcpu.arch.event_exit_inst_len);
4514 	} else
4515 		intr |= INTR_TYPE_EXT_INTR;
4516 	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4517 
4518 	vmx_clear_hlt(vcpu);
4519 }
4520 
4521 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4522 {
4523 	struct vcpu_vmx *vmx = to_vmx(vcpu);
4524 
4525 	if (!enable_vnmi) {
4526 		/*
4527 		 * Tracking the NMI-blocked state in software is built upon
4528 		 * finding the next open IRQ window. This, in turn, depends on
4529 		 * well-behaving guests: They have to keep IRQs disabled at
4530 		 * least as long as the NMI handler runs. Otherwise we may
4531 		 * cause NMI nesting, maybe breaking the guest. But as this is
4532 		 * highly unlikely, we can live with the residual risk.
4533 		 */
4534 		vmx->loaded_vmcs->soft_vnmi_blocked = 1;
4535 		vmx->loaded_vmcs->vnmi_blocked_time = 0;
4536 	}
4537 
4538 	++vcpu->stat.nmi_injections;
4539 	vmx->loaded_vmcs->nmi_known_unmasked = false;
4540 
4541 	if (vmx->rmode.vm86_active) {
4542 		kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0);
4543 		return;
4544 	}
4545 
4546 	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4547 			INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4548 
4549 	vmx_clear_hlt(vcpu);
4550 }
4551 
4552 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4553 {
4554 	struct vcpu_vmx *vmx = to_vmx(vcpu);
4555 	bool masked;
4556 
4557 	if (!enable_vnmi)
4558 		return vmx->loaded_vmcs->soft_vnmi_blocked;
4559 	if (vmx->loaded_vmcs->nmi_known_unmasked)
4560 		return false;
4561 	masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4562 	vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4563 	return masked;
4564 }
4565 
4566 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4567 {
4568 	struct vcpu_vmx *vmx = to_vmx(vcpu);
4569 
4570 	if (!enable_vnmi) {
4571 		if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4572 			vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4573 			vmx->loaded_vmcs->vnmi_blocked_time = 0;
4574 		}
4575 	} else {
4576 		vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4577 		if (masked)
4578 			vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4579 				      GUEST_INTR_STATE_NMI);
4580 		else
4581 			vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4582 					GUEST_INTR_STATE_NMI);
4583 	}
4584 }
4585 
4586 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu)
4587 {
4588 	if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4589 		return false;
4590 
4591 	if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4592 		return true;
4593 
4594 	return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4595 		(GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4596 		 GUEST_INTR_STATE_NMI));
4597 }
4598 
4599 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4600 {
4601 	if (to_vmx(vcpu)->nested.nested_run_pending)
4602 		return -EBUSY;
4603 
4604 	/* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
4605 	if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
4606 		return -EBUSY;
4607 
4608 	return !vmx_nmi_blocked(vcpu);
4609 }
4610 
4611 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu)
4612 {
4613 	if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4614 		return false;
4615 
4616 	return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
4617 	       (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4618 		(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4619 }
4620 
4621 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4622 {
4623 	if (to_vmx(vcpu)->nested.nested_run_pending)
4624 		return -EBUSY;
4625 
4626        /*
4627         * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4628         * e.g. if the IRQ arrived asynchronously after checking nested events.
4629         */
4630 	if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4631 		return -EBUSY;
4632 
4633 	return !vmx_interrupt_blocked(vcpu);
4634 }
4635 
4636 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4637 {
4638 	void __user *ret;
4639 
4640 	if (enable_unrestricted_guest)
4641 		return 0;
4642 
4643 	mutex_lock(&kvm->slots_lock);
4644 	ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4645 				      PAGE_SIZE * 3);
4646 	mutex_unlock(&kvm->slots_lock);
4647 
4648 	if (IS_ERR(ret))
4649 		return PTR_ERR(ret);
4650 
4651 	to_kvm_vmx(kvm)->tss_addr = addr;
4652 
4653 	return init_rmode_tss(kvm, ret);
4654 }
4655 
4656 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4657 {
4658 	to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
4659 	return 0;
4660 }
4661 
4662 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4663 {
4664 	switch (vec) {
4665 	case BP_VECTOR:
4666 		/*
4667 		 * Update instruction length as we may reinject the exception
4668 		 * from user space while in guest debugging mode.
4669 		 */
4670 		to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4671 			vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4672 		if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4673 			return false;
4674 		fallthrough;
4675 	case DB_VECTOR:
4676 		return !(vcpu->guest_debug &
4677 			(KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
4678 	case DE_VECTOR:
4679 	case OF_VECTOR:
4680 	case BR_VECTOR:
4681 	case UD_VECTOR:
4682 	case DF_VECTOR:
4683 	case SS_VECTOR:
4684 	case GP_VECTOR:
4685 	case MF_VECTOR:
4686 		return true;
4687 	}
4688 	return false;
4689 }
4690 
4691 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4692 				  int vec, u32 err_code)
4693 {
4694 	/*
4695 	 * Instruction with address size override prefix opcode 0x67
4696 	 * Cause the #SS fault with 0 error code in VM86 mode.
4697 	 */
4698 	if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4699 		if (kvm_emulate_instruction(vcpu, 0)) {
4700 			if (vcpu->arch.halt_request) {
4701 				vcpu->arch.halt_request = 0;
4702 				return kvm_vcpu_halt(vcpu);
4703 			}
4704 			return 1;
4705 		}
4706 		return 0;
4707 	}
4708 
4709 	/*
4710 	 * Forward all other exceptions that are valid in real mode.
4711 	 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4712 	 *        the required debugging infrastructure rework.
4713 	 */
4714 	kvm_queue_exception(vcpu, vec);
4715 	return 1;
4716 }
4717 
4718 static int handle_machine_check(struct kvm_vcpu *vcpu)
4719 {
4720 	/* handled by vmx_vcpu_run() */
4721 	return 1;
4722 }
4723 
4724 /*
4725  * If the host has split lock detection disabled, then #AC is
4726  * unconditionally injected into the guest, which is the pre split lock
4727  * detection behaviour.
4728  *
4729  * If the host has split lock detection enabled then #AC is
4730  * only injected into the guest when:
4731  *  - Guest CPL == 3 (user mode)
4732  *  - Guest has #AC detection enabled in CR0
4733  *  - Guest EFLAGS has AC bit set
4734  */
4735 static inline bool guest_inject_ac(struct kvm_vcpu *vcpu)
4736 {
4737 	if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
4738 		return true;
4739 
4740 	return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
4741 	       (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
4742 }
4743 
4744 static int handle_exception_nmi(struct kvm_vcpu *vcpu)
4745 {
4746 	struct vcpu_vmx *vmx = to_vmx(vcpu);
4747 	struct kvm_run *kvm_run = vcpu->run;
4748 	u32 intr_info, ex_no, error_code;
4749 	unsigned long cr2, rip, dr6;
4750 	u32 vect_info;
4751 
4752 	vect_info = vmx->idt_vectoring_info;
4753 	intr_info = vmx_get_intr_info(vcpu);
4754 
4755 	if (is_machine_check(intr_info) || is_nmi(intr_info))
4756 		return 1; /* handled by handle_exception_nmi_irqoff() */
4757 
4758 	if (is_invalid_opcode(intr_info))
4759 		return handle_ud(vcpu);
4760 
4761 	error_code = 0;
4762 	if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4763 		error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4764 
4765 	if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4766 		WARN_ON_ONCE(!enable_vmware_backdoor);
4767 
4768 		/*
4769 		 * VMware backdoor emulation on #GP interception only handles
4770 		 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4771 		 * error code on #GP.
4772 		 */
4773 		if (error_code) {
4774 			kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4775 			return 1;
4776 		}
4777 		return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
4778 	}
4779 
4780 	/*
4781 	 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4782 	 * MMIO, it is better to report an internal error.
4783 	 * See the comments in vmx_handle_exit.
4784 	 */
4785 	if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4786 	    !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4787 		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4788 		vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4789 		vcpu->run->internal.ndata = 4;
4790 		vcpu->run->internal.data[0] = vect_info;
4791 		vcpu->run->internal.data[1] = intr_info;
4792 		vcpu->run->internal.data[2] = error_code;
4793 		vcpu->run->internal.data[3] = vcpu->arch.last_vmentry_cpu;
4794 		return 0;
4795 	}
4796 
4797 	if (is_page_fault(intr_info)) {
4798 		cr2 = vmx_get_exit_qual(vcpu);
4799 		if (enable_ept && !vcpu->arch.apf.host_apf_flags) {
4800 			/*
4801 			 * EPT will cause page fault only if we need to
4802 			 * detect illegal GPAs.
4803 			 */
4804 			WARN_ON_ONCE(!allow_smaller_maxphyaddr);
4805 			kvm_fixup_and_inject_pf_error(vcpu, cr2, error_code);
4806 			return 1;
4807 		} else
4808 			return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
4809 	}
4810 
4811 	ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4812 
4813 	if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4814 		return handle_rmode_exception(vcpu, ex_no, error_code);
4815 
4816 	switch (ex_no) {
4817 	case DB_VECTOR:
4818 		dr6 = vmx_get_exit_qual(vcpu);
4819 		if (!(vcpu->guest_debug &
4820 		      (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4821 			if (is_icebp(intr_info))
4822 				WARN_ON(!skip_emulated_instruction(vcpu));
4823 
4824 			kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
4825 			return 1;
4826 		}
4827 		kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4828 		kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4829 		fallthrough;
4830 	case BP_VECTOR:
4831 		/*
4832 		 * Update instruction length as we may reinject #BP from
4833 		 * user space while in guest debugging mode. Reading it for
4834 		 * #DB as well causes no harm, it is not used in that case.
4835 		 */
4836 		vmx->vcpu.arch.event_exit_inst_len =
4837 			vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4838 		kvm_run->exit_reason = KVM_EXIT_DEBUG;
4839 		rip = kvm_rip_read(vcpu);
4840 		kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4841 		kvm_run->debug.arch.exception = ex_no;
4842 		break;
4843 	case AC_VECTOR:
4844 		if (guest_inject_ac(vcpu)) {
4845 			kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4846 			return 1;
4847 		}
4848 
4849 		/*
4850 		 * Handle split lock. Depending on detection mode this will
4851 		 * either warn and disable split lock detection for this
4852 		 * task or force SIGBUS on it.
4853 		 */
4854 		if (handle_guest_split_lock(kvm_rip_read(vcpu)))
4855 			return 1;
4856 		fallthrough;
4857 	default:
4858 		kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4859 		kvm_run->ex.exception = ex_no;
4860 		kvm_run->ex.error_code = error_code;
4861 		break;
4862 	}
4863 	return 0;
4864 }
4865 
4866 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu)
4867 {
4868 	++vcpu->stat.irq_exits;
4869 	return 1;
4870 }
4871 
4872 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4873 {
4874 	vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4875 	vcpu->mmio_needed = 0;
4876 	return 0;
4877 }
4878 
4879 static int handle_io(struct kvm_vcpu *vcpu)
4880 {
4881 	unsigned long exit_qualification;
4882 	int size, in, string;
4883 	unsigned port;
4884 
4885 	exit_qualification = vmx_get_exit_qual(vcpu);
4886 	string = (exit_qualification & 16) != 0;
4887 
4888 	++vcpu->stat.io_exits;
4889 
4890 	if (string)
4891 		return kvm_emulate_instruction(vcpu, 0);
4892 
4893 	port = exit_qualification >> 16;
4894 	size = (exit_qualification & 7) + 1;
4895 	in = (exit_qualification & 8) != 0;
4896 
4897 	return kvm_fast_pio(vcpu, size, port, in);
4898 }
4899 
4900 static void
4901 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4902 {
4903 	/*
4904 	 * Patch in the VMCALL instruction:
4905 	 */
4906 	hypercall[0] = 0x0f;
4907 	hypercall[1] = 0x01;
4908 	hypercall[2] = 0xc1;
4909 }
4910 
4911 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4912 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4913 {
4914 	if (is_guest_mode(vcpu)) {
4915 		struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4916 		unsigned long orig_val = val;
4917 
4918 		/*
4919 		 * We get here when L2 changed cr0 in a way that did not change
4920 		 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4921 		 * but did change L0 shadowed bits. So we first calculate the
4922 		 * effective cr0 value that L1 would like to write into the
4923 		 * hardware. It consists of the L2-owned bits from the new
4924 		 * value combined with the L1-owned bits from L1's guest_cr0.
4925 		 */
4926 		val = (val & ~vmcs12->cr0_guest_host_mask) |
4927 			(vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4928 
4929 		if (!nested_guest_cr0_valid(vcpu, val))
4930 			return 1;
4931 
4932 		if (kvm_set_cr0(vcpu, val))
4933 			return 1;
4934 		vmcs_writel(CR0_READ_SHADOW, orig_val);
4935 		return 0;
4936 	} else {
4937 		if (to_vmx(vcpu)->nested.vmxon &&
4938 		    !nested_host_cr0_valid(vcpu, val))
4939 			return 1;
4940 
4941 		return kvm_set_cr0(vcpu, val);
4942 	}
4943 }
4944 
4945 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4946 {
4947 	if (is_guest_mode(vcpu)) {
4948 		struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4949 		unsigned long orig_val = val;
4950 
4951 		/* analogously to handle_set_cr0 */
4952 		val = (val & ~vmcs12->cr4_guest_host_mask) |
4953 			(vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4954 		if (kvm_set_cr4(vcpu, val))
4955 			return 1;
4956 		vmcs_writel(CR4_READ_SHADOW, orig_val);
4957 		return 0;
4958 	} else
4959 		return kvm_set_cr4(vcpu, val);
4960 }
4961 
4962 static int handle_desc(struct kvm_vcpu *vcpu)
4963 {
4964 	WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
4965 	return kvm_emulate_instruction(vcpu, 0);
4966 }
4967 
4968 static int handle_cr(struct kvm_vcpu *vcpu)
4969 {
4970 	unsigned long exit_qualification, val;
4971 	int cr;
4972 	int reg;
4973 	int err;
4974 	int ret;
4975 
4976 	exit_qualification = vmx_get_exit_qual(vcpu);
4977 	cr = exit_qualification & 15;
4978 	reg = (exit_qualification >> 8) & 15;
4979 	switch ((exit_qualification >> 4) & 3) {
4980 	case 0: /* mov to cr */
4981 		val = kvm_register_readl(vcpu, reg);
4982 		trace_kvm_cr_write(cr, val);
4983 		switch (cr) {
4984 		case 0:
4985 			err = handle_set_cr0(vcpu, val);
4986 			return kvm_complete_insn_gp(vcpu, err);
4987 		case 3:
4988 			WARN_ON_ONCE(enable_unrestricted_guest);
4989 			err = kvm_set_cr3(vcpu, val);
4990 			return kvm_complete_insn_gp(vcpu, err);
4991 		case 4:
4992 			err = handle_set_cr4(vcpu, val);
4993 			return kvm_complete_insn_gp(vcpu, err);
4994 		case 8: {
4995 				u8 cr8_prev = kvm_get_cr8(vcpu);
4996 				u8 cr8 = (u8)val;
4997 				err = kvm_set_cr8(vcpu, cr8);
4998 				ret = kvm_complete_insn_gp(vcpu, err);
4999 				if (lapic_in_kernel(vcpu))
5000 					return ret;
5001 				if (cr8_prev <= cr8)
5002 					return ret;
5003 				/*
5004 				 * TODO: we might be squashing a
5005 				 * KVM_GUESTDBG_SINGLESTEP-triggered
5006 				 * KVM_EXIT_DEBUG here.
5007 				 */
5008 				vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5009 				return 0;
5010 			}
5011 		}
5012 		break;
5013 	case 2: /* clts */
5014 		WARN_ONCE(1, "Guest should always own CR0.TS");
5015 		vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5016 		trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5017 		return kvm_skip_emulated_instruction(vcpu);
5018 	case 1: /*mov from cr*/
5019 		switch (cr) {
5020 		case 3:
5021 			WARN_ON_ONCE(enable_unrestricted_guest);
5022 			val = kvm_read_cr3(vcpu);
5023 			kvm_register_write(vcpu, reg, val);
5024 			trace_kvm_cr_read(cr, val);
5025 			return kvm_skip_emulated_instruction(vcpu);
5026 		case 8:
5027 			val = kvm_get_cr8(vcpu);
5028 			kvm_register_write(vcpu, reg, val);
5029 			trace_kvm_cr_read(cr, val);
5030 			return kvm_skip_emulated_instruction(vcpu);
5031 		}
5032 		break;
5033 	case 3: /* lmsw */
5034 		val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5035 		trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5036 		kvm_lmsw(vcpu, val);
5037 
5038 		return kvm_skip_emulated_instruction(vcpu);
5039 	default:
5040 		break;
5041 	}
5042 	vcpu->run->exit_reason = 0;
5043 	vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5044 	       (int)(exit_qualification >> 4) & 3, cr);
5045 	return 0;
5046 }
5047 
5048 static int handle_dr(struct kvm_vcpu *vcpu)
5049 {
5050 	unsigned long exit_qualification;
5051 	int dr, dr7, reg;
5052 
5053 	exit_qualification = vmx_get_exit_qual(vcpu);
5054 	dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5055 
5056 	/* First, if DR does not exist, trigger UD */
5057 	if (!kvm_require_dr(vcpu, dr))
5058 		return 1;
5059 
5060 	/* Do not handle if the CPL > 0, will trigger GP on re-entry */
5061 	if (!kvm_require_cpl(vcpu, 0))
5062 		return 1;
5063 	dr7 = vmcs_readl(GUEST_DR7);
5064 	if (dr7 & DR7_GD) {
5065 		/*
5066 		 * As the vm-exit takes precedence over the debug trap, we
5067 		 * need to emulate the latter, either for the host or the
5068 		 * guest debugging itself.
5069 		 */
5070 		if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5071 			vcpu->run->debug.arch.dr6 = DR6_BD | DR6_RTM | DR6_FIXED_1;
5072 			vcpu->run->debug.arch.dr7 = dr7;
5073 			vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5074 			vcpu->run->debug.arch.exception = DB_VECTOR;
5075 			vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5076 			return 0;
5077 		} else {
5078 			kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BD);
5079 			return 1;
5080 		}
5081 	}
5082 
5083 	if (vcpu->guest_debug == 0) {
5084 		exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5085 
5086 		/*
5087 		 * No more DR vmexits; force a reload of the debug registers
5088 		 * and reenter on this instruction.  The next vmexit will
5089 		 * retrieve the full state of the debug registers.
5090 		 */
5091 		vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5092 		return 1;
5093 	}
5094 
5095 	reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5096 	if (exit_qualification & TYPE_MOV_FROM_DR) {
5097 		unsigned long val;
5098 
5099 		if (kvm_get_dr(vcpu, dr, &val))
5100 			return 1;
5101 		kvm_register_write(vcpu, reg, val);
5102 	} else
5103 		if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5104 			return 1;
5105 
5106 	return kvm_skip_emulated_instruction(vcpu);
5107 }
5108 
5109 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5110 {
5111 	get_debugreg(vcpu->arch.db[0], 0);
5112 	get_debugreg(vcpu->arch.db[1], 1);
5113 	get_debugreg(vcpu->arch.db[2], 2);
5114 	get_debugreg(vcpu->arch.db[3], 3);
5115 	get_debugreg(vcpu->arch.dr6, 6);
5116 	vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5117 
5118 	vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5119 	exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING);
5120 }
5121 
5122 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5123 {
5124 	vmcs_writel(GUEST_DR7, val);
5125 }
5126 
5127 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5128 {
5129 	kvm_apic_update_ppr(vcpu);
5130 	return 1;
5131 }
5132 
5133 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5134 {
5135 	exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING);
5136 
5137 	kvm_make_request(KVM_REQ_EVENT, vcpu);
5138 
5139 	++vcpu->stat.irq_window_exits;
5140 	return 1;
5141 }
5142 
5143 static int handle_vmcall(struct kvm_vcpu *vcpu)
5144 {
5145 	return kvm_emulate_hypercall(vcpu);
5146 }
5147 
5148 static int handle_invd(struct kvm_vcpu *vcpu)
5149 {
5150 	/* Treat an INVD instruction as a NOP and just skip it. */
5151 	return kvm_skip_emulated_instruction(vcpu);
5152 }
5153 
5154 static int handle_invlpg(struct kvm_vcpu *vcpu)
5155 {
5156 	unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5157 
5158 	kvm_mmu_invlpg(vcpu, exit_qualification);
5159 	return kvm_skip_emulated_instruction(vcpu);
5160 }
5161 
5162 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5163 {
5164 	int err;
5165 
5166 	err = kvm_rdpmc(vcpu);
5167 	return kvm_complete_insn_gp(vcpu, err);
5168 }
5169 
5170 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5171 {
5172 	return kvm_emulate_wbinvd(vcpu);
5173 }
5174 
5175 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5176 {
5177 	u64 new_bv = kvm_read_edx_eax(vcpu);
5178 	u32 index = kvm_rcx_read(vcpu);
5179 
5180 	if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5181 		return kvm_skip_emulated_instruction(vcpu);
5182 	return 1;
5183 }
5184 
5185 static int handle_apic_access(struct kvm_vcpu *vcpu)
5186 {
5187 	if (likely(fasteoi)) {
5188 		unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5189 		int access_type, offset;
5190 
5191 		access_type = exit_qualification & APIC_ACCESS_TYPE;
5192 		offset = exit_qualification & APIC_ACCESS_OFFSET;
5193 		/*
5194 		 * Sane guest uses MOV to write EOI, with written value
5195 		 * not cared. So make a short-circuit here by avoiding
5196 		 * heavy instruction emulation.
5197 		 */
5198 		if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5199 		    (offset == APIC_EOI)) {
5200 			kvm_lapic_set_eoi(vcpu);
5201 			return kvm_skip_emulated_instruction(vcpu);
5202 		}
5203 	}
5204 	return kvm_emulate_instruction(vcpu, 0);
5205 }
5206 
5207 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5208 {
5209 	unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5210 	int vector = exit_qualification & 0xff;
5211 
5212 	/* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5213 	kvm_apic_set_eoi_accelerated(vcpu, vector);
5214 	return 1;
5215 }
5216 
5217 static int handle_apic_write(struct kvm_vcpu *vcpu)
5218 {
5219 	unsigned long exit_qualification = vmx_get_exit_qual(vcpu);
5220 	u32 offset = exit_qualification & 0xfff;
5221 
5222 	/* APIC-write VM exit is trap-like and thus no need to adjust IP */
5223 	kvm_apic_write_nodecode(vcpu, offset);
5224 	return 1;
5225 }
5226 
5227 static int handle_task_switch(struct kvm_vcpu *vcpu)
5228 {
5229 	struct vcpu_vmx *vmx = to_vmx(vcpu);
5230 	unsigned long exit_qualification;
5231 	bool has_error_code = false;
5232 	u32 error_code = 0;
5233 	u16 tss_selector;
5234 	int reason, type, idt_v, idt_index;
5235 
5236 	idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5237 	idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5238 	type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5239 
5240 	exit_qualification = vmx_get_exit_qual(vcpu);
5241 
5242 	reason = (u32)exit_qualification >> 30;
5243 	if (reason == TASK_SWITCH_GATE && idt_v) {
5244 		switch (type) {
5245 		case INTR_TYPE_NMI_INTR:
5246 			vcpu->arch.nmi_injected = false;
5247 			vmx_set_nmi_mask(vcpu, true);
5248 			break;
5249 		case INTR_TYPE_EXT_INTR:
5250 		case INTR_TYPE_SOFT_INTR:
5251 			kvm_clear_interrupt_queue(vcpu);
5252 			break;
5253 		case INTR_TYPE_HARD_EXCEPTION:
5254 			if (vmx->idt_vectoring_info &
5255 			    VECTORING_INFO_DELIVER_CODE_MASK) {
5256 				has_error_code = true;
5257 				error_code =
5258 					vmcs_read32(IDT_VECTORING_ERROR_CODE);
5259 			}
5260 			fallthrough;
5261 		case INTR_TYPE_SOFT_EXCEPTION:
5262 			kvm_clear_exception_queue(vcpu);
5263 			break;
5264 		default:
5265 			break;
5266 		}
5267 	}
5268 	tss_selector = exit_qualification;
5269 
5270 	if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5271 		       type != INTR_TYPE_EXT_INTR &&
5272 		       type != INTR_TYPE_NMI_INTR))
5273 		WARN_ON(!skip_emulated_instruction(vcpu));
5274 
5275 	/*
5276 	 * TODO: What about debug traps on tss switch?
5277 	 *       Are we supposed to inject them and update dr6?
5278 	 */
5279 	return kvm_task_switch(vcpu, tss_selector,
5280 			       type == INTR_TYPE_SOFT_INTR ? idt_index : -1,
5281 			       reason, has_error_code, error_code);
5282 }
5283 
5284 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5285 {
5286 	unsigned long exit_qualification;
5287 	gpa_t gpa;
5288 	u64 error_code;
5289 
5290 	exit_qualification = vmx_get_exit_qual(vcpu);
5291 
5292 	/*
5293 	 * EPT violation happened while executing iret from NMI,
5294 	 * "blocked by NMI" bit has to be set before next VM entry.
5295 	 * There are errata that may cause this bit to not be set:
5296 	 * AAK134, BY25.
5297 	 */
5298 	if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5299 			enable_vnmi &&
5300 			(exit_qualification & INTR_INFO_UNBLOCK_NMI))
5301 		vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5302 
5303 	gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5304 	trace_kvm_page_fault(gpa, exit_qualification);
5305 
5306 	/* Is it a read fault? */
5307 	error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
5308 		     ? PFERR_USER_MASK : 0;
5309 	/* Is it a write fault? */
5310 	error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
5311 		      ? PFERR_WRITE_MASK : 0;
5312 	/* Is it a fetch fault? */
5313 	error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
5314 		      ? PFERR_FETCH_MASK : 0;
5315 	/* ept page table entry is present? */
5316 	error_code |= (exit_qualification &
5317 		       (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
5318 			EPT_VIOLATION_EXECUTABLE))
5319 		      ? PFERR_PRESENT_MASK : 0;
5320 
5321 	error_code |= (exit_qualification & 0x100) != 0 ?
5322 	       PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
5323 
5324 	vcpu->arch.exit_qualification = exit_qualification;
5325 
5326 	/*
5327 	 * Check that the GPA doesn't exceed physical memory limits, as that is
5328 	 * a guest page fault.  We have to emulate the instruction here, because
5329 	 * if the illegal address is that of a paging structure, then
5330 	 * EPT_VIOLATION_ACC_WRITE bit is set.  Alternatively, if supported we
5331 	 * would also use advanced VM-exit information for EPT violations to
5332 	 * reconstruct the page fault error code.
5333 	 */
5334 	if (unlikely(allow_smaller_maxphyaddr && kvm_vcpu_is_illegal_gpa(vcpu, gpa)))
5335 		return kvm_emulate_instruction(vcpu, 0);
5336 
5337 	return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5338 }
5339 
5340 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5341 {
5342 	gpa_t gpa;
5343 
5344 	/*
5345 	 * A nested guest cannot optimize MMIO vmexits, because we have an
5346 	 * nGPA here instead of the required GPA.
5347 	 */
5348 	gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5349 	if (!is_guest_mode(vcpu) &&
5350 	    !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5351 		trace_kvm_fast_mmio(gpa);
5352 		return kvm_skip_emulated_instruction(vcpu);
5353 	}
5354 
5355 	return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
5356 }
5357 
5358 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5359 {
5360 	WARN_ON_ONCE(!enable_vnmi);
5361 	exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING);
5362 	++vcpu->stat.nmi_window_exits;
5363 	kvm_make_request(KVM_REQ_EVENT, vcpu);
5364 
5365 	return 1;
5366 }
5367 
5368 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5369 {
5370 	struct vcpu_vmx *vmx = to_vmx(vcpu);
5371 	bool intr_window_requested;
5372 	unsigned count = 130;
5373 
5374 	intr_window_requested = exec_controls_get(vmx) &
5375 				CPU_BASED_INTR_WINDOW_EXITING;
5376 
5377 	while (vmx->emulation_required && count-- != 0) {
5378 		if (intr_window_requested && !vmx_interrupt_blocked(vcpu))
5379 			return handle_interrupt_window(&vmx->vcpu);
5380 
5381 		if (kvm_test_request(KVM_REQ_EVENT, vcpu))
5382 			return 1;
5383 
5384 		if (!kvm_emulate_instruction(vcpu, 0))
5385 			return 0;
5386 
5387 		if (vmx->emulation_required && !vmx->rmode.vm86_active &&
5388 		    vcpu->arch.exception.pending) {
5389 			vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5390 			vcpu->run->internal.suberror =
5391 						KVM_INTERNAL_ERROR_EMULATION;
5392 			vcpu->run->internal.ndata = 0;
5393 			return 0;
5394 		}
5395 
5396 		if (vcpu->arch.halt_request) {
5397 			vcpu->arch.halt_request = 0;
5398 			return kvm_vcpu_halt(vcpu);
5399 		}
5400 
5401 		/*
5402 		 * Note, return 1 and not 0, vcpu_run() will invoke
5403 		 * xfer_to_guest_mode() which will create a proper return
5404 		 * code.
5405 		 */
5406 		if (__xfer_to_guest_mode_work_pending())
5407 			return 1;
5408 	}
5409 
5410 	return 1;
5411 }
5412 
5413 static void grow_ple_window(struct kvm_vcpu *vcpu)
5414 {
5415 	struct vcpu_vmx *vmx = to_vmx(vcpu);
5416 	unsigned int old = vmx->ple_window;
5417 
5418 	vmx->ple_window = __grow_ple_window(old, ple_window,
5419 					    ple_window_grow,
5420 					    ple_window_max);
5421 
5422 	if (vmx->ple_window != old) {
5423 		vmx->ple_window_dirty = true;
5424 		trace_kvm_ple_window_update(vcpu->vcpu_id,
5425 					    vmx->ple_window, old);
5426 	}
5427 }
5428 
5429 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5430 {
5431 	struct vcpu_vmx *vmx = to_vmx(vcpu);
5432 	unsigned int old = vmx->ple_window;
5433 
5434 	vmx->ple_window = __shrink_ple_window(old, ple_window,
5435 					      ple_window_shrink,
5436 					      ple_window);
5437 
5438 	if (vmx->ple_window != old) {
5439 		vmx->ple_window_dirty = true;
5440 		trace_kvm_ple_window_update(vcpu->vcpu_id,
5441 					    vmx->ple_window, old);
5442 	}
5443 }
5444 
5445 static void vmx_enable_tdp(void)
5446 {
5447 	kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
5448 		enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
5449 		enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
5450 		0ull, VMX_EPT_EXECUTABLE_MASK,
5451 		cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
5452 		VMX_EPT_RWX_MASK, 0ull);
5453 
5454 	ept_set_mmio_spte_mask();
5455 }
5456 
5457 /*
5458  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5459  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5460  */
5461 static int handle_pause(struct kvm_vcpu *vcpu)
5462 {
5463 	if (!kvm_pause_in_guest(vcpu->kvm))
5464 		grow_ple_window(vcpu);
5465 
5466 	/*
5467 	 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5468 	 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5469 	 * never set PAUSE_EXITING and just set PLE if supported,
5470 	 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5471 	 */
5472 	kvm_vcpu_on_spin(vcpu, true);
5473 	return kvm_skip_emulated_instruction(vcpu);
5474 }
5475 
5476 static int handle_nop(struct kvm_vcpu *vcpu)
5477 {
5478 	return kvm_skip_emulated_instruction(vcpu);
5479 }
5480 
5481 static int handle_mwait(struct kvm_vcpu *vcpu)
5482 {
5483 	printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5484 	return handle_nop(vcpu);
5485 }
5486 
5487 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5488 {
5489 	kvm_queue_exception(vcpu, UD_VECTOR);
5490 	return 1;
5491 }
5492 
5493 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5494 {
5495 	return 1;
5496 }
5497 
5498 static int handle_monitor(struct kvm_vcpu *vcpu)
5499 {
5500 	printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5501 	return handle_nop(vcpu);
5502 }
5503 
5504 static int handle_invpcid(struct kvm_vcpu *vcpu)
5505 {
5506 	u32 vmx_instruction_info;
5507 	unsigned long type;
5508 	gva_t gva;
5509 	struct {
5510 		u64 pcid;
5511 		u64 gla;
5512 	} operand;
5513 
5514 	if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
5515 		kvm_queue_exception(vcpu, UD_VECTOR);
5516 		return 1;
5517 	}
5518 
5519 	vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5520 	type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5521 
5522 	if (type > 3) {
5523 		kvm_inject_gp(vcpu, 0);
5524 		return 1;
5525 	}
5526 
5527 	/* According to the Intel instruction reference, the memory operand
5528 	 * is read even if it isn't needed (e.g., for type==all)
5529 	 */
5530 	if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu),
5531 				vmx_instruction_info, false,
5532 				sizeof(operand), &gva))
5533 		return 1;
5534 
5535 	return kvm_handle_invpcid(vcpu, type, gva);
5536 }
5537 
5538 static int handle_pml_full(struct kvm_vcpu *vcpu)
5539 {
5540 	unsigned long exit_qualification;
5541 
5542 	trace_kvm_pml_full(vcpu->vcpu_id);
5543 
5544 	exit_qualification = vmx_get_exit_qual(vcpu);
5545 
5546 	/*
5547 	 * PML buffer FULL happened while executing iret from NMI,
5548 	 * "blocked by NMI" bit has to be set before next VM entry.
5549 	 */
5550 	if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5551 			enable_vnmi &&
5552 			(exit_qualification & INTR_INFO_UNBLOCK_NMI))
5553 		vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5554 				GUEST_INTR_STATE_NMI);
5555 
5556 	/*
5557 	 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5558 	 * here.., and there's no userspace involvement needed for PML.
5559 	 */
5560 	return 1;
5561 }
5562 
5563 static fastpath_t handle_fastpath_preemption_timer(struct kvm_vcpu *vcpu)
5564 {
5565 	struct vcpu_vmx *vmx = to_vmx(vcpu);
5566 
5567 	if (!vmx->req_immediate_exit &&
5568 	    !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) {
5569 		kvm_lapic_expired_hv_timer(vcpu);
5570 		return EXIT_FASTPATH_REENTER_GUEST;
5571 	}
5572 
5573 	return EXIT_FASTPATH_NONE;
5574 }
5575 
5576 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
5577 {
5578 	handle_fastpath_preemption_timer(vcpu);
5579 	return 1;
5580 }
5581 
5582 /*
5583  * When nested=0, all VMX instruction VM Exits filter here.  The handlers
5584  * are overwritten by nested_vmx_setup() when nested=1.
5585  */
5586 static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
5587 {
5588 	kvm_queue_exception(vcpu, UD_VECTOR);
5589 	return 1;
5590 }
5591 
5592 static int handle_encls(struct kvm_vcpu *vcpu)
5593 {
5594 	/*
5595 	 * SGX virtualization is not yet supported.  There is no software
5596 	 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5597 	 * to prevent the guest from executing ENCLS.
5598 	 */
5599 	kvm_queue_exception(vcpu, UD_VECTOR);
5600 	return 1;
5601 }
5602 
5603 /*
5604  * The exit handlers return 1 if the exit was handled fully and guest execution
5605  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5606  * to be done to userspace and return 0.
5607  */
5608 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5609 	[EXIT_REASON_EXCEPTION_NMI]           = handle_exception_nmi,
5610 	[EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5611 	[EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5612 	[EXIT_REASON_NMI_WINDOW]	      = handle_nmi_window,
5613 	[EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5614 	[EXIT_REASON_CR_ACCESS]               = handle_cr,
5615 	[EXIT_REASON_DR_ACCESS]               = handle_dr,
5616 	[EXIT_REASON_CPUID]                   = kvm_emulate_cpuid,
5617 	[EXIT_REASON_MSR_READ]                = kvm_emulate_rdmsr,
5618 	[EXIT_REASON_MSR_WRITE]               = kvm_emulate_wrmsr,
5619 	[EXIT_REASON_INTERRUPT_WINDOW]        = handle_interrupt_window,
5620 	[EXIT_REASON_HLT]                     = kvm_emulate_halt,
5621 	[EXIT_REASON_INVD]		      = handle_invd,
5622 	[EXIT_REASON_INVLPG]		      = handle_invlpg,
5623 	[EXIT_REASON_RDPMC]                   = handle_rdpmc,
5624 	[EXIT_REASON_VMCALL]                  = handle_vmcall,
5625 	[EXIT_REASON_VMCLEAR]		      = handle_vmx_instruction,
5626 	[EXIT_REASON_VMLAUNCH]		      = handle_vmx_instruction,
5627 	[EXIT_REASON_VMPTRLD]		      = handle_vmx_instruction,
5628 	[EXIT_REASON_VMPTRST]		      = handle_vmx_instruction,
5629 	[EXIT_REASON_VMREAD]		      = handle_vmx_instruction,
5630 	[EXIT_REASON_VMRESUME]		      = handle_vmx_instruction,
5631 	[EXIT_REASON_VMWRITE]		      = handle_vmx_instruction,
5632 	[EXIT_REASON_VMOFF]		      = handle_vmx_instruction,
5633 	[EXIT_REASON_VMON]		      = handle_vmx_instruction,
5634 	[EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5635 	[EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5636 	[EXIT_REASON_APIC_WRITE]              = handle_apic_write,
5637 	[EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
5638 	[EXIT_REASON_WBINVD]                  = handle_wbinvd,
5639 	[EXIT_REASON_XSETBV]                  = handle_xsetbv,
5640 	[EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5641 	[EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5642 	[EXIT_REASON_GDTR_IDTR]		      = handle_desc,
5643 	[EXIT_REASON_LDTR_TR]		      = handle_desc,
5644 	[EXIT_REASON_EPT_VIOLATION]	      = handle_ept_violation,
5645 	[EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5646 	[EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5647 	[EXIT_REASON_MWAIT_INSTRUCTION]	      = handle_mwait,
5648 	[EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
5649 	[EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
5650 	[EXIT_REASON_INVEPT]                  = handle_vmx_instruction,
5651 	[EXIT_REASON_INVVPID]                 = handle_vmx_instruction,
5652 	[EXIT_REASON_RDRAND]                  = handle_invalid_op,
5653 	[EXIT_REASON_RDSEED]                  = handle_invalid_op,
5654 	[EXIT_REASON_PML_FULL]		      = handle_pml_full,
5655 	[EXIT_REASON_INVPCID]                 = handle_invpcid,
5656 	[EXIT_REASON_VMFUNC]		      = handle_vmx_instruction,
5657 	[EXIT_REASON_PREEMPTION_TIMER]	      = handle_preemption_timer,
5658 	[EXIT_REASON_ENCLS]		      = handle_encls,
5659 };
5660 
5661 static const int kvm_vmx_max_exit_handlers =
5662 	ARRAY_SIZE(kvm_vmx_exit_handlers);
5663 
5664 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
5665 			      u32 *intr_info, u32 *error_code)
5666 {
5667 	struct vcpu_vmx *vmx = to_vmx(vcpu);
5668 
5669 	*info1 = vmx_get_exit_qual(vcpu);
5670 	if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
5671 		*info2 = vmx->idt_vectoring_info;
5672 		*intr_info = vmx_get_intr_info(vcpu);
5673 		if (is_exception_with_error_code(*intr_info))
5674 			*error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5675 		else
5676 			*error_code = 0;
5677 	} else {
5678 		*info2 = 0;
5679 		*intr_info = 0;
5680 		*error_code = 0;
5681 	}
5682 }
5683 
5684 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
5685 {
5686 	if (vmx->pml_pg) {
5687 		__free_page(vmx->pml_pg);
5688 		vmx->pml_pg = NULL;
5689 	}
5690 }
5691 
5692 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
5693 {
5694 	struct vcpu_vmx *vmx = to_vmx(vcpu);
5695 	u64 *pml_buf;
5696 	u16 pml_idx;
5697 
5698 	pml_idx = vmcs_read16(GUEST_PML_INDEX);
5699 
5700 	/* Do nothing if PML buffer is empty */
5701 	if (pml_idx == (PML_ENTITY_NUM - 1))
5702 		return;
5703 
5704 	/* PML index always points to next available PML buffer entity */
5705 	if (pml_idx >= PML_ENTITY_NUM)
5706 		pml_idx = 0;
5707 	else
5708 		pml_idx++;
5709 
5710 	pml_buf = page_address(vmx->pml_pg);
5711 	for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5712 		u64 gpa;
5713 
5714 		gpa = pml_buf[pml_idx];
5715 		WARN_ON(gpa & (PAGE_SIZE - 1));
5716 		kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5717 	}
5718 
5719 	/* reset PML index */
5720 	vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5721 }
5722 
5723 /*
5724  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5725  * Called before reporting dirty_bitmap to userspace.
5726  */
5727 static void kvm_flush_pml_buffers(struct kvm *kvm)
5728 {
5729 	int i;
5730 	struct kvm_vcpu *vcpu;
5731 	/*
5732 	 * We only need to kick vcpu out of guest mode here, as PML buffer
5733 	 * is flushed at beginning of all VMEXITs, and it's obvious that only
5734 	 * vcpus running in guest are possible to have unflushed GPAs in PML
5735 	 * buffer.
5736 	 */
5737 	kvm_for_each_vcpu(i, vcpu, kvm)
5738 		kvm_vcpu_kick(vcpu);
5739 }
5740 
5741 static void vmx_dump_sel(char *name, uint32_t sel)
5742 {
5743 	pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5744 	       name, vmcs_read16(sel),
5745 	       vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5746 	       vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5747 	       vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
5748 }
5749 
5750 static void vmx_dump_dtsel(char *name, uint32_t limit)
5751 {
5752 	pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
5753 	       name, vmcs_read32(limit),
5754 	       vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
5755 }
5756 
5757 void dump_vmcs(void)
5758 {
5759 	u32 vmentry_ctl, vmexit_ctl;
5760 	u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
5761 	unsigned long cr4;
5762 	u64 efer;
5763 
5764 	if (!dump_invalid_vmcs) {
5765 		pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5766 		return;
5767 	}
5768 
5769 	vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5770 	vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5771 	cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5772 	pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5773 	cr4 = vmcs_readl(GUEST_CR4);
5774 	efer = vmcs_read64(GUEST_IA32_EFER);
5775 	secondary_exec_control = 0;
5776 	if (cpu_has_secondary_exec_ctrls())
5777 		secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5778 
5779 	pr_err("*** Guest State ***\n");
5780 	pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5781 	       vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5782 	       vmcs_readl(CR0_GUEST_HOST_MASK));
5783 	pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5784 	       cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5785 	pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5786 	if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5787 	    (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5788 	{
5789 		pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
5790 		       vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5791 		pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
5792 		       vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
5793 	}
5794 	pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
5795 	       vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5796 	pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
5797 	       vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5798 	pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5799 	       vmcs_readl(GUEST_SYSENTER_ESP),
5800 	       vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5801 	vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
5802 	vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
5803 	vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
5804 	vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
5805 	vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
5806 	vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
5807 	vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5808 	vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5809 	vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5810 	vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
5811 	if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5812 	    (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5813 		pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
5814 		       efer, vmcs_read64(GUEST_IA32_PAT));
5815 	pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
5816 	       vmcs_read64(GUEST_IA32_DEBUGCTL),
5817 	       vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5818 	if (cpu_has_load_perf_global_ctrl() &&
5819 	    vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5820 		pr_err("PerfGlobCtl = 0x%016llx\n",
5821 		       vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5822 	if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5823 		pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5824 	pr_err("Interruptibility = %08x  ActivityState = %08x\n",
5825 	       vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5826 	       vmcs_read32(GUEST_ACTIVITY_STATE));
5827 	if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5828 		pr_err("InterruptStatus = %04x\n",
5829 		       vmcs_read16(GUEST_INTR_STATUS));
5830 
5831 	pr_err("*** Host State ***\n");
5832 	pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
5833 	       vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5834 	pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5835 	       vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5836 	       vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5837 	       vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5838 	       vmcs_read16(HOST_TR_SELECTOR));
5839 	pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5840 	       vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5841 	       vmcs_readl(HOST_TR_BASE));
5842 	pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5843 	       vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5844 	pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5845 	       vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5846 	       vmcs_readl(HOST_CR4));
5847 	pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5848 	       vmcs_readl(HOST_IA32_SYSENTER_ESP),
5849 	       vmcs_read32(HOST_IA32_SYSENTER_CS),
5850 	       vmcs_readl(HOST_IA32_SYSENTER_EIP));
5851 	if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5852 		pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
5853 		       vmcs_read64(HOST_IA32_EFER),
5854 		       vmcs_read64(HOST_IA32_PAT));
5855 	if (cpu_has_load_perf_global_ctrl() &&
5856 	    vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5857 		pr_err("PerfGlobCtl = 0x%016llx\n",
5858 		       vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
5859 
5860 	pr_err("*** Control State ***\n");
5861 	pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5862 	       pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5863 	pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5864 	pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5865 	       vmcs_read32(EXCEPTION_BITMAP),
5866 	       vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5867 	       vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5868 	pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5869 	       vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5870 	       vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5871 	       vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5872 	pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5873 	       vmcs_read32(VM_EXIT_INTR_INFO),
5874 	       vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5875 	       vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5876 	pr_err("        reason=%08x qualification=%016lx\n",
5877 	       vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5878 	pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5879 	       vmcs_read32(IDT_VECTORING_INFO_FIELD),
5880 	       vmcs_read32(IDT_VECTORING_ERROR_CODE));
5881 	pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5882 	if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5883 		pr_err("TSC Multiplier = 0x%016llx\n",
5884 		       vmcs_read64(TSC_MULTIPLIER));
5885 	if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
5886 		if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
5887 			u16 status = vmcs_read16(GUEST_INTR_STATUS);
5888 			pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
5889 		}
5890 		pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5891 		if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
5892 			pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
5893 		pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
5894 	}
5895 	if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5896 		pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5897 	if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5898 		pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5899 	if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5900 		pr_err("PLE Gap=%08x Window=%08x\n",
5901 		       vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5902 	if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5903 		pr_err("Virtual processor ID = 0x%04x\n",
5904 		       vmcs_read16(VIRTUAL_PROCESSOR_ID));
5905 }
5906 
5907 /*
5908  * The guest has exited.  See if we can fix it or if we need userspace
5909  * assistance.
5910  */
5911 static int vmx_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
5912 {
5913 	struct vcpu_vmx *vmx = to_vmx(vcpu);
5914 	u32 exit_reason = vmx->exit_reason;
5915 	u32 vectoring_info = vmx->idt_vectoring_info;
5916 
5917 	/*
5918 	 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5919 	 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5920 	 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5921 	 * mode as if vcpus is in root mode, the PML buffer must has been
5922 	 * flushed already.
5923 	 */
5924 	if (enable_pml)
5925 		vmx_flush_pml_buffer(vcpu);
5926 
5927 	/*
5928 	 * We should never reach this point with a pending nested VM-Enter, and
5929 	 * more specifically emulation of L2 due to invalid guest state (see
5930 	 * below) should never happen as that means we incorrectly allowed a
5931 	 * nested VM-Enter with an invalid vmcs12.
5932 	 */
5933 	WARN_ON_ONCE(vmx->nested.nested_run_pending);
5934 
5935 	/* If guest state is invalid, start emulating */
5936 	if (vmx->emulation_required)
5937 		return handle_invalid_guest_state(vcpu);
5938 
5939 	if (is_guest_mode(vcpu)) {
5940 		/*
5941 		 * The host physical addresses of some pages of guest memory
5942 		 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5943 		 * Page). The CPU may write to these pages via their host
5944 		 * physical address while L2 is running, bypassing any
5945 		 * address-translation-based dirty tracking (e.g. EPT write
5946 		 * protection).
5947 		 *
5948 		 * Mark them dirty on every exit from L2 to prevent them from
5949 		 * getting out of sync with dirty tracking.
5950 		 */
5951 		nested_mark_vmcs12_pages_dirty(vcpu);
5952 
5953 		if (nested_vmx_reflect_vmexit(vcpu))
5954 			return 1;
5955 	}
5956 
5957 	if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5958 		dump_vmcs();
5959 		vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5960 		vcpu->run->fail_entry.hardware_entry_failure_reason
5961 			= exit_reason;
5962 		vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5963 		return 0;
5964 	}
5965 
5966 	if (unlikely(vmx->fail)) {
5967 		dump_vmcs();
5968 		vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5969 		vcpu->run->fail_entry.hardware_entry_failure_reason
5970 			= vmcs_read32(VM_INSTRUCTION_ERROR);
5971 		vcpu->run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
5972 		return 0;
5973 	}
5974 
5975 	/*
5976 	 * Note:
5977 	 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5978 	 * delivery event since it indicates guest is accessing MMIO.
5979 	 * The vm-exit can be triggered again after return to guest that
5980 	 * will cause infinite loop.
5981 	 */
5982 	if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5983 			(exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5984 			exit_reason != EXIT_REASON_EPT_VIOLATION &&
5985 			exit_reason != EXIT_REASON_PML_FULL &&
5986 			exit_reason != EXIT_REASON_APIC_ACCESS &&
5987 			exit_reason != EXIT_REASON_TASK_SWITCH)) {
5988 		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5989 		vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5990 		vcpu->run->internal.ndata = 3;
5991 		vcpu->run->internal.data[0] = vectoring_info;
5992 		vcpu->run->internal.data[1] = exit_reason;
5993 		vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5994 		if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5995 			vcpu->run->internal.ndata++;
5996 			vcpu->run->internal.data[3] =
5997 				vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5998 		}
5999 		vcpu->run->internal.data[vcpu->run->internal.ndata++] =
6000 			vcpu->arch.last_vmentry_cpu;
6001 		return 0;
6002 	}
6003 
6004 	if (unlikely(!enable_vnmi &&
6005 		     vmx->loaded_vmcs->soft_vnmi_blocked)) {
6006 		if (!vmx_interrupt_blocked(vcpu)) {
6007 			vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6008 		} else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
6009 			   vcpu->arch.nmi_pending) {
6010 			/*
6011 			 * This CPU don't support us in finding the end of an
6012 			 * NMI-blocked window if the guest runs with IRQs
6013 			 * disabled. So we pull the trigger after 1 s of
6014 			 * futile waiting, but inform the user about this.
6015 			 */
6016 			printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6017 			       "state on VCPU %d after 1 s timeout\n",
6018 			       __func__, vcpu->vcpu_id);
6019 			vmx->loaded_vmcs->soft_vnmi_blocked = 0;
6020 		}
6021 	}
6022 
6023 	if (exit_fastpath != EXIT_FASTPATH_NONE)
6024 		return 1;
6025 
6026 	if (exit_reason >= kvm_vmx_max_exit_handlers)
6027 		goto unexpected_vmexit;
6028 #ifdef CONFIG_RETPOLINE
6029 	if (exit_reason == EXIT_REASON_MSR_WRITE)
6030 		return kvm_emulate_wrmsr(vcpu);
6031 	else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER)
6032 		return handle_preemption_timer(vcpu);
6033 	else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW)
6034 		return handle_interrupt_window(vcpu);
6035 	else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6036 		return handle_external_interrupt(vcpu);
6037 	else if (exit_reason == EXIT_REASON_HLT)
6038 		return kvm_emulate_halt(vcpu);
6039 	else if (exit_reason == EXIT_REASON_EPT_MISCONFIG)
6040 		return handle_ept_misconfig(vcpu);
6041 #endif
6042 
6043 	exit_reason = array_index_nospec(exit_reason,
6044 					 kvm_vmx_max_exit_handlers);
6045 	if (!kvm_vmx_exit_handlers[exit_reason])
6046 		goto unexpected_vmexit;
6047 
6048 	return kvm_vmx_exit_handlers[exit_reason](vcpu);
6049 
6050 unexpected_vmexit:
6051 	vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6052 	dump_vmcs();
6053 	vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6054 	vcpu->run->internal.suberror =
6055 			KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
6056 	vcpu->run->internal.ndata = 2;
6057 	vcpu->run->internal.data[0] = exit_reason;
6058 	vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
6059 	return 0;
6060 }
6061 
6062 /*
6063  * Software based L1D cache flush which is used when microcode providing
6064  * the cache control MSR is not loaded.
6065  *
6066  * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6067  * flush it is required to read in 64 KiB because the replacement algorithm
6068  * is not exactly LRU. This could be sized at runtime via topology
6069  * information but as all relevant affected CPUs have 32KiB L1D cache size
6070  * there is no point in doing so.
6071  */
6072 static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
6073 {
6074 	int size = PAGE_SIZE << L1D_CACHE_ORDER;
6075 
6076 	/*
6077 	 * This code is only executed when the the flush mode is 'cond' or
6078 	 * 'always'
6079 	 */
6080 	if (static_branch_likely(&vmx_l1d_flush_cond)) {
6081 		bool flush_l1d;
6082 
6083 		/*
6084 		 * Clear the per-vcpu flush bit, it gets set again
6085 		 * either from vcpu_run() or from one of the unsafe
6086 		 * VMEXIT handlers.
6087 		 */
6088 		flush_l1d = vcpu->arch.l1tf_flush_l1d;
6089 		vcpu->arch.l1tf_flush_l1d = false;
6090 
6091 		/*
6092 		 * Clear the per-cpu flush bit, it gets set again from
6093 		 * the interrupt handlers.
6094 		 */
6095 		flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
6096 		kvm_clear_cpu_l1tf_flush_l1d();
6097 
6098 		if (!flush_l1d)
6099 			return;
6100 	}
6101 
6102 	vcpu->stat.l1d_flush++;
6103 
6104 	if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
6105 		native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
6106 		return;
6107 	}
6108 
6109 	asm volatile(
6110 		/* First ensure the pages are in the TLB */
6111 		"xorl	%%eax, %%eax\n"
6112 		".Lpopulate_tlb:\n\t"
6113 		"movzbl	(%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6114 		"addl	$4096, %%eax\n\t"
6115 		"cmpl	%%eax, %[size]\n\t"
6116 		"jne	.Lpopulate_tlb\n\t"
6117 		"xorl	%%eax, %%eax\n\t"
6118 		"cpuid\n\t"
6119 		/* Now fill the cache */
6120 		"xorl	%%eax, %%eax\n"
6121 		".Lfill_cache:\n"
6122 		"movzbl	(%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
6123 		"addl	$64, %%eax\n\t"
6124 		"cmpl	%%eax, %[size]\n\t"
6125 		"jne	.Lfill_cache\n\t"
6126 		"lfence\n"
6127 		:: [flush_pages] "r" (vmx_l1d_flush_pages),
6128 		    [size] "r" (size)
6129 		: "eax", "ebx", "ecx", "edx");
6130 }
6131 
6132 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6133 {
6134 	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6135 	int tpr_threshold;
6136 
6137 	if (is_guest_mode(vcpu) &&
6138 		nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
6139 		return;
6140 
6141 	tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
6142 	if (is_guest_mode(vcpu))
6143 		to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
6144 	else
6145 		vmcs_write32(TPR_THRESHOLD, tpr_threshold);
6146 }
6147 
6148 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
6149 {
6150 	struct vcpu_vmx *vmx = to_vmx(vcpu);
6151 	u32 sec_exec_control;
6152 
6153 	if (!lapic_in_kernel(vcpu))
6154 		return;
6155 
6156 	if (!flexpriority_enabled &&
6157 	    !cpu_has_vmx_virtualize_x2apic_mode())
6158 		return;
6159 
6160 	/* Postpone execution until vmcs01 is the current VMCS. */
6161 	if (is_guest_mode(vcpu)) {
6162 		vmx->nested.change_vmcs01_virtual_apic_mode = true;
6163 		return;
6164 	}
6165 
6166 	sec_exec_control = secondary_exec_controls_get(vmx);
6167 	sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6168 			      SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
6169 
6170 	switch (kvm_get_apic_mode(vcpu)) {
6171 	case LAPIC_MODE_INVALID:
6172 		WARN_ONCE(true, "Invalid local APIC state");
6173 	case LAPIC_MODE_DISABLED:
6174 		break;
6175 	case LAPIC_MODE_XAPIC:
6176 		if (flexpriority_enabled) {
6177 			sec_exec_control |=
6178 				SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6179 			kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6180 
6181 			/*
6182 			 * Flush the TLB, reloading the APIC access page will
6183 			 * only do so if its physical address has changed, but
6184 			 * the guest may have inserted a non-APIC mapping into
6185 			 * the TLB while the APIC access page was disabled.
6186 			 */
6187 			kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
6188 		}
6189 		break;
6190 	case LAPIC_MODE_X2APIC:
6191 		if (cpu_has_vmx_virtualize_x2apic_mode())
6192 			sec_exec_control |=
6193 				SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6194 		break;
6195 	}
6196 	secondary_exec_controls_set(vmx, sec_exec_control);
6197 
6198 	vmx_update_msr_bitmap(vcpu);
6199 }
6200 
6201 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
6202 {
6203 	struct page *page;
6204 
6205 	/* Defer reload until vmcs01 is the current VMCS. */
6206 	if (is_guest_mode(vcpu)) {
6207 		to_vmx(vcpu)->nested.reload_vmcs01_apic_access_page = true;
6208 		return;
6209 	}
6210 
6211 	if (!(secondary_exec_controls_get(to_vmx(vcpu)) &
6212 	    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
6213 		return;
6214 
6215 	page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6216 	if (is_error_page(page))
6217 		return;
6218 
6219 	vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
6220 	vmx_flush_tlb_current(vcpu);
6221 
6222 	/*
6223 	 * Do not pin apic access page in memory, the MMU notifier
6224 	 * will call us again if it is migrated or swapped out.
6225 	 */
6226 	put_page(page);
6227 }
6228 
6229 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
6230 {
6231 	u16 status;
6232 	u8 old;
6233 
6234 	if (max_isr == -1)
6235 		max_isr = 0;
6236 
6237 	status = vmcs_read16(GUEST_INTR_STATUS);
6238 	old = status >> 8;
6239 	if (max_isr != old) {
6240 		status &= 0xff;
6241 		status |= max_isr << 8;
6242 		vmcs_write16(GUEST_INTR_STATUS, status);
6243 	}
6244 }
6245 
6246 static void vmx_set_rvi(int vector)
6247 {
6248 	u16 status;
6249 	u8 old;
6250 
6251 	if (vector == -1)
6252 		vector = 0;
6253 
6254 	status = vmcs_read16(GUEST_INTR_STATUS);
6255 	old = (u8)status & 0xff;
6256 	if ((u8)vector != old) {
6257 		status &= ~0xff;
6258 		status |= (u8)vector;
6259 		vmcs_write16(GUEST_INTR_STATUS, status);
6260 	}
6261 }
6262 
6263 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6264 {
6265 	/*
6266 	 * When running L2, updating RVI is only relevant when
6267 	 * vmcs12 virtual-interrupt-delivery enabled.
6268 	 * However, it can be enabled only when L1 also
6269 	 * intercepts external-interrupts and in that case
6270 	 * we should not update vmcs02 RVI but instead intercept
6271 	 * interrupt. Therefore, do nothing when running L2.
6272 	 */
6273 	if (!is_guest_mode(vcpu))
6274 		vmx_set_rvi(max_irr);
6275 }
6276 
6277 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
6278 {
6279 	struct vcpu_vmx *vmx = to_vmx(vcpu);
6280 	int max_irr;
6281 	bool max_irr_updated;
6282 
6283 	WARN_ON(!vcpu->arch.apicv_active);
6284 	if (pi_test_on(&vmx->pi_desc)) {
6285 		pi_clear_on(&vmx->pi_desc);
6286 		/*
6287 		 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6288 		 * But on x86 this is just a compiler barrier anyway.
6289 		 */
6290 		smp_mb__after_atomic();
6291 		max_irr_updated =
6292 			kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
6293 
6294 		/*
6295 		 * If we are running L2 and L1 has a new pending interrupt
6296 		 * which can be injected, we should re-evaluate
6297 		 * what should be done with this new L1 interrupt.
6298 		 * If L1 intercepts external-interrupts, we should
6299 		 * exit from L2 to L1. Otherwise, interrupt should be
6300 		 * delivered directly to L2.
6301 		 */
6302 		if (is_guest_mode(vcpu) && max_irr_updated) {
6303 			if (nested_exit_on_intr(vcpu))
6304 				kvm_vcpu_exiting_guest_mode(vcpu);
6305 			else
6306 				kvm_make_request(KVM_REQ_EVENT, vcpu);
6307 		}
6308 	} else {
6309 		max_irr = kvm_lapic_find_highest_irr(vcpu);
6310 	}
6311 	vmx_hwapic_irr_update(vcpu, max_irr);
6312 	return max_irr;
6313 }
6314 
6315 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6316 {
6317 	if (!kvm_vcpu_apicv_active(vcpu))
6318 		return;
6319 
6320 	vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6321 	vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6322 	vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6323 	vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6324 }
6325 
6326 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
6327 {
6328 	struct vcpu_vmx *vmx = to_vmx(vcpu);
6329 
6330 	pi_clear_on(&vmx->pi_desc);
6331 	memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
6332 }
6333 
6334 void vmx_do_interrupt_nmi_irqoff(unsigned long entry);
6335 
6336 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu *vcpu, u32 intr_info)
6337 {
6338 	unsigned int vector = intr_info & INTR_INFO_VECTOR_MASK;
6339 	gate_desc *desc = (gate_desc *)host_idt_base + vector;
6340 
6341 	kvm_before_interrupt(vcpu);
6342 	vmx_do_interrupt_nmi_irqoff(gate_offset(desc));
6343 	kvm_after_interrupt(vcpu);
6344 }
6345 
6346 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx)
6347 {
6348 	u32 intr_info = vmx_get_intr_info(&vmx->vcpu);
6349 
6350 	/* if exit due to PF check for async PF */
6351 	if (is_page_fault(intr_info))
6352 		vmx->vcpu.arch.apf.host_apf_flags = kvm_read_and_reset_apf_flags();
6353 	/* Handle machine checks before interrupts are enabled */
6354 	else if (is_machine_check(intr_info))
6355 		kvm_machine_check();
6356 	/* We need to handle NMIs before interrupts are enabled */
6357 	else if (is_nmi(intr_info))
6358 		handle_interrupt_nmi_irqoff(&vmx->vcpu, intr_info);
6359 }
6360 
6361 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu)
6362 {
6363 	u32 intr_info = vmx_get_intr_info(vcpu);
6364 
6365 	if (WARN_ONCE(!is_external_intr(intr_info),
6366 	    "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info))
6367 		return;
6368 
6369 	handle_interrupt_nmi_irqoff(vcpu, intr_info);
6370 }
6371 
6372 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu)
6373 {
6374 	struct vcpu_vmx *vmx = to_vmx(vcpu);
6375 
6376 	if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
6377 		handle_external_interrupt_irqoff(vcpu);
6378 	else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)
6379 		handle_exception_nmi_irqoff(vmx);
6380 }
6381 
6382 /*
6383  * The kvm parameter can be NULL (module initialization, or invocation before
6384  * VM creation). Be sure to check the kvm parameter before using it.
6385  */
6386 static bool vmx_has_emulated_msr(struct kvm *kvm, u32 index)
6387 {
6388 	switch (index) {
6389 	case MSR_IA32_SMBASE:
6390 		/*
6391 		 * We cannot do SMM unless we can run the guest in big
6392 		 * real mode.
6393 		 */
6394 		return enable_unrestricted_guest || emulate_invalid_guest_state;
6395 	case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
6396 		return nested;
6397 	case MSR_AMD64_VIRT_SPEC_CTRL:
6398 		/* This is AMD only.  */
6399 		return false;
6400 	default:
6401 		return true;
6402 	}
6403 }
6404 
6405 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6406 {
6407 	u32 exit_intr_info;
6408 	bool unblock_nmi;
6409 	u8 vector;
6410 	bool idtv_info_valid;
6411 
6412 	idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6413 
6414 	if (enable_vnmi) {
6415 		if (vmx->loaded_vmcs->nmi_known_unmasked)
6416 			return;
6417 
6418 		exit_intr_info = vmx_get_intr_info(&vmx->vcpu);
6419 		unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6420 		vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6421 		/*
6422 		 * SDM 3: 27.7.1.2 (September 2008)
6423 		 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6424 		 * a guest IRET fault.
6425 		 * SDM 3: 23.2.2 (September 2008)
6426 		 * Bit 12 is undefined in any of the following cases:
6427 		 *  If the VM exit sets the valid bit in the IDT-vectoring
6428 		 *   information field.
6429 		 *  If the VM exit is due to a double fault.
6430 		 */
6431 		if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6432 		    vector != DF_VECTOR && !idtv_info_valid)
6433 			vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6434 				      GUEST_INTR_STATE_NMI);
6435 		else
6436 			vmx->loaded_vmcs->nmi_known_unmasked =
6437 				!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6438 				  & GUEST_INTR_STATE_NMI);
6439 	} else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
6440 		vmx->loaded_vmcs->vnmi_blocked_time +=
6441 			ktime_to_ns(ktime_sub(ktime_get(),
6442 					      vmx->loaded_vmcs->entry_time));
6443 }
6444 
6445 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6446 				      u32 idt_vectoring_info,
6447 				      int instr_len_field,
6448 				      int error_code_field)
6449 {
6450 	u8 vector;
6451 	int type;
6452 	bool idtv_info_valid;
6453 
6454 	idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6455 
6456 	vcpu->arch.nmi_injected = false;
6457 	kvm_clear_exception_queue(vcpu);
6458 	kvm_clear_interrupt_queue(vcpu);
6459 
6460 	if (!idtv_info_valid)
6461 		return;
6462 
6463 	kvm_make_request(KVM_REQ_EVENT, vcpu);
6464 
6465 	vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6466 	type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6467 
6468 	switch (type) {
6469 	case INTR_TYPE_NMI_INTR:
6470 		vcpu->arch.nmi_injected = true;
6471 		/*
6472 		 * SDM 3: 27.7.1.2 (September 2008)
6473 		 * Clear bit "block by NMI" before VM entry if a NMI
6474 		 * delivery faulted.
6475 		 */
6476 		vmx_set_nmi_mask(vcpu, false);
6477 		break;
6478 	case INTR_TYPE_SOFT_EXCEPTION:
6479 		vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6480 		fallthrough;
6481 	case INTR_TYPE_HARD_EXCEPTION:
6482 		if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6483 			u32 err = vmcs_read32(error_code_field);
6484 			kvm_requeue_exception_e(vcpu, vector, err);
6485 		} else
6486 			kvm_requeue_exception(vcpu, vector);
6487 		break;
6488 	case INTR_TYPE_SOFT_INTR:
6489 		vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6490 		fallthrough;
6491 	case INTR_TYPE_EXT_INTR:
6492 		kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6493 		break;
6494 	default:
6495 		break;
6496 	}
6497 }
6498 
6499 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6500 {
6501 	__vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6502 				  VM_EXIT_INSTRUCTION_LEN,
6503 				  IDT_VECTORING_ERROR_CODE);
6504 }
6505 
6506 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6507 {
6508 	__vmx_complete_interrupts(vcpu,
6509 				  vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6510 				  VM_ENTRY_INSTRUCTION_LEN,
6511 				  VM_ENTRY_EXCEPTION_ERROR_CODE);
6512 
6513 	vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6514 }
6515 
6516 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6517 {
6518 	int i, nr_msrs;
6519 	struct perf_guest_switch_msr *msrs;
6520 
6521 	msrs = perf_guest_get_msrs(&nr_msrs);
6522 
6523 	if (!msrs)
6524 		return;
6525 
6526 	for (i = 0; i < nr_msrs; i++)
6527 		if (msrs[i].host == msrs[i].guest)
6528 			clear_atomic_switch_msr(vmx, msrs[i].msr);
6529 		else
6530 			add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6531 					msrs[i].host, false);
6532 }
6533 
6534 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
6535 {
6536 	struct vcpu_vmx *vmx = to_vmx(vcpu);
6537 	u64 tscl;
6538 	u32 delta_tsc;
6539 
6540 	if (vmx->req_immediate_exit) {
6541 		vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0);
6542 		vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6543 	} else if (vmx->hv_deadline_tsc != -1) {
6544 		tscl = rdtsc();
6545 		if (vmx->hv_deadline_tsc > tscl)
6546 			/* set_hv_timer ensures the delta fits in 32-bits */
6547 			delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6548 				cpu_preemption_timer_multi);
6549 		else
6550 			delta_tsc = 0;
6551 
6552 		vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
6553 		vmx->loaded_vmcs->hv_timer_soft_disabled = false;
6554 	} else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) {
6555 		vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1);
6556 		vmx->loaded_vmcs->hv_timer_soft_disabled = true;
6557 	}
6558 }
6559 
6560 void noinstr vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp)
6561 {
6562 	if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
6563 		vmx->loaded_vmcs->host_state.rsp = host_rsp;
6564 		vmcs_writel(HOST_RSP, host_rsp);
6565 	}
6566 }
6567 
6568 static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
6569 {
6570 	switch (to_vmx(vcpu)->exit_reason) {
6571 	case EXIT_REASON_MSR_WRITE:
6572 		return handle_fastpath_set_msr_irqoff(vcpu);
6573 	case EXIT_REASON_PREEMPTION_TIMER:
6574 		return handle_fastpath_preemption_timer(vcpu);
6575 	default:
6576 		return EXIT_FASTPATH_NONE;
6577 	}
6578 }
6579 
6580 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched);
6581 
6582 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
6583 					struct vcpu_vmx *vmx)
6584 {
6585 	/*
6586 	 * VMENTER enables interrupts (host state), but the kernel state is
6587 	 * interrupts disabled when this is invoked. Also tell RCU about
6588 	 * it. This is the same logic as for exit_to_user_mode().
6589 	 *
6590 	 * This ensures that e.g. latency analysis on the host observes
6591 	 * guest mode as interrupt enabled.
6592 	 *
6593 	 * guest_enter_irqoff() informs context tracking about the
6594 	 * transition to guest mode and if enabled adjusts RCU state
6595 	 * accordingly.
6596 	 */
6597 	instrumentation_begin();
6598 	trace_hardirqs_on_prepare();
6599 	lockdep_hardirqs_on_prepare(CALLER_ADDR0);
6600 	instrumentation_end();
6601 
6602 	guest_enter_irqoff();
6603 	lockdep_hardirqs_on(CALLER_ADDR0);
6604 
6605 	/* L1D Flush includes CPU buffer clear to mitigate MDS */
6606 	if (static_branch_unlikely(&vmx_l1d_should_flush))
6607 		vmx_l1d_flush(vcpu);
6608 	else if (static_branch_unlikely(&mds_user_clear))
6609 		mds_clear_cpu_buffers();
6610 
6611 	if (vcpu->arch.cr2 != native_read_cr2())
6612 		native_write_cr2(vcpu->arch.cr2);
6613 
6614 	vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs,
6615 				   vmx->loaded_vmcs->launched);
6616 
6617 	vcpu->arch.cr2 = native_read_cr2();
6618 
6619 	/*
6620 	 * VMEXIT disables interrupts (host state), but tracing and lockdep
6621 	 * have them in state 'on' as recorded before entering guest mode.
6622 	 * Same as enter_from_user_mode().
6623 	 *
6624 	 * guest_exit_irqoff() restores host context and reinstates RCU if
6625 	 * enabled and required.
6626 	 *
6627 	 * This needs to be done before the below as native_read_msr()
6628 	 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
6629 	 * into world and some more.
6630 	 */
6631 	lockdep_hardirqs_off(CALLER_ADDR0);
6632 	guest_exit_irqoff();
6633 
6634 	instrumentation_begin();
6635 	trace_hardirqs_off_finish();
6636 	instrumentation_end();
6637 }
6638 
6639 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
6640 {
6641 	fastpath_t exit_fastpath;
6642 	struct vcpu_vmx *vmx = to_vmx(vcpu);
6643 	unsigned long cr3, cr4;
6644 
6645 reenter_guest:
6646 	/* Record the guest's net vcpu time for enforced NMI injections. */
6647 	if (unlikely(!enable_vnmi &&
6648 		     vmx->loaded_vmcs->soft_vnmi_blocked))
6649 		vmx->loaded_vmcs->entry_time = ktime_get();
6650 
6651 	/* Don't enter VMX if guest state is invalid, let the exit handler
6652 	   start emulation until we arrive back to a valid state */
6653 	if (vmx->emulation_required)
6654 		return EXIT_FASTPATH_NONE;
6655 
6656 	if (vmx->ple_window_dirty) {
6657 		vmx->ple_window_dirty = false;
6658 		vmcs_write32(PLE_WINDOW, vmx->ple_window);
6659 	}
6660 
6661 	/*
6662 	 * We did this in prepare_switch_to_guest, because it needs to
6663 	 * be within srcu_read_lock.
6664 	 */
6665 	WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync);
6666 
6667 	if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP))
6668 		vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6669 	if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP))
6670 		vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6671 
6672 	cr3 = __get_current_cr3_fast();
6673 	if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6674 		vmcs_writel(HOST_CR3, cr3);
6675 		vmx->loaded_vmcs->host_state.cr3 = cr3;
6676 	}
6677 
6678 	cr4 = cr4_read_shadow();
6679 	if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6680 		vmcs_writel(HOST_CR4, cr4);
6681 		vmx->loaded_vmcs->host_state.cr4 = cr4;
6682 	}
6683 
6684 	/* When single-stepping over STI and MOV SS, we must clear the
6685 	 * corresponding interruptibility bits in the guest state. Otherwise
6686 	 * vmentry fails as it then expects bit 14 (BS) in pending debug
6687 	 * exceptions being set, but that's not correct for the guest debugging
6688 	 * case. */
6689 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6690 		vmx_set_interrupt_shadow(vcpu, 0);
6691 
6692 	kvm_load_guest_xsave_state(vcpu);
6693 
6694 	pt_guest_enter(vmx);
6695 
6696 	atomic_switch_perf_msrs(vmx);
6697 
6698 	if (enable_preemption_timer)
6699 		vmx_update_hv_timer(vcpu);
6700 
6701 	kvm_wait_lapic_expire(vcpu);
6702 
6703 	/*
6704 	 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6705 	 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6706 	 * is no need to worry about the conditional branch over the wrmsr
6707 	 * being speculatively taken.
6708 	 */
6709 	x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
6710 
6711 	/* The actual VMENTER/EXIT is in the .noinstr.text section. */
6712 	vmx_vcpu_enter_exit(vcpu, vmx);
6713 
6714 	/*
6715 	 * We do not use IBRS in the kernel. If this vCPU has used the
6716 	 * SPEC_CTRL MSR it may have left it on; save the value and
6717 	 * turn it off. This is much more efficient than blindly adding
6718 	 * it to the atomic save/restore list. Especially as the former
6719 	 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6720 	 *
6721 	 * For non-nested case:
6722 	 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6723 	 * save it.
6724 	 *
6725 	 * For nested case:
6726 	 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6727 	 * save it.
6728 	 */
6729 	if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6730 		vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
6731 
6732 	x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
6733 
6734 	/* All fields are clean at this point */
6735 	if (static_branch_unlikely(&enable_evmcs))
6736 		current_evmcs->hv_clean_fields |=
6737 			HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
6738 
6739 	if (static_branch_unlikely(&enable_evmcs))
6740 		current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index;
6741 
6742 	/* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6743 	if (vmx->host_debugctlmsr)
6744 		update_debugctlmsr(vmx->host_debugctlmsr);
6745 
6746 #ifndef CONFIG_X86_64
6747 	/*
6748 	 * The sysexit path does not restore ds/es, so we must set them to
6749 	 * a reasonable value ourselves.
6750 	 *
6751 	 * We can't defer this to vmx_prepare_switch_to_host() since that
6752 	 * function may be executed in interrupt context, which saves and
6753 	 * restore segments around it, nullifying its effect.
6754 	 */
6755 	loadsegment(ds, __USER_DS);
6756 	loadsegment(es, __USER_DS);
6757 #endif
6758 
6759 	vmx_register_cache_reset(vcpu);
6760 
6761 	pt_guest_exit(vmx);
6762 
6763 	kvm_load_host_xsave_state(vcpu);
6764 
6765 	vmx->nested.nested_run_pending = 0;
6766 	vmx->idt_vectoring_info = 0;
6767 
6768 	if (unlikely(vmx->fail)) {
6769 		vmx->exit_reason = 0xdead;
6770 		return EXIT_FASTPATH_NONE;
6771 	}
6772 
6773 	vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6774 	if (unlikely((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY))
6775 		kvm_machine_check();
6776 
6777 	trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6778 
6779 	if (unlikely(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6780 		return EXIT_FASTPATH_NONE;
6781 
6782 	vmx->loaded_vmcs->launched = 1;
6783 	vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6784 
6785 	vmx_recover_nmi_blocking(vmx);
6786 	vmx_complete_interrupts(vmx);
6787 
6788 	if (is_guest_mode(vcpu))
6789 		return EXIT_FASTPATH_NONE;
6790 
6791 	exit_fastpath = vmx_exit_handlers_fastpath(vcpu);
6792 	if (exit_fastpath == EXIT_FASTPATH_REENTER_GUEST) {
6793 		if (!kvm_vcpu_exit_request(vcpu)) {
6794 			/*
6795 			 * FIXME: this goto should be a loop in vcpu_enter_guest,
6796 			 * but it would incur the cost of a retpoline for now.
6797 			 * Revisit once static calls are available.
6798 			 */
6799 			if (vcpu->arch.apicv_active)
6800 				vmx_sync_pir_to_irr(vcpu);
6801 			goto reenter_guest;
6802 		}
6803 		exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
6804 	}
6805 
6806 	return exit_fastpath;
6807 }
6808 
6809 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6810 {
6811 	struct vcpu_vmx *vmx = to_vmx(vcpu);
6812 
6813 	if (enable_pml)
6814 		vmx_destroy_pml_buffer(vmx);
6815 	free_vpid(vmx->vpid);
6816 	nested_vmx_free_vcpu(vcpu);
6817 	free_loaded_vmcs(vmx->loaded_vmcs);
6818 }
6819 
6820 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
6821 {
6822 	struct vcpu_vmx *vmx;
6823 	int i, cpu, err;
6824 
6825 	BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0);
6826 	vmx = to_vmx(vcpu);
6827 
6828 	err = -ENOMEM;
6829 
6830 	vmx->vpid = allocate_vpid();
6831 
6832 	/*
6833 	 * If PML is turned on, failure on enabling PML just results in failure
6834 	 * of creating the vcpu, therefore we can simplify PML logic (by
6835 	 * avoiding dealing with cases, such as enabling PML partially on vcpus
6836 	 * for the guest), etc.
6837 	 */
6838 	if (enable_pml) {
6839 		vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
6840 		if (!vmx->pml_pg)
6841 			goto free_vpid;
6842 	}
6843 
6844 	BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list) != MAX_NR_USER_RETURN_MSRS);
6845 
6846 	for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i) {
6847 		u32 index = vmx_uret_msrs_list[i];
6848 		u32 data_low, data_high;
6849 		int j = vmx->nr_uret_msrs;
6850 
6851 		if (rdmsr_safe(index, &data_low, &data_high) < 0)
6852 			continue;
6853 		if (wrmsr_safe(index, data_low, data_high) < 0)
6854 			continue;
6855 
6856 		vmx->guest_uret_msrs[j].slot = i;
6857 		vmx->guest_uret_msrs[j].data = 0;
6858 		switch (index) {
6859 		case MSR_IA32_TSX_CTRL:
6860 			/*
6861 			 * No need to pass TSX_CTRL_CPUID_CLEAR through, so
6862 			 * let's avoid changing CPUID bits under the host
6863 			 * kernel's feet.
6864 			 */
6865 			vmx->guest_uret_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR;
6866 			break;
6867 		default:
6868 			vmx->guest_uret_msrs[j].mask = -1ull;
6869 			break;
6870 		}
6871 		++vmx->nr_uret_msrs;
6872 	}
6873 
6874 	err = alloc_loaded_vmcs(&vmx->vmcs01);
6875 	if (err < 0)
6876 		goto free_pml;
6877 
6878 	/* The MSR bitmap starts with all ones */
6879 	bitmap_fill(vmx->shadow_msr_intercept.read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6880 	bitmap_fill(vmx->shadow_msr_intercept.write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
6881 
6882 	vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
6883 	vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
6884 	vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
6885 	vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6886 	vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6887 	vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6888 	vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6889 	if (kvm_cstate_in_guest(vcpu->kvm)) {
6890 		vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R);
6891 		vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R);
6892 		vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R);
6893 		vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R);
6894 	}
6895 	vmx->msr_bitmap_mode = 0;
6896 
6897 	vmx->loaded_vmcs = &vmx->vmcs01;
6898 	cpu = get_cpu();
6899 	vmx_vcpu_load(vcpu, cpu);
6900 	vcpu->cpu = cpu;
6901 	init_vmcs(vmx);
6902 	vmx_vcpu_put(vcpu);
6903 	put_cpu();
6904 	if (cpu_need_virtualize_apic_accesses(vcpu)) {
6905 		err = alloc_apic_access_page(vcpu->kvm);
6906 		if (err)
6907 			goto free_vmcs;
6908 	}
6909 
6910 	if (enable_ept && !enable_unrestricted_guest) {
6911 		err = init_rmode_identity_map(vcpu->kvm);
6912 		if (err)
6913 			goto free_vmcs;
6914 	}
6915 
6916 	if (nested)
6917 		memcpy(&vmx->nested.msrs, &vmcs_config.nested, sizeof(vmx->nested.msrs));
6918 	else
6919 		memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
6920 
6921 	vmx->nested.posted_intr_nv = -1;
6922 	vmx->nested.current_vmptr = -1ull;
6923 
6924 	vcpu->arch.microcode_version = 0x100000000ULL;
6925 	vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED;
6926 
6927 	/*
6928 	 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6929 	 * or POSTED_INTR_WAKEUP_VECTOR.
6930 	 */
6931 	vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6932 	vmx->pi_desc.sn = 1;
6933 
6934 	vmx->ept_pointer = INVALID_PAGE;
6935 
6936 	return 0;
6937 
6938 free_vmcs:
6939 	free_loaded_vmcs(vmx->loaded_vmcs);
6940 free_pml:
6941 	vmx_destroy_pml_buffer(vmx);
6942 free_vpid:
6943 	free_vpid(vmx->vpid);
6944 	return err;
6945 }
6946 
6947 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6948 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6949 
6950 static int vmx_vm_init(struct kvm *kvm)
6951 {
6952 	spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
6953 
6954 	if (!ple_gap)
6955 		kvm->arch.pause_in_guest = true;
6956 
6957 	if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6958 		switch (l1tf_mitigation) {
6959 		case L1TF_MITIGATION_OFF:
6960 		case L1TF_MITIGATION_FLUSH_NOWARN:
6961 			/* 'I explicitly don't care' is set */
6962 			break;
6963 		case L1TF_MITIGATION_FLUSH:
6964 		case L1TF_MITIGATION_FLUSH_NOSMT:
6965 		case L1TF_MITIGATION_FULL:
6966 			/*
6967 			 * Warn upon starting the first VM in a potentially
6968 			 * insecure environment.
6969 			 */
6970 			if (sched_smt_active())
6971 				pr_warn_once(L1TF_MSG_SMT);
6972 			if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6973 				pr_warn_once(L1TF_MSG_L1D);
6974 			break;
6975 		case L1TF_MITIGATION_FULL_FORCE:
6976 			/* Flush is enforced */
6977 			break;
6978 		}
6979 	}
6980 	kvm_apicv_init(kvm, enable_apicv);
6981 	return 0;
6982 }
6983 
6984 static int __init vmx_check_processor_compat(void)
6985 {
6986 	struct vmcs_config vmcs_conf;
6987 	struct vmx_capability vmx_cap;
6988 
6989 	if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
6990 	    !this_cpu_has(X86_FEATURE_VMX)) {
6991 		pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6992 		return -EIO;
6993 	}
6994 
6995 	if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6996 		return -EIO;
6997 	if (nested)
6998 		nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept);
6999 	if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7000 		printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7001 				smp_processor_id());
7002 		return -EIO;
7003 	}
7004 	return 0;
7005 }
7006 
7007 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7008 {
7009 	u8 cache;
7010 	u64 ipat = 0;
7011 
7012 	/* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
7013 	 * memory aliases with conflicting memory types and sometimes MCEs.
7014 	 * We have to be careful as to what are honored and when.
7015 	 *
7016 	 * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
7017 	 * UC.  The effective memory type is UC or WC depending on guest PAT.
7018 	 * This was historically the source of MCEs and we want to be
7019 	 * conservative.
7020 	 *
7021 	 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7022 	 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
7023 	 * EPT memory type is set to WB.  The effective memory type is forced
7024 	 * WB.
7025 	 *
7026 	 * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
7027 	 * EPT memory type is used to emulate guest CD/MTRR.
7028 	 */
7029 
7030 	if (is_mmio) {
7031 		cache = MTRR_TYPE_UNCACHABLE;
7032 		goto exit;
7033 	}
7034 
7035 	if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
7036 		ipat = VMX_EPT_IPAT_BIT;
7037 		cache = MTRR_TYPE_WRBACK;
7038 		goto exit;
7039 	}
7040 
7041 	if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
7042 		ipat = VMX_EPT_IPAT_BIT;
7043 		if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
7044 			cache = MTRR_TYPE_WRBACK;
7045 		else
7046 			cache = MTRR_TYPE_UNCACHABLE;
7047 		goto exit;
7048 	}
7049 
7050 	cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
7051 
7052 exit:
7053 	return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
7054 }
7055 
7056 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx)
7057 {
7058 	/*
7059 	 * These bits in the secondary execution controls field
7060 	 * are dynamic, the others are mostly based on the hypervisor
7061 	 * architecture and the guest's CPUID.  Do not touch the
7062 	 * dynamic bits.
7063 	 */
7064 	u32 mask =
7065 		SECONDARY_EXEC_SHADOW_VMCS |
7066 		SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
7067 		SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7068 		SECONDARY_EXEC_DESC;
7069 
7070 	u32 new_ctl = vmx->secondary_exec_control;
7071 	u32 cur_ctl = secondary_exec_controls_get(vmx);
7072 
7073 	secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask));
7074 }
7075 
7076 /*
7077  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7078  * (indicating "allowed-1") if they are supported in the guest's CPUID.
7079  */
7080 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
7081 {
7082 	struct vcpu_vmx *vmx = to_vmx(vcpu);
7083 	struct kvm_cpuid_entry2 *entry;
7084 
7085 	vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
7086 	vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
7087 
7088 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {		\
7089 	if (entry && (entry->_reg & (_cpuid_mask)))			\
7090 		vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask);	\
7091 } while (0)
7092 
7093 	entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
7094 	cr4_fixed1_update(X86_CR4_VME,        edx, feature_bit(VME));
7095 	cr4_fixed1_update(X86_CR4_PVI,        edx, feature_bit(VME));
7096 	cr4_fixed1_update(X86_CR4_TSD,        edx, feature_bit(TSC));
7097 	cr4_fixed1_update(X86_CR4_DE,         edx, feature_bit(DE));
7098 	cr4_fixed1_update(X86_CR4_PSE,        edx, feature_bit(PSE));
7099 	cr4_fixed1_update(X86_CR4_PAE,        edx, feature_bit(PAE));
7100 	cr4_fixed1_update(X86_CR4_MCE,        edx, feature_bit(MCE));
7101 	cr4_fixed1_update(X86_CR4_PGE,        edx, feature_bit(PGE));
7102 	cr4_fixed1_update(X86_CR4_OSFXSR,     edx, feature_bit(FXSR));
7103 	cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM));
7104 	cr4_fixed1_update(X86_CR4_VMXE,       ecx, feature_bit(VMX));
7105 	cr4_fixed1_update(X86_CR4_SMXE,       ecx, feature_bit(SMX));
7106 	cr4_fixed1_update(X86_CR4_PCIDE,      ecx, feature_bit(PCID));
7107 	cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, feature_bit(XSAVE));
7108 
7109 	entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7110 	cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, feature_bit(FSGSBASE));
7111 	cr4_fixed1_update(X86_CR4_SMEP,       ebx, feature_bit(SMEP));
7112 	cr4_fixed1_update(X86_CR4_SMAP,       ebx, feature_bit(SMAP));
7113 	cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
7114 	cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
7115 	cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
7116 
7117 #undef cr4_fixed1_update
7118 }
7119 
7120 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
7121 {
7122 	struct vcpu_vmx *vmx = to_vmx(vcpu);
7123 
7124 	if (kvm_mpx_supported()) {
7125 		bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
7126 
7127 		if (mpx_enabled) {
7128 			vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
7129 			vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
7130 		} else {
7131 			vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
7132 			vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
7133 		}
7134 	}
7135 }
7136 
7137 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu)
7138 {
7139 	struct vcpu_vmx *vmx = to_vmx(vcpu);
7140 	struct kvm_cpuid_entry2 *best = NULL;
7141 	int i;
7142 
7143 	for (i = 0; i < PT_CPUID_LEAVES; i++) {
7144 		best = kvm_find_cpuid_entry(vcpu, 0x14, i);
7145 		if (!best)
7146 			return;
7147 		vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax;
7148 		vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx;
7149 		vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx;
7150 		vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx;
7151 	}
7152 
7153 	/* Get the number of configurable Address Ranges for filtering */
7154 	vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps,
7155 						PT_CAP_num_address_ranges);
7156 
7157 	/* Initialize and clear the no dependency bits */
7158 	vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS |
7159 			RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC);
7160 
7161 	/*
7162 	 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7163 	 * will inject an #GP
7164 	 */
7165 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering))
7166 		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN;
7167 
7168 	/*
7169 	 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7170 	 * PSBFreq can be set
7171 	 */
7172 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc))
7173 		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC |
7174 				RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ);
7175 
7176 	/*
7177 	 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7178 	 * MTCFreq can be set
7179 	 */
7180 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc))
7181 		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN |
7182 				RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE);
7183 
7184 	/* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7185 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite))
7186 		vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW |
7187 							RTIT_CTL_PTW_EN);
7188 
7189 	/* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7190 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace))
7191 		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN;
7192 
7193 	/* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7194 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output))
7195 		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA;
7196 
7197 	/* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */
7198 	if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys))
7199 		vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN;
7200 
7201 	/* unmask address range configure area */
7202 	for (i = 0; i < vmx->pt_desc.addr_range; i++)
7203 		vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4));
7204 }
7205 
7206 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
7207 {
7208 	struct vcpu_vmx *vmx = to_vmx(vcpu);
7209 
7210 	/* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7211 	vcpu->arch.xsaves_enabled = false;
7212 
7213 	if (cpu_has_secondary_exec_ctrls()) {
7214 		vmx_compute_secondary_exec_control(vmx);
7215 		vmcs_set_secondary_exec_control(vmx);
7216 	}
7217 
7218 	if (nested_vmx_allowed(vcpu))
7219 		to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7220 			FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7221 			FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
7222 	else
7223 		to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7224 			~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
7225 			  FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX);
7226 
7227 	if (nested_vmx_allowed(vcpu)) {
7228 		nested_vmx_cr_fixed1_bits_update(vcpu);
7229 		nested_vmx_entry_exit_ctls_update(vcpu);
7230 	}
7231 
7232 	if (boot_cpu_has(X86_FEATURE_INTEL_PT) &&
7233 			guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT))
7234 		update_intel_pt_cfg(vcpu);
7235 
7236 	if (boot_cpu_has(X86_FEATURE_RTM)) {
7237 		struct vmx_uret_msr *msr;
7238 		msr = vmx_find_uret_msr(vmx, MSR_IA32_TSX_CTRL);
7239 		if (msr) {
7240 			bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM);
7241 			vmx_set_guest_uret_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE);
7242 		}
7243 	}
7244 
7245 	set_cr4_guest_host_mask(vmx);
7246 
7247 	/* Refresh #PF interception to account for MAXPHYADDR changes. */
7248 	update_exception_bitmap(vcpu);
7249 }
7250 
7251 static __init void vmx_set_cpu_caps(void)
7252 {
7253 	kvm_set_cpu_caps();
7254 
7255 	/* CPUID 0x1 */
7256 	if (nested)
7257 		kvm_cpu_cap_set(X86_FEATURE_VMX);
7258 
7259 	/* CPUID 0x7 */
7260 	if (kvm_mpx_supported())
7261 		kvm_cpu_cap_check_and_set(X86_FEATURE_MPX);
7262 	if (cpu_has_vmx_invpcid())
7263 		kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
7264 	if (vmx_pt_mode_is_host_guest())
7265 		kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
7266 
7267 	if (vmx_umip_emulated())
7268 		kvm_cpu_cap_set(X86_FEATURE_UMIP);
7269 
7270 	/* CPUID 0xD.1 */
7271 	supported_xss = 0;
7272 	if (!cpu_has_vmx_xsaves())
7273 		kvm_cpu_cap_clear(X86_FEATURE_XSAVES);
7274 
7275 	/* CPUID 0x80000001 */
7276 	if (!cpu_has_vmx_rdtscp())
7277 		kvm_cpu_cap_clear(X86_FEATURE_RDTSCP);
7278 
7279 	if (cpu_has_vmx_waitpkg())
7280 		kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG);
7281 }
7282 
7283 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
7284 {
7285 	to_vmx(vcpu)->req_immediate_exit = true;
7286 }
7287 
7288 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu,
7289 				  struct x86_instruction_info *info)
7290 {
7291 	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7292 	unsigned short port;
7293 	bool intercept;
7294 	int size;
7295 
7296 	if (info->intercept == x86_intercept_in ||
7297 	    info->intercept == x86_intercept_ins) {
7298 		port = info->src_val;
7299 		size = info->dst_bytes;
7300 	} else {
7301 		port = info->dst_val;
7302 		size = info->src_bytes;
7303 	}
7304 
7305 	/*
7306 	 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7307 	 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7308 	 * control.
7309 	 *
7310 	 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7311 	 */
7312 	if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7313 		intercept = nested_cpu_has(vmcs12,
7314 					   CPU_BASED_UNCOND_IO_EXITING);
7315 	else
7316 		intercept = nested_vmx_check_io_bitmaps(vcpu, port, size);
7317 
7318 	/* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7319 	return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
7320 }
7321 
7322 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7323 			       struct x86_instruction_info *info,
7324 			       enum x86_intercept_stage stage,
7325 			       struct x86_exception *exception)
7326 {
7327 	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7328 
7329 	switch (info->intercept) {
7330 	/*
7331 	 * RDPID causes #UD if disabled through secondary execution controls.
7332 	 * Because it is marked as EmulateOnUD, we need to intercept it here.
7333 	 */
7334 	case x86_intercept_rdtscp:
7335 		if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_RDTSCP)) {
7336 			exception->vector = UD_VECTOR;
7337 			exception->error_code_valid = false;
7338 			return X86EMUL_PROPAGATE_FAULT;
7339 		}
7340 		break;
7341 
7342 	case x86_intercept_in:
7343 	case x86_intercept_ins:
7344 	case x86_intercept_out:
7345 	case x86_intercept_outs:
7346 		return vmx_check_intercept_io(vcpu, info);
7347 
7348 	case x86_intercept_lgdt:
7349 	case x86_intercept_lidt:
7350 	case x86_intercept_lldt:
7351 	case x86_intercept_ltr:
7352 	case x86_intercept_sgdt:
7353 	case x86_intercept_sidt:
7354 	case x86_intercept_sldt:
7355 	case x86_intercept_str:
7356 		if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC))
7357 			return X86EMUL_CONTINUE;
7358 
7359 		/* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED.  */
7360 		break;
7361 
7362 	/* TODO: check more intercepts... */
7363 	default:
7364 		break;
7365 	}
7366 
7367 	return X86EMUL_UNHANDLEABLE;
7368 }
7369 
7370 #ifdef CONFIG_X86_64
7371 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7372 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
7373 				  u64 divisor, u64 *result)
7374 {
7375 	u64 low = a << shift, high = a >> (64 - shift);
7376 
7377 	/* To avoid the overflow on divq */
7378 	if (high >= divisor)
7379 		return 1;
7380 
7381 	/* Low hold the result, high hold rem which is discarded */
7382 	asm("divq %2\n\t" : "=a" (low), "=d" (high) :
7383 	    "rm" (divisor), "0" (low), "1" (high));
7384 	*result = low;
7385 
7386 	return 0;
7387 }
7388 
7389 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
7390 			    bool *expired)
7391 {
7392 	struct vcpu_vmx *vmx;
7393 	u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
7394 	struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;
7395 
7396 	vmx = to_vmx(vcpu);
7397 	tscl = rdtsc();
7398 	guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
7399 	delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
7400 	lapic_timer_advance_cycles = nsec_to_cycles(vcpu,
7401 						    ktimer->timer_advance_ns);
7402 
7403 	if (delta_tsc > lapic_timer_advance_cycles)
7404 		delta_tsc -= lapic_timer_advance_cycles;
7405 	else
7406 		delta_tsc = 0;
7407 
7408 	/* Convert to host delta tsc if tsc scaling is enabled */
7409 	if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
7410 	    delta_tsc && u64_shl_div_u64(delta_tsc,
7411 				kvm_tsc_scaling_ratio_frac_bits,
7412 				vcpu->arch.tsc_scaling_ratio, &delta_tsc))
7413 		return -ERANGE;
7414 
7415 	/*
7416 	 * If the delta tsc can't fit in the 32 bit after the multi shift,
7417 	 * we can't use the preemption timer.
7418 	 * It's possible that it fits on later vmentries, but checking
7419 	 * on every vmentry is costly so we just use an hrtimer.
7420 	 */
7421 	if (delta_tsc >> (cpu_preemption_timer_multi + 32))
7422 		return -ERANGE;
7423 
7424 	vmx->hv_deadline_tsc = tscl + delta_tsc;
7425 	*expired = !delta_tsc;
7426 	return 0;
7427 }
7428 
7429 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
7430 {
7431 	to_vmx(vcpu)->hv_deadline_tsc = -1;
7432 }
7433 #endif
7434 
7435 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
7436 {
7437 	if (!kvm_pause_in_guest(vcpu->kvm))
7438 		shrink_ple_window(vcpu);
7439 }
7440 
7441 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
7442 				     struct kvm_memory_slot *slot)
7443 {
7444 	if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
7445 		kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
7446 	kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
7447 }
7448 
7449 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
7450 				       struct kvm_memory_slot *slot)
7451 {
7452 	kvm_mmu_slot_set_dirty(kvm, slot);
7453 }
7454 
7455 static void vmx_flush_log_dirty(struct kvm *kvm)
7456 {
7457 	kvm_flush_pml_buffers(kvm);
7458 }
7459 
7460 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
7461 					   struct kvm_memory_slot *memslot,
7462 					   gfn_t offset, unsigned long mask)
7463 {
7464 	kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
7465 }
7466 
7467 static int vmx_pre_block(struct kvm_vcpu *vcpu)
7468 {
7469 	if (pi_pre_block(vcpu))
7470 		return 1;
7471 
7472 	if (kvm_lapic_hv_timer_in_use(vcpu))
7473 		kvm_lapic_switch_to_sw_timer(vcpu);
7474 
7475 	return 0;
7476 }
7477 
7478 static void vmx_post_block(struct kvm_vcpu *vcpu)
7479 {
7480 	if (kvm_x86_ops.set_hv_timer)
7481 		kvm_lapic_switch_to_hv_timer(vcpu);
7482 
7483 	pi_post_block(vcpu);
7484 }
7485 
7486 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7487 {
7488 	if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7489 		to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7490 			FEAT_CTL_LMCE_ENABLED;
7491 	else
7492 		to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7493 			~FEAT_CTL_LMCE_ENABLED;
7494 }
7495 
7496 static int vmx_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
7497 {
7498 	/* we need a nested vmexit to enter SMM, postpone if run is pending */
7499 	if (to_vmx(vcpu)->nested.nested_run_pending)
7500 		return -EBUSY;
7501 	return !is_smm(vcpu);
7502 }
7503 
7504 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7505 {
7506 	struct vcpu_vmx *vmx = to_vmx(vcpu);
7507 
7508 	vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7509 	if (vmx->nested.smm.guest_mode)
7510 		nested_vmx_vmexit(vcpu, -1, 0, 0);
7511 
7512 	vmx->nested.smm.vmxon = vmx->nested.vmxon;
7513 	vmx->nested.vmxon = false;
7514 	vmx_clear_hlt(vcpu);
7515 	return 0;
7516 }
7517 
7518 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
7519 {
7520 	struct vcpu_vmx *vmx = to_vmx(vcpu);
7521 	int ret;
7522 
7523 	if (vmx->nested.smm.vmxon) {
7524 		vmx->nested.vmxon = true;
7525 		vmx->nested.smm.vmxon = false;
7526 	}
7527 
7528 	if (vmx->nested.smm.guest_mode) {
7529 		ret = nested_vmx_enter_non_root_mode(vcpu, false);
7530 		if (ret)
7531 			return ret;
7532 
7533 		vmx->nested.smm.guest_mode = false;
7534 	}
7535 	return 0;
7536 }
7537 
7538 static void enable_smi_window(struct kvm_vcpu *vcpu)
7539 {
7540 	/* RSM will cause a vmexit anyway.  */
7541 }
7542 
7543 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
7544 {
7545 	return to_vmx(vcpu)->nested.vmxon && !is_guest_mode(vcpu);
7546 }
7547 
7548 static void vmx_migrate_timers(struct kvm_vcpu *vcpu)
7549 {
7550 	if (is_guest_mode(vcpu)) {
7551 		struct hrtimer *timer = &to_vmx(vcpu)->nested.preemption_timer;
7552 
7553 		if (hrtimer_try_to_cancel(timer) == 1)
7554 			hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
7555 	}
7556 }
7557 
7558 static void hardware_unsetup(void)
7559 {
7560 	if (nested)
7561 		nested_vmx_hardware_unsetup();
7562 
7563 	free_kvm_area();
7564 }
7565 
7566 static bool vmx_check_apicv_inhibit_reasons(ulong bit)
7567 {
7568 	ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
7569 			  BIT(APICV_INHIBIT_REASON_HYPERV);
7570 
7571 	return supported & BIT(bit);
7572 }
7573 
7574 static int vmx_cpu_dirty_log_size(void)
7575 {
7576 	return enable_pml ? PML_ENTITY_NUM : 0;
7577 }
7578 
7579 static struct kvm_x86_ops vmx_x86_ops __initdata = {
7580 	.hardware_unsetup = hardware_unsetup,
7581 
7582 	.hardware_enable = hardware_enable,
7583 	.hardware_disable = hardware_disable,
7584 	.cpu_has_accelerated_tpr = report_flexpriority,
7585 	.has_emulated_msr = vmx_has_emulated_msr,
7586 
7587 	.vm_size = sizeof(struct kvm_vmx),
7588 	.vm_init = vmx_vm_init,
7589 
7590 	.vcpu_create = vmx_create_vcpu,
7591 	.vcpu_free = vmx_free_vcpu,
7592 	.vcpu_reset = vmx_vcpu_reset,
7593 
7594 	.prepare_guest_switch = vmx_prepare_switch_to_guest,
7595 	.vcpu_load = vmx_vcpu_load,
7596 	.vcpu_put = vmx_vcpu_put,
7597 
7598 	.update_exception_bitmap = update_exception_bitmap,
7599 	.get_msr_feature = vmx_get_msr_feature,
7600 	.get_msr = vmx_get_msr,
7601 	.set_msr = vmx_set_msr,
7602 	.get_segment_base = vmx_get_segment_base,
7603 	.get_segment = vmx_get_segment,
7604 	.set_segment = vmx_set_segment,
7605 	.get_cpl = vmx_get_cpl,
7606 	.get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7607 	.set_cr0 = vmx_set_cr0,
7608 	.is_valid_cr4 = vmx_is_valid_cr4,
7609 	.set_cr4 = vmx_set_cr4,
7610 	.set_efer = vmx_set_efer,
7611 	.get_idt = vmx_get_idt,
7612 	.set_idt = vmx_set_idt,
7613 	.get_gdt = vmx_get_gdt,
7614 	.set_gdt = vmx_set_gdt,
7615 	.set_dr7 = vmx_set_dr7,
7616 	.sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
7617 	.cache_reg = vmx_cache_reg,
7618 	.get_rflags = vmx_get_rflags,
7619 	.set_rflags = vmx_set_rflags,
7620 
7621 	.tlb_flush_all = vmx_flush_tlb_all,
7622 	.tlb_flush_current = vmx_flush_tlb_current,
7623 	.tlb_flush_gva = vmx_flush_tlb_gva,
7624 	.tlb_flush_guest = vmx_flush_tlb_guest,
7625 
7626 	.run = vmx_vcpu_run,
7627 	.handle_exit = vmx_handle_exit,
7628 	.skip_emulated_instruction = vmx_skip_emulated_instruction,
7629 	.update_emulated_instruction = vmx_update_emulated_instruction,
7630 	.set_interrupt_shadow = vmx_set_interrupt_shadow,
7631 	.get_interrupt_shadow = vmx_get_interrupt_shadow,
7632 	.patch_hypercall = vmx_patch_hypercall,
7633 	.set_irq = vmx_inject_irq,
7634 	.set_nmi = vmx_inject_nmi,
7635 	.queue_exception = vmx_queue_exception,
7636 	.cancel_injection = vmx_cancel_injection,
7637 	.interrupt_allowed = vmx_interrupt_allowed,
7638 	.nmi_allowed = vmx_nmi_allowed,
7639 	.get_nmi_mask = vmx_get_nmi_mask,
7640 	.set_nmi_mask = vmx_set_nmi_mask,
7641 	.enable_nmi_window = enable_nmi_window,
7642 	.enable_irq_window = enable_irq_window,
7643 	.update_cr8_intercept = update_cr8_intercept,
7644 	.set_virtual_apic_mode = vmx_set_virtual_apic_mode,
7645 	.set_apic_access_page_addr = vmx_set_apic_access_page_addr,
7646 	.refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
7647 	.load_eoi_exitmap = vmx_load_eoi_exitmap,
7648 	.apicv_post_state_restore = vmx_apicv_post_state_restore,
7649 	.check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons,
7650 	.hwapic_irr_update = vmx_hwapic_irr_update,
7651 	.hwapic_isr_update = vmx_hwapic_isr_update,
7652 	.guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
7653 	.sync_pir_to_irr = vmx_sync_pir_to_irr,
7654 	.deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7655 	.dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
7656 
7657 	.set_tss_addr = vmx_set_tss_addr,
7658 	.set_identity_map_addr = vmx_set_identity_map_addr,
7659 	.get_mt_mask = vmx_get_mt_mask,
7660 
7661 	.get_exit_info = vmx_get_exit_info,
7662 
7663 	.vcpu_after_set_cpuid = vmx_vcpu_after_set_cpuid,
7664 
7665 	.has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7666 
7667 	.write_l1_tsc_offset = vmx_write_l1_tsc_offset,
7668 
7669 	.load_mmu_pgd = vmx_load_mmu_pgd,
7670 
7671 	.check_intercept = vmx_check_intercept,
7672 	.handle_exit_irqoff = vmx_handle_exit_irqoff,
7673 
7674 	.request_immediate_exit = vmx_request_immediate_exit,
7675 
7676 	.sched_in = vmx_sched_in,
7677 
7678 	.slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7679 	.slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7680 	.flush_log_dirty = vmx_flush_log_dirty,
7681 	.enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
7682 
7683 	.pre_block = vmx_pre_block,
7684 	.post_block = vmx_post_block,
7685 
7686 	.pmu_ops = &intel_pmu_ops,
7687 	.nested_ops = &vmx_nested_ops,
7688 
7689 	.update_pi_irte = pi_update_irte,
7690 
7691 #ifdef CONFIG_X86_64
7692 	.set_hv_timer = vmx_set_hv_timer,
7693 	.cancel_hv_timer = vmx_cancel_hv_timer,
7694 #endif
7695 
7696 	.setup_mce = vmx_setup_mce,
7697 
7698 	.smi_allowed = vmx_smi_allowed,
7699 	.pre_enter_smm = vmx_pre_enter_smm,
7700 	.pre_leave_smm = vmx_pre_leave_smm,
7701 	.enable_smi_window = enable_smi_window,
7702 
7703 	.can_emulate_instruction = vmx_can_emulate_instruction,
7704 	.apic_init_signal_blocked = vmx_apic_init_signal_blocked,
7705 	.migrate_timers = vmx_migrate_timers,
7706 
7707 	.msr_filter_changed = vmx_msr_filter_changed,
7708 	.complete_emulated_msr = kvm_complete_insn_gp,
7709 	.cpu_dirty_log_size = vmx_cpu_dirty_log_size,
7710 };
7711 
7712 static __init int hardware_setup(void)
7713 {
7714 	unsigned long host_bndcfgs;
7715 	struct desc_ptr dt;
7716 	int r, i, ept_lpage_level;
7717 
7718 	store_idt(&dt);
7719 	host_idt_base = dt.address;
7720 
7721 	for (i = 0; i < ARRAY_SIZE(vmx_uret_msrs_list); ++i)
7722 		kvm_define_user_return_msr(i, vmx_uret_msrs_list[i]);
7723 
7724 	if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7725 		return -EIO;
7726 
7727 	if (boot_cpu_has(X86_FEATURE_NX))
7728 		kvm_enable_efer_bits(EFER_NX);
7729 
7730 	if (boot_cpu_has(X86_FEATURE_MPX)) {
7731 		rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7732 		WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7733 	}
7734 
7735 	if (!cpu_has_vmx_mpx())
7736 		supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
7737 				    XFEATURE_MASK_BNDCSR);
7738 
7739 	if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7740 	    !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7741 		enable_vpid = 0;
7742 
7743 	if (!cpu_has_vmx_ept() ||
7744 	    !cpu_has_vmx_ept_4levels() ||
7745 	    !cpu_has_vmx_ept_mt_wb() ||
7746 	    !cpu_has_vmx_invept_global())
7747 		enable_ept = 0;
7748 
7749 	if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7750 		enable_ept_ad_bits = 0;
7751 
7752 	if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7753 		enable_unrestricted_guest = 0;
7754 
7755 	if (!cpu_has_vmx_flexpriority())
7756 		flexpriority_enabled = 0;
7757 
7758 	if (!cpu_has_virtual_nmis())
7759 		enable_vnmi = 0;
7760 
7761 	/*
7762 	 * set_apic_access_page_addr() is used to reload apic access
7763 	 * page upon invalidation.  No need to do anything if not
7764 	 * using the APIC_ACCESS_ADDR VMCS field.
7765 	 */
7766 	if (!flexpriority_enabled)
7767 		vmx_x86_ops.set_apic_access_page_addr = NULL;
7768 
7769 	if (!cpu_has_vmx_tpr_shadow())
7770 		vmx_x86_ops.update_cr8_intercept = NULL;
7771 
7772 #if IS_ENABLED(CONFIG_HYPERV)
7773 	if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7774 	    && enable_ept) {
7775 		vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb;
7776 		vmx_x86_ops.tlb_remote_flush_with_range =
7777 				hv_remote_flush_tlb_with_range;
7778 	}
7779 #endif
7780 
7781 	if (!cpu_has_vmx_ple()) {
7782 		ple_gap = 0;
7783 		ple_window = 0;
7784 		ple_window_grow = 0;
7785 		ple_window_max = 0;
7786 		ple_window_shrink = 0;
7787 	}
7788 
7789 	if (!cpu_has_vmx_apicv()) {
7790 		enable_apicv = 0;
7791 		vmx_x86_ops.sync_pir_to_irr = NULL;
7792 	}
7793 
7794 	if (cpu_has_vmx_tsc_scaling()) {
7795 		kvm_has_tsc_control = true;
7796 		kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7797 		kvm_tsc_scaling_ratio_frac_bits = 48;
7798 	}
7799 
7800 	set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7801 
7802 	if (enable_ept)
7803 		vmx_enable_tdp();
7804 
7805 	if (!enable_ept)
7806 		ept_lpage_level = 0;
7807 	else if (cpu_has_vmx_ept_1g_page())
7808 		ept_lpage_level = PG_LEVEL_1G;
7809 	else if (cpu_has_vmx_ept_2m_page())
7810 		ept_lpage_level = PG_LEVEL_2M;
7811 	else
7812 		ept_lpage_level = PG_LEVEL_4K;
7813 	kvm_configure_mmu(enable_ept, vmx_get_max_tdp_level(), ept_lpage_level);
7814 
7815 	/*
7816 	 * Only enable PML when hardware supports PML feature, and both EPT
7817 	 * and EPT A/D bit features are enabled -- PML depends on them to work.
7818 	 */
7819 	if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7820 		enable_pml = 0;
7821 
7822 	if (!enable_pml) {
7823 		vmx_x86_ops.slot_enable_log_dirty = NULL;
7824 		vmx_x86_ops.slot_disable_log_dirty = NULL;
7825 		vmx_x86_ops.flush_log_dirty = NULL;
7826 		vmx_x86_ops.enable_log_dirty_pt_masked = NULL;
7827 		vmx_x86_ops.cpu_dirty_log_size = NULL;
7828 	}
7829 
7830 	if (!cpu_has_vmx_preemption_timer())
7831 		enable_preemption_timer = false;
7832 
7833 	if (enable_preemption_timer) {
7834 		u64 use_timer_freq = 5000ULL * 1000 * 1000;
7835 		u64 vmx_msr;
7836 
7837 		rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7838 		cpu_preemption_timer_multi =
7839 			vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7840 
7841 		if (tsc_khz)
7842 			use_timer_freq = (u64)tsc_khz * 1000;
7843 		use_timer_freq >>= cpu_preemption_timer_multi;
7844 
7845 		/*
7846 		 * KVM "disables" the preemption timer by setting it to its max
7847 		 * value.  Don't use the timer if it might cause spurious exits
7848 		 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7849 		 */
7850 		if (use_timer_freq > 0xffffffffu / 10)
7851 			enable_preemption_timer = false;
7852 	}
7853 
7854 	if (!enable_preemption_timer) {
7855 		vmx_x86_ops.set_hv_timer = NULL;
7856 		vmx_x86_ops.cancel_hv_timer = NULL;
7857 		vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit;
7858 	}
7859 
7860 	kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler);
7861 
7862 	kvm_mce_cap_supported |= MCG_LMCE_P;
7863 
7864 	if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST)
7865 		return -EINVAL;
7866 	if (!enable_ept || !cpu_has_vmx_intel_pt())
7867 		pt_mode = PT_MODE_SYSTEM;
7868 
7869 	if (nested) {
7870 		nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7871 					   vmx_capability.ept);
7872 
7873 		r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
7874 		if (r)
7875 			return r;
7876 	}
7877 
7878 	vmx_set_cpu_caps();
7879 
7880 	r = alloc_kvm_area();
7881 	if (r)
7882 		nested_vmx_hardware_unsetup();
7883 	return r;
7884 }
7885 
7886 static struct kvm_x86_init_ops vmx_init_ops __initdata = {
7887 	.cpu_has_kvm_support = cpu_has_kvm_support,
7888 	.disabled_by_bios = vmx_disabled_by_bios,
7889 	.check_processor_compatibility = vmx_check_processor_compat,
7890 	.hardware_setup = hardware_setup,
7891 
7892 	.runtime_ops = &vmx_x86_ops,
7893 };
7894 
7895 static void vmx_cleanup_l1d_flush(void)
7896 {
7897 	if (vmx_l1d_flush_pages) {
7898 		free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7899 		vmx_l1d_flush_pages = NULL;
7900 	}
7901 	/* Restore state so sysfs ignores VMX */
7902 	l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
7903 }
7904 
7905 static void vmx_exit(void)
7906 {
7907 #ifdef CONFIG_KEXEC_CORE
7908 	RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7909 	synchronize_rcu();
7910 #endif
7911 
7912 	kvm_exit();
7913 
7914 #if IS_ENABLED(CONFIG_HYPERV)
7915 	if (static_branch_unlikely(&enable_evmcs)) {
7916 		int cpu;
7917 		struct hv_vp_assist_page *vp_ap;
7918 		/*
7919 		 * Reset everything to support using non-enlightened VMCS
7920 		 * access later (e.g. when we reload the module with
7921 		 * enlightened_vmcs=0)
7922 		 */
7923 		for_each_online_cpu(cpu) {
7924 			vp_ap =	hv_get_vp_assist_page(cpu);
7925 
7926 			if (!vp_ap)
7927 				continue;
7928 
7929 			vp_ap->nested_control.features.directhypercall = 0;
7930 			vp_ap->current_nested_vmcs = 0;
7931 			vp_ap->enlighten_vmentry = 0;
7932 		}
7933 
7934 		static_branch_disable(&enable_evmcs);
7935 	}
7936 #endif
7937 	vmx_cleanup_l1d_flush();
7938 }
7939 module_exit(vmx_exit);
7940 
7941 static int __init vmx_init(void)
7942 {
7943 	int r, cpu;
7944 
7945 #if IS_ENABLED(CONFIG_HYPERV)
7946 	/*
7947 	 * Enlightened VMCS usage should be recommended and the host needs
7948 	 * to support eVMCS v1 or above. We can also disable eVMCS support
7949 	 * with module parameter.
7950 	 */
7951 	if (enlightened_vmcs &&
7952 	    ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7953 	    (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7954 	    KVM_EVMCS_VERSION) {
7955 		int cpu;
7956 
7957 		/* Check that we have assist pages on all online CPUs */
7958 		for_each_online_cpu(cpu) {
7959 			if (!hv_get_vp_assist_page(cpu)) {
7960 				enlightened_vmcs = false;
7961 				break;
7962 			}
7963 		}
7964 
7965 		if (enlightened_vmcs) {
7966 			pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7967 			static_branch_enable(&enable_evmcs);
7968 		}
7969 
7970 		if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH)
7971 			vmx_x86_ops.enable_direct_tlbflush
7972 				= hv_enable_direct_tlbflush;
7973 
7974 	} else {
7975 		enlightened_vmcs = false;
7976 	}
7977 #endif
7978 
7979 	r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx),
7980 		     __alignof__(struct vcpu_vmx), THIS_MODULE);
7981 	if (r)
7982 		return r;
7983 
7984 	/*
7985 	 * Must be called after kvm_init() so enable_ept is properly set
7986 	 * up. Hand the parameter mitigation value in which was stored in
7987 	 * the pre module init parser. If no parameter was given, it will
7988 	 * contain 'auto' which will be turned into the default 'cond'
7989 	 * mitigation mode.
7990 	 */
7991 	r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7992 	if (r) {
7993 		vmx_exit();
7994 		return r;
7995 	}
7996 
7997 	for_each_possible_cpu(cpu) {
7998 		INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
7999 
8000 		pi_init_cpu(cpu);
8001 	}
8002 
8003 #ifdef CONFIG_KEXEC_CORE
8004 	rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8005 			   crash_vmclear_local_loaded_vmcss);
8006 #endif
8007 	vmx_check_vmcs12_offsets();
8008 
8009 	/*
8010 	 * Shadow paging doesn't have a (further) performance penalty
8011 	 * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8012 	 * by default
8013 	 */
8014 	if (!enable_ept)
8015 		allow_smaller_maxphyaddr = true;
8016 
8017 	return 0;
8018 }
8019 module_init(vmx_init);
8020