1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/debugreg.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/io.h> 38 #include <asm/irq_remapping.h> 39 #include <asm/kexec.h> 40 #include <asm/perf_event.h> 41 #include <asm/mce.h> 42 #include <asm/mmu_context.h> 43 #include <asm/mshyperv.h> 44 #include <asm/spec-ctrl.h> 45 #include <asm/virtext.h> 46 #include <asm/vmx.h> 47 48 #include "capabilities.h" 49 #include "cpuid.h" 50 #include "evmcs.h" 51 #include "irq.h" 52 #include "kvm_cache_regs.h" 53 #include "lapic.h" 54 #include "mmu.h" 55 #include "nested.h" 56 #include "ops.h" 57 #include "pmu.h" 58 #include "trace.h" 59 #include "vmcs.h" 60 #include "vmcs12.h" 61 #include "vmx.h" 62 #include "x86.h" 63 64 MODULE_AUTHOR("Qumranet"); 65 MODULE_LICENSE("GPL"); 66 67 static const struct x86_cpu_id vmx_cpu_id[] = { 68 X86_FEATURE_MATCH(X86_FEATURE_VMX), 69 {} 70 }; 71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 72 73 bool __read_mostly enable_vpid = 1; 74 module_param_named(vpid, enable_vpid, bool, 0444); 75 76 static bool __read_mostly enable_vnmi = 1; 77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 78 79 bool __read_mostly flexpriority_enabled = 1; 80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 81 82 bool __read_mostly enable_ept = 1; 83 module_param_named(ept, enable_ept, bool, S_IRUGO); 84 85 bool __read_mostly enable_unrestricted_guest = 1; 86 module_param_named(unrestricted_guest, 87 enable_unrestricted_guest, bool, S_IRUGO); 88 89 bool __read_mostly enable_ept_ad_bits = 1; 90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 91 92 static bool __read_mostly emulate_invalid_guest_state = true; 93 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 94 95 static bool __read_mostly fasteoi = 1; 96 module_param(fasteoi, bool, S_IRUGO); 97 98 static bool __read_mostly enable_apicv = 1; 99 module_param(enable_apicv, bool, S_IRUGO); 100 101 /* 102 * If nested=1, nested virtualization is supported, i.e., guests may use 103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 104 * use VMX instructions. 105 */ 106 static bool __read_mostly nested = 1; 107 module_param(nested, bool, S_IRUGO); 108 109 bool __read_mostly enable_pml = 1; 110 module_param_named(pml, enable_pml, bool, S_IRUGO); 111 112 static bool __read_mostly dump_invalid_vmcs = 0; 113 module_param(dump_invalid_vmcs, bool, 0644); 114 115 #define MSR_BITMAP_MODE_X2APIC 1 116 #define MSR_BITMAP_MODE_X2APIC_APICV 2 117 118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 119 120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 121 static int __read_mostly cpu_preemption_timer_multi; 122 static bool __read_mostly enable_preemption_timer = 1; 123 #ifdef CONFIG_X86_64 124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 125 #endif 126 127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 129 #define KVM_VM_CR0_ALWAYS_ON \ 130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 132 #define KVM_CR4_GUEST_OWNED_BITS \ 133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 135 136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 139 140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 141 142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 145 RTIT_STATUS_BYTECNT)) 146 147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 149 150 /* 151 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 152 * ple_gap: upper bound on the amount of time between two successive 153 * executions of PAUSE in a loop. Also indicate if ple enabled. 154 * According to test, this time is usually smaller than 128 cycles. 155 * ple_window: upper bound on the amount of time a guest is allowed to execute 156 * in a PAUSE loop. Tests indicate that most spinlocks are held for 157 * less than 2^12 cycles 158 * Time is measured based on a counter that runs at the same rate as the TSC, 159 * refer SDM volume 3b section 21.6.13 & 22.1.3. 160 */ 161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 162 module_param(ple_gap, uint, 0444); 163 164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 165 module_param(ple_window, uint, 0444); 166 167 /* Default doubles per-vcpu window every exit. */ 168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 169 module_param(ple_window_grow, uint, 0444); 170 171 /* Default resets per-vcpu window every exit to ple_window. */ 172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 173 module_param(ple_window_shrink, uint, 0444); 174 175 /* Default is to compute the maximum so we can never overflow. */ 176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 177 module_param(ple_window_max, uint, 0444); 178 179 /* Default is SYSTEM mode, 1 for host-guest mode */ 180 int __read_mostly pt_mode = PT_MODE_SYSTEM; 181 module_param(pt_mode, int, S_IRUGO); 182 183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 185 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 186 187 /* Storage for pre module init parameter parsing */ 188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 189 190 static const struct { 191 const char *option; 192 bool for_parse; 193 } vmentry_l1d_param[] = { 194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 196 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 200 }; 201 202 #define L1D_CACHE_ORDER 4 203 static void *vmx_l1d_flush_pages; 204 205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 206 { 207 struct page *page; 208 unsigned int i; 209 210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 212 return 0; 213 } 214 215 if (!enable_ept) { 216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 217 return 0; 218 } 219 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 221 u64 msr; 222 223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 226 return 0; 227 } 228 } 229 230 /* If set to auto use the default l1tf mitigation method */ 231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 232 switch (l1tf_mitigation) { 233 case L1TF_MITIGATION_OFF: 234 l1tf = VMENTER_L1D_FLUSH_NEVER; 235 break; 236 case L1TF_MITIGATION_FLUSH_NOWARN: 237 case L1TF_MITIGATION_FLUSH: 238 case L1TF_MITIGATION_FLUSH_NOSMT: 239 l1tf = VMENTER_L1D_FLUSH_COND; 240 break; 241 case L1TF_MITIGATION_FULL: 242 case L1TF_MITIGATION_FULL_FORCE: 243 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 244 break; 245 } 246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 } 249 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 252 /* 253 * This allocation for vmx_l1d_flush_pages is not tied to a VM 254 * lifetime and so should not be charged to a memcg. 255 */ 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 257 if (!page) 258 return -ENOMEM; 259 vmx_l1d_flush_pages = page_address(page); 260 261 /* 262 * Initialize each page with a different pattern in 263 * order to protect against KSM in the nested 264 * virtualization case. 265 */ 266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 268 PAGE_SIZE); 269 } 270 } 271 272 l1tf_vmx_mitigation = l1tf; 273 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 275 static_branch_enable(&vmx_l1d_should_flush); 276 else 277 static_branch_disable(&vmx_l1d_should_flush); 278 279 if (l1tf == VMENTER_L1D_FLUSH_COND) 280 static_branch_enable(&vmx_l1d_flush_cond); 281 else 282 static_branch_disable(&vmx_l1d_flush_cond); 283 return 0; 284 } 285 286 static int vmentry_l1d_flush_parse(const char *s) 287 { 288 unsigned int i; 289 290 if (s) { 291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 292 if (vmentry_l1d_param[i].for_parse && 293 sysfs_streq(s, vmentry_l1d_param[i].option)) 294 return i; 295 } 296 } 297 return -EINVAL; 298 } 299 300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 301 { 302 int l1tf, ret; 303 304 l1tf = vmentry_l1d_flush_parse(s); 305 if (l1tf < 0) 306 return l1tf; 307 308 if (!boot_cpu_has(X86_BUG_L1TF)) 309 return 0; 310 311 /* 312 * Has vmx_init() run already? If not then this is the pre init 313 * parameter parsing. In that case just store the value and let 314 * vmx_init() do the proper setup after enable_ept has been 315 * established. 316 */ 317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 318 vmentry_l1d_flush_param = l1tf; 319 return 0; 320 } 321 322 mutex_lock(&vmx_l1d_flush_mutex); 323 ret = vmx_setup_l1d_flush(l1tf); 324 mutex_unlock(&vmx_l1d_flush_mutex); 325 return ret; 326 } 327 328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 329 { 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 331 return sprintf(s, "???\n"); 332 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 334 } 335 336 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 337 .set = vmentry_l1d_flush_set, 338 .get = vmentry_l1d_flush_get, 339 }; 340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 341 342 static bool guest_state_valid(struct kvm_vcpu *vcpu); 343 static u32 vmx_segment_access_rights(struct kvm_segment *var); 344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 345 u32 msr, int type); 346 347 void vmx_vmexit(void); 348 349 #define vmx_insn_failed(fmt...) \ 350 do { \ 351 WARN_ONCE(1, fmt); \ 352 pr_warn_ratelimited(fmt); \ 353 } while (0) 354 355 asmlinkage void vmread_error(unsigned long field, bool fault) 356 { 357 if (fault) 358 kvm_spurious_fault(); 359 else 360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 361 } 362 363 noinline void vmwrite_error(unsigned long field, unsigned long value) 364 { 365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 367 } 368 369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 370 { 371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 372 } 373 374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 375 { 376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 377 } 378 379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 380 { 381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 382 ext, vpid, gva); 383 } 384 385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 386 { 387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 388 ext, eptp, gpa); 389 } 390 391 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 392 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 393 /* 394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 396 */ 397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 398 399 /* 400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 401 * can find which vCPU should be waken up. 402 */ 403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 405 406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 407 static DEFINE_SPINLOCK(vmx_vpid_lock); 408 409 struct vmcs_config vmcs_config; 410 struct vmx_capability vmx_capability; 411 412 #define VMX_SEGMENT_FIELD(seg) \ 413 [VCPU_SREG_##seg] = { \ 414 .selector = GUEST_##seg##_SELECTOR, \ 415 .base = GUEST_##seg##_BASE, \ 416 .limit = GUEST_##seg##_LIMIT, \ 417 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 418 } 419 420 static const struct kvm_vmx_segment_field { 421 unsigned selector; 422 unsigned base; 423 unsigned limit; 424 unsigned ar_bytes; 425 } kvm_vmx_segment_fields[] = { 426 VMX_SEGMENT_FIELD(CS), 427 VMX_SEGMENT_FIELD(DS), 428 VMX_SEGMENT_FIELD(ES), 429 VMX_SEGMENT_FIELD(FS), 430 VMX_SEGMENT_FIELD(GS), 431 VMX_SEGMENT_FIELD(SS), 432 VMX_SEGMENT_FIELD(TR), 433 VMX_SEGMENT_FIELD(LDTR), 434 }; 435 436 u64 host_efer; 437 static unsigned long host_idt_base; 438 439 /* 440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 441 * will emulate SYSCALL in legacy mode if the vendor string in guest 442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 443 * support this emulation, IA32_STAR must always be included in 444 * vmx_msr_index[], even in i386 builds. 445 */ 446 const u32 vmx_msr_index[] = { 447 #ifdef CONFIG_X86_64 448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 449 #endif 450 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 451 MSR_IA32_TSX_CTRL, 452 }; 453 454 #if IS_ENABLED(CONFIG_HYPERV) 455 static bool __read_mostly enlightened_vmcs = true; 456 module_param(enlightened_vmcs, bool, 0444); 457 458 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 459 static void check_ept_pointer_match(struct kvm *kvm) 460 { 461 struct kvm_vcpu *vcpu; 462 u64 tmp_eptp = INVALID_PAGE; 463 int i; 464 465 kvm_for_each_vcpu(i, vcpu, kvm) { 466 if (!VALID_PAGE(tmp_eptp)) { 467 tmp_eptp = to_vmx(vcpu)->ept_pointer; 468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 469 to_kvm_vmx(kvm)->ept_pointers_match 470 = EPT_POINTERS_MISMATCH; 471 return; 472 } 473 } 474 475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 476 } 477 478 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 479 void *data) 480 { 481 struct kvm_tlb_range *range = data; 482 483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 484 range->pages); 485 } 486 487 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 489 { 490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 491 492 /* 493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 494 * of the base of EPT PML4 table, strip off EPT configuration 495 * information. 496 */ 497 if (range) 498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 499 kvm_fill_hv_flush_list_func, (void *)range); 500 else 501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 502 } 503 504 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 505 struct kvm_tlb_range *range) 506 { 507 struct kvm_vcpu *vcpu; 508 int ret = 0, i; 509 510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 511 512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 513 check_ept_pointer_match(kvm); 514 515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 516 kvm_for_each_vcpu(i, vcpu, kvm) { 517 /* If ept_pointer is invalid pointer, bypass flush request. */ 518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 519 ret |= __hv_remote_flush_tlb_with_range( 520 kvm, vcpu, range); 521 } 522 } else { 523 ret = __hv_remote_flush_tlb_with_range(kvm, 524 kvm_get_vcpu(kvm, 0), range); 525 } 526 527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 528 return ret; 529 } 530 static int hv_remote_flush_tlb(struct kvm *kvm) 531 { 532 return hv_remote_flush_tlb_with_range(kvm, NULL); 533 } 534 535 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 536 { 537 struct hv_enlightened_vmcs *evmcs; 538 struct hv_partition_assist_pg **p_hv_pa_pg = 539 &vcpu->kvm->arch.hyperv.hv_pa_pg; 540 /* 541 * Synthetic VM-Exit is not enabled in current code and so All 542 * evmcs in singe VM shares same assist page. 543 */ 544 if (!*p_hv_pa_pg) 545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 546 547 if (!*p_hv_pa_pg) 548 return -ENOMEM; 549 550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 551 552 evmcs->partition_assist_page = 553 __pa(*p_hv_pa_pg); 554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 556 557 return 0; 558 } 559 560 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 561 562 /* 563 * Comment's format: document - errata name - stepping - processor name. 564 * Refer from 565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 566 */ 567 static u32 vmx_preemption_cpu_tfms[] = { 568 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 569 0x000206E6, 570 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 571 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 572 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 573 0x00020652, 574 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 575 0x00020655, 576 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 577 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 578 /* 579 * 320767.pdf - AAP86 - B1 - 580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 581 */ 582 0x000106E5, 583 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 584 0x000106A0, 585 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 586 0x000106A1, 587 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 588 0x000106A4, 589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 592 0x000106A5, 593 /* Xeon E3-1220 V2 */ 594 0x000306A8, 595 }; 596 597 static inline bool cpu_has_broken_vmx_preemption_timer(void) 598 { 599 u32 eax = cpuid_eax(0x00000001), i; 600 601 /* Clear the reserved bits */ 602 eax &= ~(0x3U << 14 | 0xfU << 28); 603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 604 if (eax == vmx_preemption_cpu_tfms[i]) 605 return true; 606 607 return false; 608 } 609 610 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 611 { 612 return flexpriority_enabled && lapic_in_kernel(vcpu); 613 } 614 615 static inline bool report_flexpriority(void) 616 { 617 return flexpriority_enabled; 618 } 619 620 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 621 { 622 int i; 623 624 for (i = 0; i < vmx->nmsrs; ++i) 625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 626 return i; 627 return -1; 628 } 629 630 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 631 { 632 int i; 633 634 i = __find_msr_index(vmx, msr); 635 if (i >= 0) 636 return &vmx->guest_msrs[i]; 637 return NULL; 638 } 639 640 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 641 { 642 int ret = 0; 643 644 u64 old_msr_data = msr->data; 645 msr->data = data; 646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 647 preempt_disable(); 648 ret = kvm_set_shared_msr(msr->index, msr->data, 649 msr->mask); 650 preempt_enable(); 651 if (ret) 652 msr->data = old_msr_data; 653 } 654 return ret; 655 } 656 657 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 658 { 659 vmcs_clear(loaded_vmcs->vmcs); 660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 661 vmcs_clear(loaded_vmcs->shadow_vmcs); 662 loaded_vmcs->cpu = -1; 663 loaded_vmcs->launched = 0; 664 } 665 666 #ifdef CONFIG_KEXEC_CORE 667 /* 668 * This bitmap is used to indicate whether the vmclear 669 * operation is enabled on all cpus. All disabled by 670 * default. 671 */ 672 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 673 674 static inline void crash_enable_local_vmclear(int cpu) 675 { 676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 677 } 678 679 static inline void crash_disable_local_vmclear(int cpu) 680 { 681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 682 } 683 684 static inline int crash_local_vmclear_enabled(int cpu) 685 { 686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 687 } 688 689 static void crash_vmclear_local_loaded_vmcss(void) 690 { 691 int cpu = raw_smp_processor_id(); 692 struct loaded_vmcs *v; 693 694 if (!crash_local_vmclear_enabled(cpu)) 695 return; 696 697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 698 loaded_vmcss_on_cpu_link) 699 vmcs_clear(v->vmcs); 700 } 701 #else 702 static inline void crash_enable_local_vmclear(int cpu) { } 703 static inline void crash_disable_local_vmclear(int cpu) { } 704 #endif /* CONFIG_KEXEC_CORE */ 705 706 static void __loaded_vmcs_clear(void *arg) 707 { 708 struct loaded_vmcs *loaded_vmcs = arg; 709 int cpu = raw_smp_processor_id(); 710 711 if (loaded_vmcs->cpu != cpu) 712 return; /* vcpu migration can race with cpu offline */ 713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 714 per_cpu(current_vmcs, cpu) = NULL; 715 crash_disable_local_vmclear(cpu); 716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 717 718 /* 719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 720 * is before setting loaded_vmcs->vcpu to -1 which is done in 721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 722 * then adds the vmcs into percpu list before it is deleted. 723 */ 724 smp_wmb(); 725 726 loaded_vmcs_init(loaded_vmcs); 727 crash_enable_local_vmclear(cpu); 728 } 729 730 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 731 { 732 int cpu = loaded_vmcs->cpu; 733 734 if (cpu != -1) 735 smp_call_function_single(cpu, 736 __loaded_vmcs_clear, loaded_vmcs, 1); 737 } 738 739 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 740 unsigned field) 741 { 742 bool ret; 743 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 744 745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 747 vmx->segment_cache.bitmask = 0; 748 } 749 ret = vmx->segment_cache.bitmask & mask; 750 vmx->segment_cache.bitmask |= mask; 751 return ret; 752 } 753 754 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 755 { 756 u16 *p = &vmx->segment_cache.seg[seg].selector; 757 758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 760 return *p; 761 } 762 763 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 764 { 765 ulong *p = &vmx->segment_cache.seg[seg].base; 766 767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 769 return *p; 770 } 771 772 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 773 { 774 u32 *p = &vmx->segment_cache.seg[seg].limit; 775 776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 778 return *p; 779 } 780 781 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 782 { 783 u32 *p = &vmx->segment_cache.seg[seg].ar; 784 785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 787 return *p; 788 } 789 790 void update_exception_bitmap(struct kvm_vcpu *vcpu) 791 { 792 u32 eb; 793 794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 795 (1u << DB_VECTOR) | (1u << AC_VECTOR); 796 /* 797 * Guest access to VMware backdoor ports could legitimately 798 * trigger #GP because of TSS I/O permission bitmap. 799 * We intercept those #GP and allow access to them anyway 800 * as VMware does. 801 */ 802 if (enable_vmware_backdoor) 803 eb |= (1u << GP_VECTOR); 804 if ((vcpu->guest_debug & 805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 807 eb |= 1u << BP_VECTOR; 808 if (to_vmx(vcpu)->rmode.vm86_active) 809 eb = ~0; 810 if (enable_ept) 811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 812 813 /* When we are running a nested L2 guest and L1 specified for it a 814 * certain exception bitmap, we must trap the same exceptions and pass 815 * them to L1. When running L2, we will only handle the exceptions 816 * specified above if L1 did not want them. 817 */ 818 if (is_guest_mode(vcpu)) 819 eb |= get_vmcs12(vcpu)->exception_bitmap; 820 821 vmcs_write32(EXCEPTION_BITMAP, eb); 822 } 823 824 /* 825 * Check if MSR is intercepted for currently loaded MSR bitmap. 826 */ 827 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 828 { 829 unsigned long *msr_bitmap; 830 int f = sizeof(unsigned long); 831 832 if (!cpu_has_vmx_msr_bitmap()) 833 return true; 834 835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 836 837 if (msr <= 0x1fff) { 838 return !!test_bit(msr, msr_bitmap + 0x800 / f); 839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 840 msr &= 0x1fff; 841 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 842 } 843 844 return true; 845 } 846 847 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 848 unsigned long entry, unsigned long exit) 849 { 850 vm_entry_controls_clearbit(vmx, entry); 851 vm_exit_controls_clearbit(vmx, exit); 852 } 853 854 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 855 { 856 unsigned int i; 857 858 for (i = 0; i < m->nr; ++i) { 859 if (m->val[i].index == msr) 860 return i; 861 } 862 return -ENOENT; 863 } 864 865 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 866 { 867 int i; 868 struct msr_autoload *m = &vmx->msr_autoload; 869 870 switch (msr) { 871 case MSR_EFER: 872 if (cpu_has_load_ia32_efer()) { 873 clear_atomic_switch_msr_special(vmx, 874 VM_ENTRY_LOAD_IA32_EFER, 875 VM_EXIT_LOAD_IA32_EFER); 876 return; 877 } 878 break; 879 case MSR_CORE_PERF_GLOBAL_CTRL: 880 if (cpu_has_load_perf_global_ctrl()) { 881 clear_atomic_switch_msr_special(vmx, 882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 884 return; 885 } 886 break; 887 } 888 i = vmx_find_msr_index(&m->guest, msr); 889 if (i < 0) 890 goto skip_guest; 891 --m->guest.nr; 892 m->guest.val[i] = m->guest.val[m->guest.nr]; 893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 894 895 skip_guest: 896 i = vmx_find_msr_index(&m->host, msr); 897 if (i < 0) 898 return; 899 900 --m->host.nr; 901 m->host.val[i] = m->host.val[m->host.nr]; 902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 903 } 904 905 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 906 unsigned long entry, unsigned long exit, 907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 908 u64 guest_val, u64 host_val) 909 { 910 vmcs_write64(guest_val_vmcs, guest_val); 911 if (host_val_vmcs != HOST_IA32_EFER) 912 vmcs_write64(host_val_vmcs, host_val); 913 vm_entry_controls_setbit(vmx, entry); 914 vm_exit_controls_setbit(vmx, exit); 915 } 916 917 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 918 u64 guest_val, u64 host_val, bool entry_only) 919 { 920 int i, j = 0; 921 struct msr_autoload *m = &vmx->msr_autoload; 922 923 switch (msr) { 924 case MSR_EFER: 925 if (cpu_has_load_ia32_efer()) { 926 add_atomic_switch_msr_special(vmx, 927 VM_ENTRY_LOAD_IA32_EFER, 928 VM_EXIT_LOAD_IA32_EFER, 929 GUEST_IA32_EFER, 930 HOST_IA32_EFER, 931 guest_val, host_val); 932 return; 933 } 934 break; 935 case MSR_CORE_PERF_GLOBAL_CTRL: 936 if (cpu_has_load_perf_global_ctrl()) { 937 add_atomic_switch_msr_special(vmx, 938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 940 GUEST_IA32_PERF_GLOBAL_CTRL, 941 HOST_IA32_PERF_GLOBAL_CTRL, 942 guest_val, host_val); 943 return; 944 } 945 break; 946 case MSR_IA32_PEBS_ENABLE: 947 /* PEBS needs a quiescent period after being disabled (to write 948 * a record). Disabling PEBS through VMX MSR swapping doesn't 949 * provide that period, so a CPU could write host's record into 950 * guest's memory. 951 */ 952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 953 } 954 955 i = vmx_find_msr_index(&m->guest, msr); 956 if (!entry_only) 957 j = vmx_find_msr_index(&m->host, msr); 958 959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 961 printk_once(KERN_WARNING "Not enough msr switch entries. " 962 "Can't add msr %x\n", msr); 963 return; 964 } 965 if (i < 0) { 966 i = m->guest.nr++; 967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 968 } 969 m->guest.val[i].index = msr; 970 m->guest.val[i].value = guest_val; 971 972 if (entry_only) 973 return; 974 975 if (j < 0) { 976 j = m->host.nr++; 977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 978 } 979 m->host.val[j].index = msr; 980 m->host.val[j].value = host_val; 981 } 982 983 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 984 { 985 u64 guest_efer = vmx->vcpu.arch.efer; 986 u64 ignore_bits = 0; 987 988 /* Shadow paging assumes NX to be available. */ 989 if (!enable_ept) 990 guest_efer |= EFER_NX; 991 992 /* 993 * LMA and LME handled by hardware; SCE meaningless outside long mode. 994 */ 995 ignore_bits |= EFER_SCE; 996 #ifdef CONFIG_X86_64 997 ignore_bits |= EFER_LMA | EFER_LME; 998 /* SCE is meaningful only in long mode on Intel */ 999 if (guest_efer & EFER_LMA) 1000 ignore_bits &= ~(u64)EFER_SCE; 1001 #endif 1002 1003 /* 1004 * On EPT, we can't emulate NX, so we must switch EFER atomically. 1005 * On CPUs that support "load IA32_EFER", always switch EFER 1006 * atomically, since it's faster than switching it manually. 1007 */ 1008 if (cpu_has_load_ia32_efer() || 1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 1010 if (!(guest_efer & EFER_LMA)) 1011 guest_efer &= ~EFER_LME; 1012 if (guest_efer != host_efer) 1013 add_atomic_switch_msr(vmx, MSR_EFER, 1014 guest_efer, host_efer, false); 1015 else 1016 clear_atomic_switch_msr(vmx, MSR_EFER); 1017 return false; 1018 } else { 1019 clear_atomic_switch_msr(vmx, MSR_EFER); 1020 1021 guest_efer &= ~ignore_bits; 1022 guest_efer |= host_efer & ignore_bits; 1023 1024 vmx->guest_msrs[efer_offset].data = guest_efer; 1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1026 1027 return true; 1028 } 1029 } 1030 1031 #ifdef CONFIG_X86_32 1032 /* 1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1034 * VMCS rather than the segment table. KVM uses this helper to figure 1035 * out the current bases to poke them into the VMCS before entry. 1036 */ 1037 static unsigned long segment_base(u16 selector) 1038 { 1039 struct desc_struct *table; 1040 unsigned long v; 1041 1042 if (!(selector & ~SEGMENT_RPL_MASK)) 1043 return 0; 1044 1045 table = get_current_gdt_ro(); 1046 1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1048 u16 ldt_selector = kvm_read_ldt(); 1049 1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1051 return 0; 1052 1053 table = (struct desc_struct *)segment_base(ldt_selector); 1054 } 1055 v = get_desc_base(&table[selector >> 3]); 1056 return v; 1057 } 1058 #endif 1059 1060 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1061 { 1062 u32 i; 1063 1064 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1065 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1066 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1067 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1068 for (i = 0; i < addr_range; i++) { 1069 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1070 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1071 } 1072 } 1073 1074 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1075 { 1076 u32 i; 1077 1078 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1079 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1080 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1081 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1082 for (i = 0; i < addr_range; i++) { 1083 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1084 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1085 } 1086 } 1087 1088 static void pt_guest_enter(struct vcpu_vmx *vmx) 1089 { 1090 if (pt_mode == PT_MODE_SYSTEM) 1091 return; 1092 1093 /* 1094 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1095 * Save host state before VM entry. 1096 */ 1097 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1098 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1099 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1100 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1101 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1102 } 1103 } 1104 1105 static void pt_guest_exit(struct vcpu_vmx *vmx) 1106 { 1107 if (pt_mode == PT_MODE_SYSTEM) 1108 return; 1109 1110 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1111 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1112 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1113 } 1114 1115 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1116 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1117 } 1118 1119 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1120 unsigned long fs_base, unsigned long gs_base) 1121 { 1122 if (unlikely(fs_sel != host->fs_sel)) { 1123 if (!(fs_sel & 7)) 1124 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1125 else 1126 vmcs_write16(HOST_FS_SELECTOR, 0); 1127 host->fs_sel = fs_sel; 1128 } 1129 if (unlikely(gs_sel != host->gs_sel)) { 1130 if (!(gs_sel & 7)) 1131 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1132 else 1133 vmcs_write16(HOST_GS_SELECTOR, 0); 1134 host->gs_sel = gs_sel; 1135 } 1136 if (unlikely(fs_base != host->fs_base)) { 1137 vmcs_writel(HOST_FS_BASE, fs_base); 1138 host->fs_base = fs_base; 1139 } 1140 if (unlikely(gs_base != host->gs_base)) { 1141 vmcs_writel(HOST_GS_BASE, gs_base); 1142 host->gs_base = gs_base; 1143 } 1144 } 1145 1146 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1147 { 1148 struct vcpu_vmx *vmx = to_vmx(vcpu); 1149 struct vmcs_host_state *host_state; 1150 #ifdef CONFIG_X86_64 1151 int cpu = raw_smp_processor_id(); 1152 #endif 1153 unsigned long fs_base, gs_base; 1154 u16 fs_sel, gs_sel; 1155 int i; 1156 1157 vmx->req_immediate_exit = false; 1158 1159 /* 1160 * Note that guest MSRs to be saved/restored can also be changed 1161 * when guest state is loaded. This happens when guest transitions 1162 * to/from long-mode by setting MSR_EFER.LMA. 1163 */ 1164 if (!vmx->guest_msrs_ready) { 1165 vmx->guest_msrs_ready = true; 1166 for (i = 0; i < vmx->save_nmsrs; ++i) 1167 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1168 vmx->guest_msrs[i].data, 1169 vmx->guest_msrs[i].mask); 1170 1171 } 1172 if (vmx->guest_state_loaded) 1173 return; 1174 1175 host_state = &vmx->loaded_vmcs->host_state; 1176 1177 /* 1178 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1179 * allow segment selectors with cpl > 0 or ti == 1. 1180 */ 1181 host_state->ldt_sel = kvm_read_ldt(); 1182 1183 #ifdef CONFIG_X86_64 1184 savesegment(ds, host_state->ds_sel); 1185 savesegment(es, host_state->es_sel); 1186 1187 gs_base = cpu_kernelmode_gs_base(cpu); 1188 if (likely(is_64bit_mm(current->mm))) { 1189 save_fsgs_for_kvm(); 1190 fs_sel = current->thread.fsindex; 1191 gs_sel = current->thread.gsindex; 1192 fs_base = current->thread.fsbase; 1193 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1194 } else { 1195 savesegment(fs, fs_sel); 1196 savesegment(gs, gs_sel); 1197 fs_base = read_msr(MSR_FS_BASE); 1198 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1199 } 1200 1201 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1202 #else 1203 savesegment(fs, fs_sel); 1204 savesegment(gs, gs_sel); 1205 fs_base = segment_base(fs_sel); 1206 gs_base = segment_base(gs_sel); 1207 #endif 1208 1209 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1210 vmx->guest_state_loaded = true; 1211 } 1212 1213 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1214 { 1215 struct vmcs_host_state *host_state; 1216 1217 if (!vmx->guest_state_loaded) 1218 return; 1219 1220 host_state = &vmx->loaded_vmcs->host_state; 1221 1222 ++vmx->vcpu.stat.host_state_reload; 1223 1224 #ifdef CONFIG_X86_64 1225 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1226 #endif 1227 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1228 kvm_load_ldt(host_state->ldt_sel); 1229 #ifdef CONFIG_X86_64 1230 load_gs_index(host_state->gs_sel); 1231 #else 1232 loadsegment(gs, host_state->gs_sel); 1233 #endif 1234 } 1235 if (host_state->fs_sel & 7) 1236 loadsegment(fs, host_state->fs_sel); 1237 #ifdef CONFIG_X86_64 1238 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1239 loadsegment(ds, host_state->ds_sel); 1240 loadsegment(es, host_state->es_sel); 1241 } 1242 #endif 1243 invalidate_tss_limit(); 1244 #ifdef CONFIG_X86_64 1245 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1246 #endif 1247 load_fixmap_gdt(raw_smp_processor_id()); 1248 vmx->guest_state_loaded = false; 1249 vmx->guest_msrs_ready = false; 1250 } 1251 1252 #ifdef CONFIG_X86_64 1253 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1254 { 1255 preempt_disable(); 1256 if (vmx->guest_state_loaded) 1257 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1258 preempt_enable(); 1259 return vmx->msr_guest_kernel_gs_base; 1260 } 1261 1262 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1263 { 1264 preempt_disable(); 1265 if (vmx->guest_state_loaded) 1266 wrmsrl(MSR_KERNEL_GS_BASE, data); 1267 preempt_enable(); 1268 vmx->msr_guest_kernel_gs_base = data; 1269 } 1270 #endif 1271 1272 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1273 { 1274 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1275 struct pi_desc old, new; 1276 unsigned int dest; 1277 1278 /* 1279 * In case of hot-plug or hot-unplug, we may have to undo 1280 * vmx_vcpu_pi_put even if there is no assigned device. And we 1281 * always keep PI.NDST up to date for simplicity: it makes the 1282 * code easier, and CPU migration is not a fast path. 1283 */ 1284 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1285 return; 1286 1287 /* 1288 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1289 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1290 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1291 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1292 * correctly. 1293 */ 1294 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1295 pi_clear_sn(pi_desc); 1296 goto after_clear_sn; 1297 } 1298 1299 /* The full case. */ 1300 do { 1301 old.control = new.control = pi_desc->control; 1302 1303 dest = cpu_physical_id(cpu); 1304 1305 if (x2apic_enabled()) 1306 new.ndst = dest; 1307 else 1308 new.ndst = (dest << 8) & 0xFF00; 1309 1310 new.sn = 0; 1311 } while (cmpxchg64(&pi_desc->control, old.control, 1312 new.control) != old.control); 1313 1314 after_clear_sn: 1315 1316 /* 1317 * Clear SN before reading the bitmap. The VT-d firmware 1318 * writes the bitmap and reads SN atomically (5.2.3 in the 1319 * spec), so it doesn't really have a memory barrier that 1320 * pairs with this, but we cannot do that and we need one. 1321 */ 1322 smp_mb__after_atomic(); 1323 1324 if (!pi_is_pir_empty(pi_desc)) 1325 pi_set_on(pi_desc); 1326 } 1327 1328 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1329 { 1330 struct vcpu_vmx *vmx = to_vmx(vcpu); 1331 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1332 1333 if (!already_loaded) { 1334 loaded_vmcs_clear(vmx->loaded_vmcs); 1335 local_irq_disable(); 1336 crash_disable_local_vmclear(cpu); 1337 1338 /* 1339 * Read loaded_vmcs->cpu should be before fetching 1340 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1341 * See the comments in __loaded_vmcs_clear(). 1342 */ 1343 smp_rmb(); 1344 1345 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1346 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1347 crash_enable_local_vmclear(cpu); 1348 local_irq_enable(); 1349 } 1350 1351 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1352 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1353 vmcs_load(vmx->loaded_vmcs->vmcs); 1354 indirect_branch_prediction_barrier(); 1355 } 1356 1357 if (!already_loaded) { 1358 void *gdt = get_current_gdt_ro(); 1359 unsigned long sysenter_esp; 1360 1361 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1362 1363 /* 1364 * Linux uses per-cpu TSS and GDT, so set these when switching 1365 * processors. See 22.2.4. 1366 */ 1367 vmcs_writel(HOST_TR_BASE, 1368 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1369 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1370 1371 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1372 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1373 1374 vmx->loaded_vmcs->cpu = cpu; 1375 } 1376 1377 /* Setup TSC multiplier */ 1378 if (kvm_has_tsc_control && 1379 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1380 decache_tsc_multiplier(vmx); 1381 } 1382 1383 /* 1384 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1385 * vcpu mutex is already taken. 1386 */ 1387 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1388 { 1389 struct vcpu_vmx *vmx = to_vmx(vcpu); 1390 1391 vmx_vcpu_load_vmcs(vcpu, cpu); 1392 1393 vmx_vcpu_pi_load(vcpu, cpu); 1394 1395 vmx->host_pkru = read_pkru(); 1396 vmx->host_debugctlmsr = get_debugctlmsr(); 1397 } 1398 1399 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1400 { 1401 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1402 1403 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1404 !irq_remapping_cap(IRQ_POSTING_CAP) || 1405 !kvm_vcpu_apicv_active(vcpu)) 1406 return; 1407 1408 /* Set SN when the vCPU is preempted */ 1409 if (vcpu->preempted) 1410 pi_set_sn(pi_desc); 1411 } 1412 1413 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1414 { 1415 vmx_vcpu_pi_put(vcpu); 1416 1417 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1418 } 1419 1420 static bool emulation_required(struct kvm_vcpu *vcpu) 1421 { 1422 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1423 } 1424 1425 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); 1426 1427 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1428 { 1429 struct vcpu_vmx *vmx = to_vmx(vcpu); 1430 unsigned long rflags, save_rflags; 1431 1432 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1433 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1434 rflags = vmcs_readl(GUEST_RFLAGS); 1435 if (vmx->rmode.vm86_active) { 1436 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1437 save_rflags = vmx->rmode.save_rflags; 1438 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1439 } 1440 vmx->rflags = rflags; 1441 } 1442 return vmx->rflags; 1443 } 1444 1445 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1446 { 1447 struct vcpu_vmx *vmx = to_vmx(vcpu); 1448 unsigned long old_rflags; 1449 1450 if (enable_unrestricted_guest) { 1451 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1452 vmx->rflags = rflags; 1453 vmcs_writel(GUEST_RFLAGS, rflags); 1454 return; 1455 } 1456 1457 old_rflags = vmx_get_rflags(vcpu); 1458 vmx->rflags = rflags; 1459 if (vmx->rmode.vm86_active) { 1460 vmx->rmode.save_rflags = rflags; 1461 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1462 } 1463 vmcs_writel(GUEST_RFLAGS, rflags); 1464 1465 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1466 vmx->emulation_required = emulation_required(vcpu); 1467 } 1468 1469 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1470 { 1471 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1472 int ret = 0; 1473 1474 if (interruptibility & GUEST_INTR_STATE_STI) 1475 ret |= KVM_X86_SHADOW_INT_STI; 1476 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1477 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1478 1479 return ret; 1480 } 1481 1482 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1483 { 1484 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1485 u32 interruptibility = interruptibility_old; 1486 1487 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1488 1489 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1490 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1491 else if (mask & KVM_X86_SHADOW_INT_STI) 1492 interruptibility |= GUEST_INTR_STATE_STI; 1493 1494 if ((interruptibility != interruptibility_old)) 1495 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1496 } 1497 1498 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1499 { 1500 struct vcpu_vmx *vmx = to_vmx(vcpu); 1501 unsigned long value; 1502 1503 /* 1504 * Any MSR write that attempts to change bits marked reserved will 1505 * case a #GP fault. 1506 */ 1507 if (data & vmx->pt_desc.ctl_bitmask) 1508 return 1; 1509 1510 /* 1511 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1512 * result in a #GP unless the same write also clears TraceEn. 1513 */ 1514 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1515 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1516 return 1; 1517 1518 /* 1519 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1520 * and FabricEn would cause #GP, if 1521 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1522 */ 1523 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1524 !(data & RTIT_CTL_FABRIC_EN) && 1525 !intel_pt_validate_cap(vmx->pt_desc.caps, 1526 PT_CAP_single_range_output)) 1527 return 1; 1528 1529 /* 1530 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1531 * utilize encodings marked reserved will casue a #GP fault. 1532 */ 1533 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1534 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1535 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1536 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1537 return 1; 1538 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1539 PT_CAP_cycle_thresholds); 1540 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1541 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1542 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1543 return 1; 1544 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1545 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1546 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1547 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1548 return 1; 1549 1550 /* 1551 * If ADDRx_CFG is reserved or the encodings is >2 will 1552 * cause a #GP fault. 1553 */ 1554 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1555 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1556 return 1; 1557 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1558 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1559 return 1; 1560 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1561 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1562 return 1; 1563 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1564 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1565 return 1; 1566 1567 return 0; 1568 } 1569 1570 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1571 { 1572 unsigned long rip; 1573 1574 /* 1575 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1576 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1577 * set when EPT misconfig occurs. In practice, real hardware updates 1578 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1579 * (namely Hyper-V) don't set it due to it being undefined behavior, 1580 * i.e. we end up advancing IP with some random value. 1581 */ 1582 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1583 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1584 rip = kvm_rip_read(vcpu); 1585 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1586 kvm_rip_write(vcpu, rip); 1587 } else { 1588 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1589 return 0; 1590 } 1591 1592 /* skipping an emulated instruction also counts */ 1593 vmx_set_interrupt_shadow(vcpu, 0); 1594 1595 return 1; 1596 } 1597 1598 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1599 { 1600 /* 1601 * Ensure that we clear the HLT state in the VMCS. We don't need to 1602 * explicitly skip the instruction because if the HLT state is set, 1603 * then the instruction is already executing and RIP has already been 1604 * advanced. 1605 */ 1606 if (kvm_hlt_in_guest(vcpu->kvm) && 1607 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1608 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1609 } 1610 1611 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1612 { 1613 struct vcpu_vmx *vmx = to_vmx(vcpu); 1614 unsigned nr = vcpu->arch.exception.nr; 1615 bool has_error_code = vcpu->arch.exception.has_error_code; 1616 u32 error_code = vcpu->arch.exception.error_code; 1617 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1618 1619 kvm_deliver_exception_payload(vcpu); 1620 1621 if (has_error_code) { 1622 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1623 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1624 } 1625 1626 if (vmx->rmode.vm86_active) { 1627 int inc_eip = 0; 1628 if (kvm_exception_is_soft(nr)) 1629 inc_eip = vcpu->arch.event_exit_inst_len; 1630 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1631 return; 1632 } 1633 1634 WARN_ON_ONCE(vmx->emulation_required); 1635 1636 if (kvm_exception_is_soft(nr)) { 1637 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1638 vmx->vcpu.arch.event_exit_inst_len); 1639 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1640 } else 1641 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1642 1643 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1644 1645 vmx_clear_hlt(vcpu); 1646 } 1647 1648 static bool vmx_rdtscp_supported(void) 1649 { 1650 return cpu_has_vmx_rdtscp(); 1651 } 1652 1653 static bool vmx_invpcid_supported(void) 1654 { 1655 return cpu_has_vmx_invpcid(); 1656 } 1657 1658 /* 1659 * Swap MSR entry in host/guest MSR entry array. 1660 */ 1661 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1662 { 1663 struct shared_msr_entry tmp; 1664 1665 tmp = vmx->guest_msrs[to]; 1666 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1667 vmx->guest_msrs[from] = tmp; 1668 } 1669 1670 /* 1671 * Set up the vmcs to automatically save and restore system 1672 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1673 * mode, as fiddling with msrs is very expensive. 1674 */ 1675 static void setup_msrs(struct vcpu_vmx *vmx) 1676 { 1677 int save_nmsrs, index; 1678 1679 save_nmsrs = 0; 1680 #ifdef CONFIG_X86_64 1681 /* 1682 * The SYSCALL MSRs are only needed on long mode guests, and only 1683 * when EFER.SCE is set. 1684 */ 1685 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1686 index = __find_msr_index(vmx, MSR_STAR); 1687 if (index >= 0) 1688 move_msr_up(vmx, index, save_nmsrs++); 1689 index = __find_msr_index(vmx, MSR_LSTAR); 1690 if (index >= 0) 1691 move_msr_up(vmx, index, save_nmsrs++); 1692 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1693 if (index >= 0) 1694 move_msr_up(vmx, index, save_nmsrs++); 1695 } 1696 #endif 1697 index = __find_msr_index(vmx, MSR_EFER); 1698 if (index >= 0 && update_transition_efer(vmx, index)) 1699 move_msr_up(vmx, index, save_nmsrs++); 1700 index = __find_msr_index(vmx, MSR_TSC_AUX); 1701 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1702 move_msr_up(vmx, index, save_nmsrs++); 1703 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1704 if (index >= 0) 1705 move_msr_up(vmx, index, save_nmsrs++); 1706 1707 vmx->save_nmsrs = save_nmsrs; 1708 vmx->guest_msrs_ready = false; 1709 1710 if (cpu_has_vmx_msr_bitmap()) 1711 vmx_update_msr_bitmap(&vmx->vcpu); 1712 } 1713 1714 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1715 { 1716 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1717 1718 if (is_guest_mode(vcpu) && 1719 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) 1720 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1721 1722 return vcpu->arch.tsc_offset; 1723 } 1724 1725 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1726 { 1727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1728 u64 g_tsc_offset = 0; 1729 1730 /* 1731 * We're here if L1 chose not to trap WRMSR to TSC. According 1732 * to the spec, this should set L1's TSC; The offset that L1 1733 * set for L2 remains unchanged, and still needs to be added 1734 * to the newly set TSC to get L2's TSC. 1735 */ 1736 if (is_guest_mode(vcpu) && 1737 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) 1738 g_tsc_offset = vmcs12->tsc_offset; 1739 1740 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1741 vcpu->arch.tsc_offset - g_tsc_offset, 1742 offset); 1743 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1744 return offset + g_tsc_offset; 1745 } 1746 1747 /* 1748 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1749 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1750 * all guests if the "nested" module option is off, and can also be disabled 1751 * for a single guest by disabling its VMX cpuid bit. 1752 */ 1753 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1754 { 1755 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1756 } 1757 1758 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1759 uint64_t val) 1760 { 1761 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1762 1763 return !(val & ~valid_bits); 1764 } 1765 1766 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1767 { 1768 switch (msr->index) { 1769 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1770 if (!nested) 1771 return 1; 1772 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1773 default: 1774 return 1; 1775 } 1776 1777 return 0; 1778 } 1779 1780 /* 1781 * Reads an msr value (of 'msr_index') into 'pdata'. 1782 * Returns 0 on success, non-0 otherwise. 1783 * Assumes vcpu_load() was already called. 1784 */ 1785 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1786 { 1787 struct vcpu_vmx *vmx = to_vmx(vcpu); 1788 struct shared_msr_entry *msr; 1789 u32 index; 1790 1791 switch (msr_info->index) { 1792 #ifdef CONFIG_X86_64 1793 case MSR_FS_BASE: 1794 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1795 break; 1796 case MSR_GS_BASE: 1797 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1798 break; 1799 case MSR_KERNEL_GS_BASE: 1800 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1801 break; 1802 #endif 1803 case MSR_EFER: 1804 return kvm_get_msr_common(vcpu, msr_info); 1805 case MSR_IA32_TSX_CTRL: 1806 if (!msr_info->host_initiated && 1807 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1808 return 1; 1809 goto find_shared_msr; 1810 case MSR_IA32_UMWAIT_CONTROL: 1811 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1812 return 1; 1813 1814 msr_info->data = vmx->msr_ia32_umwait_control; 1815 break; 1816 case MSR_IA32_SPEC_CTRL: 1817 if (!msr_info->host_initiated && 1818 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1819 return 1; 1820 1821 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1822 break; 1823 case MSR_IA32_SYSENTER_CS: 1824 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1825 break; 1826 case MSR_IA32_SYSENTER_EIP: 1827 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1828 break; 1829 case MSR_IA32_SYSENTER_ESP: 1830 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1831 break; 1832 case MSR_IA32_BNDCFGS: 1833 if (!kvm_mpx_supported() || 1834 (!msr_info->host_initiated && 1835 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1836 return 1; 1837 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1838 break; 1839 case MSR_IA32_MCG_EXT_CTL: 1840 if (!msr_info->host_initiated && 1841 !(vmx->msr_ia32_feature_control & 1842 FEATURE_CONTROL_LMCE)) 1843 return 1; 1844 msr_info->data = vcpu->arch.mcg_ext_ctl; 1845 break; 1846 case MSR_IA32_FEATURE_CONTROL: 1847 msr_info->data = vmx->msr_ia32_feature_control; 1848 break; 1849 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1850 if (!nested_vmx_allowed(vcpu)) 1851 return 1; 1852 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1853 &msr_info->data); 1854 case MSR_IA32_RTIT_CTL: 1855 if (pt_mode != PT_MODE_HOST_GUEST) 1856 return 1; 1857 msr_info->data = vmx->pt_desc.guest.ctl; 1858 break; 1859 case MSR_IA32_RTIT_STATUS: 1860 if (pt_mode != PT_MODE_HOST_GUEST) 1861 return 1; 1862 msr_info->data = vmx->pt_desc.guest.status; 1863 break; 1864 case MSR_IA32_RTIT_CR3_MATCH: 1865 if ((pt_mode != PT_MODE_HOST_GUEST) || 1866 !intel_pt_validate_cap(vmx->pt_desc.caps, 1867 PT_CAP_cr3_filtering)) 1868 return 1; 1869 msr_info->data = vmx->pt_desc.guest.cr3_match; 1870 break; 1871 case MSR_IA32_RTIT_OUTPUT_BASE: 1872 if ((pt_mode != PT_MODE_HOST_GUEST) || 1873 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1874 PT_CAP_topa_output) && 1875 !intel_pt_validate_cap(vmx->pt_desc.caps, 1876 PT_CAP_single_range_output))) 1877 return 1; 1878 msr_info->data = vmx->pt_desc.guest.output_base; 1879 break; 1880 case MSR_IA32_RTIT_OUTPUT_MASK: 1881 if ((pt_mode != PT_MODE_HOST_GUEST) || 1882 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1883 PT_CAP_topa_output) && 1884 !intel_pt_validate_cap(vmx->pt_desc.caps, 1885 PT_CAP_single_range_output))) 1886 return 1; 1887 msr_info->data = vmx->pt_desc.guest.output_mask; 1888 break; 1889 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1890 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1891 if ((pt_mode != PT_MODE_HOST_GUEST) || 1892 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1893 PT_CAP_num_address_ranges))) 1894 return 1; 1895 if (index % 2) 1896 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1897 else 1898 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1899 break; 1900 case MSR_TSC_AUX: 1901 if (!msr_info->host_initiated && 1902 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1903 return 1; 1904 goto find_shared_msr; 1905 default: 1906 find_shared_msr: 1907 msr = find_msr_entry(vmx, msr_info->index); 1908 if (msr) { 1909 msr_info->data = msr->data; 1910 break; 1911 } 1912 return kvm_get_msr_common(vcpu, msr_info); 1913 } 1914 1915 return 0; 1916 } 1917 1918 /* 1919 * Writes msr value into into the appropriate "register". 1920 * Returns 0 on success, non-0 otherwise. 1921 * Assumes vcpu_load() was already called. 1922 */ 1923 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1924 { 1925 struct vcpu_vmx *vmx = to_vmx(vcpu); 1926 struct shared_msr_entry *msr; 1927 int ret = 0; 1928 u32 msr_index = msr_info->index; 1929 u64 data = msr_info->data; 1930 u32 index; 1931 1932 switch (msr_index) { 1933 case MSR_EFER: 1934 ret = kvm_set_msr_common(vcpu, msr_info); 1935 break; 1936 #ifdef CONFIG_X86_64 1937 case MSR_FS_BASE: 1938 vmx_segment_cache_clear(vmx); 1939 vmcs_writel(GUEST_FS_BASE, data); 1940 break; 1941 case MSR_GS_BASE: 1942 vmx_segment_cache_clear(vmx); 1943 vmcs_writel(GUEST_GS_BASE, data); 1944 break; 1945 case MSR_KERNEL_GS_BASE: 1946 vmx_write_guest_kernel_gs_base(vmx, data); 1947 break; 1948 #endif 1949 case MSR_IA32_SYSENTER_CS: 1950 if (is_guest_mode(vcpu)) 1951 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1952 vmcs_write32(GUEST_SYSENTER_CS, data); 1953 break; 1954 case MSR_IA32_SYSENTER_EIP: 1955 if (is_guest_mode(vcpu)) 1956 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1957 vmcs_writel(GUEST_SYSENTER_EIP, data); 1958 break; 1959 case MSR_IA32_SYSENTER_ESP: 1960 if (is_guest_mode(vcpu)) 1961 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1962 vmcs_writel(GUEST_SYSENTER_ESP, data); 1963 break; 1964 case MSR_IA32_DEBUGCTLMSR: 1965 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1966 VM_EXIT_SAVE_DEBUG_CONTROLS) 1967 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1968 1969 ret = kvm_set_msr_common(vcpu, msr_info); 1970 break; 1971 1972 case MSR_IA32_BNDCFGS: 1973 if (!kvm_mpx_supported() || 1974 (!msr_info->host_initiated && 1975 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1976 return 1; 1977 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1978 (data & MSR_IA32_BNDCFGS_RSVD)) 1979 return 1; 1980 vmcs_write64(GUEST_BNDCFGS, data); 1981 break; 1982 case MSR_IA32_UMWAIT_CONTROL: 1983 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1984 return 1; 1985 1986 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 1987 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 1988 return 1; 1989 1990 vmx->msr_ia32_umwait_control = data; 1991 break; 1992 case MSR_IA32_SPEC_CTRL: 1993 if (!msr_info->host_initiated && 1994 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1995 return 1; 1996 1997 /* The STIBP bit doesn't fault even if it's not advertised */ 1998 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) 1999 return 1; 2000 2001 vmx->spec_ctrl = data; 2002 2003 if (!data) 2004 break; 2005 2006 /* 2007 * For non-nested: 2008 * When it's written (to non-zero) for the first time, pass 2009 * it through. 2010 * 2011 * For nested: 2012 * The handling of the MSR bitmap for L2 guests is done in 2013 * nested_vmx_merge_msr_bitmap. We should not touch the 2014 * vmcs02.msr_bitmap here since it gets completely overwritten 2015 * in the merging. We update the vmcs01 here for L1 as well 2016 * since it will end up touching the MSR anyway now. 2017 */ 2018 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2019 MSR_IA32_SPEC_CTRL, 2020 MSR_TYPE_RW); 2021 break; 2022 case MSR_IA32_TSX_CTRL: 2023 if (!msr_info->host_initiated && 2024 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2025 return 1; 2026 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2027 return 1; 2028 goto find_shared_msr; 2029 case MSR_IA32_PRED_CMD: 2030 if (!msr_info->host_initiated && 2031 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2032 return 1; 2033 2034 if (data & ~PRED_CMD_IBPB) 2035 return 1; 2036 2037 if (!data) 2038 break; 2039 2040 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2041 2042 /* 2043 * For non-nested: 2044 * When it's written (to non-zero) for the first time, pass 2045 * it through. 2046 * 2047 * For nested: 2048 * The handling of the MSR bitmap for L2 guests is done in 2049 * nested_vmx_merge_msr_bitmap. We should not touch the 2050 * vmcs02.msr_bitmap here since it gets completely overwritten 2051 * in the merging. 2052 */ 2053 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2054 MSR_TYPE_W); 2055 break; 2056 case MSR_IA32_CR_PAT: 2057 if (!kvm_pat_valid(data)) 2058 return 1; 2059 2060 if (is_guest_mode(vcpu) && 2061 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2062 get_vmcs12(vcpu)->guest_ia32_pat = data; 2063 2064 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2065 vmcs_write64(GUEST_IA32_PAT, data); 2066 vcpu->arch.pat = data; 2067 break; 2068 } 2069 ret = kvm_set_msr_common(vcpu, msr_info); 2070 break; 2071 case MSR_IA32_TSC_ADJUST: 2072 ret = kvm_set_msr_common(vcpu, msr_info); 2073 break; 2074 case MSR_IA32_MCG_EXT_CTL: 2075 if ((!msr_info->host_initiated && 2076 !(to_vmx(vcpu)->msr_ia32_feature_control & 2077 FEATURE_CONTROL_LMCE)) || 2078 (data & ~MCG_EXT_CTL_LMCE_EN)) 2079 return 1; 2080 vcpu->arch.mcg_ext_ctl = data; 2081 break; 2082 case MSR_IA32_FEATURE_CONTROL: 2083 if (!vmx_feature_control_msr_valid(vcpu, data) || 2084 (to_vmx(vcpu)->msr_ia32_feature_control & 2085 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) 2086 return 1; 2087 vmx->msr_ia32_feature_control = data; 2088 if (msr_info->host_initiated && data == 0) 2089 vmx_leave_nested(vcpu); 2090 break; 2091 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2092 if (!msr_info->host_initiated) 2093 return 1; /* they are read-only */ 2094 if (!nested_vmx_allowed(vcpu)) 2095 return 1; 2096 return vmx_set_vmx_msr(vcpu, msr_index, data); 2097 case MSR_IA32_RTIT_CTL: 2098 if ((pt_mode != PT_MODE_HOST_GUEST) || 2099 vmx_rtit_ctl_check(vcpu, data) || 2100 vmx->nested.vmxon) 2101 return 1; 2102 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2103 vmx->pt_desc.guest.ctl = data; 2104 pt_update_intercept_for_msr(vmx); 2105 break; 2106 case MSR_IA32_RTIT_STATUS: 2107 if ((pt_mode != PT_MODE_HOST_GUEST) || 2108 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2109 (data & MSR_IA32_RTIT_STATUS_MASK)) 2110 return 1; 2111 vmx->pt_desc.guest.status = data; 2112 break; 2113 case MSR_IA32_RTIT_CR3_MATCH: 2114 if ((pt_mode != PT_MODE_HOST_GUEST) || 2115 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2116 !intel_pt_validate_cap(vmx->pt_desc.caps, 2117 PT_CAP_cr3_filtering)) 2118 return 1; 2119 vmx->pt_desc.guest.cr3_match = data; 2120 break; 2121 case MSR_IA32_RTIT_OUTPUT_BASE: 2122 if ((pt_mode != PT_MODE_HOST_GUEST) || 2123 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2124 (!intel_pt_validate_cap(vmx->pt_desc.caps, 2125 PT_CAP_topa_output) && 2126 !intel_pt_validate_cap(vmx->pt_desc.caps, 2127 PT_CAP_single_range_output)) || 2128 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)) 2129 return 1; 2130 vmx->pt_desc.guest.output_base = data; 2131 break; 2132 case MSR_IA32_RTIT_OUTPUT_MASK: 2133 if ((pt_mode != PT_MODE_HOST_GUEST) || 2134 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2135 (!intel_pt_validate_cap(vmx->pt_desc.caps, 2136 PT_CAP_topa_output) && 2137 !intel_pt_validate_cap(vmx->pt_desc.caps, 2138 PT_CAP_single_range_output))) 2139 return 1; 2140 vmx->pt_desc.guest.output_mask = data; 2141 break; 2142 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2143 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2144 if ((pt_mode != PT_MODE_HOST_GUEST) || 2145 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2146 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2147 PT_CAP_num_address_ranges))) 2148 return 1; 2149 if (index % 2) 2150 vmx->pt_desc.guest.addr_b[index / 2] = data; 2151 else 2152 vmx->pt_desc.guest.addr_a[index / 2] = data; 2153 break; 2154 case MSR_TSC_AUX: 2155 if (!msr_info->host_initiated && 2156 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2157 return 1; 2158 /* Check reserved bit, higher 32 bits should be zero */ 2159 if ((data >> 32) != 0) 2160 return 1; 2161 goto find_shared_msr; 2162 2163 default: 2164 find_shared_msr: 2165 msr = find_msr_entry(vmx, msr_index); 2166 if (msr) 2167 ret = vmx_set_guest_msr(vmx, msr, data); 2168 else 2169 ret = kvm_set_msr_common(vcpu, msr_info); 2170 } 2171 2172 return ret; 2173 } 2174 2175 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2176 { 2177 kvm_register_mark_available(vcpu, reg); 2178 2179 switch (reg) { 2180 case VCPU_REGS_RSP: 2181 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2182 break; 2183 case VCPU_REGS_RIP: 2184 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2185 break; 2186 case VCPU_EXREG_PDPTR: 2187 if (enable_ept) 2188 ept_save_pdptrs(vcpu); 2189 break; 2190 case VCPU_EXREG_CR3: 2191 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2192 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2193 break; 2194 default: 2195 WARN_ON_ONCE(1); 2196 break; 2197 } 2198 } 2199 2200 static __init int cpu_has_kvm_support(void) 2201 { 2202 return cpu_has_vmx(); 2203 } 2204 2205 static __init int vmx_disabled_by_bios(void) 2206 { 2207 u64 msr; 2208 2209 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); 2210 if (msr & FEATURE_CONTROL_LOCKED) { 2211 /* launched w/ TXT and VMX disabled */ 2212 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) 2213 && tboot_enabled()) 2214 return 1; 2215 /* launched w/o TXT and VMX only enabled w/ TXT */ 2216 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) 2217 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) 2218 && !tboot_enabled()) { 2219 printk(KERN_WARNING "kvm: disable TXT in the BIOS or " 2220 "activate TXT before enabling KVM\n"); 2221 return 1; 2222 } 2223 /* launched w/o TXT and VMX disabled */ 2224 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) 2225 && !tboot_enabled()) 2226 return 1; 2227 } 2228 2229 return 0; 2230 } 2231 2232 static void kvm_cpu_vmxon(u64 addr) 2233 { 2234 cr4_set_bits(X86_CR4_VMXE); 2235 intel_pt_handle_vmx(1); 2236 2237 asm volatile ("vmxon %0" : : "m"(addr)); 2238 } 2239 2240 static int hardware_enable(void) 2241 { 2242 int cpu = raw_smp_processor_id(); 2243 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2244 u64 old, test_bits; 2245 2246 if (cr4_read_shadow() & X86_CR4_VMXE) 2247 return -EBUSY; 2248 2249 /* 2250 * This can happen if we hot-added a CPU but failed to allocate 2251 * VP assist page for it. 2252 */ 2253 if (static_branch_unlikely(&enable_evmcs) && 2254 !hv_get_vp_assist_page(cpu)) 2255 return -EFAULT; 2256 2257 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2258 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2259 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2260 2261 /* 2262 * Now we can enable the vmclear operation in kdump 2263 * since the loaded_vmcss_on_cpu list on this cpu 2264 * has been initialized. 2265 * 2266 * Though the cpu is not in VMX operation now, there 2267 * is no problem to enable the vmclear operation 2268 * for the loaded_vmcss_on_cpu list is empty! 2269 */ 2270 crash_enable_local_vmclear(cpu); 2271 2272 rdmsrl(MSR_IA32_FEATURE_CONTROL, old); 2273 2274 test_bits = FEATURE_CONTROL_LOCKED; 2275 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 2276 if (tboot_enabled()) 2277 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; 2278 2279 if ((old & test_bits) != test_bits) { 2280 /* enable and lock */ 2281 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); 2282 } 2283 kvm_cpu_vmxon(phys_addr); 2284 if (enable_ept) 2285 ept_sync_global(); 2286 2287 return 0; 2288 } 2289 2290 static void vmclear_local_loaded_vmcss(void) 2291 { 2292 int cpu = raw_smp_processor_id(); 2293 struct loaded_vmcs *v, *n; 2294 2295 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2296 loaded_vmcss_on_cpu_link) 2297 __loaded_vmcs_clear(v); 2298 } 2299 2300 2301 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2302 * tricks. 2303 */ 2304 static void kvm_cpu_vmxoff(void) 2305 { 2306 asm volatile (__ex("vmxoff")); 2307 2308 intel_pt_handle_vmx(0); 2309 cr4_clear_bits(X86_CR4_VMXE); 2310 } 2311 2312 static void hardware_disable(void) 2313 { 2314 vmclear_local_loaded_vmcss(); 2315 kvm_cpu_vmxoff(); 2316 } 2317 2318 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2319 u32 msr, u32 *result) 2320 { 2321 u32 vmx_msr_low, vmx_msr_high; 2322 u32 ctl = ctl_min | ctl_opt; 2323 2324 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2325 2326 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2327 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2328 2329 /* Ensure minimum (required) set of control bits are supported. */ 2330 if (ctl_min & ~ctl) 2331 return -EIO; 2332 2333 *result = ctl; 2334 return 0; 2335 } 2336 2337 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2338 struct vmx_capability *vmx_cap) 2339 { 2340 u32 vmx_msr_low, vmx_msr_high; 2341 u32 min, opt, min2, opt2; 2342 u32 _pin_based_exec_control = 0; 2343 u32 _cpu_based_exec_control = 0; 2344 u32 _cpu_based_2nd_exec_control = 0; 2345 u32 _vmexit_control = 0; 2346 u32 _vmentry_control = 0; 2347 2348 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2349 min = CPU_BASED_HLT_EXITING | 2350 #ifdef CONFIG_X86_64 2351 CPU_BASED_CR8_LOAD_EXITING | 2352 CPU_BASED_CR8_STORE_EXITING | 2353 #endif 2354 CPU_BASED_CR3_LOAD_EXITING | 2355 CPU_BASED_CR3_STORE_EXITING | 2356 CPU_BASED_UNCOND_IO_EXITING | 2357 CPU_BASED_MOV_DR_EXITING | 2358 CPU_BASED_USE_TSC_OFFSETING | 2359 CPU_BASED_MWAIT_EXITING | 2360 CPU_BASED_MONITOR_EXITING | 2361 CPU_BASED_INVLPG_EXITING | 2362 CPU_BASED_RDPMC_EXITING; 2363 2364 opt = CPU_BASED_TPR_SHADOW | 2365 CPU_BASED_USE_MSR_BITMAPS | 2366 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2367 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2368 &_cpu_based_exec_control) < 0) 2369 return -EIO; 2370 #ifdef CONFIG_X86_64 2371 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2372 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2373 ~CPU_BASED_CR8_STORE_EXITING; 2374 #endif 2375 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2376 min2 = 0; 2377 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2378 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2379 SECONDARY_EXEC_WBINVD_EXITING | 2380 SECONDARY_EXEC_ENABLE_VPID | 2381 SECONDARY_EXEC_ENABLE_EPT | 2382 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2383 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2384 SECONDARY_EXEC_DESC | 2385 SECONDARY_EXEC_RDTSCP | 2386 SECONDARY_EXEC_ENABLE_INVPCID | 2387 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2388 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2389 SECONDARY_EXEC_SHADOW_VMCS | 2390 SECONDARY_EXEC_XSAVES | 2391 SECONDARY_EXEC_RDSEED_EXITING | 2392 SECONDARY_EXEC_RDRAND_EXITING | 2393 SECONDARY_EXEC_ENABLE_PML | 2394 SECONDARY_EXEC_TSC_SCALING | 2395 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2396 SECONDARY_EXEC_PT_USE_GPA | 2397 SECONDARY_EXEC_PT_CONCEAL_VMX | 2398 SECONDARY_EXEC_ENABLE_VMFUNC | 2399 SECONDARY_EXEC_ENCLS_EXITING; 2400 if (adjust_vmx_controls(min2, opt2, 2401 MSR_IA32_VMX_PROCBASED_CTLS2, 2402 &_cpu_based_2nd_exec_control) < 0) 2403 return -EIO; 2404 } 2405 #ifndef CONFIG_X86_64 2406 if (!(_cpu_based_2nd_exec_control & 2407 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2408 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2409 #endif 2410 2411 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2412 _cpu_based_2nd_exec_control &= ~( 2413 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2414 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2415 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2416 2417 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2418 &vmx_cap->ept, &vmx_cap->vpid); 2419 2420 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2421 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2422 enabled */ 2423 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2424 CPU_BASED_CR3_STORE_EXITING | 2425 CPU_BASED_INVLPG_EXITING); 2426 } else if (vmx_cap->ept) { 2427 vmx_cap->ept = 0; 2428 pr_warn_once("EPT CAP should not exist if not support " 2429 "1-setting enable EPT VM-execution control\n"); 2430 } 2431 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2432 vmx_cap->vpid) { 2433 vmx_cap->vpid = 0; 2434 pr_warn_once("VPID CAP should not exist if not support " 2435 "1-setting enable VPID VM-execution control\n"); 2436 } 2437 2438 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2439 #ifdef CONFIG_X86_64 2440 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2441 #endif 2442 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2443 VM_EXIT_LOAD_IA32_PAT | 2444 VM_EXIT_LOAD_IA32_EFER | 2445 VM_EXIT_CLEAR_BNDCFGS | 2446 VM_EXIT_PT_CONCEAL_PIP | 2447 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2448 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2449 &_vmexit_control) < 0) 2450 return -EIO; 2451 2452 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2453 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2454 PIN_BASED_VMX_PREEMPTION_TIMER; 2455 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2456 &_pin_based_exec_control) < 0) 2457 return -EIO; 2458 2459 if (cpu_has_broken_vmx_preemption_timer()) 2460 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2461 if (!(_cpu_based_2nd_exec_control & 2462 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2463 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2464 2465 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2466 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2467 VM_ENTRY_LOAD_IA32_PAT | 2468 VM_ENTRY_LOAD_IA32_EFER | 2469 VM_ENTRY_LOAD_BNDCFGS | 2470 VM_ENTRY_PT_CONCEAL_PIP | 2471 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2472 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2473 &_vmentry_control) < 0) 2474 return -EIO; 2475 2476 /* 2477 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2478 * can't be used due to an errata where VM Exit may incorrectly clear 2479 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2480 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2481 */ 2482 if (boot_cpu_data.x86 == 0x6) { 2483 switch (boot_cpu_data.x86_model) { 2484 case 26: /* AAK155 */ 2485 case 30: /* AAP115 */ 2486 case 37: /* AAT100 */ 2487 case 44: /* BC86,AAY89,BD102 */ 2488 case 46: /* BA97 */ 2489 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2490 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2491 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2492 "does not work properly. Using workaround\n"); 2493 break; 2494 default: 2495 break; 2496 } 2497 } 2498 2499 2500 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2501 2502 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2503 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2504 return -EIO; 2505 2506 #ifdef CONFIG_X86_64 2507 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2508 if (vmx_msr_high & (1u<<16)) 2509 return -EIO; 2510 #endif 2511 2512 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2513 if (((vmx_msr_high >> 18) & 15) != 6) 2514 return -EIO; 2515 2516 vmcs_conf->size = vmx_msr_high & 0x1fff; 2517 vmcs_conf->order = get_order(vmcs_conf->size); 2518 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2519 2520 vmcs_conf->revision_id = vmx_msr_low; 2521 2522 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2523 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2524 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2525 vmcs_conf->vmexit_ctrl = _vmexit_control; 2526 vmcs_conf->vmentry_ctrl = _vmentry_control; 2527 2528 if (static_branch_unlikely(&enable_evmcs)) 2529 evmcs_sanitize_exec_ctrls(vmcs_conf); 2530 2531 return 0; 2532 } 2533 2534 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2535 { 2536 int node = cpu_to_node(cpu); 2537 struct page *pages; 2538 struct vmcs *vmcs; 2539 2540 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2541 if (!pages) 2542 return NULL; 2543 vmcs = page_address(pages); 2544 memset(vmcs, 0, vmcs_config.size); 2545 2546 /* KVM supports Enlightened VMCS v1 only */ 2547 if (static_branch_unlikely(&enable_evmcs)) 2548 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2549 else 2550 vmcs->hdr.revision_id = vmcs_config.revision_id; 2551 2552 if (shadow) 2553 vmcs->hdr.shadow_vmcs = 1; 2554 return vmcs; 2555 } 2556 2557 void free_vmcs(struct vmcs *vmcs) 2558 { 2559 free_pages((unsigned long)vmcs, vmcs_config.order); 2560 } 2561 2562 /* 2563 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2564 */ 2565 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2566 { 2567 if (!loaded_vmcs->vmcs) 2568 return; 2569 loaded_vmcs_clear(loaded_vmcs); 2570 free_vmcs(loaded_vmcs->vmcs); 2571 loaded_vmcs->vmcs = NULL; 2572 if (loaded_vmcs->msr_bitmap) 2573 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2574 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2575 } 2576 2577 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2578 { 2579 loaded_vmcs->vmcs = alloc_vmcs(false); 2580 if (!loaded_vmcs->vmcs) 2581 return -ENOMEM; 2582 2583 loaded_vmcs->shadow_vmcs = NULL; 2584 loaded_vmcs->hv_timer_soft_disabled = false; 2585 loaded_vmcs_init(loaded_vmcs); 2586 2587 if (cpu_has_vmx_msr_bitmap()) { 2588 loaded_vmcs->msr_bitmap = (unsigned long *) 2589 __get_free_page(GFP_KERNEL_ACCOUNT); 2590 if (!loaded_vmcs->msr_bitmap) 2591 goto out_vmcs; 2592 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2593 2594 if (IS_ENABLED(CONFIG_HYPERV) && 2595 static_branch_unlikely(&enable_evmcs) && 2596 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2597 struct hv_enlightened_vmcs *evmcs = 2598 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2599 2600 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2601 } 2602 } 2603 2604 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2605 memset(&loaded_vmcs->controls_shadow, 0, 2606 sizeof(struct vmcs_controls_shadow)); 2607 2608 return 0; 2609 2610 out_vmcs: 2611 free_loaded_vmcs(loaded_vmcs); 2612 return -ENOMEM; 2613 } 2614 2615 static void free_kvm_area(void) 2616 { 2617 int cpu; 2618 2619 for_each_possible_cpu(cpu) { 2620 free_vmcs(per_cpu(vmxarea, cpu)); 2621 per_cpu(vmxarea, cpu) = NULL; 2622 } 2623 } 2624 2625 static __init int alloc_kvm_area(void) 2626 { 2627 int cpu; 2628 2629 for_each_possible_cpu(cpu) { 2630 struct vmcs *vmcs; 2631 2632 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2633 if (!vmcs) { 2634 free_kvm_area(); 2635 return -ENOMEM; 2636 } 2637 2638 /* 2639 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2640 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2641 * revision_id reported by MSR_IA32_VMX_BASIC. 2642 * 2643 * However, even though not explicitly documented by 2644 * TLFS, VMXArea passed as VMXON argument should 2645 * still be marked with revision_id reported by 2646 * physical CPU. 2647 */ 2648 if (static_branch_unlikely(&enable_evmcs)) 2649 vmcs->hdr.revision_id = vmcs_config.revision_id; 2650 2651 per_cpu(vmxarea, cpu) = vmcs; 2652 } 2653 return 0; 2654 } 2655 2656 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2657 struct kvm_segment *save) 2658 { 2659 if (!emulate_invalid_guest_state) { 2660 /* 2661 * CS and SS RPL should be equal during guest entry according 2662 * to VMX spec, but in reality it is not always so. Since vcpu 2663 * is in the middle of the transition from real mode to 2664 * protected mode it is safe to assume that RPL 0 is a good 2665 * default value. 2666 */ 2667 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2668 save->selector &= ~SEGMENT_RPL_MASK; 2669 save->dpl = save->selector & SEGMENT_RPL_MASK; 2670 save->s = 1; 2671 } 2672 vmx_set_segment(vcpu, save, seg); 2673 } 2674 2675 static void enter_pmode(struct kvm_vcpu *vcpu) 2676 { 2677 unsigned long flags; 2678 struct vcpu_vmx *vmx = to_vmx(vcpu); 2679 2680 /* 2681 * Update real mode segment cache. It may be not up-to-date if sement 2682 * register was written while vcpu was in a guest mode. 2683 */ 2684 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2685 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2686 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2687 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2688 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2689 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2690 2691 vmx->rmode.vm86_active = 0; 2692 2693 vmx_segment_cache_clear(vmx); 2694 2695 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2696 2697 flags = vmcs_readl(GUEST_RFLAGS); 2698 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2699 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2700 vmcs_writel(GUEST_RFLAGS, flags); 2701 2702 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2703 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2704 2705 update_exception_bitmap(vcpu); 2706 2707 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2708 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2709 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2710 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2711 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2712 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2713 } 2714 2715 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2716 { 2717 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2718 struct kvm_segment var = *save; 2719 2720 var.dpl = 0x3; 2721 if (seg == VCPU_SREG_CS) 2722 var.type = 0x3; 2723 2724 if (!emulate_invalid_guest_state) { 2725 var.selector = var.base >> 4; 2726 var.base = var.base & 0xffff0; 2727 var.limit = 0xffff; 2728 var.g = 0; 2729 var.db = 0; 2730 var.present = 1; 2731 var.s = 1; 2732 var.l = 0; 2733 var.unusable = 0; 2734 var.type = 0x3; 2735 var.avl = 0; 2736 if (save->base & 0xf) 2737 printk_once(KERN_WARNING "kvm: segment base is not " 2738 "paragraph aligned when entering " 2739 "protected mode (seg=%d)", seg); 2740 } 2741 2742 vmcs_write16(sf->selector, var.selector); 2743 vmcs_writel(sf->base, var.base); 2744 vmcs_write32(sf->limit, var.limit); 2745 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2746 } 2747 2748 static void enter_rmode(struct kvm_vcpu *vcpu) 2749 { 2750 unsigned long flags; 2751 struct vcpu_vmx *vmx = to_vmx(vcpu); 2752 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2753 2754 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2757 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2758 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2759 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2760 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2761 2762 vmx->rmode.vm86_active = 1; 2763 2764 /* 2765 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2766 * vcpu. Warn the user that an update is overdue. 2767 */ 2768 if (!kvm_vmx->tss_addr) 2769 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2770 "called before entering vcpu\n"); 2771 2772 vmx_segment_cache_clear(vmx); 2773 2774 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2775 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2776 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2777 2778 flags = vmcs_readl(GUEST_RFLAGS); 2779 vmx->rmode.save_rflags = flags; 2780 2781 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2782 2783 vmcs_writel(GUEST_RFLAGS, flags); 2784 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2785 update_exception_bitmap(vcpu); 2786 2787 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2788 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2789 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2790 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2791 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2792 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2793 2794 kvm_mmu_reset_context(vcpu); 2795 } 2796 2797 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2798 { 2799 struct vcpu_vmx *vmx = to_vmx(vcpu); 2800 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2801 2802 if (!msr) 2803 return; 2804 2805 vcpu->arch.efer = efer; 2806 if (efer & EFER_LMA) { 2807 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2808 msr->data = efer; 2809 } else { 2810 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2811 2812 msr->data = efer & ~EFER_LME; 2813 } 2814 setup_msrs(vmx); 2815 } 2816 2817 #ifdef CONFIG_X86_64 2818 2819 static void enter_lmode(struct kvm_vcpu *vcpu) 2820 { 2821 u32 guest_tr_ar; 2822 2823 vmx_segment_cache_clear(to_vmx(vcpu)); 2824 2825 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2826 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2827 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2828 __func__); 2829 vmcs_write32(GUEST_TR_AR_BYTES, 2830 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2831 | VMX_AR_TYPE_BUSY_64_TSS); 2832 } 2833 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2834 } 2835 2836 static void exit_lmode(struct kvm_vcpu *vcpu) 2837 { 2838 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2839 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2840 } 2841 2842 #endif 2843 2844 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2845 { 2846 int vpid = to_vmx(vcpu)->vpid; 2847 2848 if (!vpid_sync_vcpu_addr(vpid, addr)) 2849 vpid_sync_context(vpid); 2850 2851 /* 2852 * If VPIDs are not supported or enabled, then the above is a no-op. 2853 * But we don't really need a TLB flush in that case anyway, because 2854 * each VM entry/exit includes an implicit flush when VPID is 0. 2855 */ 2856 } 2857 2858 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2859 { 2860 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2861 2862 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2863 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2864 } 2865 2866 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2867 { 2868 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2869 2870 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2871 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2872 } 2873 2874 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2875 { 2876 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2877 2878 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2879 return; 2880 2881 if (is_pae_paging(vcpu)) { 2882 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2883 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2884 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2885 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2886 } 2887 } 2888 2889 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2890 { 2891 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2892 2893 if (is_pae_paging(vcpu)) { 2894 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2895 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2896 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2897 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2898 } 2899 2900 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2901 } 2902 2903 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2904 unsigned long cr0, 2905 struct kvm_vcpu *vcpu) 2906 { 2907 struct vcpu_vmx *vmx = to_vmx(vcpu); 2908 2909 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2910 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2911 if (!(cr0 & X86_CR0_PG)) { 2912 /* From paging/starting to nonpaging */ 2913 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2914 CPU_BASED_CR3_STORE_EXITING); 2915 vcpu->arch.cr0 = cr0; 2916 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2917 } else if (!is_paging(vcpu)) { 2918 /* From nonpaging to paging */ 2919 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2920 CPU_BASED_CR3_STORE_EXITING); 2921 vcpu->arch.cr0 = cr0; 2922 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2923 } 2924 2925 if (!(cr0 & X86_CR0_WP)) 2926 *hw_cr0 &= ~X86_CR0_WP; 2927 } 2928 2929 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2930 { 2931 struct vcpu_vmx *vmx = to_vmx(vcpu); 2932 unsigned long hw_cr0; 2933 2934 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2935 if (enable_unrestricted_guest) 2936 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2937 else { 2938 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2939 2940 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2941 enter_pmode(vcpu); 2942 2943 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2944 enter_rmode(vcpu); 2945 } 2946 2947 #ifdef CONFIG_X86_64 2948 if (vcpu->arch.efer & EFER_LME) { 2949 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2950 enter_lmode(vcpu); 2951 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2952 exit_lmode(vcpu); 2953 } 2954 #endif 2955 2956 if (enable_ept && !enable_unrestricted_guest) 2957 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2958 2959 vmcs_writel(CR0_READ_SHADOW, cr0); 2960 vmcs_writel(GUEST_CR0, hw_cr0); 2961 vcpu->arch.cr0 = cr0; 2962 2963 /* depends on vcpu->arch.cr0 to be set to a new value */ 2964 vmx->emulation_required = emulation_required(vcpu); 2965 } 2966 2967 static int get_ept_level(struct kvm_vcpu *vcpu) 2968 { 2969 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2970 return 5; 2971 return 4; 2972 } 2973 2974 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2975 { 2976 u64 eptp = VMX_EPTP_MT_WB; 2977 2978 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2979 2980 if (enable_ept_ad_bits && 2981 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2982 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2983 eptp |= (root_hpa & PAGE_MASK); 2984 2985 return eptp; 2986 } 2987 2988 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 2989 { 2990 struct kvm *kvm = vcpu->kvm; 2991 bool update_guest_cr3 = true; 2992 unsigned long guest_cr3; 2993 u64 eptp; 2994 2995 guest_cr3 = cr3; 2996 if (enable_ept) { 2997 eptp = construct_eptp(vcpu, cr3); 2998 vmcs_write64(EPT_POINTER, eptp); 2999 3000 if (kvm_x86_ops->tlb_remote_flush) { 3001 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3002 to_vmx(vcpu)->ept_pointer = eptp; 3003 to_kvm_vmx(kvm)->ept_pointers_match 3004 = EPT_POINTERS_CHECK; 3005 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3006 } 3007 3008 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 3009 if (is_guest_mode(vcpu)) 3010 update_guest_cr3 = false; 3011 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 3012 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3013 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 3014 guest_cr3 = vcpu->arch.cr3; 3015 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3016 update_guest_cr3 = false; 3017 ept_load_pdptrs(vcpu); 3018 } 3019 3020 if (update_guest_cr3) 3021 vmcs_writel(GUEST_CR3, guest_cr3); 3022 } 3023 3024 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3025 { 3026 struct vcpu_vmx *vmx = to_vmx(vcpu); 3027 /* 3028 * Pass through host's Machine Check Enable value to hw_cr4, which 3029 * is in force while we are in guest mode. Do not let guests control 3030 * this bit, even if host CR4.MCE == 0. 3031 */ 3032 unsigned long hw_cr4; 3033 3034 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3035 if (enable_unrestricted_guest) 3036 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3037 else if (vmx->rmode.vm86_active) 3038 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3039 else 3040 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3041 3042 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3043 if (cr4 & X86_CR4_UMIP) { 3044 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3045 hw_cr4 &= ~X86_CR4_UMIP; 3046 } else if (!is_guest_mode(vcpu) || 3047 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3048 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3049 } 3050 } 3051 3052 if (cr4 & X86_CR4_VMXE) { 3053 /* 3054 * To use VMXON (and later other VMX instructions), a guest 3055 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3056 * So basically the check on whether to allow nested VMX 3057 * is here. We operate under the default treatment of SMM, 3058 * so VMX cannot be enabled under SMM. 3059 */ 3060 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3061 return 1; 3062 } 3063 3064 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3065 return 1; 3066 3067 vcpu->arch.cr4 = cr4; 3068 3069 if (!enable_unrestricted_guest) { 3070 if (enable_ept) { 3071 if (!is_paging(vcpu)) { 3072 hw_cr4 &= ~X86_CR4_PAE; 3073 hw_cr4 |= X86_CR4_PSE; 3074 } else if (!(cr4 & X86_CR4_PAE)) { 3075 hw_cr4 &= ~X86_CR4_PAE; 3076 } 3077 } 3078 3079 /* 3080 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3081 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3082 * to be manually disabled when guest switches to non-paging 3083 * mode. 3084 * 3085 * If !enable_unrestricted_guest, the CPU is always running 3086 * with CR0.PG=1 and CR4 needs to be modified. 3087 * If enable_unrestricted_guest, the CPU automatically 3088 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3089 */ 3090 if (!is_paging(vcpu)) 3091 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3092 } 3093 3094 vmcs_writel(CR4_READ_SHADOW, cr4); 3095 vmcs_writel(GUEST_CR4, hw_cr4); 3096 return 0; 3097 } 3098 3099 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3100 { 3101 struct vcpu_vmx *vmx = to_vmx(vcpu); 3102 u32 ar; 3103 3104 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3105 *var = vmx->rmode.segs[seg]; 3106 if (seg == VCPU_SREG_TR 3107 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3108 return; 3109 var->base = vmx_read_guest_seg_base(vmx, seg); 3110 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3111 return; 3112 } 3113 var->base = vmx_read_guest_seg_base(vmx, seg); 3114 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3115 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3116 ar = vmx_read_guest_seg_ar(vmx, seg); 3117 var->unusable = (ar >> 16) & 1; 3118 var->type = ar & 15; 3119 var->s = (ar >> 4) & 1; 3120 var->dpl = (ar >> 5) & 3; 3121 /* 3122 * Some userspaces do not preserve unusable property. Since usable 3123 * segment has to be present according to VMX spec we can use present 3124 * property to amend userspace bug by making unusable segment always 3125 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3126 * segment as unusable. 3127 */ 3128 var->present = !var->unusable; 3129 var->avl = (ar >> 12) & 1; 3130 var->l = (ar >> 13) & 1; 3131 var->db = (ar >> 14) & 1; 3132 var->g = (ar >> 15) & 1; 3133 } 3134 3135 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3136 { 3137 struct kvm_segment s; 3138 3139 if (to_vmx(vcpu)->rmode.vm86_active) { 3140 vmx_get_segment(vcpu, &s, seg); 3141 return s.base; 3142 } 3143 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3144 } 3145 3146 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3147 { 3148 struct vcpu_vmx *vmx = to_vmx(vcpu); 3149 3150 if (unlikely(vmx->rmode.vm86_active)) 3151 return 0; 3152 else { 3153 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3154 return VMX_AR_DPL(ar); 3155 } 3156 } 3157 3158 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3159 { 3160 u32 ar; 3161 3162 if (var->unusable || !var->present) 3163 ar = 1 << 16; 3164 else { 3165 ar = var->type & 15; 3166 ar |= (var->s & 1) << 4; 3167 ar |= (var->dpl & 3) << 5; 3168 ar |= (var->present & 1) << 7; 3169 ar |= (var->avl & 1) << 12; 3170 ar |= (var->l & 1) << 13; 3171 ar |= (var->db & 1) << 14; 3172 ar |= (var->g & 1) << 15; 3173 } 3174 3175 return ar; 3176 } 3177 3178 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3179 { 3180 struct vcpu_vmx *vmx = to_vmx(vcpu); 3181 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3182 3183 vmx_segment_cache_clear(vmx); 3184 3185 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3186 vmx->rmode.segs[seg] = *var; 3187 if (seg == VCPU_SREG_TR) 3188 vmcs_write16(sf->selector, var->selector); 3189 else if (var->s) 3190 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3191 goto out; 3192 } 3193 3194 vmcs_writel(sf->base, var->base); 3195 vmcs_write32(sf->limit, var->limit); 3196 vmcs_write16(sf->selector, var->selector); 3197 3198 /* 3199 * Fix the "Accessed" bit in AR field of segment registers for older 3200 * qemu binaries. 3201 * IA32 arch specifies that at the time of processor reset the 3202 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3203 * is setting it to 0 in the userland code. This causes invalid guest 3204 * state vmexit when "unrestricted guest" mode is turned on. 3205 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3206 * tree. Newer qemu binaries with that qemu fix would not need this 3207 * kvm hack. 3208 */ 3209 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3210 var->type |= 0x1; /* Accessed */ 3211 3212 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3213 3214 out: 3215 vmx->emulation_required = emulation_required(vcpu); 3216 } 3217 3218 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3219 { 3220 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3221 3222 *db = (ar >> 14) & 1; 3223 *l = (ar >> 13) & 1; 3224 } 3225 3226 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3227 { 3228 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3229 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3230 } 3231 3232 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3233 { 3234 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3235 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3236 } 3237 3238 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3239 { 3240 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3241 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3242 } 3243 3244 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3245 { 3246 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3247 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3248 } 3249 3250 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3251 { 3252 struct kvm_segment var; 3253 u32 ar; 3254 3255 vmx_get_segment(vcpu, &var, seg); 3256 var.dpl = 0x3; 3257 if (seg == VCPU_SREG_CS) 3258 var.type = 0x3; 3259 ar = vmx_segment_access_rights(&var); 3260 3261 if (var.base != (var.selector << 4)) 3262 return false; 3263 if (var.limit != 0xffff) 3264 return false; 3265 if (ar != 0xf3) 3266 return false; 3267 3268 return true; 3269 } 3270 3271 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3272 { 3273 struct kvm_segment cs; 3274 unsigned int cs_rpl; 3275 3276 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3277 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3278 3279 if (cs.unusable) 3280 return false; 3281 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3282 return false; 3283 if (!cs.s) 3284 return false; 3285 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3286 if (cs.dpl > cs_rpl) 3287 return false; 3288 } else { 3289 if (cs.dpl != cs_rpl) 3290 return false; 3291 } 3292 if (!cs.present) 3293 return false; 3294 3295 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3296 return true; 3297 } 3298 3299 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3300 { 3301 struct kvm_segment ss; 3302 unsigned int ss_rpl; 3303 3304 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3305 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3306 3307 if (ss.unusable) 3308 return true; 3309 if (ss.type != 3 && ss.type != 7) 3310 return false; 3311 if (!ss.s) 3312 return false; 3313 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3314 return false; 3315 if (!ss.present) 3316 return false; 3317 3318 return true; 3319 } 3320 3321 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3322 { 3323 struct kvm_segment var; 3324 unsigned int rpl; 3325 3326 vmx_get_segment(vcpu, &var, seg); 3327 rpl = var.selector & SEGMENT_RPL_MASK; 3328 3329 if (var.unusable) 3330 return true; 3331 if (!var.s) 3332 return false; 3333 if (!var.present) 3334 return false; 3335 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3336 if (var.dpl < rpl) /* DPL < RPL */ 3337 return false; 3338 } 3339 3340 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3341 * rights flags 3342 */ 3343 return true; 3344 } 3345 3346 static bool tr_valid(struct kvm_vcpu *vcpu) 3347 { 3348 struct kvm_segment tr; 3349 3350 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3351 3352 if (tr.unusable) 3353 return false; 3354 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3355 return false; 3356 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3357 return false; 3358 if (!tr.present) 3359 return false; 3360 3361 return true; 3362 } 3363 3364 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3365 { 3366 struct kvm_segment ldtr; 3367 3368 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3369 3370 if (ldtr.unusable) 3371 return true; 3372 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3373 return false; 3374 if (ldtr.type != 2) 3375 return false; 3376 if (!ldtr.present) 3377 return false; 3378 3379 return true; 3380 } 3381 3382 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3383 { 3384 struct kvm_segment cs, ss; 3385 3386 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3387 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3388 3389 return ((cs.selector & SEGMENT_RPL_MASK) == 3390 (ss.selector & SEGMENT_RPL_MASK)); 3391 } 3392 3393 /* 3394 * Check if guest state is valid. Returns true if valid, false if 3395 * not. 3396 * We assume that registers are always usable 3397 */ 3398 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3399 { 3400 if (enable_unrestricted_guest) 3401 return true; 3402 3403 /* real mode guest state checks */ 3404 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3405 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3406 return false; 3407 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3408 return false; 3409 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3410 return false; 3411 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3412 return false; 3413 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3414 return false; 3415 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3416 return false; 3417 } else { 3418 /* protected mode guest state checks */ 3419 if (!cs_ss_rpl_check(vcpu)) 3420 return false; 3421 if (!code_segment_valid(vcpu)) 3422 return false; 3423 if (!stack_segment_valid(vcpu)) 3424 return false; 3425 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3426 return false; 3427 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3428 return false; 3429 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3430 return false; 3431 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3432 return false; 3433 if (!tr_valid(vcpu)) 3434 return false; 3435 if (!ldtr_valid(vcpu)) 3436 return false; 3437 } 3438 /* TODO: 3439 * - Add checks on RIP 3440 * - Add checks on RFLAGS 3441 */ 3442 3443 return true; 3444 } 3445 3446 static int init_rmode_tss(struct kvm *kvm) 3447 { 3448 gfn_t fn; 3449 u16 data = 0; 3450 int idx, r; 3451 3452 idx = srcu_read_lock(&kvm->srcu); 3453 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3454 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3455 if (r < 0) 3456 goto out; 3457 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3458 r = kvm_write_guest_page(kvm, fn++, &data, 3459 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3460 if (r < 0) 3461 goto out; 3462 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3463 if (r < 0) 3464 goto out; 3465 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3466 if (r < 0) 3467 goto out; 3468 data = ~0; 3469 r = kvm_write_guest_page(kvm, fn, &data, 3470 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3471 sizeof(u8)); 3472 out: 3473 srcu_read_unlock(&kvm->srcu, idx); 3474 return r; 3475 } 3476 3477 static int init_rmode_identity_map(struct kvm *kvm) 3478 { 3479 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3480 int i, idx, r = 0; 3481 kvm_pfn_t identity_map_pfn; 3482 u32 tmp; 3483 3484 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3485 mutex_lock(&kvm->slots_lock); 3486 3487 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3488 goto out2; 3489 3490 if (!kvm_vmx->ept_identity_map_addr) 3491 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3492 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3493 3494 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3495 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3496 if (r < 0) 3497 goto out2; 3498 3499 idx = srcu_read_lock(&kvm->srcu); 3500 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3501 if (r < 0) 3502 goto out; 3503 /* Set up identity-mapping pagetable for EPT in real mode */ 3504 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3505 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3506 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3507 r = kvm_write_guest_page(kvm, identity_map_pfn, 3508 &tmp, i * sizeof(tmp), sizeof(tmp)); 3509 if (r < 0) 3510 goto out; 3511 } 3512 kvm_vmx->ept_identity_pagetable_done = true; 3513 3514 out: 3515 srcu_read_unlock(&kvm->srcu, idx); 3516 3517 out2: 3518 mutex_unlock(&kvm->slots_lock); 3519 return r; 3520 } 3521 3522 static void seg_setup(int seg) 3523 { 3524 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3525 unsigned int ar; 3526 3527 vmcs_write16(sf->selector, 0); 3528 vmcs_writel(sf->base, 0); 3529 vmcs_write32(sf->limit, 0xffff); 3530 ar = 0x93; 3531 if (seg == VCPU_SREG_CS) 3532 ar |= 0x08; /* code segment */ 3533 3534 vmcs_write32(sf->ar_bytes, ar); 3535 } 3536 3537 static int alloc_apic_access_page(struct kvm *kvm) 3538 { 3539 struct page *page; 3540 int r = 0; 3541 3542 mutex_lock(&kvm->slots_lock); 3543 if (kvm->arch.apic_access_page_done) 3544 goto out; 3545 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3546 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3547 if (r) 3548 goto out; 3549 3550 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3551 if (is_error_page(page)) { 3552 r = -EFAULT; 3553 goto out; 3554 } 3555 3556 /* 3557 * Do not pin the page in memory, so that memory hot-unplug 3558 * is able to migrate it. 3559 */ 3560 put_page(page); 3561 kvm->arch.apic_access_page_done = true; 3562 out: 3563 mutex_unlock(&kvm->slots_lock); 3564 return r; 3565 } 3566 3567 int allocate_vpid(void) 3568 { 3569 int vpid; 3570 3571 if (!enable_vpid) 3572 return 0; 3573 spin_lock(&vmx_vpid_lock); 3574 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3575 if (vpid < VMX_NR_VPIDS) 3576 __set_bit(vpid, vmx_vpid_bitmap); 3577 else 3578 vpid = 0; 3579 spin_unlock(&vmx_vpid_lock); 3580 return vpid; 3581 } 3582 3583 void free_vpid(int vpid) 3584 { 3585 if (!enable_vpid || vpid == 0) 3586 return; 3587 spin_lock(&vmx_vpid_lock); 3588 __clear_bit(vpid, vmx_vpid_bitmap); 3589 spin_unlock(&vmx_vpid_lock); 3590 } 3591 3592 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3593 u32 msr, int type) 3594 { 3595 int f = sizeof(unsigned long); 3596 3597 if (!cpu_has_vmx_msr_bitmap()) 3598 return; 3599 3600 if (static_branch_unlikely(&enable_evmcs)) 3601 evmcs_touch_msr_bitmap(); 3602 3603 /* 3604 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3605 * have the write-low and read-high bitmap offsets the wrong way round. 3606 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3607 */ 3608 if (msr <= 0x1fff) { 3609 if (type & MSR_TYPE_R) 3610 /* read-low */ 3611 __clear_bit(msr, msr_bitmap + 0x000 / f); 3612 3613 if (type & MSR_TYPE_W) 3614 /* write-low */ 3615 __clear_bit(msr, msr_bitmap + 0x800 / f); 3616 3617 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3618 msr &= 0x1fff; 3619 if (type & MSR_TYPE_R) 3620 /* read-high */ 3621 __clear_bit(msr, msr_bitmap + 0x400 / f); 3622 3623 if (type & MSR_TYPE_W) 3624 /* write-high */ 3625 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3626 3627 } 3628 } 3629 3630 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3631 u32 msr, int type) 3632 { 3633 int f = sizeof(unsigned long); 3634 3635 if (!cpu_has_vmx_msr_bitmap()) 3636 return; 3637 3638 if (static_branch_unlikely(&enable_evmcs)) 3639 evmcs_touch_msr_bitmap(); 3640 3641 /* 3642 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3643 * have the write-low and read-high bitmap offsets the wrong way round. 3644 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3645 */ 3646 if (msr <= 0x1fff) { 3647 if (type & MSR_TYPE_R) 3648 /* read-low */ 3649 __set_bit(msr, msr_bitmap + 0x000 / f); 3650 3651 if (type & MSR_TYPE_W) 3652 /* write-low */ 3653 __set_bit(msr, msr_bitmap + 0x800 / f); 3654 3655 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3656 msr &= 0x1fff; 3657 if (type & MSR_TYPE_R) 3658 /* read-high */ 3659 __set_bit(msr, msr_bitmap + 0x400 / f); 3660 3661 if (type & MSR_TYPE_W) 3662 /* write-high */ 3663 __set_bit(msr, msr_bitmap + 0xc00 / f); 3664 3665 } 3666 } 3667 3668 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3669 u32 msr, int type, bool value) 3670 { 3671 if (value) 3672 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3673 else 3674 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3675 } 3676 3677 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3678 { 3679 u8 mode = 0; 3680 3681 if (cpu_has_secondary_exec_ctrls() && 3682 (secondary_exec_controls_get(to_vmx(vcpu)) & 3683 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3684 mode |= MSR_BITMAP_MODE_X2APIC; 3685 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3686 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3687 } 3688 3689 return mode; 3690 } 3691 3692 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3693 u8 mode) 3694 { 3695 int msr; 3696 3697 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3698 unsigned word = msr / BITS_PER_LONG; 3699 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3700 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3701 } 3702 3703 if (mode & MSR_BITMAP_MODE_X2APIC) { 3704 /* 3705 * TPR reads and writes can be virtualized even if virtual interrupt 3706 * delivery is not in use. 3707 */ 3708 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3709 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3710 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3711 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3712 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3713 } 3714 } 3715 } 3716 3717 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3718 { 3719 struct vcpu_vmx *vmx = to_vmx(vcpu); 3720 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3721 u8 mode = vmx_msr_bitmap_mode(vcpu); 3722 u8 changed = mode ^ vmx->msr_bitmap_mode; 3723 3724 if (!changed) 3725 return; 3726 3727 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3728 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3729 3730 vmx->msr_bitmap_mode = mode; 3731 } 3732 3733 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3734 { 3735 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3736 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3737 u32 i; 3738 3739 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3740 MSR_TYPE_RW, flag); 3741 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3742 MSR_TYPE_RW, flag); 3743 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3744 MSR_TYPE_RW, flag); 3745 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3746 MSR_TYPE_RW, flag); 3747 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3748 vmx_set_intercept_for_msr(msr_bitmap, 3749 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3750 vmx_set_intercept_for_msr(msr_bitmap, 3751 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3752 } 3753 } 3754 3755 static bool vmx_get_enable_apicv(struct kvm *kvm) 3756 { 3757 return enable_apicv; 3758 } 3759 3760 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3761 { 3762 struct vcpu_vmx *vmx = to_vmx(vcpu); 3763 void *vapic_page; 3764 u32 vppr; 3765 int rvi; 3766 3767 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3768 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3769 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3770 return false; 3771 3772 rvi = vmx_get_rvi(); 3773 3774 vapic_page = vmx->nested.virtual_apic_map.hva; 3775 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3776 3777 return ((rvi & 0xf0) > (vppr & 0xf0)); 3778 } 3779 3780 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3781 bool nested) 3782 { 3783 #ifdef CONFIG_SMP 3784 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3785 3786 if (vcpu->mode == IN_GUEST_MODE) { 3787 /* 3788 * The vector of interrupt to be delivered to vcpu had 3789 * been set in PIR before this function. 3790 * 3791 * Following cases will be reached in this block, and 3792 * we always send a notification event in all cases as 3793 * explained below. 3794 * 3795 * Case 1: vcpu keeps in non-root mode. Sending a 3796 * notification event posts the interrupt to vcpu. 3797 * 3798 * Case 2: vcpu exits to root mode and is still 3799 * runnable. PIR will be synced to vIRR before the 3800 * next vcpu entry. Sending a notification event in 3801 * this case has no effect, as vcpu is not in root 3802 * mode. 3803 * 3804 * Case 3: vcpu exits to root mode and is blocked. 3805 * vcpu_block() has already synced PIR to vIRR and 3806 * never blocks vcpu if vIRR is not cleared. Therefore, 3807 * a blocked vcpu here does not wait for any requested 3808 * interrupts in PIR, and sending a notification event 3809 * which has no effect is safe here. 3810 */ 3811 3812 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3813 return true; 3814 } 3815 #endif 3816 return false; 3817 } 3818 3819 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3820 int vector) 3821 { 3822 struct vcpu_vmx *vmx = to_vmx(vcpu); 3823 3824 if (is_guest_mode(vcpu) && 3825 vector == vmx->nested.posted_intr_nv) { 3826 /* 3827 * If a posted intr is not recognized by hardware, 3828 * we will accomplish it in the next vmentry. 3829 */ 3830 vmx->nested.pi_pending = true; 3831 kvm_make_request(KVM_REQ_EVENT, vcpu); 3832 /* the PIR and ON have been set by L1. */ 3833 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3834 kvm_vcpu_kick(vcpu); 3835 return 0; 3836 } 3837 return -1; 3838 } 3839 /* 3840 * Send interrupt to vcpu via posted interrupt way. 3841 * 1. If target vcpu is running(non-root mode), send posted interrupt 3842 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3843 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3844 * interrupt from PIR in next vmentry. 3845 */ 3846 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3847 { 3848 struct vcpu_vmx *vmx = to_vmx(vcpu); 3849 int r; 3850 3851 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3852 if (!r) 3853 return; 3854 3855 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3856 return; 3857 3858 /* If a previous notification has sent the IPI, nothing to do. */ 3859 if (pi_test_and_set_on(&vmx->pi_desc)) 3860 return; 3861 3862 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3863 kvm_vcpu_kick(vcpu); 3864 } 3865 3866 /* 3867 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3868 * will not change in the lifetime of the guest. 3869 * Note that host-state that does change is set elsewhere. E.g., host-state 3870 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3871 */ 3872 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3873 { 3874 u32 low32, high32; 3875 unsigned long tmpl; 3876 unsigned long cr0, cr3, cr4; 3877 3878 cr0 = read_cr0(); 3879 WARN_ON(cr0 & X86_CR0_TS); 3880 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3881 3882 /* 3883 * Save the most likely value for this task's CR3 in the VMCS. 3884 * We can't use __get_current_cr3_fast() because we're not atomic. 3885 */ 3886 cr3 = __read_cr3(); 3887 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3888 vmx->loaded_vmcs->host_state.cr3 = cr3; 3889 3890 /* Save the most likely value for this task's CR4 in the VMCS. */ 3891 cr4 = cr4_read_shadow(); 3892 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3893 vmx->loaded_vmcs->host_state.cr4 = cr4; 3894 3895 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3896 #ifdef CONFIG_X86_64 3897 /* 3898 * Load null selectors, so we can avoid reloading them in 3899 * vmx_prepare_switch_to_host(), in case userspace uses 3900 * the null selectors too (the expected case). 3901 */ 3902 vmcs_write16(HOST_DS_SELECTOR, 0); 3903 vmcs_write16(HOST_ES_SELECTOR, 0); 3904 #else 3905 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3906 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3907 #endif 3908 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3909 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3910 3911 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3912 3913 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3914 3915 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3916 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3917 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3918 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3919 3920 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3921 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3922 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3923 } 3924 3925 if (cpu_has_load_ia32_efer()) 3926 vmcs_write64(HOST_IA32_EFER, host_efer); 3927 } 3928 3929 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3930 { 3931 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3932 if (enable_ept) 3933 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3934 if (is_guest_mode(&vmx->vcpu)) 3935 vmx->vcpu.arch.cr4_guest_owned_bits &= 3936 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3937 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3938 } 3939 3940 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3941 { 3942 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3943 3944 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3945 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3946 3947 if (!enable_vnmi) 3948 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3949 3950 if (!enable_preemption_timer) 3951 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3952 3953 return pin_based_exec_ctrl; 3954 } 3955 3956 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3957 { 3958 struct vcpu_vmx *vmx = to_vmx(vcpu); 3959 3960 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3961 if (cpu_has_secondary_exec_ctrls()) { 3962 if (kvm_vcpu_apicv_active(vcpu)) 3963 secondary_exec_controls_setbit(vmx, 3964 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3965 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3966 else 3967 secondary_exec_controls_clearbit(vmx, 3968 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3969 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3970 } 3971 3972 if (cpu_has_vmx_msr_bitmap()) 3973 vmx_update_msr_bitmap(vcpu); 3974 } 3975 3976 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3977 { 3978 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3979 3980 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3981 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3982 3983 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3984 exec_control &= ~CPU_BASED_TPR_SHADOW; 3985 #ifdef CONFIG_X86_64 3986 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3987 CPU_BASED_CR8_LOAD_EXITING; 3988 #endif 3989 } 3990 if (!enable_ept) 3991 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3992 CPU_BASED_CR3_LOAD_EXITING | 3993 CPU_BASED_INVLPG_EXITING; 3994 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3995 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3996 CPU_BASED_MONITOR_EXITING); 3997 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3998 exec_control &= ~CPU_BASED_HLT_EXITING; 3999 return exec_control; 4000 } 4001 4002 4003 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 4004 { 4005 struct kvm_vcpu *vcpu = &vmx->vcpu; 4006 4007 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 4008 4009 if (pt_mode == PT_MODE_SYSTEM) 4010 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 4011 if (!cpu_need_virtualize_apic_accesses(vcpu)) 4012 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4013 if (vmx->vpid == 0) 4014 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4015 if (!enable_ept) { 4016 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4017 enable_unrestricted_guest = 0; 4018 } 4019 if (!enable_unrestricted_guest) 4020 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4021 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4022 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4023 if (!kvm_vcpu_apicv_active(vcpu)) 4024 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4025 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4026 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4027 4028 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4029 * in vmx_set_cr4. */ 4030 exec_control &= ~SECONDARY_EXEC_DESC; 4031 4032 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4033 (handle_vmptrld). 4034 We can NOT enable shadow_vmcs here because we don't have yet 4035 a current VMCS12 4036 */ 4037 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4038 4039 if (!enable_pml) 4040 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4041 4042 if (vmx_xsaves_supported()) { 4043 /* Exposing XSAVES only when XSAVE is exposed */ 4044 bool xsaves_enabled = 4045 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4046 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4047 4048 vcpu->arch.xsaves_enabled = xsaves_enabled; 4049 4050 if (!xsaves_enabled) 4051 exec_control &= ~SECONDARY_EXEC_XSAVES; 4052 4053 if (nested) { 4054 if (xsaves_enabled) 4055 vmx->nested.msrs.secondary_ctls_high |= 4056 SECONDARY_EXEC_XSAVES; 4057 else 4058 vmx->nested.msrs.secondary_ctls_high &= 4059 ~SECONDARY_EXEC_XSAVES; 4060 } 4061 } 4062 4063 if (vmx_rdtscp_supported()) { 4064 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4065 if (!rdtscp_enabled) 4066 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4067 4068 if (nested) { 4069 if (rdtscp_enabled) 4070 vmx->nested.msrs.secondary_ctls_high |= 4071 SECONDARY_EXEC_RDTSCP; 4072 else 4073 vmx->nested.msrs.secondary_ctls_high &= 4074 ~SECONDARY_EXEC_RDTSCP; 4075 } 4076 } 4077 4078 if (vmx_invpcid_supported()) { 4079 /* Exposing INVPCID only when PCID is exposed */ 4080 bool invpcid_enabled = 4081 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4082 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4083 4084 if (!invpcid_enabled) { 4085 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4086 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4087 } 4088 4089 if (nested) { 4090 if (invpcid_enabled) 4091 vmx->nested.msrs.secondary_ctls_high |= 4092 SECONDARY_EXEC_ENABLE_INVPCID; 4093 else 4094 vmx->nested.msrs.secondary_ctls_high &= 4095 ~SECONDARY_EXEC_ENABLE_INVPCID; 4096 } 4097 } 4098 4099 if (vmx_rdrand_supported()) { 4100 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4101 if (rdrand_enabled) 4102 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4103 4104 if (nested) { 4105 if (rdrand_enabled) 4106 vmx->nested.msrs.secondary_ctls_high |= 4107 SECONDARY_EXEC_RDRAND_EXITING; 4108 else 4109 vmx->nested.msrs.secondary_ctls_high &= 4110 ~SECONDARY_EXEC_RDRAND_EXITING; 4111 } 4112 } 4113 4114 if (vmx_rdseed_supported()) { 4115 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4116 if (rdseed_enabled) 4117 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4118 4119 if (nested) { 4120 if (rdseed_enabled) 4121 vmx->nested.msrs.secondary_ctls_high |= 4122 SECONDARY_EXEC_RDSEED_EXITING; 4123 else 4124 vmx->nested.msrs.secondary_ctls_high &= 4125 ~SECONDARY_EXEC_RDSEED_EXITING; 4126 } 4127 } 4128 4129 if (vmx_waitpkg_supported()) { 4130 bool waitpkg_enabled = 4131 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4132 4133 if (!waitpkg_enabled) 4134 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4135 4136 if (nested) { 4137 if (waitpkg_enabled) 4138 vmx->nested.msrs.secondary_ctls_high |= 4139 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4140 else 4141 vmx->nested.msrs.secondary_ctls_high &= 4142 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4143 } 4144 } 4145 4146 vmx->secondary_exec_control = exec_control; 4147 } 4148 4149 static void ept_set_mmio_spte_mask(void) 4150 { 4151 /* 4152 * EPT Misconfigurations can be generated if the value of bits 2:0 4153 * of an EPT paging-structure entry is 110b (write/execute). 4154 */ 4155 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4156 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4157 } 4158 4159 #define VMX_XSS_EXIT_BITMAP 0 4160 4161 /* 4162 * Noting that the initialization of Guest-state Area of VMCS is in 4163 * vmx_vcpu_reset(). 4164 */ 4165 static void init_vmcs(struct vcpu_vmx *vmx) 4166 { 4167 if (nested) 4168 nested_vmx_set_vmcs_shadowing_bitmap(); 4169 4170 if (cpu_has_vmx_msr_bitmap()) 4171 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4172 4173 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4174 4175 /* Control */ 4176 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4177 4178 exec_controls_set(vmx, vmx_exec_control(vmx)); 4179 4180 if (cpu_has_secondary_exec_ctrls()) { 4181 vmx_compute_secondary_exec_control(vmx); 4182 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4183 } 4184 4185 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4186 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4187 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4188 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4189 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4190 4191 vmcs_write16(GUEST_INTR_STATUS, 0); 4192 4193 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4194 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4195 } 4196 4197 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4198 vmcs_write32(PLE_GAP, ple_gap); 4199 vmx->ple_window = ple_window; 4200 vmx->ple_window_dirty = true; 4201 } 4202 4203 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4204 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4205 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4206 4207 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4208 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4209 vmx_set_constant_host_state(vmx); 4210 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4211 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4212 4213 if (cpu_has_vmx_vmfunc()) 4214 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4215 4216 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4217 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4218 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4219 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4220 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4221 4222 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4223 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4224 4225 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4226 4227 /* 22.2.1, 20.8.1 */ 4228 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4229 4230 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4231 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4232 4233 set_cr4_guest_host_mask(vmx); 4234 4235 if (vmx->vpid != 0) 4236 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4237 4238 if (vmx_xsaves_supported()) 4239 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4240 4241 if (enable_pml) { 4242 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4243 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4244 } 4245 4246 if (cpu_has_vmx_encls_vmexit()) 4247 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4248 4249 if (pt_mode == PT_MODE_HOST_GUEST) { 4250 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4251 /* Bit[6~0] are forced to 1, writes are ignored. */ 4252 vmx->pt_desc.guest.output_mask = 0x7F; 4253 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4254 } 4255 } 4256 4257 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4258 { 4259 struct vcpu_vmx *vmx = to_vmx(vcpu); 4260 struct msr_data apic_base_msr; 4261 u64 cr0; 4262 4263 vmx->rmode.vm86_active = 0; 4264 vmx->spec_ctrl = 0; 4265 4266 vmx->msr_ia32_umwait_control = 0; 4267 4268 vcpu->arch.microcode_version = 0x100000000ULL; 4269 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4270 vmx->hv_deadline_tsc = -1; 4271 kvm_set_cr8(vcpu, 0); 4272 4273 if (!init_event) { 4274 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4275 MSR_IA32_APICBASE_ENABLE; 4276 if (kvm_vcpu_is_reset_bsp(vcpu)) 4277 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4278 apic_base_msr.host_initiated = true; 4279 kvm_set_apic_base(vcpu, &apic_base_msr); 4280 } 4281 4282 vmx_segment_cache_clear(vmx); 4283 4284 seg_setup(VCPU_SREG_CS); 4285 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4286 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4287 4288 seg_setup(VCPU_SREG_DS); 4289 seg_setup(VCPU_SREG_ES); 4290 seg_setup(VCPU_SREG_FS); 4291 seg_setup(VCPU_SREG_GS); 4292 seg_setup(VCPU_SREG_SS); 4293 4294 vmcs_write16(GUEST_TR_SELECTOR, 0); 4295 vmcs_writel(GUEST_TR_BASE, 0); 4296 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4297 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4298 4299 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4300 vmcs_writel(GUEST_LDTR_BASE, 0); 4301 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4302 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4303 4304 if (!init_event) { 4305 vmcs_write32(GUEST_SYSENTER_CS, 0); 4306 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4307 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4308 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4309 } 4310 4311 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4312 kvm_rip_write(vcpu, 0xfff0); 4313 4314 vmcs_writel(GUEST_GDTR_BASE, 0); 4315 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4316 4317 vmcs_writel(GUEST_IDTR_BASE, 0); 4318 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4319 4320 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4321 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4322 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4323 if (kvm_mpx_supported()) 4324 vmcs_write64(GUEST_BNDCFGS, 0); 4325 4326 setup_msrs(vmx); 4327 4328 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4329 4330 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4331 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4332 if (cpu_need_tpr_shadow(vcpu)) 4333 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4334 __pa(vcpu->arch.apic->regs)); 4335 vmcs_write32(TPR_THRESHOLD, 0); 4336 } 4337 4338 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4339 4340 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4341 vmx->vcpu.arch.cr0 = cr0; 4342 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4343 vmx_set_cr4(vcpu, 0); 4344 vmx_set_efer(vcpu, 0); 4345 4346 update_exception_bitmap(vcpu); 4347 4348 vpid_sync_context(vmx->vpid); 4349 if (init_event) 4350 vmx_clear_hlt(vcpu); 4351 } 4352 4353 static void enable_irq_window(struct kvm_vcpu *vcpu) 4354 { 4355 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING); 4356 } 4357 4358 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4359 { 4360 if (!enable_vnmi || 4361 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4362 enable_irq_window(vcpu); 4363 return; 4364 } 4365 4366 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING); 4367 } 4368 4369 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4370 { 4371 struct vcpu_vmx *vmx = to_vmx(vcpu); 4372 uint32_t intr; 4373 int irq = vcpu->arch.interrupt.nr; 4374 4375 trace_kvm_inj_virq(irq); 4376 4377 ++vcpu->stat.irq_injections; 4378 if (vmx->rmode.vm86_active) { 4379 int inc_eip = 0; 4380 if (vcpu->arch.interrupt.soft) 4381 inc_eip = vcpu->arch.event_exit_inst_len; 4382 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4383 return; 4384 } 4385 intr = irq | INTR_INFO_VALID_MASK; 4386 if (vcpu->arch.interrupt.soft) { 4387 intr |= INTR_TYPE_SOFT_INTR; 4388 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4389 vmx->vcpu.arch.event_exit_inst_len); 4390 } else 4391 intr |= INTR_TYPE_EXT_INTR; 4392 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4393 4394 vmx_clear_hlt(vcpu); 4395 } 4396 4397 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4398 { 4399 struct vcpu_vmx *vmx = to_vmx(vcpu); 4400 4401 if (!enable_vnmi) { 4402 /* 4403 * Tracking the NMI-blocked state in software is built upon 4404 * finding the next open IRQ window. This, in turn, depends on 4405 * well-behaving guests: They have to keep IRQs disabled at 4406 * least as long as the NMI handler runs. Otherwise we may 4407 * cause NMI nesting, maybe breaking the guest. But as this is 4408 * highly unlikely, we can live with the residual risk. 4409 */ 4410 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4411 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4412 } 4413 4414 ++vcpu->stat.nmi_injections; 4415 vmx->loaded_vmcs->nmi_known_unmasked = false; 4416 4417 if (vmx->rmode.vm86_active) { 4418 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4419 return; 4420 } 4421 4422 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4423 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4424 4425 vmx_clear_hlt(vcpu); 4426 } 4427 4428 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4429 { 4430 struct vcpu_vmx *vmx = to_vmx(vcpu); 4431 bool masked; 4432 4433 if (!enable_vnmi) 4434 return vmx->loaded_vmcs->soft_vnmi_blocked; 4435 if (vmx->loaded_vmcs->nmi_known_unmasked) 4436 return false; 4437 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4438 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4439 return masked; 4440 } 4441 4442 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4443 { 4444 struct vcpu_vmx *vmx = to_vmx(vcpu); 4445 4446 if (!enable_vnmi) { 4447 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4448 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4449 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4450 } 4451 } else { 4452 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4453 if (masked) 4454 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4455 GUEST_INTR_STATE_NMI); 4456 else 4457 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4458 GUEST_INTR_STATE_NMI); 4459 } 4460 } 4461 4462 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4463 { 4464 if (to_vmx(vcpu)->nested.nested_run_pending) 4465 return 0; 4466 4467 if (!enable_vnmi && 4468 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4469 return 0; 4470 4471 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4472 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4473 | GUEST_INTR_STATE_NMI)); 4474 } 4475 4476 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4477 { 4478 return (!to_vmx(vcpu)->nested.nested_run_pending && 4479 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4480 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4481 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4482 } 4483 4484 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4485 { 4486 int ret; 4487 4488 if (enable_unrestricted_guest) 4489 return 0; 4490 4491 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4492 PAGE_SIZE * 3); 4493 if (ret) 4494 return ret; 4495 to_kvm_vmx(kvm)->tss_addr = addr; 4496 return init_rmode_tss(kvm); 4497 } 4498 4499 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4500 { 4501 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4502 return 0; 4503 } 4504 4505 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4506 { 4507 switch (vec) { 4508 case BP_VECTOR: 4509 /* 4510 * Update instruction length as we may reinject the exception 4511 * from user space while in guest debugging mode. 4512 */ 4513 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4514 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4515 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4516 return false; 4517 /* fall through */ 4518 case DB_VECTOR: 4519 if (vcpu->guest_debug & 4520 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4521 return false; 4522 /* fall through */ 4523 case DE_VECTOR: 4524 case OF_VECTOR: 4525 case BR_VECTOR: 4526 case UD_VECTOR: 4527 case DF_VECTOR: 4528 case SS_VECTOR: 4529 case GP_VECTOR: 4530 case MF_VECTOR: 4531 return true; 4532 break; 4533 } 4534 return false; 4535 } 4536 4537 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4538 int vec, u32 err_code) 4539 { 4540 /* 4541 * Instruction with address size override prefix opcode 0x67 4542 * Cause the #SS fault with 0 error code in VM86 mode. 4543 */ 4544 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4545 if (kvm_emulate_instruction(vcpu, 0)) { 4546 if (vcpu->arch.halt_request) { 4547 vcpu->arch.halt_request = 0; 4548 return kvm_vcpu_halt(vcpu); 4549 } 4550 return 1; 4551 } 4552 return 0; 4553 } 4554 4555 /* 4556 * Forward all other exceptions that are valid in real mode. 4557 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4558 * the required debugging infrastructure rework. 4559 */ 4560 kvm_queue_exception(vcpu, vec); 4561 return 1; 4562 } 4563 4564 /* 4565 * Trigger machine check on the host. We assume all the MSRs are already set up 4566 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4567 * We pass a fake environment to the machine check handler because we want 4568 * the guest to be always treated like user space, no matter what context 4569 * it used internally. 4570 */ 4571 static void kvm_machine_check(void) 4572 { 4573 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4574 struct pt_regs regs = { 4575 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4576 .flags = X86_EFLAGS_IF, 4577 }; 4578 4579 do_machine_check(®s, 0); 4580 #endif 4581 } 4582 4583 static int handle_machine_check(struct kvm_vcpu *vcpu) 4584 { 4585 /* handled by vmx_vcpu_run() */ 4586 return 1; 4587 } 4588 4589 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4590 { 4591 struct vcpu_vmx *vmx = to_vmx(vcpu); 4592 struct kvm_run *kvm_run = vcpu->run; 4593 u32 intr_info, ex_no, error_code; 4594 unsigned long cr2, rip, dr6; 4595 u32 vect_info; 4596 4597 vect_info = vmx->idt_vectoring_info; 4598 intr_info = vmx->exit_intr_info; 4599 4600 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4601 return 1; /* handled by handle_exception_nmi_irqoff() */ 4602 4603 if (is_invalid_opcode(intr_info)) 4604 return handle_ud(vcpu); 4605 4606 error_code = 0; 4607 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4608 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4609 4610 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4611 WARN_ON_ONCE(!enable_vmware_backdoor); 4612 4613 /* 4614 * VMware backdoor emulation on #GP interception only handles 4615 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4616 * error code on #GP. 4617 */ 4618 if (error_code) { 4619 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4620 return 1; 4621 } 4622 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4623 } 4624 4625 /* 4626 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4627 * MMIO, it is better to report an internal error. 4628 * See the comments in vmx_handle_exit. 4629 */ 4630 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4631 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4632 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4633 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4634 vcpu->run->internal.ndata = 3; 4635 vcpu->run->internal.data[0] = vect_info; 4636 vcpu->run->internal.data[1] = intr_info; 4637 vcpu->run->internal.data[2] = error_code; 4638 return 0; 4639 } 4640 4641 if (is_page_fault(intr_info)) { 4642 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4643 /* EPT won't cause page fault directly */ 4644 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4645 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4646 } 4647 4648 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4649 4650 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4651 return handle_rmode_exception(vcpu, ex_no, error_code); 4652 4653 switch (ex_no) { 4654 case AC_VECTOR: 4655 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4656 return 1; 4657 case DB_VECTOR: 4658 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4659 if (!(vcpu->guest_debug & 4660 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4661 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4662 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4663 if (is_icebp(intr_info)) 4664 WARN_ON(!skip_emulated_instruction(vcpu)); 4665 4666 kvm_queue_exception(vcpu, DB_VECTOR); 4667 return 1; 4668 } 4669 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4670 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4671 /* fall through */ 4672 case BP_VECTOR: 4673 /* 4674 * Update instruction length as we may reinject #BP from 4675 * user space while in guest debugging mode. Reading it for 4676 * #DB as well causes no harm, it is not used in that case. 4677 */ 4678 vmx->vcpu.arch.event_exit_inst_len = 4679 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4680 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4681 rip = kvm_rip_read(vcpu); 4682 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4683 kvm_run->debug.arch.exception = ex_no; 4684 break; 4685 default: 4686 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4687 kvm_run->ex.exception = ex_no; 4688 kvm_run->ex.error_code = error_code; 4689 break; 4690 } 4691 return 0; 4692 } 4693 4694 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4695 { 4696 ++vcpu->stat.irq_exits; 4697 return 1; 4698 } 4699 4700 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4701 { 4702 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4703 vcpu->mmio_needed = 0; 4704 return 0; 4705 } 4706 4707 static int handle_io(struct kvm_vcpu *vcpu) 4708 { 4709 unsigned long exit_qualification; 4710 int size, in, string; 4711 unsigned port; 4712 4713 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4714 string = (exit_qualification & 16) != 0; 4715 4716 ++vcpu->stat.io_exits; 4717 4718 if (string) 4719 return kvm_emulate_instruction(vcpu, 0); 4720 4721 port = exit_qualification >> 16; 4722 size = (exit_qualification & 7) + 1; 4723 in = (exit_qualification & 8) != 0; 4724 4725 return kvm_fast_pio(vcpu, size, port, in); 4726 } 4727 4728 static void 4729 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4730 { 4731 /* 4732 * Patch in the VMCALL instruction: 4733 */ 4734 hypercall[0] = 0x0f; 4735 hypercall[1] = 0x01; 4736 hypercall[2] = 0xc1; 4737 } 4738 4739 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4740 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4741 { 4742 if (is_guest_mode(vcpu)) { 4743 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4744 unsigned long orig_val = val; 4745 4746 /* 4747 * We get here when L2 changed cr0 in a way that did not change 4748 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4749 * but did change L0 shadowed bits. So we first calculate the 4750 * effective cr0 value that L1 would like to write into the 4751 * hardware. It consists of the L2-owned bits from the new 4752 * value combined with the L1-owned bits from L1's guest_cr0. 4753 */ 4754 val = (val & ~vmcs12->cr0_guest_host_mask) | 4755 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4756 4757 if (!nested_guest_cr0_valid(vcpu, val)) 4758 return 1; 4759 4760 if (kvm_set_cr0(vcpu, val)) 4761 return 1; 4762 vmcs_writel(CR0_READ_SHADOW, orig_val); 4763 return 0; 4764 } else { 4765 if (to_vmx(vcpu)->nested.vmxon && 4766 !nested_host_cr0_valid(vcpu, val)) 4767 return 1; 4768 4769 return kvm_set_cr0(vcpu, val); 4770 } 4771 } 4772 4773 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4774 { 4775 if (is_guest_mode(vcpu)) { 4776 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4777 unsigned long orig_val = val; 4778 4779 /* analogously to handle_set_cr0 */ 4780 val = (val & ~vmcs12->cr4_guest_host_mask) | 4781 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4782 if (kvm_set_cr4(vcpu, val)) 4783 return 1; 4784 vmcs_writel(CR4_READ_SHADOW, orig_val); 4785 return 0; 4786 } else 4787 return kvm_set_cr4(vcpu, val); 4788 } 4789 4790 static int handle_desc(struct kvm_vcpu *vcpu) 4791 { 4792 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4793 return kvm_emulate_instruction(vcpu, 0); 4794 } 4795 4796 static int handle_cr(struct kvm_vcpu *vcpu) 4797 { 4798 unsigned long exit_qualification, val; 4799 int cr; 4800 int reg; 4801 int err; 4802 int ret; 4803 4804 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4805 cr = exit_qualification & 15; 4806 reg = (exit_qualification >> 8) & 15; 4807 switch ((exit_qualification >> 4) & 3) { 4808 case 0: /* mov to cr */ 4809 val = kvm_register_readl(vcpu, reg); 4810 trace_kvm_cr_write(cr, val); 4811 switch (cr) { 4812 case 0: 4813 err = handle_set_cr0(vcpu, val); 4814 return kvm_complete_insn_gp(vcpu, err); 4815 case 3: 4816 WARN_ON_ONCE(enable_unrestricted_guest); 4817 err = kvm_set_cr3(vcpu, val); 4818 return kvm_complete_insn_gp(vcpu, err); 4819 case 4: 4820 err = handle_set_cr4(vcpu, val); 4821 return kvm_complete_insn_gp(vcpu, err); 4822 case 8: { 4823 u8 cr8_prev = kvm_get_cr8(vcpu); 4824 u8 cr8 = (u8)val; 4825 err = kvm_set_cr8(vcpu, cr8); 4826 ret = kvm_complete_insn_gp(vcpu, err); 4827 if (lapic_in_kernel(vcpu)) 4828 return ret; 4829 if (cr8_prev <= cr8) 4830 return ret; 4831 /* 4832 * TODO: we might be squashing a 4833 * KVM_GUESTDBG_SINGLESTEP-triggered 4834 * KVM_EXIT_DEBUG here. 4835 */ 4836 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4837 return 0; 4838 } 4839 } 4840 break; 4841 case 2: /* clts */ 4842 WARN_ONCE(1, "Guest should always own CR0.TS"); 4843 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4844 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4845 return kvm_skip_emulated_instruction(vcpu); 4846 case 1: /*mov from cr*/ 4847 switch (cr) { 4848 case 3: 4849 WARN_ON_ONCE(enable_unrestricted_guest); 4850 val = kvm_read_cr3(vcpu); 4851 kvm_register_write(vcpu, reg, val); 4852 trace_kvm_cr_read(cr, val); 4853 return kvm_skip_emulated_instruction(vcpu); 4854 case 8: 4855 val = kvm_get_cr8(vcpu); 4856 kvm_register_write(vcpu, reg, val); 4857 trace_kvm_cr_read(cr, val); 4858 return kvm_skip_emulated_instruction(vcpu); 4859 } 4860 break; 4861 case 3: /* lmsw */ 4862 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4863 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4864 kvm_lmsw(vcpu, val); 4865 4866 return kvm_skip_emulated_instruction(vcpu); 4867 default: 4868 break; 4869 } 4870 vcpu->run->exit_reason = 0; 4871 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4872 (int)(exit_qualification >> 4) & 3, cr); 4873 return 0; 4874 } 4875 4876 static int handle_dr(struct kvm_vcpu *vcpu) 4877 { 4878 unsigned long exit_qualification; 4879 int dr, dr7, reg; 4880 4881 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4882 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4883 4884 /* First, if DR does not exist, trigger UD */ 4885 if (!kvm_require_dr(vcpu, dr)) 4886 return 1; 4887 4888 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4889 if (!kvm_require_cpl(vcpu, 0)) 4890 return 1; 4891 dr7 = vmcs_readl(GUEST_DR7); 4892 if (dr7 & DR7_GD) { 4893 /* 4894 * As the vm-exit takes precedence over the debug trap, we 4895 * need to emulate the latter, either for the host or the 4896 * guest debugging itself. 4897 */ 4898 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4899 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4900 vcpu->run->debug.arch.dr7 = dr7; 4901 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4902 vcpu->run->debug.arch.exception = DB_VECTOR; 4903 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4904 return 0; 4905 } else { 4906 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4907 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4908 kvm_queue_exception(vcpu, DB_VECTOR); 4909 return 1; 4910 } 4911 } 4912 4913 if (vcpu->guest_debug == 0) { 4914 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4915 4916 /* 4917 * No more DR vmexits; force a reload of the debug registers 4918 * and reenter on this instruction. The next vmexit will 4919 * retrieve the full state of the debug registers. 4920 */ 4921 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4922 return 1; 4923 } 4924 4925 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4926 if (exit_qualification & TYPE_MOV_FROM_DR) { 4927 unsigned long val; 4928 4929 if (kvm_get_dr(vcpu, dr, &val)) 4930 return 1; 4931 kvm_register_write(vcpu, reg, val); 4932 } else 4933 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4934 return 1; 4935 4936 return kvm_skip_emulated_instruction(vcpu); 4937 } 4938 4939 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4940 { 4941 return vcpu->arch.dr6; 4942 } 4943 4944 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4945 { 4946 } 4947 4948 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4949 { 4950 get_debugreg(vcpu->arch.db[0], 0); 4951 get_debugreg(vcpu->arch.db[1], 1); 4952 get_debugreg(vcpu->arch.db[2], 2); 4953 get_debugreg(vcpu->arch.db[3], 3); 4954 get_debugreg(vcpu->arch.dr6, 6); 4955 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4956 4957 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4958 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4959 } 4960 4961 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4962 { 4963 vmcs_writel(GUEST_DR7, val); 4964 } 4965 4966 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4967 { 4968 kvm_apic_update_ppr(vcpu); 4969 return 1; 4970 } 4971 4972 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4973 { 4974 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_INTR_PENDING); 4975 4976 kvm_make_request(KVM_REQ_EVENT, vcpu); 4977 4978 ++vcpu->stat.irq_window_exits; 4979 return 1; 4980 } 4981 4982 static int handle_vmcall(struct kvm_vcpu *vcpu) 4983 { 4984 return kvm_emulate_hypercall(vcpu); 4985 } 4986 4987 static int handle_invd(struct kvm_vcpu *vcpu) 4988 { 4989 return kvm_emulate_instruction(vcpu, 0); 4990 } 4991 4992 static int handle_invlpg(struct kvm_vcpu *vcpu) 4993 { 4994 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4995 4996 kvm_mmu_invlpg(vcpu, exit_qualification); 4997 return kvm_skip_emulated_instruction(vcpu); 4998 } 4999 5000 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5001 { 5002 int err; 5003 5004 err = kvm_rdpmc(vcpu); 5005 return kvm_complete_insn_gp(vcpu, err); 5006 } 5007 5008 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5009 { 5010 return kvm_emulate_wbinvd(vcpu); 5011 } 5012 5013 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5014 { 5015 u64 new_bv = kvm_read_edx_eax(vcpu); 5016 u32 index = kvm_rcx_read(vcpu); 5017 5018 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5019 return kvm_skip_emulated_instruction(vcpu); 5020 return 1; 5021 } 5022 5023 static int handle_apic_access(struct kvm_vcpu *vcpu) 5024 { 5025 if (likely(fasteoi)) { 5026 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5027 int access_type, offset; 5028 5029 access_type = exit_qualification & APIC_ACCESS_TYPE; 5030 offset = exit_qualification & APIC_ACCESS_OFFSET; 5031 /* 5032 * Sane guest uses MOV to write EOI, with written value 5033 * not cared. So make a short-circuit here by avoiding 5034 * heavy instruction emulation. 5035 */ 5036 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5037 (offset == APIC_EOI)) { 5038 kvm_lapic_set_eoi(vcpu); 5039 return kvm_skip_emulated_instruction(vcpu); 5040 } 5041 } 5042 return kvm_emulate_instruction(vcpu, 0); 5043 } 5044 5045 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5046 { 5047 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5048 int vector = exit_qualification & 0xff; 5049 5050 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5051 kvm_apic_set_eoi_accelerated(vcpu, vector); 5052 return 1; 5053 } 5054 5055 static int handle_apic_write(struct kvm_vcpu *vcpu) 5056 { 5057 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5058 u32 offset = exit_qualification & 0xfff; 5059 5060 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5061 kvm_apic_write_nodecode(vcpu, offset); 5062 return 1; 5063 } 5064 5065 static int handle_task_switch(struct kvm_vcpu *vcpu) 5066 { 5067 struct vcpu_vmx *vmx = to_vmx(vcpu); 5068 unsigned long exit_qualification; 5069 bool has_error_code = false; 5070 u32 error_code = 0; 5071 u16 tss_selector; 5072 int reason, type, idt_v, idt_index; 5073 5074 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5075 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5076 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5077 5078 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5079 5080 reason = (u32)exit_qualification >> 30; 5081 if (reason == TASK_SWITCH_GATE && idt_v) { 5082 switch (type) { 5083 case INTR_TYPE_NMI_INTR: 5084 vcpu->arch.nmi_injected = false; 5085 vmx_set_nmi_mask(vcpu, true); 5086 break; 5087 case INTR_TYPE_EXT_INTR: 5088 case INTR_TYPE_SOFT_INTR: 5089 kvm_clear_interrupt_queue(vcpu); 5090 break; 5091 case INTR_TYPE_HARD_EXCEPTION: 5092 if (vmx->idt_vectoring_info & 5093 VECTORING_INFO_DELIVER_CODE_MASK) { 5094 has_error_code = true; 5095 error_code = 5096 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5097 } 5098 /* fall through */ 5099 case INTR_TYPE_SOFT_EXCEPTION: 5100 kvm_clear_exception_queue(vcpu); 5101 break; 5102 default: 5103 break; 5104 } 5105 } 5106 tss_selector = exit_qualification; 5107 5108 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5109 type != INTR_TYPE_EXT_INTR && 5110 type != INTR_TYPE_NMI_INTR)) 5111 WARN_ON(!skip_emulated_instruction(vcpu)); 5112 5113 /* 5114 * TODO: What about debug traps on tss switch? 5115 * Are we supposed to inject them and update dr6? 5116 */ 5117 return kvm_task_switch(vcpu, tss_selector, 5118 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5119 reason, has_error_code, error_code); 5120 } 5121 5122 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5123 { 5124 unsigned long exit_qualification; 5125 gpa_t gpa; 5126 u64 error_code; 5127 5128 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5129 5130 /* 5131 * EPT violation happened while executing iret from NMI, 5132 * "blocked by NMI" bit has to be set before next VM entry. 5133 * There are errata that may cause this bit to not be set: 5134 * AAK134, BY25. 5135 */ 5136 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5137 enable_vnmi && 5138 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5139 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5140 5141 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5142 trace_kvm_page_fault(gpa, exit_qualification); 5143 5144 /* Is it a read fault? */ 5145 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5146 ? PFERR_USER_MASK : 0; 5147 /* Is it a write fault? */ 5148 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5149 ? PFERR_WRITE_MASK : 0; 5150 /* Is it a fetch fault? */ 5151 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5152 ? PFERR_FETCH_MASK : 0; 5153 /* ept page table entry is present? */ 5154 error_code |= (exit_qualification & 5155 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5156 EPT_VIOLATION_EXECUTABLE)) 5157 ? PFERR_PRESENT_MASK : 0; 5158 5159 error_code |= (exit_qualification & 0x100) != 0 ? 5160 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5161 5162 vcpu->arch.exit_qualification = exit_qualification; 5163 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5164 } 5165 5166 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5167 { 5168 gpa_t gpa; 5169 5170 /* 5171 * A nested guest cannot optimize MMIO vmexits, because we have an 5172 * nGPA here instead of the required GPA. 5173 */ 5174 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5175 if (!is_guest_mode(vcpu) && 5176 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5177 trace_kvm_fast_mmio(gpa); 5178 return kvm_skip_emulated_instruction(vcpu); 5179 } 5180 5181 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5182 } 5183 5184 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5185 { 5186 WARN_ON_ONCE(!enable_vnmi); 5187 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_VIRTUAL_NMI_PENDING); 5188 ++vcpu->stat.nmi_window_exits; 5189 kvm_make_request(KVM_REQ_EVENT, vcpu); 5190 5191 return 1; 5192 } 5193 5194 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5195 { 5196 struct vcpu_vmx *vmx = to_vmx(vcpu); 5197 bool intr_window_requested; 5198 unsigned count = 130; 5199 5200 /* 5201 * We should never reach the point where we are emulating L2 5202 * due to invalid guest state as that means we incorrectly 5203 * allowed a nested VMEntry with an invalid vmcs12. 5204 */ 5205 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5206 5207 intr_window_requested = exec_controls_get(vmx) & 5208 CPU_BASED_VIRTUAL_INTR_PENDING; 5209 5210 while (vmx->emulation_required && count-- != 0) { 5211 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5212 return handle_interrupt_window(&vmx->vcpu); 5213 5214 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5215 return 1; 5216 5217 if (!kvm_emulate_instruction(vcpu, 0)) 5218 return 0; 5219 5220 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5221 vcpu->arch.exception.pending) { 5222 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5223 vcpu->run->internal.suberror = 5224 KVM_INTERNAL_ERROR_EMULATION; 5225 vcpu->run->internal.ndata = 0; 5226 return 0; 5227 } 5228 5229 if (vcpu->arch.halt_request) { 5230 vcpu->arch.halt_request = 0; 5231 return kvm_vcpu_halt(vcpu); 5232 } 5233 5234 /* 5235 * Note, return 1 and not 0, vcpu_run() is responsible for 5236 * morphing the pending signal into the proper return code. 5237 */ 5238 if (signal_pending(current)) 5239 return 1; 5240 5241 if (need_resched()) 5242 schedule(); 5243 } 5244 5245 return 1; 5246 } 5247 5248 static void grow_ple_window(struct kvm_vcpu *vcpu) 5249 { 5250 struct vcpu_vmx *vmx = to_vmx(vcpu); 5251 unsigned int old = vmx->ple_window; 5252 5253 vmx->ple_window = __grow_ple_window(old, ple_window, 5254 ple_window_grow, 5255 ple_window_max); 5256 5257 if (vmx->ple_window != old) { 5258 vmx->ple_window_dirty = true; 5259 trace_kvm_ple_window_update(vcpu->vcpu_id, 5260 vmx->ple_window, old); 5261 } 5262 } 5263 5264 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5265 { 5266 struct vcpu_vmx *vmx = to_vmx(vcpu); 5267 unsigned int old = vmx->ple_window; 5268 5269 vmx->ple_window = __shrink_ple_window(old, ple_window, 5270 ple_window_shrink, 5271 ple_window); 5272 5273 if (vmx->ple_window != old) { 5274 vmx->ple_window_dirty = true; 5275 trace_kvm_ple_window_update(vcpu->vcpu_id, 5276 vmx->ple_window, old); 5277 } 5278 } 5279 5280 /* 5281 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5282 */ 5283 static void wakeup_handler(void) 5284 { 5285 struct kvm_vcpu *vcpu; 5286 int cpu = smp_processor_id(); 5287 5288 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5289 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5290 blocked_vcpu_list) { 5291 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5292 5293 if (pi_test_on(pi_desc) == 1) 5294 kvm_vcpu_kick(vcpu); 5295 } 5296 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5297 } 5298 5299 static void vmx_enable_tdp(void) 5300 { 5301 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5302 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5303 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5304 0ull, VMX_EPT_EXECUTABLE_MASK, 5305 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5306 VMX_EPT_RWX_MASK, 0ull); 5307 5308 ept_set_mmio_spte_mask(); 5309 kvm_enable_tdp(); 5310 } 5311 5312 /* 5313 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5314 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5315 */ 5316 static int handle_pause(struct kvm_vcpu *vcpu) 5317 { 5318 if (!kvm_pause_in_guest(vcpu->kvm)) 5319 grow_ple_window(vcpu); 5320 5321 /* 5322 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5323 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5324 * never set PAUSE_EXITING and just set PLE if supported, 5325 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5326 */ 5327 kvm_vcpu_on_spin(vcpu, true); 5328 return kvm_skip_emulated_instruction(vcpu); 5329 } 5330 5331 static int handle_nop(struct kvm_vcpu *vcpu) 5332 { 5333 return kvm_skip_emulated_instruction(vcpu); 5334 } 5335 5336 static int handle_mwait(struct kvm_vcpu *vcpu) 5337 { 5338 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5339 return handle_nop(vcpu); 5340 } 5341 5342 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5343 { 5344 kvm_queue_exception(vcpu, UD_VECTOR); 5345 return 1; 5346 } 5347 5348 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5349 { 5350 return 1; 5351 } 5352 5353 static int handle_monitor(struct kvm_vcpu *vcpu) 5354 { 5355 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5356 return handle_nop(vcpu); 5357 } 5358 5359 static int handle_invpcid(struct kvm_vcpu *vcpu) 5360 { 5361 u32 vmx_instruction_info; 5362 unsigned long type; 5363 bool pcid_enabled; 5364 gva_t gva; 5365 struct x86_exception e; 5366 unsigned i; 5367 unsigned long roots_to_free = 0; 5368 struct { 5369 u64 pcid; 5370 u64 gla; 5371 } operand; 5372 5373 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5374 kvm_queue_exception(vcpu, UD_VECTOR); 5375 return 1; 5376 } 5377 5378 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5379 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5380 5381 if (type > 3) { 5382 kvm_inject_gp(vcpu, 0); 5383 return 1; 5384 } 5385 5386 /* According to the Intel instruction reference, the memory operand 5387 * is read even if it isn't needed (e.g., for type==all) 5388 */ 5389 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5390 vmx_instruction_info, false, 5391 sizeof(operand), &gva)) 5392 return 1; 5393 5394 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5395 kvm_inject_page_fault(vcpu, &e); 5396 return 1; 5397 } 5398 5399 if (operand.pcid >> 12 != 0) { 5400 kvm_inject_gp(vcpu, 0); 5401 return 1; 5402 } 5403 5404 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5405 5406 switch (type) { 5407 case INVPCID_TYPE_INDIV_ADDR: 5408 if ((!pcid_enabled && (operand.pcid != 0)) || 5409 is_noncanonical_address(operand.gla, vcpu)) { 5410 kvm_inject_gp(vcpu, 0); 5411 return 1; 5412 } 5413 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5414 return kvm_skip_emulated_instruction(vcpu); 5415 5416 case INVPCID_TYPE_SINGLE_CTXT: 5417 if (!pcid_enabled && (operand.pcid != 0)) { 5418 kvm_inject_gp(vcpu, 0); 5419 return 1; 5420 } 5421 5422 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5423 kvm_mmu_sync_roots(vcpu); 5424 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5425 } 5426 5427 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5428 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5429 == operand.pcid) 5430 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5431 5432 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5433 /* 5434 * If neither the current cr3 nor any of the prev_roots use the 5435 * given PCID, then nothing needs to be done here because a 5436 * resync will happen anyway before switching to any other CR3. 5437 */ 5438 5439 return kvm_skip_emulated_instruction(vcpu); 5440 5441 case INVPCID_TYPE_ALL_NON_GLOBAL: 5442 /* 5443 * Currently, KVM doesn't mark global entries in the shadow 5444 * page tables, so a non-global flush just degenerates to a 5445 * global flush. If needed, we could optimize this later by 5446 * keeping track of global entries in shadow page tables. 5447 */ 5448 5449 /* fall-through */ 5450 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5451 kvm_mmu_unload(vcpu); 5452 return kvm_skip_emulated_instruction(vcpu); 5453 5454 default: 5455 BUG(); /* We have already checked above that type <= 3 */ 5456 } 5457 } 5458 5459 static int handle_pml_full(struct kvm_vcpu *vcpu) 5460 { 5461 unsigned long exit_qualification; 5462 5463 trace_kvm_pml_full(vcpu->vcpu_id); 5464 5465 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5466 5467 /* 5468 * PML buffer FULL happened while executing iret from NMI, 5469 * "blocked by NMI" bit has to be set before next VM entry. 5470 */ 5471 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5472 enable_vnmi && 5473 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5474 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5475 GUEST_INTR_STATE_NMI); 5476 5477 /* 5478 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5479 * here.., and there's no userspace involvement needed for PML. 5480 */ 5481 return 1; 5482 } 5483 5484 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5485 { 5486 struct vcpu_vmx *vmx = to_vmx(vcpu); 5487 5488 if (!vmx->req_immediate_exit && 5489 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5490 kvm_lapic_expired_hv_timer(vcpu); 5491 5492 return 1; 5493 } 5494 5495 /* 5496 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5497 * are overwritten by nested_vmx_setup() when nested=1. 5498 */ 5499 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5500 { 5501 kvm_queue_exception(vcpu, UD_VECTOR); 5502 return 1; 5503 } 5504 5505 static int handle_encls(struct kvm_vcpu *vcpu) 5506 { 5507 /* 5508 * SGX virtualization is not yet supported. There is no software 5509 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5510 * to prevent the guest from executing ENCLS. 5511 */ 5512 kvm_queue_exception(vcpu, UD_VECTOR); 5513 return 1; 5514 } 5515 5516 /* 5517 * The exit handlers return 1 if the exit was handled fully and guest execution 5518 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5519 * to be done to userspace and return 0. 5520 */ 5521 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5522 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5523 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5524 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5525 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5526 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5527 [EXIT_REASON_CR_ACCESS] = handle_cr, 5528 [EXIT_REASON_DR_ACCESS] = handle_dr, 5529 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5530 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5531 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5532 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, 5533 [EXIT_REASON_HLT] = kvm_emulate_halt, 5534 [EXIT_REASON_INVD] = handle_invd, 5535 [EXIT_REASON_INVLPG] = handle_invlpg, 5536 [EXIT_REASON_RDPMC] = handle_rdpmc, 5537 [EXIT_REASON_VMCALL] = handle_vmcall, 5538 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5539 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5540 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5541 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5542 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5543 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5544 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5545 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5546 [EXIT_REASON_VMON] = handle_vmx_instruction, 5547 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5548 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5549 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5550 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5551 [EXIT_REASON_WBINVD] = handle_wbinvd, 5552 [EXIT_REASON_XSETBV] = handle_xsetbv, 5553 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5554 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5555 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5556 [EXIT_REASON_LDTR_TR] = handle_desc, 5557 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5558 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5559 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5560 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5561 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5562 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5563 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5564 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5565 [EXIT_REASON_RDRAND] = handle_invalid_op, 5566 [EXIT_REASON_RDSEED] = handle_invalid_op, 5567 [EXIT_REASON_PML_FULL] = handle_pml_full, 5568 [EXIT_REASON_INVPCID] = handle_invpcid, 5569 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5570 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5571 [EXIT_REASON_ENCLS] = handle_encls, 5572 }; 5573 5574 static const int kvm_vmx_max_exit_handlers = 5575 ARRAY_SIZE(kvm_vmx_exit_handlers); 5576 5577 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5578 { 5579 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5580 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5581 } 5582 5583 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5584 { 5585 if (vmx->pml_pg) { 5586 __free_page(vmx->pml_pg); 5587 vmx->pml_pg = NULL; 5588 } 5589 } 5590 5591 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5592 { 5593 struct vcpu_vmx *vmx = to_vmx(vcpu); 5594 u64 *pml_buf; 5595 u16 pml_idx; 5596 5597 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5598 5599 /* Do nothing if PML buffer is empty */ 5600 if (pml_idx == (PML_ENTITY_NUM - 1)) 5601 return; 5602 5603 /* PML index always points to next available PML buffer entity */ 5604 if (pml_idx >= PML_ENTITY_NUM) 5605 pml_idx = 0; 5606 else 5607 pml_idx++; 5608 5609 pml_buf = page_address(vmx->pml_pg); 5610 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5611 u64 gpa; 5612 5613 gpa = pml_buf[pml_idx]; 5614 WARN_ON(gpa & (PAGE_SIZE - 1)); 5615 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5616 } 5617 5618 /* reset PML index */ 5619 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5620 } 5621 5622 /* 5623 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5624 * Called before reporting dirty_bitmap to userspace. 5625 */ 5626 static void kvm_flush_pml_buffers(struct kvm *kvm) 5627 { 5628 int i; 5629 struct kvm_vcpu *vcpu; 5630 /* 5631 * We only need to kick vcpu out of guest mode here, as PML buffer 5632 * is flushed at beginning of all VMEXITs, and it's obvious that only 5633 * vcpus running in guest are possible to have unflushed GPAs in PML 5634 * buffer. 5635 */ 5636 kvm_for_each_vcpu(i, vcpu, kvm) 5637 kvm_vcpu_kick(vcpu); 5638 } 5639 5640 static void vmx_dump_sel(char *name, uint32_t sel) 5641 { 5642 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5643 name, vmcs_read16(sel), 5644 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5645 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5646 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5647 } 5648 5649 static void vmx_dump_dtsel(char *name, uint32_t limit) 5650 { 5651 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5652 name, vmcs_read32(limit), 5653 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5654 } 5655 5656 void dump_vmcs(void) 5657 { 5658 u32 vmentry_ctl, vmexit_ctl; 5659 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5660 unsigned long cr4; 5661 u64 efer; 5662 int i, n; 5663 5664 if (!dump_invalid_vmcs) { 5665 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5666 return; 5667 } 5668 5669 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5670 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5671 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5672 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5673 cr4 = vmcs_readl(GUEST_CR4); 5674 efer = vmcs_read64(GUEST_IA32_EFER); 5675 secondary_exec_control = 0; 5676 if (cpu_has_secondary_exec_ctrls()) 5677 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5678 5679 pr_err("*** Guest State ***\n"); 5680 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5681 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5682 vmcs_readl(CR0_GUEST_HOST_MASK)); 5683 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5684 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5685 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5686 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5687 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5688 { 5689 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5690 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5691 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5692 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5693 } 5694 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5695 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5696 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5697 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5698 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5699 vmcs_readl(GUEST_SYSENTER_ESP), 5700 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5701 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5702 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5703 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5704 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5705 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5706 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5707 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5708 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5709 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5710 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5711 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5712 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5713 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5714 efer, vmcs_read64(GUEST_IA32_PAT)); 5715 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5716 vmcs_read64(GUEST_IA32_DEBUGCTL), 5717 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5718 if (cpu_has_load_perf_global_ctrl() && 5719 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5720 pr_err("PerfGlobCtl = 0x%016llx\n", 5721 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5722 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5723 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5724 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5725 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5726 vmcs_read32(GUEST_ACTIVITY_STATE)); 5727 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5728 pr_err("InterruptStatus = %04x\n", 5729 vmcs_read16(GUEST_INTR_STATUS)); 5730 5731 pr_err("*** Host State ***\n"); 5732 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5733 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5734 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5735 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5736 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5737 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5738 vmcs_read16(HOST_TR_SELECTOR)); 5739 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5740 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5741 vmcs_readl(HOST_TR_BASE)); 5742 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5743 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5744 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5745 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5746 vmcs_readl(HOST_CR4)); 5747 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5748 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5749 vmcs_read32(HOST_IA32_SYSENTER_CS), 5750 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5751 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5752 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5753 vmcs_read64(HOST_IA32_EFER), 5754 vmcs_read64(HOST_IA32_PAT)); 5755 if (cpu_has_load_perf_global_ctrl() && 5756 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5757 pr_err("PerfGlobCtl = 0x%016llx\n", 5758 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5759 5760 pr_err("*** Control State ***\n"); 5761 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5762 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5763 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5764 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5765 vmcs_read32(EXCEPTION_BITMAP), 5766 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5767 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5768 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5769 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5770 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5771 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5772 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5773 vmcs_read32(VM_EXIT_INTR_INFO), 5774 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5775 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5776 pr_err(" reason=%08x qualification=%016lx\n", 5777 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5778 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5779 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5780 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5781 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5782 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5783 pr_err("TSC Multiplier = 0x%016llx\n", 5784 vmcs_read64(TSC_MULTIPLIER)); 5785 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5786 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5787 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5788 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5789 } 5790 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5791 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5792 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5793 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5794 } 5795 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5796 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5797 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5798 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5799 n = vmcs_read32(CR3_TARGET_COUNT); 5800 for (i = 0; i + 1 < n; i += 4) 5801 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5802 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5803 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5804 if (i < n) 5805 pr_err("CR3 target%u=%016lx\n", 5806 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5807 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5808 pr_err("PLE Gap=%08x Window=%08x\n", 5809 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5810 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5811 pr_err("Virtual processor ID = 0x%04x\n", 5812 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5813 } 5814 5815 /* 5816 * The guest has exited. See if we can fix it or if we need userspace 5817 * assistance. 5818 */ 5819 static int vmx_handle_exit(struct kvm_vcpu *vcpu) 5820 { 5821 struct vcpu_vmx *vmx = to_vmx(vcpu); 5822 u32 exit_reason = vmx->exit_reason; 5823 u32 vectoring_info = vmx->idt_vectoring_info; 5824 5825 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5826 5827 /* 5828 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5829 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5830 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5831 * mode as if vcpus is in root mode, the PML buffer must has been 5832 * flushed already. 5833 */ 5834 if (enable_pml) 5835 vmx_flush_pml_buffer(vcpu); 5836 5837 /* If guest state is invalid, start emulating */ 5838 if (vmx->emulation_required) 5839 return handle_invalid_guest_state(vcpu); 5840 5841 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5842 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5843 5844 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5845 dump_vmcs(); 5846 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5847 vcpu->run->fail_entry.hardware_entry_failure_reason 5848 = exit_reason; 5849 return 0; 5850 } 5851 5852 if (unlikely(vmx->fail)) { 5853 dump_vmcs(); 5854 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5855 vcpu->run->fail_entry.hardware_entry_failure_reason 5856 = vmcs_read32(VM_INSTRUCTION_ERROR); 5857 return 0; 5858 } 5859 5860 /* 5861 * Note: 5862 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5863 * delivery event since it indicates guest is accessing MMIO. 5864 * The vm-exit can be triggered again after return to guest that 5865 * will cause infinite loop. 5866 */ 5867 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5868 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5869 exit_reason != EXIT_REASON_EPT_VIOLATION && 5870 exit_reason != EXIT_REASON_PML_FULL && 5871 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5872 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5873 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5874 vcpu->run->internal.ndata = 3; 5875 vcpu->run->internal.data[0] = vectoring_info; 5876 vcpu->run->internal.data[1] = exit_reason; 5877 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5878 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5879 vcpu->run->internal.ndata++; 5880 vcpu->run->internal.data[3] = 5881 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5882 } 5883 return 0; 5884 } 5885 5886 if (unlikely(!enable_vnmi && 5887 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5888 if (vmx_interrupt_allowed(vcpu)) { 5889 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5890 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5891 vcpu->arch.nmi_pending) { 5892 /* 5893 * This CPU don't support us in finding the end of an 5894 * NMI-blocked window if the guest runs with IRQs 5895 * disabled. So we pull the trigger after 1 s of 5896 * futile waiting, but inform the user about this. 5897 */ 5898 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5899 "state on VCPU %d after 1 s timeout\n", 5900 __func__, vcpu->vcpu_id); 5901 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5902 } 5903 } 5904 5905 if (exit_reason < kvm_vmx_max_exit_handlers 5906 && kvm_vmx_exit_handlers[exit_reason]) { 5907 #ifdef CONFIG_RETPOLINE 5908 if (exit_reason == EXIT_REASON_MSR_WRITE) 5909 return kvm_emulate_wrmsr(vcpu); 5910 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5911 return handle_preemption_timer(vcpu); 5912 else if (exit_reason == EXIT_REASON_PENDING_INTERRUPT) 5913 return handle_interrupt_window(vcpu); 5914 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5915 return handle_external_interrupt(vcpu); 5916 else if (exit_reason == EXIT_REASON_HLT) 5917 return kvm_emulate_halt(vcpu); 5918 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5919 return handle_ept_misconfig(vcpu); 5920 #endif 5921 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5922 } else { 5923 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", 5924 exit_reason); 5925 dump_vmcs(); 5926 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5927 vcpu->run->internal.suberror = 5928 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5929 vcpu->run->internal.ndata = 1; 5930 vcpu->run->internal.data[0] = exit_reason; 5931 return 0; 5932 } 5933 } 5934 5935 /* 5936 * Software based L1D cache flush which is used when microcode providing 5937 * the cache control MSR is not loaded. 5938 * 5939 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5940 * flush it is required to read in 64 KiB because the replacement algorithm 5941 * is not exactly LRU. This could be sized at runtime via topology 5942 * information but as all relevant affected CPUs have 32KiB L1D cache size 5943 * there is no point in doing so. 5944 */ 5945 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5946 { 5947 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5948 5949 /* 5950 * This code is only executed when the the flush mode is 'cond' or 5951 * 'always' 5952 */ 5953 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5954 bool flush_l1d; 5955 5956 /* 5957 * Clear the per-vcpu flush bit, it gets set again 5958 * either from vcpu_run() or from one of the unsafe 5959 * VMEXIT handlers. 5960 */ 5961 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5962 vcpu->arch.l1tf_flush_l1d = false; 5963 5964 /* 5965 * Clear the per-cpu flush bit, it gets set again from 5966 * the interrupt handlers. 5967 */ 5968 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 5969 kvm_clear_cpu_l1tf_flush_l1d(); 5970 5971 if (!flush_l1d) 5972 return; 5973 } 5974 5975 vcpu->stat.l1d_flush++; 5976 5977 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 5978 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 5979 return; 5980 } 5981 5982 asm volatile( 5983 /* First ensure the pages are in the TLB */ 5984 "xorl %%eax, %%eax\n" 5985 ".Lpopulate_tlb:\n\t" 5986 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5987 "addl $4096, %%eax\n\t" 5988 "cmpl %%eax, %[size]\n\t" 5989 "jne .Lpopulate_tlb\n\t" 5990 "xorl %%eax, %%eax\n\t" 5991 "cpuid\n\t" 5992 /* Now fill the cache */ 5993 "xorl %%eax, %%eax\n" 5994 ".Lfill_cache:\n" 5995 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5996 "addl $64, %%eax\n\t" 5997 "cmpl %%eax, %[size]\n\t" 5998 "jne .Lfill_cache\n\t" 5999 "lfence\n" 6000 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6001 [size] "r" (size) 6002 : "eax", "ebx", "ecx", "edx"); 6003 } 6004 6005 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6006 { 6007 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6008 int tpr_threshold; 6009 6010 if (is_guest_mode(vcpu) && 6011 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6012 return; 6013 6014 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6015 if (is_guest_mode(vcpu)) 6016 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6017 else 6018 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6019 } 6020 6021 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6022 { 6023 struct vcpu_vmx *vmx = to_vmx(vcpu); 6024 u32 sec_exec_control; 6025 6026 if (!lapic_in_kernel(vcpu)) 6027 return; 6028 6029 if (!flexpriority_enabled && 6030 !cpu_has_vmx_virtualize_x2apic_mode()) 6031 return; 6032 6033 /* Postpone execution until vmcs01 is the current VMCS. */ 6034 if (is_guest_mode(vcpu)) { 6035 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6036 return; 6037 } 6038 6039 sec_exec_control = secondary_exec_controls_get(vmx); 6040 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6041 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6042 6043 switch (kvm_get_apic_mode(vcpu)) { 6044 case LAPIC_MODE_INVALID: 6045 WARN_ONCE(true, "Invalid local APIC state"); 6046 case LAPIC_MODE_DISABLED: 6047 break; 6048 case LAPIC_MODE_XAPIC: 6049 if (flexpriority_enabled) { 6050 sec_exec_control |= 6051 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6052 vmx_flush_tlb(vcpu, true); 6053 } 6054 break; 6055 case LAPIC_MODE_X2APIC: 6056 if (cpu_has_vmx_virtualize_x2apic_mode()) 6057 sec_exec_control |= 6058 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6059 break; 6060 } 6061 secondary_exec_controls_set(vmx, sec_exec_control); 6062 6063 vmx_update_msr_bitmap(vcpu); 6064 } 6065 6066 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6067 { 6068 if (!is_guest_mode(vcpu)) { 6069 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6070 vmx_flush_tlb(vcpu, true); 6071 } 6072 } 6073 6074 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6075 { 6076 u16 status; 6077 u8 old; 6078 6079 if (max_isr == -1) 6080 max_isr = 0; 6081 6082 status = vmcs_read16(GUEST_INTR_STATUS); 6083 old = status >> 8; 6084 if (max_isr != old) { 6085 status &= 0xff; 6086 status |= max_isr << 8; 6087 vmcs_write16(GUEST_INTR_STATUS, status); 6088 } 6089 } 6090 6091 static void vmx_set_rvi(int vector) 6092 { 6093 u16 status; 6094 u8 old; 6095 6096 if (vector == -1) 6097 vector = 0; 6098 6099 status = vmcs_read16(GUEST_INTR_STATUS); 6100 old = (u8)status & 0xff; 6101 if ((u8)vector != old) { 6102 status &= ~0xff; 6103 status |= (u8)vector; 6104 vmcs_write16(GUEST_INTR_STATUS, status); 6105 } 6106 } 6107 6108 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6109 { 6110 /* 6111 * When running L2, updating RVI is only relevant when 6112 * vmcs12 virtual-interrupt-delivery enabled. 6113 * However, it can be enabled only when L1 also 6114 * intercepts external-interrupts and in that case 6115 * we should not update vmcs02 RVI but instead intercept 6116 * interrupt. Therefore, do nothing when running L2. 6117 */ 6118 if (!is_guest_mode(vcpu)) 6119 vmx_set_rvi(max_irr); 6120 } 6121 6122 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6123 { 6124 struct vcpu_vmx *vmx = to_vmx(vcpu); 6125 int max_irr; 6126 bool max_irr_updated; 6127 6128 WARN_ON(!vcpu->arch.apicv_active); 6129 if (pi_test_on(&vmx->pi_desc)) { 6130 pi_clear_on(&vmx->pi_desc); 6131 /* 6132 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6133 * But on x86 this is just a compiler barrier anyway. 6134 */ 6135 smp_mb__after_atomic(); 6136 max_irr_updated = 6137 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6138 6139 /* 6140 * If we are running L2 and L1 has a new pending interrupt 6141 * which can be injected, we should re-evaluate 6142 * what should be done with this new L1 interrupt. 6143 * If L1 intercepts external-interrupts, we should 6144 * exit from L2 to L1. Otherwise, interrupt should be 6145 * delivered directly to L2. 6146 */ 6147 if (is_guest_mode(vcpu) && max_irr_updated) { 6148 if (nested_exit_on_intr(vcpu)) 6149 kvm_vcpu_exiting_guest_mode(vcpu); 6150 else 6151 kvm_make_request(KVM_REQ_EVENT, vcpu); 6152 } 6153 } else { 6154 max_irr = kvm_lapic_find_highest_irr(vcpu); 6155 } 6156 vmx_hwapic_irr_update(vcpu, max_irr); 6157 return max_irr; 6158 } 6159 6160 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6161 { 6162 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6163 6164 return pi_test_on(pi_desc) || 6165 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6166 } 6167 6168 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6169 { 6170 if (!kvm_vcpu_apicv_active(vcpu)) 6171 return; 6172 6173 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6174 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6175 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6176 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6177 } 6178 6179 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6180 { 6181 struct vcpu_vmx *vmx = to_vmx(vcpu); 6182 6183 pi_clear_on(&vmx->pi_desc); 6184 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6185 } 6186 6187 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6188 { 6189 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6190 6191 /* if exit due to PF check for async PF */ 6192 if (is_page_fault(vmx->exit_intr_info)) 6193 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6194 6195 /* Handle machine checks before interrupts are enabled */ 6196 if (is_machine_check(vmx->exit_intr_info)) 6197 kvm_machine_check(); 6198 6199 /* We need to handle NMIs before interrupts are enabled */ 6200 if (is_nmi(vmx->exit_intr_info)) { 6201 kvm_before_interrupt(&vmx->vcpu); 6202 asm("int $2"); 6203 kvm_after_interrupt(&vmx->vcpu); 6204 } 6205 } 6206 6207 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6208 { 6209 unsigned int vector; 6210 unsigned long entry; 6211 #ifdef CONFIG_X86_64 6212 unsigned long tmp; 6213 #endif 6214 gate_desc *desc; 6215 u32 intr_info; 6216 6217 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6218 if (WARN_ONCE(!is_external_intr(intr_info), 6219 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6220 return; 6221 6222 vector = intr_info & INTR_INFO_VECTOR_MASK; 6223 desc = (gate_desc *)host_idt_base + vector; 6224 entry = gate_offset(desc); 6225 6226 kvm_before_interrupt(vcpu); 6227 6228 asm volatile( 6229 #ifdef CONFIG_X86_64 6230 "mov %%" _ASM_SP ", %[sp]\n\t" 6231 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6232 "push $%c[ss]\n\t" 6233 "push %[sp]\n\t" 6234 #endif 6235 "pushf\n\t" 6236 __ASM_SIZE(push) " $%c[cs]\n\t" 6237 CALL_NOSPEC 6238 : 6239 #ifdef CONFIG_X86_64 6240 [sp]"=&r"(tmp), 6241 #endif 6242 ASM_CALL_CONSTRAINT 6243 : 6244 THUNK_TARGET(entry), 6245 [ss]"i"(__KERNEL_DS), 6246 [cs]"i"(__KERNEL_CS) 6247 ); 6248 6249 kvm_after_interrupt(vcpu); 6250 } 6251 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6252 6253 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu) 6254 { 6255 struct vcpu_vmx *vmx = to_vmx(vcpu); 6256 6257 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6258 handle_external_interrupt_irqoff(vcpu); 6259 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6260 handle_exception_nmi_irqoff(vmx); 6261 } 6262 6263 static bool vmx_has_emulated_msr(int index) 6264 { 6265 switch (index) { 6266 case MSR_IA32_SMBASE: 6267 /* 6268 * We cannot do SMM unless we can run the guest in big 6269 * real mode. 6270 */ 6271 return enable_unrestricted_guest || emulate_invalid_guest_state; 6272 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6273 return nested; 6274 case MSR_AMD64_VIRT_SPEC_CTRL: 6275 /* This is AMD only. */ 6276 return false; 6277 default: 6278 return true; 6279 } 6280 } 6281 6282 static bool vmx_pt_supported(void) 6283 { 6284 return pt_mode == PT_MODE_HOST_GUEST; 6285 } 6286 6287 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6288 { 6289 u32 exit_intr_info; 6290 bool unblock_nmi; 6291 u8 vector; 6292 bool idtv_info_valid; 6293 6294 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6295 6296 if (enable_vnmi) { 6297 if (vmx->loaded_vmcs->nmi_known_unmasked) 6298 return; 6299 /* 6300 * Can't use vmx->exit_intr_info since we're not sure what 6301 * the exit reason is. 6302 */ 6303 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6304 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6305 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6306 /* 6307 * SDM 3: 27.7.1.2 (September 2008) 6308 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6309 * a guest IRET fault. 6310 * SDM 3: 23.2.2 (September 2008) 6311 * Bit 12 is undefined in any of the following cases: 6312 * If the VM exit sets the valid bit in the IDT-vectoring 6313 * information field. 6314 * If the VM exit is due to a double fault. 6315 */ 6316 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6317 vector != DF_VECTOR && !idtv_info_valid) 6318 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6319 GUEST_INTR_STATE_NMI); 6320 else 6321 vmx->loaded_vmcs->nmi_known_unmasked = 6322 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6323 & GUEST_INTR_STATE_NMI); 6324 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6325 vmx->loaded_vmcs->vnmi_blocked_time += 6326 ktime_to_ns(ktime_sub(ktime_get(), 6327 vmx->loaded_vmcs->entry_time)); 6328 } 6329 6330 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6331 u32 idt_vectoring_info, 6332 int instr_len_field, 6333 int error_code_field) 6334 { 6335 u8 vector; 6336 int type; 6337 bool idtv_info_valid; 6338 6339 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6340 6341 vcpu->arch.nmi_injected = false; 6342 kvm_clear_exception_queue(vcpu); 6343 kvm_clear_interrupt_queue(vcpu); 6344 6345 if (!idtv_info_valid) 6346 return; 6347 6348 kvm_make_request(KVM_REQ_EVENT, vcpu); 6349 6350 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6351 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6352 6353 switch (type) { 6354 case INTR_TYPE_NMI_INTR: 6355 vcpu->arch.nmi_injected = true; 6356 /* 6357 * SDM 3: 27.7.1.2 (September 2008) 6358 * Clear bit "block by NMI" before VM entry if a NMI 6359 * delivery faulted. 6360 */ 6361 vmx_set_nmi_mask(vcpu, false); 6362 break; 6363 case INTR_TYPE_SOFT_EXCEPTION: 6364 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6365 /* fall through */ 6366 case INTR_TYPE_HARD_EXCEPTION: 6367 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6368 u32 err = vmcs_read32(error_code_field); 6369 kvm_requeue_exception_e(vcpu, vector, err); 6370 } else 6371 kvm_requeue_exception(vcpu, vector); 6372 break; 6373 case INTR_TYPE_SOFT_INTR: 6374 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6375 /* fall through */ 6376 case INTR_TYPE_EXT_INTR: 6377 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6378 break; 6379 default: 6380 break; 6381 } 6382 } 6383 6384 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6385 { 6386 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6387 VM_EXIT_INSTRUCTION_LEN, 6388 IDT_VECTORING_ERROR_CODE); 6389 } 6390 6391 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6392 { 6393 __vmx_complete_interrupts(vcpu, 6394 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6395 VM_ENTRY_INSTRUCTION_LEN, 6396 VM_ENTRY_EXCEPTION_ERROR_CODE); 6397 6398 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6399 } 6400 6401 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6402 { 6403 int i, nr_msrs; 6404 struct perf_guest_switch_msr *msrs; 6405 6406 msrs = perf_guest_get_msrs(&nr_msrs); 6407 6408 if (!msrs) 6409 return; 6410 6411 for (i = 0; i < nr_msrs; i++) 6412 if (msrs[i].host == msrs[i].guest) 6413 clear_atomic_switch_msr(vmx, msrs[i].msr); 6414 else 6415 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6416 msrs[i].host, false); 6417 } 6418 6419 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6420 { 6421 u32 host_umwait_control; 6422 6423 if (!vmx_has_waitpkg(vmx)) 6424 return; 6425 6426 host_umwait_control = get_umwait_control_msr(); 6427 6428 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6429 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6430 vmx->msr_ia32_umwait_control, 6431 host_umwait_control, false); 6432 else 6433 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6434 } 6435 6436 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6437 { 6438 struct vcpu_vmx *vmx = to_vmx(vcpu); 6439 u64 tscl; 6440 u32 delta_tsc; 6441 6442 if (vmx->req_immediate_exit) { 6443 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6444 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6445 } else if (vmx->hv_deadline_tsc != -1) { 6446 tscl = rdtsc(); 6447 if (vmx->hv_deadline_tsc > tscl) 6448 /* set_hv_timer ensures the delta fits in 32-bits */ 6449 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6450 cpu_preemption_timer_multi); 6451 else 6452 delta_tsc = 0; 6453 6454 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6455 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6456 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6457 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6458 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6459 } 6460 } 6461 6462 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6463 { 6464 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6465 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6466 vmcs_writel(HOST_RSP, host_rsp); 6467 } 6468 } 6469 6470 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6471 6472 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6473 { 6474 struct vcpu_vmx *vmx = to_vmx(vcpu); 6475 unsigned long cr3, cr4; 6476 6477 /* Record the guest's net vcpu time for enforced NMI injections. */ 6478 if (unlikely(!enable_vnmi && 6479 vmx->loaded_vmcs->soft_vnmi_blocked)) 6480 vmx->loaded_vmcs->entry_time = ktime_get(); 6481 6482 /* Don't enter VMX if guest state is invalid, let the exit handler 6483 start emulation until we arrive back to a valid state */ 6484 if (vmx->emulation_required) 6485 return; 6486 6487 if (vmx->ple_window_dirty) { 6488 vmx->ple_window_dirty = false; 6489 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6490 } 6491 6492 if (vmx->nested.need_vmcs12_to_shadow_sync) 6493 nested_sync_vmcs12_to_shadow(vcpu); 6494 6495 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6496 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6497 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6498 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6499 6500 cr3 = __get_current_cr3_fast(); 6501 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6502 vmcs_writel(HOST_CR3, cr3); 6503 vmx->loaded_vmcs->host_state.cr3 = cr3; 6504 } 6505 6506 cr4 = cr4_read_shadow(); 6507 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6508 vmcs_writel(HOST_CR4, cr4); 6509 vmx->loaded_vmcs->host_state.cr4 = cr4; 6510 } 6511 6512 /* When single-stepping over STI and MOV SS, we must clear the 6513 * corresponding interruptibility bits in the guest state. Otherwise 6514 * vmentry fails as it then expects bit 14 (BS) in pending debug 6515 * exceptions being set, but that's not correct for the guest debugging 6516 * case. */ 6517 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6518 vmx_set_interrupt_shadow(vcpu, 0); 6519 6520 kvm_load_guest_xsave_state(vcpu); 6521 6522 if (static_cpu_has(X86_FEATURE_PKU) && 6523 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6524 vcpu->arch.pkru != vmx->host_pkru) 6525 __write_pkru(vcpu->arch.pkru); 6526 6527 pt_guest_enter(vmx); 6528 6529 atomic_switch_perf_msrs(vmx); 6530 atomic_switch_umwait_control_msr(vmx); 6531 6532 if (enable_preemption_timer) 6533 vmx_update_hv_timer(vcpu); 6534 6535 if (lapic_in_kernel(vcpu) && 6536 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6537 kvm_wait_lapic_expire(vcpu); 6538 6539 /* 6540 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6541 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6542 * is no need to worry about the conditional branch over the wrmsr 6543 * being speculatively taken. 6544 */ 6545 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6546 6547 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6548 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6549 vmx_l1d_flush(vcpu); 6550 else if (static_branch_unlikely(&mds_user_clear)) 6551 mds_clear_cpu_buffers(); 6552 6553 if (vcpu->arch.cr2 != read_cr2()) 6554 write_cr2(vcpu->arch.cr2); 6555 6556 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6557 vmx->loaded_vmcs->launched); 6558 6559 vcpu->arch.cr2 = read_cr2(); 6560 6561 /* 6562 * We do not use IBRS in the kernel. If this vCPU has used the 6563 * SPEC_CTRL MSR it may have left it on; save the value and 6564 * turn it off. This is much more efficient than blindly adding 6565 * it to the atomic save/restore list. Especially as the former 6566 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6567 * 6568 * For non-nested case: 6569 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6570 * save it. 6571 * 6572 * For nested case: 6573 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6574 * save it. 6575 */ 6576 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6577 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6578 6579 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6580 6581 /* All fields are clean at this point */ 6582 if (static_branch_unlikely(&enable_evmcs)) 6583 current_evmcs->hv_clean_fields |= 6584 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6585 6586 if (static_branch_unlikely(&enable_evmcs)) 6587 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6588 6589 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6590 if (vmx->host_debugctlmsr) 6591 update_debugctlmsr(vmx->host_debugctlmsr); 6592 6593 #ifndef CONFIG_X86_64 6594 /* 6595 * The sysexit path does not restore ds/es, so we must set them to 6596 * a reasonable value ourselves. 6597 * 6598 * We can't defer this to vmx_prepare_switch_to_host() since that 6599 * function may be executed in interrupt context, which saves and 6600 * restore segments around it, nullifying its effect. 6601 */ 6602 loadsegment(ds, __USER_DS); 6603 loadsegment(es, __USER_DS); 6604 #endif 6605 6606 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6607 | (1 << VCPU_EXREG_RFLAGS) 6608 | (1 << VCPU_EXREG_PDPTR) 6609 | (1 << VCPU_EXREG_SEGMENTS) 6610 | (1 << VCPU_EXREG_CR3)); 6611 vcpu->arch.regs_dirty = 0; 6612 6613 pt_guest_exit(vmx); 6614 6615 /* 6616 * eager fpu is enabled if PKEY is supported and CR4 is switched 6617 * back on host, so it is safe to read guest PKRU from current 6618 * XSAVE. 6619 */ 6620 if (static_cpu_has(X86_FEATURE_PKU) && 6621 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6622 vcpu->arch.pkru = rdpkru(); 6623 if (vcpu->arch.pkru != vmx->host_pkru) 6624 __write_pkru(vmx->host_pkru); 6625 } 6626 6627 kvm_load_host_xsave_state(vcpu); 6628 6629 vmx->nested.nested_run_pending = 0; 6630 vmx->idt_vectoring_info = 0; 6631 6632 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6633 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6634 kvm_machine_check(); 6635 6636 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6637 return; 6638 6639 vmx->loaded_vmcs->launched = 1; 6640 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6641 6642 vmx_recover_nmi_blocking(vmx); 6643 vmx_complete_interrupts(vmx); 6644 } 6645 6646 static struct kvm *vmx_vm_alloc(void) 6647 { 6648 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6649 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6650 PAGE_KERNEL); 6651 return &kvm_vmx->kvm; 6652 } 6653 6654 static void vmx_vm_free(struct kvm *kvm) 6655 { 6656 kfree(kvm->arch.hyperv.hv_pa_pg); 6657 vfree(to_kvm_vmx(kvm)); 6658 } 6659 6660 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6661 { 6662 struct vcpu_vmx *vmx = to_vmx(vcpu); 6663 6664 if (enable_pml) 6665 vmx_destroy_pml_buffer(vmx); 6666 free_vpid(vmx->vpid); 6667 nested_vmx_free_vcpu(vcpu); 6668 free_loaded_vmcs(vmx->loaded_vmcs); 6669 kvm_vcpu_uninit(vcpu); 6670 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); 6671 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); 6672 kmem_cache_free(kvm_vcpu_cache, vmx); 6673 } 6674 6675 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) 6676 { 6677 int err; 6678 struct vcpu_vmx *vmx; 6679 unsigned long *msr_bitmap; 6680 int i, cpu; 6681 6682 BUILD_BUG_ON_MSG(offsetof(struct vcpu_vmx, vcpu) != 0, 6683 "struct kvm_vcpu must be at offset 0 for arch usercopy region"); 6684 6685 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT); 6686 if (!vmx) 6687 return ERR_PTR(-ENOMEM); 6688 6689 vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 6690 GFP_KERNEL_ACCOUNT); 6691 if (!vmx->vcpu.arch.user_fpu) { 6692 printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n"); 6693 err = -ENOMEM; 6694 goto free_partial_vcpu; 6695 } 6696 6697 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 6698 GFP_KERNEL_ACCOUNT); 6699 if (!vmx->vcpu.arch.guest_fpu) { 6700 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); 6701 err = -ENOMEM; 6702 goto free_user_fpu; 6703 } 6704 6705 vmx->vpid = allocate_vpid(); 6706 6707 err = kvm_vcpu_init(&vmx->vcpu, kvm, id); 6708 if (err) 6709 goto free_vcpu; 6710 6711 err = -ENOMEM; 6712 6713 /* 6714 * If PML is turned on, failure on enabling PML just results in failure 6715 * of creating the vcpu, therefore we can simplify PML logic (by 6716 * avoiding dealing with cases, such as enabling PML partially on vcpus 6717 * for the guest, etc. 6718 */ 6719 if (enable_pml) { 6720 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6721 if (!vmx->pml_pg) 6722 goto uninit_vcpu; 6723 } 6724 6725 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6726 6727 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6728 u32 index = vmx_msr_index[i]; 6729 u32 data_low, data_high; 6730 int j = vmx->nmsrs; 6731 6732 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6733 continue; 6734 if (wrmsr_safe(index, data_low, data_high) < 0) 6735 continue; 6736 6737 vmx->guest_msrs[j].index = i; 6738 vmx->guest_msrs[j].data = 0; 6739 switch (index) { 6740 case MSR_IA32_TSX_CTRL: 6741 /* 6742 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6743 * let's avoid changing CPUID bits under the host 6744 * kernel's feet. 6745 */ 6746 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6747 break; 6748 default: 6749 vmx->guest_msrs[j].mask = -1ull; 6750 break; 6751 } 6752 ++vmx->nmsrs; 6753 } 6754 6755 err = alloc_loaded_vmcs(&vmx->vmcs01); 6756 if (err < 0) 6757 goto free_pml; 6758 6759 msr_bitmap = vmx->vmcs01.msr_bitmap; 6760 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6761 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6762 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6763 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6764 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6765 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6766 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6767 if (kvm_cstate_in_guest(kvm)) { 6768 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6769 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6770 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6771 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6772 } 6773 vmx->msr_bitmap_mode = 0; 6774 6775 vmx->loaded_vmcs = &vmx->vmcs01; 6776 cpu = get_cpu(); 6777 vmx_vcpu_load(&vmx->vcpu, cpu); 6778 vmx->vcpu.cpu = cpu; 6779 init_vmcs(vmx); 6780 vmx_vcpu_put(&vmx->vcpu); 6781 put_cpu(); 6782 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { 6783 err = alloc_apic_access_page(kvm); 6784 if (err) 6785 goto free_vmcs; 6786 } 6787 6788 if (enable_ept && !enable_unrestricted_guest) { 6789 err = init_rmode_identity_map(kvm); 6790 if (err) 6791 goto free_vmcs; 6792 } 6793 6794 if (nested) 6795 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6796 vmx_capability.ept, 6797 kvm_vcpu_apicv_active(&vmx->vcpu)); 6798 else 6799 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6800 6801 vmx->nested.posted_intr_nv = -1; 6802 vmx->nested.current_vmptr = -1ull; 6803 6804 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; 6805 6806 /* 6807 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6808 * or POSTED_INTR_WAKEUP_VECTOR. 6809 */ 6810 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6811 vmx->pi_desc.sn = 1; 6812 6813 vmx->ept_pointer = INVALID_PAGE; 6814 6815 return &vmx->vcpu; 6816 6817 free_vmcs: 6818 free_loaded_vmcs(vmx->loaded_vmcs); 6819 free_pml: 6820 vmx_destroy_pml_buffer(vmx); 6821 uninit_vcpu: 6822 kvm_vcpu_uninit(&vmx->vcpu); 6823 free_vcpu: 6824 free_vpid(vmx->vpid); 6825 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); 6826 free_user_fpu: 6827 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); 6828 free_partial_vcpu: 6829 kmem_cache_free(kvm_vcpu_cache, vmx); 6830 return ERR_PTR(err); 6831 } 6832 6833 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6834 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6835 6836 static int vmx_vm_init(struct kvm *kvm) 6837 { 6838 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6839 6840 if (!ple_gap) 6841 kvm->arch.pause_in_guest = true; 6842 6843 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6844 switch (l1tf_mitigation) { 6845 case L1TF_MITIGATION_OFF: 6846 case L1TF_MITIGATION_FLUSH_NOWARN: 6847 /* 'I explicitly don't care' is set */ 6848 break; 6849 case L1TF_MITIGATION_FLUSH: 6850 case L1TF_MITIGATION_FLUSH_NOSMT: 6851 case L1TF_MITIGATION_FULL: 6852 /* 6853 * Warn upon starting the first VM in a potentially 6854 * insecure environment. 6855 */ 6856 if (sched_smt_active()) 6857 pr_warn_once(L1TF_MSG_SMT); 6858 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6859 pr_warn_once(L1TF_MSG_L1D); 6860 break; 6861 case L1TF_MITIGATION_FULL_FORCE: 6862 /* Flush is enforced */ 6863 break; 6864 } 6865 } 6866 return 0; 6867 } 6868 6869 static int __init vmx_check_processor_compat(void) 6870 { 6871 struct vmcs_config vmcs_conf; 6872 struct vmx_capability vmx_cap; 6873 6874 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6875 return -EIO; 6876 if (nested) 6877 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept, 6878 enable_apicv); 6879 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6880 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6881 smp_processor_id()); 6882 return -EIO; 6883 } 6884 return 0; 6885 } 6886 6887 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6888 { 6889 u8 cache; 6890 u64 ipat = 0; 6891 6892 /* For VT-d and EPT combination 6893 * 1. MMIO: always map as UC 6894 * 2. EPT with VT-d: 6895 * a. VT-d without snooping control feature: can't guarantee the 6896 * result, try to trust guest. 6897 * b. VT-d with snooping control feature: snooping control feature of 6898 * VT-d engine can guarantee the cache correctness. Just set it 6899 * to WB to keep consistent with host. So the same as item 3. 6900 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6901 * consistent with host MTRR 6902 */ 6903 if (is_mmio) { 6904 cache = MTRR_TYPE_UNCACHABLE; 6905 goto exit; 6906 } 6907 6908 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6909 ipat = VMX_EPT_IPAT_BIT; 6910 cache = MTRR_TYPE_WRBACK; 6911 goto exit; 6912 } 6913 6914 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6915 ipat = VMX_EPT_IPAT_BIT; 6916 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6917 cache = MTRR_TYPE_WRBACK; 6918 else 6919 cache = MTRR_TYPE_UNCACHABLE; 6920 goto exit; 6921 } 6922 6923 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6924 6925 exit: 6926 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6927 } 6928 6929 static int vmx_get_lpage_level(void) 6930 { 6931 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6932 return PT_DIRECTORY_LEVEL; 6933 else 6934 /* For shadow and EPT supported 1GB page */ 6935 return PT_PDPE_LEVEL; 6936 } 6937 6938 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6939 { 6940 /* 6941 * These bits in the secondary execution controls field 6942 * are dynamic, the others are mostly based on the hypervisor 6943 * architecture and the guest's CPUID. Do not touch the 6944 * dynamic bits. 6945 */ 6946 u32 mask = 6947 SECONDARY_EXEC_SHADOW_VMCS | 6948 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6949 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6950 SECONDARY_EXEC_DESC; 6951 6952 u32 new_ctl = vmx->secondary_exec_control; 6953 u32 cur_ctl = secondary_exec_controls_get(vmx); 6954 6955 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6956 } 6957 6958 /* 6959 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6960 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6961 */ 6962 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6963 { 6964 struct vcpu_vmx *vmx = to_vmx(vcpu); 6965 struct kvm_cpuid_entry2 *entry; 6966 6967 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6968 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6969 6970 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6971 if (entry && (entry->_reg & (_cpuid_mask))) \ 6972 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6973 } while (0) 6974 6975 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6976 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); 6977 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); 6978 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); 6979 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); 6980 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); 6981 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); 6982 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); 6983 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); 6984 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); 6985 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); 6986 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); 6987 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); 6988 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); 6989 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); 6990 6991 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6992 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); 6993 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); 6994 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); 6995 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); 6996 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); 6997 cr4_fixed1_update(X86_CR4_LA57, ecx, bit(X86_FEATURE_LA57)); 6998 6999 #undef cr4_fixed1_update 7000 } 7001 7002 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 7003 { 7004 struct vcpu_vmx *vmx = to_vmx(vcpu); 7005 7006 if (kvm_mpx_supported()) { 7007 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 7008 7009 if (mpx_enabled) { 7010 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 7011 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 7012 } else { 7013 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 7014 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 7015 } 7016 } 7017 } 7018 7019 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7020 { 7021 struct vcpu_vmx *vmx = to_vmx(vcpu); 7022 struct kvm_cpuid_entry2 *best = NULL; 7023 int i; 7024 7025 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7026 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7027 if (!best) 7028 return; 7029 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7030 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7031 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7032 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7033 } 7034 7035 /* Get the number of configurable Address Ranges for filtering */ 7036 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7037 PT_CAP_num_address_ranges); 7038 7039 /* Initialize and clear the no dependency bits */ 7040 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7041 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7042 7043 /* 7044 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7045 * will inject an #GP 7046 */ 7047 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7048 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7049 7050 /* 7051 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7052 * PSBFreq can be set 7053 */ 7054 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7055 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7056 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7057 7058 /* 7059 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7060 * MTCFreq can be set 7061 */ 7062 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7063 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7064 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7065 7066 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7067 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7068 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7069 RTIT_CTL_PTW_EN); 7070 7071 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7072 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7073 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7074 7075 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7076 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7077 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7078 7079 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7080 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7081 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7082 7083 /* unmask address range configure area */ 7084 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7085 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7086 } 7087 7088 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7089 { 7090 struct vcpu_vmx *vmx = to_vmx(vcpu); 7091 7092 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7093 vcpu->arch.xsaves_enabled = false; 7094 7095 if (cpu_has_secondary_exec_ctrls()) { 7096 vmx_compute_secondary_exec_control(vmx); 7097 vmcs_set_secondary_exec_control(vmx); 7098 } 7099 7100 if (nested_vmx_allowed(vcpu)) 7101 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7102 FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX | 7103 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 7104 else 7105 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7106 ~(FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX | 7107 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX); 7108 7109 if (nested_vmx_allowed(vcpu)) { 7110 nested_vmx_cr_fixed1_bits_update(vcpu); 7111 nested_vmx_entry_exit_ctls_update(vcpu); 7112 } 7113 7114 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7115 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7116 update_intel_pt_cfg(vcpu); 7117 7118 if (boot_cpu_has(X86_FEATURE_RTM)) { 7119 struct shared_msr_entry *msr; 7120 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7121 if (msr) { 7122 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7123 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7124 } 7125 } 7126 } 7127 7128 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 7129 { 7130 if (func == 1 && nested) 7131 entry->ecx |= bit(X86_FEATURE_VMX); 7132 } 7133 7134 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7135 { 7136 to_vmx(vcpu)->req_immediate_exit = true; 7137 } 7138 7139 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7140 struct x86_instruction_info *info, 7141 enum x86_intercept_stage stage) 7142 { 7143 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7144 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7145 7146 /* 7147 * RDPID causes #UD if disabled through secondary execution controls. 7148 * Because it is marked as EmulateOnUD, we need to intercept it here. 7149 */ 7150 if (info->intercept == x86_intercept_rdtscp && 7151 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7152 ctxt->exception.vector = UD_VECTOR; 7153 ctxt->exception.error_code_valid = false; 7154 return X86EMUL_PROPAGATE_FAULT; 7155 } 7156 7157 /* TODO: check more intercepts... */ 7158 return X86EMUL_CONTINUE; 7159 } 7160 7161 #ifdef CONFIG_X86_64 7162 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7163 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7164 u64 divisor, u64 *result) 7165 { 7166 u64 low = a << shift, high = a >> (64 - shift); 7167 7168 /* To avoid the overflow on divq */ 7169 if (high >= divisor) 7170 return 1; 7171 7172 /* Low hold the result, high hold rem which is discarded */ 7173 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7174 "rm" (divisor), "0" (low), "1" (high)); 7175 *result = low; 7176 7177 return 0; 7178 } 7179 7180 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7181 bool *expired) 7182 { 7183 struct vcpu_vmx *vmx; 7184 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7185 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7186 7187 if (kvm_mwait_in_guest(vcpu->kvm) || 7188 kvm_can_post_timer_interrupt(vcpu)) 7189 return -EOPNOTSUPP; 7190 7191 vmx = to_vmx(vcpu); 7192 tscl = rdtsc(); 7193 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7194 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7195 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7196 ktimer->timer_advance_ns); 7197 7198 if (delta_tsc > lapic_timer_advance_cycles) 7199 delta_tsc -= lapic_timer_advance_cycles; 7200 else 7201 delta_tsc = 0; 7202 7203 /* Convert to host delta tsc if tsc scaling is enabled */ 7204 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7205 delta_tsc && u64_shl_div_u64(delta_tsc, 7206 kvm_tsc_scaling_ratio_frac_bits, 7207 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7208 return -ERANGE; 7209 7210 /* 7211 * If the delta tsc can't fit in the 32 bit after the multi shift, 7212 * we can't use the preemption timer. 7213 * It's possible that it fits on later vmentries, but checking 7214 * on every vmentry is costly so we just use an hrtimer. 7215 */ 7216 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7217 return -ERANGE; 7218 7219 vmx->hv_deadline_tsc = tscl + delta_tsc; 7220 *expired = !delta_tsc; 7221 return 0; 7222 } 7223 7224 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7225 { 7226 to_vmx(vcpu)->hv_deadline_tsc = -1; 7227 } 7228 #endif 7229 7230 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7231 { 7232 if (!kvm_pause_in_guest(vcpu->kvm)) 7233 shrink_ple_window(vcpu); 7234 } 7235 7236 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7237 struct kvm_memory_slot *slot) 7238 { 7239 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7240 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7241 } 7242 7243 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7244 struct kvm_memory_slot *slot) 7245 { 7246 kvm_mmu_slot_set_dirty(kvm, slot); 7247 } 7248 7249 static void vmx_flush_log_dirty(struct kvm *kvm) 7250 { 7251 kvm_flush_pml_buffers(kvm); 7252 } 7253 7254 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7255 { 7256 struct vmcs12 *vmcs12; 7257 struct vcpu_vmx *vmx = to_vmx(vcpu); 7258 gpa_t gpa, dst; 7259 7260 if (is_guest_mode(vcpu)) { 7261 WARN_ON_ONCE(vmx->nested.pml_full); 7262 7263 /* 7264 * Check if PML is enabled for the nested guest. 7265 * Whether eptp bit 6 is set is already checked 7266 * as part of A/D emulation. 7267 */ 7268 vmcs12 = get_vmcs12(vcpu); 7269 if (!nested_cpu_has_pml(vmcs12)) 7270 return 0; 7271 7272 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7273 vmx->nested.pml_full = true; 7274 return 1; 7275 } 7276 7277 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7278 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7279 7280 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7281 offset_in_page(dst), sizeof(gpa))) 7282 return 0; 7283 7284 vmcs12->guest_pml_index--; 7285 } 7286 7287 return 0; 7288 } 7289 7290 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7291 struct kvm_memory_slot *memslot, 7292 gfn_t offset, unsigned long mask) 7293 { 7294 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7295 } 7296 7297 static void __pi_post_block(struct kvm_vcpu *vcpu) 7298 { 7299 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7300 struct pi_desc old, new; 7301 unsigned int dest; 7302 7303 do { 7304 old.control = new.control = pi_desc->control; 7305 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7306 "Wakeup handler not enabled while the VCPU is blocked\n"); 7307 7308 dest = cpu_physical_id(vcpu->cpu); 7309 7310 if (x2apic_enabled()) 7311 new.ndst = dest; 7312 else 7313 new.ndst = (dest << 8) & 0xFF00; 7314 7315 /* set 'NV' to 'notification vector' */ 7316 new.nv = POSTED_INTR_VECTOR; 7317 } while (cmpxchg64(&pi_desc->control, old.control, 7318 new.control) != old.control); 7319 7320 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7321 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7322 list_del(&vcpu->blocked_vcpu_list); 7323 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7324 vcpu->pre_pcpu = -1; 7325 } 7326 } 7327 7328 /* 7329 * This routine does the following things for vCPU which is going 7330 * to be blocked if VT-d PI is enabled. 7331 * - Store the vCPU to the wakeup list, so when interrupts happen 7332 * we can find the right vCPU to wake up. 7333 * - Change the Posted-interrupt descriptor as below: 7334 * 'NDST' <-- vcpu->pre_pcpu 7335 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7336 * - If 'ON' is set during this process, which means at least one 7337 * interrupt is posted for this vCPU, we cannot block it, in 7338 * this case, return 1, otherwise, return 0. 7339 * 7340 */ 7341 static int pi_pre_block(struct kvm_vcpu *vcpu) 7342 { 7343 unsigned int dest; 7344 struct pi_desc old, new; 7345 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7346 7347 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7348 !irq_remapping_cap(IRQ_POSTING_CAP) || 7349 !kvm_vcpu_apicv_active(vcpu)) 7350 return 0; 7351 7352 WARN_ON(irqs_disabled()); 7353 local_irq_disable(); 7354 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7355 vcpu->pre_pcpu = vcpu->cpu; 7356 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7357 list_add_tail(&vcpu->blocked_vcpu_list, 7358 &per_cpu(blocked_vcpu_on_cpu, 7359 vcpu->pre_pcpu)); 7360 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7361 } 7362 7363 do { 7364 old.control = new.control = pi_desc->control; 7365 7366 WARN((pi_desc->sn == 1), 7367 "Warning: SN field of posted-interrupts " 7368 "is set before blocking\n"); 7369 7370 /* 7371 * Since vCPU can be preempted during this process, 7372 * vcpu->cpu could be different with pre_pcpu, we 7373 * need to set pre_pcpu as the destination of wakeup 7374 * notification event, then we can find the right vCPU 7375 * to wakeup in wakeup handler if interrupts happen 7376 * when the vCPU is in blocked state. 7377 */ 7378 dest = cpu_physical_id(vcpu->pre_pcpu); 7379 7380 if (x2apic_enabled()) 7381 new.ndst = dest; 7382 else 7383 new.ndst = (dest << 8) & 0xFF00; 7384 7385 /* set 'NV' to 'wakeup vector' */ 7386 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7387 } while (cmpxchg64(&pi_desc->control, old.control, 7388 new.control) != old.control); 7389 7390 /* We should not block the vCPU if an interrupt is posted for it. */ 7391 if (pi_test_on(pi_desc) == 1) 7392 __pi_post_block(vcpu); 7393 7394 local_irq_enable(); 7395 return (vcpu->pre_pcpu == -1); 7396 } 7397 7398 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7399 { 7400 if (pi_pre_block(vcpu)) 7401 return 1; 7402 7403 if (kvm_lapic_hv_timer_in_use(vcpu)) 7404 kvm_lapic_switch_to_sw_timer(vcpu); 7405 7406 return 0; 7407 } 7408 7409 static void pi_post_block(struct kvm_vcpu *vcpu) 7410 { 7411 if (vcpu->pre_pcpu == -1) 7412 return; 7413 7414 WARN_ON(irqs_disabled()); 7415 local_irq_disable(); 7416 __pi_post_block(vcpu); 7417 local_irq_enable(); 7418 } 7419 7420 static void vmx_post_block(struct kvm_vcpu *vcpu) 7421 { 7422 if (kvm_x86_ops->set_hv_timer) 7423 kvm_lapic_switch_to_hv_timer(vcpu); 7424 7425 pi_post_block(vcpu); 7426 } 7427 7428 /* 7429 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7430 * 7431 * @kvm: kvm 7432 * @host_irq: host irq of the interrupt 7433 * @guest_irq: gsi of the interrupt 7434 * @set: set or unset PI 7435 * returns 0 on success, < 0 on failure 7436 */ 7437 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7438 uint32_t guest_irq, bool set) 7439 { 7440 struct kvm_kernel_irq_routing_entry *e; 7441 struct kvm_irq_routing_table *irq_rt; 7442 struct kvm_lapic_irq irq; 7443 struct kvm_vcpu *vcpu; 7444 struct vcpu_data vcpu_info; 7445 int idx, ret = 0; 7446 7447 if (!kvm_arch_has_assigned_device(kvm) || 7448 !irq_remapping_cap(IRQ_POSTING_CAP) || 7449 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7450 return 0; 7451 7452 idx = srcu_read_lock(&kvm->irq_srcu); 7453 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7454 if (guest_irq >= irq_rt->nr_rt_entries || 7455 hlist_empty(&irq_rt->map[guest_irq])) { 7456 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7457 guest_irq, irq_rt->nr_rt_entries); 7458 goto out; 7459 } 7460 7461 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7462 if (e->type != KVM_IRQ_ROUTING_MSI) 7463 continue; 7464 /* 7465 * VT-d PI cannot support posting multicast/broadcast 7466 * interrupts to a vCPU, we still use interrupt remapping 7467 * for these kind of interrupts. 7468 * 7469 * For lowest-priority interrupts, we only support 7470 * those with single CPU as the destination, e.g. user 7471 * configures the interrupts via /proc/irq or uses 7472 * irqbalance to make the interrupts single-CPU. 7473 * 7474 * We will support full lowest-priority interrupt later. 7475 * 7476 * In addition, we can only inject generic interrupts using 7477 * the PI mechanism, refuse to route others through it. 7478 */ 7479 7480 kvm_set_msi_irq(kvm, e, &irq); 7481 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7482 !kvm_irq_is_postable(&irq)) { 7483 /* 7484 * Make sure the IRTE is in remapped mode if 7485 * we don't handle it in posted mode. 7486 */ 7487 ret = irq_set_vcpu_affinity(host_irq, NULL); 7488 if (ret < 0) { 7489 printk(KERN_INFO 7490 "failed to back to remapped mode, irq: %u\n", 7491 host_irq); 7492 goto out; 7493 } 7494 7495 continue; 7496 } 7497 7498 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7499 vcpu_info.vector = irq.vector; 7500 7501 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7502 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7503 7504 if (set) 7505 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7506 else 7507 ret = irq_set_vcpu_affinity(host_irq, NULL); 7508 7509 if (ret < 0) { 7510 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7511 __func__); 7512 goto out; 7513 } 7514 } 7515 7516 ret = 0; 7517 out: 7518 srcu_read_unlock(&kvm->irq_srcu, idx); 7519 return ret; 7520 } 7521 7522 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7523 { 7524 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7525 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7526 FEATURE_CONTROL_LMCE; 7527 else 7528 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7529 ~FEATURE_CONTROL_LMCE; 7530 } 7531 7532 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7533 { 7534 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7535 if (to_vmx(vcpu)->nested.nested_run_pending) 7536 return 0; 7537 return 1; 7538 } 7539 7540 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7541 { 7542 struct vcpu_vmx *vmx = to_vmx(vcpu); 7543 7544 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7545 if (vmx->nested.smm.guest_mode) 7546 nested_vmx_vmexit(vcpu, -1, 0, 0); 7547 7548 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7549 vmx->nested.vmxon = false; 7550 vmx_clear_hlt(vcpu); 7551 return 0; 7552 } 7553 7554 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7555 { 7556 struct vcpu_vmx *vmx = to_vmx(vcpu); 7557 int ret; 7558 7559 if (vmx->nested.smm.vmxon) { 7560 vmx->nested.vmxon = true; 7561 vmx->nested.smm.vmxon = false; 7562 } 7563 7564 if (vmx->nested.smm.guest_mode) { 7565 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7566 if (ret) 7567 return ret; 7568 7569 vmx->nested.smm.guest_mode = false; 7570 } 7571 return 0; 7572 } 7573 7574 static int enable_smi_window(struct kvm_vcpu *vcpu) 7575 { 7576 return 0; 7577 } 7578 7579 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7580 { 7581 return false; 7582 } 7583 7584 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7585 { 7586 return to_vmx(vcpu)->nested.vmxon; 7587 } 7588 7589 static __init int hardware_setup(void) 7590 { 7591 unsigned long host_bndcfgs; 7592 struct desc_ptr dt; 7593 int r, i; 7594 7595 rdmsrl_safe(MSR_EFER, &host_efer); 7596 7597 store_idt(&dt); 7598 host_idt_base = dt.address; 7599 7600 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7601 kvm_define_shared_msr(i, vmx_msr_index[i]); 7602 7603 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7604 return -EIO; 7605 7606 if (boot_cpu_has(X86_FEATURE_NX)) 7607 kvm_enable_efer_bits(EFER_NX); 7608 7609 if (boot_cpu_has(X86_FEATURE_MPX)) { 7610 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7611 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7612 } 7613 7614 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7615 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7616 enable_vpid = 0; 7617 7618 if (!cpu_has_vmx_ept() || 7619 !cpu_has_vmx_ept_4levels() || 7620 !cpu_has_vmx_ept_mt_wb() || 7621 !cpu_has_vmx_invept_global()) 7622 enable_ept = 0; 7623 7624 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7625 enable_ept_ad_bits = 0; 7626 7627 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7628 enable_unrestricted_guest = 0; 7629 7630 if (!cpu_has_vmx_flexpriority()) 7631 flexpriority_enabled = 0; 7632 7633 if (!cpu_has_virtual_nmis()) 7634 enable_vnmi = 0; 7635 7636 /* 7637 * set_apic_access_page_addr() is used to reload apic access 7638 * page upon invalidation. No need to do anything if not 7639 * using the APIC_ACCESS_ADDR VMCS field. 7640 */ 7641 if (!flexpriority_enabled) 7642 kvm_x86_ops->set_apic_access_page_addr = NULL; 7643 7644 if (!cpu_has_vmx_tpr_shadow()) 7645 kvm_x86_ops->update_cr8_intercept = NULL; 7646 7647 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7648 kvm_disable_largepages(); 7649 7650 #if IS_ENABLED(CONFIG_HYPERV) 7651 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7652 && enable_ept) { 7653 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7654 kvm_x86_ops->tlb_remote_flush_with_range = 7655 hv_remote_flush_tlb_with_range; 7656 } 7657 #endif 7658 7659 if (!cpu_has_vmx_ple()) { 7660 ple_gap = 0; 7661 ple_window = 0; 7662 ple_window_grow = 0; 7663 ple_window_max = 0; 7664 ple_window_shrink = 0; 7665 } 7666 7667 if (!cpu_has_vmx_apicv()) { 7668 enable_apicv = 0; 7669 kvm_x86_ops->sync_pir_to_irr = NULL; 7670 } 7671 7672 if (cpu_has_vmx_tsc_scaling()) { 7673 kvm_has_tsc_control = true; 7674 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7675 kvm_tsc_scaling_ratio_frac_bits = 48; 7676 } 7677 7678 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7679 7680 if (enable_ept) 7681 vmx_enable_tdp(); 7682 else 7683 kvm_disable_tdp(); 7684 7685 /* 7686 * Only enable PML when hardware supports PML feature, and both EPT 7687 * and EPT A/D bit features are enabled -- PML depends on them to work. 7688 */ 7689 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7690 enable_pml = 0; 7691 7692 if (!enable_pml) { 7693 kvm_x86_ops->slot_enable_log_dirty = NULL; 7694 kvm_x86_ops->slot_disable_log_dirty = NULL; 7695 kvm_x86_ops->flush_log_dirty = NULL; 7696 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7697 } 7698 7699 if (!cpu_has_vmx_preemption_timer()) 7700 enable_preemption_timer = false; 7701 7702 if (enable_preemption_timer) { 7703 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7704 u64 vmx_msr; 7705 7706 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7707 cpu_preemption_timer_multi = 7708 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7709 7710 if (tsc_khz) 7711 use_timer_freq = (u64)tsc_khz * 1000; 7712 use_timer_freq >>= cpu_preemption_timer_multi; 7713 7714 /* 7715 * KVM "disables" the preemption timer by setting it to its max 7716 * value. Don't use the timer if it might cause spurious exits 7717 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7718 */ 7719 if (use_timer_freq > 0xffffffffu / 10) 7720 enable_preemption_timer = false; 7721 } 7722 7723 if (!enable_preemption_timer) { 7724 kvm_x86_ops->set_hv_timer = NULL; 7725 kvm_x86_ops->cancel_hv_timer = NULL; 7726 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7727 } 7728 7729 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7730 7731 kvm_mce_cap_supported |= MCG_LMCE_P; 7732 7733 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7734 return -EINVAL; 7735 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7736 pt_mode = PT_MODE_SYSTEM; 7737 7738 if (nested) { 7739 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7740 vmx_capability.ept, enable_apicv); 7741 7742 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7743 if (r) 7744 return r; 7745 } 7746 7747 r = alloc_kvm_area(); 7748 if (r) 7749 nested_vmx_hardware_unsetup(); 7750 return r; 7751 } 7752 7753 static __exit void hardware_unsetup(void) 7754 { 7755 if (nested) 7756 nested_vmx_hardware_unsetup(); 7757 7758 free_kvm_area(); 7759 } 7760 7761 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7762 .cpu_has_kvm_support = cpu_has_kvm_support, 7763 .disabled_by_bios = vmx_disabled_by_bios, 7764 .hardware_setup = hardware_setup, 7765 .hardware_unsetup = hardware_unsetup, 7766 .check_processor_compatibility = vmx_check_processor_compat, 7767 .hardware_enable = hardware_enable, 7768 .hardware_disable = hardware_disable, 7769 .cpu_has_accelerated_tpr = report_flexpriority, 7770 .has_emulated_msr = vmx_has_emulated_msr, 7771 7772 .vm_init = vmx_vm_init, 7773 .vm_alloc = vmx_vm_alloc, 7774 .vm_free = vmx_vm_free, 7775 7776 .vcpu_create = vmx_create_vcpu, 7777 .vcpu_free = vmx_free_vcpu, 7778 .vcpu_reset = vmx_vcpu_reset, 7779 7780 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7781 .vcpu_load = vmx_vcpu_load, 7782 .vcpu_put = vmx_vcpu_put, 7783 7784 .update_bp_intercept = update_exception_bitmap, 7785 .get_msr_feature = vmx_get_msr_feature, 7786 .get_msr = vmx_get_msr, 7787 .set_msr = vmx_set_msr, 7788 .get_segment_base = vmx_get_segment_base, 7789 .get_segment = vmx_get_segment, 7790 .set_segment = vmx_set_segment, 7791 .get_cpl = vmx_get_cpl, 7792 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7793 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7794 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7795 .set_cr0 = vmx_set_cr0, 7796 .set_cr3 = vmx_set_cr3, 7797 .set_cr4 = vmx_set_cr4, 7798 .set_efer = vmx_set_efer, 7799 .get_idt = vmx_get_idt, 7800 .set_idt = vmx_set_idt, 7801 .get_gdt = vmx_get_gdt, 7802 .set_gdt = vmx_set_gdt, 7803 .get_dr6 = vmx_get_dr6, 7804 .set_dr6 = vmx_set_dr6, 7805 .set_dr7 = vmx_set_dr7, 7806 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7807 .cache_reg = vmx_cache_reg, 7808 .get_rflags = vmx_get_rflags, 7809 .set_rflags = vmx_set_rflags, 7810 7811 .tlb_flush = vmx_flush_tlb, 7812 .tlb_flush_gva = vmx_flush_tlb_gva, 7813 7814 .run = vmx_vcpu_run, 7815 .handle_exit = vmx_handle_exit, 7816 .skip_emulated_instruction = skip_emulated_instruction, 7817 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7818 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7819 .patch_hypercall = vmx_patch_hypercall, 7820 .set_irq = vmx_inject_irq, 7821 .set_nmi = vmx_inject_nmi, 7822 .queue_exception = vmx_queue_exception, 7823 .cancel_injection = vmx_cancel_injection, 7824 .interrupt_allowed = vmx_interrupt_allowed, 7825 .nmi_allowed = vmx_nmi_allowed, 7826 .get_nmi_mask = vmx_get_nmi_mask, 7827 .set_nmi_mask = vmx_set_nmi_mask, 7828 .enable_nmi_window = enable_nmi_window, 7829 .enable_irq_window = enable_irq_window, 7830 .update_cr8_intercept = update_cr8_intercept, 7831 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7832 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7833 .get_enable_apicv = vmx_get_enable_apicv, 7834 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7835 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7836 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7837 .hwapic_irr_update = vmx_hwapic_irr_update, 7838 .hwapic_isr_update = vmx_hwapic_isr_update, 7839 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7840 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7841 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7842 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7843 7844 .set_tss_addr = vmx_set_tss_addr, 7845 .set_identity_map_addr = vmx_set_identity_map_addr, 7846 .get_tdp_level = get_ept_level, 7847 .get_mt_mask = vmx_get_mt_mask, 7848 7849 .get_exit_info = vmx_get_exit_info, 7850 7851 .get_lpage_level = vmx_get_lpage_level, 7852 7853 .cpuid_update = vmx_cpuid_update, 7854 7855 .rdtscp_supported = vmx_rdtscp_supported, 7856 .invpcid_supported = vmx_invpcid_supported, 7857 7858 .set_supported_cpuid = vmx_set_supported_cpuid, 7859 7860 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7861 7862 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7863 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7864 7865 .set_tdp_cr3 = vmx_set_cr3, 7866 7867 .check_intercept = vmx_check_intercept, 7868 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7869 .mpx_supported = vmx_mpx_supported, 7870 .xsaves_supported = vmx_xsaves_supported, 7871 .umip_emulated = vmx_umip_emulated, 7872 .pt_supported = vmx_pt_supported, 7873 7874 .request_immediate_exit = vmx_request_immediate_exit, 7875 7876 .sched_in = vmx_sched_in, 7877 7878 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7879 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7880 .flush_log_dirty = vmx_flush_log_dirty, 7881 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7882 .write_log_dirty = vmx_write_pml_buffer, 7883 7884 .pre_block = vmx_pre_block, 7885 .post_block = vmx_post_block, 7886 7887 .pmu_ops = &intel_pmu_ops, 7888 7889 .update_pi_irte = vmx_update_pi_irte, 7890 7891 #ifdef CONFIG_X86_64 7892 .set_hv_timer = vmx_set_hv_timer, 7893 .cancel_hv_timer = vmx_cancel_hv_timer, 7894 #endif 7895 7896 .setup_mce = vmx_setup_mce, 7897 7898 .smi_allowed = vmx_smi_allowed, 7899 .pre_enter_smm = vmx_pre_enter_smm, 7900 .pre_leave_smm = vmx_pre_leave_smm, 7901 .enable_smi_window = enable_smi_window, 7902 7903 .check_nested_events = NULL, 7904 .get_nested_state = NULL, 7905 .set_nested_state = NULL, 7906 .get_vmcs12_pages = NULL, 7907 .nested_enable_evmcs = NULL, 7908 .nested_get_evmcs_version = NULL, 7909 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7910 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7911 }; 7912 7913 static void vmx_cleanup_l1d_flush(void) 7914 { 7915 if (vmx_l1d_flush_pages) { 7916 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7917 vmx_l1d_flush_pages = NULL; 7918 } 7919 /* Restore state so sysfs ignores VMX */ 7920 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 7921 } 7922 7923 static void vmx_exit(void) 7924 { 7925 #ifdef CONFIG_KEXEC_CORE 7926 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 7927 synchronize_rcu(); 7928 #endif 7929 7930 kvm_exit(); 7931 7932 #if IS_ENABLED(CONFIG_HYPERV) 7933 if (static_branch_unlikely(&enable_evmcs)) { 7934 int cpu; 7935 struct hv_vp_assist_page *vp_ap; 7936 /* 7937 * Reset everything to support using non-enlightened VMCS 7938 * access later (e.g. when we reload the module with 7939 * enlightened_vmcs=0) 7940 */ 7941 for_each_online_cpu(cpu) { 7942 vp_ap = hv_get_vp_assist_page(cpu); 7943 7944 if (!vp_ap) 7945 continue; 7946 7947 vp_ap->nested_control.features.directhypercall = 0; 7948 vp_ap->current_nested_vmcs = 0; 7949 vp_ap->enlighten_vmentry = 0; 7950 } 7951 7952 static_branch_disable(&enable_evmcs); 7953 } 7954 #endif 7955 vmx_cleanup_l1d_flush(); 7956 } 7957 module_exit(vmx_exit); 7958 7959 static int __init vmx_init(void) 7960 { 7961 int r; 7962 7963 #if IS_ENABLED(CONFIG_HYPERV) 7964 /* 7965 * Enlightened VMCS usage should be recommended and the host needs 7966 * to support eVMCS v1 or above. We can also disable eVMCS support 7967 * with module parameter. 7968 */ 7969 if (enlightened_vmcs && 7970 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 7971 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 7972 KVM_EVMCS_VERSION) { 7973 int cpu; 7974 7975 /* Check that we have assist pages on all online CPUs */ 7976 for_each_online_cpu(cpu) { 7977 if (!hv_get_vp_assist_page(cpu)) { 7978 enlightened_vmcs = false; 7979 break; 7980 } 7981 } 7982 7983 if (enlightened_vmcs) { 7984 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 7985 static_branch_enable(&enable_evmcs); 7986 } 7987 7988 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 7989 vmx_x86_ops.enable_direct_tlbflush 7990 = hv_enable_direct_tlbflush; 7991 7992 } else { 7993 enlightened_vmcs = false; 7994 } 7995 #endif 7996 7997 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 7998 __alignof__(struct vcpu_vmx), THIS_MODULE); 7999 if (r) 8000 return r; 8001 8002 /* 8003 * Must be called after kvm_init() so enable_ept is properly set 8004 * up. Hand the parameter mitigation value in which was stored in 8005 * the pre module init parser. If no parameter was given, it will 8006 * contain 'auto' which will be turned into the default 'cond' 8007 * mitigation mode. 8008 */ 8009 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 8010 if (r) { 8011 vmx_exit(); 8012 return r; 8013 } 8014 8015 #ifdef CONFIG_KEXEC_CORE 8016 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 8017 crash_vmclear_local_loaded_vmcss); 8018 #endif 8019 vmx_check_vmcs12_offsets(); 8020 8021 return 0; 8022 } 8023 module_init(vmx_init); 8024