1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * This module enables machines with Intel VT-x extensions to run virtual 5 * machines without emulation or binary translation. 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Avi Kivity <avi@qumranet.com> 12 * Yaniv Kamay <yaniv@qumranet.com> 13 * 14 * This work is licensed under the terms of the GNU GPL, version 2. See 15 * the COPYING file in the top-level directory. 16 * 17 */ 18 19 #include <linux/frame.h> 20 #include <linux/highmem.h> 21 #include <linux/hrtimer.h> 22 #include <linux/kernel.h> 23 #include <linux/kvm_host.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/mod_devicetable.h> 27 #include <linux/mm.h> 28 #include <linux/sched.h> 29 #include <linux/sched/smt.h> 30 #include <linux/slab.h> 31 #include <linux/tboot.h> 32 #include <linux/trace_events.h> 33 34 #include <asm/apic.h> 35 #include <asm/asm.h> 36 #include <asm/cpu.h> 37 #include <asm/debugreg.h> 38 #include <asm/desc.h> 39 #include <asm/fpu/internal.h> 40 #include <asm/io.h> 41 #include <asm/irq_remapping.h> 42 #include <asm/kexec.h> 43 #include <asm/perf_event.h> 44 #include <asm/mce.h> 45 #include <asm/mmu_context.h> 46 #include <asm/mshyperv.h> 47 #include <asm/spec-ctrl.h> 48 #include <asm/virtext.h> 49 #include <asm/vmx.h> 50 51 #include "capabilities.h" 52 #include "cpuid.h" 53 #include "evmcs.h" 54 #include "irq.h" 55 #include "kvm_cache_regs.h" 56 #include "lapic.h" 57 #include "mmu.h" 58 #include "nested.h" 59 #include "ops.h" 60 #include "pmu.h" 61 #include "trace.h" 62 #include "vmcs.h" 63 #include "vmcs12.h" 64 #include "vmx.h" 65 #include "x86.h" 66 67 MODULE_AUTHOR("Qumranet"); 68 MODULE_LICENSE("GPL"); 69 70 static const struct x86_cpu_id vmx_cpu_id[] = { 71 X86_FEATURE_MATCH(X86_FEATURE_VMX), 72 {} 73 }; 74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 75 76 bool __read_mostly enable_vpid = 1; 77 module_param_named(vpid, enable_vpid, bool, 0444); 78 79 static bool __read_mostly enable_vnmi = 1; 80 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 81 82 bool __read_mostly flexpriority_enabled = 1; 83 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 84 85 bool __read_mostly enable_ept = 1; 86 module_param_named(ept, enable_ept, bool, S_IRUGO); 87 88 bool __read_mostly enable_unrestricted_guest = 1; 89 module_param_named(unrestricted_guest, 90 enable_unrestricted_guest, bool, S_IRUGO); 91 92 bool __read_mostly enable_ept_ad_bits = 1; 93 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 94 95 static bool __read_mostly emulate_invalid_guest_state = true; 96 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 97 98 static bool __read_mostly fasteoi = 1; 99 module_param(fasteoi, bool, S_IRUGO); 100 101 static bool __read_mostly enable_apicv = 1; 102 module_param(enable_apicv, bool, S_IRUGO); 103 104 /* 105 * If nested=1, nested virtualization is supported, i.e., guests may use 106 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 107 * use VMX instructions. 108 */ 109 static bool __read_mostly nested = 1; 110 module_param(nested, bool, S_IRUGO); 111 112 static u64 __read_mostly host_xss; 113 114 bool __read_mostly enable_pml = 1; 115 module_param_named(pml, enable_pml, bool, S_IRUGO); 116 117 #define MSR_BITMAP_MODE_X2APIC 1 118 #define MSR_BITMAP_MODE_X2APIC_APICV 2 119 120 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 121 122 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 123 static int __read_mostly cpu_preemption_timer_multi; 124 static bool __read_mostly enable_preemption_timer = 1; 125 #ifdef CONFIG_X86_64 126 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 127 #endif 128 129 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 130 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 131 #define KVM_VM_CR0_ALWAYS_ON \ 132 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 133 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 134 #define KVM_CR4_GUEST_OWNED_BITS \ 135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 137 138 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 141 142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 143 144 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 145 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 146 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 147 RTIT_STATUS_BYTECNT)) 148 149 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 150 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 151 152 /* 153 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 154 * ple_gap: upper bound on the amount of time between two successive 155 * executions of PAUSE in a loop. Also indicate if ple enabled. 156 * According to test, this time is usually smaller than 128 cycles. 157 * ple_window: upper bound on the amount of time a guest is allowed to execute 158 * in a PAUSE loop. Tests indicate that most spinlocks are held for 159 * less than 2^12 cycles 160 * Time is measured based on a counter that runs at the same rate as the TSC, 161 * refer SDM volume 3b section 21.6.13 & 22.1.3. 162 */ 163 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 164 module_param(ple_gap, uint, 0444); 165 166 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 167 module_param(ple_window, uint, 0444); 168 169 /* Default doubles per-vcpu window every exit. */ 170 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 171 module_param(ple_window_grow, uint, 0444); 172 173 /* Default resets per-vcpu window every exit to ple_window. */ 174 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 175 module_param(ple_window_shrink, uint, 0444); 176 177 /* Default is to compute the maximum so we can never overflow. */ 178 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 179 module_param(ple_window_max, uint, 0444); 180 181 /* Default is SYSTEM mode, 1 for host-guest mode */ 182 int __read_mostly pt_mode = PT_MODE_SYSTEM; 183 module_param(pt_mode, int, S_IRUGO); 184 185 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 186 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 187 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 188 189 /* Storage for pre module init parameter parsing */ 190 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 191 192 static const struct { 193 const char *option; 194 bool for_parse; 195 } vmentry_l1d_param[] = { 196 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 197 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 198 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 199 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 200 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 201 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 202 }; 203 204 #define L1D_CACHE_ORDER 4 205 static void *vmx_l1d_flush_pages; 206 207 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 208 { 209 struct page *page; 210 unsigned int i; 211 212 if (!enable_ept) { 213 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 214 return 0; 215 } 216 217 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 218 u64 msr; 219 220 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 221 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 222 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 223 return 0; 224 } 225 } 226 227 /* If set to auto use the default l1tf mitigation method */ 228 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 229 switch (l1tf_mitigation) { 230 case L1TF_MITIGATION_OFF: 231 l1tf = VMENTER_L1D_FLUSH_NEVER; 232 break; 233 case L1TF_MITIGATION_FLUSH_NOWARN: 234 case L1TF_MITIGATION_FLUSH: 235 case L1TF_MITIGATION_FLUSH_NOSMT: 236 l1tf = VMENTER_L1D_FLUSH_COND; 237 break; 238 case L1TF_MITIGATION_FULL: 239 case L1TF_MITIGATION_FULL_FORCE: 240 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 241 break; 242 } 243 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 244 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 245 } 246 247 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 248 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 249 /* 250 * This allocation for vmx_l1d_flush_pages is not tied to a VM 251 * lifetime and so should not be charged to a memcg. 252 */ 253 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 254 if (!page) 255 return -ENOMEM; 256 vmx_l1d_flush_pages = page_address(page); 257 258 /* 259 * Initialize each page with a different pattern in 260 * order to protect against KSM in the nested 261 * virtualization case. 262 */ 263 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 264 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 265 PAGE_SIZE); 266 } 267 } 268 269 l1tf_vmx_mitigation = l1tf; 270 271 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 272 static_branch_enable(&vmx_l1d_should_flush); 273 else 274 static_branch_disable(&vmx_l1d_should_flush); 275 276 if (l1tf == VMENTER_L1D_FLUSH_COND) 277 static_branch_enable(&vmx_l1d_flush_cond); 278 else 279 static_branch_disable(&vmx_l1d_flush_cond); 280 return 0; 281 } 282 283 static int vmentry_l1d_flush_parse(const char *s) 284 { 285 unsigned int i; 286 287 if (s) { 288 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 289 if (vmentry_l1d_param[i].for_parse && 290 sysfs_streq(s, vmentry_l1d_param[i].option)) 291 return i; 292 } 293 } 294 return -EINVAL; 295 } 296 297 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 298 { 299 int l1tf, ret; 300 301 l1tf = vmentry_l1d_flush_parse(s); 302 if (l1tf < 0) 303 return l1tf; 304 305 if (!boot_cpu_has(X86_BUG_L1TF)) 306 return 0; 307 308 /* 309 * Has vmx_init() run already? If not then this is the pre init 310 * parameter parsing. In that case just store the value and let 311 * vmx_init() do the proper setup after enable_ept has been 312 * established. 313 */ 314 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 315 vmentry_l1d_flush_param = l1tf; 316 return 0; 317 } 318 319 mutex_lock(&vmx_l1d_flush_mutex); 320 ret = vmx_setup_l1d_flush(l1tf); 321 mutex_unlock(&vmx_l1d_flush_mutex); 322 return ret; 323 } 324 325 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 326 { 327 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 328 return sprintf(s, "???\n"); 329 330 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 331 } 332 333 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 334 .set = vmentry_l1d_flush_set, 335 .get = vmentry_l1d_flush_get, 336 }; 337 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 338 339 static bool guest_state_valid(struct kvm_vcpu *vcpu); 340 static u32 vmx_segment_access_rights(struct kvm_segment *var); 341 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 342 u32 msr, int type); 343 344 void vmx_vmexit(void); 345 346 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 347 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 348 /* 349 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 350 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 351 */ 352 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 353 354 /* 355 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 356 * can find which vCPU should be waken up. 357 */ 358 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 359 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 360 361 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 362 static DEFINE_SPINLOCK(vmx_vpid_lock); 363 364 struct vmcs_config vmcs_config; 365 struct vmx_capability vmx_capability; 366 367 #define VMX_SEGMENT_FIELD(seg) \ 368 [VCPU_SREG_##seg] = { \ 369 .selector = GUEST_##seg##_SELECTOR, \ 370 .base = GUEST_##seg##_BASE, \ 371 .limit = GUEST_##seg##_LIMIT, \ 372 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 373 } 374 375 static const struct kvm_vmx_segment_field { 376 unsigned selector; 377 unsigned base; 378 unsigned limit; 379 unsigned ar_bytes; 380 } kvm_vmx_segment_fields[] = { 381 VMX_SEGMENT_FIELD(CS), 382 VMX_SEGMENT_FIELD(DS), 383 VMX_SEGMENT_FIELD(ES), 384 VMX_SEGMENT_FIELD(FS), 385 VMX_SEGMENT_FIELD(GS), 386 VMX_SEGMENT_FIELD(SS), 387 VMX_SEGMENT_FIELD(TR), 388 VMX_SEGMENT_FIELD(LDTR), 389 }; 390 391 u64 host_efer; 392 393 /* 394 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 395 * will emulate SYSCALL in legacy mode if the vendor string in guest 396 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 397 * support this emulation, IA32_STAR must always be included in 398 * vmx_msr_index[], even in i386 builds. 399 */ 400 const u32 vmx_msr_index[] = { 401 #ifdef CONFIG_X86_64 402 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 403 #endif 404 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 405 }; 406 407 #if IS_ENABLED(CONFIG_HYPERV) 408 static bool __read_mostly enlightened_vmcs = true; 409 module_param(enlightened_vmcs, bool, 0444); 410 411 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 412 static void check_ept_pointer_match(struct kvm *kvm) 413 { 414 struct kvm_vcpu *vcpu; 415 u64 tmp_eptp = INVALID_PAGE; 416 int i; 417 418 kvm_for_each_vcpu(i, vcpu, kvm) { 419 if (!VALID_PAGE(tmp_eptp)) { 420 tmp_eptp = to_vmx(vcpu)->ept_pointer; 421 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 422 to_kvm_vmx(kvm)->ept_pointers_match 423 = EPT_POINTERS_MISMATCH; 424 return; 425 } 426 } 427 428 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 429 } 430 431 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 432 void *data) 433 { 434 struct kvm_tlb_range *range = data; 435 436 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 437 range->pages); 438 } 439 440 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 441 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 442 { 443 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 444 445 /* 446 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 447 * of the base of EPT PML4 table, strip off EPT configuration 448 * information. 449 */ 450 if (range) 451 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 452 kvm_fill_hv_flush_list_func, (void *)range); 453 else 454 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 455 } 456 457 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 458 struct kvm_tlb_range *range) 459 { 460 struct kvm_vcpu *vcpu; 461 int ret = 0, i; 462 463 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 464 465 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 466 check_ept_pointer_match(kvm); 467 468 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 469 kvm_for_each_vcpu(i, vcpu, kvm) { 470 /* If ept_pointer is invalid pointer, bypass flush request. */ 471 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 472 ret |= __hv_remote_flush_tlb_with_range( 473 kvm, vcpu, range); 474 } 475 } else { 476 ret = __hv_remote_flush_tlb_with_range(kvm, 477 kvm_get_vcpu(kvm, 0), range); 478 } 479 480 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 481 return ret; 482 } 483 static int hv_remote_flush_tlb(struct kvm *kvm) 484 { 485 return hv_remote_flush_tlb_with_range(kvm, NULL); 486 } 487 488 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 489 490 /* 491 * Comment's format: document - errata name - stepping - processor name. 492 * Refer from 493 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 494 */ 495 static u32 vmx_preemption_cpu_tfms[] = { 496 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 497 0x000206E6, 498 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 499 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 500 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 501 0x00020652, 502 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 503 0x00020655, 504 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 505 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 506 /* 507 * 320767.pdf - AAP86 - B1 - 508 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 509 */ 510 0x000106E5, 511 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 512 0x000106A0, 513 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 514 0x000106A1, 515 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 516 0x000106A4, 517 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 518 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 519 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 520 0x000106A5, 521 /* Xeon E3-1220 V2 */ 522 0x000306A8, 523 }; 524 525 static inline bool cpu_has_broken_vmx_preemption_timer(void) 526 { 527 u32 eax = cpuid_eax(0x00000001), i; 528 529 /* Clear the reserved bits */ 530 eax &= ~(0x3U << 14 | 0xfU << 28); 531 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 532 if (eax == vmx_preemption_cpu_tfms[i]) 533 return true; 534 535 return false; 536 } 537 538 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 539 { 540 return flexpriority_enabled && lapic_in_kernel(vcpu); 541 } 542 543 static inline bool report_flexpriority(void) 544 { 545 return flexpriority_enabled; 546 } 547 548 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 549 { 550 int i; 551 552 for (i = 0; i < vmx->nmsrs; ++i) 553 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 554 return i; 555 return -1; 556 } 557 558 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 559 { 560 int i; 561 562 i = __find_msr_index(vmx, msr); 563 if (i >= 0) 564 return &vmx->guest_msrs[i]; 565 return NULL; 566 } 567 568 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 569 { 570 vmcs_clear(loaded_vmcs->vmcs); 571 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 572 vmcs_clear(loaded_vmcs->shadow_vmcs); 573 loaded_vmcs->cpu = -1; 574 loaded_vmcs->launched = 0; 575 } 576 577 #ifdef CONFIG_KEXEC_CORE 578 /* 579 * This bitmap is used to indicate whether the vmclear 580 * operation is enabled on all cpus. All disabled by 581 * default. 582 */ 583 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 584 585 static inline void crash_enable_local_vmclear(int cpu) 586 { 587 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 588 } 589 590 static inline void crash_disable_local_vmclear(int cpu) 591 { 592 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 593 } 594 595 static inline int crash_local_vmclear_enabled(int cpu) 596 { 597 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 598 } 599 600 static void crash_vmclear_local_loaded_vmcss(void) 601 { 602 int cpu = raw_smp_processor_id(); 603 struct loaded_vmcs *v; 604 605 if (!crash_local_vmclear_enabled(cpu)) 606 return; 607 608 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 609 loaded_vmcss_on_cpu_link) 610 vmcs_clear(v->vmcs); 611 } 612 #else 613 static inline void crash_enable_local_vmclear(int cpu) { } 614 static inline void crash_disable_local_vmclear(int cpu) { } 615 #endif /* CONFIG_KEXEC_CORE */ 616 617 static void __loaded_vmcs_clear(void *arg) 618 { 619 struct loaded_vmcs *loaded_vmcs = arg; 620 int cpu = raw_smp_processor_id(); 621 622 if (loaded_vmcs->cpu != cpu) 623 return; /* vcpu migration can race with cpu offline */ 624 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 625 per_cpu(current_vmcs, cpu) = NULL; 626 crash_disable_local_vmclear(cpu); 627 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 628 629 /* 630 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 631 * is before setting loaded_vmcs->vcpu to -1 which is done in 632 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 633 * then adds the vmcs into percpu list before it is deleted. 634 */ 635 smp_wmb(); 636 637 loaded_vmcs_init(loaded_vmcs); 638 crash_enable_local_vmclear(cpu); 639 } 640 641 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 642 { 643 int cpu = loaded_vmcs->cpu; 644 645 if (cpu != -1) 646 smp_call_function_single(cpu, 647 __loaded_vmcs_clear, loaded_vmcs, 1); 648 } 649 650 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 651 unsigned field) 652 { 653 bool ret; 654 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 655 656 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { 657 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); 658 vmx->segment_cache.bitmask = 0; 659 } 660 ret = vmx->segment_cache.bitmask & mask; 661 vmx->segment_cache.bitmask |= mask; 662 return ret; 663 } 664 665 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 666 { 667 u16 *p = &vmx->segment_cache.seg[seg].selector; 668 669 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 670 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 671 return *p; 672 } 673 674 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 675 { 676 ulong *p = &vmx->segment_cache.seg[seg].base; 677 678 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 679 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 680 return *p; 681 } 682 683 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 684 { 685 u32 *p = &vmx->segment_cache.seg[seg].limit; 686 687 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 688 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 689 return *p; 690 } 691 692 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 693 { 694 u32 *p = &vmx->segment_cache.seg[seg].ar; 695 696 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 697 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 698 return *p; 699 } 700 701 void update_exception_bitmap(struct kvm_vcpu *vcpu) 702 { 703 u32 eb; 704 705 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 706 (1u << DB_VECTOR) | (1u << AC_VECTOR); 707 /* 708 * Guest access to VMware backdoor ports could legitimately 709 * trigger #GP because of TSS I/O permission bitmap. 710 * We intercept those #GP and allow access to them anyway 711 * as VMware does. 712 */ 713 if (enable_vmware_backdoor) 714 eb |= (1u << GP_VECTOR); 715 if ((vcpu->guest_debug & 716 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 717 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 718 eb |= 1u << BP_VECTOR; 719 if (to_vmx(vcpu)->rmode.vm86_active) 720 eb = ~0; 721 if (enable_ept) 722 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 723 724 /* When we are running a nested L2 guest and L1 specified for it a 725 * certain exception bitmap, we must trap the same exceptions and pass 726 * them to L1. When running L2, we will only handle the exceptions 727 * specified above if L1 did not want them. 728 */ 729 if (is_guest_mode(vcpu)) 730 eb |= get_vmcs12(vcpu)->exception_bitmap; 731 732 vmcs_write32(EXCEPTION_BITMAP, eb); 733 } 734 735 /* 736 * Check if MSR is intercepted for currently loaded MSR bitmap. 737 */ 738 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 739 { 740 unsigned long *msr_bitmap; 741 int f = sizeof(unsigned long); 742 743 if (!cpu_has_vmx_msr_bitmap()) 744 return true; 745 746 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 747 748 if (msr <= 0x1fff) { 749 return !!test_bit(msr, msr_bitmap + 0x800 / f); 750 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 751 msr &= 0x1fff; 752 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 753 } 754 755 return true; 756 } 757 758 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 759 unsigned long entry, unsigned long exit) 760 { 761 vm_entry_controls_clearbit(vmx, entry); 762 vm_exit_controls_clearbit(vmx, exit); 763 } 764 765 static int find_msr(struct vmx_msrs *m, unsigned int msr) 766 { 767 unsigned int i; 768 769 for (i = 0; i < m->nr; ++i) { 770 if (m->val[i].index == msr) 771 return i; 772 } 773 return -ENOENT; 774 } 775 776 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 777 { 778 int i; 779 struct msr_autoload *m = &vmx->msr_autoload; 780 781 switch (msr) { 782 case MSR_EFER: 783 if (cpu_has_load_ia32_efer()) { 784 clear_atomic_switch_msr_special(vmx, 785 VM_ENTRY_LOAD_IA32_EFER, 786 VM_EXIT_LOAD_IA32_EFER); 787 return; 788 } 789 break; 790 case MSR_CORE_PERF_GLOBAL_CTRL: 791 if (cpu_has_load_perf_global_ctrl()) { 792 clear_atomic_switch_msr_special(vmx, 793 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 794 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 795 return; 796 } 797 break; 798 } 799 i = find_msr(&m->guest, msr); 800 if (i < 0) 801 goto skip_guest; 802 --m->guest.nr; 803 m->guest.val[i] = m->guest.val[m->guest.nr]; 804 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 805 806 skip_guest: 807 i = find_msr(&m->host, msr); 808 if (i < 0) 809 return; 810 811 --m->host.nr; 812 m->host.val[i] = m->host.val[m->host.nr]; 813 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 814 } 815 816 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 817 unsigned long entry, unsigned long exit, 818 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 819 u64 guest_val, u64 host_val) 820 { 821 vmcs_write64(guest_val_vmcs, guest_val); 822 if (host_val_vmcs != HOST_IA32_EFER) 823 vmcs_write64(host_val_vmcs, host_val); 824 vm_entry_controls_setbit(vmx, entry); 825 vm_exit_controls_setbit(vmx, exit); 826 } 827 828 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 829 u64 guest_val, u64 host_val, bool entry_only) 830 { 831 int i, j = 0; 832 struct msr_autoload *m = &vmx->msr_autoload; 833 834 switch (msr) { 835 case MSR_EFER: 836 if (cpu_has_load_ia32_efer()) { 837 add_atomic_switch_msr_special(vmx, 838 VM_ENTRY_LOAD_IA32_EFER, 839 VM_EXIT_LOAD_IA32_EFER, 840 GUEST_IA32_EFER, 841 HOST_IA32_EFER, 842 guest_val, host_val); 843 return; 844 } 845 break; 846 case MSR_CORE_PERF_GLOBAL_CTRL: 847 if (cpu_has_load_perf_global_ctrl()) { 848 add_atomic_switch_msr_special(vmx, 849 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 850 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 851 GUEST_IA32_PERF_GLOBAL_CTRL, 852 HOST_IA32_PERF_GLOBAL_CTRL, 853 guest_val, host_val); 854 return; 855 } 856 break; 857 case MSR_IA32_PEBS_ENABLE: 858 /* PEBS needs a quiescent period after being disabled (to write 859 * a record). Disabling PEBS through VMX MSR swapping doesn't 860 * provide that period, so a CPU could write host's record into 861 * guest's memory. 862 */ 863 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 864 } 865 866 i = find_msr(&m->guest, msr); 867 if (!entry_only) 868 j = find_msr(&m->host, msr); 869 870 if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) || 871 (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) { 872 printk_once(KERN_WARNING "Not enough msr switch entries. " 873 "Can't add msr %x\n", msr); 874 return; 875 } 876 if (i < 0) { 877 i = m->guest.nr++; 878 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 879 } 880 m->guest.val[i].index = msr; 881 m->guest.val[i].value = guest_val; 882 883 if (entry_only) 884 return; 885 886 if (j < 0) { 887 j = m->host.nr++; 888 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 889 } 890 m->host.val[j].index = msr; 891 m->host.val[j].value = host_val; 892 } 893 894 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 895 { 896 u64 guest_efer = vmx->vcpu.arch.efer; 897 u64 ignore_bits = 0; 898 899 if (!enable_ept) { 900 /* 901 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing 902 * host CPUID is more efficient than testing guest CPUID 903 * or CR4. Host SMEP is anyway a requirement for guest SMEP. 904 */ 905 if (boot_cpu_has(X86_FEATURE_SMEP)) 906 guest_efer |= EFER_NX; 907 else if (!(guest_efer & EFER_NX)) 908 ignore_bits |= EFER_NX; 909 } 910 911 /* 912 * LMA and LME handled by hardware; SCE meaningless outside long mode. 913 */ 914 ignore_bits |= EFER_SCE; 915 #ifdef CONFIG_X86_64 916 ignore_bits |= EFER_LMA | EFER_LME; 917 /* SCE is meaningful only in long mode on Intel */ 918 if (guest_efer & EFER_LMA) 919 ignore_bits &= ~(u64)EFER_SCE; 920 #endif 921 922 /* 923 * On EPT, we can't emulate NX, so we must switch EFER atomically. 924 * On CPUs that support "load IA32_EFER", always switch EFER 925 * atomically, since it's faster than switching it manually. 926 */ 927 if (cpu_has_load_ia32_efer() || 928 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 929 if (!(guest_efer & EFER_LMA)) 930 guest_efer &= ~EFER_LME; 931 if (guest_efer != host_efer) 932 add_atomic_switch_msr(vmx, MSR_EFER, 933 guest_efer, host_efer, false); 934 else 935 clear_atomic_switch_msr(vmx, MSR_EFER); 936 return false; 937 } else { 938 clear_atomic_switch_msr(vmx, MSR_EFER); 939 940 guest_efer &= ~ignore_bits; 941 guest_efer |= host_efer & ignore_bits; 942 943 vmx->guest_msrs[efer_offset].data = guest_efer; 944 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 945 946 return true; 947 } 948 } 949 950 #ifdef CONFIG_X86_32 951 /* 952 * On 32-bit kernels, VM exits still load the FS and GS bases from the 953 * VMCS rather than the segment table. KVM uses this helper to figure 954 * out the current bases to poke them into the VMCS before entry. 955 */ 956 static unsigned long segment_base(u16 selector) 957 { 958 struct desc_struct *table; 959 unsigned long v; 960 961 if (!(selector & ~SEGMENT_RPL_MASK)) 962 return 0; 963 964 table = get_current_gdt_ro(); 965 966 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 967 u16 ldt_selector = kvm_read_ldt(); 968 969 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 970 return 0; 971 972 table = (struct desc_struct *)segment_base(ldt_selector); 973 } 974 v = get_desc_base(&table[selector >> 3]); 975 return v; 976 } 977 #endif 978 979 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 980 { 981 u32 i; 982 983 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 984 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 985 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 986 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 987 for (i = 0; i < addr_range; i++) { 988 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 989 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 990 } 991 } 992 993 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 994 { 995 u32 i; 996 997 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 998 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 999 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1000 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1001 for (i = 0; i < addr_range; i++) { 1002 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1003 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1004 } 1005 } 1006 1007 static void pt_guest_enter(struct vcpu_vmx *vmx) 1008 { 1009 if (pt_mode == PT_MODE_SYSTEM) 1010 return; 1011 1012 /* 1013 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1014 * Save host state before VM entry. 1015 */ 1016 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1017 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1018 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1019 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1020 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1021 } 1022 } 1023 1024 static void pt_guest_exit(struct vcpu_vmx *vmx) 1025 { 1026 if (pt_mode == PT_MODE_SYSTEM) 1027 return; 1028 1029 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1030 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1031 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1032 } 1033 1034 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1035 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1036 } 1037 1038 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1039 { 1040 struct vcpu_vmx *vmx = to_vmx(vcpu); 1041 struct vmcs_host_state *host_state; 1042 #ifdef CONFIG_X86_64 1043 int cpu = raw_smp_processor_id(); 1044 #endif 1045 unsigned long fs_base, gs_base; 1046 u16 fs_sel, gs_sel; 1047 int i; 1048 1049 vmx->req_immediate_exit = false; 1050 1051 /* 1052 * Note that guest MSRs to be saved/restored can also be changed 1053 * when guest state is loaded. This happens when guest transitions 1054 * to/from long-mode by setting MSR_EFER.LMA. 1055 */ 1056 if (!vmx->loaded_cpu_state || vmx->guest_msrs_dirty) { 1057 vmx->guest_msrs_dirty = false; 1058 for (i = 0; i < vmx->save_nmsrs; ++i) 1059 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1060 vmx->guest_msrs[i].data, 1061 vmx->guest_msrs[i].mask); 1062 1063 } 1064 1065 if (vmx->loaded_cpu_state) 1066 return; 1067 1068 vmx->loaded_cpu_state = vmx->loaded_vmcs; 1069 host_state = &vmx->loaded_cpu_state->host_state; 1070 1071 /* 1072 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1073 * allow segment selectors with cpl > 0 or ti == 1. 1074 */ 1075 host_state->ldt_sel = kvm_read_ldt(); 1076 1077 #ifdef CONFIG_X86_64 1078 savesegment(ds, host_state->ds_sel); 1079 savesegment(es, host_state->es_sel); 1080 1081 gs_base = cpu_kernelmode_gs_base(cpu); 1082 if (likely(is_64bit_mm(current->mm))) { 1083 save_fsgs_for_kvm(); 1084 fs_sel = current->thread.fsindex; 1085 gs_sel = current->thread.gsindex; 1086 fs_base = current->thread.fsbase; 1087 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1088 } else { 1089 savesegment(fs, fs_sel); 1090 savesegment(gs, gs_sel); 1091 fs_base = read_msr(MSR_FS_BASE); 1092 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1093 } 1094 1095 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1096 #else 1097 savesegment(fs, fs_sel); 1098 savesegment(gs, gs_sel); 1099 fs_base = segment_base(fs_sel); 1100 gs_base = segment_base(gs_sel); 1101 #endif 1102 1103 if (unlikely(fs_sel != host_state->fs_sel)) { 1104 if (!(fs_sel & 7)) 1105 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1106 else 1107 vmcs_write16(HOST_FS_SELECTOR, 0); 1108 host_state->fs_sel = fs_sel; 1109 } 1110 if (unlikely(gs_sel != host_state->gs_sel)) { 1111 if (!(gs_sel & 7)) 1112 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1113 else 1114 vmcs_write16(HOST_GS_SELECTOR, 0); 1115 host_state->gs_sel = gs_sel; 1116 } 1117 if (unlikely(fs_base != host_state->fs_base)) { 1118 vmcs_writel(HOST_FS_BASE, fs_base); 1119 host_state->fs_base = fs_base; 1120 } 1121 if (unlikely(gs_base != host_state->gs_base)) { 1122 vmcs_writel(HOST_GS_BASE, gs_base); 1123 host_state->gs_base = gs_base; 1124 } 1125 } 1126 1127 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1128 { 1129 struct vmcs_host_state *host_state; 1130 1131 if (!vmx->loaded_cpu_state) 1132 return; 1133 1134 WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs); 1135 host_state = &vmx->loaded_cpu_state->host_state; 1136 1137 ++vmx->vcpu.stat.host_state_reload; 1138 vmx->loaded_cpu_state = NULL; 1139 1140 #ifdef CONFIG_X86_64 1141 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1142 #endif 1143 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1144 kvm_load_ldt(host_state->ldt_sel); 1145 #ifdef CONFIG_X86_64 1146 load_gs_index(host_state->gs_sel); 1147 #else 1148 loadsegment(gs, host_state->gs_sel); 1149 #endif 1150 } 1151 if (host_state->fs_sel & 7) 1152 loadsegment(fs, host_state->fs_sel); 1153 #ifdef CONFIG_X86_64 1154 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1155 loadsegment(ds, host_state->ds_sel); 1156 loadsegment(es, host_state->es_sel); 1157 } 1158 #endif 1159 invalidate_tss_limit(); 1160 #ifdef CONFIG_X86_64 1161 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1162 #endif 1163 load_fixmap_gdt(raw_smp_processor_id()); 1164 } 1165 1166 #ifdef CONFIG_X86_64 1167 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1168 { 1169 preempt_disable(); 1170 if (vmx->loaded_cpu_state) 1171 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1172 preempt_enable(); 1173 return vmx->msr_guest_kernel_gs_base; 1174 } 1175 1176 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1177 { 1178 preempt_disable(); 1179 if (vmx->loaded_cpu_state) 1180 wrmsrl(MSR_KERNEL_GS_BASE, data); 1181 preempt_enable(); 1182 vmx->msr_guest_kernel_gs_base = data; 1183 } 1184 #endif 1185 1186 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1187 { 1188 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1189 struct pi_desc old, new; 1190 unsigned int dest; 1191 1192 /* 1193 * In case of hot-plug or hot-unplug, we may have to undo 1194 * vmx_vcpu_pi_put even if there is no assigned device. And we 1195 * always keep PI.NDST up to date for simplicity: it makes the 1196 * code easier, and CPU migration is not a fast path. 1197 */ 1198 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1199 return; 1200 1201 /* The full case. */ 1202 do { 1203 old.control = new.control = pi_desc->control; 1204 1205 dest = cpu_physical_id(cpu); 1206 1207 if (x2apic_enabled()) 1208 new.ndst = dest; 1209 else 1210 new.ndst = (dest << 8) & 0xFF00; 1211 1212 new.sn = 0; 1213 } while (cmpxchg64(&pi_desc->control, old.control, 1214 new.control) != old.control); 1215 1216 /* 1217 * Clear SN before reading the bitmap. The VT-d firmware 1218 * writes the bitmap and reads SN atomically (5.2.3 in the 1219 * spec), so it doesn't really have a memory barrier that 1220 * pairs with this, but we cannot do that and we need one. 1221 */ 1222 smp_mb__after_atomic(); 1223 1224 if (!bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS)) 1225 pi_set_on(pi_desc); 1226 } 1227 1228 /* 1229 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1230 * vcpu mutex is already taken. 1231 */ 1232 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1233 { 1234 struct vcpu_vmx *vmx = to_vmx(vcpu); 1235 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1236 1237 if (!already_loaded) { 1238 loaded_vmcs_clear(vmx->loaded_vmcs); 1239 local_irq_disable(); 1240 crash_disable_local_vmclear(cpu); 1241 1242 /* 1243 * Read loaded_vmcs->cpu should be before fetching 1244 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1245 * See the comments in __loaded_vmcs_clear(). 1246 */ 1247 smp_rmb(); 1248 1249 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1250 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1251 crash_enable_local_vmclear(cpu); 1252 local_irq_enable(); 1253 } 1254 1255 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1256 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1257 vmcs_load(vmx->loaded_vmcs->vmcs); 1258 indirect_branch_prediction_barrier(); 1259 } 1260 1261 if (!already_loaded) { 1262 void *gdt = get_current_gdt_ro(); 1263 unsigned long sysenter_esp; 1264 1265 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1266 1267 /* 1268 * Linux uses per-cpu TSS and GDT, so set these when switching 1269 * processors. See 22.2.4. 1270 */ 1271 vmcs_writel(HOST_TR_BASE, 1272 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1273 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1274 1275 /* 1276 * VM exits change the host TR limit to 0x67 after a VM 1277 * exit. This is okay, since 0x67 covers everything except 1278 * the IO bitmap and have have code to handle the IO bitmap 1279 * being lost after a VM exit. 1280 */ 1281 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); 1282 1283 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1284 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1285 1286 vmx->loaded_vmcs->cpu = cpu; 1287 } 1288 1289 /* Setup TSC multiplier */ 1290 if (kvm_has_tsc_control && 1291 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1292 decache_tsc_multiplier(vmx); 1293 1294 vmx_vcpu_pi_load(vcpu, cpu); 1295 vmx->host_pkru = read_pkru(); 1296 vmx->host_debugctlmsr = get_debugctlmsr(); 1297 } 1298 1299 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1300 { 1301 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1302 1303 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1304 !irq_remapping_cap(IRQ_POSTING_CAP) || 1305 !kvm_vcpu_apicv_active(vcpu)) 1306 return; 1307 1308 /* Set SN when the vCPU is preempted */ 1309 if (vcpu->preempted) 1310 pi_set_sn(pi_desc); 1311 } 1312 1313 void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1314 { 1315 vmx_vcpu_pi_put(vcpu); 1316 1317 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1318 } 1319 1320 static bool emulation_required(struct kvm_vcpu *vcpu) 1321 { 1322 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1323 } 1324 1325 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); 1326 1327 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1328 { 1329 unsigned long rflags, save_rflags; 1330 1331 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { 1332 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); 1333 rflags = vmcs_readl(GUEST_RFLAGS); 1334 if (to_vmx(vcpu)->rmode.vm86_active) { 1335 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1336 save_rflags = to_vmx(vcpu)->rmode.save_rflags; 1337 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1338 } 1339 to_vmx(vcpu)->rflags = rflags; 1340 } 1341 return to_vmx(vcpu)->rflags; 1342 } 1343 1344 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1345 { 1346 unsigned long old_rflags = vmx_get_rflags(vcpu); 1347 1348 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); 1349 to_vmx(vcpu)->rflags = rflags; 1350 if (to_vmx(vcpu)->rmode.vm86_active) { 1351 to_vmx(vcpu)->rmode.save_rflags = rflags; 1352 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1353 } 1354 vmcs_writel(GUEST_RFLAGS, rflags); 1355 1356 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM) 1357 to_vmx(vcpu)->emulation_required = emulation_required(vcpu); 1358 } 1359 1360 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1361 { 1362 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1363 int ret = 0; 1364 1365 if (interruptibility & GUEST_INTR_STATE_STI) 1366 ret |= KVM_X86_SHADOW_INT_STI; 1367 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1368 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1369 1370 return ret; 1371 } 1372 1373 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1374 { 1375 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1376 u32 interruptibility = interruptibility_old; 1377 1378 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1379 1380 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1381 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1382 else if (mask & KVM_X86_SHADOW_INT_STI) 1383 interruptibility |= GUEST_INTR_STATE_STI; 1384 1385 if ((interruptibility != interruptibility_old)) 1386 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1387 } 1388 1389 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1390 { 1391 struct vcpu_vmx *vmx = to_vmx(vcpu); 1392 unsigned long value; 1393 1394 /* 1395 * Any MSR write that attempts to change bits marked reserved will 1396 * case a #GP fault. 1397 */ 1398 if (data & vmx->pt_desc.ctl_bitmask) 1399 return 1; 1400 1401 /* 1402 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1403 * result in a #GP unless the same write also clears TraceEn. 1404 */ 1405 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1406 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1407 return 1; 1408 1409 /* 1410 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1411 * and FabricEn would cause #GP, if 1412 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1413 */ 1414 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1415 !(data & RTIT_CTL_FABRIC_EN) && 1416 !intel_pt_validate_cap(vmx->pt_desc.caps, 1417 PT_CAP_single_range_output)) 1418 return 1; 1419 1420 /* 1421 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1422 * utilize encodings marked reserved will casue a #GP fault. 1423 */ 1424 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1425 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1426 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1427 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1428 return 1; 1429 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1430 PT_CAP_cycle_thresholds); 1431 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1432 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1433 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1434 return 1; 1435 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1436 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1437 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1438 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1439 return 1; 1440 1441 /* 1442 * If ADDRx_CFG is reserved or the encodings is >2 will 1443 * cause a #GP fault. 1444 */ 1445 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1446 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1447 return 1; 1448 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1449 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1450 return 1; 1451 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1452 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1453 return 1; 1454 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1455 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1456 return 1; 1457 1458 return 0; 1459 } 1460 1461 1462 static void skip_emulated_instruction(struct kvm_vcpu *vcpu) 1463 { 1464 unsigned long rip; 1465 1466 rip = kvm_rip_read(vcpu); 1467 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1468 kvm_rip_write(vcpu, rip); 1469 1470 /* skipping an emulated instruction also counts */ 1471 vmx_set_interrupt_shadow(vcpu, 0); 1472 } 1473 1474 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1475 { 1476 /* 1477 * Ensure that we clear the HLT state in the VMCS. We don't need to 1478 * explicitly skip the instruction because if the HLT state is set, 1479 * then the instruction is already executing and RIP has already been 1480 * advanced. 1481 */ 1482 if (kvm_hlt_in_guest(vcpu->kvm) && 1483 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1484 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1485 } 1486 1487 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1488 { 1489 struct vcpu_vmx *vmx = to_vmx(vcpu); 1490 unsigned nr = vcpu->arch.exception.nr; 1491 bool has_error_code = vcpu->arch.exception.has_error_code; 1492 u32 error_code = vcpu->arch.exception.error_code; 1493 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1494 1495 kvm_deliver_exception_payload(vcpu); 1496 1497 if (has_error_code) { 1498 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1499 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1500 } 1501 1502 if (vmx->rmode.vm86_active) { 1503 int inc_eip = 0; 1504 if (kvm_exception_is_soft(nr)) 1505 inc_eip = vcpu->arch.event_exit_inst_len; 1506 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) 1507 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 1508 return; 1509 } 1510 1511 WARN_ON_ONCE(vmx->emulation_required); 1512 1513 if (kvm_exception_is_soft(nr)) { 1514 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1515 vmx->vcpu.arch.event_exit_inst_len); 1516 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1517 } else 1518 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1519 1520 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1521 1522 vmx_clear_hlt(vcpu); 1523 } 1524 1525 static bool vmx_rdtscp_supported(void) 1526 { 1527 return cpu_has_vmx_rdtscp(); 1528 } 1529 1530 static bool vmx_invpcid_supported(void) 1531 { 1532 return cpu_has_vmx_invpcid(); 1533 } 1534 1535 /* 1536 * Swap MSR entry in host/guest MSR entry array. 1537 */ 1538 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1539 { 1540 struct shared_msr_entry tmp; 1541 1542 tmp = vmx->guest_msrs[to]; 1543 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1544 vmx->guest_msrs[from] = tmp; 1545 } 1546 1547 /* 1548 * Set up the vmcs to automatically save and restore system 1549 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1550 * mode, as fiddling with msrs is very expensive. 1551 */ 1552 static void setup_msrs(struct vcpu_vmx *vmx) 1553 { 1554 int save_nmsrs, index; 1555 1556 save_nmsrs = 0; 1557 #ifdef CONFIG_X86_64 1558 /* 1559 * The SYSCALL MSRs are only needed on long mode guests, and only 1560 * when EFER.SCE is set. 1561 */ 1562 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1563 index = __find_msr_index(vmx, MSR_STAR); 1564 if (index >= 0) 1565 move_msr_up(vmx, index, save_nmsrs++); 1566 index = __find_msr_index(vmx, MSR_LSTAR); 1567 if (index >= 0) 1568 move_msr_up(vmx, index, save_nmsrs++); 1569 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1570 if (index >= 0) 1571 move_msr_up(vmx, index, save_nmsrs++); 1572 } 1573 #endif 1574 index = __find_msr_index(vmx, MSR_EFER); 1575 if (index >= 0 && update_transition_efer(vmx, index)) 1576 move_msr_up(vmx, index, save_nmsrs++); 1577 index = __find_msr_index(vmx, MSR_TSC_AUX); 1578 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1579 move_msr_up(vmx, index, save_nmsrs++); 1580 1581 vmx->save_nmsrs = save_nmsrs; 1582 vmx->guest_msrs_dirty = true; 1583 1584 if (cpu_has_vmx_msr_bitmap()) 1585 vmx_update_msr_bitmap(&vmx->vcpu); 1586 } 1587 1588 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1589 { 1590 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1591 1592 if (is_guest_mode(vcpu) && 1593 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) 1594 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1595 1596 return vcpu->arch.tsc_offset; 1597 } 1598 1599 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1600 { 1601 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1602 u64 g_tsc_offset = 0; 1603 1604 /* 1605 * We're here if L1 chose not to trap WRMSR to TSC. According 1606 * to the spec, this should set L1's TSC; The offset that L1 1607 * set for L2 remains unchanged, and still needs to be added 1608 * to the newly set TSC to get L2's TSC. 1609 */ 1610 if (is_guest_mode(vcpu) && 1611 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) 1612 g_tsc_offset = vmcs12->tsc_offset; 1613 1614 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1615 vcpu->arch.tsc_offset - g_tsc_offset, 1616 offset); 1617 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1618 return offset + g_tsc_offset; 1619 } 1620 1621 /* 1622 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1623 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1624 * all guests if the "nested" module option is off, and can also be disabled 1625 * for a single guest by disabling its VMX cpuid bit. 1626 */ 1627 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1628 { 1629 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1630 } 1631 1632 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1633 uint64_t val) 1634 { 1635 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1636 1637 return !(val & ~valid_bits); 1638 } 1639 1640 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1641 { 1642 switch (msr->index) { 1643 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1644 if (!nested) 1645 return 1; 1646 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1647 default: 1648 return 1; 1649 } 1650 1651 return 0; 1652 } 1653 1654 /* 1655 * Reads an msr value (of 'msr_index') into 'pdata'. 1656 * Returns 0 on success, non-0 otherwise. 1657 * Assumes vcpu_load() was already called. 1658 */ 1659 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1660 { 1661 struct vcpu_vmx *vmx = to_vmx(vcpu); 1662 struct shared_msr_entry *msr; 1663 u32 index; 1664 1665 switch (msr_info->index) { 1666 #ifdef CONFIG_X86_64 1667 case MSR_FS_BASE: 1668 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1669 break; 1670 case MSR_GS_BASE: 1671 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1672 break; 1673 case MSR_KERNEL_GS_BASE: 1674 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1675 break; 1676 #endif 1677 case MSR_EFER: 1678 return kvm_get_msr_common(vcpu, msr_info); 1679 case MSR_IA32_SPEC_CTRL: 1680 if (!msr_info->host_initiated && 1681 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1682 return 1; 1683 1684 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1685 break; 1686 case MSR_IA32_ARCH_CAPABILITIES: 1687 if (!msr_info->host_initiated && 1688 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 1689 return 1; 1690 msr_info->data = to_vmx(vcpu)->arch_capabilities; 1691 break; 1692 case MSR_IA32_SYSENTER_CS: 1693 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1694 break; 1695 case MSR_IA32_SYSENTER_EIP: 1696 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1697 break; 1698 case MSR_IA32_SYSENTER_ESP: 1699 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1700 break; 1701 case MSR_IA32_BNDCFGS: 1702 if (!kvm_mpx_supported() || 1703 (!msr_info->host_initiated && 1704 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1705 return 1; 1706 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1707 break; 1708 case MSR_IA32_MCG_EXT_CTL: 1709 if (!msr_info->host_initiated && 1710 !(vmx->msr_ia32_feature_control & 1711 FEATURE_CONTROL_LMCE)) 1712 return 1; 1713 msr_info->data = vcpu->arch.mcg_ext_ctl; 1714 break; 1715 case MSR_IA32_FEATURE_CONTROL: 1716 msr_info->data = vmx->msr_ia32_feature_control; 1717 break; 1718 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1719 if (!nested_vmx_allowed(vcpu)) 1720 return 1; 1721 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1722 &msr_info->data); 1723 case MSR_IA32_XSS: 1724 if (!vmx_xsaves_supported()) 1725 return 1; 1726 msr_info->data = vcpu->arch.ia32_xss; 1727 break; 1728 case MSR_IA32_RTIT_CTL: 1729 if (pt_mode != PT_MODE_HOST_GUEST) 1730 return 1; 1731 msr_info->data = vmx->pt_desc.guest.ctl; 1732 break; 1733 case MSR_IA32_RTIT_STATUS: 1734 if (pt_mode != PT_MODE_HOST_GUEST) 1735 return 1; 1736 msr_info->data = vmx->pt_desc.guest.status; 1737 break; 1738 case MSR_IA32_RTIT_CR3_MATCH: 1739 if ((pt_mode != PT_MODE_HOST_GUEST) || 1740 !intel_pt_validate_cap(vmx->pt_desc.caps, 1741 PT_CAP_cr3_filtering)) 1742 return 1; 1743 msr_info->data = vmx->pt_desc.guest.cr3_match; 1744 break; 1745 case MSR_IA32_RTIT_OUTPUT_BASE: 1746 if ((pt_mode != PT_MODE_HOST_GUEST) || 1747 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1748 PT_CAP_topa_output) && 1749 !intel_pt_validate_cap(vmx->pt_desc.caps, 1750 PT_CAP_single_range_output))) 1751 return 1; 1752 msr_info->data = vmx->pt_desc.guest.output_base; 1753 break; 1754 case MSR_IA32_RTIT_OUTPUT_MASK: 1755 if ((pt_mode != PT_MODE_HOST_GUEST) || 1756 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1757 PT_CAP_topa_output) && 1758 !intel_pt_validate_cap(vmx->pt_desc.caps, 1759 PT_CAP_single_range_output))) 1760 return 1; 1761 msr_info->data = vmx->pt_desc.guest.output_mask; 1762 break; 1763 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1764 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1765 if ((pt_mode != PT_MODE_HOST_GUEST) || 1766 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1767 PT_CAP_num_address_ranges))) 1768 return 1; 1769 if (index % 2) 1770 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1771 else 1772 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1773 break; 1774 case MSR_TSC_AUX: 1775 if (!msr_info->host_initiated && 1776 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1777 return 1; 1778 /* Else, falls through */ 1779 default: 1780 msr = find_msr_entry(vmx, msr_info->index); 1781 if (msr) { 1782 msr_info->data = msr->data; 1783 break; 1784 } 1785 return kvm_get_msr_common(vcpu, msr_info); 1786 } 1787 1788 return 0; 1789 } 1790 1791 /* 1792 * Writes msr value into into the appropriate "register". 1793 * Returns 0 on success, non-0 otherwise. 1794 * Assumes vcpu_load() was already called. 1795 */ 1796 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1797 { 1798 struct vcpu_vmx *vmx = to_vmx(vcpu); 1799 struct shared_msr_entry *msr; 1800 int ret = 0; 1801 u32 msr_index = msr_info->index; 1802 u64 data = msr_info->data; 1803 u32 index; 1804 1805 switch (msr_index) { 1806 case MSR_EFER: 1807 ret = kvm_set_msr_common(vcpu, msr_info); 1808 break; 1809 #ifdef CONFIG_X86_64 1810 case MSR_FS_BASE: 1811 vmx_segment_cache_clear(vmx); 1812 vmcs_writel(GUEST_FS_BASE, data); 1813 break; 1814 case MSR_GS_BASE: 1815 vmx_segment_cache_clear(vmx); 1816 vmcs_writel(GUEST_GS_BASE, data); 1817 break; 1818 case MSR_KERNEL_GS_BASE: 1819 vmx_write_guest_kernel_gs_base(vmx, data); 1820 break; 1821 #endif 1822 case MSR_IA32_SYSENTER_CS: 1823 vmcs_write32(GUEST_SYSENTER_CS, data); 1824 break; 1825 case MSR_IA32_SYSENTER_EIP: 1826 vmcs_writel(GUEST_SYSENTER_EIP, data); 1827 break; 1828 case MSR_IA32_SYSENTER_ESP: 1829 vmcs_writel(GUEST_SYSENTER_ESP, data); 1830 break; 1831 case MSR_IA32_BNDCFGS: 1832 if (!kvm_mpx_supported() || 1833 (!msr_info->host_initiated && 1834 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1835 return 1; 1836 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1837 (data & MSR_IA32_BNDCFGS_RSVD)) 1838 return 1; 1839 vmcs_write64(GUEST_BNDCFGS, data); 1840 break; 1841 case MSR_IA32_SPEC_CTRL: 1842 if (!msr_info->host_initiated && 1843 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1844 return 1; 1845 1846 /* The STIBP bit doesn't fault even if it's not advertised */ 1847 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) 1848 return 1; 1849 1850 vmx->spec_ctrl = data; 1851 1852 if (!data) 1853 break; 1854 1855 /* 1856 * For non-nested: 1857 * When it's written (to non-zero) for the first time, pass 1858 * it through. 1859 * 1860 * For nested: 1861 * The handling of the MSR bitmap for L2 guests is done in 1862 * nested_vmx_merge_msr_bitmap. We should not touch the 1863 * vmcs02.msr_bitmap here since it gets completely overwritten 1864 * in the merging. We update the vmcs01 here for L1 as well 1865 * since it will end up touching the MSR anyway now. 1866 */ 1867 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 1868 MSR_IA32_SPEC_CTRL, 1869 MSR_TYPE_RW); 1870 break; 1871 case MSR_IA32_PRED_CMD: 1872 if (!msr_info->host_initiated && 1873 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1874 return 1; 1875 1876 if (data & ~PRED_CMD_IBPB) 1877 return 1; 1878 1879 if (!data) 1880 break; 1881 1882 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 1883 1884 /* 1885 * For non-nested: 1886 * When it's written (to non-zero) for the first time, pass 1887 * it through. 1888 * 1889 * For nested: 1890 * The handling of the MSR bitmap for L2 guests is done in 1891 * nested_vmx_merge_msr_bitmap. We should not touch the 1892 * vmcs02.msr_bitmap here since it gets completely overwritten 1893 * in the merging. 1894 */ 1895 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 1896 MSR_TYPE_W); 1897 break; 1898 case MSR_IA32_ARCH_CAPABILITIES: 1899 if (!msr_info->host_initiated) 1900 return 1; 1901 vmx->arch_capabilities = data; 1902 break; 1903 case MSR_IA32_CR_PAT: 1904 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 1905 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) 1906 return 1; 1907 vmcs_write64(GUEST_IA32_PAT, data); 1908 vcpu->arch.pat = data; 1909 break; 1910 } 1911 ret = kvm_set_msr_common(vcpu, msr_info); 1912 break; 1913 case MSR_IA32_TSC_ADJUST: 1914 ret = kvm_set_msr_common(vcpu, msr_info); 1915 break; 1916 case MSR_IA32_MCG_EXT_CTL: 1917 if ((!msr_info->host_initiated && 1918 !(to_vmx(vcpu)->msr_ia32_feature_control & 1919 FEATURE_CONTROL_LMCE)) || 1920 (data & ~MCG_EXT_CTL_LMCE_EN)) 1921 return 1; 1922 vcpu->arch.mcg_ext_ctl = data; 1923 break; 1924 case MSR_IA32_FEATURE_CONTROL: 1925 if (!vmx_feature_control_msr_valid(vcpu, data) || 1926 (to_vmx(vcpu)->msr_ia32_feature_control & 1927 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) 1928 return 1; 1929 vmx->msr_ia32_feature_control = data; 1930 if (msr_info->host_initiated && data == 0) 1931 vmx_leave_nested(vcpu); 1932 break; 1933 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1934 if (!msr_info->host_initiated) 1935 return 1; /* they are read-only */ 1936 if (!nested_vmx_allowed(vcpu)) 1937 return 1; 1938 return vmx_set_vmx_msr(vcpu, msr_index, data); 1939 case MSR_IA32_XSS: 1940 if (!vmx_xsaves_supported()) 1941 return 1; 1942 /* 1943 * The only supported bit as of Skylake is bit 8, but 1944 * it is not supported on KVM. 1945 */ 1946 if (data != 0) 1947 return 1; 1948 vcpu->arch.ia32_xss = data; 1949 if (vcpu->arch.ia32_xss != host_xss) 1950 add_atomic_switch_msr(vmx, MSR_IA32_XSS, 1951 vcpu->arch.ia32_xss, host_xss, false); 1952 else 1953 clear_atomic_switch_msr(vmx, MSR_IA32_XSS); 1954 break; 1955 case MSR_IA32_RTIT_CTL: 1956 if ((pt_mode != PT_MODE_HOST_GUEST) || 1957 vmx_rtit_ctl_check(vcpu, data) || 1958 vmx->nested.vmxon) 1959 return 1; 1960 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 1961 vmx->pt_desc.guest.ctl = data; 1962 pt_update_intercept_for_msr(vmx); 1963 break; 1964 case MSR_IA32_RTIT_STATUS: 1965 if ((pt_mode != PT_MODE_HOST_GUEST) || 1966 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 1967 (data & MSR_IA32_RTIT_STATUS_MASK)) 1968 return 1; 1969 vmx->pt_desc.guest.status = data; 1970 break; 1971 case MSR_IA32_RTIT_CR3_MATCH: 1972 if ((pt_mode != PT_MODE_HOST_GUEST) || 1973 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 1974 !intel_pt_validate_cap(vmx->pt_desc.caps, 1975 PT_CAP_cr3_filtering)) 1976 return 1; 1977 vmx->pt_desc.guest.cr3_match = data; 1978 break; 1979 case MSR_IA32_RTIT_OUTPUT_BASE: 1980 if ((pt_mode != PT_MODE_HOST_GUEST) || 1981 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 1982 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1983 PT_CAP_topa_output) && 1984 !intel_pt_validate_cap(vmx->pt_desc.caps, 1985 PT_CAP_single_range_output)) || 1986 (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK)) 1987 return 1; 1988 vmx->pt_desc.guest.output_base = data; 1989 break; 1990 case MSR_IA32_RTIT_OUTPUT_MASK: 1991 if ((pt_mode != PT_MODE_HOST_GUEST) || 1992 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 1993 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1994 PT_CAP_topa_output) && 1995 !intel_pt_validate_cap(vmx->pt_desc.caps, 1996 PT_CAP_single_range_output))) 1997 return 1; 1998 vmx->pt_desc.guest.output_mask = data; 1999 break; 2000 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2001 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2002 if ((pt_mode != PT_MODE_HOST_GUEST) || 2003 (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) || 2004 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2005 PT_CAP_num_address_ranges))) 2006 return 1; 2007 if (index % 2) 2008 vmx->pt_desc.guest.addr_b[index / 2] = data; 2009 else 2010 vmx->pt_desc.guest.addr_a[index / 2] = data; 2011 break; 2012 case MSR_TSC_AUX: 2013 if (!msr_info->host_initiated && 2014 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2015 return 1; 2016 /* Check reserved bit, higher 32 bits should be zero */ 2017 if ((data >> 32) != 0) 2018 return 1; 2019 /* Else, falls through */ 2020 default: 2021 msr = find_msr_entry(vmx, msr_index); 2022 if (msr) { 2023 u64 old_msr_data = msr->data; 2024 msr->data = data; 2025 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 2026 preempt_disable(); 2027 ret = kvm_set_shared_msr(msr->index, msr->data, 2028 msr->mask); 2029 preempt_enable(); 2030 if (ret) 2031 msr->data = old_msr_data; 2032 } 2033 break; 2034 } 2035 ret = kvm_set_msr_common(vcpu, msr_info); 2036 } 2037 2038 return ret; 2039 } 2040 2041 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2042 { 2043 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); 2044 switch (reg) { 2045 case VCPU_REGS_RSP: 2046 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2047 break; 2048 case VCPU_REGS_RIP: 2049 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2050 break; 2051 case VCPU_EXREG_PDPTR: 2052 if (enable_ept) 2053 ept_save_pdptrs(vcpu); 2054 break; 2055 default: 2056 break; 2057 } 2058 } 2059 2060 static __init int cpu_has_kvm_support(void) 2061 { 2062 return cpu_has_vmx(); 2063 } 2064 2065 static __init int vmx_disabled_by_bios(void) 2066 { 2067 u64 msr; 2068 2069 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); 2070 if (msr & FEATURE_CONTROL_LOCKED) { 2071 /* launched w/ TXT and VMX disabled */ 2072 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) 2073 && tboot_enabled()) 2074 return 1; 2075 /* launched w/o TXT and VMX only enabled w/ TXT */ 2076 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) 2077 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) 2078 && !tboot_enabled()) { 2079 printk(KERN_WARNING "kvm: disable TXT in the BIOS or " 2080 "activate TXT before enabling KVM\n"); 2081 return 1; 2082 } 2083 /* launched w/o TXT and VMX disabled */ 2084 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) 2085 && !tboot_enabled()) 2086 return 1; 2087 } 2088 2089 return 0; 2090 } 2091 2092 static void kvm_cpu_vmxon(u64 addr) 2093 { 2094 cr4_set_bits(X86_CR4_VMXE); 2095 intel_pt_handle_vmx(1); 2096 2097 asm volatile ("vmxon %0" : : "m"(addr)); 2098 } 2099 2100 static int hardware_enable(void) 2101 { 2102 int cpu = raw_smp_processor_id(); 2103 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2104 u64 old, test_bits; 2105 2106 if (cr4_read_shadow() & X86_CR4_VMXE) 2107 return -EBUSY; 2108 2109 /* 2110 * This can happen if we hot-added a CPU but failed to allocate 2111 * VP assist page for it. 2112 */ 2113 if (static_branch_unlikely(&enable_evmcs) && 2114 !hv_get_vp_assist_page(cpu)) 2115 return -EFAULT; 2116 2117 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2118 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2119 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2120 2121 /* 2122 * Now we can enable the vmclear operation in kdump 2123 * since the loaded_vmcss_on_cpu list on this cpu 2124 * has been initialized. 2125 * 2126 * Though the cpu is not in VMX operation now, there 2127 * is no problem to enable the vmclear operation 2128 * for the loaded_vmcss_on_cpu list is empty! 2129 */ 2130 crash_enable_local_vmclear(cpu); 2131 2132 rdmsrl(MSR_IA32_FEATURE_CONTROL, old); 2133 2134 test_bits = FEATURE_CONTROL_LOCKED; 2135 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 2136 if (tboot_enabled()) 2137 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; 2138 2139 if ((old & test_bits) != test_bits) { 2140 /* enable and lock */ 2141 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); 2142 } 2143 kvm_cpu_vmxon(phys_addr); 2144 if (enable_ept) 2145 ept_sync_global(); 2146 2147 return 0; 2148 } 2149 2150 static void vmclear_local_loaded_vmcss(void) 2151 { 2152 int cpu = raw_smp_processor_id(); 2153 struct loaded_vmcs *v, *n; 2154 2155 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2156 loaded_vmcss_on_cpu_link) 2157 __loaded_vmcs_clear(v); 2158 } 2159 2160 2161 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2162 * tricks. 2163 */ 2164 static void kvm_cpu_vmxoff(void) 2165 { 2166 asm volatile (__ex("vmxoff")); 2167 2168 intel_pt_handle_vmx(0); 2169 cr4_clear_bits(X86_CR4_VMXE); 2170 } 2171 2172 static void hardware_disable(void) 2173 { 2174 vmclear_local_loaded_vmcss(); 2175 kvm_cpu_vmxoff(); 2176 } 2177 2178 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2179 u32 msr, u32 *result) 2180 { 2181 u32 vmx_msr_low, vmx_msr_high; 2182 u32 ctl = ctl_min | ctl_opt; 2183 2184 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2185 2186 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2187 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2188 2189 /* Ensure minimum (required) set of control bits are supported. */ 2190 if (ctl_min & ~ctl) 2191 return -EIO; 2192 2193 *result = ctl; 2194 return 0; 2195 } 2196 2197 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2198 struct vmx_capability *vmx_cap) 2199 { 2200 u32 vmx_msr_low, vmx_msr_high; 2201 u32 min, opt, min2, opt2; 2202 u32 _pin_based_exec_control = 0; 2203 u32 _cpu_based_exec_control = 0; 2204 u32 _cpu_based_2nd_exec_control = 0; 2205 u32 _vmexit_control = 0; 2206 u32 _vmentry_control = 0; 2207 2208 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2209 min = CPU_BASED_HLT_EXITING | 2210 #ifdef CONFIG_X86_64 2211 CPU_BASED_CR8_LOAD_EXITING | 2212 CPU_BASED_CR8_STORE_EXITING | 2213 #endif 2214 CPU_BASED_CR3_LOAD_EXITING | 2215 CPU_BASED_CR3_STORE_EXITING | 2216 CPU_BASED_UNCOND_IO_EXITING | 2217 CPU_BASED_MOV_DR_EXITING | 2218 CPU_BASED_USE_TSC_OFFSETING | 2219 CPU_BASED_MWAIT_EXITING | 2220 CPU_BASED_MONITOR_EXITING | 2221 CPU_BASED_INVLPG_EXITING | 2222 CPU_BASED_RDPMC_EXITING; 2223 2224 opt = CPU_BASED_TPR_SHADOW | 2225 CPU_BASED_USE_MSR_BITMAPS | 2226 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2227 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2228 &_cpu_based_exec_control) < 0) 2229 return -EIO; 2230 #ifdef CONFIG_X86_64 2231 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2232 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2233 ~CPU_BASED_CR8_STORE_EXITING; 2234 #endif 2235 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2236 min2 = 0; 2237 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2238 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2239 SECONDARY_EXEC_WBINVD_EXITING | 2240 SECONDARY_EXEC_ENABLE_VPID | 2241 SECONDARY_EXEC_ENABLE_EPT | 2242 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2243 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2244 SECONDARY_EXEC_DESC | 2245 SECONDARY_EXEC_RDTSCP | 2246 SECONDARY_EXEC_ENABLE_INVPCID | 2247 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2248 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2249 SECONDARY_EXEC_SHADOW_VMCS | 2250 SECONDARY_EXEC_XSAVES | 2251 SECONDARY_EXEC_RDSEED_EXITING | 2252 SECONDARY_EXEC_RDRAND_EXITING | 2253 SECONDARY_EXEC_ENABLE_PML | 2254 SECONDARY_EXEC_TSC_SCALING | 2255 SECONDARY_EXEC_PT_USE_GPA | 2256 SECONDARY_EXEC_PT_CONCEAL_VMX | 2257 SECONDARY_EXEC_ENABLE_VMFUNC | 2258 SECONDARY_EXEC_ENCLS_EXITING; 2259 if (adjust_vmx_controls(min2, opt2, 2260 MSR_IA32_VMX_PROCBASED_CTLS2, 2261 &_cpu_based_2nd_exec_control) < 0) 2262 return -EIO; 2263 } 2264 #ifndef CONFIG_X86_64 2265 if (!(_cpu_based_2nd_exec_control & 2266 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2267 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2268 #endif 2269 2270 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2271 _cpu_based_2nd_exec_control &= ~( 2272 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2273 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2274 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2275 2276 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2277 &vmx_cap->ept, &vmx_cap->vpid); 2278 2279 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2280 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2281 enabled */ 2282 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2283 CPU_BASED_CR3_STORE_EXITING | 2284 CPU_BASED_INVLPG_EXITING); 2285 } else if (vmx_cap->ept) { 2286 vmx_cap->ept = 0; 2287 pr_warn_once("EPT CAP should not exist if not support " 2288 "1-setting enable EPT VM-execution control\n"); 2289 } 2290 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2291 vmx_cap->vpid) { 2292 vmx_cap->vpid = 0; 2293 pr_warn_once("VPID CAP should not exist if not support " 2294 "1-setting enable VPID VM-execution control\n"); 2295 } 2296 2297 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2298 #ifdef CONFIG_X86_64 2299 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2300 #endif 2301 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2302 VM_EXIT_SAVE_IA32_PAT | 2303 VM_EXIT_LOAD_IA32_PAT | 2304 VM_EXIT_LOAD_IA32_EFER | 2305 VM_EXIT_CLEAR_BNDCFGS | 2306 VM_EXIT_PT_CONCEAL_PIP | 2307 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2308 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2309 &_vmexit_control) < 0) 2310 return -EIO; 2311 2312 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2313 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2314 PIN_BASED_VMX_PREEMPTION_TIMER; 2315 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2316 &_pin_based_exec_control) < 0) 2317 return -EIO; 2318 2319 if (cpu_has_broken_vmx_preemption_timer()) 2320 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2321 if (!(_cpu_based_2nd_exec_control & 2322 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2323 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2324 2325 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2326 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2327 VM_ENTRY_LOAD_IA32_PAT | 2328 VM_ENTRY_LOAD_IA32_EFER | 2329 VM_ENTRY_LOAD_BNDCFGS | 2330 VM_ENTRY_PT_CONCEAL_PIP | 2331 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2332 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2333 &_vmentry_control) < 0) 2334 return -EIO; 2335 2336 /* 2337 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2338 * can't be used due to an errata where VM Exit may incorrectly clear 2339 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2340 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2341 */ 2342 if (boot_cpu_data.x86 == 0x6) { 2343 switch (boot_cpu_data.x86_model) { 2344 case 26: /* AAK155 */ 2345 case 30: /* AAP115 */ 2346 case 37: /* AAT100 */ 2347 case 44: /* BC86,AAY89,BD102 */ 2348 case 46: /* BA97 */ 2349 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2350 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2351 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2352 "does not work properly. Using workaround\n"); 2353 break; 2354 default: 2355 break; 2356 } 2357 } 2358 2359 2360 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2361 2362 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2363 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2364 return -EIO; 2365 2366 #ifdef CONFIG_X86_64 2367 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2368 if (vmx_msr_high & (1u<<16)) 2369 return -EIO; 2370 #endif 2371 2372 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2373 if (((vmx_msr_high >> 18) & 15) != 6) 2374 return -EIO; 2375 2376 vmcs_conf->size = vmx_msr_high & 0x1fff; 2377 vmcs_conf->order = get_order(vmcs_conf->size); 2378 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2379 2380 vmcs_conf->revision_id = vmx_msr_low; 2381 2382 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2383 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2384 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2385 vmcs_conf->vmexit_ctrl = _vmexit_control; 2386 vmcs_conf->vmentry_ctrl = _vmentry_control; 2387 2388 if (static_branch_unlikely(&enable_evmcs)) 2389 evmcs_sanitize_exec_ctrls(vmcs_conf); 2390 2391 return 0; 2392 } 2393 2394 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2395 { 2396 int node = cpu_to_node(cpu); 2397 struct page *pages; 2398 struct vmcs *vmcs; 2399 2400 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2401 if (!pages) 2402 return NULL; 2403 vmcs = page_address(pages); 2404 memset(vmcs, 0, vmcs_config.size); 2405 2406 /* KVM supports Enlightened VMCS v1 only */ 2407 if (static_branch_unlikely(&enable_evmcs)) 2408 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2409 else 2410 vmcs->hdr.revision_id = vmcs_config.revision_id; 2411 2412 if (shadow) 2413 vmcs->hdr.shadow_vmcs = 1; 2414 return vmcs; 2415 } 2416 2417 void free_vmcs(struct vmcs *vmcs) 2418 { 2419 free_pages((unsigned long)vmcs, vmcs_config.order); 2420 } 2421 2422 /* 2423 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2424 */ 2425 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2426 { 2427 if (!loaded_vmcs->vmcs) 2428 return; 2429 loaded_vmcs_clear(loaded_vmcs); 2430 free_vmcs(loaded_vmcs->vmcs); 2431 loaded_vmcs->vmcs = NULL; 2432 if (loaded_vmcs->msr_bitmap) 2433 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2434 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2435 } 2436 2437 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2438 { 2439 loaded_vmcs->vmcs = alloc_vmcs(false); 2440 if (!loaded_vmcs->vmcs) 2441 return -ENOMEM; 2442 2443 loaded_vmcs->shadow_vmcs = NULL; 2444 loaded_vmcs_init(loaded_vmcs); 2445 2446 if (cpu_has_vmx_msr_bitmap()) { 2447 loaded_vmcs->msr_bitmap = (unsigned long *) 2448 __get_free_page(GFP_KERNEL_ACCOUNT); 2449 if (!loaded_vmcs->msr_bitmap) 2450 goto out_vmcs; 2451 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2452 2453 if (IS_ENABLED(CONFIG_HYPERV) && 2454 static_branch_unlikely(&enable_evmcs) && 2455 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2456 struct hv_enlightened_vmcs *evmcs = 2457 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2458 2459 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2460 } 2461 } 2462 2463 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2464 2465 return 0; 2466 2467 out_vmcs: 2468 free_loaded_vmcs(loaded_vmcs); 2469 return -ENOMEM; 2470 } 2471 2472 static void free_kvm_area(void) 2473 { 2474 int cpu; 2475 2476 for_each_possible_cpu(cpu) { 2477 free_vmcs(per_cpu(vmxarea, cpu)); 2478 per_cpu(vmxarea, cpu) = NULL; 2479 } 2480 } 2481 2482 static __init int alloc_kvm_area(void) 2483 { 2484 int cpu; 2485 2486 for_each_possible_cpu(cpu) { 2487 struct vmcs *vmcs; 2488 2489 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2490 if (!vmcs) { 2491 free_kvm_area(); 2492 return -ENOMEM; 2493 } 2494 2495 /* 2496 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2497 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2498 * revision_id reported by MSR_IA32_VMX_BASIC. 2499 * 2500 * However, even though not explicitly documented by 2501 * TLFS, VMXArea passed as VMXON argument should 2502 * still be marked with revision_id reported by 2503 * physical CPU. 2504 */ 2505 if (static_branch_unlikely(&enable_evmcs)) 2506 vmcs->hdr.revision_id = vmcs_config.revision_id; 2507 2508 per_cpu(vmxarea, cpu) = vmcs; 2509 } 2510 return 0; 2511 } 2512 2513 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2514 struct kvm_segment *save) 2515 { 2516 if (!emulate_invalid_guest_state) { 2517 /* 2518 * CS and SS RPL should be equal during guest entry according 2519 * to VMX spec, but in reality it is not always so. Since vcpu 2520 * is in the middle of the transition from real mode to 2521 * protected mode it is safe to assume that RPL 0 is a good 2522 * default value. 2523 */ 2524 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2525 save->selector &= ~SEGMENT_RPL_MASK; 2526 save->dpl = save->selector & SEGMENT_RPL_MASK; 2527 save->s = 1; 2528 } 2529 vmx_set_segment(vcpu, save, seg); 2530 } 2531 2532 static void enter_pmode(struct kvm_vcpu *vcpu) 2533 { 2534 unsigned long flags; 2535 struct vcpu_vmx *vmx = to_vmx(vcpu); 2536 2537 /* 2538 * Update real mode segment cache. It may be not up-to-date if sement 2539 * register was written while vcpu was in a guest mode. 2540 */ 2541 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2542 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2543 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2544 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2545 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2546 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2547 2548 vmx->rmode.vm86_active = 0; 2549 2550 vmx_segment_cache_clear(vmx); 2551 2552 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2553 2554 flags = vmcs_readl(GUEST_RFLAGS); 2555 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2556 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2557 vmcs_writel(GUEST_RFLAGS, flags); 2558 2559 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2560 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2561 2562 update_exception_bitmap(vcpu); 2563 2564 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2565 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2566 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2567 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2568 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2569 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2570 } 2571 2572 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2573 { 2574 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2575 struct kvm_segment var = *save; 2576 2577 var.dpl = 0x3; 2578 if (seg == VCPU_SREG_CS) 2579 var.type = 0x3; 2580 2581 if (!emulate_invalid_guest_state) { 2582 var.selector = var.base >> 4; 2583 var.base = var.base & 0xffff0; 2584 var.limit = 0xffff; 2585 var.g = 0; 2586 var.db = 0; 2587 var.present = 1; 2588 var.s = 1; 2589 var.l = 0; 2590 var.unusable = 0; 2591 var.type = 0x3; 2592 var.avl = 0; 2593 if (save->base & 0xf) 2594 printk_once(KERN_WARNING "kvm: segment base is not " 2595 "paragraph aligned when entering " 2596 "protected mode (seg=%d)", seg); 2597 } 2598 2599 vmcs_write16(sf->selector, var.selector); 2600 vmcs_writel(sf->base, var.base); 2601 vmcs_write32(sf->limit, var.limit); 2602 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2603 } 2604 2605 static void enter_rmode(struct kvm_vcpu *vcpu) 2606 { 2607 unsigned long flags; 2608 struct vcpu_vmx *vmx = to_vmx(vcpu); 2609 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2610 2611 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2612 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2613 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2614 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2615 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2616 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2617 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2618 2619 vmx->rmode.vm86_active = 1; 2620 2621 /* 2622 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2623 * vcpu. Warn the user that an update is overdue. 2624 */ 2625 if (!kvm_vmx->tss_addr) 2626 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2627 "called before entering vcpu\n"); 2628 2629 vmx_segment_cache_clear(vmx); 2630 2631 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2632 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2633 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2634 2635 flags = vmcs_readl(GUEST_RFLAGS); 2636 vmx->rmode.save_rflags = flags; 2637 2638 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2639 2640 vmcs_writel(GUEST_RFLAGS, flags); 2641 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2642 update_exception_bitmap(vcpu); 2643 2644 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2645 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2646 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2647 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2648 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2649 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2650 2651 kvm_mmu_reset_context(vcpu); 2652 } 2653 2654 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2655 { 2656 struct vcpu_vmx *vmx = to_vmx(vcpu); 2657 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2658 2659 if (!msr) 2660 return; 2661 2662 vcpu->arch.efer = efer; 2663 if (efer & EFER_LMA) { 2664 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2665 msr->data = efer; 2666 } else { 2667 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2668 2669 msr->data = efer & ~EFER_LME; 2670 } 2671 setup_msrs(vmx); 2672 } 2673 2674 #ifdef CONFIG_X86_64 2675 2676 static void enter_lmode(struct kvm_vcpu *vcpu) 2677 { 2678 u32 guest_tr_ar; 2679 2680 vmx_segment_cache_clear(to_vmx(vcpu)); 2681 2682 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2683 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2684 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2685 __func__); 2686 vmcs_write32(GUEST_TR_AR_BYTES, 2687 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2688 | VMX_AR_TYPE_BUSY_64_TSS); 2689 } 2690 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2691 } 2692 2693 static void exit_lmode(struct kvm_vcpu *vcpu) 2694 { 2695 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2696 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2697 } 2698 2699 #endif 2700 2701 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2702 { 2703 int vpid = to_vmx(vcpu)->vpid; 2704 2705 if (!vpid_sync_vcpu_addr(vpid, addr)) 2706 vpid_sync_context(vpid); 2707 2708 /* 2709 * If VPIDs are not supported or enabled, then the above is a no-op. 2710 * But we don't really need a TLB flush in that case anyway, because 2711 * each VM entry/exit includes an implicit flush when VPID is 0. 2712 */ 2713 } 2714 2715 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2716 { 2717 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2718 2719 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2720 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2721 } 2722 2723 static void vmx_decache_cr3(struct kvm_vcpu *vcpu) 2724 { 2725 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2726 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2727 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 2728 } 2729 2730 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2731 { 2732 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2733 2734 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2735 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2736 } 2737 2738 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2739 { 2740 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2741 2742 if (!test_bit(VCPU_EXREG_PDPTR, 2743 (unsigned long *)&vcpu->arch.regs_dirty)) 2744 return; 2745 2746 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { 2747 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2748 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2749 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2750 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2751 } 2752 } 2753 2754 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2755 { 2756 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2757 2758 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { 2759 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2760 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2761 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2762 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2763 } 2764 2765 __set_bit(VCPU_EXREG_PDPTR, 2766 (unsigned long *)&vcpu->arch.regs_avail); 2767 __set_bit(VCPU_EXREG_PDPTR, 2768 (unsigned long *)&vcpu->arch.regs_dirty); 2769 } 2770 2771 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2772 unsigned long cr0, 2773 struct kvm_vcpu *vcpu) 2774 { 2775 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 2776 vmx_decache_cr3(vcpu); 2777 if (!(cr0 & X86_CR0_PG)) { 2778 /* From paging/starting to nonpaging */ 2779 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, 2780 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | 2781 (CPU_BASED_CR3_LOAD_EXITING | 2782 CPU_BASED_CR3_STORE_EXITING)); 2783 vcpu->arch.cr0 = cr0; 2784 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2785 } else if (!is_paging(vcpu)) { 2786 /* From nonpaging to paging */ 2787 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, 2788 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & 2789 ~(CPU_BASED_CR3_LOAD_EXITING | 2790 CPU_BASED_CR3_STORE_EXITING)); 2791 vcpu->arch.cr0 = cr0; 2792 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2793 } 2794 2795 if (!(cr0 & X86_CR0_WP)) 2796 *hw_cr0 &= ~X86_CR0_WP; 2797 } 2798 2799 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2800 { 2801 struct vcpu_vmx *vmx = to_vmx(vcpu); 2802 unsigned long hw_cr0; 2803 2804 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2805 if (enable_unrestricted_guest) 2806 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2807 else { 2808 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2809 2810 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2811 enter_pmode(vcpu); 2812 2813 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2814 enter_rmode(vcpu); 2815 } 2816 2817 #ifdef CONFIG_X86_64 2818 if (vcpu->arch.efer & EFER_LME) { 2819 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2820 enter_lmode(vcpu); 2821 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2822 exit_lmode(vcpu); 2823 } 2824 #endif 2825 2826 if (enable_ept && !enable_unrestricted_guest) 2827 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2828 2829 vmcs_writel(CR0_READ_SHADOW, cr0); 2830 vmcs_writel(GUEST_CR0, hw_cr0); 2831 vcpu->arch.cr0 = cr0; 2832 2833 /* depends on vcpu->arch.cr0 to be set to a new value */ 2834 vmx->emulation_required = emulation_required(vcpu); 2835 } 2836 2837 static int get_ept_level(struct kvm_vcpu *vcpu) 2838 { 2839 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2840 return 5; 2841 return 4; 2842 } 2843 2844 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2845 { 2846 u64 eptp = VMX_EPTP_MT_WB; 2847 2848 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2849 2850 if (enable_ept_ad_bits && 2851 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2852 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2853 eptp |= (root_hpa & PAGE_MASK); 2854 2855 return eptp; 2856 } 2857 2858 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 2859 { 2860 struct kvm *kvm = vcpu->kvm; 2861 unsigned long guest_cr3; 2862 u64 eptp; 2863 2864 guest_cr3 = cr3; 2865 if (enable_ept) { 2866 eptp = construct_eptp(vcpu, cr3); 2867 vmcs_write64(EPT_POINTER, eptp); 2868 2869 if (kvm_x86_ops->tlb_remote_flush) { 2870 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2871 to_vmx(vcpu)->ept_pointer = eptp; 2872 to_kvm_vmx(kvm)->ept_pointers_match 2873 = EPT_POINTERS_CHECK; 2874 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2875 } 2876 2877 if (enable_unrestricted_guest || is_paging(vcpu) || 2878 is_guest_mode(vcpu)) 2879 guest_cr3 = kvm_read_cr3(vcpu); 2880 else 2881 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 2882 ept_load_pdptrs(vcpu); 2883 } 2884 2885 vmcs_writel(GUEST_CR3, guest_cr3); 2886 } 2887 2888 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 2889 { 2890 /* 2891 * Pass through host's Machine Check Enable value to hw_cr4, which 2892 * is in force while we are in guest mode. Do not let guests control 2893 * this bit, even if host CR4.MCE == 0. 2894 */ 2895 unsigned long hw_cr4; 2896 2897 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 2898 if (enable_unrestricted_guest) 2899 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 2900 else if (to_vmx(vcpu)->rmode.vm86_active) 2901 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 2902 else 2903 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 2904 2905 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 2906 if (cr4 & X86_CR4_UMIP) { 2907 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, 2908 SECONDARY_EXEC_DESC); 2909 hw_cr4 &= ~X86_CR4_UMIP; 2910 } else if (!is_guest_mode(vcpu) || 2911 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) 2912 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, 2913 SECONDARY_EXEC_DESC); 2914 } 2915 2916 if (cr4 & X86_CR4_VMXE) { 2917 /* 2918 * To use VMXON (and later other VMX instructions), a guest 2919 * must first be able to turn on cr4.VMXE (see handle_vmon()). 2920 * So basically the check on whether to allow nested VMX 2921 * is here. We operate under the default treatment of SMM, 2922 * so VMX cannot be enabled under SMM. 2923 */ 2924 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 2925 return 1; 2926 } 2927 2928 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 2929 return 1; 2930 2931 vcpu->arch.cr4 = cr4; 2932 2933 if (!enable_unrestricted_guest) { 2934 if (enable_ept) { 2935 if (!is_paging(vcpu)) { 2936 hw_cr4 &= ~X86_CR4_PAE; 2937 hw_cr4 |= X86_CR4_PSE; 2938 } else if (!(cr4 & X86_CR4_PAE)) { 2939 hw_cr4 &= ~X86_CR4_PAE; 2940 } 2941 } 2942 2943 /* 2944 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 2945 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 2946 * to be manually disabled when guest switches to non-paging 2947 * mode. 2948 * 2949 * If !enable_unrestricted_guest, the CPU is always running 2950 * with CR0.PG=1 and CR4 needs to be modified. 2951 * If enable_unrestricted_guest, the CPU automatically 2952 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 2953 */ 2954 if (!is_paging(vcpu)) 2955 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 2956 } 2957 2958 vmcs_writel(CR4_READ_SHADOW, cr4); 2959 vmcs_writel(GUEST_CR4, hw_cr4); 2960 return 0; 2961 } 2962 2963 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 2964 { 2965 struct vcpu_vmx *vmx = to_vmx(vcpu); 2966 u32 ar; 2967 2968 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 2969 *var = vmx->rmode.segs[seg]; 2970 if (seg == VCPU_SREG_TR 2971 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 2972 return; 2973 var->base = vmx_read_guest_seg_base(vmx, seg); 2974 var->selector = vmx_read_guest_seg_selector(vmx, seg); 2975 return; 2976 } 2977 var->base = vmx_read_guest_seg_base(vmx, seg); 2978 var->limit = vmx_read_guest_seg_limit(vmx, seg); 2979 var->selector = vmx_read_guest_seg_selector(vmx, seg); 2980 ar = vmx_read_guest_seg_ar(vmx, seg); 2981 var->unusable = (ar >> 16) & 1; 2982 var->type = ar & 15; 2983 var->s = (ar >> 4) & 1; 2984 var->dpl = (ar >> 5) & 3; 2985 /* 2986 * Some userspaces do not preserve unusable property. Since usable 2987 * segment has to be present according to VMX spec we can use present 2988 * property to amend userspace bug by making unusable segment always 2989 * nonpresent. vmx_segment_access_rights() already marks nonpresent 2990 * segment as unusable. 2991 */ 2992 var->present = !var->unusable; 2993 var->avl = (ar >> 12) & 1; 2994 var->l = (ar >> 13) & 1; 2995 var->db = (ar >> 14) & 1; 2996 var->g = (ar >> 15) & 1; 2997 } 2998 2999 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3000 { 3001 struct kvm_segment s; 3002 3003 if (to_vmx(vcpu)->rmode.vm86_active) { 3004 vmx_get_segment(vcpu, &s, seg); 3005 return s.base; 3006 } 3007 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3008 } 3009 3010 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3011 { 3012 struct vcpu_vmx *vmx = to_vmx(vcpu); 3013 3014 if (unlikely(vmx->rmode.vm86_active)) 3015 return 0; 3016 else { 3017 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3018 return VMX_AR_DPL(ar); 3019 } 3020 } 3021 3022 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3023 { 3024 u32 ar; 3025 3026 if (var->unusable || !var->present) 3027 ar = 1 << 16; 3028 else { 3029 ar = var->type & 15; 3030 ar |= (var->s & 1) << 4; 3031 ar |= (var->dpl & 3) << 5; 3032 ar |= (var->present & 1) << 7; 3033 ar |= (var->avl & 1) << 12; 3034 ar |= (var->l & 1) << 13; 3035 ar |= (var->db & 1) << 14; 3036 ar |= (var->g & 1) << 15; 3037 } 3038 3039 return ar; 3040 } 3041 3042 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3043 { 3044 struct vcpu_vmx *vmx = to_vmx(vcpu); 3045 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3046 3047 vmx_segment_cache_clear(vmx); 3048 3049 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3050 vmx->rmode.segs[seg] = *var; 3051 if (seg == VCPU_SREG_TR) 3052 vmcs_write16(sf->selector, var->selector); 3053 else if (var->s) 3054 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3055 goto out; 3056 } 3057 3058 vmcs_writel(sf->base, var->base); 3059 vmcs_write32(sf->limit, var->limit); 3060 vmcs_write16(sf->selector, var->selector); 3061 3062 /* 3063 * Fix the "Accessed" bit in AR field of segment registers for older 3064 * qemu binaries. 3065 * IA32 arch specifies that at the time of processor reset the 3066 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3067 * is setting it to 0 in the userland code. This causes invalid guest 3068 * state vmexit when "unrestricted guest" mode is turned on. 3069 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3070 * tree. Newer qemu binaries with that qemu fix would not need this 3071 * kvm hack. 3072 */ 3073 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3074 var->type |= 0x1; /* Accessed */ 3075 3076 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3077 3078 out: 3079 vmx->emulation_required = emulation_required(vcpu); 3080 } 3081 3082 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3083 { 3084 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3085 3086 *db = (ar >> 14) & 1; 3087 *l = (ar >> 13) & 1; 3088 } 3089 3090 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3091 { 3092 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3093 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3094 } 3095 3096 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3097 { 3098 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3099 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3100 } 3101 3102 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3103 { 3104 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3105 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3106 } 3107 3108 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3109 { 3110 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3111 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3112 } 3113 3114 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3115 { 3116 struct kvm_segment var; 3117 u32 ar; 3118 3119 vmx_get_segment(vcpu, &var, seg); 3120 var.dpl = 0x3; 3121 if (seg == VCPU_SREG_CS) 3122 var.type = 0x3; 3123 ar = vmx_segment_access_rights(&var); 3124 3125 if (var.base != (var.selector << 4)) 3126 return false; 3127 if (var.limit != 0xffff) 3128 return false; 3129 if (ar != 0xf3) 3130 return false; 3131 3132 return true; 3133 } 3134 3135 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3136 { 3137 struct kvm_segment cs; 3138 unsigned int cs_rpl; 3139 3140 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3141 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3142 3143 if (cs.unusable) 3144 return false; 3145 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3146 return false; 3147 if (!cs.s) 3148 return false; 3149 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3150 if (cs.dpl > cs_rpl) 3151 return false; 3152 } else { 3153 if (cs.dpl != cs_rpl) 3154 return false; 3155 } 3156 if (!cs.present) 3157 return false; 3158 3159 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3160 return true; 3161 } 3162 3163 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3164 { 3165 struct kvm_segment ss; 3166 unsigned int ss_rpl; 3167 3168 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3169 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3170 3171 if (ss.unusable) 3172 return true; 3173 if (ss.type != 3 && ss.type != 7) 3174 return false; 3175 if (!ss.s) 3176 return false; 3177 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3178 return false; 3179 if (!ss.present) 3180 return false; 3181 3182 return true; 3183 } 3184 3185 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3186 { 3187 struct kvm_segment var; 3188 unsigned int rpl; 3189 3190 vmx_get_segment(vcpu, &var, seg); 3191 rpl = var.selector & SEGMENT_RPL_MASK; 3192 3193 if (var.unusable) 3194 return true; 3195 if (!var.s) 3196 return false; 3197 if (!var.present) 3198 return false; 3199 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3200 if (var.dpl < rpl) /* DPL < RPL */ 3201 return false; 3202 } 3203 3204 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3205 * rights flags 3206 */ 3207 return true; 3208 } 3209 3210 static bool tr_valid(struct kvm_vcpu *vcpu) 3211 { 3212 struct kvm_segment tr; 3213 3214 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3215 3216 if (tr.unusable) 3217 return false; 3218 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3219 return false; 3220 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3221 return false; 3222 if (!tr.present) 3223 return false; 3224 3225 return true; 3226 } 3227 3228 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3229 { 3230 struct kvm_segment ldtr; 3231 3232 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3233 3234 if (ldtr.unusable) 3235 return true; 3236 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3237 return false; 3238 if (ldtr.type != 2) 3239 return false; 3240 if (!ldtr.present) 3241 return false; 3242 3243 return true; 3244 } 3245 3246 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3247 { 3248 struct kvm_segment cs, ss; 3249 3250 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3251 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3252 3253 return ((cs.selector & SEGMENT_RPL_MASK) == 3254 (ss.selector & SEGMENT_RPL_MASK)); 3255 } 3256 3257 /* 3258 * Check if guest state is valid. Returns true if valid, false if 3259 * not. 3260 * We assume that registers are always usable 3261 */ 3262 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3263 { 3264 if (enable_unrestricted_guest) 3265 return true; 3266 3267 /* real mode guest state checks */ 3268 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3269 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3270 return false; 3271 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3272 return false; 3273 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3274 return false; 3275 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3276 return false; 3277 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3278 return false; 3279 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3280 return false; 3281 } else { 3282 /* protected mode guest state checks */ 3283 if (!cs_ss_rpl_check(vcpu)) 3284 return false; 3285 if (!code_segment_valid(vcpu)) 3286 return false; 3287 if (!stack_segment_valid(vcpu)) 3288 return false; 3289 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3290 return false; 3291 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3292 return false; 3293 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3294 return false; 3295 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3296 return false; 3297 if (!tr_valid(vcpu)) 3298 return false; 3299 if (!ldtr_valid(vcpu)) 3300 return false; 3301 } 3302 /* TODO: 3303 * - Add checks on RIP 3304 * - Add checks on RFLAGS 3305 */ 3306 3307 return true; 3308 } 3309 3310 static int init_rmode_tss(struct kvm *kvm) 3311 { 3312 gfn_t fn; 3313 u16 data = 0; 3314 int idx, r; 3315 3316 idx = srcu_read_lock(&kvm->srcu); 3317 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3318 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3319 if (r < 0) 3320 goto out; 3321 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3322 r = kvm_write_guest_page(kvm, fn++, &data, 3323 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3324 if (r < 0) 3325 goto out; 3326 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3327 if (r < 0) 3328 goto out; 3329 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3330 if (r < 0) 3331 goto out; 3332 data = ~0; 3333 r = kvm_write_guest_page(kvm, fn, &data, 3334 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3335 sizeof(u8)); 3336 out: 3337 srcu_read_unlock(&kvm->srcu, idx); 3338 return r; 3339 } 3340 3341 static int init_rmode_identity_map(struct kvm *kvm) 3342 { 3343 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3344 int i, idx, r = 0; 3345 kvm_pfn_t identity_map_pfn; 3346 u32 tmp; 3347 3348 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3349 mutex_lock(&kvm->slots_lock); 3350 3351 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3352 goto out2; 3353 3354 if (!kvm_vmx->ept_identity_map_addr) 3355 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3356 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3357 3358 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3359 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3360 if (r < 0) 3361 goto out2; 3362 3363 idx = srcu_read_lock(&kvm->srcu); 3364 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3365 if (r < 0) 3366 goto out; 3367 /* Set up identity-mapping pagetable for EPT in real mode */ 3368 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3369 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3370 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3371 r = kvm_write_guest_page(kvm, identity_map_pfn, 3372 &tmp, i * sizeof(tmp), sizeof(tmp)); 3373 if (r < 0) 3374 goto out; 3375 } 3376 kvm_vmx->ept_identity_pagetable_done = true; 3377 3378 out: 3379 srcu_read_unlock(&kvm->srcu, idx); 3380 3381 out2: 3382 mutex_unlock(&kvm->slots_lock); 3383 return r; 3384 } 3385 3386 static void seg_setup(int seg) 3387 { 3388 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3389 unsigned int ar; 3390 3391 vmcs_write16(sf->selector, 0); 3392 vmcs_writel(sf->base, 0); 3393 vmcs_write32(sf->limit, 0xffff); 3394 ar = 0x93; 3395 if (seg == VCPU_SREG_CS) 3396 ar |= 0x08; /* code segment */ 3397 3398 vmcs_write32(sf->ar_bytes, ar); 3399 } 3400 3401 static int alloc_apic_access_page(struct kvm *kvm) 3402 { 3403 struct page *page; 3404 int r = 0; 3405 3406 mutex_lock(&kvm->slots_lock); 3407 if (kvm->arch.apic_access_page_done) 3408 goto out; 3409 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3410 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3411 if (r) 3412 goto out; 3413 3414 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3415 if (is_error_page(page)) { 3416 r = -EFAULT; 3417 goto out; 3418 } 3419 3420 /* 3421 * Do not pin the page in memory, so that memory hot-unplug 3422 * is able to migrate it. 3423 */ 3424 put_page(page); 3425 kvm->arch.apic_access_page_done = true; 3426 out: 3427 mutex_unlock(&kvm->slots_lock); 3428 return r; 3429 } 3430 3431 int allocate_vpid(void) 3432 { 3433 int vpid; 3434 3435 if (!enable_vpid) 3436 return 0; 3437 spin_lock(&vmx_vpid_lock); 3438 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3439 if (vpid < VMX_NR_VPIDS) 3440 __set_bit(vpid, vmx_vpid_bitmap); 3441 else 3442 vpid = 0; 3443 spin_unlock(&vmx_vpid_lock); 3444 return vpid; 3445 } 3446 3447 void free_vpid(int vpid) 3448 { 3449 if (!enable_vpid || vpid == 0) 3450 return; 3451 spin_lock(&vmx_vpid_lock); 3452 __clear_bit(vpid, vmx_vpid_bitmap); 3453 spin_unlock(&vmx_vpid_lock); 3454 } 3455 3456 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3457 u32 msr, int type) 3458 { 3459 int f = sizeof(unsigned long); 3460 3461 if (!cpu_has_vmx_msr_bitmap()) 3462 return; 3463 3464 if (static_branch_unlikely(&enable_evmcs)) 3465 evmcs_touch_msr_bitmap(); 3466 3467 /* 3468 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3469 * have the write-low and read-high bitmap offsets the wrong way round. 3470 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3471 */ 3472 if (msr <= 0x1fff) { 3473 if (type & MSR_TYPE_R) 3474 /* read-low */ 3475 __clear_bit(msr, msr_bitmap + 0x000 / f); 3476 3477 if (type & MSR_TYPE_W) 3478 /* write-low */ 3479 __clear_bit(msr, msr_bitmap + 0x800 / f); 3480 3481 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3482 msr &= 0x1fff; 3483 if (type & MSR_TYPE_R) 3484 /* read-high */ 3485 __clear_bit(msr, msr_bitmap + 0x400 / f); 3486 3487 if (type & MSR_TYPE_W) 3488 /* write-high */ 3489 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3490 3491 } 3492 } 3493 3494 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3495 u32 msr, int type) 3496 { 3497 int f = sizeof(unsigned long); 3498 3499 if (!cpu_has_vmx_msr_bitmap()) 3500 return; 3501 3502 if (static_branch_unlikely(&enable_evmcs)) 3503 evmcs_touch_msr_bitmap(); 3504 3505 /* 3506 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3507 * have the write-low and read-high bitmap offsets the wrong way round. 3508 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3509 */ 3510 if (msr <= 0x1fff) { 3511 if (type & MSR_TYPE_R) 3512 /* read-low */ 3513 __set_bit(msr, msr_bitmap + 0x000 / f); 3514 3515 if (type & MSR_TYPE_W) 3516 /* write-low */ 3517 __set_bit(msr, msr_bitmap + 0x800 / f); 3518 3519 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3520 msr &= 0x1fff; 3521 if (type & MSR_TYPE_R) 3522 /* read-high */ 3523 __set_bit(msr, msr_bitmap + 0x400 / f); 3524 3525 if (type & MSR_TYPE_W) 3526 /* write-high */ 3527 __set_bit(msr, msr_bitmap + 0xc00 / f); 3528 3529 } 3530 } 3531 3532 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3533 u32 msr, int type, bool value) 3534 { 3535 if (value) 3536 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3537 else 3538 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3539 } 3540 3541 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3542 { 3543 u8 mode = 0; 3544 3545 if (cpu_has_secondary_exec_ctrls() && 3546 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & 3547 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3548 mode |= MSR_BITMAP_MODE_X2APIC; 3549 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3550 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3551 } 3552 3553 return mode; 3554 } 3555 3556 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3557 u8 mode) 3558 { 3559 int msr; 3560 3561 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3562 unsigned word = msr / BITS_PER_LONG; 3563 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3564 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3565 } 3566 3567 if (mode & MSR_BITMAP_MODE_X2APIC) { 3568 /* 3569 * TPR reads and writes can be virtualized even if virtual interrupt 3570 * delivery is not in use. 3571 */ 3572 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3573 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3574 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3575 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3576 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3577 } 3578 } 3579 } 3580 3581 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3582 { 3583 struct vcpu_vmx *vmx = to_vmx(vcpu); 3584 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3585 u8 mode = vmx_msr_bitmap_mode(vcpu); 3586 u8 changed = mode ^ vmx->msr_bitmap_mode; 3587 3588 if (!changed) 3589 return; 3590 3591 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3592 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3593 3594 vmx->msr_bitmap_mode = mode; 3595 } 3596 3597 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3598 { 3599 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3600 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3601 u32 i; 3602 3603 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3604 MSR_TYPE_RW, flag); 3605 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3606 MSR_TYPE_RW, flag); 3607 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3608 MSR_TYPE_RW, flag); 3609 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3610 MSR_TYPE_RW, flag); 3611 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3612 vmx_set_intercept_for_msr(msr_bitmap, 3613 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3614 vmx_set_intercept_for_msr(msr_bitmap, 3615 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3616 } 3617 } 3618 3619 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) 3620 { 3621 return enable_apicv; 3622 } 3623 3624 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3625 { 3626 struct vcpu_vmx *vmx = to_vmx(vcpu); 3627 void *vapic_page; 3628 u32 vppr; 3629 int rvi; 3630 3631 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3632 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3633 WARN_ON_ONCE(!vmx->nested.virtual_apic_page)) 3634 return false; 3635 3636 rvi = vmx_get_rvi(); 3637 3638 vapic_page = kmap(vmx->nested.virtual_apic_page); 3639 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3640 kunmap(vmx->nested.virtual_apic_page); 3641 3642 return ((rvi & 0xf0) > (vppr & 0xf0)); 3643 } 3644 3645 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3646 bool nested) 3647 { 3648 #ifdef CONFIG_SMP 3649 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3650 3651 if (vcpu->mode == IN_GUEST_MODE) { 3652 /* 3653 * The vector of interrupt to be delivered to vcpu had 3654 * been set in PIR before this function. 3655 * 3656 * Following cases will be reached in this block, and 3657 * we always send a notification event in all cases as 3658 * explained below. 3659 * 3660 * Case 1: vcpu keeps in non-root mode. Sending a 3661 * notification event posts the interrupt to vcpu. 3662 * 3663 * Case 2: vcpu exits to root mode and is still 3664 * runnable. PIR will be synced to vIRR before the 3665 * next vcpu entry. Sending a notification event in 3666 * this case has no effect, as vcpu is not in root 3667 * mode. 3668 * 3669 * Case 3: vcpu exits to root mode and is blocked. 3670 * vcpu_block() has already synced PIR to vIRR and 3671 * never blocks vcpu if vIRR is not cleared. Therefore, 3672 * a blocked vcpu here does not wait for any requested 3673 * interrupts in PIR, and sending a notification event 3674 * which has no effect is safe here. 3675 */ 3676 3677 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3678 return true; 3679 } 3680 #endif 3681 return false; 3682 } 3683 3684 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3685 int vector) 3686 { 3687 struct vcpu_vmx *vmx = to_vmx(vcpu); 3688 3689 if (is_guest_mode(vcpu) && 3690 vector == vmx->nested.posted_intr_nv) { 3691 /* 3692 * If a posted intr is not recognized by hardware, 3693 * we will accomplish it in the next vmentry. 3694 */ 3695 vmx->nested.pi_pending = true; 3696 kvm_make_request(KVM_REQ_EVENT, vcpu); 3697 /* the PIR and ON have been set by L1. */ 3698 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3699 kvm_vcpu_kick(vcpu); 3700 return 0; 3701 } 3702 return -1; 3703 } 3704 /* 3705 * Send interrupt to vcpu via posted interrupt way. 3706 * 1. If target vcpu is running(non-root mode), send posted interrupt 3707 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3708 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3709 * interrupt from PIR in next vmentry. 3710 */ 3711 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3712 { 3713 struct vcpu_vmx *vmx = to_vmx(vcpu); 3714 int r; 3715 3716 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3717 if (!r) 3718 return; 3719 3720 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3721 return; 3722 3723 /* If a previous notification has sent the IPI, nothing to do. */ 3724 if (pi_test_and_set_on(&vmx->pi_desc)) 3725 return; 3726 3727 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3728 kvm_vcpu_kick(vcpu); 3729 } 3730 3731 /* 3732 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3733 * will not change in the lifetime of the guest. 3734 * Note that host-state that does change is set elsewhere. E.g., host-state 3735 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3736 */ 3737 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3738 { 3739 u32 low32, high32; 3740 unsigned long tmpl; 3741 struct desc_ptr dt; 3742 unsigned long cr0, cr3, cr4; 3743 3744 cr0 = read_cr0(); 3745 WARN_ON(cr0 & X86_CR0_TS); 3746 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3747 3748 /* 3749 * Save the most likely value for this task's CR3 in the VMCS. 3750 * We can't use __get_current_cr3_fast() because we're not atomic. 3751 */ 3752 cr3 = __read_cr3(); 3753 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3754 vmx->loaded_vmcs->host_state.cr3 = cr3; 3755 3756 /* Save the most likely value for this task's CR4 in the VMCS. */ 3757 cr4 = cr4_read_shadow(); 3758 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3759 vmx->loaded_vmcs->host_state.cr4 = cr4; 3760 3761 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3762 #ifdef CONFIG_X86_64 3763 /* 3764 * Load null selectors, so we can avoid reloading them in 3765 * vmx_prepare_switch_to_host(), in case userspace uses 3766 * the null selectors too (the expected case). 3767 */ 3768 vmcs_write16(HOST_DS_SELECTOR, 0); 3769 vmcs_write16(HOST_ES_SELECTOR, 0); 3770 #else 3771 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3772 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3773 #endif 3774 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3775 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3776 3777 store_idt(&dt); 3778 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ 3779 vmx->host_idt_base = dt.address; 3780 3781 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3782 3783 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3784 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3785 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3786 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3787 3788 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3789 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3790 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3791 } 3792 3793 if (cpu_has_load_ia32_efer()) 3794 vmcs_write64(HOST_IA32_EFER, host_efer); 3795 } 3796 3797 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3798 { 3799 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3800 if (enable_ept) 3801 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3802 if (is_guest_mode(&vmx->vcpu)) 3803 vmx->vcpu.arch.cr4_guest_owned_bits &= 3804 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3805 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3806 } 3807 3808 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3809 { 3810 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3811 3812 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3813 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3814 3815 if (!enable_vnmi) 3816 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3817 3818 /* Enable the preemption timer dynamically */ 3819 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3820 return pin_based_exec_ctrl; 3821 } 3822 3823 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3824 { 3825 struct vcpu_vmx *vmx = to_vmx(vcpu); 3826 3827 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); 3828 if (cpu_has_secondary_exec_ctrls()) { 3829 if (kvm_vcpu_apicv_active(vcpu)) 3830 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, 3831 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3832 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3833 else 3834 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, 3835 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3836 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3837 } 3838 3839 if (cpu_has_vmx_msr_bitmap()) 3840 vmx_update_msr_bitmap(vcpu); 3841 } 3842 3843 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3844 { 3845 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3846 3847 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3848 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3849 3850 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3851 exec_control &= ~CPU_BASED_TPR_SHADOW; 3852 #ifdef CONFIG_X86_64 3853 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3854 CPU_BASED_CR8_LOAD_EXITING; 3855 #endif 3856 } 3857 if (!enable_ept) 3858 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3859 CPU_BASED_CR3_LOAD_EXITING | 3860 CPU_BASED_INVLPG_EXITING; 3861 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3862 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3863 CPU_BASED_MONITOR_EXITING); 3864 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3865 exec_control &= ~CPU_BASED_HLT_EXITING; 3866 return exec_control; 3867 } 3868 3869 3870 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 3871 { 3872 struct kvm_vcpu *vcpu = &vmx->vcpu; 3873 3874 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 3875 3876 if (pt_mode == PT_MODE_SYSTEM) 3877 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 3878 if (!cpu_need_virtualize_apic_accesses(vcpu)) 3879 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 3880 if (vmx->vpid == 0) 3881 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 3882 if (!enable_ept) { 3883 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 3884 enable_unrestricted_guest = 0; 3885 } 3886 if (!enable_unrestricted_guest) 3887 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 3888 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 3889 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 3890 if (!kvm_vcpu_apicv_active(vcpu)) 3891 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 3892 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3893 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 3894 3895 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 3896 * in vmx_set_cr4. */ 3897 exec_control &= ~SECONDARY_EXEC_DESC; 3898 3899 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 3900 (handle_vmptrld). 3901 We can NOT enable shadow_vmcs here because we don't have yet 3902 a current VMCS12 3903 */ 3904 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 3905 3906 if (!enable_pml) 3907 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 3908 3909 if (vmx_xsaves_supported()) { 3910 /* Exposing XSAVES only when XSAVE is exposed */ 3911 bool xsaves_enabled = 3912 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 3913 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 3914 3915 if (!xsaves_enabled) 3916 exec_control &= ~SECONDARY_EXEC_XSAVES; 3917 3918 if (nested) { 3919 if (xsaves_enabled) 3920 vmx->nested.msrs.secondary_ctls_high |= 3921 SECONDARY_EXEC_XSAVES; 3922 else 3923 vmx->nested.msrs.secondary_ctls_high &= 3924 ~SECONDARY_EXEC_XSAVES; 3925 } 3926 } 3927 3928 if (vmx_rdtscp_supported()) { 3929 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 3930 if (!rdtscp_enabled) 3931 exec_control &= ~SECONDARY_EXEC_RDTSCP; 3932 3933 if (nested) { 3934 if (rdtscp_enabled) 3935 vmx->nested.msrs.secondary_ctls_high |= 3936 SECONDARY_EXEC_RDTSCP; 3937 else 3938 vmx->nested.msrs.secondary_ctls_high &= 3939 ~SECONDARY_EXEC_RDTSCP; 3940 } 3941 } 3942 3943 if (vmx_invpcid_supported()) { 3944 /* Exposing INVPCID only when PCID is exposed */ 3945 bool invpcid_enabled = 3946 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 3947 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 3948 3949 if (!invpcid_enabled) { 3950 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 3951 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 3952 } 3953 3954 if (nested) { 3955 if (invpcid_enabled) 3956 vmx->nested.msrs.secondary_ctls_high |= 3957 SECONDARY_EXEC_ENABLE_INVPCID; 3958 else 3959 vmx->nested.msrs.secondary_ctls_high &= 3960 ~SECONDARY_EXEC_ENABLE_INVPCID; 3961 } 3962 } 3963 3964 if (vmx_rdrand_supported()) { 3965 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 3966 if (rdrand_enabled) 3967 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 3968 3969 if (nested) { 3970 if (rdrand_enabled) 3971 vmx->nested.msrs.secondary_ctls_high |= 3972 SECONDARY_EXEC_RDRAND_EXITING; 3973 else 3974 vmx->nested.msrs.secondary_ctls_high &= 3975 ~SECONDARY_EXEC_RDRAND_EXITING; 3976 } 3977 } 3978 3979 if (vmx_rdseed_supported()) { 3980 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 3981 if (rdseed_enabled) 3982 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 3983 3984 if (nested) { 3985 if (rdseed_enabled) 3986 vmx->nested.msrs.secondary_ctls_high |= 3987 SECONDARY_EXEC_RDSEED_EXITING; 3988 else 3989 vmx->nested.msrs.secondary_ctls_high &= 3990 ~SECONDARY_EXEC_RDSEED_EXITING; 3991 } 3992 } 3993 3994 vmx->secondary_exec_control = exec_control; 3995 } 3996 3997 static void ept_set_mmio_spte_mask(void) 3998 { 3999 /* 4000 * EPT Misconfigurations can be generated if the value of bits 2:0 4001 * of an EPT paging-structure entry is 110b (write/execute). 4002 */ 4003 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4004 VMX_EPT_MISCONFIG_WX_VALUE); 4005 } 4006 4007 #define VMX_XSS_EXIT_BITMAP 0 4008 4009 /* 4010 * Sets up the vmcs for emulated real mode. 4011 */ 4012 static void vmx_vcpu_setup(struct vcpu_vmx *vmx) 4013 { 4014 int i; 4015 4016 if (nested) 4017 nested_vmx_vcpu_setup(); 4018 4019 if (cpu_has_vmx_msr_bitmap()) 4020 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4021 4022 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4023 4024 /* Control */ 4025 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); 4026 vmx->hv_deadline_tsc = -1; 4027 4028 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); 4029 4030 if (cpu_has_secondary_exec_ctrls()) { 4031 vmx_compute_secondary_exec_control(vmx); 4032 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, 4033 vmx->secondary_exec_control); 4034 } 4035 4036 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4037 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4038 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4039 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4040 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4041 4042 vmcs_write16(GUEST_INTR_STATUS, 0); 4043 4044 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4045 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4046 } 4047 4048 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4049 vmcs_write32(PLE_GAP, ple_gap); 4050 vmx->ple_window = ple_window; 4051 vmx->ple_window_dirty = true; 4052 } 4053 4054 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4055 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4056 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4057 4058 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4059 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4060 vmx_set_constant_host_state(vmx); 4061 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4062 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4063 4064 if (cpu_has_vmx_vmfunc()) 4065 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4066 4067 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4068 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4069 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4070 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4071 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4072 4073 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4074 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4075 4076 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 4077 u32 index = vmx_msr_index[i]; 4078 u32 data_low, data_high; 4079 int j = vmx->nmsrs; 4080 4081 if (rdmsr_safe(index, &data_low, &data_high) < 0) 4082 continue; 4083 if (wrmsr_safe(index, data_low, data_high) < 0) 4084 continue; 4085 vmx->guest_msrs[j].index = i; 4086 vmx->guest_msrs[j].data = 0; 4087 vmx->guest_msrs[j].mask = -1ull; 4088 ++vmx->nmsrs; 4089 } 4090 4091 vmx->arch_capabilities = kvm_get_arch_capabilities(); 4092 4093 vm_exit_controls_init(vmx, vmx_vmexit_ctrl()); 4094 4095 /* 22.2.1, 20.8.1 */ 4096 vm_entry_controls_init(vmx, vmx_vmentry_ctrl()); 4097 4098 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4099 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4100 4101 set_cr4_guest_host_mask(vmx); 4102 4103 if (vmx_xsaves_supported()) 4104 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4105 4106 if (enable_pml) { 4107 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4108 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4109 } 4110 4111 if (cpu_has_vmx_encls_vmexit()) 4112 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4113 4114 if (pt_mode == PT_MODE_HOST_GUEST) { 4115 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4116 /* Bit[6~0] are forced to 1, writes are ignored. */ 4117 vmx->pt_desc.guest.output_mask = 0x7F; 4118 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4119 } 4120 } 4121 4122 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4123 { 4124 struct vcpu_vmx *vmx = to_vmx(vcpu); 4125 struct msr_data apic_base_msr; 4126 u64 cr0; 4127 4128 vmx->rmode.vm86_active = 0; 4129 vmx->spec_ctrl = 0; 4130 4131 vcpu->arch.microcode_version = 0x100000000ULL; 4132 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4133 kvm_set_cr8(vcpu, 0); 4134 4135 if (!init_event) { 4136 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4137 MSR_IA32_APICBASE_ENABLE; 4138 if (kvm_vcpu_is_reset_bsp(vcpu)) 4139 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4140 apic_base_msr.host_initiated = true; 4141 kvm_set_apic_base(vcpu, &apic_base_msr); 4142 } 4143 4144 vmx_segment_cache_clear(vmx); 4145 4146 seg_setup(VCPU_SREG_CS); 4147 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4148 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4149 4150 seg_setup(VCPU_SREG_DS); 4151 seg_setup(VCPU_SREG_ES); 4152 seg_setup(VCPU_SREG_FS); 4153 seg_setup(VCPU_SREG_GS); 4154 seg_setup(VCPU_SREG_SS); 4155 4156 vmcs_write16(GUEST_TR_SELECTOR, 0); 4157 vmcs_writel(GUEST_TR_BASE, 0); 4158 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4159 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4160 4161 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4162 vmcs_writel(GUEST_LDTR_BASE, 0); 4163 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4164 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4165 4166 if (!init_event) { 4167 vmcs_write32(GUEST_SYSENTER_CS, 0); 4168 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4169 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4170 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4171 } 4172 4173 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4174 kvm_rip_write(vcpu, 0xfff0); 4175 4176 vmcs_writel(GUEST_GDTR_BASE, 0); 4177 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4178 4179 vmcs_writel(GUEST_IDTR_BASE, 0); 4180 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4181 4182 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4183 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4184 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4185 if (kvm_mpx_supported()) 4186 vmcs_write64(GUEST_BNDCFGS, 0); 4187 4188 setup_msrs(vmx); 4189 4190 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4191 4192 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4193 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4194 if (cpu_need_tpr_shadow(vcpu)) 4195 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4196 __pa(vcpu->arch.apic->regs)); 4197 vmcs_write32(TPR_THRESHOLD, 0); 4198 } 4199 4200 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4201 4202 if (vmx->vpid != 0) 4203 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4204 4205 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4206 vmx->vcpu.arch.cr0 = cr0; 4207 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4208 vmx_set_cr4(vcpu, 0); 4209 vmx_set_efer(vcpu, 0); 4210 4211 update_exception_bitmap(vcpu); 4212 4213 vpid_sync_context(vmx->vpid); 4214 if (init_event) 4215 vmx_clear_hlt(vcpu); 4216 } 4217 4218 static void enable_irq_window(struct kvm_vcpu *vcpu) 4219 { 4220 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, 4221 CPU_BASED_VIRTUAL_INTR_PENDING); 4222 } 4223 4224 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4225 { 4226 if (!enable_vnmi || 4227 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4228 enable_irq_window(vcpu); 4229 return; 4230 } 4231 4232 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, 4233 CPU_BASED_VIRTUAL_NMI_PENDING); 4234 } 4235 4236 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4237 { 4238 struct vcpu_vmx *vmx = to_vmx(vcpu); 4239 uint32_t intr; 4240 int irq = vcpu->arch.interrupt.nr; 4241 4242 trace_kvm_inj_virq(irq); 4243 4244 ++vcpu->stat.irq_injections; 4245 if (vmx->rmode.vm86_active) { 4246 int inc_eip = 0; 4247 if (vcpu->arch.interrupt.soft) 4248 inc_eip = vcpu->arch.event_exit_inst_len; 4249 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) 4250 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4251 return; 4252 } 4253 intr = irq | INTR_INFO_VALID_MASK; 4254 if (vcpu->arch.interrupt.soft) { 4255 intr |= INTR_TYPE_SOFT_INTR; 4256 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4257 vmx->vcpu.arch.event_exit_inst_len); 4258 } else 4259 intr |= INTR_TYPE_EXT_INTR; 4260 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4261 4262 vmx_clear_hlt(vcpu); 4263 } 4264 4265 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4266 { 4267 struct vcpu_vmx *vmx = to_vmx(vcpu); 4268 4269 if (!enable_vnmi) { 4270 /* 4271 * Tracking the NMI-blocked state in software is built upon 4272 * finding the next open IRQ window. This, in turn, depends on 4273 * well-behaving guests: They have to keep IRQs disabled at 4274 * least as long as the NMI handler runs. Otherwise we may 4275 * cause NMI nesting, maybe breaking the guest. But as this is 4276 * highly unlikely, we can live with the residual risk. 4277 */ 4278 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4279 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4280 } 4281 4282 ++vcpu->stat.nmi_injections; 4283 vmx->loaded_vmcs->nmi_known_unmasked = false; 4284 4285 if (vmx->rmode.vm86_active) { 4286 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) 4287 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4288 return; 4289 } 4290 4291 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4292 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4293 4294 vmx_clear_hlt(vcpu); 4295 } 4296 4297 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4298 { 4299 struct vcpu_vmx *vmx = to_vmx(vcpu); 4300 bool masked; 4301 4302 if (!enable_vnmi) 4303 return vmx->loaded_vmcs->soft_vnmi_blocked; 4304 if (vmx->loaded_vmcs->nmi_known_unmasked) 4305 return false; 4306 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4307 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4308 return masked; 4309 } 4310 4311 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4312 { 4313 struct vcpu_vmx *vmx = to_vmx(vcpu); 4314 4315 if (!enable_vnmi) { 4316 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4317 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4318 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4319 } 4320 } else { 4321 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4322 if (masked) 4323 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4324 GUEST_INTR_STATE_NMI); 4325 else 4326 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4327 GUEST_INTR_STATE_NMI); 4328 } 4329 } 4330 4331 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4332 { 4333 if (to_vmx(vcpu)->nested.nested_run_pending) 4334 return 0; 4335 4336 if (!enable_vnmi && 4337 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4338 return 0; 4339 4340 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4341 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4342 | GUEST_INTR_STATE_NMI)); 4343 } 4344 4345 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4346 { 4347 return (!to_vmx(vcpu)->nested.nested_run_pending && 4348 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4349 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4350 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4351 } 4352 4353 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4354 { 4355 int ret; 4356 4357 if (enable_unrestricted_guest) 4358 return 0; 4359 4360 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4361 PAGE_SIZE * 3); 4362 if (ret) 4363 return ret; 4364 to_kvm_vmx(kvm)->tss_addr = addr; 4365 return init_rmode_tss(kvm); 4366 } 4367 4368 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4369 { 4370 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4371 return 0; 4372 } 4373 4374 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4375 { 4376 switch (vec) { 4377 case BP_VECTOR: 4378 /* 4379 * Update instruction length as we may reinject the exception 4380 * from user space while in guest debugging mode. 4381 */ 4382 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4383 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4384 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4385 return false; 4386 /* fall through */ 4387 case DB_VECTOR: 4388 if (vcpu->guest_debug & 4389 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4390 return false; 4391 /* fall through */ 4392 case DE_VECTOR: 4393 case OF_VECTOR: 4394 case BR_VECTOR: 4395 case UD_VECTOR: 4396 case DF_VECTOR: 4397 case SS_VECTOR: 4398 case GP_VECTOR: 4399 case MF_VECTOR: 4400 return true; 4401 break; 4402 } 4403 return false; 4404 } 4405 4406 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4407 int vec, u32 err_code) 4408 { 4409 /* 4410 * Instruction with address size override prefix opcode 0x67 4411 * Cause the #SS fault with 0 error code in VM86 mode. 4412 */ 4413 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4414 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) { 4415 if (vcpu->arch.halt_request) { 4416 vcpu->arch.halt_request = 0; 4417 return kvm_vcpu_halt(vcpu); 4418 } 4419 return 1; 4420 } 4421 return 0; 4422 } 4423 4424 /* 4425 * Forward all other exceptions that are valid in real mode. 4426 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4427 * the required debugging infrastructure rework. 4428 */ 4429 kvm_queue_exception(vcpu, vec); 4430 return 1; 4431 } 4432 4433 /* 4434 * Trigger machine check on the host. We assume all the MSRs are already set up 4435 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4436 * We pass a fake environment to the machine check handler because we want 4437 * the guest to be always treated like user space, no matter what context 4438 * it used internally. 4439 */ 4440 static void kvm_machine_check(void) 4441 { 4442 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4443 struct pt_regs regs = { 4444 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4445 .flags = X86_EFLAGS_IF, 4446 }; 4447 4448 do_machine_check(®s, 0); 4449 #endif 4450 } 4451 4452 static int handle_machine_check(struct kvm_vcpu *vcpu) 4453 { 4454 /* already handled by vcpu_run */ 4455 return 1; 4456 } 4457 4458 static int handle_exception(struct kvm_vcpu *vcpu) 4459 { 4460 struct vcpu_vmx *vmx = to_vmx(vcpu); 4461 struct kvm_run *kvm_run = vcpu->run; 4462 u32 intr_info, ex_no, error_code; 4463 unsigned long cr2, rip, dr6; 4464 u32 vect_info; 4465 enum emulation_result er; 4466 4467 vect_info = vmx->idt_vectoring_info; 4468 intr_info = vmx->exit_intr_info; 4469 4470 if (is_machine_check(intr_info)) 4471 return handle_machine_check(vcpu); 4472 4473 if (is_nmi(intr_info)) 4474 return 1; /* already handled by vmx_vcpu_run() */ 4475 4476 if (is_invalid_opcode(intr_info)) 4477 return handle_ud(vcpu); 4478 4479 error_code = 0; 4480 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4481 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4482 4483 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4484 WARN_ON_ONCE(!enable_vmware_backdoor); 4485 er = kvm_emulate_instruction(vcpu, 4486 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL); 4487 if (er == EMULATE_USER_EXIT) 4488 return 0; 4489 else if (er != EMULATE_DONE) 4490 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4491 return 1; 4492 } 4493 4494 /* 4495 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4496 * MMIO, it is better to report an internal error. 4497 * See the comments in vmx_handle_exit. 4498 */ 4499 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4500 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4501 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4502 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4503 vcpu->run->internal.ndata = 3; 4504 vcpu->run->internal.data[0] = vect_info; 4505 vcpu->run->internal.data[1] = intr_info; 4506 vcpu->run->internal.data[2] = error_code; 4507 return 0; 4508 } 4509 4510 if (is_page_fault(intr_info)) { 4511 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4512 /* EPT won't cause page fault directly */ 4513 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4514 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4515 } 4516 4517 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4518 4519 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4520 return handle_rmode_exception(vcpu, ex_no, error_code); 4521 4522 switch (ex_no) { 4523 case AC_VECTOR: 4524 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4525 return 1; 4526 case DB_VECTOR: 4527 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4528 if (!(vcpu->guest_debug & 4529 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4530 vcpu->arch.dr6 &= ~15; 4531 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4532 if (is_icebp(intr_info)) 4533 skip_emulated_instruction(vcpu); 4534 4535 kvm_queue_exception(vcpu, DB_VECTOR); 4536 return 1; 4537 } 4538 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4539 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4540 /* fall through */ 4541 case BP_VECTOR: 4542 /* 4543 * Update instruction length as we may reinject #BP from 4544 * user space while in guest debugging mode. Reading it for 4545 * #DB as well causes no harm, it is not used in that case. 4546 */ 4547 vmx->vcpu.arch.event_exit_inst_len = 4548 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4549 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4550 rip = kvm_rip_read(vcpu); 4551 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4552 kvm_run->debug.arch.exception = ex_no; 4553 break; 4554 default: 4555 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4556 kvm_run->ex.exception = ex_no; 4557 kvm_run->ex.error_code = error_code; 4558 break; 4559 } 4560 return 0; 4561 } 4562 4563 static int handle_external_interrupt(struct kvm_vcpu *vcpu) 4564 { 4565 ++vcpu->stat.irq_exits; 4566 return 1; 4567 } 4568 4569 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4570 { 4571 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4572 vcpu->mmio_needed = 0; 4573 return 0; 4574 } 4575 4576 static int handle_io(struct kvm_vcpu *vcpu) 4577 { 4578 unsigned long exit_qualification; 4579 int size, in, string; 4580 unsigned port; 4581 4582 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4583 string = (exit_qualification & 16) != 0; 4584 4585 ++vcpu->stat.io_exits; 4586 4587 if (string) 4588 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE; 4589 4590 port = exit_qualification >> 16; 4591 size = (exit_qualification & 7) + 1; 4592 in = (exit_qualification & 8) != 0; 4593 4594 return kvm_fast_pio(vcpu, size, port, in); 4595 } 4596 4597 static void 4598 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4599 { 4600 /* 4601 * Patch in the VMCALL instruction: 4602 */ 4603 hypercall[0] = 0x0f; 4604 hypercall[1] = 0x01; 4605 hypercall[2] = 0xc1; 4606 } 4607 4608 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4609 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4610 { 4611 if (is_guest_mode(vcpu)) { 4612 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4613 unsigned long orig_val = val; 4614 4615 /* 4616 * We get here when L2 changed cr0 in a way that did not change 4617 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4618 * but did change L0 shadowed bits. So we first calculate the 4619 * effective cr0 value that L1 would like to write into the 4620 * hardware. It consists of the L2-owned bits from the new 4621 * value combined with the L1-owned bits from L1's guest_cr0. 4622 */ 4623 val = (val & ~vmcs12->cr0_guest_host_mask) | 4624 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4625 4626 if (!nested_guest_cr0_valid(vcpu, val)) 4627 return 1; 4628 4629 if (kvm_set_cr0(vcpu, val)) 4630 return 1; 4631 vmcs_writel(CR0_READ_SHADOW, orig_val); 4632 return 0; 4633 } else { 4634 if (to_vmx(vcpu)->nested.vmxon && 4635 !nested_host_cr0_valid(vcpu, val)) 4636 return 1; 4637 4638 return kvm_set_cr0(vcpu, val); 4639 } 4640 } 4641 4642 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4643 { 4644 if (is_guest_mode(vcpu)) { 4645 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4646 unsigned long orig_val = val; 4647 4648 /* analogously to handle_set_cr0 */ 4649 val = (val & ~vmcs12->cr4_guest_host_mask) | 4650 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4651 if (kvm_set_cr4(vcpu, val)) 4652 return 1; 4653 vmcs_writel(CR4_READ_SHADOW, orig_val); 4654 return 0; 4655 } else 4656 return kvm_set_cr4(vcpu, val); 4657 } 4658 4659 static int handle_desc(struct kvm_vcpu *vcpu) 4660 { 4661 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4662 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE; 4663 } 4664 4665 static int handle_cr(struct kvm_vcpu *vcpu) 4666 { 4667 unsigned long exit_qualification, val; 4668 int cr; 4669 int reg; 4670 int err; 4671 int ret; 4672 4673 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4674 cr = exit_qualification & 15; 4675 reg = (exit_qualification >> 8) & 15; 4676 switch ((exit_qualification >> 4) & 3) { 4677 case 0: /* mov to cr */ 4678 val = kvm_register_readl(vcpu, reg); 4679 trace_kvm_cr_write(cr, val); 4680 switch (cr) { 4681 case 0: 4682 err = handle_set_cr0(vcpu, val); 4683 return kvm_complete_insn_gp(vcpu, err); 4684 case 3: 4685 WARN_ON_ONCE(enable_unrestricted_guest); 4686 err = kvm_set_cr3(vcpu, val); 4687 return kvm_complete_insn_gp(vcpu, err); 4688 case 4: 4689 err = handle_set_cr4(vcpu, val); 4690 return kvm_complete_insn_gp(vcpu, err); 4691 case 8: { 4692 u8 cr8_prev = kvm_get_cr8(vcpu); 4693 u8 cr8 = (u8)val; 4694 err = kvm_set_cr8(vcpu, cr8); 4695 ret = kvm_complete_insn_gp(vcpu, err); 4696 if (lapic_in_kernel(vcpu)) 4697 return ret; 4698 if (cr8_prev <= cr8) 4699 return ret; 4700 /* 4701 * TODO: we might be squashing a 4702 * KVM_GUESTDBG_SINGLESTEP-triggered 4703 * KVM_EXIT_DEBUG here. 4704 */ 4705 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4706 return 0; 4707 } 4708 } 4709 break; 4710 case 2: /* clts */ 4711 WARN_ONCE(1, "Guest should always own CR0.TS"); 4712 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4713 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4714 return kvm_skip_emulated_instruction(vcpu); 4715 case 1: /*mov from cr*/ 4716 switch (cr) { 4717 case 3: 4718 WARN_ON_ONCE(enable_unrestricted_guest); 4719 val = kvm_read_cr3(vcpu); 4720 kvm_register_write(vcpu, reg, val); 4721 trace_kvm_cr_read(cr, val); 4722 return kvm_skip_emulated_instruction(vcpu); 4723 case 8: 4724 val = kvm_get_cr8(vcpu); 4725 kvm_register_write(vcpu, reg, val); 4726 trace_kvm_cr_read(cr, val); 4727 return kvm_skip_emulated_instruction(vcpu); 4728 } 4729 break; 4730 case 3: /* lmsw */ 4731 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4732 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4733 kvm_lmsw(vcpu, val); 4734 4735 return kvm_skip_emulated_instruction(vcpu); 4736 default: 4737 break; 4738 } 4739 vcpu->run->exit_reason = 0; 4740 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4741 (int)(exit_qualification >> 4) & 3, cr); 4742 return 0; 4743 } 4744 4745 static int handle_dr(struct kvm_vcpu *vcpu) 4746 { 4747 unsigned long exit_qualification; 4748 int dr, dr7, reg; 4749 4750 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4751 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4752 4753 /* First, if DR does not exist, trigger UD */ 4754 if (!kvm_require_dr(vcpu, dr)) 4755 return 1; 4756 4757 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4758 if (!kvm_require_cpl(vcpu, 0)) 4759 return 1; 4760 dr7 = vmcs_readl(GUEST_DR7); 4761 if (dr7 & DR7_GD) { 4762 /* 4763 * As the vm-exit takes precedence over the debug trap, we 4764 * need to emulate the latter, either for the host or the 4765 * guest debugging itself. 4766 */ 4767 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4768 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4769 vcpu->run->debug.arch.dr7 = dr7; 4770 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4771 vcpu->run->debug.arch.exception = DB_VECTOR; 4772 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4773 return 0; 4774 } else { 4775 vcpu->arch.dr6 &= ~15; 4776 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4777 kvm_queue_exception(vcpu, DB_VECTOR); 4778 return 1; 4779 } 4780 } 4781 4782 if (vcpu->guest_debug == 0) { 4783 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, 4784 CPU_BASED_MOV_DR_EXITING); 4785 4786 /* 4787 * No more DR vmexits; force a reload of the debug registers 4788 * and reenter on this instruction. The next vmexit will 4789 * retrieve the full state of the debug registers. 4790 */ 4791 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4792 return 1; 4793 } 4794 4795 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4796 if (exit_qualification & TYPE_MOV_FROM_DR) { 4797 unsigned long val; 4798 4799 if (kvm_get_dr(vcpu, dr, &val)) 4800 return 1; 4801 kvm_register_write(vcpu, reg, val); 4802 } else 4803 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4804 return 1; 4805 4806 return kvm_skip_emulated_instruction(vcpu); 4807 } 4808 4809 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4810 { 4811 return vcpu->arch.dr6; 4812 } 4813 4814 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4815 { 4816 } 4817 4818 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4819 { 4820 get_debugreg(vcpu->arch.db[0], 0); 4821 get_debugreg(vcpu->arch.db[1], 1); 4822 get_debugreg(vcpu->arch.db[2], 2); 4823 get_debugreg(vcpu->arch.db[3], 3); 4824 get_debugreg(vcpu->arch.dr6, 6); 4825 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4826 4827 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4828 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); 4829 } 4830 4831 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4832 { 4833 vmcs_writel(GUEST_DR7, val); 4834 } 4835 4836 static int handle_cpuid(struct kvm_vcpu *vcpu) 4837 { 4838 return kvm_emulate_cpuid(vcpu); 4839 } 4840 4841 static int handle_rdmsr(struct kvm_vcpu *vcpu) 4842 { 4843 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; 4844 struct msr_data msr_info; 4845 4846 msr_info.index = ecx; 4847 msr_info.host_initiated = false; 4848 if (vmx_get_msr(vcpu, &msr_info)) { 4849 trace_kvm_msr_read_ex(ecx); 4850 kvm_inject_gp(vcpu, 0); 4851 return 1; 4852 } 4853 4854 trace_kvm_msr_read(ecx, msr_info.data); 4855 4856 /* FIXME: handling of bits 32:63 of rax, rdx */ 4857 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; 4858 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; 4859 return kvm_skip_emulated_instruction(vcpu); 4860 } 4861 4862 static int handle_wrmsr(struct kvm_vcpu *vcpu) 4863 { 4864 struct msr_data msr; 4865 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; 4866 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) 4867 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); 4868 4869 msr.data = data; 4870 msr.index = ecx; 4871 msr.host_initiated = false; 4872 if (kvm_set_msr(vcpu, &msr) != 0) { 4873 trace_kvm_msr_write_ex(ecx, data); 4874 kvm_inject_gp(vcpu, 0); 4875 return 1; 4876 } 4877 4878 trace_kvm_msr_write(ecx, data); 4879 return kvm_skip_emulated_instruction(vcpu); 4880 } 4881 4882 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4883 { 4884 kvm_apic_update_ppr(vcpu); 4885 return 1; 4886 } 4887 4888 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4889 { 4890 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, 4891 CPU_BASED_VIRTUAL_INTR_PENDING); 4892 4893 kvm_make_request(KVM_REQ_EVENT, vcpu); 4894 4895 ++vcpu->stat.irq_window_exits; 4896 return 1; 4897 } 4898 4899 static int handle_halt(struct kvm_vcpu *vcpu) 4900 { 4901 return kvm_emulate_halt(vcpu); 4902 } 4903 4904 static int handle_vmcall(struct kvm_vcpu *vcpu) 4905 { 4906 return kvm_emulate_hypercall(vcpu); 4907 } 4908 4909 static int handle_invd(struct kvm_vcpu *vcpu) 4910 { 4911 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE; 4912 } 4913 4914 static int handle_invlpg(struct kvm_vcpu *vcpu) 4915 { 4916 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4917 4918 kvm_mmu_invlpg(vcpu, exit_qualification); 4919 return kvm_skip_emulated_instruction(vcpu); 4920 } 4921 4922 static int handle_rdpmc(struct kvm_vcpu *vcpu) 4923 { 4924 int err; 4925 4926 err = kvm_rdpmc(vcpu); 4927 return kvm_complete_insn_gp(vcpu, err); 4928 } 4929 4930 static int handle_wbinvd(struct kvm_vcpu *vcpu) 4931 { 4932 return kvm_emulate_wbinvd(vcpu); 4933 } 4934 4935 static int handle_xsetbv(struct kvm_vcpu *vcpu) 4936 { 4937 u64 new_bv = kvm_read_edx_eax(vcpu); 4938 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); 4939 4940 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 4941 return kvm_skip_emulated_instruction(vcpu); 4942 return 1; 4943 } 4944 4945 static int handle_xsaves(struct kvm_vcpu *vcpu) 4946 { 4947 kvm_skip_emulated_instruction(vcpu); 4948 WARN(1, "this should never happen\n"); 4949 return 1; 4950 } 4951 4952 static int handle_xrstors(struct kvm_vcpu *vcpu) 4953 { 4954 kvm_skip_emulated_instruction(vcpu); 4955 WARN(1, "this should never happen\n"); 4956 return 1; 4957 } 4958 4959 static int handle_apic_access(struct kvm_vcpu *vcpu) 4960 { 4961 if (likely(fasteoi)) { 4962 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4963 int access_type, offset; 4964 4965 access_type = exit_qualification & APIC_ACCESS_TYPE; 4966 offset = exit_qualification & APIC_ACCESS_OFFSET; 4967 /* 4968 * Sane guest uses MOV to write EOI, with written value 4969 * not cared. So make a short-circuit here by avoiding 4970 * heavy instruction emulation. 4971 */ 4972 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 4973 (offset == APIC_EOI)) { 4974 kvm_lapic_set_eoi(vcpu); 4975 return kvm_skip_emulated_instruction(vcpu); 4976 } 4977 } 4978 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE; 4979 } 4980 4981 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 4982 { 4983 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4984 int vector = exit_qualification & 0xff; 4985 4986 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 4987 kvm_apic_set_eoi_accelerated(vcpu, vector); 4988 return 1; 4989 } 4990 4991 static int handle_apic_write(struct kvm_vcpu *vcpu) 4992 { 4993 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4994 u32 offset = exit_qualification & 0xfff; 4995 4996 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 4997 kvm_apic_write_nodecode(vcpu, offset); 4998 return 1; 4999 } 5000 5001 static int handle_task_switch(struct kvm_vcpu *vcpu) 5002 { 5003 struct vcpu_vmx *vmx = to_vmx(vcpu); 5004 unsigned long exit_qualification; 5005 bool has_error_code = false; 5006 u32 error_code = 0; 5007 u16 tss_selector; 5008 int reason, type, idt_v, idt_index; 5009 5010 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5011 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5012 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5013 5014 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5015 5016 reason = (u32)exit_qualification >> 30; 5017 if (reason == TASK_SWITCH_GATE && idt_v) { 5018 switch (type) { 5019 case INTR_TYPE_NMI_INTR: 5020 vcpu->arch.nmi_injected = false; 5021 vmx_set_nmi_mask(vcpu, true); 5022 break; 5023 case INTR_TYPE_EXT_INTR: 5024 case INTR_TYPE_SOFT_INTR: 5025 kvm_clear_interrupt_queue(vcpu); 5026 break; 5027 case INTR_TYPE_HARD_EXCEPTION: 5028 if (vmx->idt_vectoring_info & 5029 VECTORING_INFO_DELIVER_CODE_MASK) { 5030 has_error_code = true; 5031 error_code = 5032 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5033 } 5034 /* fall through */ 5035 case INTR_TYPE_SOFT_EXCEPTION: 5036 kvm_clear_exception_queue(vcpu); 5037 break; 5038 default: 5039 break; 5040 } 5041 } 5042 tss_selector = exit_qualification; 5043 5044 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5045 type != INTR_TYPE_EXT_INTR && 5046 type != INTR_TYPE_NMI_INTR)) 5047 skip_emulated_instruction(vcpu); 5048 5049 if (kvm_task_switch(vcpu, tss_selector, 5050 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, 5051 has_error_code, error_code) == EMULATE_FAIL) { 5052 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5053 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5054 vcpu->run->internal.ndata = 0; 5055 return 0; 5056 } 5057 5058 /* 5059 * TODO: What about debug traps on tss switch? 5060 * Are we supposed to inject them and update dr6? 5061 */ 5062 5063 return 1; 5064 } 5065 5066 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5067 { 5068 unsigned long exit_qualification; 5069 gpa_t gpa; 5070 u64 error_code; 5071 5072 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5073 5074 /* 5075 * EPT violation happened while executing iret from NMI, 5076 * "blocked by NMI" bit has to be set before next VM entry. 5077 * There are errata that may cause this bit to not be set: 5078 * AAK134, BY25. 5079 */ 5080 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5081 enable_vnmi && 5082 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5083 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5084 5085 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5086 trace_kvm_page_fault(gpa, exit_qualification); 5087 5088 /* Is it a read fault? */ 5089 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5090 ? PFERR_USER_MASK : 0; 5091 /* Is it a write fault? */ 5092 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5093 ? PFERR_WRITE_MASK : 0; 5094 /* Is it a fetch fault? */ 5095 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5096 ? PFERR_FETCH_MASK : 0; 5097 /* ept page table entry is present? */ 5098 error_code |= (exit_qualification & 5099 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5100 EPT_VIOLATION_EXECUTABLE)) 5101 ? PFERR_PRESENT_MASK : 0; 5102 5103 error_code |= (exit_qualification & 0x100) != 0 ? 5104 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5105 5106 vcpu->arch.exit_qualification = exit_qualification; 5107 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5108 } 5109 5110 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5111 { 5112 gpa_t gpa; 5113 5114 /* 5115 * A nested guest cannot optimize MMIO vmexits, because we have an 5116 * nGPA here instead of the required GPA. 5117 */ 5118 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5119 if (!is_guest_mode(vcpu) && 5120 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5121 trace_kvm_fast_mmio(gpa); 5122 /* 5123 * Doing kvm_skip_emulated_instruction() depends on undefined 5124 * behavior: Intel's manual doesn't mandate 5125 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG 5126 * occurs and while on real hardware it was observed to be set, 5127 * other hypervisors (namely Hyper-V) don't set it, we end up 5128 * advancing IP with some random value. Disable fast mmio when 5129 * running nested and keep it for real hardware in hope that 5130 * VM_EXIT_INSTRUCTION_LEN will always be set correctly. 5131 */ 5132 if (!static_cpu_has(X86_FEATURE_HYPERVISOR)) 5133 return kvm_skip_emulated_instruction(vcpu); 5134 else 5135 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) == 5136 EMULATE_DONE; 5137 } 5138 5139 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5140 } 5141 5142 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5143 { 5144 WARN_ON_ONCE(!enable_vnmi); 5145 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, 5146 CPU_BASED_VIRTUAL_NMI_PENDING); 5147 ++vcpu->stat.nmi_window_exits; 5148 kvm_make_request(KVM_REQ_EVENT, vcpu); 5149 5150 return 1; 5151 } 5152 5153 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5154 { 5155 struct vcpu_vmx *vmx = to_vmx(vcpu); 5156 enum emulation_result err = EMULATE_DONE; 5157 int ret = 1; 5158 u32 cpu_exec_ctrl; 5159 bool intr_window_requested; 5160 unsigned count = 130; 5161 5162 /* 5163 * We should never reach the point where we are emulating L2 5164 * due to invalid guest state as that means we incorrectly 5165 * allowed a nested VMEntry with an invalid vmcs12. 5166 */ 5167 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5168 5169 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5170 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; 5171 5172 while (vmx->emulation_required && count-- != 0) { 5173 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5174 return handle_interrupt_window(&vmx->vcpu); 5175 5176 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5177 return 1; 5178 5179 err = kvm_emulate_instruction(vcpu, 0); 5180 5181 if (err == EMULATE_USER_EXIT) { 5182 ++vcpu->stat.mmio_exits; 5183 ret = 0; 5184 goto out; 5185 } 5186 5187 if (err != EMULATE_DONE) 5188 goto emulation_error; 5189 5190 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5191 vcpu->arch.exception.pending) 5192 goto emulation_error; 5193 5194 if (vcpu->arch.halt_request) { 5195 vcpu->arch.halt_request = 0; 5196 ret = kvm_vcpu_halt(vcpu); 5197 goto out; 5198 } 5199 5200 if (signal_pending(current)) 5201 goto out; 5202 if (need_resched()) 5203 schedule(); 5204 } 5205 5206 out: 5207 return ret; 5208 5209 emulation_error: 5210 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5211 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5212 vcpu->run->internal.ndata = 0; 5213 return 0; 5214 } 5215 5216 static void grow_ple_window(struct kvm_vcpu *vcpu) 5217 { 5218 struct vcpu_vmx *vmx = to_vmx(vcpu); 5219 int old = vmx->ple_window; 5220 5221 vmx->ple_window = __grow_ple_window(old, ple_window, 5222 ple_window_grow, 5223 ple_window_max); 5224 5225 if (vmx->ple_window != old) 5226 vmx->ple_window_dirty = true; 5227 5228 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); 5229 } 5230 5231 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5232 { 5233 struct vcpu_vmx *vmx = to_vmx(vcpu); 5234 int old = vmx->ple_window; 5235 5236 vmx->ple_window = __shrink_ple_window(old, ple_window, 5237 ple_window_shrink, 5238 ple_window); 5239 5240 if (vmx->ple_window != old) 5241 vmx->ple_window_dirty = true; 5242 5243 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); 5244 } 5245 5246 /* 5247 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5248 */ 5249 static void wakeup_handler(void) 5250 { 5251 struct kvm_vcpu *vcpu; 5252 int cpu = smp_processor_id(); 5253 5254 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5255 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5256 blocked_vcpu_list) { 5257 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5258 5259 if (pi_test_on(pi_desc) == 1) 5260 kvm_vcpu_kick(vcpu); 5261 } 5262 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5263 } 5264 5265 static void vmx_enable_tdp(void) 5266 { 5267 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5268 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5269 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5270 0ull, VMX_EPT_EXECUTABLE_MASK, 5271 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5272 VMX_EPT_RWX_MASK, 0ull); 5273 5274 ept_set_mmio_spte_mask(); 5275 kvm_enable_tdp(); 5276 } 5277 5278 /* 5279 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5280 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5281 */ 5282 static int handle_pause(struct kvm_vcpu *vcpu) 5283 { 5284 if (!kvm_pause_in_guest(vcpu->kvm)) 5285 grow_ple_window(vcpu); 5286 5287 /* 5288 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5289 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5290 * never set PAUSE_EXITING and just set PLE if supported, 5291 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5292 */ 5293 kvm_vcpu_on_spin(vcpu, true); 5294 return kvm_skip_emulated_instruction(vcpu); 5295 } 5296 5297 static int handle_nop(struct kvm_vcpu *vcpu) 5298 { 5299 return kvm_skip_emulated_instruction(vcpu); 5300 } 5301 5302 static int handle_mwait(struct kvm_vcpu *vcpu) 5303 { 5304 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5305 return handle_nop(vcpu); 5306 } 5307 5308 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5309 { 5310 kvm_queue_exception(vcpu, UD_VECTOR); 5311 return 1; 5312 } 5313 5314 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5315 { 5316 return 1; 5317 } 5318 5319 static int handle_monitor(struct kvm_vcpu *vcpu) 5320 { 5321 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5322 return handle_nop(vcpu); 5323 } 5324 5325 static int handle_invpcid(struct kvm_vcpu *vcpu) 5326 { 5327 u32 vmx_instruction_info; 5328 unsigned long type; 5329 bool pcid_enabled; 5330 gva_t gva; 5331 struct x86_exception e; 5332 unsigned i; 5333 unsigned long roots_to_free = 0; 5334 struct { 5335 u64 pcid; 5336 u64 gla; 5337 } operand; 5338 5339 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5340 kvm_queue_exception(vcpu, UD_VECTOR); 5341 return 1; 5342 } 5343 5344 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5345 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5346 5347 if (type > 3) { 5348 kvm_inject_gp(vcpu, 0); 5349 return 1; 5350 } 5351 5352 /* According to the Intel instruction reference, the memory operand 5353 * is read even if it isn't needed (e.g., for type==all) 5354 */ 5355 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5356 vmx_instruction_info, false, &gva)) 5357 return 1; 5358 5359 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5360 kvm_inject_page_fault(vcpu, &e); 5361 return 1; 5362 } 5363 5364 if (operand.pcid >> 12 != 0) { 5365 kvm_inject_gp(vcpu, 0); 5366 return 1; 5367 } 5368 5369 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5370 5371 switch (type) { 5372 case INVPCID_TYPE_INDIV_ADDR: 5373 if ((!pcid_enabled && (operand.pcid != 0)) || 5374 is_noncanonical_address(operand.gla, vcpu)) { 5375 kvm_inject_gp(vcpu, 0); 5376 return 1; 5377 } 5378 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5379 return kvm_skip_emulated_instruction(vcpu); 5380 5381 case INVPCID_TYPE_SINGLE_CTXT: 5382 if (!pcid_enabled && (operand.pcid != 0)) { 5383 kvm_inject_gp(vcpu, 0); 5384 return 1; 5385 } 5386 5387 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5388 kvm_mmu_sync_roots(vcpu); 5389 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5390 } 5391 5392 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5393 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5394 == operand.pcid) 5395 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5396 5397 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5398 /* 5399 * If neither the current cr3 nor any of the prev_roots use the 5400 * given PCID, then nothing needs to be done here because a 5401 * resync will happen anyway before switching to any other CR3. 5402 */ 5403 5404 return kvm_skip_emulated_instruction(vcpu); 5405 5406 case INVPCID_TYPE_ALL_NON_GLOBAL: 5407 /* 5408 * Currently, KVM doesn't mark global entries in the shadow 5409 * page tables, so a non-global flush just degenerates to a 5410 * global flush. If needed, we could optimize this later by 5411 * keeping track of global entries in shadow page tables. 5412 */ 5413 5414 /* fall-through */ 5415 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5416 kvm_mmu_unload(vcpu); 5417 return kvm_skip_emulated_instruction(vcpu); 5418 5419 default: 5420 BUG(); /* We have already checked above that type <= 3 */ 5421 } 5422 } 5423 5424 static int handle_pml_full(struct kvm_vcpu *vcpu) 5425 { 5426 unsigned long exit_qualification; 5427 5428 trace_kvm_pml_full(vcpu->vcpu_id); 5429 5430 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5431 5432 /* 5433 * PML buffer FULL happened while executing iret from NMI, 5434 * "blocked by NMI" bit has to be set before next VM entry. 5435 */ 5436 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5437 enable_vnmi && 5438 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5439 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5440 GUEST_INTR_STATE_NMI); 5441 5442 /* 5443 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5444 * here.., and there's no userspace involvement needed for PML. 5445 */ 5446 return 1; 5447 } 5448 5449 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5450 { 5451 if (!to_vmx(vcpu)->req_immediate_exit) 5452 kvm_lapic_expired_hv_timer(vcpu); 5453 return 1; 5454 } 5455 5456 /* 5457 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5458 * are overwritten by nested_vmx_setup() when nested=1. 5459 */ 5460 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5461 { 5462 kvm_queue_exception(vcpu, UD_VECTOR); 5463 return 1; 5464 } 5465 5466 static int handle_encls(struct kvm_vcpu *vcpu) 5467 { 5468 /* 5469 * SGX virtualization is not yet supported. There is no software 5470 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5471 * to prevent the guest from executing ENCLS. 5472 */ 5473 kvm_queue_exception(vcpu, UD_VECTOR); 5474 return 1; 5475 } 5476 5477 /* 5478 * The exit handlers return 1 if the exit was handled fully and guest execution 5479 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5480 * to be done to userspace and return 0. 5481 */ 5482 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5483 [EXIT_REASON_EXCEPTION_NMI] = handle_exception, 5484 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5485 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5486 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5487 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5488 [EXIT_REASON_CR_ACCESS] = handle_cr, 5489 [EXIT_REASON_DR_ACCESS] = handle_dr, 5490 [EXIT_REASON_CPUID] = handle_cpuid, 5491 [EXIT_REASON_MSR_READ] = handle_rdmsr, 5492 [EXIT_REASON_MSR_WRITE] = handle_wrmsr, 5493 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, 5494 [EXIT_REASON_HLT] = handle_halt, 5495 [EXIT_REASON_INVD] = handle_invd, 5496 [EXIT_REASON_INVLPG] = handle_invlpg, 5497 [EXIT_REASON_RDPMC] = handle_rdpmc, 5498 [EXIT_REASON_VMCALL] = handle_vmcall, 5499 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5500 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5501 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5502 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5503 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5504 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5505 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5506 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5507 [EXIT_REASON_VMON] = handle_vmx_instruction, 5508 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5509 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5510 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5511 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5512 [EXIT_REASON_WBINVD] = handle_wbinvd, 5513 [EXIT_REASON_XSETBV] = handle_xsetbv, 5514 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5515 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5516 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5517 [EXIT_REASON_LDTR_TR] = handle_desc, 5518 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5519 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5520 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5521 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5522 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5523 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5524 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5525 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5526 [EXIT_REASON_RDRAND] = handle_invalid_op, 5527 [EXIT_REASON_RDSEED] = handle_invalid_op, 5528 [EXIT_REASON_XSAVES] = handle_xsaves, 5529 [EXIT_REASON_XRSTORS] = handle_xrstors, 5530 [EXIT_REASON_PML_FULL] = handle_pml_full, 5531 [EXIT_REASON_INVPCID] = handle_invpcid, 5532 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5533 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5534 [EXIT_REASON_ENCLS] = handle_encls, 5535 }; 5536 5537 static const int kvm_vmx_max_exit_handlers = 5538 ARRAY_SIZE(kvm_vmx_exit_handlers); 5539 5540 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5541 { 5542 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5543 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5544 } 5545 5546 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5547 { 5548 if (vmx->pml_pg) { 5549 __free_page(vmx->pml_pg); 5550 vmx->pml_pg = NULL; 5551 } 5552 } 5553 5554 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5555 { 5556 struct vcpu_vmx *vmx = to_vmx(vcpu); 5557 u64 *pml_buf; 5558 u16 pml_idx; 5559 5560 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5561 5562 /* Do nothing if PML buffer is empty */ 5563 if (pml_idx == (PML_ENTITY_NUM - 1)) 5564 return; 5565 5566 /* PML index always points to next available PML buffer entity */ 5567 if (pml_idx >= PML_ENTITY_NUM) 5568 pml_idx = 0; 5569 else 5570 pml_idx++; 5571 5572 pml_buf = page_address(vmx->pml_pg); 5573 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5574 u64 gpa; 5575 5576 gpa = pml_buf[pml_idx]; 5577 WARN_ON(gpa & (PAGE_SIZE - 1)); 5578 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5579 } 5580 5581 /* reset PML index */ 5582 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5583 } 5584 5585 /* 5586 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5587 * Called before reporting dirty_bitmap to userspace. 5588 */ 5589 static void kvm_flush_pml_buffers(struct kvm *kvm) 5590 { 5591 int i; 5592 struct kvm_vcpu *vcpu; 5593 /* 5594 * We only need to kick vcpu out of guest mode here, as PML buffer 5595 * is flushed at beginning of all VMEXITs, and it's obvious that only 5596 * vcpus running in guest are possible to have unflushed GPAs in PML 5597 * buffer. 5598 */ 5599 kvm_for_each_vcpu(i, vcpu, kvm) 5600 kvm_vcpu_kick(vcpu); 5601 } 5602 5603 static void vmx_dump_sel(char *name, uint32_t sel) 5604 { 5605 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5606 name, vmcs_read16(sel), 5607 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5608 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5609 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5610 } 5611 5612 static void vmx_dump_dtsel(char *name, uint32_t limit) 5613 { 5614 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5615 name, vmcs_read32(limit), 5616 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5617 } 5618 5619 static void dump_vmcs(void) 5620 { 5621 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5622 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5623 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5624 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5625 u32 secondary_exec_control = 0; 5626 unsigned long cr4 = vmcs_readl(GUEST_CR4); 5627 u64 efer = vmcs_read64(GUEST_IA32_EFER); 5628 int i, n; 5629 5630 if (cpu_has_secondary_exec_ctrls()) 5631 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5632 5633 pr_err("*** Guest State ***\n"); 5634 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5635 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5636 vmcs_readl(CR0_GUEST_HOST_MASK)); 5637 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5638 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5639 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5640 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5641 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5642 { 5643 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5644 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5645 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5646 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5647 } 5648 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5649 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5650 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5651 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5652 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5653 vmcs_readl(GUEST_SYSENTER_ESP), 5654 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5655 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5656 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5657 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5658 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5659 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5660 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5661 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5662 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5663 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5664 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5665 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5666 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5667 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5668 efer, vmcs_read64(GUEST_IA32_PAT)); 5669 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5670 vmcs_read64(GUEST_IA32_DEBUGCTL), 5671 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5672 if (cpu_has_load_perf_global_ctrl() && 5673 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5674 pr_err("PerfGlobCtl = 0x%016llx\n", 5675 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5676 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5677 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5678 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5679 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5680 vmcs_read32(GUEST_ACTIVITY_STATE)); 5681 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5682 pr_err("InterruptStatus = %04x\n", 5683 vmcs_read16(GUEST_INTR_STATUS)); 5684 5685 pr_err("*** Host State ***\n"); 5686 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5687 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5688 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5689 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5690 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5691 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5692 vmcs_read16(HOST_TR_SELECTOR)); 5693 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5694 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5695 vmcs_readl(HOST_TR_BASE)); 5696 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5697 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5698 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5699 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5700 vmcs_readl(HOST_CR4)); 5701 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5702 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5703 vmcs_read32(HOST_IA32_SYSENTER_CS), 5704 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5705 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5706 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5707 vmcs_read64(HOST_IA32_EFER), 5708 vmcs_read64(HOST_IA32_PAT)); 5709 if (cpu_has_load_perf_global_ctrl() && 5710 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5711 pr_err("PerfGlobCtl = 0x%016llx\n", 5712 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5713 5714 pr_err("*** Control State ***\n"); 5715 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5716 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5717 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5718 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5719 vmcs_read32(EXCEPTION_BITMAP), 5720 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5721 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5722 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5723 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5724 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5725 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5726 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5727 vmcs_read32(VM_EXIT_INTR_INFO), 5728 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5729 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5730 pr_err(" reason=%08x qualification=%016lx\n", 5731 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5732 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5733 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5734 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5735 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5736 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5737 pr_err("TSC Multiplier = 0x%016llx\n", 5738 vmcs_read64(TSC_MULTIPLIER)); 5739 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) 5740 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5741 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5742 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5743 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5744 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5745 n = vmcs_read32(CR3_TARGET_COUNT); 5746 for (i = 0; i + 1 < n; i += 4) 5747 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5748 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5749 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5750 if (i < n) 5751 pr_err("CR3 target%u=%016lx\n", 5752 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5753 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5754 pr_err("PLE Gap=%08x Window=%08x\n", 5755 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5756 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5757 pr_err("Virtual processor ID = 0x%04x\n", 5758 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5759 } 5760 5761 /* 5762 * The guest has exited. See if we can fix it or if we need userspace 5763 * assistance. 5764 */ 5765 static int vmx_handle_exit(struct kvm_vcpu *vcpu) 5766 { 5767 struct vcpu_vmx *vmx = to_vmx(vcpu); 5768 u32 exit_reason = vmx->exit_reason; 5769 u32 vectoring_info = vmx->idt_vectoring_info; 5770 5771 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5772 5773 /* 5774 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5775 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5776 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5777 * mode as if vcpus is in root mode, the PML buffer must has been 5778 * flushed already. 5779 */ 5780 if (enable_pml) 5781 vmx_flush_pml_buffer(vcpu); 5782 5783 /* If guest state is invalid, start emulating */ 5784 if (vmx->emulation_required) 5785 return handle_invalid_guest_state(vcpu); 5786 5787 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5788 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5789 5790 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5791 dump_vmcs(); 5792 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5793 vcpu->run->fail_entry.hardware_entry_failure_reason 5794 = exit_reason; 5795 return 0; 5796 } 5797 5798 if (unlikely(vmx->fail)) { 5799 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5800 vcpu->run->fail_entry.hardware_entry_failure_reason 5801 = vmcs_read32(VM_INSTRUCTION_ERROR); 5802 return 0; 5803 } 5804 5805 /* 5806 * Note: 5807 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5808 * delivery event since it indicates guest is accessing MMIO. 5809 * The vm-exit can be triggered again after return to guest that 5810 * will cause infinite loop. 5811 */ 5812 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5813 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5814 exit_reason != EXIT_REASON_EPT_VIOLATION && 5815 exit_reason != EXIT_REASON_PML_FULL && 5816 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5817 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5818 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5819 vcpu->run->internal.ndata = 3; 5820 vcpu->run->internal.data[0] = vectoring_info; 5821 vcpu->run->internal.data[1] = exit_reason; 5822 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5823 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5824 vcpu->run->internal.ndata++; 5825 vcpu->run->internal.data[3] = 5826 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5827 } 5828 return 0; 5829 } 5830 5831 if (unlikely(!enable_vnmi && 5832 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5833 if (vmx_interrupt_allowed(vcpu)) { 5834 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5835 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5836 vcpu->arch.nmi_pending) { 5837 /* 5838 * This CPU don't support us in finding the end of an 5839 * NMI-blocked window if the guest runs with IRQs 5840 * disabled. So we pull the trigger after 1 s of 5841 * futile waiting, but inform the user about this. 5842 */ 5843 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5844 "state on VCPU %d after 1 s timeout\n", 5845 __func__, vcpu->vcpu_id); 5846 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5847 } 5848 } 5849 5850 if (exit_reason < kvm_vmx_max_exit_handlers 5851 && kvm_vmx_exit_handlers[exit_reason]) 5852 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5853 else { 5854 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", 5855 exit_reason); 5856 kvm_queue_exception(vcpu, UD_VECTOR); 5857 return 1; 5858 } 5859 } 5860 5861 /* 5862 * Software based L1D cache flush which is used when microcode providing 5863 * the cache control MSR is not loaded. 5864 * 5865 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5866 * flush it is required to read in 64 KiB because the replacement algorithm 5867 * is not exactly LRU. This could be sized at runtime via topology 5868 * information but as all relevant affected CPUs have 32KiB L1D cache size 5869 * there is no point in doing so. 5870 */ 5871 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5872 { 5873 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5874 5875 /* 5876 * This code is only executed when the the flush mode is 'cond' or 5877 * 'always' 5878 */ 5879 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5880 bool flush_l1d; 5881 5882 /* 5883 * Clear the per-vcpu flush bit, it gets set again 5884 * either from vcpu_run() or from one of the unsafe 5885 * VMEXIT handlers. 5886 */ 5887 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5888 vcpu->arch.l1tf_flush_l1d = false; 5889 5890 /* 5891 * Clear the per-cpu flush bit, it gets set again from 5892 * the interrupt handlers. 5893 */ 5894 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 5895 kvm_clear_cpu_l1tf_flush_l1d(); 5896 5897 if (!flush_l1d) 5898 return; 5899 } 5900 5901 vcpu->stat.l1d_flush++; 5902 5903 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 5904 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 5905 return; 5906 } 5907 5908 asm volatile( 5909 /* First ensure the pages are in the TLB */ 5910 "xorl %%eax, %%eax\n" 5911 ".Lpopulate_tlb:\n\t" 5912 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5913 "addl $4096, %%eax\n\t" 5914 "cmpl %%eax, %[size]\n\t" 5915 "jne .Lpopulate_tlb\n\t" 5916 "xorl %%eax, %%eax\n\t" 5917 "cpuid\n\t" 5918 /* Now fill the cache */ 5919 "xorl %%eax, %%eax\n" 5920 ".Lfill_cache:\n" 5921 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5922 "addl $64, %%eax\n\t" 5923 "cmpl %%eax, %[size]\n\t" 5924 "jne .Lfill_cache\n\t" 5925 "lfence\n" 5926 :: [flush_pages] "r" (vmx_l1d_flush_pages), 5927 [size] "r" (size) 5928 : "eax", "ebx", "ecx", "edx"); 5929 } 5930 5931 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 5932 { 5933 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5934 5935 if (is_guest_mode(vcpu) && 5936 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 5937 return; 5938 5939 if (irr == -1 || tpr < irr) { 5940 vmcs_write32(TPR_THRESHOLD, 0); 5941 return; 5942 } 5943 5944 vmcs_write32(TPR_THRESHOLD, irr); 5945 } 5946 5947 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 5948 { 5949 u32 sec_exec_control; 5950 5951 if (!lapic_in_kernel(vcpu)) 5952 return; 5953 5954 if (!flexpriority_enabled && 5955 !cpu_has_vmx_virtualize_x2apic_mode()) 5956 return; 5957 5958 /* Postpone execution until vmcs01 is the current VMCS. */ 5959 if (is_guest_mode(vcpu)) { 5960 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true; 5961 return; 5962 } 5963 5964 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5965 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5966 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 5967 5968 switch (kvm_get_apic_mode(vcpu)) { 5969 case LAPIC_MODE_INVALID: 5970 WARN_ONCE(true, "Invalid local APIC state"); 5971 case LAPIC_MODE_DISABLED: 5972 break; 5973 case LAPIC_MODE_XAPIC: 5974 if (flexpriority_enabled) { 5975 sec_exec_control |= 5976 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 5977 vmx_flush_tlb(vcpu, true); 5978 } 5979 break; 5980 case LAPIC_MODE_X2APIC: 5981 if (cpu_has_vmx_virtualize_x2apic_mode()) 5982 sec_exec_control |= 5983 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 5984 break; 5985 } 5986 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); 5987 5988 vmx_update_msr_bitmap(vcpu); 5989 } 5990 5991 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 5992 { 5993 if (!is_guest_mode(vcpu)) { 5994 vmcs_write64(APIC_ACCESS_ADDR, hpa); 5995 vmx_flush_tlb(vcpu, true); 5996 } 5997 } 5998 5999 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6000 { 6001 u16 status; 6002 u8 old; 6003 6004 if (max_isr == -1) 6005 max_isr = 0; 6006 6007 status = vmcs_read16(GUEST_INTR_STATUS); 6008 old = status >> 8; 6009 if (max_isr != old) { 6010 status &= 0xff; 6011 status |= max_isr << 8; 6012 vmcs_write16(GUEST_INTR_STATUS, status); 6013 } 6014 } 6015 6016 static void vmx_set_rvi(int vector) 6017 { 6018 u16 status; 6019 u8 old; 6020 6021 if (vector == -1) 6022 vector = 0; 6023 6024 status = vmcs_read16(GUEST_INTR_STATUS); 6025 old = (u8)status & 0xff; 6026 if ((u8)vector != old) { 6027 status &= ~0xff; 6028 status |= (u8)vector; 6029 vmcs_write16(GUEST_INTR_STATUS, status); 6030 } 6031 } 6032 6033 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6034 { 6035 /* 6036 * When running L2, updating RVI is only relevant when 6037 * vmcs12 virtual-interrupt-delivery enabled. 6038 * However, it can be enabled only when L1 also 6039 * intercepts external-interrupts and in that case 6040 * we should not update vmcs02 RVI but instead intercept 6041 * interrupt. Therefore, do nothing when running L2. 6042 */ 6043 if (!is_guest_mode(vcpu)) 6044 vmx_set_rvi(max_irr); 6045 } 6046 6047 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6048 { 6049 struct vcpu_vmx *vmx = to_vmx(vcpu); 6050 int max_irr; 6051 bool max_irr_updated; 6052 6053 WARN_ON(!vcpu->arch.apicv_active); 6054 if (pi_test_on(&vmx->pi_desc)) { 6055 pi_clear_on(&vmx->pi_desc); 6056 /* 6057 * IOMMU can write to PIR.ON, so the barrier matters even on UP. 6058 * But on x86 this is just a compiler barrier anyway. 6059 */ 6060 smp_mb__after_atomic(); 6061 max_irr_updated = 6062 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6063 6064 /* 6065 * If we are running L2 and L1 has a new pending interrupt 6066 * which can be injected, we should re-evaluate 6067 * what should be done with this new L1 interrupt. 6068 * If L1 intercepts external-interrupts, we should 6069 * exit from L2 to L1. Otherwise, interrupt should be 6070 * delivered directly to L2. 6071 */ 6072 if (is_guest_mode(vcpu) && max_irr_updated) { 6073 if (nested_exit_on_intr(vcpu)) 6074 kvm_vcpu_exiting_guest_mode(vcpu); 6075 else 6076 kvm_make_request(KVM_REQ_EVENT, vcpu); 6077 } 6078 } else { 6079 max_irr = kvm_lapic_find_highest_irr(vcpu); 6080 } 6081 vmx_hwapic_irr_update(vcpu, max_irr); 6082 return max_irr; 6083 } 6084 6085 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6086 { 6087 if (!kvm_vcpu_apicv_active(vcpu)) 6088 return; 6089 6090 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6091 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6092 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6093 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6094 } 6095 6096 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6097 { 6098 struct vcpu_vmx *vmx = to_vmx(vcpu); 6099 6100 pi_clear_on(&vmx->pi_desc); 6101 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6102 } 6103 6104 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) 6105 { 6106 u32 exit_intr_info = 0; 6107 u16 basic_exit_reason = (u16)vmx->exit_reason; 6108 6109 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY 6110 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI)) 6111 return; 6112 6113 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6114 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6115 vmx->exit_intr_info = exit_intr_info; 6116 6117 /* if exit due to PF check for async PF */ 6118 if (is_page_fault(exit_intr_info)) 6119 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6120 6121 /* Handle machine checks before interrupts are enabled */ 6122 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY || 6123 is_machine_check(exit_intr_info)) 6124 kvm_machine_check(); 6125 6126 /* We need to handle NMIs before interrupts are enabled */ 6127 if (is_nmi(exit_intr_info)) { 6128 kvm_before_interrupt(&vmx->vcpu); 6129 asm("int $2"); 6130 kvm_after_interrupt(&vmx->vcpu); 6131 } 6132 } 6133 6134 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) 6135 { 6136 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6137 6138 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) 6139 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { 6140 unsigned int vector; 6141 unsigned long entry; 6142 gate_desc *desc; 6143 struct vcpu_vmx *vmx = to_vmx(vcpu); 6144 #ifdef CONFIG_X86_64 6145 unsigned long tmp; 6146 #endif 6147 6148 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6149 desc = (gate_desc *)vmx->host_idt_base + vector; 6150 entry = gate_offset(desc); 6151 asm volatile( 6152 #ifdef CONFIG_X86_64 6153 "mov %%" _ASM_SP ", %[sp]\n\t" 6154 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6155 "push $%c[ss]\n\t" 6156 "push %[sp]\n\t" 6157 #endif 6158 "pushf\n\t" 6159 __ASM_SIZE(push) " $%c[cs]\n\t" 6160 CALL_NOSPEC 6161 : 6162 #ifdef CONFIG_X86_64 6163 [sp]"=&r"(tmp), 6164 #endif 6165 ASM_CALL_CONSTRAINT 6166 : 6167 THUNK_TARGET(entry), 6168 [ss]"i"(__KERNEL_DS), 6169 [cs]"i"(__KERNEL_CS) 6170 ); 6171 } 6172 } 6173 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr); 6174 6175 static bool vmx_has_emulated_msr(int index) 6176 { 6177 switch (index) { 6178 case MSR_IA32_SMBASE: 6179 /* 6180 * We cannot do SMM unless we can run the guest in big 6181 * real mode. 6182 */ 6183 return enable_unrestricted_guest || emulate_invalid_guest_state; 6184 case MSR_AMD64_VIRT_SPEC_CTRL: 6185 /* This is AMD only. */ 6186 return false; 6187 default: 6188 return true; 6189 } 6190 } 6191 6192 static bool vmx_pt_supported(void) 6193 { 6194 return pt_mode == PT_MODE_HOST_GUEST; 6195 } 6196 6197 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6198 { 6199 u32 exit_intr_info; 6200 bool unblock_nmi; 6201 u8 vector; 6202 bool idtv_info_valid; 6203 6204 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6205 6206 if (enable_vnmi) { 6207 if (vmx->loaded_vmcs->nmi_known_unmasked) 6208 return; 6209 /* 6210 * Can't use vmx->exit_intr_info since we're not sure what 6211 * the exit reason is. 6212 */ 6213 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6214 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6215 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6216 /* 6217 * SDM 3: 27.7.1.2 (September 2008) 6218 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6219 * a guest IRET fault. 6220 * SDM 3: 23.2.2 (September 2008) 6221 * Bit 12 is undefined in any of the following cases: 6222 * If the VM exit sets the valid bit in the IDT-vectoring 6223 * information field. 6224 * If the VM exit is due to a double fault. 6225 */ 6226 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6227 vector != DF_VECTOR && !idtv_info_valid) 6228 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6229 GUEST_INTR_STATE_NMI); 6230 else 6231 vmx->loaded_vmcs->nmi_known_unmasked = 6232 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6233 & GUEST_INTR_STATE_NMI); 6234 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6235 vmx->loaded_vmcs->vnmi_blocked_time += 6236 ktime_to_ns(ktime_sub(ktime_get(), 6237 vmx->loaded_vmcs->entry_time)); 6238 } 6239 6240 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6241 u32 idt_vectoring_info, 6242 int instr_len_field, 6243 int error_code_field) 6244 { 6245 u8 vector; 6246 int type; 6247 bool idtv_info_valid; 6248 6249 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6250 6251 vcpu->arch.nmi_injected = false; 6252 kvm_clear_exception_queue(vcpu); 6253 kvm_clear_interrupt_queue(vcpu); 6254 6255 if (!idtv_info_valid) 6256 return; 6257 6258 kvm_make_request(KVM_REQ_EVENT, vcpu); 6259 6260 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6261 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6262 6263 switch (type) { 6264 case INTR_TYPE_NMI_INTR: 6265 vcpu->arch.nmi_injected = true; 6266 /* 6267 * SDM 3: 27.7.1.2 (September 2008) 6268 * Clear bit "block by NMI" before VM entry if a NMI 6269 * delivery faulted. 6270 */ 6271 vmx_set_nmi_mask(vcpu, false); 6272 break; 6273 case INTR_TYPE_SOFT_EXCEPTION: 6274 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6275 /* fall through */ 6276 case INTR_TYPE_HARD_EXCEPTION: 6277 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6278 u32 err = vmcs_read32(error_code_field); 6279 kvm_requeue_exception_e(vcpu, vector, err); 6280 } else 6281 kvm_requeue_exception(vcpu, vector); 6282 break; 6283 case INTR_TYPE_SOFT_INTR: 6284 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6285 /* fall through */ 6286 case INTR_TYPE_EXT_INTR: 6287 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6288 break; 6289 default: 6290 break; 6291 } 6292 } 6293 6294 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6295 { 6296 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6297 VM_EXIT_INSTRUCTION_LEN, 6298 IDT_VECTORING_ERROR_CODE); 6299 } 6300 6301 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6302 { 6303 __vmx_complete_interrupts(vcpu, 6304 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6305 VM_ENTRY_INSTRUCTION_LEN, 6306 VM_ENTRY_EXCEPTION_ERROR_CODE); 6307 6308 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6309 } 6310 6311 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6312 { 6313 int i, nr_msrs; 6314 struct perf_guest_switch_msr *msrs; 6315 6316 msrs = perf_guest_get_msrs(&nr_msrs); 6317 6318 if (!msrs) 6319 return; 6320 6321 for (i = 0; i < nr_msrs; i++) 6322 if (msrs[i].host == msrs[i].guest) 6323 clear_atomic_switch_msr(vmx, msrs[i].msr); 6324 else 6325 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6326 msrs[i].host, false); 6327 } 6328 6329 static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val) 6330 { 6331 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val); 6332 if (!vmx->loaded_vmcs->hv_timer_armed) 6333 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, 6334 PIN_BASED_VMX_PREEMPTION_TIMER); 6335 vmx->loaded_vmcs->hv_timer_armed = true; 6336 } 6337 6338 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6339 { 6340 struct vcpu_vmx *vmx = to_vmx(vcpu); 6341 u64 tscl; 6342 u32 delta_tsc; 6343 6344 if (vmx->req_immediate_exit) { 6345 vmx_arm_hv_timer(vmx, 0); 6346 return; 6347 } 6348 6349 if (vmx->hv_deadline_tsc != -1) { 6350 tscl = rdtsc(); 6351 if (vmx->hv_deadline_tsc > tscl) 6352 /* set_hv_timer ensures the delta fits in 32-bits */ 6353 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6354 cpu_preemption_timer_multi); 6355 else 6356 delta_tsc = 0; 6357 6358 vmx_arm_hv_timer(vmx, delta_tsc); 6359 return; 6360 } 6361 6362 if (vmx->loaded_vmcs->hv_timer_armed) 6363 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, 6364 PIN_BASED_VMX_PREEMPTION_TIMER); 6365 vmx->loaded_vmcs->hv_timer_armed = false; 6366 } 6367 6368 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6369 { 6370 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6371 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6372 vmcs_writel(HOST_RSP, host_rsp); 6373 } 6374 } 6375 6376 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6377 6378 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6379 { 6380 struct vcpu_vmx *vmx = to_vmx(vcpu); 6381 unsigned long cr3, cr4; 6382 6383 /* Record the guest's net vcpu time for enforced NMI injections. */ 6384 if (unlikely(!enable_vnmi && 6385 vmx->loaded_vmcs->soft_vnmi_blocked)) 6386 vmx->loaded_vmcs->entry_time = ktime_get(); 6387 6388 /* Don't enter VMX if guest state is invalid, let the exit handler 6389 start emulation until we arrive back to a valid state */ 6390 if (vmx->emulation_required) 6391 return; 6392 6393 if (vmx->ple_window_dirty) { 6394 vmx->ple_window_dirty = false; 6395 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6396 } 6397 6398 if (vmx->nested.need_vmcs12_sync) 6399 nested_sync_from_vmcs12(vcpu); 6400 6401 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) 6402 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6403 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) 6404 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6405 6406 cr3 = __get_current_cr3_fast(); 6407 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6408 vmcs_writel(HOST_CR3, cr3); 6409 vmx->loaded_vmcs->host_state.cr3 = cr3; 6410 } 6411 6412 cr4 = cr4_read_shadow(); 6413 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6414 vmcs_writel(HOST_CR4, cr4); 6415 vmx->loaded_vmcs->host_state.cr4 = cr4; 6416 } 6417 6418 /* When single-stepping over STI and MOV SS, we must clear the 6419 * corresponding interruptibility bits in the guest state. Otherwise 6420 * vmentry fails as it then expects bit 14 (BS) in pending debug 6421 * exceptions being set, but that's not correct for the guest debugging 6422 * case. */ 6423 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6424 vmx_set_interrupt_shadow(vcpu, 0); 6425 6426 if (static_cpu_has(X86_FEATURE_PKU) && 6427 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6428 vcpu->arch.pkru != vmx->host_pkru) 6429 __write_pkru(vcpu->arch.pkru); 6430 6431 pt_guest_enter(vmx); 6432 6433 atomic_switch_perf_msrs(vmx); 6434 6435 vmx_update_hv_timer(vcpu); 6436 6437 /* 6438 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6439 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6440 * is no need to worry about the conditional branch over the wrmsr 6441 * being speculatively taken. 6442 */ 6443 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6444 6445 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6446 vmx_l1d_flush(vcpu); 6447 6448 if (vcpu->arch.cr2 != read_cr2()) 6449 write_cr2(vcpu->arch.cr2); 6450 6451 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6452 vmx->loaded_vmcs->launched); 6453 6454 vcpu->arch.cr2 = read_cr2(); 6455 6456 /* 6457 * We do not use IBRS in the kernel. If this vCPU has used the 6458 * SPEC_CTRL MSR it may have left it on; save the value and 6459 * turn it off. This is much more efficient than blindly adding 6460 * it to the atomic save/restore list. Especially as the former 6461 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6462 * 6463 * For non-nested case: 6464 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6465 * save it. 6466 * 6467 * For nested case: 6468 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6469 * save it. 6470 */ 6471 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6472 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6473 6474 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6475 6476 /* Eliminate branch target predictions from guest mode */ 6477 vmexit_fill_RSB(); 6478 6479 /* All fields are clean at this point */ 6480 if (static_branch_unlikely(&enable_evmcs)) 6481 current_evmcs->hv_clean_fields |= 6482 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6483 6484 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6485 if (vmx->host_debugctlmsr) 6486 update_debugctlmsr(vmx->host_debugctlmsr); 6487 6488 #ifndef CONFIG_X86_64 6489 /* 6490 * The sysexit path does not restore ds/es, so we must set them to 6491 * a reasonable value ourselves. 6492 * 6493 * We can't defer this to vmx_prepare_switch_to_host() since that 6494 * function may be executed in interrupt context, which saves and 6495 * restore segments around it, nullifying its effect. 6496 */ 6497 loadsegment(ds, __USER_DS); 6498 loadsegment(es, __USER_DS); 6499 #endif 6500 6501 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6502 | (1 << VCPU_EXREG_RFLAGS) 6503 | (1 << VCPU_EXREG_PDPTR) 6504 | (1 << VCPU_EXREG_SEGMENTS) 6505 | (1 << VCPU_EXREG_CR3)); 6506 vcpu->arch.regs_dirty = 0; 6507 6508 pt_guest_exit(vmx); 6509 6510 /* 6511 * eager fpu is enabled if PKEY is supported and CR4 is switched 6512 * back on host, so it is safe to read guest PKRU from current 6513 * XSAVE. 6514 */ 6515 if (static_cpu_has(X86_FEATURE_PKU) && 6516 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6517 vcpu->arch.pkru = __read_pkru(); 6518 if (vcpu->arch.pkru != vmx->host_pkru) 6519 __write_pkru(vmx->host_pkru); 6520 } 6521 6522 vmx->nested.nested_run_pending = 0; 6523 vmx->idt_vectoring_info = 0; 6524 6525 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6526 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6527 return; 6528 6529 vmx->loaded_vmcs->launched = 1; 6530 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6531 6532 vmx_complete_atomic_exit(vmx); 6533 vmx_recover_nmi_blocking(vmx); 6534 vmx_complete_interrupts(vmx); 6535 } 6536 6537 static struct kvm *vmx_vm_alloc(void) 6538 { 6539 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6540 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6541 PAGE_KERNEL); 6542 return &kvm_vmx->kvm; 6543 } 6544 6545 static void vmx_vm_free(struct kvm *kvm) 6546 { 6547 vfree(to_kvm_vmx(kvm)); 6548 } 6549 6550 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6551 { 6552 struct vcpu_vmx *vmx = to_vmx(vcpu); 6553 6554 if (enable_pml) 6555 vmx_destroy_pml_buffer(vmx); 6556 free_vpid(vmx->vpid); 6557 nested_vmx_free_vcpu(vcpu); 6558 free_loaded_vmcs(vmx->loaded_vmcs); 6559 kfree(vmx->guest_msrs); 6560 kvm_vcpu_uninit(vcpu); 6561 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); 6562 kmem_cache_free(kvm_vcpu_cache, vmx); 6563 } 6564 6565 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) 6566 { 6567 int err; 6568 struct vcpu_vmx *vmx; 6569 unsigned long *msr_bitmap; 6570 int cpu; 6571 6572 vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL_ACCOUNT); 6573 if (!vmx) 6574 return ERR_PTR(-ENOMEM); 6575 6576 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 6577 GFP_KERNEL_ACCOUNT); 6578 if (!vmx->vcpu.arch.guest_fpu) { 6579 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); 6580 err = -ENOMEM; 6581 goto free_partial_vcpu; 6582 } 6583 6584 vmx->vpid = allocate_vpid(); 6585 6586 err = kvm_vcpu_init(&vmx->vcpu, kvm, id); 6587 if (err) 6588 goto free_vcpu; 6589 6590 err = -ENOMEM; 6591 6592 /* 6593 * If PML is turned on, failure on enabling PML just results in failure 6594 * of creating the vcpu, therefore we can simplify PML logic (by 6595 * avoiding dealing with cases, such as enabling PML partially on vcpus 6596 * for the guest, etc. 6597 */ 6598 if (enable_pml) { 6599 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6600 if (!vmx->pml_pg) 6601 goto uninit_vcpu; 6602 } 6603 6604 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT); 6605 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) 6606 > PAGE_SIZE); 6607 6608 if (!vmx->guest_msrs) 6609 goto free_pml; 6610 6611 err = alloc_loaded_vmcs(&vmx->vmcs01); 6612 if (err < 0) 6613 goto free_msrs; 6614 6615 msr_bitmap = vmx->vmcs01.msr_bitmap; 6616 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6617 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6618 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6619 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6620 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6621 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6622 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6623 vmx->msr_bitmap_mode = 0; 6624 6625 vmx->loaded_vmcs = &vmx->vmcs01; 6626 cpu = get_cpu(); 6627 vmx_vcpu_load(&vmx->vcpu, cpu); 6628 vmx->vcpu.cpu = cpu; 6629 vmx_vcpu_setup(vmx); 6630 vmx_vcpu_put(&vmx->vcpu); 6631 put_cpu(); 6632 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { 6633 err = alloc_apic_access_page(kvm); 6634 if (err) 6635 goto free_vmcs; 6636 } 6637 6638 if (enable_ept && !enable_unrestricted_guest) { 6639 err = init_rmode_identity_map(kvm); 6640 if (err) 6641 goto free_vmcs; 6642 } 6643 6644 if (nested) 6645 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6646 vmx_capability.ept, 6647 kvm_vcpu_apicv_active(&vmx->vcpu)); 6648 else 6649 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6650 6651 vmx->nested.posted_intr_nv = -1; 6652 vmx->nested.current_vmptr = -1ull; 6653 6654 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; 6655 6656 /* 6657 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6658 * or POSTED_INTR_WAKEUP_VECTOR. 6659 */ 6660 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6661 vmx->pi_desc.sn = 1; 6662 6663 vmx->ept_pointer = INVALID_PAGE; 6664 6665 return &vmx->vcpu; 6666 6667 free_vmcs: 6668 free_loaded_vmcs(vmx->loaded_vmcs); 6669 free_msrs: 6670 kfree(vmx->guest_msrs); 6671 free_pml: 6672 vmx_destroy_pml_buffer(vmx); 6673 uninit_vcpu: 6674 kvm_vcpu_uninit(&vmx->vcpu); 6675 free_vcpu: 6676 free_vpid(vmx->vpid); 6677 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); 6678 free_partial_vcpu: 6679 kmem_cache_free(kvm_vcpu_cache, vmx); 6680 return ERR_PTR(err); 6681 } 6682 6683 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n" 6684 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n" 6685 6686 static int vmx_vm_init(struct kvm *kvm) 6687 { 6688 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6689 6690 if (!ple_gap) 6691 kvm->arch.pause_in_guest = true; 6692 6693 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6694 switch (l1tf_mitigation) { 6695 case L1TF_MITIGATION_OFF: 6696 case L1TF_MITIGATION_FLUSH_NOWARN: 6697 /* 'I explicitly don't care' is set */ 6698 break; 6699 case L1TF_MITIGATION_FLUSH: 6700 case L1TF_MITIGATION_FLUSH_NOSMT: 6701 case L1TF_MITIGATION_FULL: 6702 /* 6703 * Warn upon starting the first VM in a potentially 6704 * insecure environment. 6705 */ 6706 if (sched_smt_active()) 6707 pr_warn_once(L1TF_MSG_SMT); 6708 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6709 pr_warn_once(L1TF_MSG_L1D); 6710 break; 6711 case L1TF_MITIGATION_FULL_FORCE: 6712 /* Flush is enforced */ 6713 break; 6714 } 6715 } 6716 return 0; 6717 } 6718 6719 static void __init vmx_check_processor_compat(void *rtn) 6720 { 6721 struct vmcs_config vmcs_conf; 6722 struct vmx_capability vmx_cap; 6723 6724 *(int *)rtn = 0; 6725 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6726 *(int *)rtn = -EIO; 6727 if (nested) 6728 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept, 6729 enable_apicv); 6730 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6731 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6732 smp_processor_id()); 6733 *(int *)rtn = -EIO; 6734 } 6735 } 6736 6737 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6738 { 6739 u8 cache; 6740 u64 ipat = 0; 6741 6742 /* For VT-d and EPT combination 6743 * 1. MMIO: always map as UC 6744 * 2. EPT with VT-d: 6745 * a. VT-d without snooping control feature: can't guarantee the 6746 * result, try to trust guest. 6747 * b. VT-d with snooping control feature: snooping control feature of 6748 * VT-d engine can guarantee the cache correctness. Just set it 6749 * to WB to keep consistent with host. So the same as item 3. 6750 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6751 * consistent with host MTRR 6752 */ 6753 if (is_mmio) { 6754 cache = MTRR_TYPE_UNCACHABLE; 6755 goto exit; 6756 } 6757 6758 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6759 ipat = VMX_EPT_IPAT_BIT; 6760 cache = MTRR_TYPE_WRBACK; 6761 goto exit; 6762 } 6763 6764 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6765 ipat = VMX_EPT_IPAT_BIT; 6766 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6767 cache = MTRR_TYPE_WRBACK; 6768 else 6769 cache = MTRR_TYPE_UNCACHABLE; 6770 goto exit; 6771 } 6772 6773 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6774 6775 exit: 6776 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6777 } 6778 6779 static int vmx_get_lpage_level(void) 6780 { 6781 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6782 return PT_DIRECTORY_LEVEL; 6783 else 6784 /* For shadow and EPT supported 1GB page */ 6785 return PT_PDPE_LEVEL; 6786 } 6787 6788 static void vmcs_set_secondary_exec_control(u32 new_ctl) 6789 { 6790 /* 6791 * These bits in the secondary execution controls field 6792 * are dynamic, the others are mostly based on the hypervisor 6793 * architecture and the guest's CPUID. Do not touch the 6794 * dynamic bits. 6795 */ 6796 u32 mask = 6797 SECONDARY_EXEC_SHADOW_VMCS | 6798 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6799 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6800 SECONDARY_EXEC_DESC; 6801 6802 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 6803 6804 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, 6805 (new_ctl & ~mask) | (cur_ctl & mask)); 6806 } 6807 6808 /* 6809 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6810 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6811 */ 6812 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6813 { 6814 struct vcpu_vmx *vmx = to_vmx(vcpu); 6815 struct kvm_cpuid_entry2 *entry; 6816 6817 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6818 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6819 6820 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6821 if (entry && (entry->_reg & (_cpuid_mask))) \ 6822 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6823 } while (0) 6824 6825 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6826 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); 6827 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); 6828 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); 6829 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); 6830 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); 6831 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); 6832 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); 6833 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); 6834 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); 6835 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); 6836 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); 6837 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); 6838 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); 6839 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); 6840 6841 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6842 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); 6843 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); 6844 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); 6845 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); 6846 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); 6847 6848 #undef cr4_fixed1_update 6849 } 6850 6851 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 6852 { 6853 struct vcpu_vmx *vmx = to_vmx(vcpu); 6854 6855 if (kvm_mpx_supported()) { 6856 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 6857 6858 if (mpx_enabled) { 6859 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 6860 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 6861 } else { 6862 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 6863 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 6864 } 6865 } 6866 } 6867 6868 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 6869 { 6870 struct vcpu_vmx *vmx = to_vmx(vcpu); 6871 struct kvm_cpuid_entry2 *best = NULL; 6872 int i; 6873 6874 for (i = 0; i < PT_CPUID_LEAVES; i++) { 6875 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 6876 if (!best) 6877 return; 6878 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 6879 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 6880 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 6881 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 6882 } 6883 6884 /* Get the number of configurable Address Ranges for filtering */ 6885 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 6886 PT_CAP_num_address_ranges); 6887 6888 /* Initialize and clear the no dependency bits */ 6889 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 6890 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 6891 6892 /* 6893 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 6894 * will inject an #GP 6895 */ 6896 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 6897 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 6898 6899 /* 6900 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 6901 * PSBFreq can be set 6902 */ 6903 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 6904 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 6905 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 6906 6907 /* 6908 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 6909 * MTCFreq can be set 6910 */ 6911 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 6912 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 6913 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 6914 6915 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 6916 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 6917 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 6918 RTIT_CTL_PTW_EN); 6919 6920 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 6921 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 6922 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 6923 6924 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 6925 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 6926 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 6927 6928 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 6929 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 6930 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 6931 6932 /* unmask address range configure area */ 6933 for (i = 0; i < vmx->pt_desc.addr_range; i++) 6934 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 6935 } 6936 6937 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 6938 { 6939 struct vcpu_vmx *vmx = to_vmx(vcpu); 6940 6941 if (cpu_has_secondary_exec_ctrls()) { 6942 vmx_compute_secondary_exec_control(vmx); 6943 vmcs_set_secondary_exec_control(vmx->secondary_exec_control); 6944 } 6945 6946 if (nested_vmx_allowed(vcpu)) 6947 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 6948 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 6949 else 6950 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 6951 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 6952 6953 if (nested_vmx_allowed(vcpu)) { 6954 nested_vmx_cr_fixed1_bits_update(vcpu); 6955 nested_vmx_entry_exit_ctls_update(vcpu); 6956 } 6957 6958 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 6959 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 6960 update_intel_pt_cfg(vcpu); 6961 } 6962 6963 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 6964 { 6965 if (func == 1 && nested) 6966 entry->ecx |= bit(X86_FEATURE_VMX); 6967 } 6968 6969 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 6970 { 6971 to_vmx(vcpu)->req_immediate_exit = true; 6972 } 6973 6974 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 6975 struct x86_instruction_info *info, 6976 enum x86_intercept_stage stage) 6977 { 6978 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6979 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6980 6981 /* 6982 * RDPID causes #UD if disabled through secondary execution controls. 6983 * Because it is marked as EmulateOnUD, we need to intercept it here. 6984 */ 6985 if (info->intercept == x86_intercept_rdtscp && 6986 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 6987 ctxt->exception.vector = UD_VECTOR; 6988 ctxt->exception.error_code_valid = false; 6989 return X86EMUL_PROPAGATE_FAULT; 6990 } 6991 6992 /* TODO: check more intercepts... */ 6993 return X86EMUL_CONTINUE; 6994 } 6995 6996 #ifdef CONFIG_X86_64 6997 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 6998 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 6999 u64 divisor, u64 *result) 7000 { 7001 u64 low = a << shift, high = a >> (64 - shift); 7002 7003 /* To avoid the overflow on divq */ 7004 if (high >= divisor) 7005 return 1; 7006 7007 /* Low hold the result, high hold rem which is discarded */ 7008 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7009 "rm" (divisor), "0" (low), "1" (high)); 7010 *result = low; 7011 7012 return 0; 7013 } 7014 7015 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) 7016 { 7017 struct vcpu_vmx *vmx; 7018 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7019 7020 if (kvm_mwait_in_guest(vcpu->kvm)) 7021 return -EOPNOTSUPP; 7022 7023 vmx = to_vmx(vcpu); 7024 tscl = rdtsc(); 7025 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7026 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7027 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns); 7028 7029 if (delta_tsc > lapic_timer_advance_cycles) 7030 delta_tsc -= lapic_timer_advance_cycles; 7031 else 7032 delta_tsc = 0; 7033 7034 /* Convert to host delta tsc if tsc scaling is enabled */ 7035 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7036 u64_shl_div_u64(delta_tsc, 7037 kvm_tsc_scaling_ratio_frac_bits, 7038 vcpu->arch.tsc_scaling_ratio, 7039 &delta_tsc)) 7040 return -ERANGE; 7041 7042 /* 7043 * If the delta tsc can't fit in the 32 bit after the multi shift, 7044 * we can't use the preemption timer. 7045 * It's possible that it fits on later vmentries, but checking 7046 * on every vmentry is costly so we just use an hrtimer. 7047 */ 7048 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7049 return -ERANGE; 7050 7051 vmx->hv_deadline_tsc = tscl + delta_tsc; 7052 return delta_tsc == 0; 7053 } 7054 7055 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7056 { 7057 to_vmx(vcpu)->hv_deadline_tsc = -1; 7058 } 7059 #endif 7060 7061 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7062 { 7063 if (!kvm_pause_in_guest(vcpu->kvm)) 7064 shrink_ple_window(vcpu); 7065 } 7066 7067 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7068 struct kvm_memory_slot *slot) 7069 { 7070 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7071 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7072 } 7073 7074 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7075 struct kvm_memory_slot *slot) 7076 { 7077 kvm_mmu_slot_set_dirty(kvm, slot); 7078 } 7079 7080 static void vmx_flush_log_dirty(struct kvm *kvm) 7081 { 7082 kvm_flush_pml_buffers(kvm); 7083 } 7084 7085 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7086 { 7087 struct vmcs12 *vmcs12; 7088 struct vcpu_vmx *vmx = to_vmx(vcpu); 7089 gpa_t gpa; 7090 struct page *page = NULL; 7091 u64 *pml_address; 7092 7093 if (is_guest_mode(vcpu)) { 7094 WARN_ON_ONCE(vmx->nested.pml_full); 7095 7096 /* 7097 * Check if PML is enabled for the nested guest. 7098 * Whether eptp bit 6 is set is already checked 7099 * as part of A/D emulation. 7100 */ 7101 vmcs12 = get_vmcs12(vcpu); 7102 if (!nested_cpu_has_pml(vmcs12)) 7103 return 0; 7104 7105 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7106 vmx->nested.pml_full = true; 7107 return 1; 7108 } 7109 7110 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7111 7112 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address); 7113 if (is_error_page(page)) 7114 return 0; 7115 7116 pml_address = kmap(page); 7117 pml_address[vmcs12->guest_pml_index--] = gpa; 7118 kunmap(page); 7119 kvm_release_page_clean(page); 7120 } 7121 7122 return 0; 7123 } 7124 7125 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7126 struct kvm_memory_slot *memslot, 7127 gfn_t offset, unsigned long mask) 7128 { 7129 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7130 } 7131 7132 static void __pi_post_block(struct kvm_vcpu *vcpu) 7133 { 7134 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7135 struct pi_desc old, new; 7136 unsigned int dest; 7137 7138 do { 7139 old.control = new.control = pi_desc->control; 7140 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7141 "Wakeup handler not enabled while the VCPU is blocked\n"); 7142 7143 dest = cpu_physical_id(vcpu->cpu); 7144 7145 if (x2apic_enabled()) 7146 new.ndst = dest; 7147 else 7148 new.ndst = (dest << 8) & 0xFF00; 7149 7150 /* set 'NV' to 'notification vector' */ 7151 new.nv = POSTED_INTR_VECTOR; 7152 } while (cmpxchg64(&pi_desc->control, old.control, 7153 new.control) != old.control); 7154 7155 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7156 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7157 list_del(&vcpu->blocked_vcpu_list); 7158 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7159 vcpu->pre_pcpu = -1; 7160 } 7161 } 7162 7163 /* 7164 * This routine does the following things for vCPU which is going 7165 * to be blocked if VT-d PI is enabled. 7166 * - Store the vCPU to the wakeup list, so when interrupts happen 7167 * we can find the right vCPU to wake up. 7168 * - Change the Posted-interrupt descriptor as below: 7169 * 'NDST' <-- vcpu->pre_pcpu 7170 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7171 * - If 'ON' is set during this process, which means at least one 7172 * interrupt is posted for this vCPU, we cannot block it, in 7173 * this case, return 1, otherwise, return 0. 7174 * 7175 */ 7176 static int pi_pre_block(struct kvm_vcpu *vcpu) 7177 { 7178 unsigned int dest; 7179 struct pi_desc old, new; 7180 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7181 7182 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7183 !irq_remapping_cap(IRQ_POSTING_CAP) || 7184 !kvm_vcpu_apicv_active(vcpu)) 7185 return 0; 7186 7187 WARN_ON(irqs_disabled()); 7188 local_irq_disable(); 7189 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7190 vcpu->pre_pcpu = vcpu->cpu; 7191 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7192 list_add_tail(&vcpu->blocked_vcpu_list, 7193 &per_cpu(blocked_vcpu_on_cpu, 7194 vcpu->pre_pcpu)); 7195 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7196 } 7197 7198 do { 7199 old.control = new.control = pi_desc->control; 7200 7201 WARN((pi_desc->sn == 1), 7202 "Warning: SN field of posted-interrupts " 7203 "is set before blocking\n"); 7204 7205 /* 7206 * Since vCPU can be preempted during this process, 7207 * vcpu->cpu could be different with pre_pcpu, we 7208 * need to set pre_pcpu as the destination of wakeup 7209 * notification event, then we can find the right vCPU 7210 * to wakeup in wakeup handler if interrupts happen 7211 * when the vCPU is in blocked state. 7212 */ 7213 dest = cpu_physical_id(vcpu->pre_pcpu); 7214 7215 if (x2apic_enabled()) 7216 new.ndst = dest; 7217 else 7218 new.ndst = (dest << 8) & 0xFF00; 7219 7220 /* set 'NV' to 'wakeup vector' */ 7221 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7222 } while (cmpxchg64(&pi_desc->control, old.control, 7223 new.control) != old.control); 7224 7225 /* We should not block the vCPU if an interrupt is posted for it. */ 7226 if (pi_test_on(pi_desc) == 1) 7227 __pi_post_block(vcpu); 7228 7229 local_irq_enable(); 7230 return (vcpu->pre_pcpu == -1); 7231 } 7232 7233 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7234 { 7235 if (pi_pre_block(vcpu)) 7236 return 1; 7237 7238 if (kvm_lapic_hv_timer_in_use(vcpu)) 7239 kvm_lapic_switch_to_sw_timer(vcpu); 7240 7241 return 0; 7242 } 7243 7244 static void pi_post_block(struct kvm_vcpu *vcpu) 7245 { 7246 if (vcpu->pre_pcpu == -1) 7247 return; 7248 7249 WARN_ON(irqs_disabled()); 7250 local_irq_disable(); 7251 __pi_post_block(vcpu); 7252 local_irq_enable(); 7253 } 7254 7255 static void vmx_post_block(struct kvm_vcpu *vcpu) 7256 { 7257 if (kvm_x86_ops->set_hv_timer) 7258 kvm_lapic_switch_to_hv_timer(vcpu); 7259 7260 pi_post_block(vcpu); 7261 } 7262 7263 /* 7264 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7265 * 7266 * @kvm: kvm 7267 * @host_irq: host irq of the interrupt 7268 * @guest_irq: gsi of the interrupt 7269 * @set: set or unset PI 7270 * returns 0 on success, < 0 on failure 7271 */ 7272 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7273 uint32_t guest_irq, bool set) 7274 { 7275 struct kvm_kernel_irq_routing_entry *e; 7276 struct kvm_irq_routing_table *irq_rt; 7277 struct kvm_lapic_irq irq; 7278 struct kvm_vcpu *vcpu; 7279 struct vcpu_data vcpu_info; 7280 int idx, ret = 0; 7281 7282 if (!kvm_arch_has_assigned_device(kvm) || 7283 !irq_remapping_cap(IRQ_POSTING_CAP) || 7284 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7285 return 0; 7286 7287 idx = srcu_read_lock(&kvm->irq_srcu); 7288 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7289 if (guest_irq >= irq_rt->nr_rt_entries || 7290 hlist_empty(&irq_rt->map[guest_irq])) { 7291 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7292 guest_irq, irq_rt->nr_rt_entries); 7293 goto out; 7294 } 7295 7296 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7297 if (e->type != KVM_IRQ_ROUTING_MSI) 7298 continue; 7299 /* 7300 * VT-d PI cannot support posting multicast/broadcast 7301 * interrupts to a vCPU, we still use interrupt remapping 7302 * for these kind of interrupts. 7303 * 7304 * For lowest-priority interrupts, we only support 7305 * those with single CPU as the destination, e.g. user 7306 * configures the interrupts via /proc/irq or uses 7307 * irqbalance to make the interrupts single-CPU. 7308 * 7309 * We will support full lowest-priority interrupt later. 7310 */ 7311 7312 kvm_set_msi_irq(kvm, e, &irq); 7313 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { 7314 /* 7315 * Make sure the IRTE is in remapped mode if 7316 * we don't handle it in posted mode. 7317 */ 7318 ret = irq_set_vcpu_affinity(host_irq, NULL); 7319 if (ret < 0) { 7320 printk(KERN_INFO 7321 "failed to back to remapped mode, irq: %u\n", 7322 host_irq); 7323 goto out; 7324 } 7325 7326 continue; 7327 } 7328 7329 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7330 vcpu_info.vector = irq.vector; 7331 7332 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7333 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7334 7335 if (set) 7336 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7337 else 7338 ret = irq_set_vcpu_affinity(host_irq, NULL); 7339 7340 if (ret < 0) { 7341 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7342 __func__); 7343 goto out; 7344 } 7345 } 7346 7347 ret = 0; 7348 out: 7349 srcu_read_unlock(&kvm->irq_srcu, idx); 7350 return ret; 7351 } 7352 7353 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7354 { 7355 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7356 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7357 FEATURE_CONTROL_LMCE; 7358 else 7359 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7360 ~FEATURE_CONTROL_LMCE; 7361 } 7362 7363 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7364 { 7365 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7366 if (to_vmx(vcpu)->nested.nested_run_pending) 7367 return 0; 7368 return 1; 7369 } 7370 7371 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7372 { 7373 struct vcpu_vmx *vmx = to_vmx(vcpu); 7374 7375 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7376 if (vmx->nested.smm.guest_mode) 7377 nested_vmx_vmexit(vcpu, -1, 0, 0); 7378 7379 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7380 vmx->nested.vmxon = false; 7381 vmx_clear_hlt(vcpu); 7382 return 0; 7383 } 7384 7385 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) 7386 { 7387 struct vcpu_vmx *vmx = to_vmx(vcpu); 7388 int ret; 7389 7390 if (vmx->nested.smm.vmxon) { 7391 vmx->nested.vmxon = true; 7392 vmx->nested.smm.vmxon = false; 7393 } 7394 7395 if (vmx->nested.smm.guest_mode) { 7396 vcpu->arch.hflags &= ~HF_SMM_MASK; 7397 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7398 vcpu->arch.hflags |= HF_SMM_MASK; 7399 if (ret) 7400 return ret; 7401 7402 vmx->nested.smm.guest_mode = false; 7403 } 7404 return 0; 7405 } 7406 7407 static int enable_smi_window(struct kvm_vcpu *vcpu) 7408 { 7409 return 0; 7410 } 7411 7412 static __init int hardware_setup(void) 7413 { 7414 unsigned long host_bndcfgs; 7415 int r, i; 7416 7417 rdmsrl_safe(MSR_EFER, &host_efer); 7418 7419 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7420 kvm_define_shared_msr(i, vmx_msr_index[i]); 7421 7422 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7423 return -EIO; 7424 7425 if (boot_cpu_has(X86_FEATURE_NX)) 7426 kvm_enable_efer_bits(EFER_NX); 7427 7428 if (boot_cpu_has(X86_FEATURE_MPX)) { 7429 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7430 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7431 } 7432 7433 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7434 rdmsrl(MSR_IA32_XSS, host_xss); 7435 7436 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7437 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7438 enable_vpid = 0; 7439 7440 if (!cpu_has_vmx_ept() || 7441 !cpu_has_vmx_ept_4levels() || 7442 !cpu_has_vmx_ept_mt_wb() || 7443 !cpu_has_vmx_invept_global()) 7444 enable_ept = 0; 7445 7446 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7447 enable_ept_ad_bits = 0; 7448 7449 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7450 enable_unrestricted_guest = 0; 7451 7452 if (!cpu_has_vmx_flexpriority()) 7453 flexpriority_enabled = 0; 7454 7455 if (!cpu_has_virtual_nmis()) 7456 enable_vnmi = 0; 7457 7458 /* 7459 * set_apic_access_page_addr() is used to reload apic access 7460 * page upon invalidation. No need to do anything if not 7461 * using the APIC_ACCESS_ADDR VMCS field. 7462 */ 7463 if (!flexpriority_enabled) 7464 kvm_x86_ops->set_apic_access_page_addr = NULL; 7465 7466 if (!cpu_has_vmx_tpr_shadow()) 7467 kvm_x86_ops->update_cr8_intercept = NULL; 7468 7469 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7470 kvm_disable_largepages(); 7471 7472 #if IS_ENABLED(CONFIG_HYPERV) 7473 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7474 && enable_ept) { 7475 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7476 kvm_x86_ops->tlb_remote_flush_with_range = 7477 hv_remote_flush_tlb_with_range; 7478 } 7479 #endif 7480 7481 if (!cpu_has_vmx_ple()) { 7482 ple_gap = 0; 7483 ple_window = 0; 7484 ple_window_grow = 0; 7485 ple_window_max = 0; 7486 ple_window_shrink = 0; 7487 } 7488 7489 if (!cpu_has_vmx_apicv()) { 7490 enable_apicv = 0; 7491 kvm_x86_ops->sync_pir_to_irr = NULL; 7492 } 7493 7494 if (cpu_has_vmx_tsc_scaling()) { 7495 kvm_has_tsc_control = true; 7496 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7497 kvm_tsc_scaling_ratio_frac_bits = 48; 7498 } 7499 7500 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7501 7502 if (enable_ept) 7503 vmx_enable_tdp(); 7504 else 7505 kvm_disable_tdp(); 7506 7507 /* 7508 * Only enable PML when hardware supports PML feature, and both EPT 7509 * and EPT A/D bit features are enabled -- PML depends on them to work. 7510 */ 7511 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7512 enable_pml = 0; 7513 7514 if (!enable_pml) { 7515 kvm_x86_ops->slot_enable_log_dirty = NULL; 7516 kvm_x86_ops->slot_disable_log_dirty = NULL; 7517 kvm_x86_ops->flush_log_dirty = NULL; 7518 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7519 } 7520 7521 if (!cpu_has_vmx_preemption_timer()) 7522 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7523 7524 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { 7525 u64 vmx_msr; 7526 7527 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7528 cpu_preemption_timer_multi = 7529 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7530 } else { 7531 kvm_x86_ops->set_hv_timer = NULL; 7532 kvm_x86_ops->cancel_hv_timer = NULL; 7533 } 7534 7535 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7536 7537 kvm_mce_cap_supported |= MCG_LMCE_P; 7538 7539 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7540 return -EINVAL; 7541 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7542 pt_mode = PT_MODE_SYSTEM; 7543 7544 if (nested) { 7545 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7546 vmx_capability.ept, enable_apicv); 7547 7548 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7549 if (r) 7550 return r; 7551 } 7552 7553 r = alloc_kvm_area(); 7554 if (r) 7555 nested_vmx_hardware_unsetup(); 7556 return r; 7557 } 7558 7559 static __exit void hardware_unsetup(void) 7560 { 7561 if (nested) 7562 nested_vmx_hardware_unsetup(); 7563 7564 free_kvm_area(); 7565 } 7566 7567 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7568 .cpu_has_kvm_support = cpu_has_kvm_support, 7569 .disabled_by_bios = vmx_disabled_by_bios, 7570 .hardware_setup = hardware_setup, 7571 .hardware_unsetup = hardware_unsetup, 7572 .check_processor_compatibility = vmx_check_processor_compat, 7573 .hardware_enable = hardware_enable, 7574 .hardware_disable = hardware_disable, 7575 .cpu_has_accelerated_tpr = report_flexpriority, 7576 .has_emulated_msr = vmx_has_emulated_msr, 7577 7578 .vm_init = vmx_vm_init, 7579 .vm_alloc = vmx_vm_alloc, 7580 .vm_free = vmx_vm_free, 7581 7582 .vcpu_create = vmx_create_vcpu, 7583 .vcpu_free = vmx_free_vcpu, 7584 .vcpu_reset = vmx_vcpu_reset, 7585 7586 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7587 .vcpu_load = vmx_vcpu_load, 7588 .vcpu_put = vmx_vcpu_put, 7589 7590 .update_bp_intercept = update_exception_bitmap, 7591 .get_msr_feature = vmx_get_msr_feature, 7592 .get_msr = vmx_get_msr, 7593 .set_msr = vmx_set_msr, 7594 .get_segment_base = vmx_get_segment_base, 7595 .get_segment = vmx_get_segment, 7596 .set_segment = vmx_set_segment, 7597 .get_cpl = vmx_get_cpl, 7598 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7599 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7600 .decache_cr3 = vmx_decache_cr3, 7601 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7602 .set_cr0 = vmx_set_cr0, 7603 .set_cr3 = vmx_set_cr3, 7604 .set_cr4 = vmx_set_cr4, 7605 .set_efer = vmx_set_efer, 7606 .get_idt = vmx_get_idt, 7607 .set_idt = vmx_set_idt, 7608 .get_gdt = vmx_get_gdt, 7609 .set_gdt = vmx_set_gdt, 7610 .get_dr6 = vmx_get_dr6, 7611 .set_dr6 = vmx_set_dr6, 7612 .set_dr7 = vmx_set_dr7, 7613 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7614 .cache_reg = vmx_cache_reg, 7615 .get_rflags = vmx_get_rflags, 7616 .set_rflags = vmx_set_rflags, 7617 7618 .tlb_flush = vmx_flush_tlb, 7619 .tlb_flush_gva = vmx_flush_tlb_gva, 7620 7621 .run = vmx_vcpu_run, 7622 .handle_exit = vmx_handle_exit, 7623 .skip_emulated_instruction = skip_emulated_instruction, 7624 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7625 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7626 .patch_hypercall = vmx_patch_hypercall, 7627 .set_irq = vmx_inject_irq, 7628 .set_nmi = vmx_inject_nmi, 7629 .queue_exception = vmx_queue_exception, 7630 .cancel_injection = vmx_cancel_injection, 7631 .interrupt_allowed = vmx_interrupt_allowed, 7632 .nmi_allowed = vmx_nmi_allowed, 7633 .get_nmi_mask = vmx_get_nmi_mask, 7634 .set_nmi_mask = vmx_set_nmi_mask, 7635 .enable_nmi_window = enable_nmi_window, 7636 .enable_irq_window = enable_irq_window, 7637 .update_cr8_intercept = update_cr8_intercept, 7638 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7639 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7640 .get_enable_apicv = vmx_get_enable_apicv, 7641 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7642 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7643 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7644 .hwapic_irr_update = vmx_hwapic_irr_update, 7645 .hwapic_isr_update = vmx_hwapic_isr_update, 7646 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7647 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7648 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7649 7650 .set_tss_addr = vmx_set_tss_addr, 7651 .set_identity_map_addr = vmx_set_identity_map_addr, 7652 .get_tdp_level = get_ept_level, 7653 .get_mt_mask = vmx_get_mt_mask, 7654 7655 .get_exit_info = vmx_get_exit_info, 7656 7657 .get_lpage_level = vmx_get_lpage_level, 7658 7659 .cpuid_update = vmx_cpuid_update, 7660 7661 .rdtscp_supported = vmx_rdtscp_supported, 7662 .invpcid_supported = vmx_invpcid_supported, 7663 7664 .set_supported_cpuid = vmx_set_supported_cpuid, 7665 7666 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7667 7668 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7669 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7670 7671 .set_tdp_cr3 = vmx_set_cr3, 7672 7673 .check_intercept = vmx_check_intercept, 7674 .handle_external_intr = vmx_handle_external_intr, 7675 .mpx_supported = vmx_mpx_supported, 7676 .xsaves_supported = vmx_xsaves_supported, 7677 .umip_emulated = vmx_umip_emulated, 7678 .pt_supported = vmx_pt_supported, 7679 7680 .request_immediate_exit = vmx_request_immediate_exit, 7681 7682 .sched_in = vmx_sched_in, 7683 7684 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7685 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7686 .flush_log_dirty = vmx_flush_log_dirty, 7687 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7688 .write_log_dirty = vmx_write_pml_buffer, 7689 7690 .pre_block = vmx_pre_block, 7691 .post_block = vmx_post_block, 7692 7693 .pmu_ops = &intel_pmu_ops, 7694 7695 .update_pi_irte = vmx_update_pi_irte, 7696 7697 #ifdef CONFIG_X86_64 7698 .set_hv_timer = vmx_set_hv_timer, 7699 .cancel_hv_timer = vmx_cancel_hv_timer, 7700 #endif 7701 7702 .setup_mce = vmx_setup_mce, 7703 7704 .smi_allowed = vmx_smi_allowed, 7705 .pre_enter_smm = vmx_pre_enter_smm, 7706 .pre_leave_smm = vmx_pre_leave_smm, 7707 .enable_smi_window = enable_smi_window, 7708 7709 .check_nested_events = NULL, 7710 .get_nested_state = NULL, 7711 .set_nested_state = NULL, 7712 .get_vmcs12_pages = NULL, 7713 .nested_enable_evmcs = NULL, 7714 }; 7715 7716 static void vmx_cleanup_l1d_flush(void) 7717 { 7718 if (vmx_l1d_flush_pages) { 7719 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7720 vmx_l1d_flush_pages = NULL; 7721 } 7722 /* Restore state so sysfs ignores VMX */ 7723 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 7724 } 7725 7726 static void vmx_exit(void) 7727 { 7728 #ifdef CONFIG_KEXEC_CORE 7729 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 7730 synchronize_rcu(); 7731 #endif 7732 7733 kvm_exit(); 7734 7735 #if IS_ENABLED(CONFIG_HYPERV) 7736 if (static_branch_unlikely(&enable_evmcs)) { 7737 int cpu; 7738 struct hv_vp_assist_page *vp_ap; 7739 /* 7740 * Reset everything to support using non-enlightened VMCS 7741 * access later (e.g. when we reload the module with 7742 * enlightened_vmcs=0) 7743 */ 7744 for_each_online_cpu(cpu) { 7745 vp_ap = hv_get_vp_assist_page(cpu); 7746 7747 if (!vp_ap) 7748 continue; 7749 7750 vp_ap->current_nested_vmcs = 0; 7751 vp_ap->enlighten_vmentry = 0; 7752 } 7753 7754 static_branch_disable(&enable_evmcs); 7755 } 7756 #endif 7757 vmx_cleanup_l1d_flush(); 7758 } 7759 module_exit(vmx_exit); 7760 7761 static int __init vmx_init(void) 7762 { 7763 int r; 7764 7765 #if IS_ENABLED(CONFIG_HYPERV) 7766 /* 7767 * Enlightened VMCS usage should be recommended and the host needs 7768 * to support eVMCS v1 or above. We can also disable eVMCS support 7769 * with module parameter. 7770 */ 7771 if (enlightened_vmcs && 7772 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 7773 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 7774 KVM_EVMCS_VERSION) { 7775 int cpu; 7776 7777 /* Check that we have assist pages on all online CPUs */ 7778 for_each_online_cpu(cpu) { 7779 if (!hv_get_vp_assist_page(cpu)) { 7780 enlightened_vmcs = false; 7781 break; 7782 } 7783 } 7784 7785 if (enlightened_vmcs) { 7786 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 7787 static_branch_enable(&enable_evmcs); 7788 } 7789 } else { 7790 enlightened_vmcs = false; 7791 } 7792 #endif 7793 7794 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 7795 __alignof__(struct vcpu_vmx), THIS_MODULE); 7796 if (r) 7797 return r; 7798 7799 /* 7800 * Must be called after kvm_init() so enable_ept is properly set 7801 * up. Hand the parameter mitigation value in which was stored in 7802 * the pre module init parser. If no parameter was given, it will 7803 * contain 'auto' which will be turned into the default 'cond' 7804 * mitigation mode. 7805 */ 7806 if (boot_cpu_has(X86_BUG_L1TF)) { 7807 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 7808 if (r) { 7809 vmx_exit(); 7810 return r; 7811 } 7812 } 7813 7814 #ifdef CONFIG_KEXEC_CORE 7815 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 7816 crash_vmclear_local_loaded_vmcss); 7817 #endif 7818 vmx_check_vmcs12_offsets(); 7819 7820 return 0; 7821 } 7822 module_init(vmx_init); 7823