1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_VMCS_H 3 #define __KVM_X86_VMX_VMCS_H 4 5 #include <linux/ktime.h> 6 #include <linux/list.h> 7 #include <linux/nospec.h> 8 9 #include <asm/kvm.h> 10 #include <asm/vmx.h> 11 12 #include "capabilities.h" 13 14 struct vmcs_hdr { 15 u32 revision_id:31; 16 u32 shadow_vmcs:1; 17 }; 18 19 struct vmcs { 20 struct vmcs_hdr hdr; 21 u32 abort; 22 char data[0]; 23 }; 24 25 DECLARE_PER_CPU(struct vmcs *, current_vmcs); 26 27 /* 28 * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT 29 * and whose values change infrequently, but are not constant. I.e. this is 30 * used as a write-through cache of the corresponding VMCS fields. 31 */ 32 struct vmcs_host_state { 33 unsigned long cr3; /* May not match real cr3 */ 34 unsigned long cr4; /* May not match real cr4 */ 35 unsigned long gs_base; 36 unsigned long fs_base; 37 unsigned long rsp; 38 39 u16 fs_sel, gs_sel, ldt_sel; 40 #ifdef CONFIG_X86_64 41 u16 ds_sel, es_sel; 42 #endif 43 }; 44 45 /* 46 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also 47 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs 48 * loaded on this CPU (so we can clear them if the CPU goes down). 49 */ 50 struct loaded_vmcs { 51 struct vmcs *vmcs; 52 struct vmcs *shadow_vmcs; 53 int cpu; 54 bool launched; 55 bool nmi_known_unmasked; 56 bool hv_timer_armed; 57 /* Support for vnmi-less CPUs */ 58 int soft_vnmi_blocked; 59 ktime_t entry_time; 60 s64 vnmi_blocked_time; 61 unsigned long *msr_bitmap; 62 struct list_head loaded_vmcss_on_cpu_link; 63 struct vmcs_host_state host_state; 64 }; 65 66 static inline bool is_exception_n(u32 intr_info, u8 vector) 67 { 68 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | 69 INTR_INFO_VALID_MASK)) == 70 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); 71 } 72 73 static inline bool is_debug(u32 intr_info) 74 { 75 return is_exception_n(intr_info, DB_VECTOR); 76 } 77 78 static inline bool is_breakpoint(u32 intr_info) 79 { 80 return is_exception_n(intr_info, BP_VECTOR); 81 } 82 83 static inline bool is_page_fault(u32 intr_info) 84 { 85 return is_exception_n(intr_info, PF_VECTOR); 86 } 87 88 static inline bool is_invalid_opcode(u32 intr_info) 89 { 90 return is_exception_n(intr_info, UD_VECTOR); 91 } 92 93 static inline bool is_gp_fault(u32 intr_info) 94 { 95 return is_exception_n(intr_info, GP_VECTOR); 96 } 97 98 static inline bool is_machine_check(u32 intr_info) 99 { 100 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | 101 INTR_INFO_VALID_MASK)) == 102 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); 103 } 104 105 /* Undocumented: icebp/int1 */ 106 static inline bool is_icebp(u32 intr_info) 107 { 108 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) 109 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK); 110 } 111 112 static inline bool is_nmi(u32 intr_info) 113 { 114 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) 115 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK); 116 } 117 118 enum vmcs_field_width { 119 VMCS_FIELD_WIDTH_U16 = 0, 120 VMCS_FIELD_WIDTH_U64 = 1, 121 VMCS_FIELD_WIDTH_U32 = 2, 122 VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3 123 }; 124 125 static inline int vmcs_field_width(unsigned long field) 126 { 127 if (0x1 & field) /* the *_HIGH fields are all 32 bit */ 128 return VMCS_FIELD_WIDTH_U32; 129 return (field >> 13) & 0x3; 130 } 131 132 static inline int vmcs_field_readonly(unsigned long field) 133 { 134 return (((field >> 10) & 0x3) == 1); 135 } 136 137 #endif /* __KVM_X86_VMX_VMCS_H */ 138