xref: /openbmc/linux/arch/x86/kvm/vmx/vmcs.h (revision d0e22329)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_VMCS_H
3 #define __KVM_X86_VMX_VMCS_H
4 
5 #include <linux/ktime.h>
6 #include <linux/list.h>
7 #include <linux/nospec.h>
8 
9 #include <asm/kvm.h>
10 #include <asm/vmx.h>
11 
12 #include "capabilities.h"
13 
14 struct vmcs_hdr {
15 	u32 revision_id:31;
16 	u32 shadow_vmcs:1;
17 };
18 
19 struct vmcs {
20 	struct vmcs_hdr hdr;
21 	u32 abort;
22 	char data[0];
23 };
24 
25 DECLARE_PER_CPU(struct vmcs *, current_vmcs);
26 
27 /*
28  * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
29  * and whose values change infrequently, but are not constant.  I.e. this is
30  * used as a write-through cache of the corresponding VMCS fields.
31  */
32 struct vmcs_host_state {
33 	unsigned long cr3;	/* May not match real cr3 */
34 	unsigned long cr4;	/* May not match real cr4 */
35 	unsigned long gs_base;
36 	unsigned long fs_base;
37 
38 	u16           fs_sel, gs_sel, ldt_sel;
39 #ifdef CONFIG_X86_64
40 	u16           ds_sel, es_sel;
41 #endif
42 };
43 
44 /*
45  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
46  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
47  * loaded on this CPU (so we can clear them if the CPU goes down).
48  */
49 struct loaded_vmcs {
50 	struct vmcs *vmcs;
51 	struct vmcs *shadow_vmcs;
52 	int cpu;
53 	bool launched;
54 	bool nmi_known_unmasked;
55 	bool hv_timer_armed;
56 	/* Support for vnmi-less CPUs */
57 	int soft_vnmi_blocked;
58 	ktime_t entry_time;
59 	s64 vnmi_blocked_time;
60 	unsigned long *msr_bitmap;
61 	struct list_head loaded_vmcss_on_cpu_link;
62 	struct vmcs_host_state host_state;
63 };
64 
65 static inline bool is_exception_n(u32 intr_info, u8 vector)
66 {
67 	return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
68 			     INTR_INFO_VALID_MASK)) ==
69 		(INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
70 }
71 
72 static inline bool is_debug(u32 intr_info)
73 {
74 	return is_exception_n(intr_info, DB_VECTOR);
75 }
76 
77 static inline bool is_breakpoint(u32 intr_info)
78 {
79 	return is_exception_n(intr_info, BP_VECTOR);
80 }
81 
82 static inline bool is_page_fault(u32 intr_info)
83 {
84 	return is_exception_n(intr_info, PF_VECTOR);
85 }
86 
87 static inline bool is_invalid_opcode(u32 intr_info)
88 {
89 	return is_exception_n(intr_info, UD_VECTOR);
90 }
91 
92 static inline bool is_gp_fault(u32 intr_info)
93 {
94 	return is_exception_n(intr_info, GP_VECTOR);
95 }
96 
97 static inline bool is_machine_check(u32 intr_info)
98 {
99 	return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
100 			     INTR_INFO_VALID_MASK)) ==
101 		(INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
102 }
103 
104 /* Undocumented: icebp/int1 */
105 static inline bool is_icebp(u32 intr_info)
106 {
107 	return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
108 		== (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
109 }
110 
111 static inline bool is_nmi(u32 intr_info)
112 {
113 	return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
114 		== (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
115 }
116 
117 enum vmcs_field_width {
118 	VMCS_FIELD_WIDTH_U16 = 0,
119 	VMCS_FIELD_WIDTH_U64 = 1,
120 	VMCS_FIELD_WIDTH_U32 = 2,
121 	VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
122 };
123 
124 static inline int vmcs_field_width(unsigned long field)
125 {
126 	if (0x1 & field)	/* the *_HIGH fields are all 32 bit */
127 		return VMCS_FIELD_WIDTH_U32;
128 	return (field >> 13) & 0x3;
129 }
130 
131 static inline int vmcs_field_readonly(unsigned long field)
132 {
133 	return (((field >> 10) & 0x3) == 1);
134 }
135 
136 #endif /* __KVM_X86_VMX_VMCS_H */
137