1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_VMCS_H 3 #define __KVM_X86_VMX_VMCS_H 4 5 #include <linux/ktime.h> 6 #include <linux/list.h> 7 #include <linux/nospec.h> 8 9 #include <asm/kvm.h> 10 #include <asm/vmx.h> 11 12 #include "capabilities.h" 13 14 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n))))) 15 16 struct vmcs_hdr { 17 u32 revision_id:31; 18 u32 shadow_vmcs:1; 19 }; 20 21 struct vmcs { 22 struct vmcs_hdr hdr; 23 u32 abort; 24 char data[]; 25 }; 26 27 DECLARE_PER_CPU(struct vmcs *, current_vmcs); 28 29 /* 30 * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT 31 * and whose values change infrequently, but are not constant. I.e. this is 32 * used as a write-through cache of the corresponding VMCS fields. 33 */ 34 struct vmcs_host_state { 35 unsigned long cr3; /* May not match real cr3 */ 36 unsigned long cr4; /* May not match real cr4 */ 37 unsigned long gs_base; 38 unsigned long fs_base; 39 unsigned long rsp; 40 41 u16 fs_sel, gs_sel, ldt_sel; 42 #ifdef CONFIG_X86_64 43 u16 ds_sel, es_sel; 44 #endif 45 }; 46 47 struct vmcs_controls_shadow { 48 u32 vm_entry; 49 u32 vm_exit; 50 u32 pin; 51 u32 exec; 52 u32 secondary_exec; 53 u64 tertiary_exec; 54 }; 55 56 /* 57 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also 58 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs 59 * loaded on this CPU (so we can clear them if the CPU goes down). 60 */ 61 struct loaded_vmcs { 62 struct vmcs *vmcs; 63 struct vmcs *shadow_vmcs; 64 int cpu; 65 bool launched; 66 bool nmi_known_unmasked; 67 bool hv_timer_soft_disabled; 68 /* Support for vnmi-less CPUs */ 69 int soft_vnmi_blocked; 70 ktime_t entry_time; 71 s64 vnmi_blocked_time; 72 unsigned long *msr_bitmap; 73 struct list_head loaded_vmcss_on_cpu_link; 74 struct vmcs_host_state host_state; 75 struct vmcs_controls_shadow controls_shadow; 76 }; 77 78 static inline bool is_intr_type(u32 intr_info, u32 type) 79 { 80 const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK; 81 82 return (intr_info & mask) == (INTR_INFO_VALID_MASK | type); 83 } 84 85 static inline bool is_intr_type_n(u32 intr_info, u32 type, u8 vector) 86 { 87 const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK | 88 INTR_INFO_VECTOR_MASK; 89 90 return (intr_info & mask) == (INTR_INFO_VALID_MASK | type | vector); 91 } 92 93 static inline bool is_exception_n(u32 intr_info, u8 vector) 94 { 95 return is_intr_type_n(intr_info, INTR_TYPE_HARD_EXCEPTION, vector); 96 } 97 98 static inline bool is_debug(u32 intr_info) 99 { 100 return is_exception_n(intr_info, DB_VECTOR); 101 } 102 103 static inline bool is_breakpoint(u32 intr_info) 104 { 105 return is_exception_n(intr_info, BP_VECTOR); 106 } 107 108 static inline bool is_double_fault(u32 intr_info) 109 { 110 return is_exception_n(intr_info, DF_VECTOR); 111 } 112 113 static inline bool is_page_fault(u32 intr_info) 114 { 115 return is_exception_n(intr_info, PF_VECTOR); 116 } 117 118 static inline bool is_invalid_opcode(u32 intr_info) 119 { 120 return is_exception_n(intr_info, UD_VECTOR); 121 } 122 123 static inline bool is_gp_fault(u32 intr_info) 124 { 125 return is_exception_n(intr_info, GP_VECTOR); 126 } 127 128 static inline bool is_alignment_check(u32 intr_info) 129 { 130 return is_exception_n(intr_info, AC_VECTOR); 131 } 132 133 static inline bool is_machine_check(u32 intr_info) 134 { 135 return is_exception_n(intr_info, MC_VECTOR); 136 } 137 138 static inline bool is_nm_fault(u32 intr_info) 139 { 140 return is_exception_n(intr_info, NM_VECTOR); 141 } 142 143 /* Undocumented: icebp/int1 */ 144 static inline bool is_icebp(u32 intr_info) 145 { 146 return is_intr_type(intr_info, INTR_TYPE_PRIV_SW_EXCEPTION); 147 } 148 149 static inline bool is_nmi(u32 intr_info) 150 { 151 return is_intr_type(intr_info, INTR_TYPE_NMI_INTR); 152 } 153 154 static inline bool is_external_intr(u32 intr_info) 155 { 156 return is_intr_type(intr_info, INTR_TYPE_EXT_INTR); 157 } 158 159 static inline bool is_exception_with_error_code(u32 intr_info) 160 { 161 const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK; 162 163 return (intr_info & mask) == mask; 164 } 165 166 enum vmcs_field_width { 167 VMCS_FIELD_WIDTH_U16 = 0, 168 VMCS_FIELD_WIDTH_U64 = 1, 169 VMCS_FIELD_WIDTH_U32 = 2, 170 VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3 171 }; 172 173 static inline int vmcs_field_width(unsigned long field) 174 { 175 if (0x1 & field) /* the *_HIGH fields are all 32 bit */ 176 return VMCS_FIELD_WIDTH_U32; 177 return (field >> 13) & 0x3; 178 } 179 180 static inline int vmcs_field_readonly(unsigned long field) 181 { 182 return (((field >> 10) & 0x3) == 1); 183 } 184 185 #define VMCS_FIELD_INDEX_SHIFT (1) 186 #define VMCS_FIELD_INDEX_MASK GENMASK(9, 1) 187 188 static inline unsigned int vmcs_field_index(unsigned long field) 189 { 190 return (field & VMCS_FIELD_INDEX_MASK) >> VMCS_FIELD_INDEX_SHIFT; 191 } 192 193 #endif /* __KVM_X86_VMX_VMCS_H */ 194