1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * KVM PMU support for Intel CPUs 4 * 5 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 6 * 7 * Authors: 8 * Avi Kivity <avi@redhat.com> 9 * Gleb Natapov <gleb@redhat.com> 10 */ 11 #include <linux/types.h> 12 #include <linux/kvm_host.h> 13 #include <linux/perf_event.h> 14 #include <asm/perf_event.h> 15 #include "x86.h" 16 #include "cpuid.h" 17 #include "lapic.h" 18 #include "nested.h" 19 #include "pmu.h" 20 21 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0) 22 23 static struct kvm_event_hw_type_mapping intel_arch_events[] = { 24 [0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES }, 25 [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS }, 26 [2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES }, 27 [3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES }, 28 [4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES }, 29 [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS }, 30 [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES }, 31 /* The above index must match CPUID 0x0A.EBX bit vector */ 32 [7] = { 0x00, 0x03, PERF_COUNT_HW_REF_CPU_CYCLES }, 33 }; 34 35 /* mapping between fixed pmc index and intel_arch_events array */ 36 static int fixed_pmc_events[] = {1, 0, 7}; 37 38 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) 39 { 40 struct kvm_pmc *pmc; 41 u8 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl; 42 int i; 43 44 pmu->fixed_ctr_ctrl = data; 45 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { 46 u8 new_ctrl = fixed_ctrl_field(data, i); 47 u8 old_ctrl = fixed_ctrl_field(old_fixed_ctr_ctrl, i); 48 49 if (old_ctrl == new_ctrl) 50 continue; 51 52 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); 53 54 __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use); 55 reprogram_counter(pmc); 56 } 57 } 58 59 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx) 60 { 61 if (pmc_idx < INTEL_PMC_IDX_FIXED) { 62 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx, 63 MSR_P6_EVNTSEL0); 64 } else { 65 u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED; 66 67 return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0); 68 } 69 } 70 71 /* function is called when global control register has been updated. */ 72 static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data) 73 { 74 int bit; 75 u64 diff = pmu->global_ctrl ^ data; 76 struct kvm_pmc *pmc; 77 78 pmu->global_ctrl = data; 79 80 for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) { 81 pmc = intel_pmc_idx_to_pmc(pmu, bit); 82 if (pmc) 83 reprogram_counter(pmc); 84 } 85 } 86 87 static bool intel_hw_event_available(struct kvm_pmc *pmc) 88 { 89 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 90 u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT; 91 u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; 92 int i; 93 94 for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++) { 95 if (intel_arch_events[i].eventsel != event_select || 96 intel_arch_events[i].unit_mask != unit_mask) 97 continue; 98 99 /* disable event that reported as not present by cpuid */ 100 if ((i < 7) && !(pmu->available_event_types & (1 << i))) 101 return false; 102 103 break; 104 } 105 106 return true; 107 } 108 109 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */ 110 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) 111 { 112 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 113 114 if (!intel_pmu_has_perf_global_ctrl(pmu)) 115 return true; 116 117 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); 118 } 119 120 static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) 121 { 122 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 123 bool fixed = idx & (1u << 30); 124 125 idx &= ~(3u << 30); 126 127 return fixed ? idx < pmu->nr_arch_fixed_counters 128 : idx < pmu->nr_arch_gp_counters; 129 } 130 131 static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, 132 unsigned int idx, u64 *mask) 133 { 134 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 135 bool fixed = idx & (1u << 30); 136 struct kvm_pmc *counters; 137 unsigned int num_counters; 138 139 idx &= ~(3u << 30); 140 if (fixed) { 141 counters = pmu->fixed_counters; 142 num_counters = pmu->nr_arch_fixed_counters; 143 } else { 144 counters = pmu->gp_counters; 145 num_counters = pmu->nr_arch_gp_counters; 146 } 147 if (idx >= num_counters) 148 return NULL; 149 *mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP]; 150 return &counters[array_index_nospec(idx, num_counters)]; 151 } 152 153 static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu) 154 { 155 if (!guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 156 return 0; 157 158 return vcpu->arch.perf_capabilities; 159 } 160 161 static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu) 162 { 163 return (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_FW_WRITES) != 0; 164 } 165 166 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr) 167 { 168 if (!fw_writes_is_enabled(pmu_to_vcpu(pmu))) 169 return NULL; 170 171 return get_gp_pmc(pmu, msr, MSR_IA32_PMC0); 172 } 173 174 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu) 175 { 176 struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu); 177 178 return lbr->nr && (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_LBR_FMT); 179 } 180 181 static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index) 182 { 183 struct x86_pmu_lbr *records = vcpu_to_lbr_records(vcpu); 184 bool ret = false; 185 186 if (!intel_pmu_lbr_is_enabled(vcpu)) 187 return ret; 188 189 ret = (index == MSR_LBR_SELECT) || (index == MSR_LBR_TOS) || 190 (index >= records->from && index < records->from + records->nr) || 191 (index >= records->to && index < records->to + records->nr); 192 193 if (!ret && records->info) 194 ret = (index >= records->info && index < records->info + records->nr); 195 196 return ret; 197 } 198 199 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) 200 { 201 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 202 u64 perf_capabilities; 203 int ret; 204 205 switch (msr) { 206 case MSR_CORE_PERF_FIXED_CTR_CTRL: 207 case MSR_CORE_PERF_GLOBAL_STATUS: 208 case MSR_CORE_PERF_GLOBAL_CTRL: 209 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 210 return intel_pmu_has_perf_global_ctrl(pmu); 211 break; 212 case MSR_IA32_PEBS_ENABLE: 213 ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; 214 break; 215 case MSR_IA32_DS_AREA: 216 ret = guest_cpuid_has(vcpu, X86_FEATURE_DS); 217 break; 218 case MSR_PEBS_DATA_CFG: 219 perf_capabilities = vcpu_get_perf_capabilities(vcpu); 220 ret = (perf_capabilities & PERF_CAP_PEBS_BASELINE) && 221 ((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3); 222 break; 223 default: 224 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) || 225 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) || 226 get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr) || 227 intel_pmu_is_valid_lbr_msr(vcpu, msr); 228 break; 229 } 230 231 return ret; 232 } 233 234 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) 235 { 236 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 237 struct kvm_pmc *pmc; 238 239 pmc = get_fixed_pmc(pmu, msr); 240 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0); 241 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0); 242 243 return pmc; 244 } 245 246 static inline void intel_pmu_release_guest_lbr_event(struct kvm_vcpu *vcpu) 247 { 248 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 249 250 if (lbr_desc->event) { 251 perf_event_release_kernel(lbr_desc->event); 252 lbr_desc->event = NULL; 253 vcpu_to_pmu(vcpu)->event_count--; 254 } 255 } 256 257 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu) 258 { 259 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 260 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 261 struct perf_event *event; 262 263 /* 264 * The perf_event_attr is constructed in the minimum efficient way: 265 * - set 'pinned = true' to make it task pinned so that if another 266 * cpu pinned event reclaims LBR, the event->oncpu will be set to -1; 267 * - set '.exclude_host = true' to record guest branches behavior; 268 * 269 * - set '.config = INTEL_FIXED_VLBR_EVENT' to indicates host perf 270 * schedule the event without a real HW counter but a fake one; 271 * check is_guest_lbr_event() and __intel_get_event_constraints(); 272 * 273 * - set 'sample_type = PERF_SAMPLE_BRANCH_STACK' and 274 * 'branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK | 275 * PERF_SAMPLE_BRANCH_USER' to configure it as a LBR callstack 276 * event, which helps KVM to save/restore guest LBR records 277 * during host context switches and reduces quite a lot overhead, 278 * check branch_user_callstack() and intel_pmu_lbr_sched_task(); 279 */ 280 struct perf_event_attr attr = { 281 .type = PERF_TYPE_RAW, 282 .size = sizeof(attr), 283 .config = INTEL_FIXED_VLBR_EVENT, 284 .sample_type = PERF_SAMPLE_BRANCH_STACK, 285 .pinned = true, 286 .exclude_host = true, 287 .branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK | 288 PERF_SAMPLE_BRANCH_USER, 289 }; 290 291 if (unlikely(lbr_desc->event)) { 292 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 293 return 0; 294 } 295 296 event = perf_event_create_kernel_counter(&attr, -1, 297 current, NULL, NULL); 298 if (IS_ERR(event)) { 299 pr_debug_ratelimited("%s: failed %ld\n", 300 __func__, PTR_ERR(event)); 301 return PTR_ERR(event); 302 } 303 lbr_desc->event = event; 304 pmu->event_count++; 305 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 306 return 0; 307 } 308 309 /* 310 * It's safe to access LBR msrs from guest when they have not 311 * been passthrough since the host would help restore or reset 312 * the LBR msrs records when the guest LBR event is scheduled in. 313 */ 314 static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu, 315 struct msr_data *msr_info, bool read) 316 { 317 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 318 u32 index = msr_info->index; 319 320 if (!intel_pmu_is_valid_lbr_msr(vcpu, index)) 321 return false; 322 323 if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0) 324 goto dummy; 325 326 /* 327 * Disable irq to ensure the LBR feature doesn't get reclaimed by the 328 * host at the time the value is read from the msr, and this avoids the 329 * host LBR value to be leaked to the guest. If LBR has been reclaimed, 330 * return 0 on guest reads. 331 */ 332 local_irq_disable(); 333 if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) { 334 if (read) 335 rdmsrl(index, msr_info->data); 336 else 337 wrmsrl(index, msr_info->data); 338 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use); 339 local_irq_enable(); 340 return true; 341 } 342 clear_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use); 343 local_irq_enable(); 344 345 dummy: 346 if (read) 347 msr_info->data = 0; 348 return true; 349 } 350 351 static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 352 { 353 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 354 struct kvm_pmc *pmc; 355 u32 msr = msr_info->index; 356 357 switch (msr) { 358 case MSR_CORE_PERF_FIXED_CTR_CTRL: 359 msr_info->data = pmu->fixed_ctr_ctrl; 360 return 0; 361 case MSR_CORE_PERF_GLOBAL_STATUS: 362 msr_info->data = pmu->global_status; 363 return 0; 364 case MSR_CORE_PERF_GLOBAL_CTRL: 365 msr_info->data = pmu->global_ctrl; 366 return 0; 367 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 368 msr_info->data = 0; 369 return 0; 370 case MSR_IA32_PEBS_ENABLE: 371 msr_info->data = pmu->pebs_enable; 372 return 0; 373 case MSR_IA32_DS_AREA: 374 msr_info->data = pmu->ds_area; 375 return 0; 376 case MSR_PEBS_DATA_CFG: 377 msr_info->data = pmu->pebs_data_cfg; 378 return 0; 379 default: 380 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || 381 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { 382 u64 val = pmc_read_counter(pmc); 383 msr_info->data = 384 val & pmu->counter_bitmask[KVM_PMC_GP]; 385 return 0; 386 } else if ((pmc = get_fixed_pmc(pmu, msr))) { 387 u64 val = pmc_read_counter(pmc); 388 msr_info->data = 389 val & pmu->counter_bitmask[KVM_PMC_FIXED]; 390 return 0; 391 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { 392 msr_info->data = pmc->eventsel; 393 return 0; 394 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, true)) 395 return 0; 396 } 397 398 return 1; 399 } 400 401 static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 402 { 403 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 404 struct kvm_pmc *pmc; 405 u32 msr = msr_info->index; 406 u64 data = msr_info->data; 407 u64 reserved_bits; 408 409 switch (msr) { 410 case MSR_CORE_PERF_FIXED_CTR_CTRL: 411 if (pmu->fixed_ctr_ctrl == data) 412 return 0; 413 if (!(data & pmu->fixed_ctr_ctrl_mask)) { 414 reprogram_fixed_counters(pmu, data); 415 return 0; 416 } 417 break; 418 case MSR_CORE_PERF_GLOBAL_STATUS: 419 if (msr_info->host_initiated) { 420 pmu->global_status = data; 421 return 0; 422 } 423 break; /* RO MSR */ 424 case MSR_CORE_PERF_GLOBAL_CTRL: 425 if (pmu->global_ctrl == data) 426 return 0; 427 if (kvm_valid_perf_global_ctrl(pmu, data)) { 428 global_ctrl_changed(pmu, data); 429 return 0; 430 } 431 break; 432 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 433 if (!(data & pmu->global_ovf_ctrl_mask)) { 434 if (!msr_info->host_initiated) 435 pmu->global_status &= ~data; 436 return 0; 437 } 438 break; 439 case MSR_IA32_PEBS_ENABLE: 440 if (pmu->pebs_enable == data) 441 return 0; 442 if (!(data & pmu->pebs_enable_mask)) { 443 pmu->pebs_enable = data; 444 return 0; 445 } 446 break; 447 case MSR_IA32_DS_AREA: 448 if (msr_info->host_initiated && data && !guest_cpuid_has(vcpu, X86_FEATURE_DS)) 449 return 1; 450 if (is_noncanonical_address(data, vcpu)) 451 return 1; 452 pmu->ds_area = data; 453 return 0; 454 case MSR_PEBS_DATA_CFG: 455 if (pmu->pebs_data_cfg == data) 456 return 0; 457 if (!(data & pmu->pebs_data_cfg_mask)) { 458 pmu->pebs_data_cfg = data; 459 return 0; 460 } 461 break; 462 default: 463 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || 464 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { 465 if ((msr & MSR_PMC_FULL_WIDTH_BIT) && 466 (data & ~pmu->counter_bitmask[KVM_PMC_GP])) 467 return 1; 468 if (!msr_info->host_initiated && 469 !(msr & MSR_PMC_FULL_WIDTH_BIT)) 470 data = (s64)(s32)data; 471 pmc->counter += data - pmc_read_counter(pmc); 472 pmc_update_sample_period(pmc); 473 return 0; 474 } else if ((pmc = get_fixed_pmc(pmu, msr))) { 475 pmc->counter += data - pmc_read_counter(pmc); 476 pmc_update_sample_period(pmc); 477 return 0; 478 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { 479 if (data == pmc->eventsel) 480 return 0; 481 reserved_bits = pmu->reserved_bits; 482 if ((pmc->idx == 2) && 483 (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED)) 484 reserved_bits ^= HSW_IN_TX_CHECKPOINTED; 485 if (!(data & reserved_bits)) { 486 pmc->eventsel = data; 487 reprogram_counter(pmc); 488 return 0; 489 } 490 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false)) 491 return 0; 492 } 493 494 return 1; 495 } 496 497 static void setup_fixed_pmc_eventsel(struct kvm_pmu *pmu) 498 { 499 size_t size = ARRAY_SIZE(fixed_pmc_events); 500 struct kvm_pmc *pmc; 501 u32 event; 502 int i; 503 504 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { 505 pmc = &pmu->fixed_counters[i]; 506 event = fixed_pmc_events[array_index_nospec(i, size)]; 507 pmc->eventsel = (intel_arch_events[event].unit_mask << 8) | 508 intel_arch_events[event].eventsel; 509 } 510 } 511 512 static void intel_pmu_refresh(struct kvm_vcpu *vcpu) 513 { 514 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 515 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 516 struct kvm_cpuid_entry2 *entry; 517 union cpuid10_eax eax; 518 union cpuid10_edx edx; 519 u64 perf_capabilities; 520 u64 counter_mask; 521 int i; 522 523 pmu->nr_arch_gp_counters = 0; 524 pmu->nr_arch_fixed_counters = 0; 525 pmu->counter_bitmask[KVM_PMC_GP] = 0; 526 pmu->counter_bitmask[KVM_PMC_FIXED] = 0; 527 pmu->version = 0; 528 pmu->reserved_bits = 0xffffffff00200000ull; 529 pmu->raw_event_mask = X86_RAW_EVENT_MASK; 530 pmu->global_ctrl_mask = ~0ull; 531 pmu->global_ovf_ctrl_mask = ~0ull; 532 pmu->fixed_ctr_ctrl_mask = ~0ull; 533 pmu->pebs_enable_mask = ~0ull; 534 pmu->pebs_data_cfg_mask = ~0ull; 535 536 entry = kvm_find_cpuid_entry(vcpu, 0xa); 537 if (!entry || !vcpu->kvm->arch.enable_pmu) 538 return; 539 eax.full = entry->eax; 540 edx.full = entry->edx; 541 542 pmu->version = eax.split.version_id; 543 if (!pmu->version) 544 return; 545 546 pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters, 547 kvm_pmu_cap.num_counters_gp); 548 eax.split.bit_width = min_t(int, eax.split.bit_width, 549 kvm_pmu_cap.bit_width_gp); 550 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1; 551 eax.split.mask_length = min_t(int, eax.split.mask_length, 552 kvm_pmu_cap.events_mask_len); 553 pmu->available_event_types = ~entry->ebx & 554 ((1ull << eax.split.mask_length) - 1); 555 556 if (pmu->version == 1) { 557 pmu->nr_arch_fixed_counters = 0; 558 } else { 559 pmu->nr_arch_fixed_counters = 560 min3(ARRAY_SIZE(fixed_pmc_events), 561 (size_t) edx.split.num_counters_fixed, 562 (size_t)kvm_pmu_cap.num_counters_fixed); 563 edx.split.bit_width_fixed = min_t(int, edx.split.bit_width_fixed, 564 kvm_pmu_cap.bit_width_fixed); 565 pmu->counter_bitmask[KVM_PMC_FIXED] = 566 ((u64)1 << edx.split.bit_width_fixed) - 1; 567 setup_fixed_pmc_eventsel(pmu); 568 } 569 570 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) 571 pmu->fixed_ctr_ctrl_mask &= ~(0xbull << (i * 4)); 572 counter_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) | 573 (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED)); 574 pmu->global_ctrl_mask = counter_mask; 575 pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask 576 & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF | 577 MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD); 578 if (vmx_pt_mode_is_host_guest()) 579 pmu->global_ovf_ctrl_mask &= 580 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI; 581 582 entry = kvm_find_cpuid_entry_index(vcpu, 7, 0); 583 if (entry && 584 (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) && 585 (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) { 586 pmu->reserved_bits ^= HSW_IN_TX; 587 pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 588 } 589 590 bitmap_set(pmu->all_valid_pmc_idx, 591 0, pmu->nr_arch_gp_counters); 592 bitmap_set(pmu->all_valid_pmc_idx, 593 INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters); 594 595 if (cpuid_model_is_consistent(vcpu)) 596 x86_perf_get_lbr(&lbr_desc->records); 597 else 598 lbr_desc->records.nr = 0; 599 600 if (lbr_desc->records.nr) 601 bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1); 602 603 perf_capabilities = vcpu_get_perf_capabilities(vcpu); 604 if (perf_capabilities & PERF_CAP_PEBS_FORMAT) { 605 if (perf_capabilities & PERF_CAP_PEBS_BASELINE) { 606 pmu->pebs_enable_mask = counter_mask; 607 pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; 608 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { 609 pmu->fixed_ctr_ctrl_mask &= 610 ~(1ULL << (INTEL_PMC_IDX_FIXED + i * 4)); 611 } 612 pmu->pebs_data_cfg_mask = ~0xff00000full; 613 } else { 614 pmu->pebs_enable_mask = 615 ~((1ull << pmu->nr_arch_gp_counters) - 1); 616 } 617 } 618 } 619 620 static void intel_pmu_init(struct kvm_vcpu *vcpu) 621 { 622 int i; 623 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 624 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 625 626 for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) { 627 pmu->gp_counters[i].type = KVM_PMC_GP; 628 pmu->gp_counters[i].vcpu = vcpu; 629 pmu->gp_counters[i].idx = i; 630 pmu->gp_counters[i].current_config = 0; 631 } 632 633 for (i = 0; i < KVM_PMC_MAX_FIXED; i++) { 634 pmu->fixed_counters[i].type = KVM_PMC_FIXED; 635 pmu->fixed_counters[i].vcpu = vcpu; 636 pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED; 637 pmu->fixed_counters[i].current_config = 0; 638 } 639 640 vcpu->arch.perf_capabilities = vmx_get_perf_capabilities(); 641 lbr_desc->records.nr = 0; 642 lbr_desc->event = NULL; 643 lbr_desc->msr_passthrough = false; 644 } 645 646 static void intel_pmu_reset(struct kvm_vcpu *vcpu) 647 { 648 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 649 struct kvm_pmc *pmc = NULL; 650 int i; 651 652 for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) { 653 pmc = &pmu->gp_counters[i]; 654 655 pmc_stop_counter(pmc); 656 pmc->counter = pmc->eventsel = 0; 657 } 658 659 for (i = 0; i < KVM_PMC_MAX_FIXED; i++) { 660 pmc = &pmu->fixed_counters[i]; 661 662 pmc_stop_counter(pmc); 663 pmc->counter = 0; 664 } 665 666 pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = 0; 667 668 intel_pmu_release_guest_lbr_event(vcpu); 669 } 670 671 /* 672 * Emulate LBR_On_PMI behavior for 1 < pmu.version < 4. 673 * 674 * If Freeze_LBR_On_PMI = 1, the LBR is frozen on PMI and 675 * the KVM emulates to clear the LBR bit (bit 0) in IA32_DEBUGCTL. 676 * 677 * Guest needs to re-enable LBR to resume branches recording. 678 */ 679 static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu) 680 { 681 u64 data = vmcs_read64(GUEST_IA32_DEBUGCTL); 682 683 if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) { 684 data &= ~DEBUGCTLMSR_LBR; 685 vmcs_write64(GUEST_IA32_DEBUGCTL, data); 686 } 687 } 688 689 static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu) 690 { 691 u8 version = vcpu_to_pmu(vcpu)->version; 692 693 if (!intel_pmu_lbr_is_enabled(vcpu)) 694 return; 695 696 if (version > 1 && version < 4) 697 intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu); 698 } 699 700 static void vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set) 701 { 702 struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu); 703 int i; 704 705 for (i = 0; i < lbr->nr; i++) { 706 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set); 707 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set); 708 if (lbr->info) 709 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set); 710 } 711 712 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set); 713 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set); 714 } 715 716 static inline void vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu) 717 { 718 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 719 720 if (!lbr_desc->msr_passthrough) 721 return; 722 723 vmx_update_intercept_for_lbr_msrs(vcpu, true); 724 lbr_desc->msr_passthrough = false; 725 } 726 727 static inline void vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu) 728 { 729 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 730 731 if (lbr_desc->msr_passthrough) 732 return; 733 734 vmx_update_intercept_for_lbr_msrs(vcpu, false); 735 lbr_desc->msr_passthrough = true; 736 } 737 738 /* 739 * Higher priority host perf events (e.g. cpu pinned) could reclaim the 740 * pmu resources (e.g. LBR) that were assigned to the guest. This is 741 * usually done via ipi calls (more details in perf_install_in_context). 742 * 743 * Before entering the non-root mode (with irq disabled here), double 744 * confirm that the pmu features enabled to the guest are not reclaimed 745 * by higher priority host events. Otherwise, disallow vcpu's access to 746 * the reclaimed features. 747 */ 748 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu) 749 { 750 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 751 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 752 753 if (!lbr_desc->event) { 754 vmx_disable_lbr_msrs_passthrough(vcpu); 755 if (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR) 756 goto warn; 757 if (test_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use)) 758 goto warn; 759 return; 760 } 761 762 if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) { 763 vmx_disable_lbr_msrs_passthrough(vcpu); 764 __clear_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 765 goto warn; 766 } else 767 vmx_enable_lbr_msrs_passthrough(vcpu); 768 769 return; 770 771 warn: 772 pr_warn_ratelimited("kvm: vcpu-%d: fail to passthrough LBR.\n", 773 vcpu->vcpu_id); 774 } 775 776 static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) 777 { 778 if (!(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR)) 779 intel_pmu_release_guest_lbr_event(vcpu); 780 } 781 782 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) 783 { 784 struct kvm_pmc *pmc = NULL; 785 int bit; 786 787 for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl, 788 X86_PMC_IDX_MAX) { 789 pmc = intel_pmc_idx_to_pmc(pmu, bit); 790 791 if (!pmc || !pmc_speculative_in_use(pmc) || 792 !intel_pmc_is_enabled(pmc)) 793 continue; 794 795 if (pmc->perf_event && pmc->idx != pmc->perf_event->hw.idx) { 796 pmu->host_cross_mapped_mask |= 797 BIT_ULL(pmc->perf_event->hw.idx); 798 } 799 } 800 } 801 802 struct kvm_pmu_ops intel_pmu_ops __initdata = { 803 .hw_event_available = intel_hw_event_available, 804 .pmc_is_enabled = intel_pmc_is_enabled, 805 .pmc_idx_to_pmc = intel_pmc_idx_to_pmc, 806 .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc, 807 .msr_idx_to_pmc = intel_msr_idx_to_pmc, 808 .is_valid_rdpmc_ecx = intel_is_valid_rdpmc_ecx, 809 .is_valid_msr = intel_is_valid_msr, 810 .get_msr = intel_pmu_get_msr, 811 .set_msr = intel_pmu_set_msr, 812 .refresh = intel_pmu_refresh, 813 .init = intel_pmu_init, 814 .reset = intel_pmu_reset, 815 .deliver_pmi = intel_pmu_deliver_pmi, 816 .cleanup = intel_pmu_cleanup, 817 }; 818