1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * KVM PMU support for Intel CPUs 4 * 5 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 6 * 7 * Authors: 8 * Avi Kivity <avi@redhat.com> 9 * Gleb Natapov <gleb@redhat.com> 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/types.h> 14 #include <linux/kvm_host.h> 15 #include <linux/perf_event.h> 16 #include <asm/perf_event.h> 17 #include "x86.h" 18 #include "cpuid.h" 19 #include "lapic.h" 20 #include "nested.h" 21 #include "pmu.h" 22 23 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0) 24 25 static struct { 26 u8 eventsel; 27 u8 unit_mask; 28 } const intel_arch_events[] = { 29 [0] = { 0x3c, 0x00 }, 30 [1] = { 0xc0, 0x00 }, 31 [2] = { 0x3c, 0x01 }, 32 [3] = { 0x2e, 0x4f }, 33 [4] = { 0x2e, 0x41 }, 34 [5] = { 0xc4, 0x00 }, 35 [6] = { 0xc5, 0x00 }, 36 /* The above index must match CPUID 0x0A.EBX bit vector */ 37 [7] = { 0x00, 0x03 }, 38 }; 39 40 /* mapping between fixed pmc index and intel_arch_events array */ 41 static int fixed_pmc_events[] = {1, 0, 7}; 42 43 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) 44 { 45 struct kvm_pmc *pmc; 46 u8 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl; 47 int i; 48 49 pmu->fixed_ctr_ctrl = data; 50 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { 51 u8 new_ctrl = fixed_ctrl_field(data, i); 52 u8 old_ctrl = fixed_ctrl_field(old_fixed_ctr_ctrl, i); 53 54 if (old_ctrl == new_ctrl) 55 continue; 56 57 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); 58 59 __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use); 60 kvm_pmu_request_counter_reprogam(pmc); 61 } 62 } 63 64 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx) 65 { 66 if (pmc_idx < INTEL_PMC_IDX_FIXED) { 67 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx, 68 MSR_P6_EVNTSEL0); 69 } else { 70 u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED; 71 72 return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0); 73 } 74 } 75 76 static void reprogram_counters(struct kvm_pmu *pmu, u64 diff) 77 { 78 int bit; 79 struct kvm_pmc *pmc; 80 81 for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) { 82 pmc = intel_pmc_idx_to_pmc(pmu, bit); 83 if (pmc) 84 kvm_pmu_request_counter_reprogam(pmc); 85 } 86 } 87 88 static bool intel_hw_event_available(struct kvm_pmc *pmc) 89 { 90 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 91 u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT; 92 u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; 93 int i; 94 95 for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++) { 96 if (intel_arch_events[i].eventsel != event_select || 97 intel_arch_events[i].unit_mask != unit_mask) 98 continue; 99 100 /* disable event that reported as not present by cpuid */ 101 if ((i < 7) && !(pmu->available_event_types & (1 << i))) 102 return false; 103 104 break; 105 } 106 107 return true; 108 } 109 110 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */ 111 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) 112 { 113 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 114 115 if (!intel_pmu_has_perf_global_ctrl(pmu)) 116 return true; 117 118 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); 119 } 120 121 static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) 122 { 123 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 124 bool fixed = idx & (1u << 30); 125 126 idx &= ~(3u << 30); 127 128 return fixed ? idx < pmu->nr_arch_fixed_counters 129 : idx < pmu->nr_arch_gp_counters; 130 } 131 132 static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, 133 unsigned int idx, u64 *mask) 134 { 135 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 136 bool fixed = idx & (1u << 30); 137 struct kvm_pmc *counters; 138 unsigned int num_counters; 139 140 idx &= ~(3u << 30); 141 if (fixed) { 142 counters = pmu->fixed_counters; 143 num_counters = pmu->nr_arch_fixed_counters; 144 } else { 145 counters = pmu->gp_counters; 146 num_counters = pmu->nr_arch_gp_counters; 147 } 148 if (idx >= num_counters) 149 return NULL; 150 *mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP]; 151 return &counters[array_index_nospec(idx, num_counters)]; 152 } 153 154 static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu) 155 { 156 if (!guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 157 return 0; 158 159 return vcpu->arch.perf_capabilities; 160 } 161 162 static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu) 163 { 164 return (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_FW_WRITES) != 0; 165 } 166 167 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr) 168 { 169 if (!fw_writes_is_enabled(pmu_to_vcpu(pmu))) 170 return NULL; 171 172 return get_gp_pmc(pmu, msr, MSR_IA32_PMC0); 173 } 174 175 static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index) 176 { 177 struct x86_pmu_lbr *records = vcpu_to_lbr_records(vcpu); 178 bool ret = false; 179 180 if (!intel_pmu_lbr_is_enabled(vcpu)) 181 return ret; 182 183 ret = (index == MSR_LBR_SELECT) || (index == MSR_LBR_TOS) || 184 (index >= records->from && index < records->from + records->nr) || 185 (index >= records->to && index < records->to + records->nr); 186 187 if (!ret && records->info) 188 ret = (index >= records->info && index < records->info + records->nr); 189 190 return ret; 191 } 192 193 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) 194 { 195 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 196 u64 perf_capabilities; 197 int ret; 198 199 switch (msr) { 200 case MSR_CORE_PERF_FIXED_CTR_CTRL: 201 case MSR_CORE_PERF_GLOBAL_STATUS: 202 case MSR_CORE_PERF_GLOBAL_CTRL: 203 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 204 return intel_pmu_has_perf_global_ctrl(pmu); 205 break; 206 case MSR_IA32_PEBS_ENABLE: 207 ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; 208 break; 209 case MSR_IA32_DS_AREA: 210 ret = guest_cpuid_has(vcpu, X86_FEATURE_DS); 211 break; 212 case MSR_PEBS_DATA_CFG: 213 perf_capabilities = vcpu_get_perf_capabilities(vcpu); 214 ret = (perf_capabilities & PERF_CAP_PEBS_BASELINE) && 215 ((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3); 216 break; 217 default: 218 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) || 219 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) || 220 get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr) || 221 intel_pmu_is_valid_lbr_msr(vcpu, msr); 222 break; 223 } 224 225 return ret; 226 } 227 228 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) 229 { 230 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 231 struct kvm_pmc *pmc; 232 233 pmc = get_fixed_pmc(pmu, msr); 234 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0); 235 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0); 236 237 return pmc; 238 } 239 240 static inline void intel_pmu_release_guest_lbr_event(struct kvm_vcpu *vcpu) 241 { 242 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 243 244 if (lbr_desc->event) { 245 perf_event_release_kernel(lbr_desc->event); 246 lbr_desc->event = NULL; 247 vcpu_to_pmu(vcpu)->event_count--; 248 } 249 } 250 251 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu) 252 { 253 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 254 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 255 struct perf_event *event; 256 257 /* 258 * The perf_event_attr is constructed in the minimum efficient way: 259 * - set 'pinned = true' to make it task pinned so that if another 260 * cpu pinned event reclaims LBR, the event->oncpu will be set to -1; 261 * - set '.exclude_host = true' to record guest branches behavior; 262 * 263 * - set '.config = INTEL_FIXED_VLBR_EVENT' to indicates host perf 264 * schedule the event without a real HW counter but a fake one; 265 * check is_guest_lbr_event() and __intel_get_event_constraints(); 266 * 267 * - set 'sample_type = PERF_SAMPLE_BRANCH_STACK' and 268 * 'branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK | 269 * PERF_SAMPLE_BRANCH_USER' to configure it as a LBR callstack 270 * event, which helps KVM to save/restore guest LBR records 271 * during host context switches and reduces quite a lot overhead, 272 * check branch_user_callstack() and intel_pmu_lbr_sched_task(); 273 */ 274 struct perf_event_attr attr = { 275 .type = PERF_TYPE_RAW, 276 .size = sizeof(attr), 277 .config = INTEL_FIXED_VLBR_EVENT, 278 .sample_type = PERF_SAMPLE_BRANCH_STACK, 279 .pinned = true, 280 .exclude_host = true, 281 .branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK | 282 PERF_SAMPLE_BRANCH_USER, 283 }; 284 285 if (unlikely(lbr_desc->event)) { 286 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 287 return 0; 288 } 289 290 event = perf_event_create_kernel_counter(&attr, -1, 291 current, NULL, NULL); 292 if (IS_ERR(event)) { 293 pr_debug_ratelimited("%s: failed %ld\n", 294 __func__, PTR_ERR(event)); 295 return PTR_ERR(event); 296 } 297 lbr_desc->event = event; 298 pmu->event_count++; 299 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 300 return 0; 301 } 302 303 /* 304 * It's safe to access LBR msrs from guest when they have not 305 * been passthrough since the host would help restore or reset 306 * the LBR msrs records when the guest LBR event is scheduled in. 307 */ 308 static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu, 309 struct msr_data *msr_info, bool read) 310 { 311 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 312 u32 index = msr_info->index; 313 314 if (!intel_pmu_is_valid_lbr_msr(vcpu, index)) 315 return false; 316 317 if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0) 318 goto dummy; 319 320 /* 321 * Disable irq to ensure the LBR feature doesn't get reclaimed by the 322 * host at the time the value is read from the msr, and this avoids the 323 * host LBR value to be leaked to the guest. If LBR has been reclaimed, 324 * return 0 on guest reads. 325 */ 326 local_irq_disable(); 327 if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) { 328 if (read) 329 rdmsrl(index, msr_info->data); 330 else 331 wrmsrl(index, msr_info->data); 332 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use); 333 local_irq_enable(); 334 return true; 335 } 336 clear_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use); 337 local_irq_enable(); 338 339 dummy: 340 if (read) 341 msr_info->data = 0; 342 return true; 343 } 344 345 static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 346 { 347 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 348 struct kvm_pmc *pmc; 349 u32 msr = msr_info->index; 350 351 switch (msr) { 352 case MSR_CORE_PERF_FIXED_CTR_CTRL: 353 msr_info->data = pmu->fixed_ctr_ctrl; 354 return 0; 355 case MSR_CORE_PERF_GLOBAL_STATUS: 356 msr_info->data = pmu->global_status; 357 return 0; 358 case MSR_CORE_PERF_GLOBAL_CTRL: 359 msr_info->data = pmu->global_ctrl; 360 return 0; 361 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 362 msr_info->data = 0; 363 return 0; 364 case MSR_IA32_PEBS_ENABLE: 365 msr_info->data = pmu->pebs_enable; 366 return 0; 367 case MSR_IA32_DS_AREA: 368 msr_info->data = pmu->ds_area; 369 return 0; 370 case MSR_PEBS_DATA_CFG: 371 msr_info->data = pmu->pebs_data_cfg; 372 return 0; 373 default: 374 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || 375 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { 376 u64 val = pmc_read_counter(pmc); 377 msr_info->data = 378 val & pmu->counter_bitmask[KVM_PMC_GP]; 379 return 0; 380 } else if ((pmc = get_fixed_pmc(pmu, msr))) { 381 u64 val = pmc_read_counter(pmc); 382 msr_info->data = 383 val & pmu->counter_bitmask[KVM_PMC_FIXED]; 384 return 0; 385 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { 386 msr_info->data = pmc->eventsel; 387 return 0; 388 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, true)) 389 return 0; 390 } 391 392 return 1; 393 } 394 395 static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 396 { 397 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 398 struct kvm_pmc *pmc; 399 u32 msr = msr_info->index; 400 u64 data = msr_info->data; 401 u64 reserved_bits, diff; 402 403 switch (msr) { 404 case MSR_CORE_PERF_FIXED_CTR_CTRL: 405 if (pmu->fixed_ctr_ctrl == data) 406 return 0; 407 if (!(data & pmu->fixed_ctr_ctrl_mask)) { 408 reprogram_fixed_counters(pmu, data); 409 return 0; 410 } 411 break; 412 case MSR_CORE_PERF_GLOBAL_STATUS: 413 if (msr_info->host_initiated) { 414 pmu->global_status = data; 415 return 0; 416 } 417 break; /* RO MSR */ 418 case MSR_CORE_PERF_GLOBAL_CTRL: 419 if (pmu->global_ctrl == data) 420 return 0; 421 if (kvm_valid_perf_global_ctrl(pmu, data)) { 422 diff = pmu->global_ctrl ^ data; 423 pmu->global_ctrl = data; 424 reprogram_counters(pmu, diff); 425 return 0; 426 } 427 break; 428 case MSR_CORE_PERF_GLOBAL_OVF_CTRL: 429 if (!(data & pmu->global_ovf_ctrl_mask)) { 430 if (!msr_info->host_initiated) 431 pmu->global_status &= ~data; 432 return 0; 433 } 434 break; 435 case MSR_IA32_PEBS_ENABLE: 436 if (pmu->pebs_enable == data) 437 return 0; 438 if (!(data & pmu->pebs_enable_mask)) { 439 diff = pmu->pebs_enable ^ data; 440 pmu->pebs_enable = data; 441 reprogram_counters(pmu, diff); 442 return 0; 443 } 444 break; 445 case MSR_IA32_DS_AREA: 446 if (msr_info->host_initiated && data && !guest_cpuid_has(vcpu, X86_FEATURE_DS)) 447 return 1; 448 if (is_noncanonical_address(data, vcpu)) 449 return 1; 450 pmu->ds_area = data; 451 return 0; 452 case MSR_PEBS_DATA_CFG: 453 if (pmu->pebs_data_cfg == data) 454 return 0; 455 if (!(data & pmu->pebs_data_cfg_mask)) { 456 pmu->pebs_data_cfg = data; 457 return 0; 458 } 459 break; 460 default: 461 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || 462 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { 463 if ((msr & MSR_PMC_FULL_WIDTH_BIT) && 464 (data & ~pmu->counter_bitmask[KVM_PMC_GP])) 465 return 1; 466 if (!msr_info->host_initiated && 467 !(msr & MSR_PMC_FULL_WIDTH_BIT)) 468 data = (s64)(s32)data; 469 pmc->counter += data - pmc_read_counter(pmc); 470 pmc_update_sample_period(pmc); 471 return 0; 472 } else if ((pmc = get_fixed_pmc(pmu, msr))) { 473 pmc->counter += data - pmc_read_counter(pmc); 474 pmc_update_sample_period(pmc); 475 return 0; 476 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { 477 if (data == pmc->eventsel) 478 return 0; 479 reserved_bits = pmu->reserved_bits; 480 if ((pmc->idx == 2) && 481 (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED)) 482 reserved_bits ^= HSW_IN_TX_CHECKPOINTED; 483 if (!(data & reserved_bits)) { 484 pmc->eventsel = data; 485 kvm_pmu_request_counter_reprogam(pmc); 486 return 0; 487 } 488 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false)) 489 return 0; 490 } 491 492 return 1; 493 } 494 495 static void setup_fixed_pmc_eventsel(struct kvm_pmu *pmu) 496 { 497 size_t size = ARRAY_SIZE(fixed_pmc_events); 498 struct kvm_pmc *pmc; 499 u32 event; 500 int i; 501 502 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { 503 pmc = &pmu->fixed_counters[i]; 504 event = fixed_pmc_events[array_index_nospec(i, size)]; 505 pmc->eventsel = (intel_arch_events[event].unit_mask << 8) | 506 intel_arch_events[event].eventsel; 507 } 508 } 509 510 static void intel_pmu_refresh(struct kvm_vcpu *vcpu) 511 { 512 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 513 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 514 struct kvm_cpuid_entry2 *entry; 515 union cpuid10_eax eax; 516 union cpuid10_edx edx; 517 u64 perf_capabilities; 518 u64 counter_mask; 519 int i; 520 521 pmu->nr_arch_gp_counters = 0; 522 pmu->nr_arch_fixed_counters = 0; 523 pmu->counter_bitmask[KVM_PMC_GP] = 0; 524 pmu->counter_bitmask[KVM_PMC_FIXED] = 0; 525 pmu->version = 0; 526 pmu->reserved_bits = 0xffffffff00200000ull; 527 pmu->raw_event_mask = X86_RAW_EVENT_MASK; 528 pmu->global_ctrl_mask = ~0ull; 529 pmu->global_ovf_ctrl_mask = ~0ull; 530 pmu->fixed_ctr_ctrl_mask = ~0ull; 531 pmu->pebs_enable_mask = ~0ull; 532 pmu->pebs_data_cfg_mask = ~0ull; 533 534 entry = kvm_find_cpuid_entry(vcpu, 0xa); 535 if (!entry || !vcpu->kvm->arch.enable_pmu) 536 return; 537 eax.full = entry->eax; 538 edx.full = entry->edx; 539 540 pmu->version = eax.split.version_id; 541 if (!pmu->version) 542 return; 543 544 pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters, 545 kvm_pmu_cap.num_counters_gp); 546 eax.split.bit_width = min_t(int, eax.split.bit_width, 547 kvm_pmu_cap.bit_width_gp); 548 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1; 549 eax.split.mask_length = min_t(int, eax.split.mask_length, 550 kvm_pmu_cap.events_mask_len); 551 pmu->available_event_types = ~entry->ebx & 552 ((1ull << eax.split.mask_length) - 1); 553 554 if (pmu->version == 1) { 555 pmu->nr_arch_fixed_counters = 0; 556 } else { 557 pmu->nr_arch_fixed_counters = 558 min3(ARRAY_SIZE(fixed_pmc_events), 559 (size_t) edx.split.num_counters_fixed, 560 (size_t)kvm_pmu_cap.num_counters_fixed); 561 edx.split.bit_width_fixed = min_t(int, edx.split.bit_width_fixed, 562 kvm_pmu_cap.bit_width_fixed); 563 pmu->counter_bitmask[KVM_PMC_FIXED] = 564 ((u64)1 << edx.split.bit_width_fixed) - 1; 565 setup_fixed_pmc_eventsel(pmu); 566 } 567 568 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) 569 pmu->fixed_ctr_ctrl_mask &= ~(0xbull << (i * 4)); 570 counter_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) | 571 (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED)); 572 pmu->global_ctrl_mask = counter_mask; 573 pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask 574 & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF | 575 MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD); 576 if (vmx_pt_mode_is_host_guest()) 577 pmu->global_ovf_ctrl_mask &= 578 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI; 579 580 entry = kvm_find_cpuid_entry_index(vcpu, 7, 0); 581 if (entry && 582 (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) && 583 (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) { 584 pmu->reserved_bits ^= HSW_IN_TX; 585 pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 586 } 587 588 bitmap_set(pmu->all_valid_pmc_idx, 589 0, pmu->nr_arch_gp_counters); 590 bitmap_set(pmu->all_valid_pmc_idx, 591 INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters); 592 593 perf_capabilities = vcpu_get_perf_capabilities(vcpu); 594 if (cpuid_model_is_consistent(vcpu) && 595 (perf_capabilities & PMU_CAP_LBR_FMT)) 596 x86_perf_get_lbr(&lbr_desc->records); 597 else 598 lbr_desc->records.nr = 0; 599 600 if (lbr_desc->records.nr) 601 bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1); 602 603 if (perf_capabilities & PERF_CAP_PEBS_FORMAT) { 604 if (perf_capabilities & PERF_CAP_PEBS_BASELINE) { 605 pmu->pebs_enable_mask = counter_mask; 606 pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; 607 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { 608 pmu->fixed_ctr_ctrl_mask &= 609 ~(1ULL << (INTEL_PMC_IDX_FIXED + i * 4)); 610 } 611 pmu->pebs_data_cfg_mask = ~0xff00000full; 612 } else { 613 pmu->pebs_enable_mask = 614 ~((1ull << pmu->nr_arch_gp_counters) - 1); 615 } 616 } 617 } 618 619 static void intel_pmu_init(struct kvm_vcpu *vcpu) 620 { 621 int i; 622 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 623 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 624 625 for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) { 626 pmu->gp_counters[i].type = KVM_PMC_GP; 627 pmu->gp_counters[i].vcpu = vcpu; 628 pmu->gp_counters[i].idx = i; 629 pmu->gp_counters[i].current_config = 0; 630 } 631 632 for (i = 0; i < KVM_PMC_MAX_FIXED; i++) { 633 pmu->fixed_counters[i].type = KVM_PMC_FIXED; 634 pmu->fixed_counters[i].vcpu = vcpu; 635 pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED; 636 pmu->fixed_counters[i].current_config = 0; 637 } 638 639 lbr_desc->records.nr = 0; 640 lbr_desc->event = NULL; 641 lbr_desc->msr_passthrough = false; 642 } 643 644 static void intel_pmu_reset(struct kvm_vcpu *vcpu) 645 { 646 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 647 struct kvm_pmc *pmc = NULL; 648 int i; 649 650 for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) { 651 pmc = &pmu->gp_counters[i]; 652 653 pmc_stop_counter(pmc); 654 pmc->counter = pmc->prev_counter = pmc->eventsel = 0; 655 } 656 657 for (i = 0; i < KVM_PMC_MAX_FIXED; i++) { 658 pmc = &pmu->fixed_counters[i]; 659 660 pmc_stop_counter(pmc); 661 pmc->counter = pmc->prev_counter = 0; 662 } 663 664 pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = 0; 665 666 intel_pmu_release_guest_lbr_event(vcpu); 667 } 668 669 /* 670 * Emulate LBR_On_PMI behavior for 1 < pmu.version < 4. 671 * 672 * If Freeze_LBR_On_PMI = 1, the LBR is frozen on PMI and 673 * the KVM emulates to clear the LBR bit (bit 0) in IA32_DEBUGCTL. 674 * 675 * Guest needs to re-enable LBR to resume branches recording. 676 */ 677 static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu) 678 { 679 u64 data = vmcs_read64(GUEST_IA32_DEBUGCTL); 680 681 if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) { 682 data &= ~DEBUGCTLMSR_LBR; 683 vmcs_write64(GUEST_IA32_DEBUGCTL, data); 684 } 685 } 686 687 static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu) 688 { 689 u8 version = vcpu_to_pmu(vcpu)->version; 690 691 if (!intel_pmu_lbr_is_enabled(vcpu)) 692 return; 693 694 if (version > 1 && version < 4) 695 intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu); 696 } 697 698 static void vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set) 699 { 700 struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu); 701 int i; 702 703 for (i = 0; i < lbr->nr; i++) { 704 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set); 705 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set); 706 if (lbr->info) 707 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set); 708 } 709 710 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set); 711 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set); 712 } 713 714 static inline void vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu) 715 { 716 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 717 718 if (!lbr_desc->msr_passthrough) 719 return; 720 721 vmx_update_intercept_for_lbr_msrs(vcpu, true); 722 lbr_desc->msr_passthrough = false; 723 } 724 725 static inline void vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu) 726 { 727 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 728 729 if (lbr_desc->msr_passthrough) 730 return; 731 732 vmx_update_intercept_for_lbr_msrs(vcpu, false); 733 lbr_desc->msr_passthrough = true; 734 } 735 736 /* 737 * Higher priority host perf events (e.g. cpu pinned) could reclaim the 738 * pmu resources (e.g. LBR) that were assigned to the guest. This is 739 * usually done via ipi calls (more details in perf_install_in_context). 740 * 741 * Before entering the non-root mode (with irq disabled here), double 742 * confirm that the pmu features enabled to the guest are not reclaimed 743 * by higher priority host events. Otherwise, disallow vcpu's access to 744 * the reclaimed features. 745 */ 746 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu) 747 { 748 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 749 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu); 750 751 if (!lbr_desc->event) { 752 vmx_disable_lbr_msrs_passthrough(vcpu); 753 if (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR) 754 goto warn; 755 if (test_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use)) 756 goto warn; 757 return; 758 } 759 760 if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) { 761 vmx_disable_lbr_msrs_passthrough(vcpu); 762 __clear_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use); 763 goto warn; 764 } else 765 vmx_enable_lbr_msrs_passthrough(vcpu); 766 767 return; 768 769 warn: 770 pr_warn_ratelimited("vcpu-%d: fail to passthrough LBR.\n", vcpu->vcpu_id); 771 } 772 773 static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) 774 { 775 if (!(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR)) 776 intel_pmu_release_guest_lbr_event(vcpu); 777 } 778 779 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) 780 { 781 struct kvm_pmc *pmc = NULL; 782 int bit, hw_idx; 783 784 for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl, 785 X86_PMC_IDX_MAX) { 786 pmc = intel_pmc_idx_to_pmc(pmu, bit); 787 788 if (!pmc || !pmc_speculative_in_use(pmc) || 789 !intel_pmc_is_enabled(pmc) || !pmc->perf_event) 790 continue; 791 792 /* 793 * A negative index indicates the event isn't mapped to a 794 * physical counter in the host, e.g. due to contention. 795 */ 796 hw_idx = pmc->perf_event->hw.idx; 797 if (hw_idx != pmc->idx && hw_idx > -1) 798 pmu->host_cross_mapped_mask |= BIT_ULL(hw_idx); 799 } 800 } 801 802 struct kvm_pmu_ops intel_pmu_ops __initdata = { 803 .hw_event_available = intel_hw_event_available, 804 .pmc_is_enabled = intel_pmc_is_enabled, 805 .pmc_idx_to_pmc = intel_pmc_idx_to_pmc, 806 .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc, 807 .msr_idx_to_pmc = intel_msr_idx_to_pmc, 808 .is_valid_rdpmc_ecx = intel_is_valid_rdpmc_ecx, 809 .is_valid_msr = intel_is_valid_msr, 810 .get_msr = intel_pmu_get_msr, 811 .set_msr = intel_pmu_set_msr, 812 .refresh = intel_pmu_refresh, 813 .init = intel_pmu_init, 814 .reset = intel_pmu_reset, 815 .deliver_pmi = intel_pmu_deliver_pmi, 816 .cleanup = intel_pmu_cleanup, 817 .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT, 818 .MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC, 819 }; 820