1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_NESTED_H 3 #define __KVM_X86_VMX_NESTED_H 4 5 #include "kvm_cache_regs.h" 6 #include "vmcs12.h" 7 #include "vmx.h" 8 9 /* 10 * Status returned by nested_vmx_enter_non_root_mode(): 11 */ 12 enum nvmx_vmentry_status { 13 NVMX_VMENTRY_SUCCESS, /* Entered VMX non-root mode */ 14 NVMX_VMENTRY_VMFAIL, /* Consistency check VMFail */ 15 NVMX_VMENTRY_VMEXIT, /* Consistency check VMExit */ 16 NVMX_VMENTRY_KVM_INTERNAL_ERROR,/* KVM internal error */ 17 }; 18 19 void vmx_leave_nested(struct kvm_vcpu *vcpu); 20 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps); 21 void nested_vmx_hardware_unsetup(void); 22 __init int nested_vmx_hardware_setup(struct kvm_x86_ops *ops, 23 int (*exit_handlers[])(struct kvm_vcpu *)); 24 void nested_vmx_set_vmcs_shadowing_bitmap(void); 25 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu); 26 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, 27 bool from_vmentry); 28 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu); 29 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, 30 u32 exit_intr_info, unsigned long exit_qualification); 31 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu); 32 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); 33 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata); 34 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, 35 u32 vmx_instruction_info, bool wr, int len, gva_t *ret); 36 void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu); 37 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu); 38 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, 39 int size); 40 41 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) 42 { 43 return to_vmx(vcpu)->nested.cached_vmcs12; 44 } 45 46 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu) 47 { 48 return to_vmx(vcpu)->nested.cached_shadow_vmcs12; 49 } 50 51 static inline int vmx_has_valid_vmcs12(struct kvm_vcpu *vcpu) 52 { 53 struct vcpu_vmx *vmx = to_vmx(vcpu); 54 55 /* 56 * In case we do two consecutive get/set_nested_state()s while L2 was 57 * running hv_evmcs may end up not being mapped (we map it from 58 * nested_vmx_run()/vmx_vcpu_run()). Check is_guest_mode() as we always 59 * have vmcs12 if it is true. 60 */ 61 return is_guest_mode(vcpu) || vmx->nested.current_vmptr != -1ull || 62 vmx->nested.hv_evmcs; 63 } 64 65 static inline u16 nested_get_vpid02(struct kvm_vcpu *vcpu) 66 { 67 struct vcpu_vmx *vmx = to_vmx(vcpu); 68 69 return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid; 70 } 71 72 static inline unsigned long nested_ept_get_eptp(struct kvm_vcpu *vcpu) 73 { 74 /* return the page table to be shadowed - in our case, EPT12 */ 75 return get_vmcs12(vcpu)->ept_pointer; 76 } 77 78 static inline bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) 79 { 80 return nested_ept_get_eptp(vcpu) & VMX_EPTP_AD_ENABLE_BIT; 81 } 82 83 /* 84 * Return the cr0 value that a nested guest would read. This is a combination 85 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by 86 * its hypervisor (cr0_read_shadow). 87 */ 88 static inline unsigned long nested_read_cr0(struct vmcs12 *fields) 89 { 90 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | 91 (fields->cr0_read_shadow & fields->cr0_guest_host_mask); 92 } 93 static inline unsigned long nested_read_cr4(struct vmcs12 *fields) 94 { 95 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | 96 (fields->cr4_read_shadow & fields->cr4_guest_host_mask); 97 } 98 99 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) 100 { 101 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low); 102 } 103 104 /* 105 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE 106 * to modify any valid field of the VMCS, or are the VM-exit 107 * information fields read-only? 108 */ 109 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu) 110 { 111 return to_vmx(vcpu)->nested.msrs.misc_low & 112 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS; 113 } 114 115 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu) 116 { 117 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS; 118 } 119 120 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu) 121 { 122 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high & 123 CPU_BASED_MONITOR_TRAP_FLAG; 124 } 125 126 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu) 127 { 128 return to_vmx(vcpu)->nested.msrs.secondary_ctls_high & 129 SECONDARY_EXEC_SHADOW_VMCS; 130 } 131 132 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) 133 { 134 return vmcs12->cpu_based_vm_exec_control & bit; 135 } 136 137 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) 138 { 139 return (vmcs12->cpu_based_vm_exec_control & 140 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && 141 (vmcs12->secondary_vm_exec_control & bit); 142 } 143 144 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) 145 { 146 return vmcs12->pin_based_vm_exec_control & 147 PIN_BASED_VMX_PREEMPTION_TIMER; 148 } 149 150 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12) 151 { 152 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING; 153 } 154 155 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) 156 { 157 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; 158 } 159 160 static inline int nested_cpu_has_mtf(struct vmcs12 *vmcs12) 161 { 162 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); 163 } 164 165 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) 166 { 167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); 168 } 169 170 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) 171 { 172 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); 173 } 174 175 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) 176 { 177 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); 178 } 179 180 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) 181 { 182 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 183 } 184 185 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) 186 { 187 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); 188 } 189 190 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) 191 { 192 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); 193 } 194 195 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) 196 { 197 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 198 } 199 200 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) 201 { 202 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; 203 } 204 205 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) 206 { 207 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); 208 } 209 210 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) 211 { 212 return nested_cpu_has_vmfunc(vmcs12) && 213 (vmcs12->vm_function_control & 214 VMX_VMFUNC_EPTP_SWITCHING); 215 } 216 217 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12) 218 { 219 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS); 220 } 221 222 static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12 *vmcs12) 223 { 224 return vmcs12->vm_exit_controls & 225 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER; 226 } 227 228 /* 229 * In nested virtualization, check if L1 asked to exit on external interrupts. 230 * For most existing hypervisors, this will always return true. 231 */ 232 static inline bool nested_exit_on_intr(struct kvm_vcpu *vcpu) 233 { 234 return get_vmcs12(vcpu)->pin_based_vm_exec_control & 235 PIN_BASED_EXT_INTR_MASK; 236 } 237 238 /* 239 * if fixed0[i] == 1: val[i] must be 1 240 * if fixed1[i] == 0: val[i] must be 0 241 */ 242 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) 243 { 244 return ((val & fixed1) | fixed0) == val; 245 } 246 247 static inline bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) 248 { 249 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; 250 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; 251 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 252 253 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high & 254 SECONDARY_EXEC_UNRESTRICTED_GUEST && 255 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) 256 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); 257 258 return fixed_bits_valid(val, fixed0, fixed1); 259 } 260 261 static inline bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) 262 { 263 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; 264 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; 265 266 return fixed_bits_valid(val, fixed0, fixed1); 267 } 268 269 static inline bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) 270 { 271 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0; 272 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1; 273 274 return fixed_bits_valid(val, fixed0, fixed1); 275 } 276 277 /* No difference in the restrictions on guest and host CR4 in VMX operation. */ 278 #define nested_guest_cr4_valid nested_cr4_valid 279 #define nested_host_cr4_valid nested_cr4_valid 280 281 #endif /* __KVM_X86_VMX_NESTED_H */ 282