1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_NESTED_H 3 #define __KVM_X86_VMX_NESTED_H 4 5 #include "kvm_cache_regs.h" 6 #include "vmcs12.h" 7 #include "vmx.h" 8 9 /* 10 * Status returned by nested_vmx_enter_non_root_mode(): 11 */ 12 enum nvmx_vmentry_status { 13 NVMX_VMENTRY_SUCCESS, /* Entered VMX non-root mode */ 14 NVMX_VMENTRY_VMFAIL, /* Consistency check VMFail */ 15 NVMX_VMENTRY_VMEXIT, /* Consistency check VMExit */ 16 NVMX_VMENTRY_KVM_INTERNAL_ERROR,/* KVM internal error */ 17 }; 18 19 void vmx_leave_nested(struct kvm_vcpu *vcpu); 20 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps); 21 void nested_vmx_hardware_unsetup(void); 22 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *)); 23 void nested_vmx_set_vmcs_shadowing_bitmap(void); 24 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu); 25 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, 26 bool from_vmentry); 27 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu); 28 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, 29 u32 exit_intr_info, unsigned long exit_qualification); 30 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu); 31 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); 32 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata); 33 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, 34 u32 vmx_instruction_info, bool wr, int len, gva_t *ret); 35 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu); 36 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, 37 int size); 38 39 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) 40 { 41 return to_vmx(vcpu)->nested.cached_vmcs12; 42 } 43 44 static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu) 45 { 46 return to_vmx(vcpu)->nested.cached_shadow_vmcs12; 47 } 48 49 /* 50 * Note: the same condition is checked against the state provided by userspace 51 * in vmx_set_nested_state; if it is satisfied, the nested state must include 52 * the VMCS12. 53 */ 54 static inline int vmx_has_valid_vmcs12(struct kvm_vcpu *vcpu) 55 { 56 struct vcpu_vmx *vmx = to_vmx(vcpu); 57 58 /* 'hv_evmcs_vmptr' can also be EVMPTR_MAP_PENDING here */ 59 return vmx->nested.current_vmptr != -1ull || 60 vmx->nested.hv_evmcs_vmptr != EVMPTR_INVALID; 61 } 62 63 static inline u16 nested_get_vpid02(struct kvm_vcpu *vcpu) 64 { 65 struct vcpu_vmx *vmx = to_vmx(vcpu); 66 67 return vmx->nested.vpid02 ? vmx->nested.vpid02 : vmx->vpid; 68 } 69 70 static inline unsigned long nested_ept_get_eptp(struct kvm_vcpu *vcpu) 71 { 72 /* return the page table to be shadowed - in our case, EPT12 */ 73 return get_vmcs12(vcpu)->ept_pointer; 74 } 75 76 static inline bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) 77 { 78 return nested_ept_get_eptp(vcpu) & VMX_EPTP_AD_ENABLE_BIT; 79 } 80 81 /* 82 * Return the cr0 value that a nested guest would read. This is a combination 83 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by 84 * its hypervisor (cr0_read_shadow). 85 */ 86 static inline unsigned long nested_read_cr0(struct vmcs12 *fields) 87 { 88 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | 89 (fields->cr0_read_shadow & fields->cr0_guest_host_mask); 90 } 91 static inline unsigned long nested_read_cr4(struct vmcs12 *fields) 92 { 93 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | 94 (fields->cr4_read_shadow & fields->cr4_guest_host_mask); 95 } 96 97 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) 98 { 99 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low); 100 } 101 102 /* 103 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE 104 * to modify any valid field of the VMCS, or are the VM-exit 105 * information fields read-only? 106 */ 107 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu) 108 { 109 return to_vmx(vcpu)->nested.msrs.misc_low & 110 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS; 111 } 112 113 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu) 114 { 115 return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS; 116 } 117 118 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu) 119 { 120 return to_vmx(vcpu)->nested.msrs.procbased_ctls_high & 121 CPU_BASED_MONITOR_TRAP_FLAG; 122 } 123 124 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu) 125 { 126 return to_vmx(vcpu)->nested.msrs.secondary_ctls_high & 127 SECONDARY_EXEC_SHADOW_VMCS; 128 } 129 130 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) 131 { 132 return vmcs12->cpu_based_vm_exec_control & bit; 133 } 134 135 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) 136 { 137 return (vmcs12->cpu_based_vm_exec_control & 138 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && 139 (vmcs12->secondary_vm_exec_control & bit); 140 } 141 142 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) 143 { 144 return vmcs12->pin_based_vm_exec_control & 145 PIN_BASED_VMX_PREEMPTION_TIMER; 146 } 147 148 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12) 149 { 150 return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING; 151 } 152 153 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) 154 { 155 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; 156 } 157 158 static inline int nested_cpu_has_mtf(struct vmcs12 *vmcs12) 159 { 160 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); 161 } 162 163 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) 164 { 165 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); 166 } 167 168 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) 169 { 170 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); 171 } 172 173 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) 174 { 175 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); 176 } 177 178 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) 179 { 180 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 181 } 182 183 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) 184 { 185 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); 186 } 187 188 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) 189 { 190 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); 191 } 192 193 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) 194 { 195 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 196 } 197 198 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) 199 { 200 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; 201 } 202 203 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) 204 { 205 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); 206 } 207 208 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) 209 { 210 return nested_cpu_has_vmfunc(vmcs12) && 211 (vmcs12->vm_function_control & 212 VMX_VMFUNC_EPTP_SWITCHING); 213 } 214 215 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12) 216 { 217 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS); 218 } 219 220 static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12 *vmcs12) 221 { 222 return vmcs12->vm_exit_controls & 223 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER; 224 } 225 226 static inline bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) 227 { 228 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu)); 229 } 230 231 /* 232 * In nested virtualization, check if L1 asked to exit on external interrupts. 233 * For most existing hypervisors, this will always return true. 234 */ 235 static inline bool nested_exit_on_intr(struct kvm_vcpu *vcpu) 236 { 237 return get_vmcs12(vcpu)->pin_based_vm_exec_control & 238 PIN_BASED_EXT_INTR_MASK; 239 } 240 241 static inline bool nested_cpu_has_encls_exit(struct vmcs12 *vmcs12) 242 { 243 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING); 244 } 245 246 /* 247 * if fixed0[i] == 1: val[i] must be 1 248 * if fixed1[i] == 0: val[i] must be 0 249 */ 250 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) 251 { 252 return ((val & fixed1) | fixed0) == val; 253 } 254 255 static inline bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) 256 { 257 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; 258 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; 259 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 260 261 if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high & 262 SECONDARY_EXEC_UNRESTRICTED_GUEST && 263 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) 264 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); 265 266 return fixed_bits_valid(val, fixed0, fixed1); 267 } 268 269 static inline bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) 270 { 271 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0; 272 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1; 273 274 return fixed_bits_valid(val, fixed0, fixed1); 275 } 276 277 static inline bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) 278 { 279 u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0; 280 u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1; 281 282 return fixed_bits_valid(val, fixed0, fixed1) && 283 __kvm_is_valid_cr4(vcpu, val); 284 } 285 286 /* No difference in the restrictions on guest and host CR4 in VMX operation. */ 287 #define nested_guest_cr4_valid nested_cr4_valid 288 #define nested_host_cr4_valid nested_cr4_valid 289 290 extern struct kvm_x86_nested_ops vmx_nested_ops; 291 292 #endif /* __KVM_X86_VMX_NESTED_H */ 293