1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/objtool.h> 5 #include <linux/percpu.h> 6 7 #include <asm/debugreg.h> 8 #include <asm/mmu_context.h> 9 10 #include "cpuid.h" 11 #include "hyperv.h" 12 #include "mmu.h" 13 #include "nested.h" 14 #include "pmu.h" 15 #include "posted_intr.h" 16 #include "sgx.h" 17 #include "trace.h" 18 #include "vmx.h" 19 #include "x86.h" 20 #include "smm.h" 21 22 static bool __read_mostly enable_shadow_vmcs = 1; 23 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); 24 25 static bool __read_mostly nested_early_check = 0; 26 module_param(nested_early_check, bool, S_IRUGO); 27 28 #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK 29 30 /* 31 * Hyper-V requires all of these, so mark them as supported even though 32 * they are just treated the same as all-context. 33 */ 34 #define VMX_VPID_EXTENT_SUPPORTED_MASK \ 35 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ 36 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ 37 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ 38 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) 39 40 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 41 42 enum { 43 VMX_VMREAD_BITMAP, 44 VMX_VMWRITE_BITMAP, 45 VMX_BITMAP_NR 46 }; 47 static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; 48 49 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) 50 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) 51 52 struct shadow_vmcs_field { 53 u16 encoding; 54 u16 offset; 55 }; 56 static struct shadow_vmcs_field shadow_read_only_fields[] = { 57 #define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) }, 58 #include "vmcs_shadow_fields.h" 59 }; 60 static int max_shadow_read_only_fields = 61 ARRAY_SIZE(shadow_read_only_fields); 62 63 static struct shadow_vmcs_field shadow_read_write_fields[] = { 64 #define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) }, 65 #include "vmcs_shadow_fields.h" 66 }; 67 static int max_shadow_read_write_fields = 68 ARRAY_SIZE(shadow_read_write_fields); 69 70 static void init_vmcs_shadow_fields(void) 71 { 72 int i, j; 73 74 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); 75 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); 76 77 for (i = j = 0; i < max_shadow_read_only_fields; i++) { 78 struct shadow_vmcs_field entry = shadow_read_only_fields[i]; 79 u16 field = entry.encoding; 80 81 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 && 82 (i + 1 == max_shadow_read_only_fields || 83 shadow_read_only_fields[i + 1].encoding != field + 1)) 84 pr_err("Missing field from shadow_read_only_field %x\n", 85 field + 1); 86 87 clear_bit(field, vmx_vmread_bitmap); 88 if (field & 1) 89 #ifdef CONFIG_X86_64 90 continue; 91 #else 92 entry.offset += sizeof(u32); 93 #endif 94 shadow_read_only_fields[j++] = entry; 95 } 96 max_shadow_read_only_fields = j; 97 98 for (i = j = 0; i < max_shadow_read_write_fields; i++) { 99 struct shadow_vmcs_field entry = shadow_read_write_fields[i]; 100 u16 field = entry.encoding; 101 102 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 && 103 (i + 1 == max_shadow_read_write_fields || 104 shadow_read_write_fields[i + 1].encoding != field + 1)) 105 pr_err("Missing field from shadow_read_write_field %x\n", 106 field + 1); 107 108 WARN_ONCE(field >= GUEST_ES_AR_BYTES && 109 field <= GUEST_TR_AR_BYTES, 110 "Update vmcs12_write_any() to drop reserved bits from AR_BYTES"); 111 112 /* 113 * PML and the preemption timer can be emulated, but the 114 * processor cannot vmwrite to fields that don't exist 115 * on bare metal. 116 */ 117 switch (field) { 118 case GUEST_PML_INDEX: 119 if (!cpu_has_vmx_pml()) 120 continue; 121 break; 122 case VMX_PREEMPTION_TIMER_VALUE: 123 if (!cpu_has_vmx_preemption_timer()) 124 continue; 125 break; 126 case GUEST_INTR_STATUS: 127 if (!cpu_has_vmx_apicv()) 128 continue; 129 break; 130 default: 131 break; 132 } 133 134 clear_bit(field, vmx_vmwrite_bitmap); 135 clear_bit(field, vmx_vmread_bitmap); 136 if (field & 1) 137 #ifdef CONFIG_X86_64 138 continue; 139 #else 140 entry.offset += sizeof(u32); 141 #endif 142 shadow_read_write_fields[j++] = entry; 143 } 144 max_shadow_read_write_fields = j; 145 } 146 147 /* 148 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), 149 * set the success or error code of an emulated VMX instruction (as specified 150 * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated 151 * instruction. 152 */ 153 static int nested_vmx_succeed(struct kvm_vcpu *vcpu) 154 { 155 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) 156 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 157 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); 158 return kvm_skip_emulated_instruction(vcpu); 159 } 160 161 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu) 162 { 163 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) 164 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 165 X86_EFLAGS_SF | X86_EFLAGS_OF)) 166 | X86_EFLAGS_CF); 167 return kvm_skip_emulated_instruction(vcpu); 168 } 169 170 static int nested_vmx_failValid(struct kvm_vcpu *vcpu, 171 u32 vm_instruction_error) 172 { 173 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) 174 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 175 X86_EFLAGS_SF | X86_EFLAGS_OF)) 176 | X86_EFLAGS_ZF); 177 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; 178 /* 179 * We don't need to force sync to shadow VMCS because 180 * VM_INSTRUCTION_ERROR is not shadowed. Enlightened VMCS 'shadows' all 181 * fields and thus must be synced. 182 */ 183 if (to_vmx(vcpu)->nested.hv_evmcs_vmptr != EVMPTR_INVALID) 184 to_vmx(vcpu)->nested.need_vmcs12_to_shadow_sync = true; 185 186 return kvm_skip_emulated_instruction(vcpu); 187 } 188 189 static int nested_vmx_fail(struct kvm_vcpu *vcpu, u32 vm_instruction_error) 190 { 191 struct vcpu_vmx *vmx = to_vmx(vcpu); 192 193 /* 194 * failValid writes the error number to the current VMCS, which 195 * can't be done if there isn't a current VMCS. 196 */ 197 if (vmx->nested.current_vmptr == INVALID_GPA && 198 !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) 199 return nested_vmx_failInvalid(vcpu); 200 201 return nested_vmx_failValid(vcpu, vm_instruction_error); 202 } 203 204 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) 205 { 206 /* TODO: not to reset guest simply here. */ 207 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 208 pr_debug_ratelimited("nested vmx abort, indicator %d\n", indicator); 209 } 210 211 static inline bool vmx_control_verify(u32 control, u32 low, u32 high) 212 { 213 return fixed_bits_valid(control, low, high); 214 } 215 216 static inline u64 vmx_control_msr(u32 low, u32 high) 217 { 218 return low | ((u64)high << 32); 219 } 220 221 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) 222 { 223 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS); 224 vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); 225 vmx->nested.need_vmcs12_to_shadow_sync = false; 226 } 227 228 static inline void nested_release_evmcs(struct kvm_vcpu *vcpu) 229 { 230 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 231 struct vcpu_vmx *vmx = to_vmx(vcpu); 232 233 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) { 234 kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true); 235 vmx->nested.hv_evmcs = NULL; 236 } 237 238 vmx->nested.hv_evmcs_vmptr = EVMPTR_INVALID; 239 240 if (hv_vcpu) { 241 hv_vcpu->nested.pa_page_gpa = INVALID_GPA; 242 hv_vcpu->nested.vm_id = 0; 243 hv_vcpu->nested.vp_id = 0; 244 } 245 } 246 247 static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx, 248 struct loaded_vmcs *prev) 249 { 250 struct vmcs_host_state *dest, *src; 251 252 if (unlikely(!vmx->guest_state_loaded)) 253 return; 254 255 src = &prev->host_state; 256 dest = &vmx->loaded_vmcs->host_state; 257 258 vmx_set_host_fs_gs(dest, src->fs_sel, src->gs_sel, src->fs_base, src->gs_base); 259 dest->ldt_sel = src->ldt_sel; 260 #ifdef CONFIG_X86_64 261 dest->ds_sel = src->ds_sel; 262 dest->es_sel = src->es_sel; 263 #endif 264 } 265 266 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) 267 { 268 struct vcpu_vmx *vmx = to_vmx(vcpu); 269 struct loaded_vmcs *prev; 270 int cpu; 271 272 if (WARN_ON_ONCE(vmx->loaded_vmcs == vmcs)) 273 return; 274 275 cpu = get_cpu(); 276 prev = vmx->loaded_vmcs; 277 vmx->loaded_vmcs = vmcs; 278 vmx_vcpu_load_vmcs(vcpu, cpu, prev); 279 vmx_sync_vmcs_host_state(vmx, prev); 280 put_cpu(); 281 282 vcpu->arch.regs_avail = ~VMX_REGS_LAZY_LOAD_SET; 283 284 /* 285 * All lazily updated registers will be reloaded from VMCS12 on both 286 * vmentry and vmexit. 287 */ 288 vcpu->arch.regs_dirty = 0; 289 } 290 291 /* 292 * Free whatever needs to be freed from vmx->nested when L1 goes down, or 293 * just stops using VMX. 294 */ 295 static void free_nested(struct kvm_vcpu *vcpu) 296 { 297 struct vcpu_vmx *vmx = to_vmx(vcpu); 298 299 if (WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01)) 300 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 301 302 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) 303 return; 304 305 kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 306 307 vmx->nested.vmxon = false; 308 vmx->nested.smm.vmxon = false; 309 vmx->nested.vmxon_ptr = INVALID_GPA; 310 free_vpid(vmx->nested.vpid02); 311 vmx->nested.posted_intr_nv = -1; 312 vmx->nested.current_vmptr = INVALID_GPA; 313 if (enable_shadow_vmcs) { 314 vmx_disable_shadow_vmcs(vmx); 315 vmcs_clear(vmx->vmcs01.shadow_vmcs); 316 free_vmcs(vmx->vmcs01.shadow_vmcs); 317 vmx->vmcs01.shadow_vmcs = NULL; 318 } 319 kfree(vmx->nested.cached_vmcs12); 320 vmx->nested.cached_vmcs12 = NULL; 321 kfree(vmx->nested.cached_shadow_vmcs12); 322 vmx->nested.cached_shadow_vmcs12 = NULL; 323 /* 324 * Unpin physical memory we referred to in the vmcs02. The APIC access 325 * page's backing page (yeah, confusing) shouldn't actually be accessed, 326 * and if it is written, the contents are irrelevant. 327 */ 328 kvm_vcpu_unmap(vcpu, &vmx->nested.apic_access_page_map, false); 329 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true); 330 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true); 331 vmx->nested.pi_desc = NULL; 332 333 kvm_mmu_free_roots(vcpu->kvm, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); 334 335 nested_release_evmcs(vcpu); 336 337 free_loaded_vmcs(&vmx->nested.vmcs02); 338 } 339 340 /* 341 * Ensure that the current vmcs of the logical processor is the 342 * vmcs01 of the vcpu before calling free_nested(). 343 */ 344 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu) 345 { 346 vcpu_load(vcpu); 347 vmx_leave_nested(vcpu); 348 vcpu_put(vcpu); 349 } 350 351 #define EPTP_PA_MASK GENMASK_ULL(51, 12) 352 353 static bool nested_ept_root_matches(hpa_t root_hpa, u64 root_eptp, u64 eptp) 354 { 355 return VALID_PAGE(root_hpa) && 356 ((root_eptp & EPTP_PA_MASK) == (eptp & EPTP_PA_MASK)); 357 } 358 359 static void nested_ept_invalidate_addr(struct kvm_vcpu *vcpu, gpa_t eptp, 360 gpa_t addr) 361 { 362 unsigned long roots = 0; 363 uint i; 364 struct kvm_mmu_root_info *cached_root; 365 366 WARN_ON_ONCE(!mmu_is_nested(vcpu)); 367 368 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { 369 cached_root = &vcpu->arch.mmu->prev_roots[i]; 370 371 if (nested_ept_root_matches(cached_root->hpa, cached_root->pgd, 372 eptp)) 373 roots |= KVM_MMU_ROOT_PREVIOUS(i); 374 } 375 if (roots) 376 kvm_mmu_invalidate_addr(vcpu, vcpu->arch.mmu, addr, roots); 377 } 378 379 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, 380 struct x86_exception *fault) 381 { 382 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 383 struct vcpu_vmx *vmx = to_vmx(vcpu); 384 u32 vm_exit_reason; 385 unsigned long exit_qualification = vcpu->arch.exit_qualification; 386 387 if (vmx->nested.pml_full) { 388 vm_exit_reason = EXIT_REASON_PML_FULL; 389 vmx->nested.pml_full = false; 390 exit_qualification &= INTR_INFO_UNBLOCK_NMI; 391 } else { 392 if (fault->error_code & PFERR_RSVD_MASK) 393 vm_exit_reason = EXIT_REASON_EPT_MISCONFIG; 394 else 395 vm_exit_reason = EXIT_REASON_EPT_VIOLATION; 396 397 /* 398 * Although the caller (kvm_inject_emulated_page_fault) would 399 * have already synced the faulting address in the shadow EPT 400 * tables for the current EPTP12, we also need to sync it for 401 * any other cached EPTP02s based on the same EP4TA, since the 402 * TLB associates mappings to the EP4TA rather than the full EPTP. 403 */ 404 nested_ept_invalidate_addr(vcpu, vmcs12->ept_pointer, 405 fault->address); 406 } 407 408 nested_vmx_vmexit(vcpu, vm_exit_reason, 0, exit_qualification); 409 vmcs12->guest_physical_address = fault->address; 410 } 411 412 static void nested_ept_new_eptp(struct kvm_vcpu *vcpu) 413 { 414 struct vcpu_vmx *vmx = to_vmx(vcpu); 415 bool execonly = vmx->nested.msrs.ept_caps & VMX_EPT_EXECUTE_ONLY_BIT; 416 int ept_lpage_level = ept_caps_to_lpage_level(vmx->nested.msrs.ept_caps); 417 418 kvm_init_shadow_ept_mmu(vcpu, execonly, ept_lpage_level, 419 nested_ept_ad_enabled(vcpu), 420 nested_ept_get_eptp(vcpu)); 421 } 422 423 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) 424 { 425 WARN_ON(mmu_is_nested(vcpu)); 426 427 vcpu->arch.mmu = &vcpu->arch.guest_mmu; 428 nested_ept_new_eptp(vcpu); 429 vcpu->arch.mmu->get_guest_pgd = nested_ept_get_eptp; 430 vcpu->arch.mmu->inject_page_fault = nested_ept_inject_page_fault; 431 vcpu->arch.mmu->get_pdptr = kvm_pdptr_read; 432 433 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; 434 } 435 436 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) 437 { 438 vcpu->arch.mmu = &vcpu->arch.root_mmu; 439 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; 440 } 441 442 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, 443 u16 error_code) 444 { 445 bool inequality, bit; 446 447 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; 448 inequality = 449 (error_code & vmcs12->page_fault_error_code_mask) != 450 vmcs12->page_fault_error_code_match; 451 return inequality ^ bit; 452 } 453 454 static bool nested_vmx_is_exception_vmexit(struct kvm_vcpu *vcpu, u8 vector, 455 u32 error_code) 456 { 457 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 458 459 /* 460 * Drop bits 31:16 of the error code when performing the #PF mask+match 461 * check. All VMCS fields involved are 32 bits, but Intel CPUs never 462 * set bits 31:16 and VMX disallows setting bits 31:16 in the injected 463 * error code. Including the to-be-dropped bits in the check might 464 * result in an "impossible" or missed exit from L1's perspective. 465 */ 466 if (vector == PF_VECTOR) 467 return nested_vmx_is_page_fault_vmexit(vmcs12, (u16)error_code); 468 469 return (vmcs12->exception_bitmap & (1u << vector)); 470 } 471 472 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, 473 struct vmcs12 *vmcs12) 474 { 475 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 476 return 0; 477 478 if (CC(!page_address_valid(vcpu, vmcs12->io_bitmap_a)) || 479 CC(!page_address_valid(vcpu, vmcs12->io_bitmap_b))) 480 return -EINVAL; 481 482 return 0; 483 } 484 485 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, 486 struct vmcs12 *vmcs12) 487 { 488 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 489 return 0; 490 491 if (CC(!page_address_valid(vcpu, vmcs12->msr_bitmap))) 492 return -EINVAL; 493 494 return 0; 495 } 496 497 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, 498 struct vmcs12 *vmcs12) 499 { 500 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 501 return 0; 502 503 if (CC(!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))) 504 return -EINVAL; 505 506 return 0; 507 } 508 509 /* 510 * For x2APIC MSRs, ignore the vmcs01 bitmap. L1 can enable x2APIC without L1 511 * itself utilizing x2APIC. All MSRs were previously set to be intercepted, 512 * only the "disable intercept" case needs to be handled. 513 */ 514 static void nested_vmx_disable_intercept_for_x2apic_msr(unsigned long *msr_bitmap_l1, 515 unsigned long *msr_bitmap_l0, 516 u32 msr, int type) 517 { 518 if (type & MSR_TYPE_R && !vmx_test_msr_bitmap_read(msr_bitmap_l1, msr)) 519 vmx_clear_msr_bitmap_read(msr_bitmap_l0, msr); 520 521 if (type & MSR_TYPE_W && !vmx_test_msr_bitmap_write(msr_bitmap_l1, msr)) 522 vmx_clear_msr_bitmap_write(msr_bitmap_l0, msr); 523 } 524 525 static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap) 526 { 527 int msr; 528 529 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 530 unsigned word = msr / BITS_PER_LONG; 531 532 msr_bitmap[word] = ~0; 533 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 534 } 535 } 536 537 #define BUILD_NVMX_MSR_INTERCEPT_HELPER(rw) \ 538 static inline \ 539 void nested_vmx_set_msr_##rw##_intercept(struct vcpu_vmx *vmx, \ 540 unsigned long *msr_bitmap_l1, \ 541 unsigned long *msr_bitmap_l0, u32 msr) \ 542 { \ 543 if (vmx_test_msr_bitmap_##rw(vmx->vmcs01.msr_bitmap, msr) || \ 544 vmx_test_msr_bitmap_##rw(msr_bitmap_l1, msr)) \ 545 vmx_set_msr_bitmap_##rw(msr_bitmap_l0, msr); \ 546 else \ 547 vmx_clear_msr_bitmap_##rw(msr_bitmap_l0, msr); \ 548 } 549 BUILD_NVMX_MSR_INTERCEPT_HELPER(read) 550 BUILD_NVMX_MSR_INTERCEPT_HELPER(write) 551 552 static inline void nested_vmx_set_intercept_for_msr(struct vcpu_vmx *vmx, 553 unsigned long *msr_bitmap_l1, 554 unsigned long *msr_bitmap_l0, 555 u32 msr, int types) 556 { 557 if (types & MSR_TYPE_R) 558 nested_vmx_set_msr_read_intercept(vmx, msr_bitmap_l1, 559 msr_bitmap_l0, msr); 560 if (types & MSR_TYPE_W) 561 nested_vmx_set_msr_write_intercept(vmx, msr_bitmap_l1, 562 msr_bitmap_l0, msr); 563 } 564 565 /* 566 * Merge L0's and L1's MSR bitmap, return false to indicate that 567 * we do not use the hardware. 568 */ 569 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, 570 struct vmcs12 *vmcs12) 571 { 572 struct vcpu_vmx *vmx = to_vmx(vcpu); 573 int msr; 574 unsigned long *msr_bitmap_l1; 575 unsigned long *msr_bitmap_l0 = vmx->nested.vmcs02.msr_bitmap; 576 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs; 577 struct kvm_host_map *map = &vmx->nested.msr_bitmap_map; 578 579 /* Nothing to do if the MSR bitmap is not in use. */ 580 if (!cpu_has_vmx_msr_bitmap() || 581 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 582 return false; 583 584 /* 585 * MSR bitmap update can be skipped when: 586 * - MSR bitmap for L1 hasn't changed. 587 * - Nested hypervisor (L1) is attempting to launch the same L2 as 588 * before. 589 * - Nested hypervisor (L1) has enabled 'Enlightened MSR Bitmap' feature 590 * and tells KVM (L0) there were no changes in MSR bitmap for L2. 591 */ 592 if (!vmx->nested.force_msr_bitmap_recalc && evmcs && 593 evmcs->hv_enlightenments_control.msr_bitmap && 594 evmcs->hv_clean_fields & HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP) 595 return true; 596 597 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->msr_bitmap), map)) 598 return false; 599 600 msr_bitmap_l1 = (unsigned long *)map->hva; 601 602 /* 603 * To keep the control flow simple, pay eight 8-byte writes (sixteen 604 * 4-byte writes on 32-bit systems) up front to enable intercepts for 605 * the x2APIC MSR range and selectively toggle those relevant to L2. 606 */ 607 enable_x2apic_msr_intercepts(msr_bitmap_l0); 608 609 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { 610 if (nested_cpu_has_apic_reg_virt(vmcs12)) { 611 /* 612 * L0 need not intercept reads for MSRs between 0x800 613 * and 0x8ff, it just lets the processor take the value 614 * from the virtual-APIC page; take those 256 bits 615 * directly from the L1 bitmap. 616 */ 617 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 618 unsigned word = msr / BITS_PER_LONG; 619 620 msr_bitmap_l0[word] = msr_bitmap_l1[word]; 621 } 622 } 623 624 nested_vmx_disable_intercept_for_x2apic_msr( 625 msr_bitmap_l1, msr_bitmap_l0, 626 X2APIC_MSR(APIC_TASKPRI), 627 MSR_TYPE_R | MSR_TYPE_W); 628 629 if (nested_cpu_has_vid(vmcs12)) { 630 nested_vmx_disable_intercept_for_x2apic_msr( 631 msr_bitmap_l1, msr_bitmap_l0, 632 X2APIC_MSR(APIC_EOI), 633 MSR_TYPE_W); 634 nested_vmx_disable_intercept_for_x2apic_msr( 635 msr_bitmap_l1, msr_bitmap_l0, 636 X2APIC_MSR(APIC_SELF_IPI), 637 MSR_TYPE_W); 638 } 639 } 640 641 /* 642 * Always check vmcs01's bitmap to honor userspace MSR filters and any 643 * other runtime changes to vmcs01's bitmap, e.g. dynamic pass-through. 644 */ 645 #ifdef CONFIG_X86_64 646 nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, 647 MSR_FS_BASE, MSR_TYPE_RW); 648 649 nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, 650 MSR_GS_BASE, MSR_TYPE_RW); 651 652 nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, 653 MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 654 #endif 655 nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, 656 MSR_IA32_SPEC_CTRL, MSR_TYPE_RW); 657 658 nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, 659 MSR_IA32_PRED_CMD, MSR_TYPE_W); 660 661 nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, 662 MSR_IA32_FLUSH_CMD, MSR_TYPE_W); 663 664 kvm_vcpu_unmap(vcpu, &vmx->nested.msr_bitmap_map, false); 665 666 vmx->nested.force_msr_bitmap_recalc = false; 667 668 return true; 669 } 670 671 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu, 672 struct vmcs12 *vmcs12) 673 { 674 struct vcpu_vmx *vmx = to_vmx(vcpu); 675 struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache; 676 677 if (!nested_cpu_has_shadow_vmcs(vmcs12) || 678 vmcs12->vmcs_link_pointer == INVALID_GPA) 679 return; 680 681 if (ghc->gpa != vmcs12->vmcs_link_pointer && 682 kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, 683 vmcs12->vmcs_link_pointer, VMCS12_SIZE)) 684 return; 685 686 kvm_read_guest_cached(vmx->vcpu.kvm, ghc, get_shadow_vmcs12(vcpu), 687 VMCS12_SIZE); 688 } 689 690 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu, 691 struct vmcs12 *vmcs12) 692 { 693 struct vcpu_vmx *vmx = to_vmx(vcpu); 694 struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache; 695 696 if (!nested_cpu_has_shadow_vmcs(vmcs12) || 697 vmcs12->vmcs_link_pointer == INVALID_GPA) 698 return; 699 700 if (ghc->gpa != vmcs12->vmcs_link_pointer && 701 kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, 702 vmcs12->vmcs_link_pointer, VMCS12_SIZE)) 703 return; 704 705 kvm_write_guest_cached(vmx->vcpu.kvm, ghc, get_shadow_vmcs12(vcpu), 706 VMCS12_SIZE); 707 } 708 709 /* 710 * In nested virtualization, check if L1 has set 711 * VM_EXIT_ACK_INTR_ON_EXIT 712 */ 713 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) 714 { 715 return get_vmcs12(vcpu)->vm_exit_controls & 716 VM_EXIT_ACK_INTR_ON_EXIT; 717 } 718 719 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu, 720 struct vmcs12 *vmcs12) 721 { 722 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) && 723 CC(!page_address_valid(vcpu, vmcs12->apic_access_addr))) 724 return -EINVAL; 725 else 726 return 0; 727 } 728 729 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, 730 struct vmcs12 *vmcs12) 731 { 732 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && 733 !nested_cpu_has_apic_reg_virt(vmcs12) && 734 !nested_cpu_has_vid(vmcs12) && 735 !nested_cpu_has_posted_intr(vmcs12)) 736 return 0; 737 738 /* 739 * If virtualize x2apic mode is enabled, 740 * virtualize apic access must be disabled. 741 */ 742 if (CC(nested_cpu_has_virt_x2apic_mode(vmcs12) && 743 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))) 744 return -EINVAL; 745 746 /* 747 * If virtual interrupt delivery is enabled, 748 * we must exit on external interrupts. 749 */ 750 if (CC(nested_cpu_has_vid(vmcs12) && !nested_exit_on_intr(vcpu))) 751 return -EINVAL; 752 753 /* 754 * bits 15:8 should be zero in posted_intr_nv, 755 * the descriptor address has been already checked 756 * in nested_get_vmcs12_pages. 757 * 758 * bits 5:0 of posted_intr_desc_addr should be zero. 759 */ 760 if (nested_cpu_has_posted_intr(vmcs12) && 761 (CC(!nested_cpu_has_vid(vmcs12)) || 762 CC(!nested_exit_intr_ack_set(vcpu)) || 763 CC((vmcs12->posted_intr_nv & 0xff00)) || 764 CC(!kvm_vcpu_is_legal_aligned_gpa(vcpu, vmcs12->posted_intr_desc_addr, 64)))) 765 return -EINVAL; 766 767 /* tpr shadow is needed by all apicv features. */ 768 if (CC(!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))) 769 return -EINVAL; 770 771 return 0; 772 } 773 774 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, 775 u32 count, u64 addr) 776 { 777 if (count == 0) 778 return 0; 779 780 if (!kvm_vcpu_is_legal_aligned_gpa(vcpu, addr, 16) || 781 !kvm_vcpu_is_legal_gpa(vcpu, (addr + count * sizeof(struct vmx_msr_entry) - 1))) 782 return -EINVAL; 783 784 return 0; 785 } 786 787 static int nested_vmx_check_exit_msr_switch_controls(struct kvm_vcpu *vcpu, 788 struct vmcs12 *vmcs12) 789 { 790 if (CC(nested_vmx_check_msr_switch(vcpu, 791 vmcs12->vm_exit_msr_load_count, 792 vmcs12->vm_exit_msr_load_addr)) || 793 CC(nested_vmx_check_msr_switch(vcpu, 794 vmcs12->vm_exit_msr_store_count, 795 vmcs12->vm_exit_msr_store_addr))) 796 return -EINVAL; 797 798 return 0; 799 } 800 801 static int nested_vmx_check_entry_msr_switch_controls(struct kvm_vcpu *vcpu, 802 struct vmcs12 *vmcs12) 803 { 804 if (CC(nested_vmx_check_msr_switch(vcpu, 805 vmcs12->vm_entry_msr_load_count, 806 vmcs12->vm_entry_msr_load_addr))) 807 return -EINVAL; 808 809 return 0; 810 } 811 812 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, 813 struct vmcs12 *vmcs12) 814 { 815 if (!nested_cpu_has_pml(vmcs12)) 816 return 0; 817 818 if (CC(!nested_cpu_has_ept(vmcs12)) || 819 CC(!page_address_valid(vcpu, vmcs12->pml_address))) 820 return -EINVAL; 821 822 return 0; 823 } 824 825 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu *vcpu, 826 struct vmcs12 *vmcs12) 827 { 828 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST) && 829 !nested_cpu_has_ept(vmcs12))) 830 return -EINVAL; 831 return 0; 832 } 833 834 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu *vcpu, 835 struct vmcs12 *vmcs12) 836 { 837 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_MODE_BASED_EPT_EXEC) && 838 !nested_cpu_has_ept(vmcs12))) 839 return -EINVAL; 840 return 0; 841 } 842 843 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu, 844 struct vmcs12 *vmcs12) 845 { 846 if (!nested_cpu_has_shadow_vmcs(vmcs12)) 847 return 0; 848 849 if (CC(!page_address_valid(vcpu, vmcs12->vmread_bitmap)) || 850 CC(!page_address_valid(vcpu, vmcs12->vmwrite_bitmap))) 851 return -EINVAL; 852 853 return 0; 854 } 855 856 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, 857 struct vmx_msr_entry *e) 858 { 859 /* x2APIC MSR accesses are not allowed */ 860 if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)) 861 return -EINVAL; 862 if (CC(e->index == MSR_IA32_UCODE_WRITE) || /* SDM Table 35-2 */ 863 CC(e->index == MSR_IA32_UCODE_REV)) 864 return -EINVAL; 865 if (CC(e->reserved != 0)) 866 return -EINVAL; 867 return 0; 868 } 869 870 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, 871 struct vmx_msr_entry *e) 872 { 873 if (CC(e->index == MSR_FS_BASE) || 874 CC(e->index == MSR_GS_BASE) || 875 CC(e->index == MSR_IA32_SMM_MONITOR_CTL) || /* SMM is not supported */ 876 nested_vmx_msr_check_common(vcpu, e)) 877 return -EINVAL; 878 return 0; 879 } 880 881 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, 882 struct vmx_msr_entry *e) 883 { 884 if (CC(e->index == MSR_IA32_SMBASE) || /* SMM is not supported */ 885 nested_vmx_msr_check_common(vcpu, e)) 886 return -EINVAL; 887 return 0; 888 } 889 890 static u32 nested_vmx_max_atomic_switch_msrs(struct kvm_vcpu *vcpu) 891 { 892 struct vcpu_vmx *vmx = to_vmx(vcpu); 893 u64 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low, 894 vmx->nested.msrs.misc_high); 895 896 return (vmx_misc_max_msr(vmx_misc) + 1) * VMX_MISC_MSR_LIST_MULTIPLIER; 897 } 898 899 /* 900 * Load guest's/host's msr at nested entry/exit. 901 * return 0 for success, entry index for failure. 902 * 903 * One of the failure modes for MSR load/store is when a list exceeds the 904 * virtual hardware's capacity. To maintain compatibility with hardware inasmuch 905 * as possible, process all valid entries before failing rather than precheck 906 * for a capacity violation. 907 */ 908 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) 909 { 910 u32 i; 911 struct vmx_msr_entry e; 912 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu); 913 914 for (i = 0; i < count; i++) { 915 if (unlikely(i >= max_msr_list_size)) 916 goto fail; 917 918 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), 919 &e, sizeof(e))) { 920 pr_debug_ratelimited( 921 "%s cannot read MSR entry (%u, 0x%08llx)\n", 922 __func__, i, gpa + i * sizeof(e)); 923 goto fail; 924 } 925 if (nested_vmx_load_msr_check(vcpu, &e)) { 926 pr_debug_ratelimited( 927 "%s check failed (%u, 0x%x, 0x%x)\n", 928 __func__, i, e.index, e.reserved); 929 goto fail; 930 } 931 if (kvm_set_msr(vcpu, e.index, e.value)) { 932 pr_debug_ratelimited( 933 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", 934 __func__, i, e.index, e.value); 935 goto fail; 936 } 937 } 938 return 0; 939 fail: 940 /* Note, max_msr_list_size is at most 4096, i.e. this can't wrap. */ 941 return i + 1; 942 } 943 944 static bool nested_vmx_get_vmexit_msr_value(struct kvm_vcpu *vcpu, 945 u32 msr_index, 946 u64 *data) 947 { 948 struct vcpu_vmx *vmx = to_vmx(vcpu); 949 950 /* 951 * If the L0 hypervisor stored a more accurate value for the TSC that 952 * does not include the time taken for emulation of the L2->L1 953 * VM-exit in L0, use the more accurate value. 954 */ 955 if (msr_index == MSR_IA32_TSC) { 956 int i = vmx_find_loadstore_msr_slot(&vmx->msr_autostore.guest, 957 MSR_IA32_TSC); 958 959 if (i >= 0) { 960 u64 val = vmx->msr_autostore.guest.val[i].value; 961 962 *data = kvm_read_l1_tsc(vcpu, val); 963 return true; 964 } 965 } 966 967 if (kvm_get_msr(vcpu, msr_index, data)) { 968 pr_debug_ratelimited("%s cannot read MSR (0x%x)\n", __func__, 969 msr_index); 970 return false; 971 } 972 return true; 973 } 974 975 static bool read_and_check_msr_entry(struct kvm_vcpu *vcpu, u64 gpa, int i, 976 struct vmx_msr_entry *e) 977 { 978 if (kvm_vcpu_read_guest(vcpu, 979 gpa + i * sizeof(*e), 980 e, 2 * sizeof(u32))) { 981 pr_debug_ratelimited( 982 "%s cannot read MSR entry (%u, 0x%08llx)\n", 983 __func__, i, gpa + i * sizeof(*e)); 984 return false; 985 } 986 if (nested_vmx_store_msr_check(vcpu, e)) { 987 pr_debug_ratelimited( 988 "%s check failed (%u, 0x%x, 0x%x)\n", 989 __func__, i, e->index, e->reserved); 990 return false; 991 } 992 return true; 993 } 994 995 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) 996 { 997 u64 data; 998 u32 i; 999 struct vmx_msr_entry e; 1000 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu); 1001 1002 for (i = 0; i < count; i++) { 1003 if (unlikely(i >= max_msr_list_size)) 1004 return -EINVAL; 1005 1006 if (!read_and_check_msr_entry(vcpu, gpa, i, &e)) 1007 return -EINVAL; 1008 1009 if (!nested_vmx_get_vmexit_msr_value(vcpu, e.index, &data)) 1010 return -EINVAL; 1011 1012 if (kvm_vcpu_write_guest(vcpu, 1013 gpa + i * sizeof(e) + 1014 offsetof(struct vmx_msr_entry, value), 1015 &data, sizeof(data))) { 1016 pr_debug_ratelimited( 1017 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", 1018 __func__, i, e.index, data); 1019 return -EINVAL; 1020 } 1021 } 1022 return 0; 1023 } 1024 1025 static bool nested_msr_store_list_has_msr(struct kvm_vcpu *vcpu, u32 msr_index) 1026 { 1027 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1028 u32 count = vmcs12->vm_exit_msr_store_count; 1029 u64 gpa = vmcs12->vm_exit_msr_store_addr; 1030 struct vmx_msr_entry e; 1031 u32 i; 1032 1033 for (i = 0; i < count; i++) { 1034 if (!read_and_check_msr_entry(vcpu, gpa, i, &e)) 1035 return false; 1036 1037 if (e.index == msr_index) 1038 return true; 1039 } 1040 return false; 1041 } 1042 1043 static void prepare_vmx_msr_autostore_list(struct kvm_vcpu *vcpu, 1044 u32 msr_index) 1045 { 1046 struct vcpu_vmx *vmx = to_vmx(vcpu); 1047 struct vmx_msrs *autostore = &vmx->msr_autostore.guest; 1048 bool in_vmcs12_store_list; 1049 int msr_autostore_slot; 1050 bool in_autostore_list; 1051 int last; 1052 1053 msr_autostore_slot = vmx_find_loadstore_msr_slot(autostore, msr_index); 1054 in_autostore_list = msr_autostore_slot >= 0; 1055 in_vmcs12_store_list = nested_msr_store_list_has_msr(vcpu, msr_index); 1056 1057 if (in_vmcs12_store_list && !in_autostore_list) { 1058 if (autostore->nr == MAX_NR_LOADSTORE_MSRS) { 1059 /* 1060 * Emulated VMEntry does not fail here. Instead a less 1061 * accurate value will be returned by 1062 * nested_vmx_get_vmexit_msr_value() using kvm_get_msr() 1063 * instead of reading the value from the vmcs02 VMExit 1064 * MSR-store area. 1065 */ 1066 pr_warn_ratelimited( 1067 "Not enough msr entries in msr_autostore. Can't add msr %x\n", 1068 msr_index); 1069 return; 1070 } 1071 last = autostore->nr++; 1072 autostore->val[last].index = msr_index; 1073 } else if (!in_vmcs12_store_list && in_autostore_list) { 1074 last = --autostore->nr; 1075 autostore->val[msr_autostore_slot] = autostore->val[last]; 1076 } 1077 } 1078 1079 /* 1080 * Load guest's/host's cr3 at nested entry/exit. @nested_ept is true if we are 1081 * emulating VM-Entry into a guest with EPT enabled. On failure, the expected 1082 * Exit Qualification (for a VM-Entry consistency check VM-Exit) is assigned to 1083 * @entry_failure_code. 1084 */ 1085 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, 1086 bool nested_ept, bool reload_pdptrs, 1087 enum vm_entry_failure_code *entry_failure_code) 1088 { 1089 if (CC(kvm_vcpu_is_illegal_gpa(vcpu, cr3))) { 1090 *entry_failure_code = ENTRY_FAIL_DEFAULT; 1091 return -EINVAL; 1092 } 1093 1094 /* 1095 * If PAE paging and EPT are both on, CR3 is not used by the CPU and 1096 * must not be dereferenced. 1097 */ 1098 if (reload_pdptrs && !nested_ept && is_pae_paging(vcpu) && 1099 CC(!load_pdptrs(vcpu, cr3))) { 1100 *entry_failure_code = ENTRY_FAIL_PDPTE; 1101 return -EINVAL; 1102 } 1103 1104 vcpu->arch.cr3 = cr3; 1105 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 1106 1107 /* Re-initialize the MMU, e.g. to pick up CR4 MMU role changes. */ 1108 kvm_init_mmu(vcpu); 1109 1110 if (!nested_ept) 1111 kvm_mmu_new_pgd(vcpu, cr3); 1112 1113 return 0; 1114 } 1115 1116 /* 1117 * Returns if KVM is able to config CPU to tag TLB entries 1118 * populated by L2 differently than TLB entries populated 1119 * by L1. 1120 * 1121 * If L0 uses EPT, L1 and L2 run with different EPTP because 1122 * guest_mode is part of kvm_mmu_page_role. Thus, TLB entries 1123 * are tagged with different EPTP. 1124 * 1125 * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged 1126 * with different VPID (L1 entries are tagged with vmx->vpid 1127 * while L2 entries are tagged with vmx->nested.vpid02). 1128 */ 1129 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu) 1130 { 1131 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1132 1133 return enable_ept || 1134 (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02); 1135 } 1136 1137 static void nested_vmx_transition_tlb_flush(struct kvm_vcpu *vcpu, 1138 struct vmcs12 *vmcs12, 1139 bool is_vmenter) 1140 { 1141 struct vcpu_vmx *vmx = to_vmx(vcpu); 1142 1143 /* 1144 * KVM_REQ_HV_TLB_FLUSH flushes entries from either L1's VP_ID or 1145 * L2's VP_ID upon request from the guest. Make sure we check for 1146 * pending entries in the right FIFO upon L1/L2 transition as these 1147 * requests are put by other vCPUs asynchronously. 1148 */ 1149 if (to_hv_vcpu(vcpu) && enable_ept) 1150 kvm_make_request(KVM_REQ_HV_TLB_FLUSH, vcpu); 1151 1152 /* 1153 * If VPID is disabled, then guest TLB accesses use VPID=0, i.e. the 1154 * same VPID as the host, and so architecturally, linear and combined 1155 * mappings for VPID=0 must be flushed at VM-Enter and VM-Exit. KVM 1156 * emulates L2 sharing L1's VPID=0 by using vpid01 while running L2, 1157 * and so KVM must also emulate TLB flush of VPID=0, i.e. vpid01. This 1158 * is required if VPID is disabled in KVM, as a TLB flush (there are no 1159 * VPIDs) still occurs from L1's perspective, and KVM may need to 1160 * synchronize the MMU in response to the guest TLB flush. 1161 * 1162 * Note, using TLB_FLUSH_GUEST is correct even if nested EPT is in use. 1163 * EPT is a special snowflake, as guest-physical mappings aren't 1164 * flushed on VPID invalidations, including VM-Enter or VM-Exit with 1165 * VPID disabled. As a result, KVM _never_ needs to sync nEPT 1166 * entries on VM-Enter because L1 can't rely on VM-Enter to flush 1167 * those mappings. 1168 */ 1169 if (!nested_cpu_has_vpid(vmcs12)) { 1170 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1171 return; 1172 } 1173 1174 /* L2 should never have a VPID if VPID is disabled. */ 1175 WARN_ON(!enable_vpid); 1176 1177 /* 1178 * VPID is enabled and in use by vmcs12. If vpid12 is changing, then 1179 * emulate a guest TLB flush as KVM does not track vpid12 history nor 1180 * is the VPID incorporated into the MMU context. I.e. KVM must assume 1181 * that the new vpid12 has never been used and thus represents a new 1182 * guest ASID that cannot have entries in the TLB. 1183 */ 1184 if (is_vmenter && vmcs12->virtual_processor_id != vmx->nested.last_vpid) { 1185 vmx->nested.last_vpid = vmcs12->virtual_processor_id; 1186 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1187 return; 1188 } 1189 1190 /* 1191 * If VPID is enabled, used by vmc12, and vpid12 is not changing but 1192 * does not have a unique TLB tag (ASID), i.e. EPT is disabled and 1193 * KVM was unable to allocate a VPID for L2, flush the current context 1194 * as the effective ASID is common to both L1 and L2. 1195 */ 1196 if (!nested_has_guest_tlb_tag(vcpu)) 1197 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1198 } 1199 1200 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) 1201 { 1202 superset &= mask; 1203 subset &= mask; 1204 1205 return (superset | subset) == superset; 1206 } 1207 1208 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) 1209 { 1210 const u64 feature_and_reserved = 1211 /* feature (except bit 48; see below) */ 1212 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | 1213 /* reserved */ 1214 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); 1215 u64 vmx_basic = vmcs_config.nested.basic; 1216 1217 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) 1218 return -EINVAL; 1219 1220 /* 1221 * KVM does not emulate a version of VMX that constrains physical 1222 * addresses of VMX structures (e.g. VMCS) to 32-bits. 1223 */ 1224 if (data & BIT_ULL(48)) 1225 return -EINVAL; 1226 1227 if (vmx_basic_vmcs_revision_id(vmx_basic) != 1228 vmx_basic_vmcs_revision_id(data)) 1229 return -EINVAL; 1230 1231 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) 1232 return -EINVAL; 1233 1234 vmx->nested.msrs.basic = data; 1235 return 0; 1236 } 1237 1238 static void vmx_get_control_msr(struct nested_vmx_msrs *msrs, u32 msr_index, 1239 u32 **low, u32 **high) 1240 { 1241 switch (msr_index) { 1242 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1243 *low = &msrs->pinbased_ctls_low; 1244 *high = &msrs->pinbased_ctls_high; 1245 break; 1246 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1247 *low = &msrs->procbased_ctls_low; 1248 *high = &msrs->procbased_ctls_high; 1249 break; 1250 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1251 *low = &msrs->exit_ctls_low; 1252 *high = &msrs->exit_ctls_high; 1253 break; 1254 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1255 *low = &msrs->entry_ctls_low; 1256 *high = &msrs->entry_ctls_high; 1257 break; 1258 case MSR_IA32_VMX_PROCBASED_CTLS2: 1259 *low = &msrs->secondary_ctls_low; 1260 *high = &msrs->secondary_ctls_high; 1261 break; 1262 default: 1263 BUG(); 1264 } 1265 } 1266 1267 static int 1268 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) 1269 { 1270 u32 *lowp, *highp; 1271 u64 supported; 1272 1273 vmx_get_control_msr(&vmcs_config.nested, msr_index, &lowp, &highp); 1274 1275 supported = vmx_control_msr(*lowp, *highp); 1276 1277 /* Check must-be-1 bits are still 1. */ 1278 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) 1279 return -EINVAL; 1280 1281 /* Check must-be-0 bits are still 0. */ 1282 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) 1283 return -EINVAL; 1284 1285 vmx_get_control_msr(&vmx->nested.msrs, msr_index, &lowp, &highp); 1286 *lowp = data; 1287 *highp = data >> 32; 1288 return 0; 1289 } 1290 1291 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) 1292 { 1293 const u64 feature_and_reserved_bits = 1294 /* feature */ 1295 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | 1296 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | 1297 /* reserved */ 1298 GENMASK_ULL(13, 9) | BIT_ULL(31); 1299 u64 vmx_misc = vmx_control_msr(vmcs_config.nested.misc_low, 1300 vmcs_config.nested.misc_high); 1301 1302 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) 1303 return -EINVAL; 1304 1305 if ((vmx->nested.msrs.pinbased_ctls_high & 1306 PIN_BASED_VMX_PREEMPTION_TIMER) && 1307 vmx_misc_preemption_timer_rate(data) != 1308 vmx_misc_preemption_timer_rate(vmx_misc)) 1309 return -EINVAL; 1310 1311 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) 1312 return -EINVAL; 1313 1314 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) 1315 return -EINVAL; 1316 1317 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) 1318 return -EINVAL; 1319 1320 vmx->nested.msrs.misc_low = data; 1321 vmx->nested.msrs.misc_high = data >> 32; 1322 1323 return 0; 1324 } 1325 1326 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) 1327 { 1328 u64 vmx_ept_vpid_cap = vmx_control_msr(vmcs_config.nested.ept_caps, 1329 vmcs_config.nested.vpid_caps); 1330 1331 /* Every bit is either reserved or a feature bit. */ 1332 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) 1333 return -EINVAL; 1334 1335 vmx->nested.msrs.ept_caps = data; 1336 vmx->nested.msrs.vpid_caps = data >> 32; 1337 return 0; 1338 } 1339 1340 static u64 *vmx_get_fixed0_msr(struct nested_vmx_msrs *msrs, u32 msr_index) 1341 { 1342 switch (msr_index) { 1343 case MSR_IA32_VMX_CR0_FIXED0: 1344 return &msrs->cr0_fixed0; 1345 case MSR_IA32_VMX_CR4_FIXED0: 1346 return &msrs->cr4_fixed0; 1347 default: 1348 BUG(); 1349 } 1350 } 1351 1352 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) 1353 { 1354 const u64 *msr = vmx_get_fixed0_msr(&vmcs_config.nested, msr_index); 1355 1356 /* 1357 * 1 bits (which indicates bits which "must-be-1" during VMX operation) 1358 * must be 1 in the restored value. 1359 */ 1360 if (!is_bitwise_subset(data, *msr, -1ULL)) 1361 return -EINVAL; 1362 1363 *vmx_get_fixed0_msr(&vmx->nested.msrs, msr_index) = data; 1364 return 0; 1365 } 1366 1367 /* 1368 * Called when userspace is restoring VMX MSRs. 1369 * 1370 * Returns 0 on success, non-0 otherwise. 1371 */ 1372 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) 1373 { 1374 struct vcpu_vmx *vmx = to_vmx(vcpu); 1375 1376 /* 1377 * Don't allow changes to the VMX capability MSRs while the vCPU 1378 * is in VMX operation. 1379 */ 1380 if (vmx->nested.vmxon) 1381 return -EBUSY; 1382 1383 switch (msr_index) { 1384 case MSR_IA32_VMX_BASIC: 1385 return vmx_restore_vmx_basic(vmx, data); 1386 case MSR_IA32_VMX_PINBASED_CTLS: 1387 case MSR_IA32_VMX_PROCBASED_CTLS: 1388 case MSR_IA32_VMX_EXIT_CTLS: 1389 case MSR_IA32_VMX_ENTRY_CTLS: 1390 /* 1391 * The "non-true" VMX capability MSRs are generated from the 1392 * "true" MSRs, so we do not support restoring them directly. 1393 * 1394 * If userspace wants to emulate VMX_BASIC[55]=0, userspace 1395 * should restore the "true" MSRs with the must-be-1 bits 1396 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND 1397 * DEFAULT SETTINGS". 1398 */ 1399 return -EINVAL; 1400 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1401 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1402 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1403 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1404 case MSR_IA32_VMX_PROCBASED_CTLS2: 1405 return vmx_restore_control_msr(vmx, msr_index, data); 1406 case MSR_IA32_VMX_MISC: 1407 return vmx_restore_vmx_misc(vmx, data); 1408 case MSR_IA32_VMX_CR0_FIXED0: 1409 case MSR_IA32_VMX_CR4_FIXED0: 1410 return vmx_restore_fixed0_msr(vmx, msr_index, data); 1411 case MSR_IA32_VMX_CR0_FIXED1: 1412 case MSR_IA32_VMX_CR4_FIXED1: 1413 /* 1414 * These MSRs are generated based on the vCPU's CPUID, so we 1415 * do not support restoring them directly. 1416 */ 1417 return -EINVAL; 1418 case MSR_IA32_VMX_EPT_VPID_CAP: 1419 return vmx_restore_vmx_ept_vpid_cap(vmx, data); 1420 case MSR_IA32_VMX_VMCS_ENUM: 1421 vmx->nested.msrs.vmcs_enum = data; 1422 return 0; 1423 case MSR_IA32_VMX_VMFUNC: 1424 if (data & ~vmcs_config.nested.vmfunc_controls) 1425 return -EINVAL; 1426 vmx->nested.msrs.vmfunc_controls = data; 1427 return 0; 1428 default: 1429 /* 1430 * The rest of the VMX capability MSRs do not support restore. 1431 */ 1432 return -EINVAL; 1433 } 1434 } 1435 1436 /* Returns 0 on success, non-0 otherwise. */ 1437 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata) 1438 { 1439 switch (msr_index) { 1440 case MSR_IA32_VMX_BASIC: 1441 *pdata = msrs->basic; 1442 break; 1443 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1444 case MSR_IA32_VMX_PINBASED_CTLS: 1445 *pdata = vmx_control_msr( 1446 msrs->pinbased_ctls_low, 1447 msrs->pinbased_ctls_high); 1448 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) 1449 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 1450 break; 1451 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1452 case MSR_IA32_VMX_PROCBASED_CTLS: 1453 *pdata = vmx_control_msr( 1454 msrs->procbased_ctls_low, 1455 msrs->procbased_ctls_high); 1456 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) 1457 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 1458 break; 1459 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1460 case MSR_IA32_VMX_EXIT_CTLS: 1461 *pdata = vmx_control_msr( 1462 msrs->exit_ctls_low, 1463 msrs->exit_ctls_high); 1464 if (msr_index == MSR_IA32_VMX_EXIT_CTLS) 1465 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; 1466 break; 1467 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1468 case MSR_IA32_VMX_ENTRY_CTLS: 1469 *pdata = vmx_control_msr( 1470 msrs->entry_ctls_low, 1471 msrs->entry_ctls_high); 1472 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) 1473 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; 1474 break; 1475 case MSR_IA32_VMX_MISC: 1476 *pdata = vmx_control_msr( 1477 msrs->misc_low, 1478 msrs->misc_high); 1479 break; 1480 case MSR_IA32_VMX_CR0_FIXED0: 1481 *pdata = msrs->cr0_fixed0; 1482 break; 1483 case MSR_IA32_VMX_CR0_FIXED1: 1484 *pdata = msrs->cr0_fixed1; 1485 break; 1486 case MSR_IA32_VMX_CR4_FIXED0: 1487 *pdata = msrs->cr4_fixed0; 1488 break; 1489 case MSR_IA32_VMX_CR4_FIXED1: 1490 *pdata = msrs->cr4_fixed1; 1491 break; 1492 case MSR_IA32_VMX_VMCS_ENUM: 1493 *pdata = msrs->vmcs_enum; 1494 break; 1495 case MSR_IA32_VMX_PROCBASED_CTLS2: 1496 *pdata = vmx_control_msr( 1497 msrs->secondary_ctls_low, 1498 msrs->secondary_ctls_high); 1499 break; 1500 case MSR_IA32_VMX_EPT_VPID_CAP: 1501 *pdata = msrs->ept_caps | 1502 ((u64)msrs->vpid_caps << 32); 1503 break; 1504 case MSR_IA32_VMX_VMFUNC: 1505 *pdata = msrs->vmfunc_controls; 1506 break; 1507 default: 1508 return 1; 1509 } 1510 1511 return 0; 1512 } 1513 1514 /* 1515 * Copy the writable VMCS shadow fields back to the VMCS12, in case they have 1516 * been modified by the L1 guest. Note, "writable" in this context means 1517 * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of 1518 * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only" 1519 * VM-exit information fields (which are actually writable if the vCPU is 1520 * configured to support "VMWRITE to any supported field in the VMCS"). 1521 */ 1522 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) 1523 { 1524 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; 1525 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu); 1526 struct shadow_vmcs_field field; 1527 unsigned long val; 1528 int i; 1529 1530 if (WARN_ON(!shadow_vmcs)) 1531 return; 1532 1533 preempt_disable(); 1534 1535 vmcs_load(shadow_vmcs); 1536 1537 for (i = 0; i < max_shadow_read_write_fields; i++) { 1538 field = shadow_read_write_fields[i]; 1539 val = __vmcs_readl(field.encoding); 1540 vmcs12_write_any(vmcs12, field.encoding, field.offset, val); 1541 } 1542 1543 vmcs_clear(shadow_vmcs); 1544 vmcs_load(vmx->loaded_vmcs->vmcs); 1545 1546 preempt_enable(); 1547 } 1548 1549 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) 1550 { 1551 const struct shadow_vmcs_field *fields[] = { 1552 shadow_read_write_fields, 1553 shadow_read_only_fields 1554 }; 1555 const int max_fields[] = { 1556 max_shadow_read_write_fields, 1557 max_shadow_read_only_fields 1558 }; 1559 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; 1560 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu); 1561 struct shadow_vmcs_field field; 1562 unsigned long val; 1563 int i, q; 1564 1565 if (WARN_ON(!shadow_vmcs)) 1566 return; 1567 1568 vmcs_load(shadow_vmcs); 1569 1570 for (q = 0; q < ARRAY_SIZE(fields); q++) { 1571 for (i = 0; i < max_fields[q]; i++) { 1572 field = fields[q][i]; 1573 val = vmcs12_read_any(vmcs12, field.encoding, 1574 field.offset); 1575 __vmcs_writel(field.encoding, val); 1576 } 1577 } 1578 1579 vmcs_clear(shadow_vmcs); 1580 vmcs_load(vmx->loaded_vmcs->vmcs); 1581 } 1582 1583 static void copy_enlightened_to_vmcs12(struct vcpu_vmx *vmx, u32 hv_clean_fields) 1584 { 1585 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12; 1586 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs; 1587 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(&vmx->vcpu); 1588 1589 /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */ 1590 vmcs12->tpr_threshold = evmcs->tpr_threshold; 1591 vmcs12->guest_rip = evmcs->guest_rip; 1592 1593 if (unlikely(!(hv_clean_fields & 1594 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL))) { 1595 hv_vcpu->nested.pa_page_gpa = evmcs->partition_assist_page; 1596 hv_vcpu->nested.vm_id = evmcs->hv_vm_id; 1597 hv_vcpu->nested.vp_id = evmcs->hv_vp_id; 1598 } 1599 1600 if (unlikely(!(hv_clean_fields & 1601 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC))) { 1602 vmcs12->guest_rsp = evmcs->guest_rsp; 1603 vmcs12->guest_rflags = evmcs->guest_rflags; 1604 vmcs12->guest_interruptibility_info = 1605 evmcs->guest_interruptibility_info; 1606 /* 1607 * Not present in struct vmcs12: 1608 * vmcs12->guest_ssp = evmcs->guest_ssp; 1609 */ 1610 } 1611 1612 if (unlikely(!(hv_clean_fields & 1613 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC))) { 1614 vmcs12->cpu_based_vm_exec_control = 1615 evmcs->cpu_based_vm_exec_control; 1616 } 1617 1618 if (unlikely(!(hv_clean_fields & 1619 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN))) { 1620 vmcs12->exception_bitmap = evmcs->exception_bitmap; 1621 } 1622 1623 if (unlikely(!(hv_clean_fields & 1624 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY))) { 1625 vmcs12->vm_entry_controls = evmcs->vm_entry_controls; 1626 } 1627 1628 if (unlikely(!(hv_clean_fields & 1629 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT))) { 1630 vmcs12->vm_entry_intr_info_field = 1631 evmcs->vm_entry_intr_info_field; 1632 vmcs12->vm_entry_exception_error_code = 1633 evmcs->vm_entry_exception_error_code; 1634 vmcs12->vm_entry_instruction_len = 1635 evmcs->vm_entry_instruction_len; 1636 } 1637 1638 if (unlikely(!(hv_clean_fields & 1639 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1))) { 1640 vmcs12->host_ia32_pat = evmcs->host_ia32_pat; 1641 vmcs12->host_ia32_efer = evmcs->host_ia32_efer; 1642 vmcs12->host_cr0 = evmcs->host_cr0; 1643 vmcs12->host_cr3 = evmcs->host_cr3; 1644 vmcs12->host_cr4 = evmcs->host_cr4; 1645 vmcs12->host_ia32_sysenter_esp = evmcs->host_ia32_sysenter_esp; 1646 vmcs12->host_ia32_sysenter_eip = evmcs->host_ia32_sysenter_eip; 1647 vmcs12->host_rip = evmcs->host_rip; 1648 vmcs12->host_ia32_sysenter_cs = evmcs->host_ia32_sysenter_cs; 1649 vmcs12->host_es_selector = evmcs->host_es_selector; 1650 vmcs12->host_cs_selector = evmcs->host_cs_selector; 1651 vmcs12->host_ss_selector = evmcs->host_ss_selector; 1652 vmcs12->host_ds_selector = evmcs->host_ds_selector; 1653 vmcs12->host_fs_selector = evmcs->host_fs_selector; 1654 vmcs12->host_gs_selector = evmcs->host_gs_selector; 1655 vmcs12->host_tr_selector = evmcs->host_tr_selector; 1656 vmcs12->host_ia32_perf_global_ctrl = evmcs->host_ia32_perf_global_ctrl; 1657 /* 1658 * Not present in struct vmcs12: 1659 * vmcs12->host_ia32_s_cet = evmcs->host_ia32_s_cet; 1660 * vmcs12->host_ssp = evmcs->host_ssp; 1661 * vmcs12->host_ia32_int_ssp_table_addr = evmcs->host_ia32_int_ssp_table_addr; 1662 */ 1663 } 1664 1665 if (unlikely(!(hv_clean_fields & 1666 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1))) { 1667 vmcs12->pin_based_vm_exec_control = 1668 evmcs->pin_based_vm_exec_control; 1669 vmcs12->vm_exit_controls = evmcs->vm_exit_controls; 1670 vmcs12->secondary_vm_exec_control = 1671 evmcs->secondary_vm_exec_control; 1672 } 1673 1674 if (unlikely(!(hv_clean_fields & 1675 HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP))) { 1676 vmcs12->io_bitmap_a = evmcs->io_bitmap_a; 1677 vmcs12->io_bitmap_b = evmcs->io_bitmap_b; 1678 } 1679 1680 if (unlikely(!(hv_clean_fields & 1681 HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP))) { 1682 vmcs12->msr_bitmap = evmcs->msr_bitmap; 1683 } 1684 1685 if (unlikely(!(hv_clean_fields & 1686 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2))) { 1687 vmcs12->guest_es_base = evmcs->guest_es_base; 1688 vmcs12->guest_cs_base = evmcs->guest_cs_base; 1689 vmcs12->guest_ss_base = evmcs->guest_ss_base; 1690 vmcs12->guest_ds_base = evmcs->guest_ds_base; 1691 vmcs12->guest_fs_base = evmcs->guest_fs_base; 1692 vmcs12->guest_gs_base = evmcs->guest_gs_base; 1693 vmcs12->guest_ldtr_base = evmcs->guest_ldtr_base; 1694 vmcs12->guest_tr_base = evmcs->guest_tr_base; 1695 vmcs12->guest_gdtr_base = evmcs->guest_gdtr_base; 1696 vmcs12->guest_idtr_base = evmcs->guest_idtr_base; 1697 vmcs12->guest_es_limit = evmcs->guest_es_limit; 1698 vmcs12->guest_cs_limit = evmcs->guest_cs_limit; 1699 vmcs12->guest_ss_limit = evmcs->guest_ss_limit; 1700 vmcs12->guest_ds_limit = evmcs->guest_ds_limit; 1701 vmcs12->guest_fs_limit = evmcs->guest_fs_limit; 1702 vmcs12->guest_gs_limit = evmcs->guest_gs_limit; 1703 vmcs12->guest_ldtr_limit = evmcs->guest_ldtr_limit; 1704 vmcs12->guest_tr_limit = evmcs->guest_tr_limit; 1705 vmcs12->guest_gdtr_limit = evmcs->guest_gdtr_limit; 1706 vmcs12->guest_idtr_limit = evmcs->guest_idtr_limit; 1707 vmcs12->guest_es_ar_bytes = evmcs->guest_es_ar_bytes; 1708 vmcs12->guest_cs_ar_bytes = evmcs->guest_cs_ar_bytes; 1709 vmcs12->guest_ss_ar_bytes = evmcs->guest_ss_ar_bytes; 1710 vmcs12->guest_ds_ar_bytes = evmcs->guest_ds_ar_bytes; 1711 vmcs12->guest_fs_ar_bytes = evmcs->guest_fs_ar_bytes; 1712 vmcs12->guest_gs_ar_bytes = evmcs->guest_gs_ar_bytes; 1713 vmcs12->guest_ldtr_ar_bytes = evmcs->guest_ldtr_ar_bytes; 1714 vmcs12->guest_tr_ar_bytes = evmcs->guest_tr_ar_bytes; 1715 vmcs12->guest_es_selector = evmcs->guest_es_selector; 1716 vmcs12->guest_cs_selector = evmcs->guest_cs_selector; 1717 vmcs12->guest_ss_selector = evmcs->guest_ss_selector; 1718 vmcs12->guest_ds_selector = evmcs->guest_ds_selector; 1719 vmcs12->guest_fs_selector = evmcs->guest_fs_selector; 1720 vmcs12->guest_gs_selector = evmcs->guest_gs_selector; 1721 vmcs12->guest_ldtr_selector = evmcs->guest_ldtr_selector; 1722 vmcs12->guest_tr_selector = evmcs->guest_tr_selector; 1723 } 1724 1725 if (unlikely(!(hv_clean_fields & 1726 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2))) { 1727 vmcs12->tsc_offset = evmcs->tsc_offset; 1728 vmcs12->virtual_apic_page_addr = evmcs->virtual_apic_page_addr; 1729 vmcs12->xss_exit_bitmap = evmcs->xss_exit_bitmap; 1730 vmcs12->encls_exiting_bitmap = evmcs->encls_exiting_bitmap; 1731 vmcs12->tsc_multiplier = evmcs->tsc_multiplier; 1732 } 1733 1734 if (unlikely(!(hv_clean_fields & 1735 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR))) { 1736 vmcs12->cr0_guest_host_mask = evmcs->cr0_guest_host_mask; 1737 vmcs12->cr4_guest_host_mask = evmcs->cr4_guest_host_mask; 1738 vmcs12->cr0_read_shadow = evmcs->cr0_read_shadow; 1739 vmcs12->cr4_read_shadow = evmcs->cr4_read_shadow; 1740 vmcs12->guest_cr0 = evmcs->guest_cr0; 1741 vmcs12->guest_cr3 = evmcs->guest_cr3; 1742 vmcs12->guest_cr4 = evmcs->guest_cr4; 1743 vmcs12->guest_dr7 = evmcs->guest_dr7; 1744 } 1745 1746 if (unlikely(!(hv_clean_fields & 1747 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER))) { 1748 vmcs12->host_fs_base = evmcs->host_fs_base; 1749 vmcs12->host_gs_base = evmcs->host_gs_base; 1750 vmcs12->host_tr_base = evmcs->host_tr_base; 1751 vmcs12->host_gdtr_base = evmcs->host_gdtr_base; 1752 vmcs12->host_idtr_base = evmcs->host_idtr_base; 1753 vmcs12->host_rsp = evmcs->host_rsp; 1754 } 1755 1756 if (unlikely(!(hv_clean_fields & 1757 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT))) { 1758 vmcs12->ept_pointer = evmcs->ept_pointer; 1759 vmcs12->virtual_processor_id = evmcs->virtual_processor_id; 1760 } 1761 1762 if (unlikely(!(hv_clean_fields & 1763 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1))) { 1764 vmcs12->vmcs_link_pointer = evmcs->vmcs_link_pointer; 1765 vmcs12->guest_ia32_debugctl = evmcs->guest_ia32_debugctl; 1766 vmcs12->guest_ia32_pat = evmcs->guest_ia32_pat; 1767 vmcs12->guest_ia32_efer = evmcs->guest_ia32_efer; 1768 vmcs12->guest_pdptr0 = evmcs->guest_pdptr0; 1769 vmcs12->guest_pdptr1 = evmcs->guest_pdptr1; 1770 vmcs12->guest_pdptr2 = evmcs->guest_pdptr2; 1771 vmcs12->guest_pdptr3 = evmcs->guest_pdptr3; 1772 vmcs12->guest_pending_dbg_exceptions = 1773 evmcs->guest_pending_dbg_exceptions; 1774 vmcs12->guest_sysenter_esp = evmcs->guest_sysenter_esp; 1775 vmcs12->guest_sysenter_eip = evmcs->guest_sysenter_eip; 1776 vmcs12->guest_bndcfgs = evmcs->guest_bndcfgs; 1777 vmcs12->guest_activity_state = evmcs->guest_activity_state; 1778 vmcs12->guest_sysenter_cs = evmcs->guest_sysenter_cs; 1779 vmcs12->guest_ia32_perf_global_ctrl = evmcs->guest_ia32_perf_global_ctrl; 1780 /* 1781 * Not present in struct vmcs12: 1782 * vmcs12->guest_ia32_s_cet = evmcs->guest_ia32_s_cet; 1783 * vmcs12->guest_ia32_lbr_ctl = evmcs->guest_ia32_lbr_ctl; 1784 * vmcs12->guest_ia32_int_ssp_table_addr = evmcs->guest_ia32_int_ssp_table_addr; 1785 */ 1786 } 1787 1788 /* 1789 * Not used? 1790 * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr; 1791 * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr; 1792 * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr; 1793 * vmcs12->page_fault_error_code_mask = 1794 * evmcs->page_fault_error_code_mask; 1795 * vmcs12->page_fault_error_code_match = 1796 * evmcs->page_fault_error_code_match; 1797 * vmcs12->cr3_target_count = evmcs->cr3_target_count; 1798 * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count; 1799 * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count; 1800 * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count; 1801 */ 1802 1803 /* 1804 * Read only fields: 1805 * vmcs12->guest_physical_address = evmcs->guest_physical_address; 1806 * vmcs12->vm_instruction_error = evmcs->vm_instruction_error; 1807 * vmcs12->vm_exit_reason = evmcs->vm_exit_reason; 1808 * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info; 1809 * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code; 1810 * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field; 1811 * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code; 1812 * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len; 1813 * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info; 1814 * vmcs12->exit_qualification = evmcs->exit_qualification; 1815 * vmcs12->guest_linear_address = evmcs->guest_linear_address; 1816 * 1817 * Not present in struct vmcs12: 1818 * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx; 1819 * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi; 1820 * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi; 1821 * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip; 1822 */ 1823 1824 return; 1825 } 1826 1827 static void copy_vmcs12_to_enlightened(struct vcpu_vmx *vmx) 1828 { 1829 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12; 1830 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs; 1831 1832 /* 1833 * Should not be changed by KVM: 1834 * 1835 * evmcs->host_es_selector = vmcs12->host_es_selector; 1836 * evmcs->host_cs_selector = vmcs12->host_cs_selector; 1837 * evmcs->host_ss_selector = vmcs12->host_ss_selector; 1838 * evmcs->host_ds_selector = vmcs12->host_ds_selector; 1839 * evmcs->host_fs_selector = vmcs12->host_fs_selector; 1840 * evmcs->host_gs_selector = vmcs12->host_gs_selector; 1841 * evmcs->host_tr_selector = vmcs12->host_tr_selector; 1842 * evmcs->host_ia32_pat = vmcs12->host_ia32_pat; 1843 * evmcs->host_ia32_efer = vmcs12->host_ia32_efer; 1844 * evmcs->host_cr0 = vmcs12->host_cr0; 1845 * evmcs->host_cr3 = vmcs12->host_cr3; 1846 * evmcs->host_cr4 = vmcs12->host_cr4; 1847 * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp; 1848 * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip; 1849 * evmcs->host_rip = vmcs12->host_rip; 1850 * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs; 1851 * evmcs->host_fs_base = vmcs12->host_fs_base; 1852 * evmcs->host_gs_base = vmcs12->host_gs_base; 1853 * evmcs->host_tr_base = vmcs12->host_tr_base; 1854 * evmcs->host_gdtr_base = vmcs12->host_gdtr_base; 1855 * evmcs->host_idtr_base = vmcs12->host_idtr_base; 1856 * evmcs->host_rsp = vmcs12->host_rsp; 1857 * sync_vmcs02_to_vmcs12() doesn't read these: 1858 * evmcs->io_bitmap_a = vmcs12->io_bitmap_a; 1859 * evmcs->io_bitmap_b = vmcs12->io_bitmap_b; 1860 * evmcs->msr_bitmap = vmcs12->msr_bitmap; 1861 * evmcs->ept_pointer = vmcs12->ept_pointer; 1862 * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap; 1863 * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr; 1864 * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr; 1865 * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr; 1866 * evmcs->tpr_threshold = vmcs12->tpr_threshold; 1867 * evmcs->virtual_processor_id = vmcs12->virtual_processor_id; 1868 * evmcs->exception_bitmap = vmcs12->exception_bitmap; 1869 * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer; 1870 * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control; 1871 * evmcs->vm_exit_controls = vmcs12->vm_exit_controls; 1872 * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control; 1873 * evmcs->page_fault_error_code_mask = 1874 * vmcs12->page_fault_error_code_mask; 1875 * evmcs->page_fault_error_code_match = 1876 * vmcs12->page_fault_error_code_match; 1877 * evmcs->cr3_target_count = vmcs12->cr3_target_count; 1878 * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr; 1879 * evmcs->tsc_offset = vmcs12->tsc_offset; 1880 * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl; 1881 * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask; 1882 * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask; 1883 * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow; 1884 * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow; 1885 * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count; 1886 * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count; 1887 * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count; 1888 * evmcs->guest_ia32_perf_global_ctrl = vmcs12->guest_ia32_perf_global_ctrl; 1889 * evmcs->host_ia32_perf_global_ctrl = vmcs12->host_ia32_perf_global_ctrl; 1890 * evmcs->encls_exiting_bitmap = vmcs12->encls_exiting_bitmap; 1891 * evmcs->tsc_multiplier = vmcs12->tsc_multiplier; 1892 * 1893 * Not present in struct vmcs12: 1894 * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx; 1895 * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi; 1896 * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi; 1897 * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip; 1898 * evmcs->host_ia32_s_cet = vmcs12->host_ia32_s_cet; 1899 * evmcs->host_ssp = vmcs12->host_ssp; 1900 * evmcs->host_ia32_int_ssp_table_addr = vmcs12->host_ia32_int_ssp_table_addr; 1901 * evmcs->guest_ia32_s_cet = vmcs12->guest_ia32_s_cet; 1902 * evmcs->guest_ia32_lbr_ctl = vmcs12->guest_ia32_lbr_ctl; 1903 * evmcs->guest_ia32_int_ssp_table_addr = vmcs12->guest_ia32_int_ssp_table_addr; 1904 * evmcs->guest_ssp = vmcs12->guest_ssp; 1905 */ 1906 1907 evmcs->guest_es_selector = vmcs12->guest_es_selector; 1908 evmcs->guest_cs_selector = vmcs12->guest_cs_selector; 1909 evmcs->guest_ss_selector = vmcs12->guest_ss_selector; 1910 evmcs->guest_ds_selector = vmcs12->guest_ds_selector; 1911 evmcs->guest_fs_selector = vmcs12->guest_fs_selector; 1912 evmcs->guest_gs_selector = vmcs12->guest_gs_selector; 1913 evmcs->guest_ldtr_selector = vmcs12->guest_ldtr_selector; 1914 evmcs->guest_tr_selector = vmcs12->guest_tr_selector; 1915 1916 evmcs->guest_es_limit = vmcs12->guest_es_limit; 1917 evmcs->guest_cs_limit = vmcs12->guest_cs_limit; 1918 evmcs->guest_ss_limit = vmcs12->guest_ss_limit; 1919 evmcs->guest_ds_limit = vmcs12->guest_ds_limit; 1920 evmcs->guest_fs_limit = vmcs12->guest_fs_limit; 1921 evmcs->guest_gs_limit = vmcs12->guest_gs_limit; 1922 evmcs->guest_ldtr_limit = vmcs12->guest_ldtr_limit; 1923 evmcs->guest_tr_limit = vmcs12->guest_tr_limit; 1924 evmcs->guest_gdtr_limit = vmcs12->guest_gdtr_limit; 1925 evmcs->guest_idtr_limit = vmcs12->guest_idtr_limit; 1926 1927 evmcs->guest_es_ar_bytes = vmcs12->guest_es_ar_bytes; 1928 evmcs->guest_cs_ar_bytes = vmcs12->guest_cs_ar_bytes; 1929 evmcs->guest_ss_ar_bytes = vmcs12->guest_ss_ar_bytes; 1930 evmcs->guest_ds_ar_bytes = vmcs12->guest_ds_ar_bytes; 1931 evmcs->guest_fs_ar_bytes = vmcs12->guest_fs_ar_bytes; 1932 evmcs->guest_gs_ar_bytes = vmcs12->guest_gs_ar_bytes; 1933 evmcs->guest_ldtr_ar_bytes = vmcs12->guest_ldtr_ar_bytes; 1934 evmcs->guest_tr_ar_bytes = vmcs12->guest_tr_ar_bytes; 1935 1936 evmcs->guest_es_base = vmcs12->guest_es_base; 1937 evmcs->guest_cs_base = vmcs12->guest_cs_base; 1938 evmcs->guest_ss_base = vmcs12->guest_ss_base; 1939 evmcs->guest_ds_base = vmcs12->guest_ds_base; 1940 evmcs->guest_fs_base = vmcs12->guest_fs_base; 1941 evmcs->guest_gs_base = vmcs12->guest_gs_base; 1942 evmcs->guest_ldtr_base = vmcs12->guest_ldtr_base; 1943 evmcs->guest_tr_base = vmcs12->guest_tr_base; 1944 evmcs->guest_gdtr_base = vmcs12->guest_gdtr_base; 1945 evmcs->guest_idtr_base = vmcs12->guest_idtr_base; 1946 1947 evmcs->guest_ia32_pat = vmcs12->guest_ia32_pat; 1948 evmcs->guest_ia32_efer = vmcs12->guest_ia32_efer; 1949 1950 evmcs->guest_pdptr0 = vmcs12->guest_pdptr0; 1951 evmcs->guest_pdptr1 = vmcs12->guest_pdptr1; 1952 evmcs->guest_pdptr2 = vmcs12->guest_pdptr2; 1953 evmcs->guest_pdptr3 = vmcs12->guest_pdptr3; 1954 1955 evmcs->guest_pending_dbg_exceptions = 1956 vmcs12->guest_pending_dbg_exceptions; 1957 evmcs->guest_sysenter_esp = vmcs12->guest_sysenter_esp; 1958 evmcs->guest_sysenter_eip = vmcs12->guest_sysenter_eip; 1959 1960 evmcs->guest_activity_state = vmcs12->guest_activity_state; 1961 evmcs->guest_sysenter_cs = vmcs12->guest_sysenter_cs; 1962 1963 evmcs->guest_cr0 = vmcs12->guest_cr0; 1964 evmcs->guest_cr3 = vmcs12->guest_cr3; 1965 evmcs->guest_cr4 = vmcs12->guest_cr4; 1966 evmcs->guest_dr7 = vmcs12->guest_dr7; 1967 1968 evmcs->guest_physical_address = vmcs12->guest_physical_address; 1969 1970 evmcs->vm_instruction_error = vmcs12->vm_instruction_error; 1971 evmcs->vm_exit_reason = vmcs12->vm_exit_reason; 1972 evmcs->vm_exit_intr_info = vmcs12->vm_exit_intr_info; 1973 evmcs->vm_exit_intr_error_code = vmcs12->vm_exit_intr_error_code; 1974 evmcs->idt_vectoring_info_field = vmcs12->idt_vectoring_info_field; 1975 evmcs->idt_vectoring_error_code = vmcs12->idt_vectoring_error_code; 1976 evmcs->vm_exit_instruction_len = vmcs12->vm_exit_instruction_len; 1977 evmcs->vmx_instruction_info = vmcs12->vmx_instruction_info; 1978 1979 evmcs->exit_qualification = vmcs12->exit_qualification; 1980 1981 evmcs->guest_linear_address = vmcs12->guest_linear_address; 1982 evmcs->guest_rsp = vmcs12->guest_rsp; 1983 evmcs->guest_rflags = vmcs12->guest_rflags; 1984 1985 evmcs->guest_interruptibility_info = 1986 vmcs12->guest_interruptibility_info; 1987 evmcs->cpu_based_vm_exec_control = vmcs12->cpu_based_vm_exec_control; 1988 evmcs->vm_entry_controls = vmcs12->vm_entry_controls; 1989 evmcs->vm_entry_intr_info_field = vmcs12->vm_entry_intr_info_field; 1990 evmcs->vm_entry_exception_error_code = 1991 vmcs12->vm_entry_exception_error_code; 1992 evmcs->vm_entry_instruction_len = vmcs12->vm_entry_instruction_len; 1993 1994 evmcs->guest_rip = vmcs12->guest_rip; 1995 1996 evmcs->guest_bndcfgs = vmcs12->guest_bndcfgs; 1997 1998 return; 1999 } 2000 2001 /* 2002 * This is an equivalent of the nested hypervisor executing the vmptrld 2003 * instruction. 2004 */ 2005 static enum nested_evmptrld_status nested_vmx_handle_enlightened_vmptrld( 2006 struct kvm_vcpu *vcpu, bool from_launch) 2007 { 2008 struct vcpu_vmx *vmx = to_vmx(vcpu); 2009 bool evmcs_gpa_changed = false; 2010 u64 evmcs_gpa; 2011 2012 if (likely(!guest_cpuid_has_evmcs(vcpu))) 2013 return EVMPTRLD_DISABLED; 2014 2015 evmcs_gpa = nested_get_evmptr(vcpu); 2016 if (!evmptr_is_valid(evmcs_gpa)) { 2017 nested_release_evmcs(vcpu); 2018 return EVMPTRLD_DISABLED; 2019 } 2020 2021 if (unlikely(evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) { 2022 vmx->nested.current_vmptr = INVALID_GPA; 2023 2024 nested_release_evmcs(vcpu); 2025 2026 if (kvm_vcpu_map(vcpu, gpa_to_gfn(evmcs_gpa), 2027 &vmx->nested.hv_evmcs_map)) 2028 return EVMPTRLD_ERROR; 2029 2030 vmx->nested.hv_evmcs = vmx->nested.hv_evmcs_map.hva; 2031 2032 /* 2033 * Currently, KVM only supports eVMCS version 1 2034 * (== KVM_EVMCS_VERSION) and thus we expect guest to set this 2035 * value to first u32 field of eVMCS which should specify eVMCS 2036 * VersionNumber. 2037 * 2038 * Guest should be aware of supported eVMCS versions by host by 2039 * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is 2040 * expected to set this CPUID leaf according to the value 2041 * returned in vmcs_version from nested_enable_evmcs(). 2042 * 2043 * However, it turns out that Microsoft Hyper-V fails to comply 2044 * to their own invented interface: When Hyper-V use eVMCS, it 2045 * just sets first u32 field of eVMCS to revision_id specified 2046 * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number 2047 * which is one of the supported versions specified in 2048 * CPUID.0x4000000A.EAX[0:15]. 2049 * 2050 * To overcome Hyper-V bug, we accept here either a supported 2051 * eVMCS version or VMCS12 revision_id as valid values for first 2052 * u32 field of eVMCS. 2053 */ 2054 if ((vmx->nested.hv_evmcs->revision_id != KVM_EVMCS_VERSION) && 2055 (vmx->nested.hv_evmcs->revision_id != VMCS12_REVISION)) { 2056 nested_release_evmcs(vcpu); 2057 return EVMPTRLD_VMFAIL; 2058 } 2059 2060 vmx->nested.hv_evmcs_vmptr = evmcs_gpa; 2061 2062 evmcs_gpa_changed = true; 2063 /* 2064 * Unlike normal vmcs12, enlightened vmcs12 is not fully 2065 * reloaded from guest's memory (read only fields, fields not 2066 * present in struct hv_enlightened_vmcs, ...). Make sure there 2067 * are no leftovers. 2068 */ 2069 if (from_launch) { 2070 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 2071 memset(vmcs12, 0, sizeof(*vmcs12)); 2072 vmcs12->hdr.revision_id = VMCS12_REVISION; 2073 } 2074 2075 } 2076 2077 /* 2078 * Clean fields data can't be used on VMLAUNCH and when we switch 2079 * between different L2 guests as KVM keeps a single VMCS12 per L1. 2080 */ 2081 if (from_launch || evmcs_gpa_changed) { 2082 vmx->nested.hv_evmcs->hv_clean_fields &= 2083 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 2084 2085 vmx->nested.force_msr_bitmap_recalc = true; 2086 } 2087 2088 return EVMPTRLD_SUCCEEDED; 2089 } 2090 2091 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu) 2092 { 2093 struct vcpu_vmx *vmx = to_vmx(vcpu); 2094 2095 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) 2096 copy_vmcs12_to_enlightened(vmx); 2097 else 2098 copy_vmcs12_to_shadow(vmx); 2099 2100 vmx->nested.need_vmcs12_to_shadow_sync = false; 2101 } 2102 2103 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) 2104 { 2105 struct vcpu_vmx *vmx = 2106 container_of(timer, struct vcpu_vmx, nested.preemption_timer); 2107 2108 vmx->nested.preemption_timer_expired = true; 2109 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); 2110 kvm_vcpu_kick(&vmx->vcpu); 2111 2112 return HRTIMER_NORESTART; 2113 } 2114 2115 static u64 vmx_calc_preemption_timer_value(struct kvm_vcpu *vcpu) 2116 { 2117 struct vcpu_vmx *vmx = to_vmx(vcpu); 2118 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 2119 2120 u64 l1_scaled_tsc = kvm_read_l1_tsc(vcpu, rdtsc()) >> 2121 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; 2122 2123 if (!vmx->nested.has_preemption_timer_deadline) { 2124 vmx->nested.preemption_timer_deadline = 2125 vmcs12->vmx_preemption_timer_value + l1_scaled_tsc; 2126 vmx->nested.has_preemption_timer_deadline = true; 2127 } 2128 return vmx->nested.preemption_timer_deadline - l1_scaled_tsc; 2129 } 2130 2131 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu, 2132 u64 preemption_timeout) 2133 { 2134 struct vcpu_vmx *vmx = to_vmx(vcpu); 2135 2136 /* 2137 * A timer value of zero is architecturally guaranteed to cause 2138 * a VMExit prior to executing any instructions in the guest. 2139 */ 2140 if (preemption_timeout == 0) { 2141 vmx_preemption_timer_fn(&vmx->nested.preemption_timer); 2142 return; 2143 } 2144 2145 if (vcpu->arch.virtual_tsc_khz == 0) 2146 return; 2147 2148 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; 2149 preemption_timeout *= 1000000; 2150 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); 2151 hrtimer_start(&vmx->nested.preemption_timer, 2152 ktime_add_ns(ktime_get(), preemption_timeout), 2153 HRTIMER_MODE_ABS_PINNED); 2154 } 2155 2156 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) 2157 { 2158 if (vmx->nested.nested_run_pending && 2159 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) 2160 return vmcs12->guest_ia32_efer; 2161 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) 2162 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME); 2163 else 2164 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME); 2165 } 2166 2167 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx) 2168 { 2169 struct kvm *kvm = vmx->vcpu.kvm; 2170 2171 /* 2172 * If vmcs02 hasn't been initialized, set the constant vmcs02 state 2173 * according to L0's settings (vmcs12 is irrelevant here). Host 2174 * fields that come from L0 and are not constant, e.g. HOST_CR3, 2175 * will be set as needed prior to VMLAUNCH/VMRESUME. 2176 */ 2177 if (vmx->nested.vmcs02_initialized) 2178 return; 2179 vmx->nested.vmcs02_initialized = true; 2180 2181 /* 2182 * We don't care what the EPTP value is we just need to guarantee 2183 * it's valid so we don't get a false positive when doing early 2184 * consistency checks. 2185 */ 2186 if (enable_ept && nested_early_check) 2187 vmcs_write64(EPT_POINTER, 2188 construct_eptp(&vmx->vcpu, 0, PT64_ROOT_4LEVEL)); 2189 2190 /* All VMFUNCs are currently emulated through L0 vmexits. */ 2191 if (cpu_has_vmx_vmfunc()) 2192 vmcs_write64(VM_FUNCTION_CONTROL, 0); 2193 2194 if (cpu_has_vmx_posted_intr()) 2195 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); 2196 2197 if (cpu_has_vmx_msr_bitmap()) 2198 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap)); 2199 2200 /* 2201 * PML is emulated for L2, but never enabled in hardware as the MMU 2202 * handles A/D emulation. Disabling PML for L2 also avoids having to 2203 * deal with filtering out L2 GPAs from the buffer. 2204 */ 2205 if (enable_pml) { 2206 vmcs_write64(PML_ADDRESS, 0); 2207 vmcs_write16(GUEST_PML_INDEX, -1); 2208 } 2209 2210 if (cpu_has_vmx_encls_vmexit()) 2211 vmcs_write64(ENCLS_EXITING_BITMAP, INVALID_GPA); 2212 2213 if (kvm_notify_vmexit_enabled(kvm)) 2214 vmcs_write32(NOTIFY_WINDOW, kvm->arch.notify_window); 2215 2216 /* 2217 * Set the MSR load/store lists to match L0's settings. Only the 2218 * addresses are constant (for vmcs02), the counts can change based 2219 * on L2's behavior, e.g. switching to/from long mode. 2220 */ 2221 vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val)); 2222 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 2223 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 2224 2225 vmx_set_constant_host_state(vmx); 2226 } 2227 2228 static void prepare_vmcs02_early_rare(struct vcpu_vmx *vmx, 2229 struct vmcs12 *vmcs12) 2230 { 2231 prepare_vmcs02_constant_state(vmx); 2232 2233 vmcs_write64(VMCS_LINK_POINTER, INVALID_GPA); 2234 2235 /* 2236 * If VPID is disabled, then guest TLB accesses use VPID=0, i.e. the 2237 * same VPID as the host. Emulate this behavior by using vpid01 for L2 2238 * if VPID is disabled in vmcs12. Note, if VPID is disabled, VM-Enter 2239 * and VM-Exit are architecturally required to flush VPID=0, but *only* 2240 * VPID=0. I.e. using vpid02 would be ok (so long as KVM emulates the 2241 * required flushes), but doing so would cause KVM to over-flush. E.g. 2242 * if L1 runs L2 X with VPID12=1, then runs L2 Y with VPID12 disabled, 2243 * and then runs L2 X again, then KVM can and should retain TLB entries 2244 * for VPID12=1. 2245 */ 2246 if (enable_vpid) { 2247 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) 2248 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); 2249 else 2250 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 2251 } 2252 } 2253 2254 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct loaded_vmcs *vmcs01, 2255 struct vmcs12 *vmcs12) 2256 { 2257 u32 exec_control; 2258 u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12); 2259 2260 if (vmx->nested.dirty_vmcs12 || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) 2261 prepare_vmcs02_early_rare(vmx, vmcs12); 2262 2263 /* 2264 * PIN CONTROLS 2265 */ 2266 exec_control = __pin_controls_get(vmcs01); 2267 exec_control |= (vmcs12->pin_based_vm_exec_control & 2268 ~PIN_BASED_VMX_PREEMPTION_TIMER); 2269 2270 /* Posted interrupts setting is only taken from vmcs12. */ 2271 vmx->nested.pi_pending = false; 2272 if (nested_cpu_has_posted_intr(vmcs12)) 2273 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; 2274 else 2275 exec_control &= ~PIN_BASED_POSTED_INTR; 2276 pin_controls_set(vmx, exec_control); 2277 2278 /* 2279 * EXEC CONTROLS 2280 */ 2281 exec_control = __exec_controls_get(vmcs01); /* L0's desires */ 2282 exec_control &= ~CPU_BASED_INTR_WINDOW_EXITING; 2283 exec_control &= ~CPU_BASED_NMI_WINDOW_EXITING; 2284 exec_control &= ~CPU_BASED_TPR_SHADOW; 2285 exec_control |= vmcs12->cpu_based_vm_exec_control; 2286 2287 vmx->nested.l1_tpr_threshold = -1; 2288 if (exec_control & CPU_BASED_TPR_SHADOW) 2289 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); 2290 #ifdef CONFIG_X86_64 2291 else 2292 exec_control |= CPU_BASED_CR8_LOAD_EXITING | 2293 CPU_BASED_CR8_STORE_EXITING; 2294 #endif 2295 2296 /* 2297 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed 2298 * for I/O port accesses. 2299 */ 2300 exec_control |= CPU_BASED_UNCOND_IO_EXITING; 2301 exec_control &= ~CPU_BASED_USE_IO_BITMAPS; 2302 2303 /* 2304 * This bit will be computed in nested_get_vmcs12_pages, because 2305 * we do not have access to L1's MSR bitmap yet. For now, keep 2306 * the same bit as before, hoping to avoid multiple VMWRITEs that 2307 * only set/clear this bit. 2308 */ 2309 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; 2310 exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS; 2311 2312 exec_controls_set(vmx, exec_control); 2313 2314 /* 2315 * SECONDARY EXEC CONTROLS 2316 */ 2317 if (cpu_has_secondary_exec_ctrls()) { 2318 exec_control = __secondary_exec_controls_get(vmcs01); 2319 2320 /* Take the following fields only from vmcs12 */ 2321 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2322 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2323 SECONDARY_EXEC_ENABLE_INVPCID | 2324 SECONDARY_EXEC_ENABLE_RDTSCP | 2325 SECONDARY_EXEC_ENABLE_XSAVES | 2326 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2327 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2328 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2329 SECONDARY_EXEC_ENABLE_VMFUNC | 2330 SECONDARY_EXEC_DESC); 2331 2332 if (nested_cpu_has(vmcs12, 2333 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) 2334 exec_control |= vmcs12->secondary_vm_exec_control; 2335 2336 /* PML is emulated and never enabled in hardware for L2. */ 2337 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 2338 2339 /* VMCS shadowing for L2 is emulated for now */ 2340 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 2341 2342 /* 2343 * Preset *DT exiting when emulating UMIP, so that vmx_set_cr4() 2344 * will not have to rewrite the controls just for this bit. 2345 */ 2346 if (vmx_umip_emulated() && (vmcs12->guest_cr4 & X86_CR4_UMIP)) 2347 exec_control |= SECONDARY_EXEC_DESC; 2348 2349 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 2350 vmcs_write16(GUEST_INTR_STATUS, 2351 vmcs12->guest_intr_status); 2352 2353 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) 2354 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 2355 2356 if (exec_control & SECONDARY_EXEC_ENCLS_EXITING) 2357 vmx_write_encls_bitmap(&vmx->vcpu, vmcs12); 2358 2359 secondary_exec_controls_set(vmx, exec_control); 2360 } 2361 2362 /* 2363 * ENTRY CONTROLS 2364 * 2365 * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE 2366 * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate 2367 * on the related bits (if supported by the CPU) in the hope that 2368 * we can avoid VMWrites during vmx_set_efer(). 2369 * 2370 * Similarly, take vmcs01's PERF_GLOBAL_CTRL in the hope that if KVM is 2371 * loading PERF_GLOBAL_CTRL via the VMCS for L1, then KVM will want to 2372 * do the same for L2. 2373 */ 2374 exec_control = __vm_entry_controls_get(vmcs01); 2375 exec_control |= (vmcs12->vm_entry_controls & 2376 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL); 2377 exec_control &= ~(VM_ENTRY_IA32E_MODE | VM_ENTRY_LOAD_IA32_EFER); 2378 if (cpu_has_load_ia32_efer()) { 2379 if (guest_efer & EFER_LMA) 2380 exec_control |= VM_ENTRY_IA32E_MODE; 2381 if (guest_efer != host_efer) 2382 exec_control |= VM_ENTRY_LOAD_IA32_EFER; 2383 } 2384 vm_entry_controls_set(vmx, exec_control); 2385 2386 /* 2387 * EXIT CONTROLS 2388 * 2389 * L2->L1 exit controls are emulated - the hardware exit is to L0 so 2390 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER 2391 * bits may be modified by vmx_set_efer() in prepare_vmcs02(). 2392 */ 2393 exec_control = __vm_exit_controls_get(vmcs01); 2394 if (cpu_has_load_ia32_efer() && guest_efer != host_efer) 2395 exec_control |= VM_EXIT_LOAD_IA32_EFER; 2396 else 2397 exec_control &= ~VM_EXIT_LOAD_IA32_EFER; 2398 vm_exit_controls_set(vmx, exec_control); 2399 2400 /* 2401 * Interrupt/Exception Fields 2402 */ 2403 if (vmx->nested.nested_run_pending) { 2404 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 2405 vmcs12->vm_entry_intr_info_field); 2406 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 2407 vmcs12->vm_entry_exception_error_code); 2408 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 2409 vmcs12->vm_entry_instruction_len); 2410 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 2411 vmcs12->guest_interruptibility_info); 2412 vmx->loaded_vmcs->nmi_known_unmasked = 2413 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); 2414 } else { 2415 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 2416 } 2417 } 2418 2419 static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) 2420 { 2421 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs; 2422 2423 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields & 2424 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2)) { 2425 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); 2426 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); 2427 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); 2428 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); 2429 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); 2430 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); 2431 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); 2432 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); 2433 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); 2434 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); 2435 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); 2436 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); 2437 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); 2438 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); 2439 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); 2440 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); 2441 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); 2442 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); 2443 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); 2444 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); 2445 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); 2446 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); 2447 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); 2448 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); 2449 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); 2450 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); 2451 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); 2452 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); 2453 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); 2454 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); 2455 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); 2456 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); 2457 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); 2458 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); 2459 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); 2460 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); 2461 2462 vmx->segment_cache.bitmask = 0; 2463 } 2464 2465 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields & 2466 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1)) { 2467 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); 2468 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 2469 vmcs12->guest_pending_dbg_exceptions); 2470 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); 2471 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); 2472 2473 /* 2474 * L1 may access the L2's PDPTR, so save them to construct 2475 * vmcs12 2476 */ 2477 if (enable_ept) { 2478 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); 2479 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); 2480 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); 2481 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); 2482 } 2483 2484 if (kvm_mpx_supported() && vmx->nested.nested_run_pending && 2485 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)) 2486 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); 2487 } 2488 2489 if (nested_cpu_has_xsaves(vmcs12)) 2490 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); 2491 2492 /* 2493 * Whether page-faults are trapped is determined by a combination of 2494 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. If L0 2495 * doesn't care about page faults then we should set all of these to 2496 * L1's desires. However, if L0 does care about (some) page faults, it 2497 * is not easy (if at all possible?) to merge L0 and L1's desires, we 2498 * simply ask to exit on each and every L2 page fault. This is done by 2499 * setting MASK=MATCH=0 and (see below) EB.PF=1. 2500 * Note that below we don't need special code to set EB.PF beyond the 2501 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, 2502 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when 2503 * !enable_ept, EB.PF is 1, so the "or" will always be 1. 2504 */ 2505 if (vmx_need_pf_intercept(&vmx->vcpu)) { 2506 /* 2507 * TODO: if both L0 and L1 need the same MASK and MATCH, 2508 * go ahead and use it? 2509 */ 2510 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 2511 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 2512 } else { 2513 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, vmcs12->page_fault_error_code_mask); 2514 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, vmcs12->page_fault_error_code_match); 2515 } 2516 2517 if (cpu_has_vmx_apicv()) { 2518 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0); 2519 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1); 2520 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2); 2521 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3); 2522 } 2523 2524 /* 2525 * Make sure the msr_autostore list is up to date before we set the 2526 * count in the vmcs02. 2527 */ 2528 prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC); 2529 2530 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vmx->msr_autostore.guest.nr); 2531 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 2532 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 2533 2534 set_cr4_guest_host_mask(vmx); 2535 } 2536 2537 /* 2538 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested 2539 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it 2540 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 2541 * guest in a way that will both be appropriate to L1's requests, and our 2542 * needs. In addition to modifying the active vmcs (which is vmcs02), this 2543 * function also has additional necessary side-effects, like setting various 2544 * vcpu->arch fields. 2545 * Returns 0 on success, 1 on failure. Invalid state exit qualification code 2546 * is assigned to entry_failure_code on failure. 2547 */ 2548 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, 2549 bool from_vmentry, 2550 enum vm_entry_failure_code *entry_failure_code) 2551 { 2552 struct vcpu_vmx *vmx = to_vmx(vcpu); 2553 bool load_guest_pdptrs_vmcs12 = false; 2554 2555 if (vmx->nested.dirty_vmcs12 || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) { 2556 prepare_vmcs02_rare(vmx, vmcs12); 2557 vmx->nested.dirty_vmcs12 = false; 2558 2559 load_guest_pdptrs_vmcs12 = !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr) || 2560 !(vmx->nested.hv_evmcs->hv_clean_fields & 2561 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1); 2562 } 2563 2564 if (vmx->nested.nested_run_pending && 2565 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { 2566 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); 2567 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); 2568 } else { 2569 kvm_set_dr(vcpu, 7, vcpu->arch.dr7); 2570 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.pre_vmenter_debugctl); 2571 } 2572 if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending || 2573 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))) 2574 vmcs_write64(GUEST_BNDCFGS, vmx->nested.pre_vmenter_bndcfgs); 2575 vmx_set_rflags(vcpu, vmcs12->guest_rflags); 2576 2577 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the 2578 * bitwise-or of what L1 wants to trap for L2, and what we want to 2579 * trap. Note that CR0.TS also needs updating - we do this later. 2580 */ 2581 vmx_update_exception_bitmap(vcpu); 2582 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; 2583 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); 2584 2585 if (vmx->nested.nested_run_pending && 2586 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { 2587 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); 2588 vcpu->arch.pat = vmcs12->guest_ia32_pat; 2589 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2590 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 2591 } 2592 2593 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2594 vcpu->arch.l1_tsc_offset, 2595 vmx_get_l2_tsc_offset(vcpu), 2596 vmx_get_l2_tsc_multiplier(vcpu)); 2597 2598 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2599 vcpu->arch.l1_tsc_scaling_ratio, 2600 vmx_get_l2_tsc_multiplier(vcpu)); 2601 2602 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); 2603 if (kvm_caps.has_tsc_control) 2604 vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio); 2605 2606 nested_vmx_transition_tlb_flush(vcpu, vmcs12, true); 2607 2608 if (nested_cpu_has_ept(vmcs12)) 2609 nested_ept_init_mmu_context(vcpu); 2610 2611 /* 2612 * Override the CR0/CR4 read shadows after setting the effective guest 2613 * CR0/CR4. The common helpers also set the shadows, but they don't 2614 * account for vmcs12's cr0/4_guest_host_mask. 2615 */ 2616 vmx_set_cr0(vcpu, vmcs12->guest_cr0); 2617 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); 2618 2619 vmx_set_cr4(vcpu, vmcs12->guest_cr4); 2620 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); 2621 2622 vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12); 2623 /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ 2624 vmx_set_efer(vcpu, vcpu->arch.efer); 2625 2626 /* 2627 * Guest state is invalid and unrestricted guest is disabled, 2628 * which means L1 attempted VMEntry to L2 with invalid state. 2629 * Fail the VMEntry. 2630 * 2631 * However when force loading the guest state (SMM exit or 2632 * loading nested state after migration, it is possible to 2633 * have invalid guest state now, which will be later fixed by 2634 * restoring L2 register state 2635 */ 2636 if (CC(from_vmentry && !vmx_guest_state_valid(vcpu))) { 2637 *entry_failure_code = ENTRY_FAIL_DEFAULT; 2638 return -EINVAL; 2639 } 2640 2641 /* Shadow page tables on either EPT or shadow page tables. */ 2642 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), 2643 from_vmentry, entry_failure_code)) 2644 return -EINVAL; 2645 2646 /* 2647 * Immediately write vmcs02.GUEST_CR3. It will be propagated to vmcs12 2648 * on nested VM-Exit, which can occur without actually running L2 and 2649 * thus without hitting vmx_load_mmu_pgd(), e.g. if L1 is entering L2 with 2650 * vmcs12.GUEST_ACTIVITYSTATE=HLT, in which case KVM will intercept the 2651 * transition to HLT instead of running L2. 2652 */ 2653 if (enable_ept) 2654 vmcs_writel(GUEST_CR3, vmcs12->guest_cr3); 2655 2656 /* Late preparation of GUEST_PDPTRs now that EFER and CRs are set. */ 2657 if (load_guest_pdptrs_vmcs12 && nested_cpu_has_ept(vmcs12) && 2658 is_pae_paging(vcpu)) { 2659 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); 2660 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); 2661 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); 2662 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); 2663 } 2664 2665 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && 2666 kvm_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu)) && 2667 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, 2668 vmcs12->guest_ia32_perf_global_ctrl))) { 2669 *entry_failure_code = ENTRY_FAIL_DEFAULT; 2670 return -EINVAL; 2671 } 2672 2673 kvm_rsp_write(vcpu, vmcs12->guest_rsp); 2674 kvm_rip_write(vcpu, vmcs12->guest_rip); 2675 2676 /* 2677 * It was observed that genuine Hyper-V running in L1 doesn't reset 2678 * 'hv_clean_fields' by itself, it only sets the corresponding dirty 2679 * bits when it changes a field in eVMCS. Mark all fields as clean 2680 * here. 2681 */ 2682 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) 2683 vmx->nested.hv_evmcs->hv_clean_fields |= 2684 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 2685 2686 return 0; 2687 } 2688 2689 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12) 2690 { 2691 if (CC(!nested_cpu_has_nmi_exiting(vmcs12) && 2692 nested_cpu_has_virtual_nmis(vmcs12))) 2693 return -EINVAL; 2694 2695 if (CC(!nested_cpu_has_virtual_nmis(vmcs12) && 2696 nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING))) 2697 return -EINVAL; 2698 2699 return 0; 2700 } 2701 2702 static bool nested_vmx_check_eptp(struct kvm_vcpu *vcpu, u64 new_eptp) 2703 { 2704 struct vcpu_vmx *vmx = to_vmx(vcpu); 2705 2706 /* Check for memory type validity */ 2707 switch (new_eptp & VMX_EPTP_MT_MASK) { 2708 case VMX_EPTP_MT_UC: 2709 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))) 2710 return false; 2711 break; 2712 case VMX_EPTP_MT_WB: 2713 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))) 2714 return false; 2715 break; 2716 default: 2717 return false; 2718 } 2719 2720 /* Page-walk levels validity. */ 2721 switch (new_eptp & VMX_EPTP_PWL_MASK) { 2722 case VMX_EPTP_PWL_5: 2723 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_5_BIT))) 2724 return false; 2725 break; 2726 case VMX_EPTP_PWL_4: 2727 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_4_BIT))) 2728 return false; 2729 break; 2730 default: 2731 return false; 2732 } 2733 2734 /* Reserved bits should not be set */ 2735 if (CC(kvm_vcpu_is_illegal_gpa(vcpu, new_eptp) || ((new_eptp >> 7) & 0x1f))) 2736 return false; 2737 2738 /* AD, if set, should be supported */ 2739 if (new_eptp & VMX_EPTP_AD_ENABLE_BIT) { 2740 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))) 2741 return false; 2742 } 2743 2744 return true; 2745 } 2746 2747 /* 2748 * Checks related to VM-Execution Control Fields 2749 */ 2750 static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu, 2751 struct vmcs12 *vmcs12) 2752 { 2753 struct vcpu_vmx *vmx = to_vmx(vcpu); 2754 2755 if (CC(!vmx_control_verify(vmcs12->pin_based_vm_exec_control, 2756 vmx->nested.msrs.pinbased_ctls_low, 2757 vmx->nested.msrs.pinbased_ctls_high)) || 2758 CC(!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, 2759 vmx->nested.msrs.procbased_ctls_low, 2760 vmx->nested.msrs.procbased_ctls_high))) 2761 return -EINVAL; 2762 2763 if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && 2764 CC(!vmx_control_verify(vmcs12->secondary_vm_exec_control, 2765 vmx->nested.msrs.secondary_ctls_low, 2766 vmx->nested.msrs.secondary_ctls_high))) 2767 return -EINVAL; 2768 2769 if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) || 2770 nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) || 2771 nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) || 2772 nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12) || 2773 nested_vmx_check_apic_access_controls(vcpu, vmcs12) || 2774 nested_vmx_check_apicv_controls(vcpu, vmcs12) || 2775 nested_vmx_check_nmi_controls(vmcs12) || 2776 nested_vmx_check_pml_controls(vcpu, vmcs12) || 2777 nested_vmx_check_unrestricted_guest_controls(vcpu, vmcs12) || 2778 nested_vmx_check_mode_based_ept_exec_controls(vcpu, vmcs12) || 2779 nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12) || 2780 CC(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id)) 2781 return -EINVAL; 2782 2783 if (!nested_cpu_has_preemption_timer(vmcs12) && 2784 nested_cpu_has_save_preemption_timer(vmcs12)) 2785 return -EINVAL; 2786 2787 if (nested_cpu_has_ept(vmcs12) && 2788 CC(!nested_vmx_check_eptp(vcpu, vmcs12->ept_pointer))) 2789 return -EINVAL; 2790 2791 if (nested_cpu_has_vmfunc(vmcs12)) { 2792 if (CC(vmcs12->vm_function_control & 2793 ~vmx->nested.msrs.vmfunc_controls)) 2794 return -EINVAL; 2795 2796 if (nested_cpu_has_eptp_switching(vmcs12)) { 2797 if (CC(!nested_cpu_has_ept(vmcs12)) || 2798 CC(!page_address_valid(vcpu, vmcs12->eptp_list_address))) 2799 return -EINVAL; 2800 } 2801 } 2802 2803 return 0; 2804 } 2805 2806 /* 2807 * Checks related to VM-Exit Control Fields 2808 */ 2809 static int nested_check_vm_exit_controls(struct kvm_vcpu *vcpu, 2810 struct vmcs12 *vmcs12) 2811 { 2812 struct vcpu_vmx *vmx = to_vmx(vcpu); 2813 2814 if (CC(!vmx_control_verify(vmcs12->vm_exit_controls, 2815 vmx->nested.msrs.exit_ctls_low, 2816 vmx->nested.msrs.exit_ctls_high)) || 2817 CC(nested_vmx_check_exit_msr_switch_controls(vcpu, vmcs12))) 2818 return -EINVAL; 2819 2820 return 0; 2821 } 2822 2823 /* 2824 * Checks related to VM-Entry Control Fields 2825 */ 2826 static int nested_check_vm_entry_controls(struct kvm_vcpu *vcpu, 2827 struct vmcs12 *vmcs12) 2828 { 2829 struct vcpu_vmx *vmx = to_vmx(vcpu); 2830 2831 if (CC(!vmx_control_verify(vmcs12->vm_entry_controls, 2832 vmx->nested.msrs.entry_ctls_low, 2833 vmx->nested.msrs.entry_ctls_high))) 2834 return -EINVAL; 2835 2836 /* 2837 * From the Intel SDM, volume 3: 2838 * Fields relevant to VM-entry event injection must be set properly. 2839 * These fields are the VM-entry interruption-information field, the 2840 * VM-entry exception error code, and the VM-entry instruction length. 2841 */ 2842 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) { 2843 u32 intr_info = vmcs12->vm_entry_intr_info_field; 2844 u8 vector = intr_info & INTR_INFO_VECTOR_MASK; 2845 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK; 2846 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK; 2847 bool should_have_error_code; 2848 bool urg = nested_cpu_has2(vmcs12, 2849 SECONDARY_EXEC_UNRESTRICTED_GUEST); 2850 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE; 2851 2852 /* VM-entry interruption-info field: interruption type */ 2853 if (CC(intr_type == INTR_TYPE_RESERVED) || 2854 CC(intr_type == INTR_TYPE_OTHER_EVENT && 2855 !nested_cpu_supports_monitor_trap_flag(vcpu))) 2856 return -EINVAL; 2857 2858 /* VM-entry interruption-info field: vector */ 2859 if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) || 2860 CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) || 2861 CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0)) 2862 return -EINVAL; 2863 2864 /* VM-entry interruption-info field: deliver error code */ 2865 should_have_error_code = 2866 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode && 2867 x86_exception_has_error_code(vector); 2868 if (CC(has_error_code != should_have_error_code)) 2869 return -EINVAL; 2870 2871 /* VM-entry exception error code */ 2872 if (CC(has_error_code && 2873 vmcs12->vm_entry_exception_error_code & GENMASK(31, 16))) 2874 return -EINVAL; 2875 2876 /* VM-entry interruption-info field: reserved bits */ 2877 if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK)) 2878 return -EINVAL; 2879 2880 /* VM-entry instruction length */ 2881 switch (intr_type) { 2882 case INTR_TYPE_SOFT_EXCEPTION: 2883 case INTR_TYPE_SOFT_INTR: 2884 case INTR_TYPE_PRIV_SW_EXCEPTION: 2885 if (CC(vmcs12->vm_entry_instruction_len > 15) || 2886 CC(vmcs12->vm_entry_instruction_len == 0 && 2887 CC(!nested_cpu_has_zero_length_injection(vcpu)))) 2888 return -EINVAL; 2889 } 2890 } 2891 2892 if (nested_vmx_check_entry_msr_switch_controls(vcpu, vmcs12)) 2893 return -EINVAL; 2894 2895 return 0; 2896 } 2897 2898 static int nested_vmx_check_controls(struct kvm_vcpu *vcpu, 2899 struct vmcs12 *vmcs12) 2900 { 2901 if (nested_check_vm_execution_controls(vcpu, vmcs12) || 2902 nested_check_vm_exit_controls(vcpu, vmcs12) || 2903 nested_check_vm_entry_controls(vcpu, vmcs12)) 2904 return -EINVAL; 2905 2906 if (guest_cpuid_has_evmcs(vcpu)) 2907 return nested_evmcs_check_controls(vmcs12); 2908 2909 return 0; 2910 } 2911 2912 static int nested_vmx_check_address_space_size(struct kvm_vcpu *vcpu, 2913 struct vmcs12 *vmcs12) 2914 { 2915 #ifdef CONFIG_X86_64 2916 if (CC(!!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) != 2917 !!(vcpu->arch.efer & EFER_LMA))) 2918 return -EINVAL; 2919 #endif 2920 return 0; 2921 } 2922 2923 static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu, 2924 struct vmcs12 *vmcs12) 2925 { 2926 bool ia32e = !!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE); 2927 2928 if (CC(!nested_host_cr0_valid(vcpu, vmcs12->host_cr0)) || 2929 CC(!nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) || 2930 CC(kvm_vcpu_is_illegal_gpa(vcpu, vmcs12->host_cr3))) 2931 return -EINVAL; 2932 2933 if (CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_esp, vcpu)) || 2934 CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_eip, vcpu))) 2935 return -EINVAL; 2936 2937 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) && 2938 CC(!kvm_pat_valid(vmcs12->host_ia32_pat))) 2939 return -EINVAL; 2940 2941 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) && 2942 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu), 2943 vmcs12->host_ia32_perf_global_ctrl))) 2944 return -EINVAL; 2945 2946 if (ia32e) { 2947 if (CC(!(vmcs12->host_cr4 & X86_CR4_PAE))) 2948 return -EINVAL; 2949 } else { 2950 if (CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) || 2951 CC(vmcs12->host_cr4 & X86_CR4_PCIDE) || 2952 CC((vmcs12->host_rip) >> 32)) 2953 return -EINVAL; 2954 } 2955 2956 if (CC(vmcs12->host_cs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2957 CC(vmcs12->host_ss_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2958 CC(vmcs12->host_ds_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2959 CC(vmcs12->host_es_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2960 CC(vmcs12->host_fs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2961 CC(vmcs12->host_gs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2962 CC(vmcs12->host_tr_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2963 CC(vmcs12->host_cs_selector == 0) || 2964 CC(vmcs12->host_tr_selector == 0) || 2965 CC(vmcs12->host_ss_selector == 0 && !ia32e)) 2966 return -EINVAL; 2967 2968 if (CC(is_noncanonical_address(vmcs12->host_fs_base, vcpu)) || 2969 CC(is_noncanonical_address(vmcs12->host_gs_base, vcpu)) || 2970 CC(is_noncanonical_address(vmcs12->host_gdtr_base, vcpu)) || 2971 CC(is_noncanonical_address(vmcs12->host_idtr_base, vcpu)) || 2972 CC(is_noncanonical_address(vmcs12->host_tr_base, vcpu)) || 2973 CC(is_noncanonical_address(vmcs12->host_rip, vcpu))) 2974 return -EINVAL; 2975 2976 /* 2977 * If the load IA32_EFER VM-exit control is 1, bits reserved in the 2978 * IA32_EFER MSR must be 0 in the field for that register. In addition, 2979 * the values of the LMA and LME bits in the field must each be that of 2980 * the host address-space size VM-exit control. 2981 */ 2982 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { 2983 if (CC(!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer)) || 2984 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA)) || 2985 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))) 2986 return -EINVAL; 2987 } 2988 2989 return 0; 2990 } 2991 2992 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu, 2993 struct vmcs12 *vmcs12) 2994 { 2995 struct vcpu_vmx *vmx = to_vmx(vcpu); 2996 struct gfn_to_hva_cache *ghc = &vmx->nested.shadow_vmcs12_cache; 2997 struct vmcs_hdr hdr; 2998 2999 if (vmcs12->vmcs_link_pointer == INVALID_GPA) 3000 return 0; 3001 3002 if (CC(!page_address_valid(vcpu, vmcs12->vmcs_link_pointer))) 3003 return -EINVAL; 3004 3005 if (ghc->gpa != vmcs12->vmcs_link_pointer && 3006 CC(kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, 3007 vmcs12->vmcs_link_pointer, VMCS12_SIZE))) 3008 return -EINVAL; 3009 3010 if (CC(kvm_read_guest_offset_cached(vcpu->kvm, ghc, &hdr, 3011 offsetof(struct vmcs12, hdr), 3012 sizeof(hdr)))) 3013 return -EINVAL; 3014 3015 if (CC(hdr.revision_id != VMCS12_REVISION) || 3016 CC(hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12))) 3017 return -EINVAL; 3018 3019 return 0; 3020 } 3021 3022 /* 3023 * Checks related to Guest Non-register State 3024 */ 3025 static int nested_check_guest_non_reg_state(struct vmcs12 *vmcs12) 3026 { 3027 if (CC(vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && 3028 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT && 3029 vmcs12->guest_activity_state != GUEST_ACTIVITY_WAIT_SIPI)) 3030 return -EINVAL; 3031 3032 return 0; 3033 } 3034 3035 static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu, 3036 struct vmcs12 *vmcs12, 3037 enum vm_entry_failure_code *entry_failure_code) 3038 { 3039 bool ia32e = !!(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE); 3040 3041 *entry_failure_code = ENTRY_FAIL_DEFAULT; 3042 3043 if (CC(!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0)) || 3044 CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))) 3045 return -EINVAL; 3046 3047 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) && 3048 CC(!kvm_dr7_valid(vmcs12->guest_dr7))) 3049 return -EINVAL; 3050 3051 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) && 3052 CC(!kvm_pat_valid(vmcs12->guest_ia32_pat))) 3053 return -EINVAL; 3054 3055 if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) { 3056 *entry_failure_code = ENTRY_FAIL_VMCS_LINK_PTR; 3057 return -EINVAL; 3058 } 3059 3060 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && 3061 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu), 3062 vmcs12->guest_ia32_perf_global_ctrl))) 3063 return -EINVAL; 3064 3065 if (CC((vmcs12->guest_cr0 & (X86_CR0_PG | X86_CR0_PE)) == X86_CR0_PG)) 3066 return -EINVAL; 3067 3068 if (CC(ia32e && !(vmcs12->guest_cr4 & X86_CR4_PAE)) || 3069 CC(ia32e && !(vmcs12->guest_cr0 & X86_CR0_PG))) 3070 return -EINVAL; 3071 3072 /* 3073 * If the load IA32_EFER VM-entry control is 1, the following checks 3074 * are performed on the field for the IA32_EFER MSR: 3075 * - Bits reserved in the IA32_EFER MSR must be 0. 3076 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of 3077 * the IA-32e mode guest VM-exit control. It must also be identical 3078 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to 3079 * CR0.PG) is 1. 3080 */ 3081 if (to_vmx(vcpu)->nested.nested_run_pending && 3082 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { 3083 if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) || 3084 CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) || 3085 CC(((vmcs12->guest_cr0 & X86_CR0_PG) && 3086 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))) 3087 return -EINVAL; 3088 } 3089 3090 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) && 3091 (CC(is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu)) || 3092 CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))) 3093 return -EINVAL; 3094 3095 if (nested_check_guest_non_reg_state(vmcs12)) 3096 return -EINVAL; 3097 3098 return 0; 3099 } 3100 3101 static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu) 3102 { 3103 struct vcpu_vmx *vmx = to_vmx(vcpu); 3104 unsigned long cr3, cr4; 3105 bool vm_fail; 3106 3107 if (!nested_early_check) 3108 return 0; 3109 3110 if (vmx->msr_autoload.host.nr) 3111 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 3112 if (vmx->msr_autoload.guest.nr) 3113 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 3114 3115 preempt_disable(); 3116 3117 vmx_prepare_switch_to_guest(vcpu); 3118 3119 /* 3120 * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS, 3121 * which is reserved to '1' by hardware. GUEST_RFLAGS is guaranteed to 3122 * be written (by prepare_vmcs02()) before the "real" VMEnter, i.e. 3123 * there is no need to preserve other bits or save/restore the field. 3124 */ 3125 vmcs_writel(GUEST_RFLAGS, 0); 3126 3127 cr3 = __get_current_cr3_fast(); 3128 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 3129 vmcs_writel(HOST_CR3, cr3); 3130 vmx->loaded_vmcs->host_state.cr3 = cr3; 3131 } 3132 3133 cr4 = cr4_read_shadow(); 3134 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 3135 vmcs_writel(HOST_CR4, cr4); 3136 vmx->loaded_vmcs->host_state.cr4 = cr4; 3137 } 3138 3139 vm_fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 3140 __vmx_vcpu_run_flags(vmx)); 3141 3142 if (vmx->msr_autoload.host.nr) 3143 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 3144 if (vmx->msr_autoload.guest.nr) 3145 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 3146 3147 if (vm_fail) { 3148 u32 error = vmcs_read32(VM_INSTRUCTION_ERROR); 3149 3150 preempt_enable(); 3151 3152 trace_kvm_nested_vmenter_failed( 3153 "early hardware check VM-instruction error: ", error); 3154 WARN_ON_ONCE(error != VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3155 return 1; 3156 } 3157 3158 /* 3159 * VMExit clears RFLAGS.IF and DR7, even on a consistency check. 3160 */ 3161 if (hw_breakpoint_active()) 3162 set_debugreg(__this_cpu_read(cpu_dr7), 7); 3163 local_irq_enable(); 3164 preempt_enable(); 3165 3166 /* 3167 * A non-failing VMEntry means we somehow entered guest mode with 3168 * an illegal RIP, and that's just the tip of the iceberg. There 3169 * is no telling what memory has been modified or what state has 3170 * been exposed to unknown code. Hitting this all but guarantees 3171 * a (very critical) hardware issue. 3172 */ 3173 WARN_ON(!(vmcs_read32(VM_EXIT_REASON) & 3174 VMX_EXIT_REASONS_FAILED_VMENTRY)); 3175 3176 return 0; 3177 } 3178 3179 static bool nested_get_evmcs_page(struct kvm_vcpu *vcpu) 3180 { 3181 struct vcpu_vmx *vmx = to_vmx(vcpu); 3182 3183 /* 3184 * hv_evmcs may end up being not mapped after migration (when 3185 * L2 was running), map it here to make sure vmcs12 changes are 3186 * properly reflected. 3187 */ 3188 if (guest_cpuid_has_evmcs(vcpu) && 3189 vmx->nested.hv_evmcs_vmptr == EVMPTR_MAP_PENDING) { 3190 enum nested_evmptrld_status evmptrld_status = 3191 nested_vmx_handle_enlightened_vmptrld(vcpu, false); 3192 3193 if (evmptrld_status == EVMPTRLD_VMFAIL || 3194 evmptrld_status == EVMPTRLD_ERROR) 3195 return false; 3196 3197 /* 3198 * Post migration VMCS12 always provides the most actual 3199 * information, copy it to eVMCS upon entry. 3200 */ 3201 vmx->nested.need_vmcs12_to_shadow_sync = true; 3202 } 3203 3204 return true; 3205 } 3206 3207 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu) 3208 { 3209 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3210 struct vcpu_vmx *vmx = to_vmx(vcpu); 3211 struct kvm_host_map *map; 3212 3213 if (!vcpu->arch.pdptrs_from_userspace && 3214 !nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) { 3215 /* 3216 * Reload the guest's PDPTRs since after a migration 3217 * the guest CR3 might be restored prior to setting the nested 3218 * state which can lead to a load of wrong PDPTRs. 3219 */ 3220 if (CC(!load_pdptrs(vcpu, vcpu->arch.cr3))) 3221 return false; 3222 } 3223 3224 3225 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { 3226 map = &vmx->nested.apic_access_page_map; 3227 3228 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->apic_access_addr), map)) { 3229 vmcs_write64(APIC_ACCESS_ADDR, pfn_to_hpa(map->pfn)); 3230 } else { 3231 pr_debug_ratelimited("%s: no backing for APIC-access address in vmcs12\n", 3232 __func__); 3233 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 3234 vcpu->run->internal.suberror = 3235 KVM_INTERNAL_ERROR_EMULATION; 3236 vcpu->run->internal.ndata = 0; 3237 return false; 3238 } 3239 } 3240 3241 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { 3242 map = &vmx->nested.virtual_apic_map; 3243 3244 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->virtual_apic_page_addr), map)) { 3245 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, pfn_to_hpa(map->pfn)); 3246 } else if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING) && 3247 nested_cpu_has(vmcs12, CPU_BASED_CR8_STORE_EXITING) && 3248 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { 3249 /* 3250 * The processor will never use the TPR shadow, simply 3251 * clear the bit from the execution control. Such a 3252 * configuration is useless, but it happens in tests. 3253 * For any other configuration, failing the vm entry is 3254 * _not_ what the processor does but it's basically the 3255 * only possibility we have. 3256 */ 3257 exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW); 3258 } else { 3259 /* 3260 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR to 3261 * force VM-Entry to fail. 3262 */ 3263 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, INVALID_GPA); 3264 } 3265 } 3266 3267 if (nested_cpu_has_posted_intr(vmcs12)) { 3268 map = &vmx->nested.pi_desc_map; 3269 3270 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->posted_intr_desc_addr), map)) { 3271 vmx->nested.pi_desc = 3272 (struct pi_desc *)(((void *)map->hva) + 3273 offset_in_page(vmcs12->posted_intr_desc_addr)); 3274 vmcs_write64(POSTED_INTR_DESC_ADDR, 3275 pfn_to_hpa(map->pfn) + offset_in_page(vmcs12->posted_intr_desc_addr)); 3276 } else { 3277 /* 3278 * Defer the KVM_INTERNAL_EXIT until KVM tries to 3279 * access the contents of the VMCS12 posted interrupt 3280 * descriptor. (Note that KVM may do this when it 3281 * should not, per the architectural specification.) 3282 */ 3283 vmx->nested.pi_desc = NULL; 3284 pin_controls_clearbit(vmx, PIN_BASED_POSTED_INTR); 3285 } 3286 } 3287 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12)) 3288 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS); 3289 else 3290 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS); 3291 3292 return true; 3293 } 3294 3295 static bool vmx_get_nested_state_pages(struct kvm_vcpu *vcpu) 3296 { 3297 /* 3298 * Note: nested_get_evmcs_page() also updates 'vp_assist_page' copy 3299 * in 'struct kvm_vcpu_hv' in case eVMCS is in use, this is mandatory 3300 * to make nested_evmcs_l2_tlb_flush_enabled() work correctly post 3301 * migration. 3302 */ 3303 if (!nested_get_evmcs_page(vcpu)) { 3304 pr_debug_ratelimited("%s: enlightened vmptrld failed\n", 3305 __func__); 3306 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 3307 vcpu->run->internal.suberror = 3308 KVM_INTERNAL_ERROR_EMULATION; 3309 vcpu->run->internal.ndata = 0; 3310 3311 return false; 3312 } 3313 3314 if (is_guest_mode(vcpu) && !nested_get_vmcs12_pages(vcpu)) 3315 return false; 3316 3317 return true; 3318 } 3319 3320 static int nested_vmx_write_pml_buffer(struct kvm_vcpu *vcpu, gpa_t gpa) 3321 { 3322 struct vmcs12 *vmcs12; 3323 struct vcpu_vmx *vmx = to_vmx(vcpu); 3324 gpa_t dst; 3325 3326 if (WARN_ON_ONCE(!is_guest_mode(vcpu))) 3327 return 0; 3328 3329 if (WARN_ON_ONCE(vmx->nested.pml_full)) 3330 return 1; 3331 3332 /* 3333 * Check if PML is enabled for the nested guest. Whether eptp bit 6 is 3334 * set is already checked as part of A/D emulation. 3335 */ 3336 vmcs12 = get_vmcs12(vcpu); 3337 if (!nested_cpu_has_pml(vmcs12)) 3338 return 0; 3339 3340 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 3341 vmx->nested.pml_full = true; 3342 return 1; 3343 } 3344 3345 gpa &= ~0xFFFull; 3346 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 3347 3348 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 3349 offset_in_page(dst), sizeof(gpa))) 3350 return 0; 3351 3352 vmcs12->guest_pml_index--; 3353 3354 return 0; 3355 } 3356 3357 /* 3358 * Intel's VMX Instruction Reference specifies a common set of prerequisites 3359 * for running VMX instructions (except VMXON, whose prerequisites are 3360 * slightly different). It also specifies what exception to inject otherwise. 3361 * Note that many of these exceptions have priority over VM exits, so they 3362 * don't have to be checked again here. 3363 */ 3364 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) 3365 { 3366 if (!to_vmx(vcpu)->nested.vmxon) { 3367 kvm_queue_exception(vcpu, UD_VECTOR); 3368 return 0; 3369 } 3370 3371 if (vmx_get_cpl(vcpu)) { 3372 kvm_inject_gp(vcpu, 0); 3373 return 0; 3374 } 3375 3376 return 1; 3377 } 3378 3379 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu) 3380 { 3381 u8 rvi = vmx_get_rvi(); 3382 u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI); 3383 3384 return ((rvi & 0xf0) > (vppr & 0xf0)); 3385 } 3386 3387 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, 3388 struct vmcs12 *vmcs12); 3389 3390 /* 3391 * If from_vmentry is false, this is being called from state restore (either RSM 3392 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume. 3393 * 3394 * Returns: 3395 * NVMX_VMENTRY_SUCCESS: Entered VMX non-root mode 3396 * NVMX_VMENTRY_VMFAIL: Consistency check VMFail 3397 * NVMX_VMENTRY_VMEXIT: Consistency check VMExit 3398 * NVMX_VMENTRY_KVM_INTERNAL_ERROR: KVM internal error 3399 */ 3400 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, 3401 bool from_vmentry) 3402 { 3403 struct vcpu_vmx *vmx = to_vmx(vcpu); 3404 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3405 enum vm_entry_failure_code entry_failure_code; 3406 bool evaluate_pending_interrupts; 3407 union vmx_exit_reason exit_reason = { 3408 .basic = EXIT_REASON_INVALID_STATE, 3409 .failed_vmentry = 1, 3410 }; 3411 u32 failed_index; 3412 3413 trace_kvm_nested_vmenter(kvm_rip_read(vcpu), 3414 vmx->nested.current_vmptr, 3415 vmcs12->guest_rip, 3416 vmcs12->guest_intr_status, 3417 vmcs12->vm_entry_intr_info_field, 3418 vmcs12->secondary_vm_exec_control & SECONDARY_EXEC_ENABLE_EPT, 3419 vmcs12->ept_pointer, 3420 vmcs12->guest_cr3, 3421 KVM_ISA_VMX); 3422 3423 kvm_service_local_tlb_flush_requests(vcpu); 3424 3425 evaluate_pending_interrupts = exec_controls_get(vmx) & 3426 (CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_NMI_WINDOW_EXITING); 3427 if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu)) 3428 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu); 3429 if (!evaluate_pending_interrupts) 3430 evaluate_pending_interrupts |= kvm_apic_has_pending_init_or_sipi(vcpu); 3431 3432 if (!vmx->nested.nested_run_pending || 3433 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) 3434 vmx->nested.pre_vmenter_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); 3435 if (kvm_mpx_supported() && 3436 (!vmx->nested.nested_run_pending || 3437 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))) 3438 vmx->nested.pre_vmenter_bndcfgs = vmcs_read64(GUEST_BNDCFGS); 3439 3440 /* 3441 * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and* 3442 * nested early checks are disabled. In the event of a "late" VM-Fail, 3443 * i.e. a VM-Fail detected by hardware but not KVM, KVM must unwind its 3444 * software model to the pre-VMEntry host state. When EPT is disabled, 3445 * GUEST_CR3 holds KVM's shadow CR3, not L1's "real" CR3, which causes 3446 * nested_vmx_restore_host_state() to corrupt vcpu->arch.cr3. Stuffing 3447 * vmcs01.GUEST_CR3 results in the unwind naturally setting arch.cr3 to 3448 * the correct value. Smashing vmcs01.GUEST_CR3 is safe because nested 3449 * VM-Exits, and the unwind, reset KVM's MMU, i.e. vmcs01.GUEST_CR3 is 3450 * guaranteed to be overwritten with a shadow CR3 prior to re-entering 3451 * L1. Don't stuff vmcs01.GUEST_CR3 when using nested early checks as 3452 * KVM modifies vcpu->arch.cr3 if and only if the early hardware checks 3453 * pass, and early VM-Fails do not reset KVM's MMU, i.e. the VM-Fail 3454 * path would need to manually save/restore vmcs01.GUEST_CR3. 3455 */ 3456 if (!enable_ept && !nested_early_check) 3457 vmcs_writel(GUEST_CR3, vcpu->arch.cr3); 3458 3459 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02); 3460 3461 prepare_vmcs02_early(vmx, &vmx->vmcs01, vmcs12); 3462 3463 if (from_vmentry) { 3464 if (unlikely(!nested_get_vmcs12_pages(vcpu))) { 3465 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 3466 return NVMX_VMENTRY_KVM_INTERNAL_ERROR; 3467 } 3468 3469 if (nested_vmx_check_vmentry_hw(vcpu)) { 3470 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 3471 return NVMX_VMENTRY_VMFAIL; 3472 } 3473 3474 if (nested_vmx_check_guest_state(vcpu, vmcs12, 3475 &entry_failure_code)) { 3476 exit_reason.basic = EXIT_REASON_INVALID_STATE; 3477 vmcs12->exit_qualification = entry_failure_code; 3478 goto vmentry_fail_vmexit; 3479 } 3480 } 3481 3482 enter_guest_mode(vcpu); 3483 3484 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &entry_failure_code)) { 3485 exit_reason.basic = EXIT_REASON_INVALID_STATE; 3486 vmcs12->exit_qualification = entry_failure_code; 3487 goto vmentry_fail_vmexit_guest_mode; 3488 } 3489 3490 if (from_vmentry) { 3491 failed_index = nested_vmx_load_msr(vcpu, 3492 vmcs12->vm_entry_msr_load_addr, 3493 vmcs12->vm_entry_msr_load_count); 3494 if (failed_index) { 3495 exit_reason.basic = EXIT_REASON_MSR_LOAD_FAIL; 3496 vmcs12->exit_qualification = failed_index; 3497 goto vmentry_fail_vmexit_guest_mode; 3498 } 3499 } else { 3500 /* 3501 * The MMU is not initialized to point at the right entities yet and 3502 * "get pages" would need to read data from the guest (i.e. we will 3503 * need to perform gpa to hpa translation). Request a call 3504 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs 3505 * have already been set at vmentry time and should not be reset. 3506 */ 3507 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 3508 } 3509 3510 /* 3511 * Re-evaluate pending events if L1 had a pending IRQ/NMI/INIT/SIPI 3512 * when it executed VMLAUNCH/VMRESUME, as entering non-root mode can 3513 * effectively unblock various events, e.g. INIT/SIPI cause VM-Exit 3514 * unconditionally. 3515 */ 3516 if (unlikely(evaluate_pending_interrupts)) 3517 kvm_make_request(KVM_REQ_EVENT, vcpu); 3518 3519 /* 3520 * Do not start the preemption timer hrtimer until after we know 3521 * we are successful, so that only nested_vmx_vmexit needs to cancel 3522 * the timer. 3523 */ 3524 vmx->nested.preemption_timer_expired = false; 3525 if (nested_cpu_has_preemption_timer(vmcs12)) { 3526 u64 timer_value = vmx_calc_preemption_timer_value(vcpu); 3527 vmx_start_preemption_timer(vcpu, timer_value); 3528 } 3529 3530 /* 3531 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point 3532 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet 3533 * returned as far as L1 is concerned. It will only return (and set 3534 * the success flag) when L2 exits (see nested_vmx_vmexit()). 3535 */ 3536 return NVMX_VMENTRY_SUCCESS; 3537 3538 /* 3539 * A failed consistency check that leads to a VMExit during L1's 3540 * VMEnter to L2 is a variation of a normal VMexit, as explained in 3541 * 26.7 "VM-entry failures during or after loading guest state". 3542 */ 3543 vmentry_fail_vmexit_guest_mode: 3544 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING) 3545 vcpu->arch.tsc_offset -= vmcs12->tsc_offset; 3546 leave_guest_mode(vcpu); 3547 3548 vmentry_fail_vmexit: 3549 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 3550 3551 if (!from_vmentry) 3552 return NVMX_VMENTRY_VMEXIT; 3553 3554 load_vmcs12_host_state(vcpu, vmcs12); 3555 vmcs12->vm_exit_reason = exit_reason.full; 3556 if (enable_shadow_vmcs || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) 3557 vmx->nested.need_vmcs12_to_shadow_sync = true; 3558 return NVMX_VMENTRY_VMEXIT; 3559 } 3560 3561 /* 3562 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 3563 * for running an L2 nested guest. 3564 */ 3565 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) 3566 { 3567 struct vmcs12 *vmcs12; 3568 enum nvmx_vmentry_status status; 3569 struct vcpu_vmx *vmx = to_vmx(vcpu); 3570 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); 3571 enum nested_evmptrld_status evmptrld_status; 3572 3573 if (!nested_vmx_check_permission(vcpu)) 3574 return 1; 3575 3576 evmptrld_status = nested_vmx_handle_enlightened_vmptrld(vcpu, launch); 3577 if (evmptrld_status == EVMPTRLD_ERROR) { 3578 kvm_queue_exception(vcpu, UD_VECTOR); 3579 return 1; 3580 } 3581 3582 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 3583 3584 if (CC(evmptrld_status == EVMPTRLD_VMFAIL)) 3585 return nested_vmx_failInvalid(vcpu); 3586 3587 if (CC(!evmptr_is_valid(vmx->nested.hv_evmcs_vmptr) && 3588 vmx->nested.current_vmptr == INVALID_GPA)) 3589 return nested_vmx_failInvalid(vcpu); 3590 3591 vmcs12 = get_vmcs12(vcpu); 3592 3593 /* 3594 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact 3595 * that there *is* a valid VMCS pointer, RFLAGS.CF is set 3596 * rather than RFLAGS.ZF, and no error number is stored to the 3597 * VM-instruction error field. 3598 */ 3599 if (CC(vmcs12->hdr.shadow_vmcs)) 3600 return nested_vmx_failInvalid(vcpu); 3601 3602 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) { 3603 copy_enlightened_to_vmcs12(vmx, vmx->nested.hv_evmcs->hv_clean_fields); 3604 /* Enlightened VMCS doesn't have launch state */ 3605 vmcs12->launch_state = !launch; 3606 } else if (enable_shadow_vmcs) { 3607 copy_shadow_to_vmcs12(vmx); 3608 } 3609 3610 /* 3611 * The nested entry process starts with enforcing various prerequisites 3612 * on vmcs12 as required by the Intel SDM, and act appropriately when 3613 * they fail: As the SDM explains, some conditions should cause the 3614 * instruction to fail, while others will cause the instruction to seem 3615 * to succeed, but return an EXIT_REASON_INVALID_STATE. 3616 * To speed up the normal (success) code path, we should avoid checking 3617 * for misconfigurations which will anyway be caught by the processor 3618 * when using the merged vmcs02. 3619 */ 3620 if (CC(interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS)) 3621 return nested_vmx_fail(vcpu, VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); 3622 3623 if (CC(vmcs12->launch_state == launch)) 3624 return nested_vmx_fail(vcpu, 3625 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS 3626 : VMXERR_VMRESUME_NONLAUNCHED_VMCS); 3627 3628 if (nested_vmx_check_controls(vcpu, vmcs12)) 3629 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3630 3631 if (nested_vmx_check_address_space_size(vcpu, vmcs12)) 3632 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 3633 3634 if (nested_vmx_check_host_state(vcpu, vmcs12)) 3635 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 3636 3637 /* 3638 * We're finally done with prerequisite checking, and can start with 3639 * the nested entry. 3640 */ 3641 vmx->nested.nested_run_pending = 1; 3642 vmx->nested.has_preemption_timer_deadline = false; 3643 status = nested_vmx_enter_non_root_mode(vcpu, true); 3644 if (unlikely(status != NVMX_VMENTRY_SUCCESS)) 3645 goto vmentry_failed; 3646 3647 /* Emulate processing of posted interrupts on VM-Enter. */ 3648 if (nested_cpu_has_posted_intr(vmcs12) && 3649 kvm_apic_has_interrupt(vcpu) == vmx->nested.posted_intr_nv) { 3650 vmx->nested.pi_pending = true; 3651 kvm_make_request(KVM_REQ_EVENT, vcpu); 3652 kvm_apic_clear_irr(vcpu, vmx->nested.posted_intr_nv); 3653 } 3654 3655 /* Hide L1D cache contents from the nested guest. */ 3656 vmx->vcpu.arch.l1tf_flush_l1d = true; 3657 3658 /* 3659 * Must happen outside of nested_vmx_enter_non_root_mode() as it will 3660 * also be used as part of restoring nVMX state for 3661 * snapshot restore (migration). 3662 * 3663 * In this flow, it is assumed that vmcs12 cache was 3664 * transferred as part of captured nVMX state and should 3665 * therefore not be read from guest memory (which may not 3666 * exist on destination host yet). 3667 */ 3668 nested_cache_shadow_vmcs12(vcpu, vmcs12); 3669 3670 switch (vmcs12->guest_activity_state) { 3671 case GUEST_ACTIVITY_HLT: 3672 /* 3673 * If we're entering a halted L2 vcpu and the L2 vcpu won't be 3674 * awakened by event injection or by an NMI-window VM-exit or 3675 * by an interrupt-window VM-exit, halt the vcpu. 3676 */ 3677 if (!(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) && 3678 !nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING) && 3679 !(nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING) && 3680 (vmcs12->guest_rflags & X86_EFLAGS_IF))) { 3681 vmx->nested.nested_run_pending = 0; 3682 return kvm_emulate_halt_noskip(vcpu); 3683 } 3684 break; 3685 case GUEST_ACTIVITY_WAIT_SIPI: 3686 vmx->nested.nested_run_pending = 0; 3687 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 3688 break; 3689 default: 3690 break; 3691 } 3692 3693 return 1; 3694 3695 vmentry_failed: 3696 vmx->nested.nested_run_pending = 0; 3697 if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR) 3698 return 0; 3699 if (status == NVMX_VMENTRY_VMEXIT) 3700 return 1; 3701 WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL); 3702 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3703 } 3704 3705 /* 3706 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date 3707 * because L2 may have changed some cr0 bits directly (CR0_GUEST_HOST_MASK). 3708 * This function returns the new value we should put in vmcs12.guest_cr0. 3709 * It's not enough to just return the vmcs02 GUEST_CR0. Rather, 3710 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now 3711 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 3712 * didn't trap the bit, because if L1 did, so would L0). 3713 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have 3714 * been modified by L2, and L1 knows it. So just leave the old value of 3715 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 3716 * isn't relevant, because if L0 traps this bit it can set it to anything. 3717 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have 3718 * changed these bits, and therefore they need to be updated, but L0 3719 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather 3720 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. 3721 */ 3722 static inline unsigned long 3723 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 3724 { 3725 return 3726 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | 3727 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | 3728 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | 3729 vcpu->arch.cr0_guest_owned_bits)); 3730 } 3731 3732 static inline unsigned long 3733 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 3734 { 3735 return 3736 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | 3737 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | 3738 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | 3739 vcpu->arch.cr4_guest_owned_bits)); 3740 } 3741 3742 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, 3743 struct vmcs12 *vmcs12, 3744 u32 vm_exit_reason, u32 exit_intr_info) 3745 { 3746 u32 idt_vectoring; 3747 unsigned int nr; 3748 3749 /* 3750 * Per the SDM, VM-Exits due to double and triple faults are never 3751 * considered to occur during event delivery, even if the double/triple 3752 * fault is the result of an escalating vectoring issue. 3753 * 3754 * Note, the SDM qualifies the double fault behavior with "The original 3755 * event results in a double-fault exception". It's unclear why the 3756 * qualification exists since exits due to double fault can occur only 3757 * while vectoring a different exception (injected events are never 3758 * subject to interception), i.e. there's _always_ an original event. 3759 * 3760 * The SDM also uses NMI as a confusing example for the "original event 3761 * causes the VM exit directly" clause. NMI isn't special in any way, 3762 * the same rule applies to all events that cause an exit directly. 3763 * NMI is an odd choice for the example because NMIs can only occur on 3764 * instruction boundaries, i.e. they _can't_ occur during vectoring. 3765 */ 3766 if ((u16)vm_exit_reason == EXIT_REASON_TRIPLE_FAULT || 3767 ((u16)vm_exit_reason == EXIT_REASON_EXCEPTION_NMI && 3768 is_double_fault(exit_intr_info))) { 3769 vmcs12->idt_vectoring_info_field = 0; 3770 } else if (vcpu->arch.exception.injected) { 3771 nr = vcpu->arch.exception.vector; 3772 idt_vectoring = nr | VECTORING_INFO_VALID_MASK; 3773 3774 if (kvm_exception_is_soft(nr)) { 3775 vmcs12->vm_exit_instruction_len = 3776 vcpu->arch.event_exit_inst_len; 3777 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; 3778 } else 3779 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; 3780 3781 if (vcpu->arch.exception.has_error_code) { 3782 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; 3783 vmcs12->idt_vectoring_error_code = 3784 vcpu->arch.exception.error_code; 3785 } 3786 3787 vmcs12->idt_vectoring_info_field = idt_vectoring; 3788 } else if (vcpu->arch.nmi_injected) { 3789 vmcs12->idt_vectoring_info_field = 3790 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; 3791 } else if (vcpu->arch.interrupt.injected) { 3792 nr = vcpu->arch.interrupt.nr; 3793 idt_vectoring = nr | VECTORING_INFO_VALID_MASK; 3794 3795 if (vcpu->arch.interrupt.soft) { 3796 idt_vectoring |= INTR_TYPE_SOFT_INTR; 3797 vmcs12->vm_entry_instruction_len = 3798 vcpu->arch.event_exit_inst_len; 3799 } else 3800 idt_vectoring |= INTR_TYPE_EXT_INTR; 3801 3802 vmcs12->idt_vectoring_info_field = idt_vectoring; 3803 } else { 3804 vmcs12->idt_vectoring_info_field = 0; 3805 } 3806 } 3807 3808 3809 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) 3810 { 3811 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3812 gfn_t gfn; 3813 3814 /* 3815 * Don't need to mark the APIC access page dirty; it is never 3816 * written to by the CPU during APIC virtualization. 3817 */ 3818 3819 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { 3820 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; 3821 kvm_vcpu_mark_page_dirty(vcpu, gfn); 3822 } 3823 3824 if (nested_cpu_has_posted_intr(vmcs12)) { 3825 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; 3826 kvm_vcpu_mark_page_dirty(vcpu, gfn); 3827 } 3828 } 3829 3830 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) 3831 { 3832 struct vcpu_vmx *vmx = to_vmx(vcpu); 3833 int max_irr; 3834 void *vapic_page; 3835 u16 status; 3836 3837 if (!vmx->nested.pi_pending) 3838 return 0; 3839 3840 if (!vmx->nested.pi_desc) 3841 goto mmio_needed; 3842 3843 vmx->nested.pi_pending = false; 3844 3845 if (!pi_test_and_clear_on(vmx->nested.pi_desc)) 3846 return 0; 3847 3848 max_irr = pi_find_highest_vector(vmx->nested.pi_desc); 3849 if (max_irr > 0) { 3850 vapic_page = vmx->nested.virtual_apic_map.hva; 3851 if (!vapic_page) 3852 goto mmio_needed; 3853 3854 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, 3855 vapic_page, &max_irr); 3856 status = vmcs_read16(GUEST_INTR_STATUS); 3857 if ((u8)max_irr > ((u8)status & 0xff)) { 3858 status &= ~0xff; 3859 status |= (u8)max_irr; 3860 vmcs_write16(GUEST_INTR_STATUS, status); 3861 } 3862 } 3863 3864 nested_mark_vmcs12_pages_dirty(vcpu); 3865 return 0; 3866 3867 mmio_needed: 3868 kvm_handle_memory_failure(vcpu, X86EMUL_IO_NEEDED, NULL); 3869 return -ENXIO; 3870 } 3871 3872 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu) 3873 { 3874 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit; 3875 u32 intr_info = ex->vector | INTR_INFO_VALID_MASK; 3876 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3877 unsigned long exit_qual; 3878 3879 if (ex->has_payload) { 3880 exit_qual = ex->payload; 3881 } else if (ex->vector == PF_VECTOR) { 3882 exit_qual = vcpu->arch.cr2; 3883 } else if (ex->vector == DB_VECTOR) { 3884 exit_qual = vcpu->arch.dr6; 3885 exit_qual &= ~DR6_BT; 3886 exit_qual ^= DR6_ACTIVE_LOW; 3887 } else { 3888 exit_qual = 0; 3889 } 3890 3891 /* 3892 * Unlike AMD's Paged Real Mode, which reports an error code on #PF 3893 * VM-Exits even if the CPU is in Real Mode, Intel VMX never sets the 3894 * "has error code" flags on VM-Exit if the CPU is in Real Mode. 3895 */ 3896 if (ex->has_error_code && is_protmode(vcpu)) { 3897 /* 3898 * Intel CPUs do not generate error codes with bits 31:16 set, 3899 * and more importantly VMX disallows setting bits 31:16 in the 3900 * injected error code for VM-Entry. Drop the bits to mimic 3901 * hardware and avoid inducing failure on nested VM-Entry if L1 3902 * chooses to inject the exception back to L2. AMD CPUs _do_ 3903 * generate "full" 32-bit error codes, so KVM allows userspace 3904 * to inject exception error codes with bits 31:16 set. 3905 */ 3906 vmcs12->vm_exit_intr_error_code = (u16)ex->error_code; 3907 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 3908 } 3909 3910 if (kvm_exception_is_soft(ex->vector)) 3911 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 3912 else 3913 intr_info |= INTR_TYPE_HARD_EXCEPTION; 3914 3915 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && 3916 vmx_get_nmi_mask(vcpu)) 3917 intr_info |= INTR_INFO_UNBLOCK_NMI; 3918 3919 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); 3920 } 3921 3922 /* 3923 * Returns true if a debug trap is (likely) pending delivery. Infer the class 3924 * of a #DB (trap-like vs. fault-like) from the exception payload (to-be-DR6). 3925 * Using the payload is flawed because code breakpoints (fault-like) and data 3926 * breakpoints (trap-like) set the same bits in DR6 (breakpoint detected), i.e. 3927 * this will return false positives if a to-be-injected code breakpoint #DB is 3928 * pending (from KVM's perspective, but not "pending" across an instruction 3929 * boundary). ICEBP, a.k.a. INT1, is also not reflected here even though it 3930 * too is trap-like. 3931 * 3932 * KVM "works" despite these flaws as ICEBP isn't currently supported by the 3933 * emulator, Monitor Trap Flag is not marked pending on intercepted #DBs (the 3934 * #DB has already happened), and MTF isn't marked pending on code breakpoints 3935 * from the emulator (because such #DBs are fault-like and thus don't trigger 3936 * actions that fire on instruction retire). 3937 */ 3938 static unsigned long vmx_get_pending_dbg_trap(struct kvm_queued_exception *ex) 3939 { 3940 if (!ex->pending || ex->vector != DB_VECTOR) 3941 return 0; 3942 3943 /* General Detect #DBs are always fault-like. */ 3944 return ex->payload & ~DR6_BD; 3945 } 3946 3947 /* 3948 * Returns true if there's a pending #DB exception that is lower priority than 3949 * a pending Monitor Trap Flag VM-Exit. TSS T-flag #DBs are not emulated by 3950 * KVM, but could theoretically be injected by userspace. Note, this code is 3951 * imperfect, see above. 3952 */ 3953 static bool vmx_is_low_priority_db_trap(struct kvm_queued_exception *ex) 3954 { 3955 return vmx_get_pending_dbg_trap(ex) & ~DR6_BT; 3956 } 3957 3958 /* 3959 * Certain VM-exits set the 'pending debug exceptions' field to indicate a 3960 * recognized #DB (data or single-step) that has yet to be delivered. Since KVM 3961 * represents these debug traps with a payload that is said to be compatible 3962 * with the 'pending debug exceptions' field, write the payload to the VMCS 3963 * field if a VM-exit is delivered before the debug trap. 3964 */ 3965 static void nested_vmx_update_pending_dbg(struct kvm_vcpu *vcpu) 3966 { 3967 unsigned long pending_dbg; 3968 3969 pending_dbg = vmx_get_pending_dbg_trap(&vcpu->arch.exception); 3970 if (pending_dbg) 3971 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, pending_dbg); 3972 } 3973 3974 static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu) 3975 { 3976 return nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && 3977 to_vmx(vcpu)->nested.preemption_timer_expired; 3978 } 3979 3980 static bool vmx_has_nested_events(struct kvm_vcpu *vcpu, bool for_injection) 3981 { 3982 struct vcpu_vmx *vmx = to_vmx(vcpu); 3983 void *vapic = vmx->nested.virtual_apic_map.hva; 3984 int max_irr, vppr; 3985 3986 if (nested_vmx_preemption_timer_pending(vcpu) || 3987 vmx->nested.mtf_pending) 3988 return true; 3989 3990 /* 3991 * Virtual Interrupt Delivery doesn't require manual injection. Either 3992 * the interrupt is already in GUEST_RVI and will be recognized by CPU 3993 * at VM-Entry, or there is a KVM_REQ_EVENT pending and KVM will move 3994 * the interrupt from the PIR to RVI prior to entering the guest. 3995 */ 3996 if (for_injection) 3997 return false; 3998 3999 if (!nested_cpu_has_vid(get_vmcs12(vcpu)) || 4000 __vmx_interrupt_blocked(vcpu)) 4001 return false; 4002 4003 if (!vapic) 4004 return false; 4005 4006 vppr = *((u32 *)(vapic + APIC_PROCPRI)); 4007 4008 if (vmx->nested.pi_pending && vmx->nested.pi_desc && 4009 pi_test_on(vmx->nested.pi_desc)) { 4010 max_irr = pi_find_highest_vector(vmx->nested.pi_desc); 4011 if (max_irr > 0 && (max_irr & 0xf0) > (vppr & 0xf0)) 4012 return true; 4013 } 4014 4015 return false; 4016 } 4017 4018 /* 4019 * Per the Intel SDM's table "Priority Among Concurrent Events", with minor 4020 * edits to fill in missing examples, e.g. #DB due to split-lock accesses, 4021 * and less minor edits to splice in the priority of VMX Non-Root specific 4022 * events, e.g. MTF and NMI/INTR-window exiting. 4023 * 4024 * 1 Hardware Reset and Machine Checks 4025 * - RESET 4026 * - Machine Check 4027 * 4028 * 2 Trap on Task Switch 4029 * - T flag in TSS is set (on task switch) 4030 * 4031 * 3 External Hardware Interventions 4032 * - FLUSH 4033 * - STOPCLK 4034 * - SMI 4035 * - INIT 4036 * 4037 * 3.5 Monitor Trap Flag (MTF) VM-exit[1] 4038 * 4039 * 4 Traps on Previous Instruction 4040 * - Breakpoints 4041 * - Trap-class Debug Exceptions (#DB due to TF flag set, data/I-O 4042 * breakpoint, or #DB due to a split-lock access) 4043 * 4044 * 4.3 VMX-preemption timer expired VM-exit 4045 * 4046 * 4.6 NMI-window exiting VM-exit[2] 4047 * 4048 * 5 Nonmaskable Interrupts (NMI) 4049 * 4050 * 5.5 Interrupt-window exiting VM-exit and Virtual-interrupt delivery 4051 * 4052 * 6 Maskable Hardware Interrupts 4053 * 4054 * 7 Code Breakpoint Fault 4055 * 4056 * 8 Faults from Fetching Next Instruction 4057 * - Code-Segment Limit Violation 4058 * - Code Page Fault 4059 * - Control protection exception (missing ENDBRANCH at target of indirect 4060 * call or jump) 4061 * 4062 * 9 Faults from Decoding Next Instruction 4063 * - Instruction length > 15 bytes 4064 * - Invalid Opcode 4065 * - Coprocessor Not Available 4066 * 4067 *10 Faults on Executing Instruction 4068 * - Overflow 4069 * - Bound error 4070 * - Invalid TSS 4071 * - Segment Not Present 4072 * - Stack fault 4073 * - General Protection 4074 * - Data Page Fault 4075 * - Alignment Check 4076 * - x86 FPU Floating-point exception 4077 * - SIMD floating-point exception 4078 * - Virtualization exception 4079 * - Control protection exception 4080 * 4081 * [1] Per the "Monitor Trap Flag" section: System-management interrupts (SMIs), 4082 * INIT signals, and higher priority events take priority over MTF VM exits. 4083 * MTF VM exits take priority over debug-trap exceptions and lower priority 4084 * events. 4085 * 4086 * [2] Debug-trap exceptions and higher priority events take priority over VM exits 4087 * caused by the VMX-preemption timer. VM exits caused by the VMX-preemption 4088 * timer take priority over VM exits caused by the "NMI-window exiting" 4089 * VM-execution control and lower priority events. 4090 * 4091 * [3] Debug-trap exceptions and higher priority events take priority over VM exits 4092 * caused by "NMI-window exiting". VM exits caused by this control take 4093 * priority over non-maskable interrupts (NMIs) and lower priority events. 4094 * 4095 * [4] Virtual-interrupt delivery has the same priority as that of VM exits due to 4096 * the 1-setting of the "interrupt-window exiting" VM-execution control. Thus, 4097 * non-maskable interrupts (NMIs) and higher priority events take priority over 4098 * delivery of a virtual interrupt; delivery of a virtual interrupt takes 4099 * priority over external interrupts and lower priority events. 4100 */ 4101 static int vmx_check_nested_events(struct kvm_vcpu *vcpu) 4102 { 4103 struct kvm_lapic *apic = vcpu->arch.apic; 4104 struct vcpu_vmx *vmx = to_vmx(vcpu); 4105 /* 4106 * Only a pending nested run blocks a pending exception. If there is a 4107 * previously injected event, the pending exception occurred while said 4108 * event was being delivered and thus needs to be handled. 4109 */ 4110 bool block_nested_exceptions = vmx->nested.nested_run_pending; 4111 /* 4112 * New events (not exceptions) are only recognized at instruction 4113 * boundaries. If an event needs reinjection, then KVM is handling a 4114 * VM-Exit that occurred _during_ instruction execution; new events are 4115 * blocked until the instruction completes. 4116 */ 4117 bool block_nested_events = block_nested_exceptions || 4118 kvm_event_needs_reinjection(vcpu); 4119 4120 if (lapic_in_kernel(vcpu) && 4121 test_bit(KVM_APIC_INIT, &apic->pending_events)) { 4122 if (block_nested_events) 4123 return -EBUSY; 4124 nested_vmx_update_pending_dbg(vcpu); 4125 clear_bit(KVM_APIC_INIT, &apic->pending_events); 4126 if (vcpu->arch.mp_state != KVM_MP_STATE_INIT_RECEIVED) 4127 nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0); 4128 4129 /* MTF is discarded if the vCPU is in WFS. */ 4130 vmx->nested.mtf_pending = false; 4131 return 0; 4132 } 4133 4134 if (lapic_in_kernel(vcpu) && 4135 test_bit(KVM_APIC_SIPI, &apic->pending_events)) { 4136 if (block_nested_events) 4137 return -EBUSY; 4138 4139 clear_bit(KVM_APIC_SIPI, &apic->pending_events); 4140 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 4141 nested_vmx_vmexit(vcpu, EXIT_REASON_SIPI_SIGNAL, 0, 4142 apic->sipi_vector & 0xFFUL); 4143 return 0; 4144 } 4145 /* Fallthrough, the SIPI is completely ignored. */ 4146 } 4147 4148 /* 4149 * Process exceptions that are higher priority than Monitor Trap Flag: 4150 * fault-like exceptions, TSS T flag #DB (not emulated by KVM, but 4151 * could theoretically come in from userspace), and ICEBP (INT1). 4152 * 4153 * TODO: SMIs have higher priority than MTF and trap-like #DBs (except 4154 * for TSS T flag #DBs). KVM also doesn't save/restore pending MTF 4155 * across SMI/RSM as it should; that needs to be addressed in order to 4156 * prioritize SMI over MTF and trap-like #DBs. 4157 */ 4158 if (vcpu->arch.exception_vmexit.pending && 4159 !vmx_is_low_priority_db_trap(&vcpu->arch.exception_vmexit)) { 4160 if (block_nested_exceptions) 4161 return -EBUSY; 4162 4163 nested_vmx_inject_exception_vmexit(vcpu); 4164 return 0; 4165 } 4166 4167 if (vcpu->arch.exception.pending && 4168 !vmx_is_low_priority_db_trap(&vcpu->arch.exception)) { 4169 if (block_nested_exceptions) 4170 return -EBUSY; 4171 goto no_vmexit; 4172 } 4173 4174 if (vmx->nested.mtf_pending) { 4175 if (block_nested_events) 4176 return -EBUSY; 4177 nested_vmx_update_pending_dbg(vcpu); 4178 nested_vmx_vmexit(vcpu, EXIT_REASON_MONITOR_TRAP_FLAG, 0, 0); 4179 return 0; 4180 } 4181 4182 if (vcpu->arch.exception_vmexit.pending) { 4183 if (block_nested_exceptions) 4184 return -EBUSY; 4185 4186 nested_vmx_inject_exception_vmexit(vcpu); 4187 return 0; 4188 } 4189 4190 if (vcpu->arch.exception.pending) { 4191 if (block_nested_exceptions) 4192 return -EBUSY; 4193 goto no_vmexit; 4194 } 4195 4196 if (nested_vmx_preemption_timer_pending(vcpu)) { 4197 if (block_nested_events) 4198 return -EBUSY; 4199 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); 4200 return 0; 4201 } 4202 4203 if (vcpu->arch.smi_pending && !is_smm(vcpu)) { 4204 if (block_nested_events) 4205 return -EBUSY; 4206 goto no_vmexit; 4207 } 4208 4209 if (vcpu->arch.nmi_pending && !vmx_nmi_blocked(vcpu)) { 4210 if (block_nested_events) 4211 return -EBUSY; 4212 if (!nested_exit_on_nmi(vcpu)) 4213 goto no_vmexit; 4214 4215 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, 4216 NMI_VECTOR | INTR_TYPE_NMI_INTR | 4217 INTR_INFO_VALID_MASK, 0); 4218 /* 4219 * The NMI-triggered VM exit counts as injection: 4220 * clear this one and block further NMIs. 4221 */ 4222 vcpu->arch.nmi_pending = 0; 4223 vmx_set_nmi_mask(vcpu, true); 4224 return 0; 4225 } 4226 4227 if (kvm_cpu_has_interrupt(vcpu) && !vmx_interrupt_blocked(vcpu)) { 4228 if (block_nested_events) 4229 return -EBUSY; 4230 if (!nested_exit_on_intr(vcpu)) 4231 goto no_vmexit; 4232 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); 4233 return 0; 4234 } 4235 4236 no_vmexit: 4237 return vmx_complete_nested_posted_interrupt(vcpu); 4238 } 4239 4240 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) 4241 { 4242 ktime_t remaining = 4243 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); 4244 u64 value; 4245 4246 if (ktime_to_ns(remaining) <= 0) 4247 return 0; 4248 4249 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; 4250 do_div(value, 1000000); 4251 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; 4252 } 4253 4254 static bool is_vmcs12_ext_field(unsigned long field) 4255 { 4256 switch (field) { 4257 case GUEST_ES_SELECTOR: 4258 case GUEST_CS_SELECTOR: 4259 case GUEST_SS_SELECTOR: 4260 case GUEST_DS_SELECTOR: 4261 case GUEST_FS_SELECTOR: 4262 case GUEST_GS_SELECTOR: 4263 case GUEST_LDTR_SELECTOR: 4264 case GUEST_TR_SELECTOR: 4265 case GUEST_ES_LIMIT: 4266 case GUEST_CS_LIMIT: 4267 case GUEST_SS_LIMIT: 4268 case GUEST_DS_LIMIT: 4269 case GUEST_FS_LIMIT: 4270 case GUEST_GS_LIMIT: 4271 case GUEST_LDTR_LIMIT: 4272 case GUEST_TR_LIMIT: 4273 case GUEST_GDTR_LIMIT: 4274 case GUEST_IDTR_LIMIT: 4275 case GUEST_ES_AR_BYTES: 4276 case GUEST_DS_AR_BYTES: 4277 case GUEST_FS_AR_BYTES: 4278 case GUEST_GS_AR_BYTES: 4279 case GUEST_LDTR_AR_BYTES: 4280 case GUEST_TR_AR_BYTES: 4281 case GUEST_ES_BASE: 4282 case GUEST_CS_BASE: 4283 case GUEST_SS_BASE: 4284 case GUEST_DS_BASE: 4285 case GUEST_FS_BASE: 4286 case GUEST_GS_BASE: 4287 case GUEST_LDTR_BASE: 4288 case GUEST_TR_BASE: 4289 case GUEST_GDTR_BASE: 4290 case GUEST_IDTR_BASE: 4291 case GUEST_PENDING_DBG_EXCEPTIONS: 4292 case GUEST_BNDCFGS: 4293 return true; 4294 default: 4295 break; 4296 } 4297 4298 return false; 4299 } 4300 4301 static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu, 4302 struct vmcs12 *vmcs12) 4303 { 4304 struct vcpu_vmx *vmx = to_vmx(vcpu); 4305 4306 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); 4307 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); 4308 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); 4309 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); 4310 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); 4311 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); 4312 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); 4313 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); 4314 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); 4315 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); 4316 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); 4317 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); 4318 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); 4319 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); 4320 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); 4321 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); 4322 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); 4323 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); 4324 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); 4325 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); 4326 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); 4327 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); 4328 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); 4329 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); 4330 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); 4331 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); 4332 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); 4333 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); 4334 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); 4335 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); 4336 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); 4337 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); 4338 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); 4339 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); 4340 vmcs12->guest_pending_dbg_exceptions = 4341 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); 4342 4343 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false; 4344 } 4345 4346 static void copy_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu, 4347 struct vmcs12 *vmcs12) 4348 { 4349 struct vcpu_vmx *vmx = to_vmx(vcpu); 4350 int cpu; 4351 4352 if (!vmx->nested.need_sync_vmcs02_to_vmcs12_rare) 4353 return; 4354 4355 4356 WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01); 4357 4358 cpu = get_cpu(); 4359 vmx->loaded_vmcs = &vmx->nested.vmcs02; 4360 vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->vmcs01); 4361 4362 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 4363 4364 vmx->loaded_vmcs = &vmx->vmcs01; 4365 vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->nested.vmcs02); 4366 put_cpu(); 4367 } 4368 4369 /* 4370 * Update the guest state fields of vmcs12 to reflect changes that 4371 * occurred while L2 was running. (The "IA-32e mode guest" bit of the 4372 * VM-entry controls is also updated, since this is really a guest 4373 * state bit.) 4374 */ 4375 static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 4376 { 4377 struct vcpu_vmx *vmx = to_vmx(vcpu); 4378 4379 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) 4380 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 4381 4382 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = 4383 !evmptr_is_valid(vmx->nested.hv_evmcs_vmptr); 4384 4385 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); 4386 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); 4387 4388 vmcs12->guest_rsp = kvm_rsp_read(vcpu); 4389 vmcs12->guest_rip = kvm_rip_read(vcpu); 4390 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); 4391 4392 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); 4393 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); 4394 4395 vmcs12->guest_interruptibility_info = 4396 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 4397 4398 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 4399 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; 4400 else if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4401 vmcs12->guest_activity_state = GUEST_ACTIVITY_WAIT_SIPI; 4402 else 4403 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; 4404 4405 if (nested_cpu_has_preemption_timer(vmcs12) && 4406 vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER && 4407 !vmx->nested.nested_run_pending) 4408 vmcs12->vmx_preemption_timer_value = 4409 vmx_get_preemption_timer_value(vcpu); 4410 4411 /* 4412 * In some cases (usually, nested EPT), L2 is allowed to change its 4413 * own CR3 without exiting. If it has changed it, we must keep it. 4414 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined 4415 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. 4416 * 4417 * Additionally, restore L2's PDPTR to vmcs12. 4418 */ 4419 if (enable_ept) { 4420 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); 4421 if (nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) { 4422 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); 4423 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); 4424 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); 4425 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); 4426 } 4427 } 4428 4429 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); 4430 4431 if (nested_cpu_has_vid(vmcs12)) 4432 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); 4433 4434 vmcs12->vm_entry_controls = 4435 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | 4436 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); 4437 4438 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) 4439 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); 4440 4441 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) 4442 vmcs12->guest_ia32_efer = vcpu->arch.efer; 4443 } 4444 4445 /* 4446 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits 4447 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), 4448 * and this function updates it to reflect the changes to the guest state while 4449 * L2 was running (and perhaps made some exits which were handled directly by L0 4450 * without going back to L1), and to reflect the exit reason. 4451 * Note that we do not have to copy here all VMCS fields, just those that 4452 * could have changed by the L2 guest or the exit - i.e., the guest-state and 4453 * exit-information fields only. Other fields are modified by L1 with VMWRITE, 4454 * which already writes to vmcs12 directly. 4455 */ 4456 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, 4457 u32 vm_exit_reason, u32 exit_intr_info, 4458 unsigned long exit_qualification) 4459 { 4460 /* update exit information fields: */ 4461 vmcs12->vm_exit_reason = vm_exit_reason; 4462 if (to_vmx(vcpu)->exit_reason.enclave_mode) 4463 vmcs12->vm_exit_reason |= VMX_EXIT_REASONS_SGX_ENCLAVE_MODE; 4464 vmcs12->exit_qualification = exit_qualification; 4465 4466 /* 4467 * On VM-Exit due to a failed VM-Entry, the VMCS isn't marked launched 4468 * and only EXIT_REASON and EXIT_QUALIFICATION are updated, all other 4469 * exit info fields are unmodified. 4470 */ 4471 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { 4472 vmcs12->launch_state = 1; 4473 4474 /* vm_entry_intr_info_field is cleared on exit. Emulate this 4475 * instead of reading the real value. */ 4476 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; 4477 4478 /* 4479 * Transfer the event that L0 or L1 may wanted to inject into 4480 * L2 to IDT_VECTORING_INFO_FIELD. 4481 */ 4482 vmcs12_save_pending_event(vcpu, vmcs12, 4483 vm_exit_reason, exit_intr_info); 4484 4485 vmcs12->vm_exit_intr_info = exit_intr_info; 4486 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4487 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 4488 4489 /* 4490 * According to spec, there's no need to store the guest's 4491 * MSRs if the exit is due to a VM-entry failure that occurs 4492 * during or after loading the guest state. Since this exit 4493 * does not fall in that category, we need to save the MSRs. 4494 */ 4495 if (nested_vmx_store_msr(vcpu, 4496 vmcs12->vm_exit_msr_store_addr, 4497 vmcs12->vm_exit_msr_store_count)) 4498 nested_vmx_abort(vcpu, 4499 VMX_ABORT_SAVE_GUEST_MSR_FAIL); 4500 } 4501 } 4502 4503 /* 4504 * A part of what we need to when the nested L2 guest exits and we want to 4505 * run its L1 parent, is to reset L1's guest state to the host state specified 4506 * in vmcs12. 4507 * This function is to be called not only on normal nested exit, but also on 4508 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry 4509 * Failures During or After Loading Guest State"). 4510 * This function should be called when the active VMCS is L1's (vmcs01). 4511 */ 4512 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, 4513 struct vmcs12 *vmcs12) 4514 { 4515 enum vm_entry_failure_code ignored; 4516 struct kvm_segment seg; 4517 4518 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) 4519 vcpu->arch.efer = vmcs12->host_ia32_efer; 4520 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) 4521 vcpu->arch.efer |= (EFER_LMA | EFER_LME); 4522 else 4523 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); 4524 vmx_set_efer(vcpu, vcpu->arch.efer); 4525 4526 kvm_rsp_write(vcpu, vmcs12->host_rsp); 4527 kvm_rip_write(vcpu, vmcs12->host_rip); 4528 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); 4529 vmx_set_interrupt_shadow(vcpu, 0); 4530 4531 /* 4532 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't 4533 * actually changed, because vmx_set_cr0 refers to efer set above. 4534 * 4535 * CR0_GUEST_HOST_MASK is already set in the original vmcs01 4536 * (KVM doesn't change it); 4537 */ 4538 vcpu->arch.cr0_guest_owned_bits = vmx_l1_guest_owned_cr0_bits(); 4539 vmx_set_cr0(vcpu, vmcs12->host_cr0); 4540 4541 /* Same as above - no reason to call set_cr4_guest_host_mask(). */ 4542 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); 4543 vmx_set_cr4(vcpu, vmcs12->host_cr4); 4544 4545 nested_ept_uninit_mmu_context(vcpu); 4546 4547 /* 4548 * Only PDPTE load can fail as the value of cr3 was checked on entry and 4549 * couldn't have changed. 4550 */ 4551 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, true, &ignored)) 4552 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); 4553 4554 nested_vmx_transition_tlb_flush(vcpu, vmcs12, false); 4555 4556 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); 4557 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); 4558 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); 4559 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); 4560 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); 4561 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF); 4562 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF); 4563 4564 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ 4565 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) 4566 vmcs_write64(GUEST_BNDCFGS, 0); 4567 4568 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { 4569 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); 4570 vcpu->arch.pat = vmcs12->host_ia32_pat; 4571 } 4572 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) && 4573 kvm_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu))) 4574 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, 4575 vmcs12->host_ia32_perf_global_ctrl)); 4576 4577 /* Set L1 segment info according to Intel SDM 4578 27.5.2 Loading Host Segment and Descriptor-Table Registers */ 4579 seg = (struct kvm_segment) { 4580 .base = 0, 4581 .limit = 0xFFFFFFFF, 4582 .selector = vmcs12->host_cs_selector, 4583 .type = 11, 4584 .present = 1, 4585 .s = 1, 4586 .g = 1 4587 }; 4588 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) 4589 seg.l = 1; 4590 else 4591 seg.db = 1; 4592 __vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); 4593 seg = (struct kvm_segment) { 4594 .base = 0, 4595 .limit = 0xFFFFFFFF, 4596 .type = 3, 4597 .present = 1, 4598 .s = 1, 4599 .db = 1, 4600 .g = 1 4601 }; 4602 seg.selector = vmcs12->host_ds_selector; 4603 __vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); 4604 seg.selector = vmcs12->host_es_selector; 4605 __vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); 4606 seg.selector = vmcs12->host_ss_selector; 4607 __vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); 4608 seg.selector = vmcs12->host_fs_selector; 4609 seg.base = vmcs12->host_fs_base; 4610 __vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); 4611 seg.selector = vmcs12->host_gs_selector; 4612 seg.base = vmcs12->host_gs_base; 4613 __vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); 4614 seg = (struct kvm_segment) { 4615 .base = vmcs12->host_tr_base, 4616 .limit = 0x67, 4617 .selector = vmcs12->host_tr_selector, 4618 .type = 11, 4619 .present = 1 4620 }; 4621 __vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); 4622 4623 memset(&seg, 0, sizeof(seg)); 4624 seg.unusable = 1; 4625 __vmx_set_segment(vcpu, &seg, VCPU_SREG_LDTR); 4626 4627 kvm_set_dr(vcpu, 7, 0x400); 4628 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4629 4630 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, 4631 vmcs12->vm_exit_msr_load_count)) 4632 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); 4633 4634 to_vmx(vcpu)->emulation_required = vmx_emulation_required(vcpu); 4635 } 4636 4637 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx) 4638 { 4639 struct vmx_uret_msr *efer_msr; 4640 unsigned int i; 4641 4642 if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER) 4643 return vmcs_read64(GUEST_IA32_EFER); 4644 4645 if (cpu_has_load_ia32_efer()) 4646 return host_efer; 4647 4648 for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) { 4649 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER) 4650 return vmx->msr_autoload.guest.val[i].value; 4651 } 4652 4653 efer_msr = vmx_find_uret_msr(vmx, MSR_EFER); 4654 if (efer_msr) 4655 return efer_msr->data; 4656 4657 return host_efer; 4658 } 4659 4660 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu) 4661 { 4662 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4663 struct vcpu_vmx *vmx = to_vmx(vcpu); 4664 struct vmx_msr_entry g, h; 4665 gpa_t gpa; 4666 u32 i, j; 4667 4668 vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT); 4669 4670 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { 4671 /* 4672 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set 4673 * as vmcs01.GUEST_DR7 contains a userspace defined value 4674 * and vcpu->arch.dr7 is not squirreled away before the 4675 * nested VMENTER (not worth adding a variable in nested_vmx). 4676 */ 4677 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 4678 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 4679 else 4680 WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7))); 4681 } 4682 4683 /* 4684 * Note that calling vmx_set_{efer,cr0,cr4} is important as they 4685 * handle a variety of side effects to KVM's software model. 4686 */ 4687 vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx)); 4688 4689 vcpu->arch.cr0_guest_owned_bits = vmx_l1_guest_owned_cr0_bits(); 4690 vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW)); 4691 4692 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); 4693 vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW)); 4694 4695 nested_ept_uninit_mmu_context(vcpu); 4696 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 4697 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 4698 4699 /* 4700 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs 4701 * from vmcs01 (if necessary). The PDPTRs are not loaded on 4702 * VMFail, like everything else we just need to ensure our 4703 * software model is up-to-date. 4704 */ 4705 if (enable_ept && is_pae_paging(vcpu)) 4706 ept_save_pdptrs(vcpu); 4707 4708 kvm_mmu_reset_context(vcpu); 4709 4710 /* 4711 * This nasty bit of open coding is a compromise between blindly 4712 * loading L1's MSRs using the exit load lists (incorrect emulation 4713 * of VMFail), leaving the nested VM's MSRs in the software model 4714 * (incorrect behavior) and snapshotting the modified MSRs (too 4715 * expensive since the lists are unbound by hardware). For each 4716 * MSR that was (prematurely) loaded from the nested VMEntry load 4717 * list, reload it from the exit load list if it exists and differs 4718 * from the guest value. The intent is to stuff host state as 4719 * silently as possible, not to fully process the exit load list. 4720 */ 4721 for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) { 4722 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g)); 4723 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) { 4724 pr_debug_ratelimited( 4725 "%s read MSR index failed (%u, 0x%08llx)\n", 4726 __func__, i, gpa); 4727 goto vmabort; 4728 } 4729 4730 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) { 4731 gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h)); 4732 if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) { 4733 pr_debug_ratelimited( 4734 "%s read MSR failed (%u, 0x%08llx)\n", 4735 __func__, j, gpa); 4736 goto vmabort; 4737 } 4738 if (h.index != g.index) 4739 continue; 4740 if (h.value == g.value) 4741 break; 4742 4743 if (nested_vmx_load_msr_check(vcpu, &h)) { 4744 pr_debug_ratelimited( 4745 "%s check failed (%u, 0x%x, 0x%x)\n", 4746 __func__, j, h.index, h.reserved); 4747 goto vmabort; 4748 } 4749 4750 if (kvm_set_msr(vcpu, h.index, h.value)) { 4751 pr_debug_ratelimited( 4752 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n", 4753 __func__, j, h.index, h.value); 4754 goto vmabort; 4755 } 4756 } 4757 } 4758 4759 return; 4760 4761 vmabort: 4762 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); 4763 } 4764 4765 /* 4766 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 4767 * and modify vmcs12 to make it see what it would expect to see there if 4768 * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) 4769 */ 4770 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, 4771 u32 exit_intr_info, unsigned long exit_qualification) 4772 { 4773 struct vcpu_vmx *vmx = to_vmx(vcpu); 4774 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4775 4776 /* Pending MTF traps are discarded on VM-Exit. */ 4777 vmx->nested.mtf_pending = false; 4778 4779 /* trying to cancel vmlaunch/vmresume is a bug */ 4780 WARN_ON_ONCE(vmx->nested.nested_run_pending); 4781 4782 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 4783 /* 4784 * KVM_REQ_GET_NESTED_STATE_PAGES is also used to map 4785 * Enlightened VMCS after migration and we still need to 4786 * do that when something is forcing L2->L1 exit prior to 4787 * the first L2 run. 4788 */ 4789 (void)nested_get_evmcs_page(vcpu); 4790 } 4791 4792 /* Service pending TLB flush requests for L2 before switching to L1. */ 4793 kvm_service_local_tlb_flush_requests(vcpu); 4794 4795 /* 4796 * VCPU_EXREG_PDPTR will be clobbered in arch/x86/kvm/vmx/vmx.h between 4797 * now and the new vmentry. Ensure that the VMCS02 PDPTR fields are 4798 * up-to-date before switching to L1. 4799 */ 4800 if (enable_ept && is_pae_paging(vcpu)) 4801 vmx_ept_load_pdptrs(vcpu); 4802 4803 leave_guest_mode(vcpu); 4804 4805 if (nested_cpu_has_preemption_timer(vmcs12)) 4806 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); 4807 4808 if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING)) { 4809 vcpu->arch.tsc_offset = vcpu->arch.l1_tsc_offset; 4810 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING)) 4811 vcpu->arch.tsc_scaling_ratio = vcpu->arch.l1_tsc_scaling_ratio; 4812 } 4813 4814 if (likely(!vmx->fail)) { 4815 sync_vmcs02_to_vmcs12(vcpu, vmcs12); 4816 4817 if (vm_exit_reason != -1) 4818 prepare_vmcs12(vcpu, vmcs12, vm_exit_reason, 4819 exit_intr_info, exit_qualification); 4820 4821 /* 4822 * Must happen outside of sync_vmcs02_to_vmcs12() as it will 4823 * also be used to capture vmcs12 cache as part of 4824 * capturing nVMX state for snapshot (migration). 4825 * 4826 * Otherwise, this flush will dirty guest memory at a 4827 * point it is already assumed by user-space to be 4828 * immutable. 4829 */ 4830 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12); 4831 } else { 4832 /* 4833 * The only expected VM-instruction error is "VM entry with 4834 * invalid control field(s)." Anything else indicates a 4835 * problem with L0. And we should never get here with a 4836 * VMFail of any type if early consistency checks are enabled. 4837 */ 4838 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) != 4839 VMXERR_ENTRY_INVALID_CONTROL_FIELD); 4840 WARN_ON_ONCE(nested_early_check); 4841 } 4842 4843 /* 4844 * Drop events/exceptions that were queued for re-injection to L2 4845 * (picked up via vmx_complete_interrupts()), as well as exceptions 4846 * that were pending for L2. Note, this must NOT be hoisted above 4847 * prepare_vmcs12(), events/exceptions queued for re-injection need to 4848 * be captured in vmcs12 (see vmcs12_save_pending_event()). 4849 */ 4850 vcpu->arch.nmi_injected = false; 4851 kvm_clear_exception_queue(vcpu); 4852 kvm_clear_interrupt_queue(vcpu); 4853 4854 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 4855 4856 /* 4857 * If IBRS is advertised to the vCPU, KVM must flush the indirect 4858 * branch predictors when transitioning from L2 to L1, as L1 expects 4859 * hardware (KVM in this case) to provide separate predictor modes. 4860 * Bare metal isolates VMX root (host) from VMX non-root (guest), but 4861 * doesn't isolate different VMCSs, i.e. in this case, doesn't provide 4862 * separate modes for L2 vs L1. 4863 */ 4864 if (guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 4865 indirect_branch_prediction_barrier(); 4866 4867 /* Update any VMCS fields that might have changed while L2 ran */ 4868 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 4869 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 4870 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); 4871 if (kvm_caps.has_tsc_control) 4872 vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio); 4873 4874 if (vmx->nested.l1_tpr_threshold != -1) 4875 vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold); 4876 4877 if (vmx->nested.change_vmcs01_virtual_apic_mode) { 4878 vmx->nested.change_vmcs01_virtual_apic_mode = false; 4879 vmx_set_virtual_apic_mode(vcpu); 4880 } 4881 4882 if (vmx->nested.update_vmcs01_cpu_dirty_logging) { 4883 vmx->nested.update_vmcs01_cpu_dirty_logging = false; 4884 vmx_update_cpu_dirty_logging(vcpu); 4885 } 4886 4887 /* Unpin physical memory we referred to in vmcs02 */ 4888 kvm_vcpu_unmap(vcpu, &vmx->nested.apic_access_page_map, false); 4889 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true); 4890 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true); 4891 vmx->nested.pi_desc = NULL; 4892 4893 if (vmx->nested.reload_vmcs01_apic_access_page) { 4894 vmx->nested.reload_vmcs01_apic_access_page = false; 4895 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4896 } 4897 4898 if (vmx->nested.update_vmcs01_apicv_status) { 4899 vmx->nested.update_vmcs01_apicv_status = false; 4900 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); 4901 } 4902 4903 if ((vm_exit_reason != -1) && 4904 (enable_shadow_vmcs || evmptr_is_valid(vmx->nested.hv_evmcs_vmptr))) 4905 vmx->nested.need_vmcs12_to_shadow_sync = true; 4906 4907 /* in case we halted in L2 */ 4908 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 4909 4910 if (likely(!vmx->fail)) { 4911 if ((u16)vm_exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && 4912 nested_exit_intr_ack_set(vcpu)) { 4913 int irq = kvm_cpu_get_interrupt(vcpu); 4914 WARN_ON(irq < 0); 4915 vmcs12->vm_exit_intr_info = irq | 4916 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; 4917 } 4918 4919 if (vm_exit_reason != -1) 4920 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, 4921 vmcs12->exit_qualification, 4922 vmcs12->idt_vectoring_info_field, 4923 vmcs12->vm_exit_intr_info, 4924 vmcs12->vm_exit_intr_error_code, 4925 KVM_ISA_VMX); 4926 4927 load_vmcs12_host_state(vcpu, vmcs12); 4928 4929 return; 4930 } 4931 4932 /* 4933 * After an early L2 VM-entry failure, we're now back 4934 * in L1 which thinks it just finished a VMLAUNCH or 4935 * VMRESUME instruction, so we need to set the failure 4936 * flag and the VM-instruction error field of the VMCS 4937 * accordingly, and skip the emulated instruction. 4938 */ 4939 (void)nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 4940 4941 /* 4942 * Restore L1's host state to KVM's software model. We're here 4943 * because a consistency check was caught by hardware, which 4944 * means some amount of guest state has been propagated to KVM's 4945 * model and needs to be unwound to the host's state. 4946 */ 4947 nested_vmx_restore_host_state(vcpu); 4948 4949 vmx->fail = 0; 4950 } 4951 4952 static void nested_vmx_triple_fault(struct kvm_vcpu *vcpu) 4953 { 4954 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4955 nested_vmx_vmexit(vcpu, EXIT_REASON_TRIPLE_FAULT, 0, 0); 4956 } 4957 4958 /* 4959 * Decode the memory-address operand of a vmx instruction, as recorded on an 4960 * exit caused by such an instruction (run by a guest hypervisor). 4961 * On success, returns 0. When the operand is invalid, returns 1 and throws 4962 * #UD, #GP, or #SS. 4963 */ 4964 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, 4965 u32 vmx_instruction_info, bool wr, int len, gva_t *ret) 4966 { 4967 gva_t off; 4968 bool exn; 4969 struct kvm_segment s; 4970 4971 /* 4972 * According to Vol. 3B, "Information for VM Exits Due to Instruction 4973 * Execution", on an exit, vmx_instruction_info holds most of the 4974 * addressing components of the operand. Only the displacement part 4975 * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). 4976 * For how an actual address is calculated from all these components, 4977 * refer to Vol. 1, "Operand Addressing". 4978 */ 4979 int scaling = vmx_instruction_info & 3; 4980 int addr_size = (vmx_instruction_info >> 7) & 7; 4981 bool is_reg = vmx_instruction_info & (1u << 10); 4982 int seg_reg = (vmx_instruction_info >> 15) & 7; 4983 int index_reg = (vmx_instruction_info >> 18) & 0xf; 4984 bool index_is_valid = !(vmx_instruction_info & (1u << 22)); 4985 int base_reg = (vmx_instruction_info >> 23) & 0xf; 4986 bool base_is_valid = !(vmx_instruction_info & (1u << 27)); 4987 4988 if (is_reg) { 4989 kvm_queue_exception(vcpu, UD_VECTOR); 4990 return 1; 4991 } 4992 4993 /* Addr = segment_base + offset */ 4994 /* offset = base + [index * scale] + displacement */ 4995 off = exit_qualification; /* holds the displacement */ 4996 if (addr_size == 1) 4997 off = (gva_t)sign_extend64(off, 31); 4998 else if (addr_size == 0) 4999 off = (gva_t)sign_extend64(off, 15); 5000 if (base_is_valid) 5001 off += kvm_register_read(vcpu, base_reg); 5002 if (index_is_valid) 5003 off += kvm_register_read(vcpu, index_reg) << scaling; 5004 vmx_get_segment(vcpu, &s, seg_reg); 5005 5006 /* 5007 * The effective address, i.e. @off, of a memory operand is truncated 5008 * based on the address size of the instruction. Note that this is 5009 * the *effective address*, i.e. the address prior to accounting for 5010 * the segment's base. 5011 */ 5012 if (addr_size == 1) /* 32 bit */ 5013 off &= 0xffffffff; 5014 else if (addr_size == 0) /* 16 bit */ 5015 off &= 0xffff; 5016 5017 /* Checks for #GP/#SS exceptions. */ 5018 exn = false; 5019 if (is_long_mode(vcpu)) { 5020 /* 5021 * The virtual/linear address is never truncated in 64-bit 5022 * mode, e.g. a 32-bit address size can yield a 64-bit virtual 5023 * address when using FS/GS with a non-zero base. 5024 */ 5025 if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS) 5026 *ret = s.base + off; 5027 else 5028 *ret = off; 5029 5030 /* Long mode: #GP(0)/#SS(0) if the memory address is in a 5031 * non-canonical form. This is the only check on the memory 5032 * destination for long mode! 5033 */ 5034 exn = is_noncanonical_address(*ret, vcpu); 5035 } else { 5036 /* 5037 * When not in long mode, the virtual/linear address is 5038 * unconditionally truncated to 32 bits regardless of the 5039 * address size. 5040 */ 5041 *ret = (s.base + off) & 0xffffffff; 5042 5043 /* Protected mode: apply checks for segment validity in the 5044 * following order: 5045 * - segment type check (#GP(0) may be thrown) 5046 * - usability check (#GP(0)/#SS(0)) 5047 * - limit check (#GP(0)/#SS(0)) 5048 */ 5049 if (wr) 5050 /* #GP(0) if the destination operand is located in a 5051 * read-only data segment or any code segment. 5052 */ 5053 exn = ((s.type & 0xa) == 0 || (s.type & 8)); 5054 else 5055 /* #GP(0) if the source operand is located in an 5056 * execute-only code segment 5057 */ 5058 exn = ((s.type & 0xa) == 8); 5059 if (exn) { 5060 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 5061 return 1; 5062 } 5063 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. 5064 */ 5065 exn = (s.unusable != 0); 5066 5067 /* 5068 * Protected mode: #GP(0)/#SS(0) if the memory operand is 5069 * outside the segment limit. All CPUs that support VMX ignore 5070 * limit checks for flat segments, i.e. segments with base==0, 5071 * limit==0xffffffff and of type expand-up data or code. 5072 */ 5073 if (!(s.base == 0 && s.limit == 0xffffffff && 5074 ((s.type & 8) || !(s.type & 4)))) 5075 exn = exn || ((u64)off + len - 1 > s.limit); 5076 } 5077 if (exn) { 5078 kvm_queue_exception_e(vcpu, 5079 seg_reg == VCPU_SREG_SS ? 5080 SS_VECTOR : GP_VECTOR, 5081 0); 5082 return 1; 5083 } 5084 5085 return 0; 5086 } 5087 5088 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer, 5089 int *ret) 5090 { 5091 gva_t gva; 5092 struct x86_exception e; 5093 int r; 5094 5095 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), 5096 vmcs_read32(VMX_INSTRUCTION_INFO), false, 5097 sizeof(*vmpointer), &gva)) { 5098 *ret = 1; 5099 return -EINVAL; 5100 } 5101 5102 r = kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e); 5103 if (r != X86EMUL_CONTINUE) { 5104 *ret = kvm_handle_memory_failure(vcpu, r, &e); 5105 return -EINVAL; 5106 } 5107 5108 return 0; 5109 } 5110 5111 /* 5112 * Allocate a shadow VMCS and associate it with the currently loaded 5113 * VMCS, unless such a shadow VMCS already exists. The newly allocated 5114 * VMCS is also VMCLEARed, so that it is ready for use. 5115 */ 5116 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu) 5117 { 5118 struct vcpu_vmx *vmx = to_vmx(vcpu); 5119 struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs; 5120 5121 /* 5122 * KVM allocates a shadow VMCS only when L1 executes VMXON and frees it 5123 * when L1 executes VMXOFF or the vCPU is forced out of nested 5124 * operation. VMXON faults if the CPU is already post-VMXON, so it 5125 * should be impossible to already have an allocated shadow VMCS. KVM 5126 * doesn't support virtualization of VMCS shadowing, so vmcs01 should 5127 * always be the loaded VMCS. 5128 */ 5129 if (WARN_ON(loaded_vmcs != &vmx->vmcs01 || loaded_vmcs->shadow_vmcs)) 5130 return loaded_vmcs->shadow_vmcs; 5131 5132 loaded_vmcs->shadow_vmcs = alloc_vmcs(true); 5133 if (loaded_vmcs->shadow_vmcs) 5134 vmcs_clear(loaded_vmcs->shadow_vmcs); 5135 5136 return loaded_vmcs->shadow_vmcs; 5137 } 5138 5139 static int enter_vmx_operation(struct kvm_vcpu *vcpu) 5140 { 5141 struct vcpu_vmx *vmx = to_vmx(vcpu); 5142 int r; 5143 5144 r = alloc_loaded_vmcs(&vmx->nested.vmcs02); 5145 if (r < 0) 5146 goto out_vmcs02; 5147 5148 vmx->nested.cached_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT); 5149 if (!vmx->nested.cached_vmcs12) 5150 goto out_cached_vmcs12; 5151 5152 vmx->nested.shadow_vmcs12_cache.gpa = INVALID_GPA; 5153 vmx->nested.cached_shadow_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT); 5154 if (!vmx->nested.cached_shadow_vmcs12) 5155 goto out_cached_shadow_vmcs12; 5156 5157 if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu)) 5158 goto out_shadow_vmcs; 5159 5160 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, 5161 HRTIMER_MODE_ABS_PINNED); 5162 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; 5163 5164 vmx->nested.vpid02 = allocate_vpid(); 5165 5166 vmx->nested.vmcs02_initialized = false; 5167 vmx->nested.vmxon = true; 5168 5169 if (vmx_pt_mode_is_host_guest()) { 5170 vmx->pt_desc.guest.ctl = 0; 5171 pt_update_intercept_for_msr(vcpu); 5172 } 5173 5174 return 0; 5175 5176 out_shadow_vmcs: 5177 kfree(vmx->nested.cached_shadow_vmcs12); 5178 5179 out_cached_shadow_vmcs12: 5180 kfree(vmx->nested.cached_vmcs12); 5181 5182 out_cached_vmcs12: 5183 free_loaded_vmcs(&vmx->nested.vmcs02); 5184 5185 out_vmcs02: 5186 return -ENOMEM; 5187 } 5188 5189 /* Emulate the VMXON instruction. */ 5190 static int handle_vmxon(struct kvm_vcpu *vcpu) 5191 { 5192 int ret; 5193 gpa_t vmptr; 5194 uint32_t revision; 5195 struct vcpu_vmx *vmx = to_vmx(vcpu); 5196 const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED 5197 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 5198 5199 /* 5200 * Manually check CR4.VMXE checks, KVM must force CR4.VMXE=1 to enter 5201 * the guest and so cannot rely on hardware to perform the check, 5202 * which has higher priority than VM-Exit (see Intel SDM's pseudocode 5203 * for VMXON). 5204 * 5205 * Rely on hardware for the other pre-VM-Exit checks, CR0.PE=1, !VM86 5206 * and !COMPATIBILITY modes. For an unrestricted guest, KVM doesn't 5207 * force any of the relevant guest state. For a restricted guest, KVM 5208 * does force CR0.PE=1, but only to also force VM86 in order to emulate 5209 * Real Mode, and so there's no need to check CR0.PE manually. 5210 */ 5211 if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_VMXE)) { 5212 kvm_queue_exception(vcpu, UD_VECTOR); 5213 return 1; 5214 } 5215 5216 /* 5217 * The CPL is checked for "not in VMX operation" and for "in VMX root", 5218 * and has higher priority than the VM-Fail due to being post-VMXON, 5219 * i.e. VMXON #GPs outside of VMX non-root if CPL!=0. In VMX non-root, 5220 * VMXON causes VM-Exit and KVM unconditionally forwards VMXON VM-Exits 5221 * from L2 to L1, i.e. there's no need to check for the vCPU being in 5222 * VMX non-root. 5223 * 5224 * Forwarding the VM-Exit unconditionally, i.e. without performing the 5225 * #UD checks (see above), is functionally ok because KVM doesn't allow 5226 * L1 to run L2 without CR4.VMXE=0, and because KVM never modifies L2's 5227 * CR0 or CR4, i.e. it's L2's responsibility to emulate #UDs that are 5228 * missed by hardware due to shadowing CR0 and/or CR4. 5229 */ 5230 if (vmx_get_cpl(vcpu)) { 5231 kvm_inject_gp(vcpu, 0); 5232 return 1; 5233 } 5234 5235 if (vmx->nested.vmxon) 5236 return nested_vmx_fail(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); 5237 5238 /* 5239 * Invalid CR0/CR4 generates #GP. These checks are performed if and 5240 * only if the vCPU isn't already in VMX operation, i.e. effectively 5241 * have lower priority than the VM-Fail above. 5242 */ 5243 if (!nested_host_cr0_valid(vcpu, kvm_read_cr0(vcpu)) || 5244 !nested_host_cr4_valid(vcpu, kvm_read_cr4(vcpu))) { 5245 kvm_inject_gp(vcpu, 0); 5246 return 1; 5247 } 5248 5249 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) 5250 != VMXON_NEEDED_FEATURES) { 5251 kvm_inject_gp(vcpu, 0); 5252 return 1; 5253 } 5254 5255 if (nested_vmx_get_vmptr(vcpu, &vmptr, &ret)) 5256 return ret; 5257 5258 /* 5259 * SDM 3: 24.11.5 5260 * The first 4 bytes of VMXON region contain the supported 5261 * VMCS revision identifier 5262 * 5263 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; 5264 * which replaces physical address width with 32 5265 */ 5266 if (!page_address_valid(vcpu, vmptr)) 5267 return nested_vmx_failInvalid(vcpu); 5268 5269 if (kvm_read_guest(vcpu->kvm, vmptr, &revision, sizeof(revision)) || 5270 revision != VMCS12_REVISION) 5271 return nested_vmx_failInvalid(vcpu); 5272 5273 vmx->nested.vmxon_ptr = vmptr; 5274 ret = enter_vmx_operation(vcpu); 5275 if (ret) 5276 return ret; 5277 5278 return nested_vmx_succeed(vcpu); 5279 } 5280 5281 static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu) 5282 { 5283 struct vcpu_vmx *vmx = to_vmx(vcpu); 5284 5285 if (vmx->nested.current_vmptr == INVALID_GPA) 5286 return; 5287 5288 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu)); 5289 5290 if (enable_shadow_vmcs) { 5291 /* copy to memory all shadowed fields in case 5292 they were modified */ 5293 copy_shadow_to_vmcs12(vmx); 5294 vmx_disable_shadow_vmcs(vmx); 5295 } 5296 vmx->nested.posted_intr_nv = -1; 5297 5298 /* Flush VMCS12 to guest memory */ 5299 kvm_vcpu_write_guest_page(vcpu, 5300 vmx->nested.current_vmptr >> PAGE_SHIFT, 5301 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); 5302 5303 kvm_mmu_free_roots(vcpu->kvm, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); 5304 5305 vmx->nested.current_vmptr = INVALID_GPA; 5306 } 5307 5308 /* Emulate the VMXOFF instruction */ 5309 static int handle_vmxoff(struct kvm_vcpu *vcpu) 5310 { 5311 if (!nested_vmx_check_permission(vcpu)) 5312 return 1; 5313 5314 free_nested(vcpu); 5315 5316 if (kvm_apic_has_pending_init_or_sipi(vcpu)) 5317 kvm_make_request(KVM_REQ_EVENT, vcpu); 5318 5319 return nested_vmx_succeed(vcpu); 5320 } 5321 5322 /* Emulate the VMCLEAR instruction */ 5323 static int handle_vmclear(struct kvm_vcpu *vcpu) 5324 { 5325 struct vcpu_vmx *vmx = to_vmx(vcpu); 5326 u32 zero = 0; 5327 gpa_t vmptr; 5328 int r; 5329 5330 if (!nested_vmx_check_permission(vcpu)) 5331 return 1; 5332 5333 if (nested_vmx_get_vmptr(vcpu, &vmptr, &r)) 5334 return r; 5335 5336 if (!page_address_valid(vcpu, vmptr)) 5337 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); 5338 5339 if (vmptr == vmx->nested.vmxon_ptr) 5340 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); 5341 5342 /* 5343 * When Enlightened VMEntry is enabled on the calling CPU we treat 5344 * memory area pointer by vmptr as Enlightened VMCS (as there's no good 5345 * way to distinguish it from VMCS12) and we must not corrupt it by 5346 * writing to the non-existent 'launch_state' field. The area doesn't 5347 * have to be the currently active EVMCS on the calling CPU and there's 5348 * nothing KVM has to do to transition it from 'active' to 'non-active' 5349 * state. It is possible that the area will stay mapped as 5350 * vmx->nested.hv_evmcs but this shouldn't be a problem. 5351 */ 5352 if (likely(!guest_cpuid_has_evmcs(vcpu) || 5353 !evmptr_is_valid(nested_get_evmptr(vcpu)))) { 5354 if (vmptr == vmx->nested.current_vmptr) 5355 nested_release_vmcs12(vcpu); 5356 5357 /* 5358 * Silently ignore memory errors on VMCLEAR, Intel's pseudocode 5359 * for VMCLEAR includes a "ensure that data for VMCS referenced 5360 * by the operand is in memory" clause that guards writes to 5361 * memory, i.e. doing nothing for I/O is architecturally valid. 5362 * 5363 * FIXME: Suppress failures if and only if no memslot is found, 5364 * i.e. exit to userspace if __copy_to_user() fails. 5365 */ 5366 (void)kvm_vcpu_write_guest(vcpu, 5367 vmptr + offsetof(struct vmcs12, 5368 launch_state), 5369 &zero, sizeof(zero)); 5370 } else if (vmx->nested.hv_evmcs && vmptr == vmx->nested.hv_evmcs_vmptr) { 5371 nested_release_evmcs(vcpu); 5372 } 5373 5374 return nested_vmx_succeed(vcpu); 5375 } 5376 5377 /* Emulate the VMLAUNCH instruction */ 5378 static int handle_vmlaunch(struct kvm_vcpu *vcpu) 5379 { 5380 return nested_vmx_run(vcpu, true); 5381 } 5382 5383 /* Emulate the VMRESUME instruction */ 5384 static int handle_vmresume(struct kvm_vcpu *vcpu) 5385 { 5386 5387 return nested_vmx_run(vcpu, false); 5388 } 5389 5390 static int handle_vmread(struct kvm_vcpu *vcpu) 5391 { 5392 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu) 5393 : get_vmcs12(vcpu); 5394 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5395 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5396 struct vcpu_vmx *vmx = to_vmx(vcpu); 5397 struct x86_exception e; 5398 unsigned long field; 5399 u64 value; 5400 gva_t gva = 0; 5401 short offset; 5402 int len, r; 5403 5404 if (!nested_vmx_check_permission(vcpu)) 5405 return 1; 5406 5407 /* Decode instruction info and find the field to read */ 5408 field = kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf)); 5409 5410 if (!evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) { 5411 /* 5412 * In VMX non-root operation, when the VMCS-link pointer is INVALID_GPA, 5413 * any VMREAD sets the ALU flags for VMfailInvalid. 5414 */ 5415 if (vmx->nested.current_vmptr == INVALID_GPA || 5416 (is_guest_mode(vcpu) && 5417 get_vmcs12(vcpu)->vmcs_link_pointer == INVALID_GPA)) 5418 return nested_vmx_failInvalid(vcpu); 5419 5420 offset = get_vmcs12_field_offset(field); 5421 if (offset < 0) 5422 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5423 5424 if (!is_guest_mode(vcpu) && is_vmcs12_ext_field(field)) 5425 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 5426 5427 /* Read the field, zero-extended to a u64 value */ 5428 value = vmcs12_read_any(vmcs12, field, offset); 5429 } else { 5430 /* 5431 * Hyper-V TLFS (as of 6.0b) explicitly states, that while an 5432 * enlightened VMCS is active VMREAD/VMWRITE instructions are 5433 * unsupported. Unfortunately, certain versions of Windows 11 5434 * don't comply with this requirement which is not enforced in 5435 * genuine Hyper-V. Allow VMREAD from an enlightened VMCS as a 5436 * workaround, as misbehaving guests will panic on VM-Fail. 5437 * Note, enlightened VMCS is incompatible with shadow VMCS so 5438 * all VMREADs from L2 should go to L1. 5439 */ 5440 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 5441 return nested_vmx_failInvalid(vcpu); 5442 5443 offset = evmcs_field_offset(field, NULL); 5444 if (offset < 0) 5445 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5446 5447 /* Read the field, zero-extended to a u64 value */ 5448 value = evmcs_read_any(vmx->nested.hv_evmcs, field, offset); 5449 } 5450 5451 /* 5452 * Now copy part of this value to register or memory, as requested. 5453 * Note that the number of bits actually copied is 32 or 64 depending 5454 * on the guest's mode (32 or 64 bit), not on the given field's length. 5455 */ 5456 if (instr_info & BIT(10)) { 5457 kvm_register_write(vcpu, (((instr_info) >> 3) & 0xf), value); 5458 } else { 5459 len = is_64_bit_mode(vcpu) ? 8 : 4; 5460 if (get_vmx_mem_address(vcpu, exit_qualification, 5461 instr_info, true, len, &gva)) 5462 return 1; 5463 /* _system ok, nested_vmx_check_permission has verified cpl=0 */ 5464 r = kvm_write_guest_virt_system(vcpu, gva, &value, len, &e); 5465 if (r != X86EMUL_CONTINUE) 5466 return kvm_handle_memory_failure(vcpu, r, &e); 5467 } 5468 5469 return nested_vmx_succeed(vcpu); 5470 } 5471 5472 static bool is_shadow_field_rw(unsigned long field) 5473 { 5474 switch (field) { 5475 #define SHADOW_FIELD_RW(x, y) case x: 5476 #include "vmcs_shadow_fields.h" 5477 return true; 5478 default: 5479 break; 5480 } 5481 return false; 5482 } 5483 5484 static bool is_shadow_field_ro(unsigned long field) 5485 { 5486 switch (field) { 5487 #define SHADOW_FIELD_RO(x, y) case x: 5488 #include "vmcs_shadow_fields.h" 5489 return true; 5490 default: 5491 break; 5492 } 5493 return false; 5494 } 5495 5496 static int handle_vmwrite(struct kvm_vcpu *vcpu) 5497 { 5498 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu) 5499 : get_vmcs12(vcpu); 5500 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5501 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5502 struct vcpu_vmx *vmx = to_vmx(vcpu); 5503 struct x86_exception e; 5504 unsigned long field; 5505 short offset; 5506 gva_t gva; 5507 int len, r; 5508 5509 /* 5510 * The value to write might be 32 or 64 bits, depending on L1's long 5511 * mode, and eventually we need to write that into a field of several 5512 * possible lengths. The code below first zero-extends the value to 64 5513 * bit (value), and then copies only the appropriate number of 5514 * bits into the vmcs12 field. 5515 */ 5516 u64 value = 0; 5517 5518 if (!nested_vmx_check_permission(vcpu)) 5519 return 1; 5520 5521 /* 5522 * In VMX non-root operation, when the VMCS-link pointer is INVALID_GPA, 5523 * any VMWRITE sets the ALU flags for VMfailInvalid. 5524 */ 5525 if (vmx->nested.current_vmptr == INVALID_GPA || 5526 (is_guest_mode(vcpu) && 5527 get_vmcs12(vcpu)->vmcs_link_pointer == INVALID_GPA)) 5528 return nested_vmx_failInvalid(vcpu); 5529 5530 if (instr_info & BIT(10)) 5531 value = kvm_register_read(vcpu, (((instr_info) >> 3) & 0xf)); 5532 else { 5533 len = is_64_bit_mode(vcpu) ? 8 : 4; 5534 if (get_vmx_mem_address(vcpu, exit_qualification, 5535 instr_info, false, len, &gva)) 5536 return 1; 5537 r = kvm_read_guest_virt(vcpu, gva, &value, len, &e); 5538 if (r != X86EMUL_CONTINUE) 5539 return kvm_handle_memory_failure(vcpu, r, &e); 5540 } 5541 5542 field = kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf)); 5543 5544 offset = get_vmcs12_field_offset(field); 5545 if (offset < 0) 5546 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5547 5548 /* 5549 * If the vCPU supports "VMWRITE to any supported field in the 5550 * VMCS," then the "read-only" fields are actually read/write. 5551 */ 5552 if (vmcs_field_readonly(field) && 5553 !nested_cpu_has_vmwrite_any_field(vcpu)) 5554 return nested_vmx_fail(vcpu, VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); 5555 5556 /* 5557 * Ensure vmcs12 is up-to-date before any VMWRITE that dirties 5558 * vmcs12, else we may crush a field or consume a stale value. 5559 */ 5560 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) 5561 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 5562 5563 /* 5564 * Some Intel CPUs intentionally drop the reserved bits of the AR byte 5565 * fields on VMWRITE. Emulate this behavior to ensure consistent KVM 5566 * behavior regardless of the underlying hardware, e.g. if an AR_BYTE 5567 * field is intercepted for VMWRITE but not VMREAD (in L1), then VMREAD 5568 * from L1 will return a different value than VMREAD from L2 (L1 sees 5569 * the stripped down value, L2 sees the full value as stored by KVM). 5570 */ 5571 if (field >= GUEST_ES_AR_BYTES && field <= GUEST_TR_AR_BYTES) 5572 value &= 0x1f0ff; 5573 5574 vmcs12_write_any(vmcs12, field, offset, value); 5575 5576 /* 5577 * Do not track vmcs12 dirty-state if in guest-mode as we actually 5578 * dirty shadow vmcs12 instead of vmcs12. Fields that can be updated 5579 * by L1 without a vmexit are always updated in the vmcs02, i.e. don't 5580 * "dirty" vmcs12, all others go down the prepare_vmcs02() slow path. 5581 */ 5582 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) { 5583 /* 5584 * L1 can read these fields without exiting, ensure the 5585 * shadow VMCS is up-to-date. 5586 */ 5587 if (enable_shadow_vmcs && is_shadow_field_ro(field)) { 5588 preempt_disable(); 5589 vmcs_load(vmx->vmcs01.shadow_vmcs); 5590 5591 __vmcs_writel(field, value); 5592 5593 vmcs_clear(vmx->vmcs01.shadow_vmcs); 5594 vmcs_load(vmx->loaded_vmcs->vmcs); 5595 preempt_enable(); 5596 } 5597 vmx->nested.dirty_vmcs12 = true; 5598 } 5599 5600 return nested_vmx_succeed(vcpu); 5601 } 5602 5603 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) 5604 { 5605 vmx->nested.current_vmptr = vmptr; 5606 if (enable_shadow_vmcs) { 5607 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS); 5608 vmcs_write64(VMCS_LINK_POINTER, 5609 __pa(vmx->vmcs01.shadow_vmcs)); 5610 vmx->nested.need_vmcs12_to_shadow_sync = true; 5611 } 5612 vmx->nested.dirty_vmcs12 = true; 5613 vmx->nested.force_msr_bitmap_recalc = true; 5614 } 5615 5616 /* Emulate the VMPTRLD instruction */ 5617 static int handle_vmptrld(struct kvm_vcpu *vcpu) 5618 { 5619 struct vcpu_vmx *vmx = to_vmx(vcpu); 5620 gpa_t vmptr; 5621 int r; 5622 5623 if (!nested_vmx_check_permission(vcpu)) 5624 return 1; 5625 5626 if (nested_vmx_get_vmptr(vcpu, &vmptr, &r)) 5627 return r; 5628 5629 if (!page_address_valid(vcpu, vmptr)) 5630 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); 5631 5632 if (vmptr == vmx->nested.vmxon_ptr) 5633 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_VMXON_POINTER); 5634 5635 /* Forbid normal VMPTRLD if Enlightened version was used */ 5636 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) 5637 return 1; 5638 5639 if (vmx->nested.current_vmptr != vmptr) { 5640 struct gfn_to_hva_cache *ghc = &vmx->nested.vmcs12_cache; 5641 struct vmcs_hdr hdr; 5642 5643 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, vmptr, VMCS12_SIZE)) { 5644 /* 5645 * Reads from an unbacked page return all 1s, 5646 * which means that the 32 bits located at the 5647 * given physical address won't match the required 5648 * VMCS12_REVISION identifier. 5649 */ 5650 return nested_vmx_fail(vcpu, 5651 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); 5652 } 5653 5654 if (kvm_read_guest_offset_cached(vcpu->kvm, ghc, &hdr, 5655 offsetof(struct vmcs12, hdr), 5656 sizeof(hdr))) { 5657 return nested_vmx_fail(vcpu, 5658 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); 5659 } 5660 5661 if (hdr.revision_id != VMCS12_REVISION || 5662 (hdr.shadow_vmcs && 5663 !nested_cpu_has_vmx_shadow_vmcs(vcpu))) { 5664 return nested_vmx_fail(vcpu, 5665 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); 5666 } 5667 5668 nested_release_vmcs12(vcpu); 5669 5670 /* 5671 * Load VMCS12 from guest memory since it is not already 5672 * cached. 5673 */ 5674 if (kvm_read_guest_cached(vcpu->kvm, ghc, vmx->nested.cached_vmcs12, 5675 VMCS12_SIZE)) { 5676 return nested_vmx_fail(vcpu, 5677 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); 5678 } 5679 5680 set_current_vmptr(vmx, vmptr); 5681 } 5682 5683 return nested_vmx_succeed(vcpu); 5684 } 5685 5686 /* Emulate the VMPTRST instruction */ 5687 static int handle_vmptrst(struct kvm_vcpu *vcpu) 5688 { 5689 unsigned long exit_qual = vmx_get_exit_qual(vcpu); 5690 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5691 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr; 5692 struct x86_exception e; 5693 gva_t gva; 5694 int r; 5695 5696 if (!nested_vmx_check_permission(vcpu)) 5697 return 1; 5698 5699 if (unlikely(evmptr_is_valid(to_vmx(vcpu)->nested.hv_evmcs_vmptr))) 5700 return 1; 5701 5702 if (get_vmx_mem_address(vcpu, exit_qual, instr_info, 5703 true, sizeof(gpa_t), &gva)) 5704 return 1; 5705 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */ 5706 r = kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr, 5707 sizeof(gpa_t), &e); 5708 if (r != X86EMUL_CONTINUE) 5709 return kvm_handle_memory_failure(vcpu, r, &e); 5710 5711 return nested_vmx_succeed(vcpu); 5712 } 5713 5714 /* Emulate the INVEPT instruction */ 5715 static int handle_invept(struct kvm_vcpu *vcpu) 5716 { 5717 struct vcpu_vmx *vmx = to_vmx(vcpu); 5718 u32 vmx_instruction_info, types; 5719 unsigned long type, roots_to_free; 5720 struct kvm_mmu *mmu; 5721 gva_t gva; 5722 struct x86_exception e; 5723 struct { 5724 u64 eptp, gpa; 5725 } operand; 5726 int i, r, gpr_index; 5727 5728 if (!(vmx->nested.msrs.secondary_ctls_high & 5729 SECONDARY_EXEC_ENABLE_EPT) || 5730 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) { 5731 kvm_queue_exception(vcpu, UD_VECTOR); 5732 return 1; 5733 } 5734 5735 if (!nested_vmx_check_permission(vcpu)) 5736 return 1; 5737 5738 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5739 gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info); 5740 type = kvm_register_read(vcpu, gpr_index); 5741 5742 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; 5743 5744 if (type >= 32 || !(types & (1 << type))) 5745 return nested_vmx_fail(vcpu, VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5746 5747 /* According to the Intel VMX instruction reference, the memory 5748 * operand is read even if it isn't needed (e.g., for type==global) 5749 */ 5750 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), 5751 vmx_instruction_info, false, sizeof(operand), &gva)) 5752 return 1; 5753 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 5754 if (r != X86EMUL_CONTINUE) 5755 return kvm_handle_memory_failure(vcpu, r, &e); 5756 5757 /* 5758 * Nested EPT roots are always held through guest_mmu, 5759 * not root_mmu. 5760 */ 5761 mmu = &vcpu->arch.guest_mmu; 5762 5763 switch (type) { 5764 case VMX_EPT_EXTENT_CONTEXT: 5765 if (!nested_vmx_check_eptp(vcpu, operand.eptp)) 5766 return nested_vmx_fail(vcpu, 5767 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5768 5769 roots_to_free = 0; 5770 if (nested_ept_root_matches(mmu->root.hpa, mmu->root.pgd, 5771 operand.eptp)) 5772 roots_to_free |= KVM_MMU_ROOT_CURRENT; 5773 5774 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { 5775 if (nested_ept_root_matches(mmu->prev_roots[i].hpa, 5776 mmu->prev_roots[i].pgd, 5777 operand.eptp)) 5778 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5779 } 5780 break; 5781 case VMX_EPT_EXTENT_GLOBAL: 5782 roots_to_free = KVM_MMU_ROOTS_ALL; 5783 break; 5784 default: 5785 BUG(); 5786 break; 5787 } 5788 5789 if (roots_to_free) 5790 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); 5791 5792 return nested_vmx_succeed(vcpu); 5793 } 5794 5795 static int handle_invvpid(struct kvm_vcpu *vcpu) 5796 { 5797 struct vcpu_vmx *vmx = to_vmx(vcpu); 5798 u32 vmx_instruction_info; 5799 unsigned long type, types; 5800 gva_t gva; 5801 struct x86_exception e; 5802 struct { 5803 u64 vpid; 5804 u64 gla; 5805 } operand; 5806 u16 vpid02; 5807 int r, gpr_index; 5808 5809 if (!(vmx->nested.msrs.secondary_ctls_high & 5810 SECONDARY_EXEC_ENABLE_VPID) || 5811 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) { 5812 kvm_queue_exception(vcpu, UD_VECTOR); 5813 return 1; 5814 } 5815 5816 if (!nested_vmx_check_permission(vcpu)) 5817 return 1; 5818 5819 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5820 gpr_index = vmx_get_instr_info_reg2(vmx_instruction_info); 5821 type = kvm_register_read(vcpu, gpr_index); 5822 5823 types = (vmx->nested.msrs.vpid_caps & 5824 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; 5825 5826 if (type >= 32 || !(types & (1 << type))) 5827 return nested_vmx_fail(vcpu, 5828 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5829 5830 /* according to the intel vmx instruction reference, the memory 5831 * operand is read even if it isn't needed (e.g., for type==global) 5832 */ 5833 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), 5834 vmx_instruction_info, false, sizeof(operand), &gva)) 5835 return 1; 5836 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 5837 if (r != X86EMUL_CONTINUE) 5838 return kvm_handle_memory_failure(vcpu, r, &e); 5839 5840 if (operand.vpid >> 16) 5841 return nested_vmx_fail(vcpu, 5842 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5843 5844 /* 5845 * Always flush the effective vpid02, i.e. never flush the current VPID 5846 * and never explicitly flush vpid01. INVVPID targets a VPID, not a 5847 * VMCS, and so whether or not the current vmcs12 has VPID enabled is 5848 * irrelevant (and there may not be a loaded vmcs12). 5849 */ 5850 vpid02 = nested_get_vpid02(vcpu); 5851 switch (type) { 5852 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: 5853 if (!operand.vpid || 5854 is_noncanonical_address(operand.gla, vcpu)) 5855 return nested_vmx_fail(vcpu, 5856 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5857 vpid_sync_vcpu_addr(vpid02, operand.gla); 5858 break; 5859 case VMX_VPID_EXTENT_SINGLE_CONTEXT: 5860 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: 5861 if (!operand.vpid) 5862 return nested_vmx_fail(vcpu, 5863 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5864 vpid_sync_context(vpid02); 5865 break; 5866 case VMX_VPID_EXTENT_ALL_CONTEXT: 5867 vpid_sync_context(vpid02); 5868 break; 5869 default: 5870 WARN_ON_ONCE(1); 5871 return kvm_skip_emulated_instruction(vcpu); 5872 } 5873 5874 /* 5875 * Sync the shadow page tables if EPT is disabled, L1 is invalidating 5876 * linear mappings for L2 (tagged with L2's VPID). Free all guest 5877 * roots as VPIDs are not tracked in the MMU role. 5878 * 5879 * Note, this operates on root_mmu, not guest_mmu, as L1 and L2 share 5880 * an MMU when EPT is disabled. 5881 * 5882 * TODO: sync only the affected SPTEs for INVDIVIDUAL_ADDR. 5883 */ 5884 if (!enable_ept) 5885 kvm_mmu_free_guest_mode_roots(vcpu->kvm, &vcpu->arch.root_mmu); 5886 5887 return nested_vmx_succeed(vcpu); 5888 } 5889 5890 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, 5891 struct vmcs12 *vmcs12) 5892 { 5893 u32 index = kvm_rcx_read(vcpu); 5894 u64 new_eptp; 5895 5896 if (WARN_ON_ONCE(!nested_cpu_has_ept(vmcs12))) 5897 return 1; 5898 if (index >= VMFUNC_EPTP_ENTRIES) 5899 return 1; 5900 5901 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, 5902 &new_eptp, index * 8, 8)) 5903 return 1; 5904 5905 /* 5906 * If the (L2) guest does a vmfunc to the currently 5907 * active ept pointer, we don't have to do anything else 5908 */ 5909 if (vmcs12->ept_pointer != new_eptp) { 5910 if (!nested_vmx_check_eptp(vcpu, new_eptp)) 5911 return 1; 5912 5913 vmcs12->ept_pointer = new_eptp; 5914 nested_ept_new_eptp(vcpu); 5915 5916 if (!nested_cpu_has_vpid(vmcs12)) 5917 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 5918 } 5919 5920 return 0; 5921 } 5922 5923 static int handle_vmfunc(struct kvm_vcpu *vcpu) 5924 { 5925 struct vcpu_vmx *vmx = to_vmx(vcpu); 5926 struct vmcs12 *vmcs12; 5927 u32 function = kvm_rax_read(vcpu); 5928 5929 /* 5930 * VMFUNC should never execute cleanly while L1 is active; KVM supports 5931 * VMFUNC for nested VMs, but not for L1. 5932 */ 5933 if (WARN_ON_ONCE(!is_guest_mode(vcpu))) { 5934 kvm_queue_exception(vcpu, UD_VECTOR); 5935 return 1; 5936 } 5937 5938 vmcs12 = get_vmcs12(vcpu); 5939 5940 /* 5941 * #UD on out-of-bounds function has priority over VM-Exit, and VMFUNC 5942 * is enabled in vmcs02 if and only if it's enabled in vmcs12. 5943 */ 5944 if (WARN_ON_ONCE((function > 63) || !nested_cpu_has_vmfunc(vmcs12))) { 5945 kvm_queue_exception(vcpu, UD_VECTOR); 5946 return 1; 5947 } 5948 5949 if (!(vmcs12->vm_function_control & BIT_ULL(function))) 5950 goto fail; 5951 5952 switch (function) { 5953 case 0: 5954 if (nested_vmx_eptp_switching(vcpu, vmcs12)) 5955 goto fail; 5956 break; 5957 default: 5958 goto fail; 5959 } 5960 return kvm_skip_emulated_instruction(vcpu); 5961 5962 fail: 5963 /* 5964 * This is effectively a reflected VM-Exit, as opposed to a synthesized 5965 * nested VM-Exit. Pass the original exit reason, i.e. don't hardcode 5966 * EXIT_REASON_VMFUNC as the exit reason. 5967 */ 5968 nested_vmx_vmexit(vcpu, vmx->exit_reason.full, 5969 vmx_get_intr_info(vcpu), 5970 vmx_get_exit_qual(vcpu)); 5971 return 1; 5972 } 5973 5974 /* 5975 * Return true if an IO instruction with the specified port and size should cause 5976 * a VM-exit into L1. 5977 */ 5978 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, 5979 int size) 5980 { 5981 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5982 gpa_t bitmap, last_bitmap; 5983 u8 b; 5984 5985 last_bitmap = INVALID_GPA; 5986 b = -1; 5987 5988 while (size > 0) { 5989 if (port < 0x8000) 5990 bitmap = vmcs12->io_bitmap_a; 5991 else if (port < 0x10000) 5992 bitmap = vmcs12->io_bitmap_b; 5993 else 5994 return true; 5995 bitmap += (port & 0x7fff) / 8; 5996 5997 if (last_bitmap != bitmap) 5998 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) 5999 return true; 6000 if (b & (1 << (port & 7))) 6001 return true; 6002 6003 port++; 6004 size--; 6005 last_bitmap = bitmap; 6006 } 6007 6008 return false; 6009 } 6010 6011 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, 6012 struct vmcs12 *vmcs12) 6013 { 6014 unsigned long exit_qualification; 6015 unsigned short port; 6016 int size; 6017 6018 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 6019 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); 6020 6021 exit_qualification = vmx_get_exit_qual(vcpu); 6022 6023 port = exit_qualification >> 16; 6024 size = (exit_qualification & 7) + 1; 6025 6026 return nested_vmx_check_io_bitmaps(vcpu, port, size); 6027 } 6028 6029 /* 6030 * Return 1 if we should exit from L2 to L1 to handle an MSR access, 6031 * rather than handle it ourselves in L0. I.e., check whether L1 expressed 6032 * disinterest in the current event (read or write a specific MSR) by using an 6033 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. 6034 */ 6035 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, 6036 struct vmcs12 *vmcs12, 6037 union vmx_exit_reason exit_reason) 6038 { 6039 u32 msr_index = kvm_rcx_read(vcpu); 6040 gpa_t bitmap; 6041 6042 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 6043 return true; 6044 6045 /* 6046 * The MSR_BITMAP page is divided into four 1024-byte bitmaps, 6047 * for the four combinations of read/write and low/high MSR numbers. 6048 * First we need to figure out which of the four to use: 6049 */ 6050 bitmap = vmcs12->msr_bitmap; 6051 if (exit_reason.basic == EXIT_REASON_MSR_WRITE) 6052 bitmap += 2048; 6053 if (msr_index >= 0xc0000000) { 6054 msr_index -= 0xc0000000; 6055 bitmap += 1024; 6056 } 6057 6058 /* Then read the msr_index'th bit from this bitmap: */ 6059 if (msr_index < 1024*8) { 6060 unsigned char b; 6061 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) 6062 return true; 6063 return 1 & (b >> (msr_index & 7)); 6064 } else 6065 return true; /* let L1 handle the wrong parameter */ 6066 } 6067 6068 /* 6069 * Return 1 if we should exit from L2 to L1 to handle a CR access exit, 6070 * rather than handle it ourselves in L0. I.e., check if L1 wanted to 6071 * intercept (via guest_host_mask etc.) the current event. 6072 */ 6073 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, 6074 struct vmcs12 *vmcs12) 6075 { 6076 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 6077 int cr = exit_qualification & 15; 6078 int reg; 6079 unsigned long val; 6080 6081 switch ((exit_qualification >> 4) & 3) { 6082 case 0: /* mov to cr */ 6083 reg = (exit_qualification >> 8) & 15; 6084 val = kvm_register_read(vcpu, reg); 6085 switch (cr) { 6086 case 0: 6087 if (vmcs12->cr0_guest_host_mask & 6088 (val ^ vmcs12->cr0_read_shadow)) 6089 return true; 6090 break; 6091 case 3: 6092 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) 6093 return true; 6094 break; 6095 case 4: 6096 if (vmcs12->cr4_guest_host_mask & 6097 (vmcs12->cr4_read_shadow ^ val)) 6098 return true; 6099 break; 6100 case 8: 6101 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) 6102 return true; 6103 break; 6104 } 6105 break; 6106 case 2: /* clts */ 6107 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && 6108 (vmcs12->cr0_read_shadow & X86_CR0_TS)) 6109 return true; 6110 break; 6111 case 1: /* mov from cr */ 6112 switch (cr) { 6113 case 3: 6114 if (vmcs12->cpu_based_vm_exec_control & 6115 CPU_BASED_CR3_STORE_EXITING) 6116 return true; 6117 break; 6118 case 8: 6119 if (vmcs12->cpu_based_vm_exec_control & 6120 CPU_BASED_CR8_STORE_EXITING) 6121 return true; 6122 break; 6123 } 6124 break; 6125 case 3: /* lmsw */ 6126 /* 6127 * lmsw can change bits 1..3 of cr0, and only set bit 0 of 6128 * cr0. Other attempted changes are ignored, with no exit. 6129 */ 6130 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 6131 if (vmcs12->cr0_guest_host_mask & 0xe & 6132 (val ^ vmcs12->cr0_read_shadow)) 6133 return true; 6134 if ((vmcs12->cr0_guest_host_mask & 0x1) && 6135 !(vmcs12->cr0_read_shadow & 0x1) && 6136 (val & 0x1)) 6137 return true; 6138 break; 6139 } 6140 return false; 6141 } 6142 6143 static bool nested_vmx_exit_handled_encls(struct kvm_vcpu *vcpu, 6144 struct vmcs12 *vmcs12) 6145 { 6146 u32 encls_leaf; 6147 6148 if (!guest_cpuid_has(vcpu, X86_FEATURE_SGX) || 6149 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING)) 6150 return false; 6151 6152 encls_leaf = kvm_rax_read(vcpu); 6153 if (encls_leaf > 62) 6154 encls_leaf = 63; 6155 return vmcs12->encls_exiting_bitmap & BIT_ULL(encls_leaf); 6156 } 6157 6158 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu, 6159 struct vmcs12 *vmcs12, gpa_t bitmap) 6160 { 6161 u32 vmx_instruction_info; 6162 unsigned long field; 6163 u8 b; 6164 6165 if (!nested_cpu_has_shadow_vmcs(vmcs12)) 6166 return true; 6167 6168 /* Decode instruction info and find the field to access */ 6169 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 6170 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); 6171 6172 /* Out-of-range fields always cause a VM exit from L2 to L1 */ 6173 if (field >> 15) 6174 return true; 6175 6176 if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1)) 6177 return true; 6178 6179 return 1 & (b >> (field & 7)); 6180 } 6181 6182 static bool nested_vmx_exit_handled_mtf(struct vmcs12 *vmcs12) 6183 { 6184 u32 entry_intr_info = vmcs12->vm_entry_intr_info_field; 6185 6186 if (nested_cpu_has_mtf(vmcs12)) 6187 return true; 6188 6189 /* 6190 * An MTF VM-exit may be injected into the guest by setting the 6191 * interruption-type to 7 (other event) and the vector field to 0. Such 6192 * is the case regardless of the 'monitor trap flag' VM-execution 6193 * control. 6194 */ 6195 return entry_intr_info == (INTR_INFO_VALID_MASK 6196 | INTR_TYPE_OTHER_EVENT); 6197 } 6198 6199 /* 6200 * Return true if L0 wants to handle an exit from L2 regardless of whether or not 6201 * L1 wants the exit. Only call this when in is_guest_mode (L2). 6202 */ 6203 static bool nested_vmx_l0_wants_exit(struct kvm_vcpu *vcpu, 6204 union vmx_exit_reason exit_reason) 6205 { 6206 u32 intr_info; 6207 6208 switch ((u16)exit_reason.basic) { 6209 case EXIT_REASON_EXCEPTION_NMI: 6210 intr_info = vmx_get_intr_info(vcpu); 6211 if (is_nmi(intr_info)) 6212 return true; 6213 else if (is_page_fault(intr_info)) 6214 return vcpu->arch.apf.host_apf_flags || 6215 vmx_need_pf_intercept(vcpu); 6216 else if (is_debug(intr_info) && 6217 vcpu->guest_debug & 6218 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 6219 return true; 6220 else if (is_breakpoint(intr_info) && 6221 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 6222 return true; 6223 else if (is_alignment_check(intr_info) && 6224 !vmx_guest_inject_ac(vcpu)) 6225 return true; 6226 return false; 6227 case EXIT_REASON_EXTERNAL_INTERRUPT: 6228 return true; 6229 case EXIT_REASON_MCE_DURING_VMENTRY: 6230 return true; 6231 case EXIT_REASON_EPT_VIOLATION: 6232 /* 6233 * L0 always deals with the EPT violation. If nested EPT is 6234 * used, and the nested mmu code discovers that the address is 6235 * missing in the guest EPT table (EPT12), the EPT violation 6236 * will be injected with nested_ept_inject_page_fault() 6237 */ 6238 return true; 6239 case EXIT_REASON_EPT_MISCONFIG: 6240 /* 6241 * L2 never uses directly L1's EPT, but rather L0's own EPT 6242 * table (shadow on EPT) or a merged EPT table that L0 built 6243 * (EPT on EPT). So any problems with the structure of the 6244 * table is L0's fault. 6245 */ 6246 return true; 6247 case EXIT_REASON_PREEMPTION_TIMER: 6248 return true; 6249 case EXIT_REASON_PML_FULL: 6250 /* 6251 * PML is emulated for an L1 VMM and should never be enabled in 6252 * vmcs02, always "handle" PML_FULL by exiting to userspace. 6253 */ 6254 return true; 6255 case EXIT_REASON_VMFUNC: 6256 /* VM functions are emulated through L2->L0 vmexits. */ 6257 return true; 6258 case EXIT_REASON_BUS_LOCK: 6259 /* 6260 * At present, bus lock VM exit is never exposed to L1. 6261 * Handle L2's bus locks in L0 directly. 6262 */ 6263 return true; 6264 case EXIT_REASON_VMCALL: 6265 /* Hyper-V L2 TLB flush hypercall is handled by L0 */ 6266 return guest_hv_cpuid_has_l2_tlb_flush(vcpu) && 6267 nested_evmcs_l2_tlb_flush_enabled(vcpu) && 6268 kvm_hv_is_tlb_flush_hcall(vcpu); 6269 default: 6270 break; 6271 } 6272 return false; 6273 } 6274 6275 /* 6276 * Return 1 if L1 wants to intercept an exit from L2. Only call this when in 6277 * is_guest_mode (L2). 6278 */ 6279 static bool nested_vmx_l1_wants_exit(struct kvm_vcpu *vcpu, 6280 union vmx_exit_reason exit_reason) 6281 { 6282 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6283 u32 intr_info; 6284 6285 switch ((u16)exit_reason.basic) { 6286 case EXIT_REASON_EXCEPTION_NMI: 6287 intr_info = vmx_get_intr_info(vcpu); 6288 if (is_nmi(intr_info)) 6289 return true; 6290 else if (is_page_fault(intr_info)) 6291 return true; 6292 return vmcs12->exception_bitmap & 6293 (1u << (intr_info & INTR_INFO_VECTOR_MASK)); 6294 case EXIT_REASON_EXTERNAL_INTERRUPT: 6295 return nested_exit_on_intr(vcpu); 6296 case EXIT_REASON_TRIPLE_FAULT: 6297 return true; 6298 case EXIT_REASON_INTERRUPT_WINDOW: 6299 return nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING); 6300 case EXIT_REASON_NMI_WINDOW: 6301 return nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING); 6302 case EXIT_REASON_TASK_SWITCH: 6303 return true; 6304 case EXIT_REASON_CPUID: 6305 return true; 6306 case EXIT_REASON_HLT: 6307 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); 6308 case EXIT_REASON_INVD: 6309 return true; 6310 case EXIT_REASON_INVLPG: 6311 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); 6312 case EXIT_REASON_RDPMC: 6313 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); 6314 case EXIT_REASON_RDRAND: 6315 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); 6316 case EXIT_REASON_RDSEED: 6317 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); 6318 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: 6319 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); 6320 case EXIT_REASON_VMREAD: 6321 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12, 6322 vmcs12->vmread_bitmap); 6323 case EXIT_REASON_VMWRITE: 6324 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12, 6325 vmcs12->vmwrite_bitmap); 6326 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: 6327 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: 6328 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME: 6329 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: 6330 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: 6331 /* 6332 * VMX instructions trap unconditionally. This allows L1 to 6333 * emulate them for its L2 guest, i.e., allows 3-level nesting! 6334 */ 6335 return true; 6336 case EXIT_REASON_CR_ACCESS: 6337 return nested_vmx_exit_handled_cr(vcpu, vmcs12); 6338 case EXIT_REASON_DR_ACCESS: 6339 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); 6340 case EXIT_REASON_IO_INSTRUCTION: 6341 return nested_vmx_exit_handled_io(vcpu, vmcs12); 6342 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: 6343 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); 6344 case EXIT_REASON_MSR_READ: 6345 case EXIT_REASON_MSR_WRITE: 6346 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); 6347 case EXIT_REASON_INVALID_STATE: 6348 return true; 6349 case EXIT_REASON_MWAIT_INSTRUCTION: 6350 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); 6351 case EXIT_REASON_MONITOR_TRAP_FLAG: 6352 return nested_vmx_exit_handled_mtf(vmcs12); 6353 case EXIT_REASON_MONITOR_INSTRUCTION: 6354 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); 6355 case EXIT_REASON_PAUSE_INSTRUCTION: 6356 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || 6357 nested_cpu_has2(vmcs12, 6358 SECONDARY_EXEC_PAUSE_LOOP_EXITING); 6359 case EXIT_REASON_MCE_DURING_VMENTRY: 6360 return true; 6361 case EXIT_REASON_TPR_BELOW_THRESHOLD: 6362 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); 6363 case EXIT_REASON_APIC_ACCESS: 6364 case EXIT_REASON_APIC_WRITE: 6365 case EXIT_REASON_EOI_INDUCED: 6366 /* 6367 * The controls for "virtualize APIC accesses," "APIC- 6368 * register virtualization," and "virtual-interrupt 6369 * delivery" only come from vmcs12. 6370 */ 6371 return true; 6372 case EXIT_REASON_INVPCID: 6373 return 6374 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && 6375 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); 6376 case EXIT_REASON_WBINVD: 6377 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); 6378 case EXIT_REASON_XSETBV: 6379 return true; 6380 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: 6381 /* 6382 * This should never happen, since it is not possible to 6383 * set XSS to a non-zero value---neither in L1 nor in L2. 6384 * If if it were, XSS would have to be checked against 6385 * the XSS exit bitmap in vmcs12. 6386 */ 6387 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_XSAVES); 6388 case EXIT_REASON_UMWAIT: 6389 case EXIT_REASON_TPAUSE: 6390 return nested_cpu_has2(vmcs12, 6391 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE); 6392 case EXIT_REASON_ENCLS: 6393 return nested_vmx_exit_handled_encls(vcpu, vmcs12); 6394 case EXIT_REASON_NOTIFY: 6395 /* Notify VM exit is not exposed to L1 */ 6396 return false; 6397 default: 6398 return true; 6399 } 6400 } 6401 6402 /* 6403 * Conditionally reflect a VM-Exit into L1. Returns %true if the VM-Exit was 6404 * reflected into L1. 6405 */ 6406 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu) 6407 { 6408 struct vcpu_vmx *vmx = to_vmx(vcpu); 6409 union vmx_exit_reason exit_reason = vmx->exit_reason; 6410 unsigned long exit_qual; 6411 u32 exit_intr_info; 6412 6413 WARN_ON_ONCE(vmx->nested.nested_run_pending); 6414 6415 /* 6416 * Late nested VM-Fail shares the same flow as nested VM-Exit since KVM 6417 * has already loaded L2's state. 6418 */ 6419 if (unlikely(vmx->fail)) { 6420 trace_kvm_nested_vmenter_failed( 6421 "hardware VM-instruction error: ", 6422 vmcs_read32(VM_INSTRUCTION_ERROR)); 6423 exit_intr_info = 0; 6424 exit_qual = 0; 6425 goto reflect_vmexit; 6426 } 6427 6428 trace_kvm_nested_vmexit(vcpu, KVM_ISA_VMX); 6429 6430 /* If L0 (KVM) wants the exit, it trumps L1's desires. */ 6431 if (nested_vmx_l0_wants_exit(vcpu, exit_reason)) 6432 return false; 6433 6434 /* If L1 doesn't want the exit, handle it in L0. */ 6435 if (!nested_vmx_l1_wants_exit(vcpu, exit_reason)) 6436 return false; 6437 6438 /* 6439 * vmcs.VM_EXIT_INTR_INFO is only valid for EXCEPTION_NMI exits. For 6440 * EXTERNAL_INTERRUPT, the value for vmcs12->vm_exit_intr_info would 6441 * need to be synthesized by querying the in-kernel LAPIC, but external 6442 * interrupts are never reflected to L1 so it's a non-issue. 6443 */ 6444 exit_intr_info = vmx_get_intr_info(vcpu); 6445 if (is_exception_with_error_code(exit_intr_info)) { 6446 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6447 6448 vmcs12->vm_exit_intr_error_code = 6449 vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 6450 } 6451 exit_qual = vmx_get_exit_qual(vcpu); 6452 6453 reflect_vmexit: 6454 nested_vmx_vmexit(vcpu, exit_reason.full, exit_intr_info, exit_qual); 6455 return true; 6456 } 6457 6458 static int vmx_get_nested_state(struct kvm_vcpu *vcpu, 6459 struct kvm_nested_state __user *user_kvm_nested_state, 6460 u32 user_data_size) 6461 { 6462 struct vcpu_vmx *vmx; 6463 struct vmcs12 *vmcs12; 6464 struct kvm_nested_state kvm_state = { 6465 .flags = 0, 6466 .format = KVM_STATE_NESTED_FORMAT_VMX, 6467 .size = sizeof(kvm_state), 6468 .hdr.vmx.flags = 0, 6469 .hdr.vmx.vmxon_pa = INVALID_GPA, 6470 .hdr.vmx.vmcs12_pa = INVALID_GPA, 6471 .hdr.vmx.preemption_timer_deadline = 0, 6472 }; 6473 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state = 6474 &user_kvm_nested_state->data.vmx[0]; 6475 6476 if (!vcpu) 6477 return kvm_state.size + sizeof(*user_vmx_nested_state); 6478 6479 vmx = to_vmx(vcpu); 6480 vmcs12 = get_vmcs12(vcpu); 6481 6482 if (guest_can_use(vcpu, X86_FEATURE_VMX) && 6483 (vmx->nested.vmxon || vmx->nested.smm.vmxon)) { 6484 kvm_state.hdr.vmx.vmxon_pa = vmx->nested.vmxon_ptr; 6485 kvm_state.hdr.vmx.vmcs12_pa = vmx->nested.current_vmptr; 6486 6487 if (vmx_has_valid_vmcs12(vcpu)) { 6488 kvm_state.size += sizeof(user_vmx_nested_state->vmcs12); 6489 6490 /* 'hv_evmcs_vmptr' can also be EVMPTR_MAP_PENDING here */ 6491 if (vmx->nested.hv_evmcs_vmptr != EVMPTR_INVALID) 6492 kvm_state.flags |= KVM_STATE_NESTED_EVMCS; 6493 6494 if (is_guest_mode(vcpu) && 6495 nested_cpu_has_shadow_vmcs(vmcs12) && 6496 vmcs12->vmcs_link_pointer != INVALID_GPA) 6497 kvm_state.size += sizeof(user_vmx_nested_state->shadow_vmcs12); 6498 } 6499 6500 if (vmx->nested.smm.vmxon) 6501 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON; 6502 6503 if (vmx->nested.smm.guest_mode) 6504 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE; 6505 6506 if (is_guest_mode(vcpu)) { 6507 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE; 6508 6509 if (vmx->nested.nested_run_pending) 6510 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING; 6511 6512 if (vmx->nested.mtf_pending) 6513 kvm_state.flags |= KVM_STATE_NESTED_MTF_PENDING; 6514 6515 if (nested_cpu_has_preemption_timer(vmcs12) && 6516 vmx->nested.has_preemption_timer_deadline) { 6517 kvm_state.hdr.vmx.flags |= 6518 KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE; 6519 kvm_state.hdr.vmx.preemption_timer_deadline = 6520 vmx->nested.preemption_timer_deadline; 6521 } 6522 } 6523 } 6524 6525 if (user_data_size < kvm_state.size) 6526 goto out; 6527 6528 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state))) 6529 return -EFAULT; 6530 6531 if (!vmx_has_valid_vmcs12(vcpu)) 6532 goto out; 6533 6534 /* 6535 * When running L2, the authoritative vmcs12 state is in the 6536 * vmcs02. When running L1, the authoritative vmcs12 state is 6537 * in the shadow or enlightened vmcs linked to vmcs01, unless 6538 * need_vmcs12_to_shadow_sync is set, in which case, the authoritative 6539 * vmcs12 state is in the vmcs12 already. 6540 */ 6541 if (is_guest_mode(vcpu)) { 6542 sync_vmcs02_to_vmcs12(vcpu, vmcs12); 6543 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 6544 } else { 6545 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu)); 6546 if (!vmx->nested.need_vmcs12_to_shadow_sync) { 6547 if (evmptr_is_valid(vmx->nested.hv_evmcs_vmptr)) 6548 /* 6549 * L1 hypervisor is not obliged to keep eVMCS 6550 * clean fields data always up-to-date while 6551 * not in guest mode, 'hv_clean_fields' is only 6552 * supposed to be actual upon vmentry so we need 6553 * to ignore it here and do full copy. 6554 */ 6555 copy_enlightened_to_vmcs12(vmx, 0); 6556 else if (enable_shadow_vmcs) 6557 copy_shadow_to_vmcs12(vmx); 6558 } 6559 } 6560 6561 BUILD_BUG_ON(sizeof(user_vmx_nested_state->vmcs12) < VMCS12_SIZE); 6562 BUILD_BUG_ON(sizeof(user_vmx_nested_state->shadow_vmcs12) < VMCS12_SIZE); 6563 6564 /* 6565 * Copy over the full allocated size of vmcs12 rather than just the size 6566 * of the struct. 6567 */ 6568 if (copy_to_user(user_vmx_nested_state->vmcs12, vmcs12, VMCS12_SIZE)) 6569 return -EFAULT; 6570 6571 if (nested_cpu_has_shadow_vmcs(vmcs12) && 6572 vmcs12->vmcs_link_pointer != INVALID_GPA) { 6573 if (copy_to_user(user_vmx_nested_state->shadow_vmcs12, 6574 get_shadow_vmcs12(vcpu), VMCS12_SIZE)) 6575 return -EFAULT; 6576 } 6577 out: 6578 return kvm_state.size; 6579 } 6580 6581 void vmx_leave_nested(struct kvm_vcpu *vcpu) 6582 { 6583 if (is_guest_mode(vcpu)) { 6584 to_vmx(vcpu)->nested.nested_run_pending = 0; 6585 nested_vmx_vmexit(vcpu, -1, 0, 0); 6586 } 6587 free_nested(vcpu); 6588 } 6589 6590 static int vmx_set_nested_state(struct kvm_vcpu *vcpu, 6591 struct kvm_nested_state __user *user_kvm_nested_state, 6592 struct kvm_nested_state *kvm_state) 6593 { 6594 struct vcpu_vmx *vmx = to_vmx(vcpu); 6595 struct vmcs12 *vmcs12; 6596 enum vm_entry_failure_code ignored; 6597 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state = 6598 &user_kvm_nested_state->data.vmx[0]; 6599 int ret; 6600 6601 if (kvm_state->format != KVM_STATE_NESTED_FORMAT_VMX) 6602 return -EINVAL; 6603 6604 if (kvm_state->hdr.vmx.vmxon_pa == INVALID_GPA) { 6605 if (kvm_state->hdr.vmx.smm.flags) 6606 return -EINVAL; 6607 6608 if (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA) 6609 return -EINVAL; 6610 6611 /* 6612 * KVM_STATE_NESTED_EVMCS used to signal that KVM should 6613 * enable eVMCS capability on vCPU. However, since then 6614 * code was changed such that flag signals vmcs12 should 6615 * be copied into eVMCS in guest memory. 6616 * 6617 * To preserve backwards compatability, allow user 6618 * to set this flag even when there is no VMXON region. 6619 */ 6620 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS) 6621 return -EINVAL; 6622 } else { 6623 if (!guest_can_use(vcpu, X86_FEATURE_VMX)) 6624 return -EINVAL; 6625 6626 if (!page_address_valid(vcpu, kvm_state->hdr.vmx.vmxon_pa)) 6627 return -EINVAL; 6628 } 6629 6630 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) && 6631 (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE)) 6632 return -EINVAL; 6633 6634 if (kvm_state->hdr.vmx.smm.flags & 6635 ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON)) 6636 return -EINVAL; 6637 6638 if (kvm_state->hdr.vmx.flags & ~KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE) 6639 return -EINVAL; 6640 6641 /* 6642 * SMM temporarily disables VMX, so we cannot be in guest mode, 6643 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags 6644 * must be zero. 6645 */ 6646 if (is_smm(vcpu) ? 6647 (kvm_state->flags & 6648 (KVM_STATE_NESTED_GUEST_MODE | KVM_STATE_NESTED_RUN_PENDING)) 6649 : kvm_state->hdr.vmx.smm.flags) 6650 return -EINVAL; 6651 6652 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) && 6653 !(kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON)) 6654 return -EINVAL; 6655 6656 if ((kvm_state->flags & KVM_STATE_NESTED_EVMCS) && 6657 (!guest_can_use(vcpu, X86_FEATURE_VMX) || 6658 !vmx->nested.enlightened_vmcs_enabled)) 6659 return -EINVAL; 6660 6661 vmx_leave_nested(vcpu); 6662 6663 if (kvm_state->hdr.vmx.vmxon_pa == INVALID_GPA) 6664 return 0; 6665 6666 vmx->nested.vmxon_ptr = kvm_state->hdr.vmx.vmxon_pa; 6667 ret = enter_vmx_operation(vcpu); 6668 if (ret) 6669 return ret; 6670 6671 /* Empty 'VMXON' state is permitted if no VMCS loaded */ 6672 if (kvm_state->size < sizeof(*kvm_state) + sizeof(*vmcs12)) { 6673 /* See vmx_has_valid_vmcs12. */ 6674 if ((kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE) || 6675 (kvm_state->flags & KVM_STATE_NESTED_EVMCS) || 6676 (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA)) 6677 return -EINVAL; 6678 else 6679 return 0; 6680 } 6681 6682 if (kvm_state->hdr.vmx.vmcs12_pa != INVALID_GPA) { 6683 if (kvm_state->hdr.vmx.vmcs12_pa == kvm_state->hdr.vmx.vmxon_pa || 6684 !page_address_valid(vcpu, kvm_state->hdr.vmx.vmcs12_pa)) 6685 return -EINVAL; 6686 6687 set_current_vmptr(vmx, kvm_state->hdr.vmx.vmcs12_pa); 6688 } else if (kvm_state->flags & KVM_STATE_NESTED_EVMCS) { 6689 /* 6690 * nested_vmx_handle_enlightened_vmptrld() cannot be called 6691 * directly from here as HV_X64_MSR_VP_ASSIST_PAGE may not be 6692 * restored yet. EVMCS will be mapped from 6693 * nested_get_vmcs12_pages(). 6694 */ 6695 vmx->nested.hv_evmcs_vmptr = EVMPTR_MAP_PENDING; 6696 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 6697 } else { 6698 return -EINVAL; 6699 } 6700 6701 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) { 6702 vmx->nested.smm.vmxon = true; 6703 vmx->nested.vmxon = false; 6704 6705 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) 6706 vmx->nested.smm.guest_mode = true; 6707 } 6708 6709 vmcs12 = get_vmcs12(vcpu); 6710 if (copy_from_user(vmcs12, user_vmx_nested_state->vmcs12, sizeof(*vmcs12))) 6711 return -EFAULT; 6712 6713 if (vmcs12->hdr.revision_id != VMCS12_REVISION) 6714 return -EINVAL; 6715 6716 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE)) 6717 return 0; 6718 6719 vmx->nested.nested_run_pending = 6720 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING); 6721 6722 vmx->nested.mtf_pending = 6723 !!(kvm_state->flags & KVM_STATE_NESTED_MTF_PENDING); 6724 6725 ret = -EINVAL; 6726 if (nested_cpu_has_shadow_vmcs(vmcs12) && 6727 vmcs12->vmcs_link_pointer != INVALID_GPA) { 6728 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu); 6729 6730 if (kvm_state->size < 6731 sizeof(*kvm_state) + 6732 sizeof(user_vmx_nested_state->vmcs12) + sizeof(*shadow_vmcs12)) 6733 goto error_guest_mode; 6734 6735 if (copy_from_user(shadow_vmcs12, 6736 user_vmx_nested_state->shadow_vmcs12, 6737 sizeof(*shadow_vmcs12))) { 6738 ret = -EFAULT; 6739 goto error_guest_mode; 6740 } 6741 6742 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION || 6743 !shadow_vmcs12->hdr.shadow_vmcs) 6744 goto error_guest_mode; 6745 } 6746 6747 vmx->nested.has_preemption_timer_deadline = false; 6748 if (kvm_state->hdr.vmx.flags & KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE) { 6749 vmx->nested.has_preemption_timer_deadline = true; 6750 vmx->nested.preemption_timer_deadline = 6751 kvm_state->hdr.vmx.preemption_timer_deadline; 6752 } 6753 6754 if (nested_vmx_check_controls(vcpu, vmcs12) || 6755 nested_vmx_check_host_state(vcpu, vmcs12) || 6756 nested_vmx_check_guest_state(vcpu, vmcs12, &ignored)) 6757 goto error_guest_mode; 6758 6759 vmx->nested.dirty_vmcs12 = true; 6760 vmx->nested.force_msr_bitmap_recalc = true; 6761 ret = nested_vmx_enter_non_root_mode(vcpu, false); 6762 if (ret) 6763 goto error_guest_mode; 6764 6765 if (vmx->nested.mtf_pending) 6766 kvm_make_request(KVM_REQ_EVENT, vcpu); 6767 6768 return 0; 6769 6770 error_guest_mode: 6771 vmx->nested.nested_run_pending = 0; 6772 return ret; 6773 } 6774 6775 void nested_vmx_set_vmcs_shadowing_bitmap(void) 6776 { 6777 if (enable_shadow_vmcs) { 6778 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); 6779 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); 6780 } 6781 } 6782 6783 /* 6784 * Indexing into the vmcs12 uses the VMCS encoding rotated left by 6. Undo 6785 * that madness to get the encoding for comparison. 6786 */ 6787 #define VMCS12_IDX_TO_ENC(idx) ((u16)(((u16)(idx) >> 6) | ((u16)(idx) << 10))) 6788 6789 static u64 nested_vmx_calc_vmcs_enum_msr(void) 6790 { 6791 /* 6792 * Note these are the so called "index" of the VMCS field encoding, not 6793 * the index into vmcs12. 6794 */ 6795 unsigned int max_idx, idx; 6796 int i; 6797 6798 /* 6799 * For better or worse, KVM allows VMREAD/VMWRITE to all fields in 6800 * vmcs12, regardless of whether or not the associated feature is 6801 * exposed to L1. Simply find the field with the highest index. 6802 */ 6803 max_idx = 0; 6804 for (i = 0; i < nr_vmcs12_fields; i++) { 6805 /* The vmcs12 table is very, very sparsely populated. */ 6806 if (!vmcs12_field_offsets[i]) 6807 continue; 6808 6809 idx = vmcs_field_index(VMCS12_IDX_TO_ENC(i)); 6810 if (idx > max_idx) 6811 max_idx = idx; 6812 } 6813 6814 return (u64)max_idx << VMCS_FIELD_INDEX_SHIFT; 6815 } 6816 6817 static void nested_vmx_setup_pinbased_ctls(struct vmcs_config *vmcs_conf, 6818 struct nested_vmx_msrs *msrs) 6819 { 6820 msrs->pinbased_ctls_low = 6821 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 6822 6823 msrs->pinbased_ctls_high = vmcs_conf->pin_based_exec_ctrl; 6824 msrs->pinbased_ctls_high &= 6825 PIN_BASED_EXT_INTR_MASK | 6826 PIN_BASED_NMI_EXITING | 6827 PIN_BASED_VIRTUAL_NMIS | 6828 (enable_apicv ? PIN_BASED_POSTED_INTR : 0); 6829 msrs->pinbased_ctls_high |= 6830 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | 6831 PIN_BASED_VMX_PREEMPTION_TIMER; 6832 } 6833 6834 static void nested_vmx_setup_exit_ctls(struct vmcs_config *vmcs_conf, 6835 struct nested_vmx_msrs *msrs) 6836 { 6837 msrs->exit_ctls_low = 6838 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; 6839 6840 msrs->exit_ctls_high = vmcs_conf->vmexit_ctrl; 6841 msrs->exit_ctls_high &= 6842 #ifdef CONFIG_X86_64 6843 VM_EXIT_HOST_ADDR_SPACE_SIZE | 6844 #endif 6845 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT | 6846 VM_EXIT_CLEAR_BNDCFGS; 6847 msrs->exit_ctls_high |= 6848 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | 6849 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | 6850 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT | 6851 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 6852 6853 /* We support free control of debug control saving. */ 6854 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; 6855 } 6856 6857 static void nested_vmx_setup_entry_ctls(struct vmcs_config *vmcs_conf, 6858 struct nested_vmx_msrs *msrs) 6859 { 6860 msrs->entry_ctls_low = 6861 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; 6862 6863 msrs->entry_ctls_high = vmcs_conf->vmentry_ctrl; 6864 msrs->entry_ctls_high &= 6865 #ifdef CONFIG_X86_64 6866 VM_ENTRY_IA32E_MODE | 6867 #endif 6868 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; 6869 msrs->entry_ctls_high |= 6870 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER | 6871 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL); 6872 6873 /* We support free control of debug control loading. */ 6874 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; 6875 } 6876 6877 static void nested_vmx_setup_cpubased_ctls(struct vmcs_config *vmcs_conf, 6878 struct nested_vmx_msrs *msrs) 6879 { 6880 msrs->procbased_ctls_low = 6881 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 6882 6883 msrs->procbased_ctls_high = vmcs_conf->cpu_based_exec_ctrl; 6884 msrs->procbased_ctls_high &= 6885 CPU_BASED_INTR_WINDOW_EXITING | 6886 CPU_BASED_NMI_WINDOW_EXITING | CPU_BASED_USE_TSC_OFFSETTING | 6887 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | 6888 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | 6889 CPU_BASED_CR3_STORE_EXITING | 6890 #ifdef CONFIG_X86_64 6891 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | 6892 #endif 6893 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | 6894 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | 6895 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | 6896 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | 6897 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 6898 /* 6899 * We can allow some features even when not supported by the 6900 * hardware. For example, L1 can specify an MSR bitmap - and we 6901 * can use it to avoid exits to L1 - even when L0 runs L2 6902 * without MSR bitmaps. 6903 */ 6904 msrs->procbased_ctls_high |= 6905 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | 6906 CPU_BASED_USE_MSR_BITMAPS; 6907 6908 /* We support free control of CR3 access interception. */ 6909 msrs->procbased_ctls_low &= 6910 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); 6911 } 6912 6913 static void nested_vmx_setup_secondary_ctls(u32 ept_caps, 6914 struct vmcs_config *vmcs_conf, 6915 struct nested_vmx_msrs *msrs) 6916 { 6917 msrs->secondary_ctls_low = 0; 6918 6919 msrs->secondary_ctls_high = vmcs_conf->cpu_based_2nd_exec_ctrl; 6920 msrs->secondary_ctls_high &= 6921 SECONDARY_EXEC_DESC | 6922 SECONDARY_EXEC_ENABLE_RDTSCP | 6923 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6924 SECONDARY_EXEC_WBINVD_EXITING | 6925 SECONDARY_EXEC_APIC_REGISTER_VIRT | 6926 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 6927 SECONDARY_EXEC_RDRAND_EXITING | 6928 SECONDARY_EXEC_ENABLE_INVPCID | 6929 SECONDARY_EXEC_ENABLE_VMFUNC | 6930 SECONDARY_EXEC_RDSEED_EXITING | 6931 SECONDARY_EXEC_ENABLE_XSAVES | 6932 SECONDARY_EXEC_TSC_SCALING | 6933 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 6934 6935 /* 6936 * We can emulate "VMCS shadowing," even if the hardware 6937 * doesn't support it. 6938 */ 6939 msrs->secondary_ctls_high |= 6940 SECONDARY_EXEC_SHADOW_VMCS; 6941 6942 if (enable_ept) { 6943 /* nested EPT: emulate EPT also to L1 */ 6944 msrs->secondary_ctls_high |= 6945 SECONDARY_EXEC_ENABLE_EPT; 6946 msrs->ept_caps = 6947 VMX_EPT_PAGE_WALK_4_BIT | 6948 VMX_EPT_PAGE_WALK_5_BIT | 6949 VMX_EPTP_WB_BIT | 6950 VMX_EPT_INVEPT_BIT | 6951 VMX_EPT_EXECUTE_ONLY_BIT; 6952 6953 msrs->ept_caps &= ept_caps; 6954 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | 6955 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | 6956 VMX_EPT_1GB_PAGE_BIT; 6957 if (enable_ept_ad_bits) { 6958 msrs->secondary_ctls_high |= 6959 SECONDARY_EXEC_ENABLE_PML; 6960 msrs->ept_caps |= VMX_EPT_AD_BIT; 6961 } 6962 6963 /* 6964 * Advertise EPTP switching irrespective of hardware support, 6965 * KVM emulates it in software so long as VMFUNC is supported. 6966 */ 6967 if (cpu_has_vmx_vmfunc()) 6968 msrs->vmfunc_controls = VMX_VMFUNC_EPTP_SWITCHING; 6969 } 6970 6971 /* 6972 * Old versions of KVM use the single-context version without 6973 * checking for support, so declare that it is supported even 6974 * though it is treated as global context. The alternative is 6975 * not failing the single-context invvpid, and it is worse. 6976 */ 6977 if (enable_vpid) { 6978 msrs->secondary_ctls_high |= 6979 SECONDARY_EXEC_ENABLE_VPID; 6980 msrs->vpid_caps = VMX_VPID_INVVPID_BIT | 6981 VMX_VPID_EXTENT_SUPPORTED_MASK; 6982 } 6983 6984 if (enable_unrestricted_guest) 6985 msrs->secondary_ctls_high |= 6986 SECONDARY_EXEC_UNRESTRICTED_GUEST; 6987 6988 if (flexpriority_enabled) 6989 msrs->secondary_ctls_high |= 6990 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6991 6992 if (enable_sgx) 6993 msrs->secondary_ctls_high |= SECONDARY_EXEC_ENCLS_EXITING; 6994 } 6995 6996 static void nested_vmx_setup_misc_data(struct vmcs_config *vmcs_conf, 6997 struct nested_vmx_msrs *msrs) 6998 { 6999 msrs->misc_low = (u32)vmcs_conf->misc & VMX_MISC_SAVE_EFER_LMA; 7000 msrs->misc_low |= 7001 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS | 7002 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | 7003 VMX_MISC_ACTIVITY_HLT | 7004 VMX_MISC_ACTIVITY_WAIT_SIPI; 7005 msrs->misc_high = 0; 7006 } 7007 7008 static void nested_vmx_setup_basic(struct nested_vmx_msrs *msrs) 7009 { 7010 /* 7011 * This MSR reports some information about VMX support. We 7012 * should return information about the VMX we emulate for the 7013 * guest, and the VMCS structure we give it - not about the 7014 * VMX support of the underlying hardware. 7015 */ 7016 msrs->basic = 7017 VMCS12_REVISION | 7018 VMX_BASIC_TRUE_CTLS | 7019 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | 7020 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); 7021 7022 if (cpu_has_vmx_basic_inout()) 7023 msrs->basic |= VMX_BASIC_INOUT; 7024 } 7025 7026 static void nested_vmx_setup_cr_fixed(struct nested_vmx_msrs *msrs) 7027 { 7028 /* 7029 * These MSRs specify bits which the guest must keep fixed on 7030 * while L1 is in VMXON mode (in L1's root mode, or running an L2). 7031 * We picked the standard core2 setting. 7032 */ 7033 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) 7034 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE 7035 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON; 7036 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON; 7037 7038 /* These MSRs specify bits which the guest must keep fixed off. */ 7039 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1); 7040 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1); 7041 7042 if (vmx_umip_emulated()) 7043 msrs->cr4_fixed1 |= X86_CR4_UMIP; 7044 } 7045 7046 /* 7047 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be 7048 * returned for the various VMX controls MSRs when nested VMX is enabled. 7049 * The same values should also be used to verify that vmcs12 control fields are 7050 * valid during nested entry from L1 to L2. 7051 * Each of these control msrs has a low and high 32-bit half: A low bit is on 7052 * if the corresponding bit in the (32-bit) control field *must* be on, and a 7053 * bit in the high half is on if the corresponding bit in the control field 7054 * may be on. See also vmx_control_verify(). 7055 */ 7056 void nested_vmx_setup_ctls_msrs(struct vmcs_config *vmcs_conf, u32 ept_caps) 7057 { 7058 struct nested_vmx_msrs *msrs = &vmcs_conf->nested; 7059 7060 /* 7061 * Note that as a general rule, the high half of the MSRs (bits in 7062 * the control fields which may be 1) should be initialized by the 7063 * intersection of the underlying hardware's MSR (i.e., features which 7064 * can be supported) and the list of features we want to expose - 7065 * because they are known to be properly supported in our code. 7066 * Also, usually, the low half of the MSRs (bits which must be 1) can 7067 * be set to 0, meaning that L1 may turn off any of these bits. The 7068 * reason is that if one of these bits is necessary, it will appear 7069 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control 7070 * fields of vmcs01 and vmcs02, will turn these bits off - and 7071 * nested_vmx_l1_wants_exit() will not pass related exits to L1. 7072 * These rules have exceptions below. 7073 */ 7074 nested_vmx_setup_pinbased_ctls(vmcs_conf, msrs); 7075 7076 nested_vmx_setup_exit_ctls(vmcs_conf, msrs); 7077 7078 nested_vmx_setup_entry_ctls(vmcs_conf, msrs); 7079 7080 nested_vmx_setup_cpubased_ctls(vmcs_conf, msrs); 7081 7082 nested_vmx_setup_secondary_ctls(ept_caps, vmcs_conf, msrs); 7083 7084 nested_vmx_setup_misc_data(vmcs_conf, msrs); 7085 7086 nested_vmx_setup_basic(msrs); 7087 7088 nested_vmx_setup_cr_fixed(msrs); 7089 7090 msrs->vmcs_enum = nested_vmx_calc_vmcs_enum_msr(); 7091 } 7092 7093 void nested_vmx_hardware_unsetup(void) 7094 { 7095 int i; 7096 7097 if (enable_shadow_vmcs) { 7098 for (i = 0; i < VMX_BITMAP_NR; i++) 7099 free_page((unsigned long)vmx_bitmap[i]); 7100 } 7101 } 7102 7103 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *)) 7104 { 7105 int i; 7106 7107 if (!cpu_has_vmx_shadow_vmcs()) 7108 enable_shadow_vmcs = 0; 7109 if (enable_shadow_vmcs) { 7110 for (i = 0; i < VMX_BITMAP_NR; i++) { 7111 /* 7112 * The vmx_bitmap is not tied to a VM and so should 7113 * not be charged to a memcg. 7114 */ 7115 vmx_bitmap[i] = (unsigned long *) 7116 __get_free_page(GFP_KERNEL); 7117 if (!vmx_bitmap[i]) { 7118 nested_vmx_hardware_unsetup(); 7119 return -ENOMEM; 7120 } 7121 } 7122 7123 init_vmcs_shadow_fields(); 7124 } 7125 7126 exit_handlers[EXIT_REASON_VMCLEAR] = handle_vmclear; 7127 exit_handlers[EXIT_REASON_VMLAUNCH] = handle_vmlaunch; 7128 exit_handlers[EXIT_REASON_VMPTRLD] = handle_vmptrld; 7129 exit_handlers[EXIT_REASON_VMPTRST] = handle_vmptrst; 7130 exit_handlers[EXIT_REASON_VMREAD] = handle_vmread; 7131 exit_handlers[EXIT_REASON_VMRESUME] = handle_vmresume; 7132 exit_handlers[EXIT_REASON_VMWRITE] = handle_vmwrite; 7133 exit_handlers[EXIT_REASON_VMOFF] = handle_vmxoff; 7134 exit_handlers[EXIT_REASON_VMON] = handle_vmxon; 7135 exit_handlers[EXIT_REASON_INVEPT] = handle_invept; 7136 exit_handlers[EXIT_REASON_INVVPID] = handle_invvpid; 7137 exit_handlers[EXIT_REASON_VMFUNC] = handle_vmfunc; 7138 7139 return 0; 7140 } 7141 7142 struct kvm_x86_nested_ops vmx_nested_ops = { 7143 .leave_nested = vmx_leave_nested, 7144 .is_exception_vmexit = nested_vmx_is_exception_vmexit, 7145 .check_events = vmx_check_nested_events, 7146 .has_events = vmx_has_nested_events, 7147 .triple_fault = nested_vmx_triple_fault, 7148 .get_state = vmx_get_nested_state, 7149 .set_state = vmx_set_nested_state, 7150 .get_nested_state_pages = vmx_get_nested_state_pages, 7151 .write_log_dirty = nested_vmx_write_pml_buffer, 7152 .enable_evmcs = nested_enable_evmcs, 7153 .get_evmcs_version = nested_get_evmcs_version, 7154 .hv_inject_synthetic_vmexit_post_tlb_flush = vmx_hv_inject_synthetic_vmexit_post_tlb_flush, 7155 }; 7156