1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/objtool.h> 4 #include <linux/percpu.h> 5 6 #include <asm/debugreg.h> 7 #include <asm/mmu_context.h> 8 9 #include "cpuid.h" 10 #include "hyperv.h" 11 #include "mmu.h" 12 #include "nested.h" 13 #include "pmu.h" 14 #include "trace.h" 15 #include "x86.h" 16 17 static bool __read_mostly enable_shadow_vmcs = 1; 18 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); 19 20 static bool __read_mostly nested_early_check = 0; 21 module_param(nested_early_check, bool, S_IRUGO); 22 23 #define CC(consistency_check) \ 24 ({ \ 25 bool failed = (consistency_check); \ 26 if (failed) \ 27 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \ 28 failed; \ 29 }) 30 31 /* 32 * Hyper-V requires all of these, so mark them as supported even though 33 * they are just treated the same as all-context. 34 */ 35 #define VMX_VPID_EXTENT_SUPPORTED_MASK \ 36 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ 37 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ 38 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ 39 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) 40 41 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 42 43 enum { 44 VMX_VMREAD_BITMAP, 45 VMX_VMWRITE_BITMAP, 46 VMX_BITMAP_NR 47 }; 48 static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; 49 50 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) 51 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) 52 53 struct shadow_vmcs_field { 54 u16 encoding; 55 u16 offset; 56 }; 57 static struct shadow_vmcs_field shadow_read_only_fields[] = { 58 #define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) }, 59 #include "vmcs_shadow_fields.h" 60 }; 61 static int max_shadow_read_only_fields = 62 ARRAY_SIZE(shadow_read_only_fields); 63 64 static struct shadow_vmcs_field shadow_read_write_fields[] = { 65 #define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) }, 66 #include "vmcs_shadow_fields.h" 67 }; 68 static int max_shadow_read_write_fields = 69 ARRAY_SIZE(shadow_read_write_fields); 70 71 static void init_vmcs_shadow_fields(void) 72 { 73 int i, j; 74 75 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); 76 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); 77 78 for (i = j = 0; i < max_shadow_read_only_fields; i++) { 79 struct shadow_vmcs_field entry = shadow_read_only_fields[i]; 80 u16 field = entry.encoding; 81 82 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 && 83 (i + 1 == max_shadow_read_only_fields || 84 shadow_read_only_fields[i + 1].encoding != field + 1)) 85 pr_err("Missing field from shadow_read_only_field %x\n", 86 field + 1); 87 88 clear_bit(field, vmx_vmread_bitmap); 89 if (field & 1) 90 #ifdef CONFIG_X86_64 91 continue; 92 #else 93 entry.offset += sizeof(u32); 94 #endif 95 shadow_read_only_fields[j++] = entry; 96 } 97 max_shadow_read_only_fields = j; 98 99 for (i = j = 0; i < max_shadow_read_write_fields; i++) { 100 struct shadow_vmcs_field entry = shadow_read_write_fields[i]; 101 u16 field = entry.encoding; 102 103 if (vmcs_field_width(field) == VMCS_FIELD_WIDTH_U64 && 104 (i + 1 == max_shadow_read_write_fields || 105 shadow_read_write_fields[i + 1].encoding != field + 1)) 106 pr_err("Missing field from shadow_read_write_field %x\n", 107 field + 1); 108 109 WARN_ONCE(field >= GUEST_ES_AR_BYTES && 110 field <= GUEST_TR_AR_BYTES, 111 "Update vmcs12_write_any() to drop reserved bits from AR_BYTES"); 112 113 /* 114 * PML and the preemption timer can be emulated, but the 115 * processor cannot vmwrite to fields that don't exist 116 * on bare metal. 117 */ 118 switch (field) { 119 case GUEST_PML_INDEX: 120 if (!cpu_has_vmx_pml()) 121 continue; 122 break; 123 case VMX_PREEMPTION_TIMER_VALUE: 124 if (!cpu_has_vmx_preemption_timer()) 125 continue; 126 break; 127 case GUEST_INTR_STATUS: 128 if (!cpu_has_vmx_apicv()) 129 continue; 130 break; 131 default: 132 break; 133 } 134 135 clear_bit(field, vmx_vmwrite_bitmap); 136 clear_bit(field, vmx_vmread_bitmap); 137 if (field & 1) 138 #ifdef CONFIG_X86_64 139 continue; 140 #else 141 entry.offset += sizeof(u32); 142 #endif 143 shadow_read_write_fields[j++] = entry; 144 } 145 max_shadow_read_write_fields = j; 146 } 147 148 /* 149 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), 150 * set the success or error code of an emulated VMX instruction (as specified 151 * by Vol 2B, VMX Instruction Reference, "Conventions"), and skip the emulated 152 * instruction. 153 */ 154 static int nested_vmx_succeed(struct kvm_vcpu *vcpu) 155 { 156 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) 157 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 158 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); 159 return kvm_skip_emulated_instruction(vcpu); 160 } 161 162 static int nested_vmx_failInvalid(struct kvm_vcpu *vcpu) 163 { 164 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) 165 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 166 X86_EFLAGS_SF | X86_EFLAGS_OF)) 167 | X86_EFLAGS_CF); 168 return kvm_skip_emulated_instruction(vcpu); 169 } 170 171 static int nested_vmx_failValid(struct kvm_vcpu *vcpu, 172 u32 vm_instruction_error) 173 { 174 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) 175 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 176 X86_EFLAGS_SF | X86_EFLAGS_OF)) 177 | X86_EFLAGS_ZF); 178 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; 179 /* 180 * We don't need to force a shadow sync because 181 * VM_INSTRUCTION_ERROR is not shadowed 182 */ 183 return kvm_skip_emulated_instruction(vcpu); 184 } 185 186 static int nested_vmx_fail(struct kvm_vcpu *vcpu, u32 vm_instruction_error) 187 { 188 struct vcpu_vmx *vmx = to_vmx(vcpu); 189 190 /* 191 * failValid writes the error number to the current VMCS, which 192 * can't be done if there isn't a current VMCS. 193 */ 194 if (vmx->nested.current_vmptr == -1ull && !vmx->nested.hv_evmcs) 195 return nested_vmx_failInvalid(vcpu); 196 197 return nested_vmx_failValid(vcpu, vm_instruction_error); 198 } 199 200 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) 201 { 202 /* TODO: not to reset guest simply here. */ 203 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 204 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); 205 } 206 207 static inline bool vmx_control_verify(u32 control, u32 low, u32 high) 208 { 209 return fixed_bits_valid(control, low, high); 210 } 211 212 static inline u64 vmx_control_msr(u32 low, u32 high) 213 { 214 return low | ((u64)high << 32); 215 } 216 217 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) 218 { 219 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_SHADOW_VMCS); 220 vmcs_write64(VMCS_LINK_POINTER, -1ull); 221 vmx->nested.need_vmcs12_to_shadow_sync = false; 222 } 223 224 static inline void nested_release_evmcs(struct kvm_vcpu *vcpu) 225 { 226 struct vcpu_vmx *vmx = to_vmx(vcpu); 227 228 if (!vmx->nested.hv_evmcs) 229 return; 230 231 kvm_vcpu_unmap(vcpu, &vmx->nested.hv_evmcs_map, true); 232 vmx->nested.hv_evmcs_vmptr = 0; 233 vmx->nested.hv_evmcs = NULL; 234 } 235 236 static void vmx_sync_vmcs_host_state(struct vcpu_vmx *vmx, 237 struct loaded_vmcs *prev) 238 { 239 struct vmcs_host_state *dest, *src; 240 241 if (unlikely(!vmx->guest_state_loaded)) 242 return; 243 244 src = &prev->host_state; 245 dest = &vmx->loaded_vmcs->host_state; 246 247 vmx_set_host_fs_gs(dest, src->fs_sel, src->gs_sel, src->fs_base, src->gs_base); 248 dest->ldt_sel = src->ldt_sel; 249 #ifdef CONFIG_X86_64 250 dest->ds_sel = src->ds_sel; 251 dest->es_sel = src->es_sel; 252 #endif 253 } 254 255 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) 256 { 257 struct vcpu_vmx *vmx = to_vmx(vcpu); 258 struct loaded_vmcs *prev; 259 int cpu; 260 261 if (WARN_ON_ONCE(vmx->loaded_vmcs == vmcs)) 262 return; 263 264 cpu = get_cpu(); 265 prev = vmx->loaded_vmcs; 266 vmx->loaded_vmcs = vmcs; 267 vmx_vcpu_load_vmcs(vcpu, cpu, prev); 268 vmx_sync_vmcs_host_state(vmx, prev); 269 put_cpu(); 270 271 vmx_register_cache_reset(vcpu); 272 } 273 274 /* 275 * Free whatever needs to be freed from vmx->nested when L1 goes down, or 276 * just stops using VMX. 277 */ 278 static void free_nested(struct kvm_vcpu *vcpu) 279 { 280 struct vcpu_vmx *vmx = to_vmx(vcpu); 281 282 if (WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01)) 283 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 284 285 if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) 286 return; 287 288 kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 289 290 vmx->nested.vmxon = false; 291 vmx->nested.smm.vmxon = false; 292 free_vpid(vmx->nested.vpid02); 293 vmx->nested.posted_intr_nv = -1; 294 vmx->nested.current_vmptr = -1ull; 295 if (enable_shadow_vmcs) { 296 vmx_disable_shadow_vmcs(vmx); 297 vmcs_clear(vmx->vmcs01.shadow_vmcs); 298 free_vmcs(vmx->vmcs01.shadow_vmcs); 299 vmx->vmcs01.shadow_vmcs = NULL; 300 } 301 kfree(vmx->nested.cached_vmcs12); 302 vmx->nested.cached_vmcs12 = NULL; 303 kfree(vmx->nested.cached_shadow_vmcs12); 304 vmx->nested.cached_shadow_vmcs12 = NULL; 305 /* Unpin physical memory we referred to in the vmcs02 */ 306 if (vmx->nested.apic_access_page) { 307 kvm_release_page_clean(vmx->nested.apic_access_page); 308 vmx->nested.apic_access_page = NULL; 309 } 310 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true); 311 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true); 312 vmx->nested.pi_desc = NULL; 313 314 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); 315 316 nested_release_evmcs(vcpu); 317 318 free_loaded_vmcs(&vmx->nested.vmcs02); 319 } 320 321 /* 322 * Ensure that the current vmcs of the logical processor is the 323 * vmcs01 of the vcpu before calling free_nested(). 324 */ 325 void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu) 326 { 327 vcpu_load(vcpu); 328 vmx_leave_nested(vcpu); 329 vcpu_put(vcpu); 330 } 331 332 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, 333 struct x86_exception *fault) 334 { 335 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 336 struct vcpu_vmx *vmx = to_vmx(vcpu); 337 u32 vm_exit_reason; 338 unsigned long exit_qualification = vcpu->arch.exit_qualification; 339 340 if (vmx->nested.pml_full) { 341 vm_exit_reason = EXIT_REASON_PML_FULL; 342 vmx->nested.pml_full = false; 343 exit_qualification &= INTR_INFO_UNBLOCK_NMI; 344 } else if (fault->error_code & PFERR_RSVD_MASK) 345 vm_exit_reason = EXIT_REASON_EPT_MISCONFIG; 346 else 347 vm_exit_reason = EXIT_REASON_EPT_VIOLATION; 348 349 nested_vmx_vmexit(vcpu, vm_exit_reason, 0, exit_qualification); 350 vmcs12->guest_physical_address = fault->address; 351 } 352 353 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) 354 { 355 WARN_ON(mmu_is_nested(vcpu)); 356 357 vcpu->arch.mmu = &vcpu->arch.guest_mmu; 358 kvm_init_shadow_ept_mmu(vcpu, 359 to_vmx(vcpu)->nested.msrs.ept_caps & 360 VMX_EPT_EXECUTE_ONLY_BIT, 361 nested_ept_ad_enabled(vcpu), 362 nested_ept_get_eptp(vcpu)); 363 vcpu->arch.mmu->get_guest_pgd = nested_ept_get_eptp; 364 vcpu->arch.mmu->inject_page_fault = nested_ept_inject_page_fault; 365 vcpu->arch.mmu->get_pdptr = kvm_pdptr_read; 366 367 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; 368 } 369 370 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) 371 { 372 vcpu->arch.mmu = &vcpu->arch.root_mmu; 373 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; 374 } 375 376 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, 377 u16 error_code) 378 { 379 bool inequality, bit; 380 381 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; 382 inequality = 383 (error_code & vmcs12->page_fault_error_code_mask) != 384 vmcs12->page_fault_error_code_match; 385 return inequality ^ bit; 386 } 387 388 389 /* 390 * KVM wants to inject page-faults which it got to the guest. This function 391 * checks whether in a nested guest, we need to inject them to L1 or L2. 392 */ 393 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual) 394 { 395 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 396 unsigned int nr = vcpu->arch.exception.nr; 397 bool has_payload = vcpu->arch.exception.has_payload; 398 unsigned long payload = vcpu->arch.exception.payload; 399 400 if (nr == PF_VECTOR) { 401 if (vcpu->arch.exception.nested_apf) { 402 *exit_qual = vcpu->arch.apf.nested_apf_token; 403 return 1; 404 } 405 if (nested_vmx_is_page_fault_vmexit(vmcs12, 406 vcpu->arch.exception.error_code)) { 407 *exit_qual = has_payload ? payload : vcpu->arch.cr2; 408 return 1; 409 } 410 } else if (vmcs12->exception_bitmap & (1u << nr)) { 411 if (nr == DB_VECTOR) { 412 if (!has_payload) { 413 payload = vcpu->arch.dr6; 414 payload &= ~(DR6_FIXED_1 | DR6_BT); 415 payload ^= DR6_RTM; 416 } 417 *exit_qual = payload; 418 } else 419 *exit_qual = 0; 420 return 1; 421 } 422 423 return 0; 424 } 425 426 427 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, 428 struct x86_exception *fault) 429 { 430 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 431 432 WARN_ON(!is_guest_mode(vcpu)); 433 434 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) && 435 !to_vmx(vcpu)->nested.nested_run_pending) { 436 vmcs12->vm_exit_intr_error_code = fault->error_code; 437 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, 438 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION | 439 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK, 440 fault->address); 441 } else { 442 kvm_inject_page_fault(vcpu, fault); 443 } 444 } 445 446 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, 447 struct vmcs12 *vmcs12) 448 { 449 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 450 return 0; 451 452 if (CC(!page_address_valid(vcpu, vmcs12->io_bitmap_a)) || 453 CC(!page_address_valid(vcpu, vmcs12->io_bitmap_b))) 454 return -EINVAL; 455 456 return 0; 457 } 458 459 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, 460 struct vmcs12 *vmcs12) 461 { 462 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 463 return 0; 464 465 if (CC(!page_address_valid(vcpu, vmcs12->msr_bitmap))) 466 return -EINVAL; 467 468 return 0; 469 } 470 471 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, 472 struct vmcs12 *vmcs12) 473 { 474 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 475 return 0; 476 477 if (CC(!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))) 478 return -EINVAL; 479 480 return 0; 481 } 482 483 /* 484 * Check if MSR is intercepted for L01 MSR bitmap. 485 */ 486 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr) 487 { 488 unsigned long *msr_bitmap; 489 int f = sizeof(unsigned long); 490 491 if (!cpu_has_vmx_msr_bitmap()) 492 return true; 493 494 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap; 495 496 if (msr <= 0x1fff) { 497 return !!test_bit(msr, msr_bitmap + 0x800 / f); 498 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 499 msr &= 0x1fff; 500 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 501 } 502 503 return true; 504 } 505 506 /* 507 * If a msr is allowed by L0, we should check whether it is allowed by L1. 508 * The corresponding bit will be cleared unless both of L0 and L1 allow it. 509 */ 510 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, 511 unsigned long *msr_bitmap_nested, 512 u32 msr, int type) 513 { 514 int f = sizeof(unsigned long); 515 516 /* 517 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 518 * have the write-low and read-high bitmap offsets the wrong way round. 519 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 520 */ 521 if (msr <= 0x1fff) { 522 if (type & MSR_TYPE_R && 523 !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) 524 /* read-low */ 525 __clear_bit(msr, msr_bitmap_nested + 0x000 / f); 526 527 if (type & MSR_TYPE_W && 528 !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) 529 /* write-low */ 530 __clear_bit(msr, msr_bitmap_nested + 0x800 / f); 531 532 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 533 msr &= 0x1fff; 534 if (type & MSR_TYPE_R && 535 !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) 536 /* read-high */ 537 __clear_bit(msr, msr_bitmap_nested + 0x400 / f); 538 539 if (type & MSR_TYPE_W && 540 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) 541 /* write-high */ 542 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); 543 544 } 545 } 546 547 static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap) 548 { 549 int msr; 550 551 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 552 unsigned word = msr / BITS_PER_LONG; 553 554 msr_bitmap[word] = ~0; 555 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 556 } 557 } 558 559 /* 560 * Merge L0's and L1's MSR bitmap, return false to indicate that 561 * we do not use the hardware. 562 */ 563 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, 564 struct vmcs12 *vmcs12) 565 { 566 int msr; 567 unsigned long *msr_bitmap_l1; 568 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap; 569 struct kvm_host_map *map = &to_vmx(vcpu)->nested.msr_bitmap_map; 570 571 /* Nothing to do if the MSR bitmap is not in use. */ 572 if (!cpu_has_vmx_msr_bitmap() || 573 !nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 574 return false; 575 576 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->msr_bitmap), map)) 577 return false; 578 579 msr_bitmap_l1 = (unsigned long *)map->hva; 580 581 /* 582 * To keep the control flow simple, pay eight 8-byte writes (sixteen 583 * 4-byte writes on 32-bit systems) up front to enable intercepts for 584 * the x2APIC MSR range and selectively disable them below. 585 */ 586 enable_x2apic_msr_intercepts(msr_bitmap_l0); 587 588 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { 589 if (nested_cpu_has_apic_reg_virt(vmcs12)) { 590 /* 591 * L0 need not intercept reads for MSRs between 0x800 592 * and 0x8ff, it just lets the processor take the value 593 * from the virtual-APIC page; take those 256 bits 594 * directly from the L1 bitmap. 595 */ 596 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 597 unsigned word = msr / BITS_PER_LONG; 598 599 msr_bitmap_l0[word] = msr_bitmap_l1[word]; 600 } 601 } 602 603 nested_vmx_disable_intercept_for_msr( 604 msr_bitmap_l1, msr_bitmap_l0, 605 X2APIC_MSR(APIC_TASKPRI), 606 MSR_TYPE_R | MSR_TYPE_W); 607 608 if (nested_cpu_has_vid(vmcs12)) { 609 nested_vmx_disable_intercept_for_msr( 610 msr_bitmap_l1, msr_bitmap_l0, 611 X2APIC_MSR(APIC_EOI), 612 MSR_TYPE_W); 613 nested_vmx_disable_intercept_for_msr( 614 msr_bitmap_l1, msr_bitmap_l0, 615 X2APIC_MSR(APIC_SELF_IPI), 616 MSR_TYPE_W); 617 } 618 } 619 620 /* KVM unconditionally exposes the FS/GS base MSRs to L1. */ 621 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0, 622 MSR_FS_BASE, MSR_TYPE_RW); 623 624 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0, 625 MSR_GS_BASE, MSR_TYPE_RW); 626 627 nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0, 628 MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 629 630 /* 631 * Checking the L0->L1 bitmap is trying to verify two things: 632 * 633 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This 634 * ensures that we do not accidentally generate an L02 MSR bitmap 635 * from the L12 MSR bitmap that is too permissive. 636 * 2. That L1 or L2s have actually used the MSR. This avoids 637 * unnecessarily merging of the bitmap if the MSR is unused. This 638 * works properly because we only update the L01 MSR bitmap lazily. 639 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only 640 * updated to reflect this when L1 (or its L2s) actually write to 641 * the MSR. 642 */ 643 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL)) 644 nested_vmx_disable_intercept_for_msr( 645 msr_bitmap_l1, msr_bitmap_l0, 646 MSR_IA32_SPEC_CTRL, 647 MSR_TYPE_R | MSR_TYPE_W); 648 649 if (!msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD)) 650 nested_vmx_disable_intercept_for_msr( 651 msr_bitmap_l1, msr_bitmap_l0, 652 MSR_IA32_PRED_CMD, 653 MSR_TYPE_W); 654 655 kvm_vcpu_unmap(vcpu, &to_vmx(vcpu)->nested.msr_bitmap_map, false); 656 657 return true; 658 } 659 660 static void nested_cache_shadow_vmcs12(struct kvm_vcpu *vcpu, 661 struct vmcs12 *vmcs12) 662 { 663 struct kvm_host_map map; 664 struct vmcs12 *shadow; 665 666 if (!nested_cpu_has_shadow_vmcs(vmcs12) || 667 vmcs12->vmcs_link_pointer == -1ull) 668 return; 669 670 shadow = get_shadow_vmcs12(vcpu); 671 672 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map)) 673 return; 674 675 memcpy(shadow, map.hva, VMCS12_SIZE); 676 kvm_vcpu_unmap(vcpu, &map, false); 677 } 678 679 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu *vcpu, 680 struct vmcs12 *vmcs12) 681 { 682 struct vcpu_vmx *vmx = to_vmx(vcpu); 683 684 if (!nested_cpu_has_shadow_vmcs(vmcs12) || 685 vmcs12->vmcs_link_pointer == -1ull) 686 return; 687 688 kvm_write_guest(vmx->vcpu.kvm, vmcs12->vmcs_link_pointer, 689 get_shadow_vmcs12(vcpu), VMCS12_SIZE); 690 } 691 692 /* 693 * In nested virtualization, check if L1 has set 694 * VM_EXIT_ACK_INTR_ON_EXIT 695 */ 696 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) 697 { 698 return get_vmcs12(vcpu)->vm_exit_controls & 699 VM_EXIT_ACK_INTR_ON_EXIT; 700 } 701 702 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu, 703 struct vmcs12 *vmcs12) 704 { 705 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) && 706 CC(!page_address_valid(vcpu, vmcs12->apic_access_addr))) 707 return -EINVAL; 708 else 709 return 0; 710 } 711 712 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, 713 struct vmcs12 *vmcs12) 714 { 715 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && 716 !nested_cpu_has_apic_reg_virt(vmcs12) && 717 !nested_cpu_has_vid(vmcs12) && 718 !nested_cpu_has_posted_intr(vmcs12)) 719 return 0; 720 721 /* 722 * If virtualize x2apic mode is enabled, 723 * virtualize apic access must be disabled. 724 */ 725 if (CC(nested_cpu_has_virt_x2apic_mode(vmcs12) && 726 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))) 727 return -EINVAL; 728 729 /* 730 * If virtual interrupt delivery is enabled, 731 * we must exit on external interrupts. 732 */ 733 if (CC(nested_cpu_has_vid(vmcs12) && !nested_exit_on_intr(vcpu))) 734 return -EINVAL; 735 736 /* 737 * bits 15:8 should be zero in posted_intr_nv, 738 * the descriptor address has been already checked 739 * in nested_get_vmcs12_pages. 740 * 741 * bits 5:0 of posted_intr_desc_addr should be zero. 742 */ 743 if (nested_cpu_has_posted_intr(vmcs12) && 744 (CC(!nested_cpu_has_vid(vmcs12)) || 745 CC(!nested_exit_intr_ack_set(vcpu)) || 746 CC((vmcs12->posted_intr_nv & 0xff00)) || 747 CC((vmcs12->posted_intr_desc_addr & 0x3f)) || 748 CC((vmcs12->posted_intr_desc_addr >> cpuid_maxphyaddr(vcpu))))) 749 return -EINVAL; 750 751 /* tpr shadow is needed by all apicv features. */ 752 if (CC(!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))) 753 return -EINVAL; 754 755 return 0; 756 } 757 758 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, 759 u32 count, u64 addr) 760 { 761 int maxphyaddr; 762 763 if (count == 0) 764 return 0; 765 maxphyaddr = cpuid_maxphyaddr(vcpu); 766 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || 767 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) 768 return -EINVAL; 769 770 return 0; 771 } 772 773 static int nested_vmx_check_exit_msr_switch_controls(struct kvm_vcpu *vcpu, 774 struct vmcs12 *vmcs12) 775 { 776 if (CC(nested_vmx_check_msr_switch(vcpu, 777 vmcs12->vm_exit_msr_load_count, 778 vmcs12->vm_exit_msr_load_addr)) || 779 CC(nested_vmx_check_msr_switch(vcpu, 780 vmcs12->vm_exit_msr_store_count, 781 vmcs12->vm_exit_msr_store_addr))) 782 return -EINVAL; 783 784 return 0; 785 } 786 787 static int nested_vmx_check_entry_msr_switch_controls(struct kvm_vcpu *vcpu, 788 struct vmcs12 *vmcs12) 789 { 790 if (CC(nested_vmx_check_msr_switch(vcpu, 791 vmcs12->vm_entry_msr_load_count, 792 vmcs12->vm_entry_msr_load_addr))) 793 return -EINVAL; 794 795 return 0; 796 } 797 798 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, 799 struct vmcs12 *vmcs12) 800 { 801 if (!nested_cpu_has_pml(vmcs12)) 802 return 0; 803 804 if (CC(!nested_cpu_has_ept(vmcs12)) || 805 CC(!page_address_valid(vcpu, vmcs12->pml_address))) 806 return -EINVAL; 807 808 return 0; 809 } 810 811 static int nested_vmx_check_unrestricted_guest_controls(struct kvm_vcpu *vcpu, 812 struct vmcs12 *vmcs12) 813 { 814 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST) && 815 !nested_cpu_has_ept(vmcs12))) 816 return -EINVAL; 817 return 0; 818 } 819 820 static int nested_vmx_check_mode_based_ept_exec_controls(struct kvm_vcpu *vcpu, 821 struct vmcs12 *vmcs12) 822 { 823 if (CC(nested_cpu_has2(vmcs12, SECONDARY_EXEC_MODE_BASED_EPT_EXEC) && 824 !nested_cpu_has_ept(vmcs12))) 825 return -EINVAL; 826 return 0; 827 } 828 829 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu *vcpu, 830 struct vmcs12 *vmcs12) 831 { 832 if (!nested_cpu_has_shadow_vmcs(vmcs12)) 833 return 0; 834 835 if (CC(!page_address_valid(vcpu, vmcs12->vmread_bitmap)) || 836 CC(!page_address_valid(vcpu, vmcs12->vmwrite_bitmap))) 837 return -EINVAL; 838 839 return 0; 840 } 841 842 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, 843 struct vmx_msr_entry *e) 844 { 845 /* x2APIC MSR accesses are not allowed */ 846 if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)) 847 return -EINVAL; 848 if (CC(e->index == MSR_IA32_UCODE_WRITE) || /* SDM Table 35-2 */ 849 CC(e->index == MSR_IA32_UCODE_REV)) 850 return -EINVAL; 851 if (CC(e->reserved != 0)) 852 return -EINVAL; 853 return 0; 854 } 855 856 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, 857 struct vmx_msr_entry *e) 858 { 859 if (CC(e->index == MSR_FS_BASE) || 860 CC(e->index == MSR_GS_BASE) || 861 CC(e->index == MSR_IA32_SMM_MONITOR_CTL) || /* SMM is not supported */ 862 nested_vmx_msr_check_common(vcpu, e)) 863 return -EINVAL; 864 return 0; 865 } 866 867 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, 868 struct vmx_msr_entry *e) 869 { 870 if (CC(e->index == MSR_IA32_SMBASE) || /* SMM is not supported */ 871 nested_vmx_msr_check_common(vcpu, e)) 872 return -EINVAL; 873 return 0; 874 } 875 876 static u32 nested_vmx_max_atomic_switch_msrs(struct kvm_vcpu *vcpu) 877 { 878 struct vcpu_vmx *vmx = to_vmx(vcpu); 879 u64 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low, 880 vmx->nested.msrs.misc_high); 881 882 return (vmx_misc_max_msr(vmx_misc) + 1) * VMX_MISC_MSR_LIST_MULTIPLIER; 883 } 884 885 /* 886 * Load guest's/host's msr at nested entry/exit. 887 * return 0 for success, entry index for failure. 888 * 889 * One of the failure modes for MSR load/store is when a list exceeds the 890 * virtual hardware's capacity. To maintain compatibility with hardware inasmuch 891 * as possible, process all valid entries before failing rather than precheck 892 * for a capacity violation. 893 */ 894 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) 895 { 896 u32 i; 897 struct vmx_msr_entry e; 898 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu); 899 900 for (i = 0; i < count; i++) { 901 if (unlikely(i >= max_msr_list_size)) 902 goto fail; 903 904 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), 905 &e, sizeof(e))) { 906 pr_debug_ratelimited( 907 "%s cannot read MSR entry (%u, 0x%08llx)\n", 908 __func__, i, gpa + i * sizeof(e)); 909 goto fail; 910 } 911 if (nested_vmx_load_msr_check(vcpu, &e)) { 912 pr_debug_ratelimited( 913 "%s check failed (%u, 0x%x, 0x%x)\n", 914 __func__, i, e.index, e.reserved); 915 goto fail; 916 } 917 if (kvm_set_msr(vcpu, e.index, e.value)) { 918 pr_debug_ratelimited( 919 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", 920 __func__, i, e.index, e.value); 921 goto fail; 922 } 923 } 924 return 0; 925 fail: 926 /* Note, max_msr_list_size is at most 4096, i.e. this can't wrap. */ 927 return i + 1; 928 } 929 930 static bool nested_vmx_get_vmexit_msr_value(struct kvm_vcpu *vcpu, 931 u32 msr_index, 932 u64 *data) 933 { 934 struct vcpu_vmx *vmx = to_vmx(vcpu); 935 936 /* 937 * If the L0 hypervisor stored a more accurate value for the TSC that 938 * does not include the time taken for emulation of the L2->L1 939 * VM-exit in L0, use the more accurate value. 940 */ 941 if (msr_index == MSR_IA32_TSC) { 942 int i = vmx_find_loadstore_msr_slot(&vmx->msr_autostore.guest, 943 MSR_IA32_TSC); 944 945 if (i >= 0) { 946 u64 val = vmx->msr_autostore.guest.val[i].value; 947 948 *data = kvm_read_l1_tsc(vcpu, val); 949 return true; 950 } 951 } 952 953 if (kvm_get_msr(vcpu, msr_index, data)) { 954 pr_debug_ratelimited("%s cannot read MSR (0x%x)\n", __func__, 955 msr_index); 956 return false; 957 } 958 return true; 959 } 960 961 static bool read_and_check_msr_entry(struct kvm_vcpu *vcpu, u64 gpa, int i, 962 struct vmx_msr_entry *e) 963 { 964 if (kvm_vcpu_read_guest(vcpu, 965 gpa + i * sizeof(*e), 966 e, 2 * sizeof(u32))) { 967 pr_debug_ratelimited( 968 "%s cannot read MSR entry (%u, 0x%08llx)\n", 969 __func__, i, gpa + i * sizeof(*e)); 970 return false; 971 } 972 if (nested_vmx_store_msr_check(vcpu, e)) { 973 pr_debug_ratelimited( 974 "%s check failed (%u, 0x%x, 0x%x)\n", 975 __func__, i, e->index, e->reserved); 976 return false; 977 } 978 return true; 979 } 980 981 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) 982 { 983 u64 data; 984 u32 i; 985 struct vmx_msr_entry e; 986 u32 max_msr_list_size = nested_vmx_max_atomic_switch_msrs(vcpu); 987 988 for (i = 0; i < count; i++) { 989 if (unlikely(i >= max_msr_list_size)) 990 return -EINVAL; 991 992 if (!read_and_check_msr_entry(vcpu, gpa, i, &e)) 993 return -EINVAL; 994 995 if (!nested_vmx_get_vmexit_msr_value(vcpu, e.index, &data)) 996 return -EINVAL; 997 998 if (kvm_vcpu_write_guest(vcpu, 999 gpa + i * sizeof(e) + 1000 offsetof(struct vmx_msr_entry, value), 1001 &data, sizeof(data))) { 1002 pr_debug_ratelimited( 1003 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", 1004 __func__, i, e.index, data); 1005 return -EINVAL; 1006 } 1007 } 1008 return 0; 1009 } 1010 1011 static bool nested_msr_store_list_has_msr(struct kvm_vcpu *vcpu, u32 msr_index) 1012 { 1013 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1014 u32 count = vmcs12->vm_exit_msr_store_count; 1015 u64 gpa = vmcs12->vm_exit_msr_store_addr; 1016 struct vmx_msr_entry e; 1017 u32 i; 1018 1019 for (i = 0; i < count; i++) { 1020 if (!read_and_check_msr_entry(vcpu, gpa, i, &e)) 1021 return false; 1022 1023 if (e.index == msr_index) 1024 return true; 1025 } 1026 return false; 1027 } 1028 1029 static void prepare_vmx_msr_autostore_list(struct kvm_vcpu *vcpu, 1030 u32 msr_index) 1031 { 1032 struct vcpu_vmx *vmx = to_vmx(vcpu); 1033 struct vmx_msrs *autostore = &vmx->msr_autostore.guest; 1034 bool in_vmcs12_store_list; 1035 int msr_autostore_slot; 1036 bool in_autostore_list; 1037 int last; 1038 1039 msr_autostore_slot = vmx_find_loadstore_msr_slot(autostore, msr_index); 1040 in_autostore_list = msr_autostore_slot >= 0; 1041 in_vmcs12_store_list = nested_msr_store_list_has_msr(vcpu, msr_index); 1042 1043 if (in_vmcs12_store_list && !in_autostore_list) { 1044 if (autostore->nr == MAX_NR_LOADSTORE_MSRS) { 1045 /* 1046 * Emulated VMEntry does not fail here. Instead a less 1047 * accurate value will be returned by 1048 * nested_vmx_get_vmexit_msr_value() using kvm_get_msr() 1049 * instead of reading the value from the vmcs02 VMExit 1050 * MSR-store area. 1051 */ 1052 pr_warn_ratelimited( 1053 "Not enough msr entries in msr_autostore. Can't add msr %x\n", 1054 msr_index); 1055 return; 1056 } 1057 last = autostore->nr++; 1058 autostore->val[last].index = msr_index; 1059 } else if (!in_vmcs12_store_list && in_autostore_list) { 1060 last = --autostore->nr; 1061 autostore->val[msr_autostore_slot] = autostore->val[last]; 1062 } 1063 } 1064 1065 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) 1066 { 1067 unsigned long invalid_mask; 1068 1069 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); 1070 return (val & invalid_mask) == 0; 1071 } 1072 1073 /* 1074 * Returns true if the MMU needs to be sync'd on nested VM-Enter/VM-Exit. 1075 * tl;dr: the MMU needs a sync if L0 is using shadow paging and L1 didn't 1076 * enable VPID for L2 (implying it expects a TLB flush on VMX transitions). 1077 * Here's why. 1078 * 1079 * If EPT is enabled by L0 a sync is never needed: 1080 * - if it is disabled by L1, then L0 is not shadowing L1 or L2 PTEs, there 1081 * cannot be unsync'd SPTEs for either L1 or L2. 1082 * 1083 * - if it is also enabled by L1, then L0 doesn't need to sync on VM-Enter 1084 * VM-Enter as VM-Enter isn't required to invalidate guest-physical mappings 1085 * (irrespective of VPID), i.e. L1 can't rely on the (virtual) CPU to flush 1086 * stale guest-physical mappings for L2 from the TLB. And as above, L0 isn't 1087 * shadowing L1 PTEs so there are no unsync'd SPTEs to sync on VM-Exit. 1088 * 1089 * If EPT is disabled by L0: 1090 * - if VPID is enabled by L1 (for L2), the situation is similar to when L1 1091 * enables EPT: L0 doesn't need to sync as VM-Enter and VM-Exit aren't 1092 * required to invalidate linear mappings (EPT is disabled so there are 1093 * no combined or guest-physical mappings), i.e. L1 can't rely on the 1094 * (virtual) CPU to flush stale linear mappings for either L2 or itself (L1). 1095 * 1096 * - however if VPID is disabled by L1, then a sync is needed as L1 expects all 1097 * linear mappings (EPT is disabled so there are no combined or guest-physical 1098 * mappings) to be invalidated on both VM-Enter and VM-Exit. 1099 * 1100 * Note, this logic is subtly different than nested_has_guest_tlb_tag(), which 1101 * additionally checks that L2 has been assigned a VPID (when EPT is disabled). 1102 * Whether or not L2 has been assigned a VPID by L0 is irrelevant with respect 1103 * to L1's expectations, e.g. L0 needs to invalidate hardware TLB entries if L2 1104 * doesn't have a unique VPID to prevent reusing L1's entries (assuming L1 has 1105 * been assigned a VPID), but L0 doesn't need to do a MMU sync because L1 1106 * doesn't expect stale (virtual) TLB entries to be flushed, i.e. L1 doesn't 1107 * know that L0 will flush the TLB and so L1 will do INVVPID as needed to flush 1108 * stale TLB entries, at which point L0 will sync L2's MMU. 1109 */ 1110 static bool nested_vmx_transition_mmu_sync(struct kvm_vcpu *vcpu) 1111 { 1112 return !enable_ept && !nested_cpu_has_vpid(get_vmcs12(vcpu)); 1113 } 1114 1115 /* 1116 * Load guest's/host's cr3 at nested entry/exit. @nested_ept is true if we are 1117 * emulating VM-Entry into a guest with EPT enabled. On failure, the expected 1118 * Exit Qualification (for a VM-Entry consistency check VM-Exit) is assigned to 1119 * @entry_failure_code. 1120 */ 1121 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, 1122 enum vm_entry_failure_code *entry_failure_code) 1123 { 1124 if (CC(!nested_cr3_valid(vcpu, cr3))) { 1125 *entry_failure_code = ENTRY_FAIL_DEFAULT; 1126 return -EINVAL; 1127 } 1128 1129 /* 1130 * If PAE paging and EPT are both on, CR3 is not used by the CPU and 1131 * must not be dereferenced. 1132 */ 1133 if (!nested_ept && is_pae_paging(vcpu) && 1134 (cr3 != kvm_read_cr3(vcpu) || pdptrs_changed(vcpu))) { 1135 if (CC(!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))) { 1136 *entry_failure_code = ENTRY_FAIL_PDPTE; 1137 return -EINVAL; 1138 } 1139 } 1140 1141 /* 1142 * Unconditionally skip the TLB flush on fast CR3 switch, all TLB 1143 * flushes are handled by nested_vmx_transition_tlb_flush(). See 1144 * nested_vmx_transition_mmu_sync for details on skipping the MMU sync. 1145 */ 1146 if (!nested_ept) 1147 kvm_mmu_new_pgd(vcpu, cr3, true, 1148 !nested_vmx_transition_mmu_sync(vcpu)); 1149 1150 vcpu->arch.cr3 = cr3; 1151 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1152 1153 kvm_init_mmu(vcpu, false); 1154 1155 return 0; 1156 } 1157 1158 /* 1159 * Returns if KVM is able to config CPU to tag TLB entries 1160 * populated by L2 differently than TLB entries populated 1161 * by L1. 1162 * 1163 * If L0 uses EPT, L1 and L2 run with different EPTP because 1164 * guest_mode is part of kvm_mmu_page_role. Thus, TLB entries 1165 * are tagged with different EPTP. 1166 * 1167 * If L1 uses VPID and we allocated a vpid02, TLB entries are tagged 1168 * with different VPID (L1 entries are tagged with vmx->vpid 1169 * while L2 entries are tagged with vmx->nested.vpid02). 1170 */ 1171 static bool nested_has_guest_tlb_tag(struct kvm_vcpu *vcpu) 1172 { 1173 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1174 1175 return enable_ept || 1176 (nested_cpu_has_vpid(vmcs12) && to_vmx(vcpu)->nested.vpid02); 1177 } 1178 1179 static void nested_vmx_transition_tlb_flush(struct kvm_vcpu *vcpu, 1180 struct vmcs12 *vmcs12, 1181 bool is_vmenter) 1182 { 1183 struct vcpu_vmx *vmx = to_vmx(vcpu); 1184 1185 /* 1186 * If VPID is disabled, linear and combined mappings are flushed on 1187 * VM-Enter/VM-Exit, and guest-physical mappings are valid only for 1188 * their associated EPTP. 1189 */ 1190 if (!enable_vpid) 1191 return; 1192 1193 /* 1194 * If vmcs12 doesn't use VPID, L1 expects linear and combined mappings 1195 * for *all* contexts to be flushed on VM-Enter/VM-Exit. 1196 * 1197 * If VPID is enabled and used by vmc12, but L2 does not have a unique 1198 * TLB tag (ASID), i.e. EPT is disabled and KVM was unable to allocate 1199 * a VPID for L2, flush the current context as the effective ASID is 1200 * common to both L1 and L2. 1201 * 1202 * Defer the flush so that it runs after vmcs02.EPTP has been set by 1203 * KVM_REQ_LOAD_MMU_PGD (if nested EPT is enabled) and to avoid 1204 * redundant flushes further down the nested pipeline. 1205 * 1206 * If a TLB flush isn't required due to any of the above, and vpid12 is 1207 * changing then the new "virtual" VPID (vpid12) will reuse the same 1208 * "real" VPID (vpid02), and so needs to be sync'd. There is no direct 1209 * mapping between vpid02 and vpid12, vpid02 is per-vCPU and reused for 1210 * all nested vCPUs. 1211 */ 1212 if (!nested_cpu_has_vpid(vmcs12)) { 1213 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1214 } else if (!nested_has_guest_tlb_tag(vcpu)) { 1215 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1216 } else if (is_vmenter && 1217 vmcs12->virtual_processor_id != vmx->nested.last_vpid) { 1218 vmx->nested.last_vpid = vmcs12->virtual_processor_id; 1219 vpid_sync_context(nested_get_vpid02(vcpu)); 1220 } 1221 } 1222 1223 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) 1224 { 1225 superset &= mask; 1226 subset &= mask; 1227 1228 return (superset | subset) == superset; 1229 } 1230 1231 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) 1232 { 1233 const u64 feature_and_reserved = 1234 /* feature (except bit 48; see below) */ 1235 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | 1236 /* reserved */ 1237 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); 1238 u64 vmx_basic = vmx->nested.msrs.basic; 1239 1240 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) 1241 return -EINVAL; 1242 1243 /* 1244 * KVM does not emulate a version of VMX that constrains physical 1245 * addresses of VMX structures (e.g. VMCS) to 32-bits. 1246 */ 1247 if (data & BIT_ULL(48)) 1248 return -EINVAL; 1249 1250 if (vmx_basic_vmcs_revision_id(vmx_basic) != 1251 vmx_basic_vmcs_revision_id(data)) 1252 return -EINVAL; 1253 1254 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) 1255 return -EINVAL; 1256 1257 vmx->nested.msrs.basic = data; 1258 return 0; 1259 } 1260 1261 static int 1262 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) 1263 { 1264 u64 supported; 1265 u32 *lowp, *highp; 1266 1267 switch (msr_index) { 1268 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1269 lowp = &vmx->nested.msrs.pinbased_ctls_low; 1270 highp = &vmx->nested.msrs.pinbased_ctls_high; 1271 break; 1272 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1273 lowp = &vmx->nested.msrs.procbased_ctls_low; 1274 highp = &vmx->nested.msrs.procbased_ctls_high; 1275 break; 1276 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1277 lowp = &vmx->nested.msrs.exit_ctls_low; 1278 highp = &vmx->nested.msrs.exit_ctls_high; 1279 break; 1280 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1281 lowp = &vmx->nested.msrs.entry_ctls_low; 1282 highp = &vmx->nested.msrs.entry_ctls_high; 1283 break; 1284 case MSR_IA32_VMX_PROCBASED_CTLS2: 1285 lowp = &vmx->nested.msrs.secondary_ctls_low; 1286 highp = &vmx->nested.msrs.secondary_ctls_high; 1287 break; 1288 default: 1289 BUG(); 1290 } 1291 1292 supported = vmx_control_msr(*lowp, *highp); 1293 1294 /* Check must-be-1 bits are still 1. */ 1295 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) 1296 return -EINVAL; 1297 1298 /* Check must-be-0 bits are still 0. */ 1299 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) 1300 return -EINVAL; 1301 1302 *lowp = data; 1303 *highp = data >> 32; 1304 return 0; 1305 } 1306 1307 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) 1308 { 1309 const u64 feature_and_reserved_bits = 1310 /* feature */ 1311 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | 1312 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | 1313 /* reserved */ 1314 GENMASK_ULL(13, 9) | BIT_ULL(31); 1315 u64 vmx_misc; 1316 1317 vmx_misc = vmx_control_msr(vmx->nested.msrs.misc_low, 1318 vmx->nested.msrs.misc_high); 1319 1320 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) 1321 return -EINVAL; 1322 1323 if ((vmx->nested.msrs.pinbased_ctls_high & 1324 PIN_BASED_VMX_PREEMPTION_TIMER) && 1325 vmx_misc_preemption_timer_rate(data) != 1326 vmx_misc_preemption_timer_rate(vmx_misc)) 1327 return -EINVAL; 1328 1329 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) 1330 return -EINVAL; 1331 1332 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) 1333 return -EINVAL; 1334 1335 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) 1336 return -EINVAL; 1337 1338 vmx->nested.msrs.misc_low = data; 1339 vmx->nested.msrs.misc_high = data >> 32; 1340 1341 return 0; 1342 } 1343 1344 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) 1345 { 1346 u64 vmx_ept_vpid_cap; 1347 1348 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.msrs.ept_caps, 1349 vmx->nested.msrs.vpid_caps); 1350 1351 /* Every bit is either reserved or a feature bit. */ 1352 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) 1353 return -EINVAL; 1354 1355 vmx->nested.msrs.ept_caps = data; 1356 vmx->nested.msrs.vpid_caps = data >> 32; 1357 return 0; 1358 } 1359 1360 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) 1361 { 1362 u64 *msr; 1363 1364 switch (msr_index) { 1365 case MSR_IA32_VMX_CR0_FIXED0: 1366 msr = &vmx->nested.msrs.cr0_fixed0; 1367 break; 1368 case MSR_IA32_VMX_CR4_FIXED0: 1369 msr = &vmx->nested.msrs.cr4_fixed0; 1370 break; 1371 default: 1372 BUG(); 1373 } 1374 1375 /* 1376 * 1 bits (which indicates bits which "must-be-1" during VMX operation) 1377 * must be 1 in the restored value. 1378 */ 1379 if (!is_bitwise_subset(data, *msr, -1ULL)) 1380 return -EINVAL; 1381 1382 *msr = data; 1383 return 0; 1384 } 1385 1386 /* 1387 * Called when userspace is restoring VMX MSRs. 1388 * 1389 * Returns 0 on success, non-0 otherwise. 1390 */ 1391 int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) 1392 { 1393 struct vcpu_vmx *vmx = to_vmx(vcpu); 1394 1395 /* 1396 * Don't allow changes to the VMX capability MSRs while the vCPU 1397 * is in VMX operation. 1398 */ 1399 if (vmx->nested.vmxon) 1400 return -EBUSY; 1401 1402 switch (msr_index) { 1403 case MSR_IA32_VMX_BASIC: 1404 return vmx_restore_vmx_basic(vmx, data); 1405 case MSR_IA32_VMX_PINBASED_CTLS: 1406 case MSR_IA32_VMX_PROCBASED_CTLS: 1407 case MSR_IA32_VMX_EXIT_CTLS: 1408 case MSR_IA32_VMX_ENTRY_CTLS: 1409 /* 1410 * The "non-true" VMX capability MSRs are generated from the 1411 * "true" MSRs, so we do not support restoring them directly. 1412 * 1413 * If userspace wants to emulate VMX_BASIC[55]=0, userspace 1414 * should restore the "true" MSRs with the must-be-1 bits 1415 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND 1416 * DEFAULT SETTINGS". 1417 */ 1418 return -EINVAL; 1419 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1420 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1421 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1422 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1423 case MSR_IA32_VMX_PROCBASED_CTLS2: 1424 return vmx_restore_control_msr(vmx, msr_index, data); 1425 case MSR_IA32_VMX_MISC: 1426 return vmx_restore_vmx_misc(vmx, data); 1427 case MSR_IA32_VMX_CR0_FIXED0: 1428 case MSR_IA32_VMX_CR4_FIXED0: 1429 return vmx_restore_fixed0_msr(vmx, msr_index, data); 1430 case MSR_IA32_VMX_CR0_FIXED1: 1431 case MSR_IA32_VMX_CR4_FIXED1: 1432 /* 1433 * These MSRs are generated based on the vCPU's CPUID, so we 1434 * do not support restoring them directly. 1435 */ 1436 return -EINVAL; 1437 case MSR_IA32_VMX_EPT_VPID_CAP: 1438 return vmx_restore_vmx_ept_vpid_cap(vmx, data); 1439 case MSR_IA32_VMX_VMCS_ENUM: 1440 vmx->nested.msrs.vmcs_enum = data; 1441 return 0; 1442 case MSR_IA32_VMX_VMFUNC: 1443 if (data & ~vmx->nested.msrs.vmfunc_controls) 1444 return -EINVAL; 1445 vmx->nested.msrs.vmfunc_controls = data; 1446 return 0; 1447 default: 1448 /* 1449 * The rest of the VMX capability MSRs do not support restore. 1450 */ 1451 return -EINVAL; 1452 } 1453 } 1454 1455 /* Returns 0 on success, non-0 otherwise. */ 1456 int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata) 1457 { 1458 switch (msr_index) { 1459 case MSR_IA32_VMX_BASIC: 1460 *pdata = msrs->basic; 1461 break; 1462 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: 1463 case MSR_IA32_VMX_PINBASED_CTLS: 1464 *pdata = vmx_control_msr( 1465 msrs->pinbased_ctls_low, 1466 msrs->pinbased_ctls_high); 1467 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) 1468 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 1469 break; 1470 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: 1471 case MSR_IA32_VMX_PROCBASED_CTLS: 1472 *pdata = vmx_control_msr( 1473 msrs->procbased_ctls_low, 1474 msrs->procbased_ctls_high); 1475 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) 1476 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 1477 break; 1478 case MSR_IA32_VMX_TRUE_EXIT_CTLS: 1479 case MSR_IA32_VMX_EXIT_CTLS: 1480 *pdata = vmx_control_msr( 1481 msrs->exit_ctls_low, 1482 msrs->exit_ctls_high); 1483 if (msr_index == MSR_IA32_VMX_EXIT_CTLS) 1484 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; 1485 break; 1486 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: 1487 case MSR_IA32_VMX_ENTRY_CTLS: 1488 *pdata = vmx_control_msr( 1489 msrs->entry_ctls_low, 1490 msrs->entry_ctls_high); 1491 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) 1492 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; 1493 break; 1494 case MSR_IA32_VMX_MISC: 1495 *pdata = vmx_control_msr( 1496 msrs->misc_low, 1497 msrs->misc_high); 1498 break; 1499 case MSR_IA32_VMX_CR0_FIXED0: 1500 *pdata = msrs->cr0_fixed0; 1501 break; 1502 case MSR_IA32_VMX_CR0_FIXED1: 1503 *pdata = msrs->cr0_fixed1; 1504 break; 1505 case MSR_IA32_VMX_CR4_FIXED0: 1506 *pdata = msrs->cr4_fixed0; 1507 break; 1508 case MSR_IA32_VMX_CR4_FIXED1: 1509 *pdata = msrs->cr4_fixed1; 1510 break; 1511 case MSR_IA32_VMX_VMCS_ENUM: 1512 *pdata = msrs->vmcs_enum; 1513 break; 1514 case MSR_IA32_VMX_PROCBASED_CTLS2: 1515 *pdata = vmx_control_msr( 1516 msrs->secondary_ctls_low, 1517 msrs->secondary_ctls_high); 1518 break; 1519 case MSR_IA32_VMX_EPT_VPID_CAP: 1520 *pdata = msrs->ept_caps | 1521 ((u64)msrs->vpid_caps << 32); 1522 break; 1523 case MSR_IA32_VMX_VMFUNC: 1524 *pdata = msrs->vmfunc_controls; 1525 break; 1526 default: 1527 return 1; 1528 } 1529 1530 return 0; 1531 } 1532 1533 /* 1534 * Copy the writable VMCS shadow fields back to the VMCS12, in case they have 1535 * been modified by the L1 guest. Note, "writable" in this context means 1536 * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of 1537 * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only" 1538 * VM-exit information fields (which are actually writable if the vCPU is 1539 * configured to support "VMWRITE to any supported field in the VMCS"). 1540 */ 1541 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) 1542 { 1543 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; 1544 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu); 1545 struct shadow_vmcs_field field; 1546 unsigned long val; 1547 int i; 1548 1549 if (WARN_ON(!shadow_vmcs)) 1550 return; 1551 1552 preempt_disable(); 1553 1554 vmcs_load(shadow_vmcs); 1555 1556 for (i = 0; i < max_shadow_read_write_fields; i++) { 1557 field = shadow_read_write_fields[i]; 1558 val = __vmcs_readl(field.encoding); 1559 vmcs12_write_any(vmcs12, field.encoding, field.offset, val); 1560 } 1561 1562 vmcs_clear(shadow_vmcs); 1563 vmcs_load(vmx->loaded_vmcs->vmcs); 1564 1565 preempt_enable(); 1566 } 1567 1568 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) 1569 { 1570 const struct shadow_vmcs_field *fields[] = { 1571 shadow_read_write_fields, 1572 shadow_read_only_fields 1573 }; 1574 const int max_fields[] = { 1575 max_shadow_read_write_fields, 1576 max_shadow_read_only_fields 1577 }; 1578 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; 1579 struct vmcs12 *vmcs12 = get_vmcs12(&vmx->vcpu); 1580 struct shadow_vmcs_field field; 1581 unsigned long val; 1582 int i, q; 1583 1584 if (WARN_ON(!shadow_vmcs)) 1585 return; 1586 1587 vmcs_load(shadow_vmcs); 1588 1589 for (q = 0; q < ARRAY_SIZE(fields); q++) { 1590 for (i = 0; i < max_fields[q]; i++) { 1591 field = fields[q][i]; 1592 val = vmcs12_read_any(vmcs12, field.encoding, 1593 field.offset); 1594 __vmcs_writel(field.encoding, val); 1595 } 1596 } 1597 1598 vmcs_clear(shadow_vmcs); 1599 vmcs_load(vmx->loaded_vmcs->vmcs); 1600 } 1601 1602 static int copy_enlightened_to_vmcs12(struct vcpu_vmx *vmx) 1603 { 1604 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12; 1605 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs; 1606 1607 /* HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE */ 1608 vmcs12->tpr_threshold = evmcs->tpr_threshold; 1609 vmcs12->guest_rip = evmcs->guest_rip; 1610 1611 if (unlikely(!(evmcs->hv_clean_fields & 1612 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC))) { 1613 vmcs12->guest_rsp = evmcs->guest_rsp; 1614 vmcs12->guest_rflags = evmcs->guest_rflags; 1615 vmcs12->guest_interruptibility_info = 1616 evmcs->guest_interruptibility_info; 1617 } 1618 1619 if (unlikely(!(evmcs->hv_clean_fields & 1620 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC))) { 1621 vmcs12->cpu_based_vm_exec_control = 1622 evmcs->cpu_based_vm_exec_control; 1623 } 1624 1625 if (unlikely(!(evmcs->hv_clean_fields & 1626 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN))) { 1627 vmcs12->exception_bitmap = evmcs->exception_bitmap; 1628 } 1629 1630 if (unlikely(!(evmcs->hv_clean_fields & 1631 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY))) { 1632 vmcs12->vm_entry_controls = evmcs->vm_entry_controls; 1633 } 1634 1635 if (unlikely(!(evmcs->hv_clean_fields & 1636 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT))) { 1637 vmcs12->vm_entry_intr_info_field = 1638 evmcs->vm_entry_intr_info_field; 1639 vmcs12->vm_entry_exception_error_code = 1640 evmcs->vm_entry_exception_error_code; 1641 vmcs12->vm_entry_instruction_len = 1642 evmcs->vm_entry_instruction_len; 1643 } 1644 1645 if (unlikely(!(evmcs->hv_clean_fields & 1646 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1))) { 1647 vmcs12->host_ia32_pat = evmcs->host_ia32_pat; 1648 vmcs12->host_ia32_efer = evmcs->host_ia32_efer; 1649 vmcs12->host_cr0 = evmcs->host_cr0; 1650 vmcs12->host_cr3 = evmcs->host_cr3; 1651 vmcs12->host_cr4 = evmcs->host_cr4; 1652 vmcs12->host_ia32_sysenter_esp = evmcs->host_ia32_sysenter_esp; 1653 vmcs12->host_ia32_sysenter_eip = evmcs->host_ia32_sysenter_eip; 1654 vmcs12->host_rip = evmcs->host_rip; 1655 vmcs12->host_ia32_sysenter_cs = evmcs->host_ia32_sysenter_cs; 1656 vmcs12->host_es_selector = evmcs->host_es_selector; 1657 vmcs12->host_cs_selector = evmcs->host_cs_selector; 1658 vmcs12->host_ss_selector = evmcs->host_ss_selector; 1659 vmcs12->host_ds_selector = evmcs->host_ds_selector; 1660 vmcs12->host_fs_selector = evmcs->host_fs_selector; 1661 vmcs12->host_gs_selector = evmcs->host_gs_selector; 1662 vmcs12->host_tr_selector = evmcs->host_tr_selector; 1663 } 1664 1665 if (unlikely(!(evmcs->hv_clean_fields & 1666 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1))) { 1667 vmcs12->pin_based_vm_exec_control = 1668 evmcs->pin_based_vm_exec_control; 1669 vmcs12->vm_exit_controls = evmcs->vm_exit_controls; 1670 vmcs12->secondary_vm_exec_control = 1671 evmcs->secondary_vm_exec_control; 1672 } 1673 1674 if (unlikely(!(evmcs->hv_clean_fields & 1675 HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP))) { 1676 vmcs12->io_bitmap_a = evmcs->io_bitmap_a; 1677 vmcs12->io_bitmap_b = evmcs->io_bitmap_b; 1678 } 1679 1680 if (unlikely(!(evmcs->hv_clean_fields & 1681 HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP))) { 1682 vmcs12->msr_bitmap = evmcs->msr_bitmap; 1683 } 1684 1685 if (unlikely(!(evmcs->hv_clean_fields & 1686 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2))) { 1687 vmcs12->guest_es_base = evmcs->guest_es_base; 1688 vmcs12->guest_cs_base = evmcs->guest_cs_base; 1689 vmcs12->guest_ss_base = evmcs->guest_ss_base; 1690 vmcs12->guest_ds_base = evmcs->guest_ds_base; 1691 vmcs12->guest_fs_base = evmcs->guest_fs_base; 1692 vmcs12->guest_gs_base = evmcs->guest_gs_base; 1693 vmcs12->guest_ldtr_base = evmcs->guest_ldtr_base; 1694 vmcs12->guest_tr_base = evmcs->guest_tr_base; 1695 vmcs12->guest_gdtr_base = evmcs->guest_gdtr_base; 1696 vmcs12->guest_idtr_base = evmcs->guest_idtr_base; 1697 vmcs12->guest_es_limit = evmcs->guest_es_limit; 1698 vmcs12->guest_cs_limit = evmcs->guest_cs_limit; 1699 vmcs12->guest_ss_limit = evmcs->guest_ss_limit; 1700 vmcs12->guest_ds_limit = evmcs->guest_ds_limit; 1701 vmcs12->guest_fs_limit = evmcs->guest_fs_limit; 1702 vmcs12->guest_gs_limit = evmcs->guest_gs_limit; 1703 vmcs12->guest_ldtr_limit = evmcs->guest_ldtr_limit; 1704 vmcs12->guest_tr_limit = evmcs->guest_tr_limit; 1705 vmcs12->guest_gdtr_limit = evmcs->guest_gdtr_limit; 1706 vmcs12->guest_idtr_limit = evmcs->guest_idtr_limit; 1707 vmcs12->guest_es_ar_bytes = evmcs->guest_es_ar_bytes; 1708 vmcs12->guest_cs_ar_bytes = evmcs->guest_cs_ar_bytes; 1709 vmcs12->guest_ss_ar_bytes = evmcs->guest_ss_ar_bytes; 1710 vmcs12->guest_ds_ar_bytes = evmcs->guest_ds_ar_bytes; 1711 vmcs12->guest_fs_ar_bytes = evmcs->guest_fs_ar_bytes; 1712 vmcs12->guest_gs_ar_bytes = evmcs->guest_gs_ar_bytes; 1713 vmcs12->guest_ldtr_ar_bytes = evmcs->guest_ldtr_ar_bytes; 1714 vmcs12->guest_tr_ar_bytes = evmcs->guest_tr_ar_bytes; 1715 vmcs12->guest_es_selector = evmcs->guest_es_selector; 1716 vmcs12->guest_cs_selector = evmcs->guest_cs_selector; 1717 vmcs12->guest_ss_selector = evmcs->guest_ss_selector; 1718 vmcs12->guest_ds_selector = evmcs->guest_ds_selector; 1719 vmcs12->guest_fs_selector = evmcs->guest_fs_selector; 1720 vmcs12->guest_gs_selector = evmcs->guest_gs_selector; 1721 vmcs12->guest_ldtr_selector = evmcs->guest_ldtr_selector; 1722 vmcs12->guest_tr_selector = evmcs->guest_tr_selector; 1723 } 1724 1725 if (unlikely(!(evmcs->hv_clean_fields & 1726 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2))) { 1727 vmcs12->tsc_offset = evmcs->tsc_offset; 1728 vmcs12->virtual_apic_page_addr = evmcs->virtual_apic_page_addr; 1729 vmcs12->xss_exit_bitmap = evmcs->xss_exit_bitmap; 1730 } 1731 1732 if (unlikely(!(evmcs->hv_clean_fields & 1733 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR))) { 1734 vmcs12->cr0_guest_host_mask = evmcs->cr0_guest_host_mask; 1735 vmcs12->cr4_guest_host_mask = evmcs->cr4_guest_host_mask; 1736 vmcs12->cr0_read_shadow = evmcs->cr0_read_shadow; 1737 vmcs12->cr4_read_shadow = evmcs->cr4_read_shadow; 1738 vmcs12->guest_cr0 = evmcs->guest_cr0; 1739 vmcs12->guest_cr3 = evmcs->guest_cr3; 1740 vmcs12->guest_cr4 = evmcs->guest_cr4; 1741 vmcs12->guest_dr7 = evmcs->guest_dr7; 1742 } 1743 1744 if (unlikely(!(evmcs->hv_clean_fields & 1745 HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER))) { 1746 vmcs12->host_fs_base = evmcs->host_fs_base; 1747 vmcs12->host_gs_base = evmcs->host_gs_base; 1748 vmcs12->host_tr_base = evmcs->host_tr_base; 1749 vmcs12->host_gdtr_base = evmcs->host_gdtr_base; 1750 vmcs12->host_idtr_base = evmcs->host_idtr_base; 1751 vmcs12->host_rsp = evmcs->host_rsp; 1752 } 1753 1754 if (unlikely(!(evmcs->hv_clean_fields & 1755 HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT))) { 1756 vmcs12->ept_pointer = evmcs->ept_pointer; 1757 vmcs12->virtual_processor_id = evmcs->virtual_processor_id; 1758 } 1759 1760 if (unlikely(!(evmcs->hv_clean_fields & 1761 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1))) { 1762 vmcs12->vmcs_link_pointer = evmcs->vmcs_link_pointer; 1763 vmcs12->guest_ia32_debugctl = evmcs->guest_ia32_debugctl; 1764 vmcs12->guest_ia32_pat = evmcs->guest_ia32_pat; 1765 vmcs12->guest_ia32_efer = evmcs->guest_ia32_efer; 1766 vmcs12->guest_pdptr0 = evmcs->guest_pdptr0; 1767 vmcs12->guest_pdptr1 = evmcs->guest_pdptr1; 1768 vmcs12->guest_pdptr2 = evmcs->guest_pdptr2; 1769 vmcs12->guest_pdptr3 = evmcs->guest_pdptr3; 1770 vmcs12->guest_pending_dbg_exceptions = 1771 evmcs->guest_pending_dbg_exceptions; 1772 vmcs12->guest_sysenter_esp = evmcs->guest_sysenter_esp; 1773 vmcs12->guest_sysenter_eip = evmcs->guest_sysenter_eip; 1774 vmcs12->guest_bndcfgs = evmcs->guest_bndcfgs; 1775 vmcs12->guest_activity_state = evmcs->guest_activity_state; 1776 vmcs12->guest_sysenter_cs = evmcs->guest_sysenter_cs; 1777 } 1778 1779 /* 1780 * Not used? 1781 * vmcs12->vm_exit_msr_store_addr = evmcs->vm_exit_msr_store_addr; 1782 * vmcs12->vm_exit_msr_load_addr = evmcs->vm_exit_msr_load_addr; 1783 * vmcs12->vm_entry_msr_load_addr = evmcs->vm_entry_msr_load_addr; 1784 * vmcs12->page_fault_error_code_mask = 1785 * evmcs->page_fault_error_code_mask; 1786 * vmcs12->page_fault_error_code_match = 1787 * evmcs->page_fault_error_code_match; 1788 * vmcs12->cr3_target_count = evmcs->cr3_target_count; 1789 * vmcs12->vm_exit_msr_store_count = evmcs->vm_exit_msr_store_count; 1790 * vmcs12->vm_exit_msr_load_count = evmcs->vm_exit_msr_load_count; 1791 * vmcs12->vm_entry_msr_load_count = evmcs->vm_entry_msr_load_count; 1792 */ 1793 1794 /* 1795 * Read only fields: 1796 * vmcs12->guest_physical_address = evmcs->guest_physical_address; 1797 * vmcs12->vm_instruction_error = evmcs->vm_instruction_error; 1798 * vmcs12->vm_exit_reason = evmcs->vm_exit_reason; 1799 * vmcs12->vm_exit_intr_info = evmcs->vm_exit_intr_info; 1800 * vmcs12->vm_exit_intr_error_code = evmcs->vm_exit_intr_error_code; 1801 * vmcs12->idt_vectoring_info_field = evmcs->idt_vectoring_info_field; 1802 * vmcs12->idt_vectoring_error_code = evmcs->idt_vectoring_error_code; 1803 * vmcs12->vm_exit_instruction_len = evmcs->vm_exit_instruction_len; 1804 * vmcs12->vmx_instruction_info = evmcs->vmx_instruction_info; 1805 * vmcs12->exit_qualification = evmcs->exit_qualification; 1806 * vmcs12->guest_linear_address = evmcs->guest_linear_address; 1807 * 1808 * Not present in struct vmcs12: 1809 * vmcs12->exit_io_instruction_ecx = evmcs->exit_io_instruction_ecx; 1810 * vmcs12->exit_io_instruction_esi = evmcs->exit_io_instruction_esi; 1811 * vmcs12->exit_io_instruction_edi = evmcs->exit_io_instruction_edi; 1812 * vmcs12->exit_io_instruction_eip = evmcs->exit_io_instruction_eip; 1813 */ 1814 1815 return 0; 1816 } 1817 1818 static int copy_vmcs12_to_enlightened(struct vcpu_vmx *vmx) 1819 { 1820 struct vmcs12 *vmcs12 = vmx->nested.cached_vmcs12; 1821 struct hv_enlightened_vmcs *evmcs = vmx->nested.hv_evmcs; 1822 1823 /* 1824 * Should not be changed by KVM: 1825 * 1826 * evmcs->host_es_selector = vmcs12->host_es_selector; 1827 * evmcs->host_cs_selector = vmcs12->host_cs_selector; 1828 * evmcs->host_ss_selector = vmcs12->host_ss_selector; 1829 * evmcs->host_ds_selector = vmcs12->host_ds_selector; 1830 * evmcs->host_fs_selector = vmcs12->host_fs_selector; 1831 * evmcs->host_gs_selector = vmcs12->host_gs_selector; 1832 * evmcs->host_tr_selector = vmcs12->host_tr_selector; 1833 * evmcs->host_ia32_pat = vmcs12->host_ia32_pat; 1834 * evmcs->host_ia32_efer = vmcs12->host_ia32_efer; 1835 * evmcs->host_cr0 = vmcs12->host_cr0; 1836 * evmcs->host_cr3 = vmcs12->host_cr3; 1837 * evmcs->host_cr4 = vmcs12->host_cr4; 1838 * evmcs->host_ia32_sysenter_esp = vmcs12->host_ia32_sysenter_esp; 1839 * evmcs->host_ia32_sysenter_eip = vmcs12->host_ia32_sysenter_eip; 1840 * evmcs->host_rip = vmcs12->host_rip; 1841 * evmcs->host_ia32_sysenter_cs = vmcs12->host_ia32_sysenter_cs; 1842 * evmcs->host_fs_base = vmcs12->host_fs_base; 1843 * evmcs->host_gs_base = vmcs12->host_gs_base; 1844 * evmcs->host_tr_base = vmcs12->host_tr_base; 1845 * evmcs->host_gdtr_base = vmcs12->host_gdtr_base; 1846 * evmcs->host_idtr_base = vmcs12->host_idtr_base; 1847 * evmcs->host_rsp = vmcs12->host_rsp; 1848 * sync_vmcs02_to_vmcs12() doesn't read these: 1849 * evmcs->io_bitmap_a = vmcs12->io_bitmap_a; 1850 * evmcs->io_bitmap_b = vmcs12->io_bitmap_b; 1851 * evmcs->msr_bitmap = vmcs12->msr_bitmap; 1852 * evmcs->ept_pointer = vmcs12->ept_pointer; 1853 * evmcs->xss_exit_bitmap = vmcs12->xss_exit_bitmap; 1854 * evmcs->vm_exit_msr_store_addr = vmcs12->vm_exit_msr_store_addr; 1855 * evmcs->vm_exit_msr_load_addr = vmcs12->vm_exit_msr_load_addr; 1856 * evmcs->vm_entry_msr_load_addr = vmcs12->vm_entry_msr_load_addr; 1857 * evmcs->tpr_threshold = vmcs12->tpr_threshold; 1858 * evmcs->virtual_processor_id = vmcs12->virtual_processor_id; 1859 * evmcs->exception_bitmap = vmcs12->exception_bitmap; 1860 * evmcs->vmcs_link_pointer = vmcs12->vmcs_link_pointer; 1861 * evmcs->pin_based_vm_exec_control = vmcs12->pin_based_vm_exec_control; 1862 * evmcs->vm_exit_controls = vmcs12->vm_exit_controls; 1863 * evmcs->secondary_vm_exec_control = vmcs12->secondary_vm_exec_control; 1864 * evmcs->page_fault_error_code_mask = 1865 * vmcs12->page_fault_error_code_mask; 1866 * evmcs->page_fault_error_code_match = 1867 * vmcs12->page_fault_error_code_match; 1868 * evmcs->cr3_target_count = vmcs12->cr3_target_count; 1869 * evmcs->virtual_apic_page_addr = vmcs12->virtual_apic_page_addr; 1870 * evmcs->tsc_offset = vmcs12->tsc_offset; 1871 * evmcs->guest_ia32_debugctl = vmcs12->guest_ia32_debugctl; 1872 * evmcs->cr0_guest_host_mask = vmcs12->cr0_guest_host_mask; 1873 * evmcs->cr4_guest_host_mask = vmcs12->cr4_guest_host_mask; 1874 * evmcs->cr0_read_shadow = vmcs12->cr0_read_shadow; 1875 * evmcs->cr4_read_shadow = vmcs12->cr4_read_shadow; 1876 * evmcs->vm_exit_msr_store_count = vmcs12->vm_exit_msr_store_count; 1877 * evmcs->vm_exit_msr_load_count = vmcs12->vm_exit_msr_load_count; 1878 * evmcs->vm_entry_msr_load_count = vmcs12->vm_entry_msr_load_count; 1879 * 1880 * Not present in struct vmcs12: 1881 * evmcs->exit_io_instruction_ecx = vmcs12->exit_io_instruction_ecx; 1882 * evmcs->exit_io_instruction_esi = vmcs12->exit_io_instruction_esi; 1883 * evmcs->exit_io_instruction_edi = vmcs12->exit_io_instruction_edi; 1884 * evmcs->exit_io_instruction_eip = vmcs12->exit_io_instruction_eip; 1885 */ 1886 1887 evmcs->guest_es_selector = vmcs12->guest_es_selector; 1888 evmcs->guest_cs_selector = vmcs12->guest_cs_selector; 1889 evmcs->guest_ss_selector = vmcs12->guest_ss_selector; 1890 evmcs->guest_ds_selector = vmcs12->guest_ds_selector; 1891 evmcs->guest_fs_selector = vmcs12->guest_fs_selector; 1892 evmcs->guest_gs_selector = vmcs12->guest_gs_selector; 1893 evmcs->guest_ldtr_selector = vmcs12->guest_ldtr_selector; 1894 evmcs->guest_tr_selector = vmcs12->guest_tr_selector; 1895 1896 evmcs->guest_es_limit = vmcs12->guest_es_limit; 1897 evmcs->guest_cs_limit = vmcs12->guest_cs_limit; 1898 evmcs->guest_ss_limit = vmcs12->guest_ss_limit; 1899 evmcs->guest_ds_limit = vmcs12->guest_ds_limit; 1900 evmcs->guest_fs_limit = vmcs12->guest_fs_limit; 1901 evmcs->guest_gs_limit = vmcs12->guest_gs_limit; 1902 evmcs->guest_ldtr_limit = vmcs12->guest_ldtr_limit; 1903 evmcs->guest_tr_limit = vmcs12->guest_tr_limit; 1904 evmcs->guest_gdtr_limit = vmcs12->guest_gdtr_limit; 1905 evmcs->guest_idtr_limit = vmcs12->guest_idtr_limit; 1906 1907 evmcs->guest_es_ar_bytes = vmcs12->guest_es_ar_bytes; 1908 evmcs->guest_cs_ar_bytes = vmcs12->guest_cs_ar_bytes; 1909 evmcs->guest_ss_ar_bytes = vmcs12->guest_ss_ar_bytes; 1910 evmcs->guest_ds_ar_bytes = vmcs12->guest_ds_ar_bytes; 1911 evmcs->guest_fs_ar_bytes = vmcs12->guest_fs_ar_bytes; 1912 evmcs->guest_gs_ar_bytes = vmcs12->guest_gs_ar_bytes; 1913 evmcs->guest_ldtr_ar_bytes = vmcs12->guest_ldtr_ar_bytes; 1914 evmcs->guest_tr_ar_bytes = vmcs12->guest_tr_ar_bytes; 1915 1916 evmcs->guest_es_base = vmcs12->guest_es_base; 1917 evmcs->guest_cs_base = vmcs12->guest_cs_base; 1918 evmcs->guest_ss_base = vmcs12->guest_ss_base; 1919 evmcs->guest_ds_base = vmcs12->guest_ds_base; 1920 evmcs->guest_fs_base = vmcs12->guest_fs_base; 1921 evmcs->guest_gs_base = vmcs12->guest_gs_base; 1922 evmcs->guest_ldtr_base = vmcs12->guest_ldtr_base; 1923 evmcs->guest_tr_base = vmcs12->guest_tr_base; 1924 evmcs->guest_gdtr_base = vmcs12->guest_gdtr_base; 1925 evmcs->guest_idtr_base = vmcs12->guest_idtr_base; 1926 1927 evmcs->guest_ia32_pat = vmcs12->guest_ia32_pat; 1928 evmcs->guest_ia32_efer = vmcs12->guest_ia32_efer; 1929 1930 evmcs->guest_pdptr0 = vmcs12->guest_pdptr0; 1931 evmcs->guest_pdptr1 = vmcs12->guest_pdptr1; 1932 evmcs->guest_pdptr2 = vmcs12->guest_pdptr2; 1933 evmcs->guest_pdptr3 = vmcs12->guest_pdptr3; 1934 1935 evmcs->guest_pending_dbg_exceptions = 1936 vmcs12->guest_pending_dbg_exceptions; 1937 evmcs->guest_sysenter_esp = vmcs12->guest_sysenter_esp; 1938 evmcs->guest_sysenter_eip = vmcs12->guest_sysenter_eip; 1939 1940 evmcs->guest_activity_state = vmcs12->guest_activity_state; 1941 evmcs->guest_sysenter_cs = vmcs12->guest_sysenter_cs; 1942 1943 evmcs->guest_cr0 = vmcs12->guest_cr0; 1944 evmcs->guest_cr3 = vmcs12->guest_cr3; 1945 evmcs->guest_cr4 = vmcs12->guest_cr4; 1946 evmcs->guest_dr7 = vmcs12->guest_dr7; 1947 1948 evmcs->guest_physical_address = vmcs12->guest_physical_address; 1949 1950 evmcs->vm_instruction_error = vmcs12->vm_instruction_error; 1951 evmcs->vm_exit_reason = vmcs12->vm_exit_reason; 1952 evmcs->vm_exit_intr_info = vmcs12->vm_exit_intr_info; 1953 evmcs->vm_exit_intr_error_code = vmcs12->vm_exit_intr_error_code; 1954 evmcs->idt_vectoring_info_field = vmcs12->idt_vectoring_info_field; 1955 evmcs->idt_vectoring_error_code = vmcs12->idt_vectoring_error_code; 1956 evmcs->vm_exit_instruction_len = vmcs12->vm_exit_instruction_len; 1957 evmcs->vmx_instruction_info = vmcs12->vmx_instruction_info; 1958 1959 evmcs->exit_qualification = vmcs12->exit_qualification; 1960 1961 evmcs->guest_linear_address = vmcs12->guest_linear_address; 1962 evmcs->guest_rsp = vmcs12->guest_rsp; 1963 evmcs->guest_rflags = vmcs12->guest_rflags; 1964 1965 evmcs->guest_interruptibility_info = 1966 vmcs12->guest_interruptibility_info; 1967 evmcs->cpu_based_vm_exec_control = vmcs12->cpu_based_vm_exec_control; 1968 evmcs->vm_entry_controls = vmcs12->vm_entry_controls; 1969 evmcs->vm_entry_intr_info_field = vmcs12->vm_entry_intr_info_field; 1970 evmcs->vm_entry_exception_error_code = 1971 vmcs12->vm_entry_exception_error_code; 1972 evmcs->vm_entry_instruction_len = vmcs12->vm_entry_instruction_len; 1973 1974 evmcs->guest_rip = vmcs12->guest_rip; 1975 1976 evmcs->guest_bndcfgs = vmcs12->guest_bndcfgs; 1977 1978 return 0; 1979 } 1980 1981 /* 1982 * This is an equivalent of the nested hypervisor executing the vmptrld 1983 * instruction. 1984 */ 1985 static enum nested_evmptrld_status nested_vmx_handle_enlightened_vmptrld( 1986 struct kvm_vcpu *vcpu, bool from_launch) 1987 { 1988 struct vcpu_vmx *vmx = to_vmx(vcpu); 1989 bool evmcs_gpa_changed = false; 1990 u64 evmcs_gpa; 1991 1992 if (likely(!vmx->nested.enlightened_vmcs_enabled)) 1993 return EVMPTRLD_DISABLED; 1994 1995 if (!nested_enlightened_vmentry(vcpu, &evmcs_gpa)) 1996 return EVMPTRLD_DISABLED; 1997 1998 if (unlikely(!vmx->nested.hv_evmcs || 1999 evmcs_gpa != vmx->nested.hv_evmcs_vmptr)) { 2000 if (!vmx->nested.hv_evmcs) 2001 vmx->nested.current_vmptr = -1ull; 2002 2003 nested_release_evmcs(vcpu); 2004 2005 if (kvm_vcpu_map(vcpu, gpa_to_gfn(evmcs_gpa), 2006 &vmx->nested.hv_evmcs_map)) 2007 return EVMPTRLD_ERROR; 2008 2009 vmx->nested.hv_evmcs = vmx->nested.hv_evmcs_map.hva; 2010 2011 /* 2012 * Currently, KVM only supports eVMCS version 1 2013 * (== KVM_EVMCS_VERSION) and thus we expect guest to set this 2014 * value to first u32 field of eVMCS which should specify eVMCS 2015 * VersionNumber. 2016 * 2017 * Guest should be aware of supported eVMCS versions by host by 2018 * examining CPUID.0x4000000A.EAX[0:15]. Host userspace VMM is 2019 * expected to set this CPUID leaf according to the value 2020 * returned in vmcs_version from nested_enable_evmcs(). 2021 * 2022 * However, it turns out that Microsoft Hyper-V fails to comply 2023 * to their own invented interface: When Hyper-V use eVMCS, it 2024 * just sets first u32 field of eVMCS to revision_id specified 2025 * in MSR_IA32_VMX_BASIC. Instead of used eVMCS version number 2026 * which is one of the supported versions specified in 2027 * CPUID.0x4000000A.EAX[0:15]. 2028 * 2029 * To overcome Hyper-V bug, we accept here either a supported 2030 * eVMCS version or VMCS12 revision_id as valid values for first 2031 * u32 field of eVMCS. 2032 */ 2033 if ((vmx->nested.hv_evmcs->revision_id != KVM_EVMCS_VERSION) && 2034 (vmx->nested.hv_evmcs->revision_id != VMCS12_REVISION)) { 2035 nested_release_evmcs(vcpu); 2036 return EVMPTRLD_VMFAIL; 2037 } 2038 2039 vmx->nested.dirty_vmcs12 = true; 2040 vmx->nested.hv_evmcs_vmptr = evmcs_gpa; 2041 2042 evmcs_gpa_changed = true; 2043 /* 2044 * Unlike normal vmcs12, enlightened vmcs12 is not fully 2045 * reloaded from guest's memory (read only fields, fields not 2046 * present in struct hv_enlightened_vmcs, ...). Make sure there 2047 * are no leftovers. 2048 */ 2049 if (from_launch) { 2050 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 2051 memset(vmcs12, 0, sizeof(*vmcs12)); 2052 vmcs12->hdr.revision_id = VMCS12_REVISION; 2053 } 2054 2055 } 2056 2057 /* 2058 * Clean fields data can't be used on VMLAUNCH and when we switch 2059 * between different L2 guests as KVM keeps a single VMCS12 per L1. 2060 */ 2061 if (from_launch || evmcs_gpa_changed) 2062 vmx->nested.hv_evmcs->hv_clean_fields &= 2063 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 2064 2065 return EVMPTRLD_SUCCEEDED; 2066 } 2067 2068 void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu) 2069 { 2070 struct vcpu_vmx *vmx = to_vmx(vcpu); 2071 2072 if (vmx->nested.hv_evmcs) { 2073 copy_vmcs12_to_enlightened(vmx); 2074 /* All fields are clean */ 2075 vmx->nested.hv_evmcs->hv_clean_fields |= 2076 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 2077 } else { 2078 copy_vmcs12_to_shadow(vmx); 2079 } 2080 2081 vmx->nested.need_vmcs12_to_shadow_sync = false; 2082 } 2083 2084 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) 2085 { 2086 struct vcpu_vmx *vmx = 2087 container_of(timer, struct vcpu_vmx, nested.preemption_timer); 2088 2089 vmx->nested.preemption_timer_expired = true; 2090 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); 2091 kvm_vcpu_kick(&vmx->vcpu); 2092 2093 return HRTIMER_NORESTART; 2094 } 2095 2096 static u64 vmx_calc_preemption_timer_value(struct kvm_vcpu *vcpu) 2097 { 2098 struct vcpu_vmx *vmx = to_vmx(vcpu); 2099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 2100 2101 u64 l1_scaled_tsc = kvm_read_l1_tsc(vcpu, rdtsc()) >> 2102 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; 2103 2104 if (!vmx->nested.has_preemption_timer_deadline) { 2105 vmx->nested.preemption_timer_deadline = 2106 vmcs12->vmx_preemption_timer_value + l1_scaled_tsc; 2107 vmx->nested.has_preemption_timer_deadline = true; 2108 } 2109 return vmx->nested.preemption_timer_deadline - l1_scaled_tsc; 2110 } 2111 2112 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu, 2113 u64 preemption_timeout) 2114 { 2115 struct vcpu_vmx *vmx = to_vmx(vcpu); 2116 2117 /* 2118 * A timer value of zero is architecturally guaranteed to cause 2119 * a VMExit prior to executing any instructions in the guest. 2120 */ 2121 if (preemption_timeout == 0) { 2122 vmx_preemption_timer_fn(&vmx->nested.preemption_timer); 2123 return; 2124 } 2125 2126 if (vcpu->arch.virtual_tsc_khz == 0) 2127 return; 2128 2129 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; 2130 preemption_timeout *= 1000000; 2131 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); 2132 hrtimer_start(&vmx->nested.preemption_timer, 2133 ktime_add_ns(ktime_get(), preemption_timeout), 2134 HRTIMER_MODE_ABS_PINNED); 2135 } 2136 2137 static u64 nested_vmx_calc_efer(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) 2138 { 2139 if (vmx->nested.nested_run_pending && 2140 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) 2141 return vmcs12->guest_ia32_efer; 2142 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) 2143 return vmx->vcpu.arch.efer | (EFER_LMA | EFER_LME); 2144 else 2145 return vmx->vcpu.arch.efer & ~(EFER_LMA | EFER_LME); 2146 } 2147 2148 static void prepare_vmcs02_constant_state(struct vcpu_vmx *vmx) 2149 { 2150 /* 2151 * If vmcs02 hasn't been initialized, set the constant vmcs02 state 2152 * according to L0's settings (vmcs12 is irrelevant here). Host 2153 * fields that come from L0 and are not constant, e.g. HOST_CR3, 2154 * will be set as needed prior to VMLAUNCH/VMRESUME. 2155 */ 2156 if (vmx->nested.vmcs02_initialized) 2157 return; 2158 vmx->nested.vmcs02_initialized = true; 2159 2160 /* 2161 * We don't care what the EPTP value is we just need to guarantee 2162 * it's valid so we don't get a false positive when doing early 2163 * consistency checks. 2164 */ 2165 if (enable_ept && nested_early_check) 2166 vmcs_write64(EPT_POINTER, 2167 construct_eptp(&vmx->vcpu, 0, PT64_ROOT_4LEVEL)); 2168 2169 /* All VMFUNCs are currently emulated through L0 vmexits. */ 2170 if (cpu_has_vmx_vmfunc()) 2171 vmcs_write64(VM_FUNCTION_CONTROL, 0); 2172 2173 if (cpu_has_vmx_posted_intr()) 2174 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); 2175 2176 if (cpu_has_vmx_msr_bitmap()) 2177 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap)); 2178 2179 /* 2180 * The PML address never changes, so it is constant in vmcs02. 2181 * Conceptually we want to copy the PML index from vmcs01 here, 2182 * and then back to vmcs01 on nested vmexit. But since we flush 2183 * the log and reset GUEST_PML_INDEX on each vmexit, the PML 2184 * index is also effectively constant in vmcs02. 2185 */ 2186 if (enable_pml) { 2187 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 2188 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 2189 } 2190 2191 if (cpu_has_vmx_encls_vmexit()) 2192 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 2193 2194 /* 2195 * Set the MSR load/store lists to match L0's settings. Only the 2196 * addresses are constant (for vmcs02), the counts can change based 2197 * on L2's behavior, e.g. switching to/from long mode. 2198 */ 2199 vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autostore.guest.val)); 2200 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 2201 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 2202 2203 vmx_set_constant_host_state(vmx); 2204 } 2205 2206 static void prepare_vmcs02_early_rare(struct vcpu_vmx *vmx, 2207 struct vmcs12 *vmcs12) 2208 { 2209 prepare_vmcs02_constant_state(vmx); 2210 2211 vmcs_write64(VMCS_LINK_POINTER, -1ull); 2212 2213 if (enable_vpid) { 2214 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) 2215 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); 2216 else 2217 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 2218 } 2219 } 2220 2221 static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) 2222 { 2223 u32 exec_control, vmcs12_exec_ctrl; 2224 u64 guest_efer = nested_vmx_calc_efer(vmx, vmcs12); 2225 2226 if (vmx->nested.dirty_vmcs12 || vmx->nested.hv_evmcs) 2227 prepare_vmcs02_early_rare(vmx, vmcs12); 2228 2229 /* 2230 * PIN CONTROLS 2231 */ 2232 exec_control = vmx_pin_based_exec_ctrl(vmx); 2233 exec_control |= (vmcs12->pin_based_vm_exec_control & 2234 ~PIN_BASED_VMX_PREEMPTION_TIMER); 2235 2236 /* Posted interrupts setting is only taken from vmcs12. */ 2237 if (nested_cpu_has_posted_intr(vmcs12)) { 2238 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; 2239 vmx->nested.pi_pending = false; 2240 } else { 2241 exec_control &= ~PIN_BASED_POSTED_INTR; 2242 } 2243 pin_controls_set(vmx, exec_control); 2244 2245 /* 2246 * EXEC CONTROLS 2247 */ 2248 exec_control = vmx_exec_control(vmx); /* L0's desires */ 2249 exec_control &= ~CPU_BASED_INTR_WINDOW_EXITING; 2250 exec_control &= ~CPU_BASED_NMI_WINDOW_EXITING; 2251 exec_control &= ~CPU_BASED_TPR_SHADOW; 2252 exec_control |= vmcs12->cpu_based_vm_exec_control; 2253 2254 vmx->nested.l1_tpr_threshold = -1; 2255 if (exec_control & CPU_BASED_TPR_SHADOW) 2256 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); 2257 #ifdef CONFIG_X86_64 2258 else 2259 exec_control |= CPU_BASED_CR8_LOAD_EXITING | 2260 CPU_BASED_CR8_STORE_EXITING; 2261 #endif 2262 2263 /* 2264 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed 2265 * for I/O port accesses. 2266 */ 2267 exec_control |= CPU_BASED_UNCOND_IO_EXITING; 2268 exec_control &= ~CPU_BASED_USE_IO_BITMAPS; 2269 2270 /* 2271 * This bit will be computed in nested_get_vmcs12_pages, because 2272 * we do not have access to L1's MSR bitmap yet. For now, keep 2273 * the same bit as before, hoping to avoid multiple VMWRITEs that 2274 * only set/clear this bit. 2275 */ 2276 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; 2277 exec_control |= exec_controls_get(vmx) & CPU_BASED_USE_MSR_BITMAPS; 2278 2279 exec_controls_set(vmx, exec_control); 2280 2281 /* 2282 * SECONDARY EXEC CONTROLS 2283 */ 2284 if (cpu_has_secondary_exec_ctrls()) { 2285 exec_control = vmx->secondary_exec_control; 2286 2287 /* Take the following fields only from vmcs12 */ 2288 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2289 SECONDARY_EXEC_ENABLE_INVPCID | 2290 SECONDARY_EXEC_ENABLE_RDTSCP | 2291 SECONDARY_EXEC_XSAVES | 2292 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2293 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2294 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2295 SECONDARY_EXEC_ENABLE_VMFUNC); 2296 if (nested_cpu_has(vmcs12, 2297 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) { 2298 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control & 2299 ~SECONDARY_EXEC_ENABLE_PML; 2300 exec_control |= vmcs12_exec_ctrl; 2301 } 2302 2303 /* VMCS shadowing for L2 is emulated for now */ 2304 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 2305 2306 /* 2307 * Preset *DT exiting when emulating UMIP, so that vmx_set_cr4() 2308 * will not have to rewrite the controls just for this bit. 2309 */ 2310 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() && 2311 (vmcs12->guest_cr4 & X86_CR4_UMIP)) 2312 exec_control |= SECONDARY_EXEC_DESC; 2313 2314 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 2315 vmcs_write16(GUEST_INTR_STATUS, 2316 vmcs12->guest_intr_status); 2317 2318 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) 2319 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 2320 2321 secondary_exec_controls_set(vmx, exec_control); 2322 } 2323 2324 /* 2325 * ENTRY CONTROLS 2326 * 2327 * vmcs12's VM_{ENTRY,EXIT}_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE 2328 * are emulated by vmx_set_efer() in prepare_vmcs02(), but speculate 2329 * on the related bits (if supported by the CPU) in the hope that 2330 * we can avoid VMWrites during vmx_set_efer(). 2331 */ 2332 exec_control = (vmcs12->vm_entry_controls | vmx_vmentry_ctrl()) & 2333 ~VM_ENTRY_IA32E_MODE & ~VM_ENTRY_LOAD_IA32_EFER; 2334 if (cpu_has_load_ia32_efer()) { 2335 if (guest_efer & EFER_LMA) 2336 exec_control |= VM_ENTRY_IA32E_MODE; 2337 if (guest_efer != host_efer) 2338 exec_control |= VM_ENTRY_LOAD_IA32_EFER; 2339 } 2340 vm_entry_controls_set(vmx, exec_control); 2341 2342 /* 2343 * EXIT CONTROLS 2344 * 2345 * L2->L1 exit controls are emulated - the hardware exit is to L0 so 2346 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER 2347 * bits may be modified by vmx_set_efer() in prepare_vmcs02(). 2348 */ 2349 exec_control = vmx_vmexit_ctrl(); 2350 if (cpu_has_load_ia32_efer() && guest_efer != host_efer) 2351 exec_control |= VM_EXIT_LOAD_IA32_EFER; 2352 vm_exit_controls_set(vmx, exec_control); 2353 2354 /* 2355 * Interrupt/Exception Fields 2356 */ 2357 if (vmx->nested.nested_run_pending) { 2358 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 2359 vmcs12->vm_entry_intr_info_field); 2360 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 2361 vmcs12->vm_entry_exception_error_code); 2362 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 2363 vmcs12->vm_entry_instruction_len); 2364 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 2365 vmcs12->guest_interruptibility_info); 2366 vmx->loaded_vmcs->nmi_known_unmasked = 2367 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); 2368 } else { 2369 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 2370 } 2371 } 2372 2373 static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12) 2374 { 2375 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs; 2376 2377 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields & 2378 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2)) { 2379 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); 2380 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); 2381 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); 2382 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); 2383 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); 2384 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); 2385 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); 2386 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); 2387 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); 2388 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); 2389 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); 2390 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); 2391 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); 2392 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); 2393 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); 2394 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); 2395 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); 2396 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); 2397 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); 2398 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); 2399 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); 2400 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); 2401 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); 2402 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); 2403 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); 2404 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); 2405 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); 2406 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); 2407 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); 2408 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); 2409 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); 2410 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); 2411 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); 2412 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); 2413 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); 2414 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); 2415 2416 vmx->segment_cache.bitmask = 0; 2417 } 2418 2419 if (!hv_evmcs || !(hv_evmcs->hv_clean_fields & 2420 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1)) { 2421 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); 2422 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 2423 vmcs12->guest_pending_dbg_exceptions); 2424 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); 2425 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); 2426 2427 /* 2428 * L1 may access the L2's PDPTR, so save them to construct 2429 * vmcs12 2430 */ 2431 if (enable_ept) { 2432 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); 2433 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); 2434 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); 2435 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); 2436 } 2437 2438 if (kvm_mpx_supported() && vmx->nested.nested_run_pending && 2439 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)) 2440 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); 2441 } 2442 2443 if (nested_cpu_has_xsaves(vmcs12)) 2444 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); 2445 2446 /* 2447 * Whether page-faults are trapped is determined by a combination of 2448 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. If L0 2449 * doesn't care about page faults then we should set all of these to 2450 * L1's desires. However, if L0 does care about (some) page faults, it 2451 * is not easy (if at all possible?) to merge L0 and L1's desires, we 2452 * simply ask to exit on each and every L2 page fault. This is done by 2453 * setting MASK=MATCH=0 and (see below) EB.PF=1. 2454 * Note that below we don't need special code to set EB.PF beyond the 2455 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, 2456 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when 2457 * !enable_ept, EB.PF is 1, so the "or" will always be 1. 2458 */ 2459 if (vmx_need_pf_intercept(&vmx->vcpu)) { 2460 /* 2461 * TODO: if both L0 and L1 need the same MASK and MATCH, 2462 * go ahead and use it? 2463 */ 2464 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 2465 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 2466 } else { 2467 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, vmcs12->page_fault_error_code_mask); 2468 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, vmcs12->page_fault_error_code_match); 2469 } 2470 2471 if (cpu_has_vmx_apicv()) { 2472 vmcs_write64(EOI_EXIT_BITMAP0, vmcs12->eoi_exit_bitmap0); 2473 vmcs_write64(EOI_EXIT_BITMAP1, vmcs12->eoi_exit_bitmap1); 2474 vmcs_write64(EOI_EXIT_BITMAP2, vmcs12->eoi_exit_bitmap2); 2475 vmcs_write64(EOI_EXIT_BITMAP3, vmcs12->eoi_exit_bitmap3); 2476 } 2477 2478 /* 2479 * Make sure the msr_autostore list is up to date before we set the 2480 * count in the vmcs02. 2481 */ 2482 prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC); 2483 2484 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, vmx->msr_autostore.guest.nr); 2485 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 2486 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 2487 2488 set_cr4_guest_host_mask(vmx); 2489 } 2490 2491 /* 2492 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested 2493 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it 2494 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 2495 * guest in a way that will both be appropriate to L1's requests, and our 2496 * needs. In addition to modifying the active vmcs (which is vmcs02), this 2497 * function also has additional necessary side-effects, like setting various 2498 * vcpu->arch fields. 2499 * Returns 0 on success, 1 on failure. Invalid state exit qualification code 2500 * is assigned to entry_failure_code on failure. 2501 */ 2502 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, 2503 enum vm_entry_failure_code *entry_failure_code) 2504 { 2505 struct vcpu_vmx *vmx = to_vmx(vcpu); 2506 struct hv_enlightened_vmcs *hv_evmcs = vmx->nested.hv_evmcs; 2507 bool load_guest_pdptrs_vmcs12 = false; 2508 2509 if (vmx->nested.dirty_vmcs12 || hv_evmcs) { 2510 prepare_vmcs02_rare(vmx, vmcs12); 2511 vmx->nested.dirty_vmcs12 = false; 2512 2513 load_guest_pdptrs_vmcs12 = !hv_evmcs || 2514 !(hv_evmcs->hv_clean_fields & 2515 HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1); 2516 } 2517 2518 if (vmx->nested.nested_run_pending && 2519 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { 2520 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); 2521 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); 2522 } else { 2523 kvm_set_dr(vcpu, 7, vcpu->arch.dr7); 2524 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); 2525 } 2526 if (kvm_mpx_supported() && (!vmx->nested.nested_run_pending || 2527 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))) 2528 vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs); 2529 vmx_set_rflags(vcpu, vmcs12->guest_rflags); 2530 2531 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the 2532 * bitwise-or of what L1 wants to trap for L2, and what we want to 2533 * trap. Note that CR0.TS also needs updating - we do this later. 2534 */ 2535 update_exception_bitmap(vcpu); 2536 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; 2537 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); 2538 2539 if (vmx->nested.nested_run_pending && 2540 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { 2541 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); 2542 vcpu->arch.pat = vmcs12->guest_ia32_pat; 2543 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2544 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 2545 } 2546 2547 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); 2548 2549 if (kvm_has_tsc_control) 2550 decache_tsc_multiplier(vmx); 2551 2552 nested_vmx_transition_tlb_flush(vcpu, vmcs12, true); 2553 2554 if (nested_cpu_has_ept(vmcs12)) 2555 nested_ept_init_mmu_context(vcpu); 2556 2557 /* 2558 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those 2559 * bits which we consider mandatory enabled. 2560 * The CR0_READ_SHADOW is what L2 should have expected to read given 2561 * the specifications by L1; It's not enough to take 2562 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we 2563 * have more bits than L1 expected. 2564 */ 2565 vmx_set_cr0(vcpu, vmcs12->guest_cr0); 2566 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); 2567 2568 vmx_set_cr4(vcpu, vmcs12->guest_cr4); 2569 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); 2570 2571 vcpu->arch.efer = nested_vmx_calc_efer(vmx, vmcs12); 2572 /* Note: may modify VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ 2573 vmx_set_efer(vcpu, vcpu->arch.efer); 2574 2575 /* 2576 * Guest state is invalid and unrestricted guest is disabled, 2577 * which means L1 attempted VMEntry to L2 with invalid state. 2578 * Fail the VMEntry. 2579 */ 2580 if (CC(!vmx_guest_state_valid(vcpu))) { 2581 *entry_failure_code = ENTRY_FAIL_DEFAULT; 2582 return -EINVAL; 2583 } 2584 2585 /* Shadow page tables on either EPT or shadow page tables. */ 2586 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), 2587 entry_failure_code)) 2588 return -EINVAL; 2589 2590 /* 2591 * Immediately write vmcs02.GUEST_CR3. It will be propagated to vmcs12 2592 * on nested VM-Exit, which can occur without actually running L2 and 2593 * thus without hitting vmx_load_mmu_pgd(), e.g. if L1 is entering L2 with 2594 * vmcs12.GUEST_ACTIVITYSTATE=HLT, in which case KVM will intercept the 2595 * transition to HLT instead of running L2. 2596 */ 2597 if (enable_ept) 2598 vmcs_writel(GUEST_CR3, vmcs12->guest_cr3); 2599 2600 /* Late preparation of GUEST_PDPTRs now that EFER and CRs are set. */ 2601 if (load_guest_pdptrs_vmcs12 && nested_cpu_has_ept(vmcs12) && 2602 is_pae_paging(vcpu)) { 2603 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); 2604 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); 2605 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); 2606 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); 2607 } 2608 2609 if (!enable_ept) 2610 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; 2611 2612 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && 2613 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, 2614 vmcs12->guest_ia32_perf_global_ctrl))) 2615 return -EINVAL; 2616 2617 kvm_rsp_write(vcpu, vmcs12->guest_rsp); 2618 kvm_rip_write(vcpu, vmcs12->guest_rip); 2619 return 0; 2620 } 2621 2622 static int nested_vmx_check_nmi_controls(struct vmcs12 *vmcs12) 2623 { 2624 if (CC(!nested_cpu_has_nmi_exiting(vmcs12) && 2625 nested_cpu_has_virtual_nmis(vmcs12))) 2626 return -EINVAL; 2627 2628 if (CC(!nested_cpu_has_virtual_nmis(vmcs12) && 2629 nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING))) 2630 return -EINVAL; 2631 2632 return 0; 2633 } 2634 2635 static bool nested_vmx_check_eptp(struct kvm_vcpu *vcpu, u64 new_eptp) 2636 { 2637 struct vcpu_vmx *vmx = to_vmx(vcpu); 2638 int maxphyaddr = cpuid_maxphyaddr(vcpu); 2639 2640 /* Check for memory type validity */ 2641 switch (new_eptp & VMX_EPTP_MT_MASK) { 2642 case VMX_EPTP_MT_UC: 2643 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_UC_BIT))) 2644 return false; 2645 break; 2646 case VMX_EPTP_MT_WB: 2647 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPTP_WB_BIT))) 2648 return false; 2649 break; 2650 default: 2651 return false; 2652 } 2653 2654 /* Page-walk levels validity. */ 2655 switch (new_eptp & VMX_EPTP_PWL_MASK) { 2656 case VMX_EPTP_PWL_5: 2657 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_5_BIT))) 2658 return false; 2659 break; 2660 case VMX_EPTP_PWL_4: 2661 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_PAGE_WALK_4_BIT))) 2662 return false; 2663 break; 2664 default: 2665 return false; 2666 } 2667 2668 /* Reserved bits should not be set */ 2669 if (CC(new_eptp >> maxphyaddr || ((new_eptp >> 7) & 0x1f))) 2670 return false; 2671 2672 /* AD, if set, should be supported */ 2673 if (new_eptp & VMX_EPTP_AD_ENABLE_BIT) { 2674 if (CC(!(vmx->nested.msrs.ept_caps & VMX_EPT_AD_BIT))) 2675 return false; 2676 } 2677 2678 return true; 2679 } 2680 2681 /* 2682 * Checks related to VM-Execution Control Fields 2683 */ 2684 static int nested_check_vm_execution_controls(struct kvm_vcpu *vcpu, 2685 struct vmcs12 *vmcs12) 2686 { 2687 struct vcpu_vmx *vmx = to_vmx(vcpu); 2688 2689 if (CC(!vmx_control_verify(vmcs12->pin_based_vm_exec_control, 2690 vmx->nested.msrs.pinbased_ctls_low, 2691 vmx->nested.msrs.pinbased_ctls_high)) || 2692 CC(!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, 2693 vmx->nested.msrs.procbased_ctls_low, 2694 vmx->nested.msrs.procbased_ctls_high))) 2695 return -EINVAL; 2696 2697 if (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && 2698 CC(!vmx_control_verify(vmcs12->secondary_vm_exec_control, 2699 vmx->nested.msrs.secondary_ctls_low, 2700 vmx->nested.msrs.secondary_ctls_high))) 2701 return -EINVAL; 2702 2703 if (CC(vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) || 2704 nested_vmx_check_io_bitmap_controls(vcpu, vmcs12) || 2705 nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12) || 2706 nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12) || 2707 nested_vmx_check_apic_access_controls(vcpu, vmcs12) || 2708 nested_vmx_check_apicv_controls(vcpu, vmcs12) || 2709 nested_vmx_check_nmi_controls(vmcs12) || 2710 nested_vmx_check_pml_controls(vcpu, vmcs12) || 2711 nested_vmx_check_unrestricted_guest_controls(vcpu, vmcs12) || 2712 nested_vmx_check_mode_based_ept_exec_controls(vcpu, vmcs12) || 2713 nested_vmx_check_shadow_vmcs_controls(vcpu, vmcs12) || 2714 CC(nested_cpu_has_vpid(vmcs12) && !vmcs12->virtual_processor_id)) 2715 return -EINVAL; 2716 2717 if (!nested_cpu_has_preemption_timer(vmcs12) && 2718 nested_cpu_has_save_preemption_timer(vmcs12)) 2719 return -EINVAL; 2720 2721 if (nested_cpu_has_ept(vmcs12) && 2722 CC(!nested_vmx_check_eptp(vcpu, vmcs12->ept_pointer))) 2723 return -EINVAL; 2724 2725 if (nested_cpu_has_vmfunc(vmcs12)) { 2726 if (CC(vmcs12->vm_function_control & 2727 ~vmx->nested.msrs.vmfunc_controls)) 2728 return -EINVAL; 2729 2730 if (nested_cpu_has_eptp_switching(vmcs12)) { 2731 if (CC(!nested_cpu_has_ept(vmcs12)) || 2732 CC(!page_address_valid(vcpu, vmcs12->eptp_list_address))) 2733 return -EINVAL; 2734 } 2735 } 2736 2737 return 0; 2738 } 2739 2740 /* 2741 * Checks related to VM-Exit Control Fields 2742 */ 2743 static int nested_check_vm_exit_controls(struct kvm_vcpu *vcpu, 2744 struct vmcs12 *vmcs12) 2745 { 2746 struct vcpu_vmx *vmx = to_vmx(vcpu); 2747 2748 if (CC(!vmx_control_verify(vmcs12->vm_exit_controls, 2749 vmx->nested.msrs.exit_ctls_low, 2750 vmx->nested.msrs.exit_ctls_high)) || 2751 CC(nested_vmx_check_exit_msr_switch_controls(vcpu, vmcs12))) 2752 return -EINVAL; 2753 2754 return 0; 2755 } 2756 2757 /* 2758 * Checks related to VM-Entry Control Fields 2759 */ 2760 static int nested_check_vm_entry_controls(struct kvm_vcpu *vcpu, 2761 struct vmcs12 *vmcs12) 2762 { 2763 struct vcpu_vmx *vmx = to_vmx(vcpu); 2764 2765 if (CC(!vmx_control_verify(vmcs12->vm_entry_controls, 2766 vmx->nested.msrs.entry_ctls_low, 2767 vmx->nested.msrs.entry_ctls_high))) 2768 return -EINVAL; 2769 2770 /* 2771 * From the Intel SDM, volume 3: 2772 * Fields relevant to VM-entry event injection must be set properly. 2773 * These fields are the VM-entry interruption-information field, the 2774 * VM-entry exception error code, and the VM-entry instruction length. 2775 */ 2776 if (vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) { 2777 u32 intr_info = vmcs12->vm_entry_intr_info_field; 2778 u8 vector = intr_info & INTR_INFO_VECTOR_MASK; 2779 u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK; 2780 bool has_error_code = intr_info & INTR_INFO_DELIVER_CODE_MASK; 2781 bool should_have_error_code; 2782 bool urg = nested_cpu_has2(vmcs12, 2783 SECONDARY_EXEC_UNRESTRICTED_GUEST); 2784 bool prot_mode = !urg || vmcs12->guest_cr0 & X86_CR0_PE; 2785 2786 /* VM-entry interruption-info field: interruption type */ 2787 if (CC(intr_type == INTR_TYPE_RESERVED) || 2788 CC(intr_type == INTR_TYPE_OTHER_EVENT && 2789 !nested_cpu_supports_monitor_trap_flag(vcpu))) 2790 return -EINVAL; 2791 2792 /* VM-entry interruption-info field: vector */ 2793 if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) || 2794 CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) || 2795 CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0)) 2796 return -EINVAL; 2797 2798 /* VM-entry interruption-info field: deliver error code */ 2799 should_have_error_code = 2800 intr_type == INTR_TYPE_HARD_EXCEPTION && prot_mode && 2801 x86_exception_has_error_code(vector); 2802 if (CC(has_error_code != should_have_error_code)) 2803 return -EINVAL; 2804 2805 /* VM-entry exception error code */ 2806 if (CC(has_error_code && 2807 vmcs12->vm_entry_exception_error_code & GENMASK(31, 16))) 2808 return -EINVAL; 2809 2810 /* VM-entry interruption-info field: reserved bits */ 2811 if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK)) 2812 return -EINVAL; 2813 2814 /* VM-entry instruction length */ 2815 switch (intr_type) { 2816 case INTR_TYPE_SOFT_EXCEPTION: 2817 case INTR_TYPE_SOFT_INTR: 2818 case INTR_TYPE_PRIV_SW_EXCEPTION: 2819 if (CC(vmcs12->vm_entry_instruction_len > 15) || 2820 CC(vmcs12->vm_entry_instruction_len == 0 && 2821 CC(!nested_cpu_has_zero_length_injection(vcpu)))) 2822 return -EINVAL; 2823 } 2824 } 2825 2826 if (nested_vmx_check_entry_msr_switch_controls(vcpu, vmcs12)) 2827 return -EINVAL; 2828 2829 return 0; 2830 } 2831 2832 static int nested_vmx_check_controls(struct kvm_vcpu *vcpu, 2833 struct vmcs12 *vmcs12) 2834 { 2835 if (nested_check_vm_execution_controls(vcpu, vmcs12) || 2836 nested_check_vm_exit_controls(vcpu, vmcs12) || 2837 nested_check_vm_entry_controls(vcpu, vmcs12)) 2838 return -EINVAL; 2839 2840 if (to_vmx(vcpu)->nested.enlightened_vmcs_enabled) 2841 return nested_evmcs_check_controls(vmcs12); 2842 2843 return 0; 2844 } 2845 2846 static int nested_vmx_check_host_state(struct kvm_vcpu *vcpu, 2847 struct vmcs12 *vmcs12) 2848 { 2849 bool ia32e; 2850 2851 if (CC(!nested_host_cr0_valid(vcpu, vmcs12->host_cr0)) || 2852 CC(!nested_host_cr4_valid(vcpu, vmcs12->host_cr4)) || 2853 CC(!nested_cr3_valid(vcpu, vmcs12->host_cr3))) 2854 return -EINVAL; 2855 2856 if (CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_esp, vcpu)) || 2857 CC(is_noncanonical_address(vmcs12->host_ia32_sysenter_eip, vcpu))) 2858 return -EINVAL; 2859 2860 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) && 2861 CC(!kvm_pat_valid(vmcs12->host_ia32_pat))) 2862 return -EINVAL; 2863 2864 if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) && 2865 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu), 2866 vmcs12->host_ia32_perf_global_ctrl))) 2867 return -EINVAL; 2868 2869 #ifdef CONFIG_X86_64 2870 ia32e = !!(vcpu->arch.efer & EFER_LMA); 2871 #else 2872 ia32e = false; 2873 #endif 2874 2875 if (ia32e) { 2876 if (CC(!(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)) || 2877 CC(!(vmcs12->host_cr4 & X86_CR4_PAE))) 2878 return -EINVAL; 2879 } else { 2880 if (CC(vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) || 2881 CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) || 2882 CC(vmcs12->host_cr4 & X86_CR4_PCIDE) || 2883 CC((vmcs12->host_rip) >> 32)) 2884 return -EINVAL; 2885 } 2886 2887 if (CC(vmcs12->host_cs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2888 CC(vmcs12->host_ss_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2889 CC(vmcs12->host_ds_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2890 CC(vmcs12->host_es_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2891 CC(vmcs12->host_fs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2892 CC(vmcs12->host_gs_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2893 CC(vmcs12->host_tr_selector & (SEGMENT_RPL_MASK | SEGMENT_TI_MASK)) || 2894 CC(vmcs12->host_cs_selector == 0) || 2895 CC(vmcs12->host_tr_selector == 0) || 2896 CC(vmcs12->host_ss_selector == 0 && !ia32e)) 2897 return -EINVAL; 2898 2899 if (CC(is_noncanonical_address(vmcs12->host_fs_base, vcpu)) || 2900 CC(is_noncanonical_address(vmcs12->host_gs_base, vcpu)) || 2901 CC(is_noncanonical_address(vmcs12->host_gdtr_base, vcpu)) || 2902 CC(is_noncanonical_address(vmcs12->host_idtr_base, vcpu)) || 2903 CC(is_noncanonical_address(vmcs12->host_tr_base, vcpu)) || 2904 CC(is_noncanonical_address(vmcs12->host_rip, vcpu))) 2905 return -EINVAL; 2906 2907 /* 2908 * If the load IA32_EFER VM-exit control is 1, bits reserved in the 2909 * IA32_EFER MSR must be 0 in the field for that register. In addition, 2910 * the values of the LMA and LME bits in the field must each be that of 2911 * the host address-space size VM-exit control. 2912 */ 2913 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { 2914 if (CC(!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer)) || 2915 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA)) || 2916 CC(ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))) 2917 return -EINVAL; 2918 } 2919 2920 return 0; 2921 } 2922 2923 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu, 2924 struct vmcs12 *vmcs12) 2925 { 2926 int r = 0; 2927 struct vmcs12 *shadow; 2928 struct kvm_host_map map; 2929 2930 if (vmcs12->vmcs_link_pointer == -1ull) 2931 return 0; 2932 2933 if (CC(!page_address_valid(vcpu, vmcs12->vmcs_link_pointer))) 2934 return -EINVAL; 2935 2936 if (CC(kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->vmcs_link_pointer), &map))) 2937 return -EINVAL; 2938 2939 shadow = map.hva; 2940 2941 if (CC(shadow->hdr.revision_id != VMCS12_REVISION) || 2942 CC(shadow->hdr.shadow_vmcs != nested_cpu_has_shadow_vmcs(vmcs12))) 2943 r = -EINVAL; 2944 2945 kvm_vcpu_unmap(vcpu, &map, false); 2946 return r; 2947 } 2948 2949 /* 2950 * Checks related to Guest Non-register State 2951 */ 2952 static int nested_check_guest_non_reg_state(struct vmcs12 *vmcs12) 2953 { 2954 if (CC(vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && 2955 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT && 2956 vmcs12->guest_activity_state != GUEST_ACTIVITY_WAIT_SIPI)) 2957 return -EINVAL; 2958 2959 return 0; 2960 } 2961 2962 static int nested_vmx_check_guest_state(struct kvm_vcpu *vcpu, 2963 struct vmcs12 *vmcs12, 2964 enum vm_entry_failure_code *entry_failure_code) 2965 { 2966 bool ia32e; 2967 2968 *entry_failure_code = ENTRY_FAIL_DEFAULT; 2969 2970 if (CC(!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0)) || 2971 CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))) 2972 return -EINVAL; 2973 2974 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) && 2975 CC(!kvm_dr7_valid(vmcs12->guest_dr7))) 2976 return -EINVAL; 2977 2978 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) && 2979 CC(!kvm_pat_valid(vmcs12->guest_ia32_pat))) 2980 return -EINVAL; 2981 2982 if (nested_vmx_check_vmcs_link_ptr(vcpu, vmcs12)) { 2983 *entry_failure_code = ENTRY_FAIL_VMCS_LINK_PTR; 2984 return -EINVAL; 2985 } 2986 2987 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && 2988 CC(!kvm_valid_perf_global_ctrl(vcpu_to_pmu(vcpu), 2989 vmcs12->guest_ia32_perf_global_ctrl))) 2990 return -EINVAL; 2991 2992 /* 2993 * If the load IA32_EFER VM-entry control is 1, the following checks 2994 * are performed on the field for the IA32_EFER MSR: 2995 * - Bits reserved in the IA32_EFER MSR must be 0. 2996 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of 2997 * the IA-32e mode guest VM-exit control. It must also be identical 2998 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to 2999 * CR0.PG) is 1. 3000 */ 3001 if (to_vmx(vcpu)->nested.nested_run_pending && 3002 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { 3003 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; 3004 if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) || 3005 CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) || 3006 CC(((vmcs12->guest_cr0 & X86_CR0_PG) && 3007 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))) 3008 return -EINVAL; 3009 } 3010 3011 if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) && 3012 (CC(is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu)) || 3013 CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))) 3014 return -EINVAL; 3015 3016 if (nested_check_guest_non_reg_state(vmcs12)) 3017 return -EINVAL; 3018 3019 return 0; 3020 } 3021 3022 static int nested_vmx_check_vmentry_hw(struct kvm_vcpu *vcpu) 3023 { 3024 struct vcpu_vmx *vmx = to_vmx(vcpu); 3025 unsigned long cr3, cr4; 3026 bool vm_fail; 3027 3028 if (!nested_early_check) 3029 return 0; 3030 3031 if (vmx->msr_autoload.host.nr) 3032 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 3033 if (vmx->msr_autoload.guest.nr) 3034 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 3035 3036 preempt_disable(); 3037 3038 vmx_prepare_switch_to_guest(vcpu); 3039 3040 /* 3041 * Induce a consistency check VMExit by clearing bit 1 in GUEST_RFLAGS, 3042 * which is reserved to '1' by hardware. GUEST_RFLAGS is guaranteed to 3043 * be written (by prepare_vmcs02()) before the "real" VMEnter, i.e. 3044 * there is no need to preserve other bits or save/restore the field. 3045 */ 3046 vmcs_writel(GUEST_RFLAGS, 0); 3047 3048 cr3 = __get_current_cr3_fast(); 3049 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 3050 vmcs_writel(HOST_CR3, cr3); 3051 vmx->loaded_vmcs->host_state.cr3 = cr3; 3052 } 3053 3054 cr4 = cr4_read_shadow(); 3055 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 3056 vmcs_writel(HOST_CR4, cr4); 3057 vmx->loaded_vmcs->host_state.cr4 = cr4; 3058 } 3059 3060 asm( 3061 "sub $%c[wordsize], %%" _ASM_SP "\n\t" /* temporarily adjust RSP for CALL */ 3062 "cmp %%" _ASM_SP ", %c[host_state_rsp](%[loaded_vmcs]) \n\t" 3063 "je 1f \n\t" 3064 __ex("vmwrite %%" _ASM_SP ", %[HOST_RSP]") "\n\t" 3065 "mov %%" _ASM_SP ", %c[host_state_rsp](%[loaded_vmcs]) \n\t" 3066 "1: \n\t" 3067 "add $%c[wordsize], %%" _ASM_SP "\n\t" /* un-adjust RSP */ 3068 3069 /* Check if vmlaunch or vmresume is needed */ 3070 "cmpb $0, %c[launched](%[loaded_vmcs])\n\t" 3071 3072 /* 3073 * VMLAUNCH and VMRESUME clear RFLAGS.{CF,ZF} on VM-Exit, set 3074 * RFLAGS.CF on VM-Fail Invalid and set RFLAGS.ZF on VM-Fail 3075 * Valid. vmx_vmenter() directly "returns" RFLAGS, and so the 3076 * results of VM-Enter is captured via CC_{SET,OUT} to vm_fail. 3077 */ 3078 "call vmx_vmenter\n\t" 3079 3080 CC_SET(be) 3081 : ASM_CALL_CONSTRAINT, CC_OUT(be) (vm_fail) 3082 : [HOST_RSP]"r"((unsigned long)HOST_RSP), 3083 [loaded_vmcs]"r"(vmx->loaded_vmcs), 3084 [launched]"i"(offsetof(struct loaded_vmcs, launched)), 3085 [host_state_rsp]"i"(offsetof(struct loaded_vmcs, host_state.rsp)), 3086 [wordsize]"i"(sizeof(ulong)) 3087 : "memory" 3088 ); 3089 3090 if (vmx->msr_autoload.host.nr) 3091 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 3092 if (vmx->msr_autoload.guest.nr) 3093 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 3094 3095 if (vm_fail) { 3096 u32 error = vmcs_read32(VM_INSTRUCTION_ERROR); 3097 3098 preempt_enable(); 3099 3100 trace_kvm_nested_vmenter_failed( 3101 "early hardware check VM-instruction error: ", error); 3102 WARN_ON_ONCE(error != VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3103 return 1; 3104 } 3105 3106 /* 3107 * VMExit clears RFLAGS.IF and DR7, even on a consistency check. 3108 */ 3109 if (hw_breakpoint_active()) 3110 set_debugreg(__this_cpu_read(cpu_dr7), 7); 3111 local_irq_enable(); 3112 preempt_enable(); 3113 3114 /* 3115 * A non-failing VMEntry means we somehow entered guest mode with 3116 * an illegal RIP, and that's just the tip of the iceberg. There 3117 * is no telling what memory has been modified or what state has 3118 * been exposed to unknown code. Hitting this all but guarantees 3119 * a (very critical) hardware issue. 3120 */ 3121 WARN_ON(!(vmcs_read32(VM_EXIT_REASON) & 3122 VMX_EXIT_REASONS_FAILED_VMENTRY)); 3123 3124 return 0; 3125 } 3126 3127 static bool nested_get_evmcs_page(struct kvm_vcpu *vcpu) 3128 { 3129 struct vcpu_vmx *vmx = to_vmx(vcpu); 3130 3131 /* 3132 * hv_evmcs may end up being not mapped after migration (when 3133 * L2 was running), map it here to make sure vmcs12 changes are 3134 * properly reflected. 3135 */ 3136 if (vmx->nested.enlightened_vmcs_enabled && !vmx->nested.hv_evmcs) { 3137 enum nested_evmptrld_status evmptrld_status = 3138 nested_vmx_handle_enlightened_vmptrld(vcpu, false); 3139 3140 if (evmptrld_status == EVMPTRLD_VMFAIL || 3141 evmptrld_status == EVMPTRLD_ERROR) { 3142 pr_debug_ratelimited("%s: enlightened vmptrld failed\n", 3143 __func__); 3144 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 3145 vcpu->run->internal.suberror = 3146 KVM_INTERNAL_ERROR_EMULATION; 3147 vcpu->run->internal.ndata = 0; 3148 return false; 3149 } 3150 } 3151 3152 return true; 3153 } 3154 3155 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu) 3156 { 3157 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3158 struct vcpu_vmx *vmx = to_vmx(vcpu); 3159 struct kvm_host_map *map; 3160 struct page *page; 3161 u64 hpa; 3162 3163 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { 3164 /* 3165 * Translate L1 physical address to host physical 3166 * address for vmcs02. Keep the page pinned, so this 3167 * physical address remains valid. We keep a reference 3168 * to it so we can release it later. 3169 */ 3170 if (vmx->nested.apic_access_page) { /* shouldn't happen */ 3171 kvm_release_page_clean(vmx->nested.apic_access_page); 3172 vmx->nested.apic_access_page = NULL; 3173 } 3174 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr); 3175 if (!is_error_page(page)) { 3176 vmx->nested.apic_access_page = page; 3177 hpa = page_to_phys(vmx->nested.apic_access_page); 3178 vmcs_write64(APIC_ACCESS_ADDR, hpa); 3179 } else { 3180 pr_debug_ratelimited("%s: no backing 'struct page' for APIC-access address in vmcs12\n", 3181 __func__); 3182 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 3183 vcpu->run->internal.suberror = 3184 KVM_INTERNAL_ERROR_EMULATION; 3185 vcpu->run->internal.ndata = 0; 3186 return false; 3187 } 3188 } 3189 3190 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { 3191 map = &vmx->nested.virtual_apic_map; 3192 3193 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->virtual_apic_page_addr), map)) { 3194 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, pfn_to_hpa(map->pfn)); 3195 } else if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING) && 3196 nested_cpu_has(vmcs12, CPU_BASED_CR8_STORE_EXITING) && 3197 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { 3198 /* 3199 * The processor will never use the TPR shadow, simply 3200 * clear the bit from the execution control. Such a 3201 * configuration is useless, but it happens in tests. 3202 * For any other configuration, failing the vm entry is 3203 * _not_ what the processor does but it's basically the 3204 * only possibility we have. 3205 */ 3206 exec_controls_clearbit(vmx, CPU_BASED_TPR_SHADOW); 3207 } else { 3208 /* 3209 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR to 3210 * force VM-Entry to fail. 3211 */ 3212 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); 3213 } 3214 } 3215 3216 if (nested_cpu_has_posted_intr(vmcs12)) { 3217 map = &vmx->nested.pi_desc_map; 3218 3219 if (!kvm_vcpu_map(vcpu, gpa_to_gfn(vmcs12->posted_intr_desc_addr), map)) { 3220 vmx->nested.pi_desc = 3221 (struct pi_desc *)(((void *)map->hva) + 3222 offset_in_page(vmcs12->posted_intr_desc_addr)); 3223 vmcs_write64(POSTED_INTR_DESC_ADDR, 3224 pfn_to_hpa(map->pfn) + offset_in_page(vmcs12->posted_intr_desc_addr)); 3225 } 3226 } 3227 if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12)) 3228 exec_controls_setbit(vmx, CPU_BASED_USE_MSR_BITMAPS); 3229 else 3230 exec_controls_clearbit(vmx, CPU_BASED_USE_MSR_BITMAPS); 3231 3232 return true; 3233 } 3234 3235 static bool vmx_get_nested_state_pages(struct kvm_vcpu *vcpu) 3236 { 3237 if (!nested_get_evmcs_page(vcpu)) 3238 return false; 3239 3240 if (is_guest_mode(vcpu) && !nested_get_vmcs12_pages(vcpu)) 3241 return false; 3242 3243 return true; 3244 } 3245 3246 static int nested_vmx_write_pml_buffer(struct kvm_vcpu *vcpu, gpa_t gpa) 3247 { 3248 struct vmcs12 *vmcs12; 3249 struct vcpu_vmx *vmx = to_vmx(vcpu); 3250 gpa_t dst; 3251 3252 if (WARN_ON_ONCE(!is_guest_mode(vcpu))) 3253 return 0; 3254 3255 if (WARN_ON_ONCE(vmx->nested.pml_full)) 3256 return 1; 3257 3258 /* 3259 * Check if PML is enabled for the nested guest. Whether eptp bit 6 is 3260 * set is already checked as part of A/D emulation. 3261 */ 3262 vmcs12 = get_vmcs12(vcpu); 3263 if (!nested_cpu_has_pml(vmcs12)) 3264 return 0; 3265 3266 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 3267 vmx->nested.pml_full = true; 3268 return 1; 3269 } 3270 3271 gpa &= ~0xFFFull; 3272 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 3273 3274 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 3275 offset_in_page(dst), sizeof(gpa))) 3276 return 0; 3277 3278 vmcs12->guest_pml_index--; 3279 3280 return 0; 3281 } 3282 3283 /* 3284 * Intel's VMX Instruction Reference specifies a common set of prerequisites 3285 * for running VMX instructions (except VMXON, whose prerequisites are 3286 * slightly different). It also specifies what exception to inject otherwise. 3287 * Note that many of these exceptions have priority over VM exits, so they 3288 * don't have to be checked again here. 3289 */ 3290 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) 3291 { 3292 if (!to_vmx(vcpu)->nested.vmxon) { 3293 kvm_queue_exception(vcpu, UD_VECTOR); 3294 return 0; 3295 } 3296 3297 if (vmx_get_cpl(vcpu)) { 3298 kvm_inject_gp(vcpu, 0); 3299 return 0; 3300 } 3301 3302 return 1; 3303 } 3304 3305 static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu) 3306 { 3307 u8 rvi = vmx_get_rvi(); 3308 u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI); 3309 3310 return ((rvi & 0xf0) > (vppr & 0xf0)); 3311 } 3312 3313 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, 3314 struct vmcs12 *vmcs12); 3315 3316 /* 3317 * If from_vmentry is false, this is being called from state restore (either RSM 3318 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume. 3319 * 3320 * Returns: 3321 * NVMX_VMENTRY_SUCCESS: Entered VMX non-root mode 3322 * NVMX_VMENTRY_VMFAIL: Consistency check VMFail 3323 * NVMX_VMENTRY_VMEXIT: Consistency check VMExit 3324 * NVMX_VMENTRY_KVM_INTERNAL_ERROR: KVM internal error 3325 */ 3326 enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu, 3327 bool from_vmentry) 3328 { 3329 struct vcpu_vmx *vmx = to_vmx(vcpu); 3330 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3331 enum vm_entry_failure_code entry_failure_code; 3332 bool evaluate_pending_interrupts; 3333 u32 exit_reason, failed_index; 3334 3335 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3336 kvm_vcpu_flush_tlb_current(vcpu); 3337 3338 evaluate_pending_interrupts = exec_controls_get(vmx) & 3339 (CPU_BASED_INTR_WINDOW_EXITING | CPU_BASED_NMI_WINDOW_EXITING); 3340 if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu)) 3341 evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu); 3342 3343 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) 3344 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); 3345 if (kvm_mpx_supported() && 3346 !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)) 3347 vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); 3348 3349 /* 3350 * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and* 3351 * nested early checks are disabled. In the event of a "late" VM-Fail, 3352 * i.e. a VM-Fail detected by hardware but not KVM, KVM must unwind its 3353 * software model to the pre-VMEntry host state. When EPT is disabled, 3354 * GUEST_CR3 holds KVM's shadow CR3, not L1's "real" CR3, which causes 3355 * nested_vmx_restore_host_state() to corrupt vcpu->arch.cr3. Stuffing 3356 * vmcs01.GUEST_CR3 results in the unwind naturally setting arch.cr3 to 3357 * the correct value. Smashing vmcs01.GUEST_CR3 is safe because nested 3358 * VM-Exits, and the unwind, reset KVM's MMU, i.e. vmcs01.GUEST_CR3 is 3359 * guaranteed to be overwritten with a shadow CR3 prior to re-entering 3360 * L1. Don't stuff vmcs01.GUEST_CR3 when using nested early checks as 3361 * KVM modifies vcpu->arch.cr3 if and only if the early hardware checks 3362 * pass, and early VM-Fails do not reset KVM's MMU, i.e. the VM-Fail 3363 * path would need to manually save/restore vmcs01.GUEST_CR3. 3364 */ 3365 if (!enable_ept && !nested_early_check) 3366 vmcs_writel(GUEST_CR3, vcpu->arch.cr3); 3367 3368 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02); 3369 3370 prepare_vmcs02_early(vmx, vmcs12); 3371 3372 if (from_vmentry) { 3373 if (unlikely(!nested_get_vmcs12_pages(vcpu))) { 3374 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 3375 return NVMX_VMENTRY_KVM_INTERNAL_ERROR; 3376 } 3377 3378 if (nested_vmx_check_vmentry_hw(vcpu)) { 3379 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 3380 return NVMX_VMENTRY_VMFAIL; 3381 } 3382 3383 if (nested_vmx_check_guest_state(vcpu, vmcs12, 3384 &entry_failure_code)) { 3385 exit_reason = EXIT_REASON_INVALID_STATE; 3386 vmcs12->exit_qualification = entry_failure_code; 3387 goto vmentry_fail_vmexit; 3388 } 3389 } 3390 3391 enter_guest_mode(vcpu); 3392 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING) 3393 vcpu->arch.tsc_offset += vmcs12->tsc_offset; 3394 3395 if (prepare_vmcs02(vcpu, vmcs12, &entry_failure_code)) { 3396 exit_reason = EXIT_REASON_INVALID_STATE; 3397 vmcs12->exit_qualification = entry_failure_code; 3398 goto vmentry_fail_vmexit_guest_mode; 3399 } 3400 3401 if (from_vmentry) { 3402 failed_index = nested_vmx_load_msr(vcpu, 3403 vmcs12->vm_entry_msr_load_addr, 3404 vmcs12->vm_entry_msr_load_count); 3405 if (failed_index) { 3406 exit_reason = EXIT_REASON_MSR_LOAD_FAIL; 3407 vmcs12->exit_qualification = failed_index; 3408 goto vmentry_fail_vmexit_guest_mode; 3409 } 3410 } else { 3411 /* 3412 * The MMU is not initialized to point at the right entities yet and 3413 * "get pages" would need to read data from the guest (i.e. we will 3414 * need to perform gpa to hpa translation). Request a call 3415 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs 3416 * have already been set at vmentry time and should not be reset. 3417 */ 3418 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 3419 } 3420 3421 /* 3422 * If L1 had a pending IRQ/NMI until it executed 3423 * VMLAUNCH/VMRESUME which wasn't delivered because it was 3424 * disallowed (e.g. interrupts disabled), L0 needs to 3425 * evaluate if this pending event should cause an exit from L2 3426 * to L1 or delivered directly to L2 (e.g. In case L1 don't 3427 * intercept EXTERNAL_INTERRUPT). 3428 * 3429 * Usually this would be handled by the processor noticing an 3430 * IRQ/NMI window request, or checking RVI during evaluation of 3431 * pending virtual interrupts. However, this setting was done 3432 * on VMCS01 and now VMCS02 is active instead. Thus, we force L0 3433 * to perform pending event evaluation by requesting a KVM_REQ_EVENT. 3434 */ 3435 if (unlikely(evaluate_pending_interrupts)) 3436 kvm_make_request(KVM_REQ_EVENT, vcpu); 3437 3438 /* 3439 * Do not start the preemption timer hrtimer until after we know 3440 * we are successful, so that only nested_vmx_vmexit needs to cancel 3441 * the timer. 3442 */ 3443 vmx->nested.preemption_timer_expired = false; 3444 if (nested_cpu_has_preemption_timer(vmcs12)) { 3445 u64 timer_value = vmx_calc_preemption_timer_value(vcpu); 3446 vmx_start_preemption_timer(vcpu, timer_value); 3447 } 3448 3449 /* 3450 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point 3451 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet 3452 * returned as far as L1 is concerned. It will only return (and set 3453 * the success flag) when L2 exits (see nested_vmx_vmexit()). 3454 */ 3455 return NVMX_VMENTRY_SUCCESS; 3456 3457 /* 3458 * A failed consistency check that leads to a VMExit during L1's 3459 * VMEnter to L2 is a variation of a normal VMexit, as explained in 3460 * 26.7 "VM-entry failures during or after loading guest state". 3461 */ 3462 vmentry_fail_vmexit_guest_mode: 3463 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING) 3464 vcpu->arch.tsc_offset -= vmcs12->tsc_offset; 3465 leave_guest_mode(vcpu); 3466 3467 vmentry_fail_vmexit: 3468 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 3469 3470 if (!from_vmentry) 3471 return NVMX_VMENTRY_VMEXIT; 3472 3473 load_vmcs12_host_state(vcpu, vmcs12); 3474 vmcs12->vm_exit_reason = exit_reason | VMX_EXIT_REASONS_FAILED_VMENTRY; 3475 if (enable_shadow_vmcs || vmx->nested.hv_evmcs) 3476 vmx->nested.need_vmcs12_to_shadow_sync = true; 3477 return NVMX_VMENTRY_VMEXIT; 3478 } 3479 3480 /* 3481 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 3482 * for running an L2 nested guest. 3483 */ 3484 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) 3485 { 3486 struct vmcs12 *vmcs12; 3487 enum nvmx_vmentry_status status; 3488 struct vcpu_vmx *vmx = to_vmx(vcpu); 3489 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); 3490 enum nested_evmptrld_status evmptrld_status; 3491 3492 if (!nested_vmx_check_permission(vcpu)) 3493 return 1; 3494 3495 evmptrld_status = nested_vmx_handle_enlightened_vmptrld(vcpu, launch); 3496 if (evmptrld_status == EVMPTRLD_ERROR) { 3497 kvm_queue_exception(vcpu, UD_VECTOR); 3498 return 1; 3499 } else if (CC(evmptrld_status == EVMPTRLD_VMFAIL)) { 3500 return nested_vmx_failInvalid(vcpu); 3501 } 3502 3503 if (CC(!vmx->nested.hv_evmcs && vmx->nested.current_vmptr == -1ull)) 3504 return nested_vmx_failInvalid(vcpu); 3505 3506 vmcs12 = get_vmcs12(vcpu); 3507 3508 /* 3509 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact 3510 * that there *is* a valid VMCS pointer, RFLAGS.CF is set 3511 * rather than RFLAGS.ZF, and no error number is stored to the 3512 * VM-instruction error field. 3513 */ 3514 if (CC(vmcs12->hdr.shadow_vmcs)) 3515 return nested_vmx_failInvalid(vcpu); 3516 3517 if (vmx->nested.hv_evmcs) { 3518 copy_enlightened_to_vmcs12(vmx); 3519 /* Enlightened VMCS doesn't have launch state */ 3520 vmcs12->launch_state = !launch; 3521 } else if (enable_shadow_vmcs) { 3522 copy_shadow_to_vmcs12(vmx); 3523 } 3524 3525 /* 3526 * The nested entry process starts with enforcing various prerequisites 3527 * on vmcs12 as required by the Intel SDM, and act appropriately when 3528 * they fail: As the SDM explains, some conditions should cause the 3529 * instruction to fail, while others will cause the instruction to seem 3530 * to succeed, but return an EXIT_REASON_INVALID_STATE. 3531 * To speed up the normal (success) code path, we should avoid checking 3532 * for misconfigurations which will anyway be caught by the processor 3533 * when using the merged vmcs02. 3534 */ 3535 if (CC(interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS)) 3536 return nested_vmx_fail(vcpu, VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); 3537 3538 if (CC(vmcs12->launch_state == launch)) 3539 return nested_vmx_fail(vcpu, 3540 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS 3541 : VMXERR_VMRESUME_NONLAUNCHED_VMCS); 3542 3543 if (nested_vmx_check_controls(vcpu, vmcs12)) 3544 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3545 3546 if (nested_vmx_check_host_state(vcpu, vmcs12)) 3547 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 3548 3549 /* 3550 * We're finally done with prerequisite checking, and can start with 3551 * the nested entry. 3552 */ 3553 vmx->nested.nested_run_pending = 1; 3554 vmx->nested.has_preemption_timer_deadline = false; 3555 status = nested_vmx_enter_non_root_mode(vcpu, true); 3556 if (unlikely(status != NVMX_VMENTRY_SUCCESS)) 3557 goto vmentry_failed; 3558 3559 /* Emulate processing of posted interrupts on VM-Enter. */ 3560 if (nested_cpu_has_posted_intr(vmcs12) && 3561 kvm_apic_has_interrupt(vcpu) == vmx->nested.posted_intr_nv) { 3562 vmx->nested.pi_pending = true; 3563 kvm_make_request(KVM_REQ_EVENT, vcpu); 3564 kvm_apic_clear_irr(vcpu, vmx->nested.posted_intr_nv); 3565 } 3566 3567 /* Hide L1D cache contents from the nested guest. */ 3568 vmx->vcpu.arch.l1tf_flush_l1d = true; 3569 3570 /* 3571 * Must happen outside of nested_vmx_enter_non_root_mode() as it will 3572 * also be used as part of restoring nVMX state for 3573 * snapshot restore (migration). 3574 * 3575 * In this flow, it is assumed that vmcs12 cache was 3576 * trasferred as part of captured nVMX state and should 3577 * therefore not be read from guest memory (which may not 3578 * exist on destination host yet). 3579 */ 3580 nested_cache_shadow_vmcs12(vcpu, vmcs12); 3581 3582 switch (vmcs12->guest_activity_state) { 3583 case GUEST_ACTIVITY_HLT: 3584 /* 3585 * If we're entering a halted L2 vcpu and the L2 vcpu won't be 3586 * awakened by event injection or by an NMI-window VM-exit or 3587 * by an interrupt-window VM-exit, halt the vcpu. 3588 */ 3589 if (!(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK) && 3590 !nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING) && 3591 !(nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING) && 3592 (vmcs12->guest_rflags & X86_EFLAGS_IF))) { 3593 vmx->nested.nested_run_pending = 0; 3594 return kvm_vcpu_halt(vcpu); 3595 } 3596 break; 3597 case GUEST_ACTIVITY_WAIT_SIPI: 3598 vmx->nested.nested_run_pending = 0; 3599 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 3600 break; 3601 default: 3602 break; 3603 } 3604 3605 return 1; 3606 3607 vmentry_failed: 3608 vmx->nested.nested_run_pending = 0; 3609 if (status == NVMX_VMENTRY_KVM_INTERNAL_ERROR) 3610 return 0; 3611 if (status == NVMX_VMENTRY_VMEXIT) 3612 return 1; 3613 WARN_ON_ONCE(status != NVMX_VMENTRY_VMFAIL); 3614 return nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3615 } 3616 3617 /* 3618 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date 3619 * because L2 may have changed some cr0 bits directly (CR0_GUEST_HOST_MASK). 3620 * This function returns the new value we should put in vmcs12.guest_cr0. 3621 * It's not enough to just return the vmcs02 GUEST_CR0. Rather, 3622 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now 3623 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 3624 * didn't trap the bit, because if L1 did, so would L0). 3625 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have 3626 * been modified by L2, and L1 knows it. So just leave the old value of 3627 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 3628 * isn't relevant, because if L0 traps this bit it can set it to anything. 3629 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have 3630 * changed these bits, and therefore they need to be updated, but L0 3631 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather 3632 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. 3633 */ 3634 static inline unsigned long 3635 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 3636 { 3637 return 3638 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | 3639 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | 3640 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | 3641 vcpu->arch.cr0_guest_owned_bits)); 3642 } 3643 3644 static inline unsigned long 3645 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 3646 { 3647 return 3648 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | 3649 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | 3650 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | 3651 vcpu->arch.cr4_guest_owned_bits)); 3652 } 3653 3654 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, 3655 struct vmcs12 *vmcs12) 3656 { 3657 u32 idt_vectoring; 3658 unsigned int nr; 3659 3660 if (vcpu->arch.exception.injected) { 3661 nr = vcpu->arch.exception.nr; 3662 idt_vectoring = nr | VECTORING_INFO_VALID_MASK; 3663 3664 if (kvm_exception_is_soft(nr)) { 3665 vmcs12->vm_exit_instruction_len = 3666 vcpu->arch.event_exit_inst_len; 3667 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; 3668 } else 3669 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; 3670 3671 if (vcpu->arch.exception.has_error_code) { 3672 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; 3673 vmcs12->idt_vectoring_error_code = 3674 vcpu->arch.exception.error_code; 3675 } 3676 3677 vmcs12->idt_vectoring_info_field = idt_vectoring; 3678 } else if (vcpu->arch.nmi_injected) { 3679 vmcs12->idt_vectoring_info_field = 3680 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; 3681 } else if (vcpu->arch.interrupt.injected) { 3682 nr = vcpu->arch.interrupt.nr; 3683 idt_vectoring = nr | VECTORING_INFO_VALID_MASK; 3684 3685 if (vcpu->arch.interrupt.soft) { 3686 idt_vectoring |= INTR_TYPE_SOFT_INTR; 3687 vmcs12->vm_entry_instruction_len = 3688 vcpu->arch.event_exit_inst_len; 3689 } else 3690 idt_vectoring |= INTR_TYPE_EXT_INTR; 3691 3692 vmcs12->idt_vectoring_info_field = idt_vectoring; 3693 } 3694 } 3695 3696 3697 void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) 3698 { 3699 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3700 gfn_t gfn; 3701 3702 /* 3703 * Don't need to mark the APIC access page dirty; it is never 3704 * written to by the CPU during APIC virtualization. 3705 */ 3706 3707 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { 3708 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; 3709 kvm_vcpu_mark_page_dirty(vcpu, gfn); 3710 } 3711 3712 if (nested_cpu_has_posted_intr(vmcs12)) { 3713 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; 3714 kvm_vcpu_mark_page_dirty(vcpu, gfn); 3715 } 3716 } 3717 3718 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) 3719 { 3720 struct vcpu_vmx *vmx = to_vmx(vcpu); 3721 int max_irr; 3722 void *vapic_page; 3723 u16 status; 3724 3725 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending) 3726 return; 3727 3728 vmx->nested.pi_pending = false; 3729 if (!pi_test_and_clear_on(vmx->nested.pi_desc)) 3730 return; 3731 3732 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); 3733 if (max_irr != 256) { 3734 vapic_page = vmx->nested.virtual_apic_map.hva; 3735 if (!vapic_page) 3736 return; 3737 3738 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, 3739 vapic_page, &max_irr); 3740 status = vmcs_read16(GUEST_INTR_STATUS); 3741 if ((u8)max_irr > ((u8)status & 0xff)) { 3742 status &= ~0xff; 3743 status |= (u8)max_irr; 3744 vmcs_write16(GUEST_INTR_STATUS, status); 3745 } 3746 } 3747 3748 nested_mark_vmcs12_pages_dirty(vcpu); 3749 } 3750 3751 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, 3752 unsigned long exit_qual) 3753 { 3754 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 3755 unsigned int nr = vcpu->arch.exception.nr; 3756 u32 intr_info = nr | INTR_INFO_VALID_MASK; 3757 3758 if (vcpu->arch.exception.has_error_code) { 3759 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; 3760 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 3761 } 3762 3763 if (kvm_exception_is_soft(nr)) 3764 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 3765 else 3766 intr_info |= INTR_TYPE_HARD_EXCEPTION; 3767 3768 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && 3769 vmx_get_nmi_mask(vcpu)) 3770 intr_info |= INTR_INFO_UNBLOCK_NMI; 3771 3772 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); 3773 } 3774 3775 /* 3776 * Returns true if a debug trap is pending delivery. 3777 * 3778 * In KVM, debug traps bear an exception payload. As such, the class of a #DB 3779 * exception may be inferred from the presence of an exception payload. 3780 */ 3781 static inline bool vmx_pending_dbg_trap(struct kvm_vcpu *vcpu) 3782 { 3783 return vcpu->arch.exception.pending && 3784 vcpu->arch.exception.nr == DB_VECTOR && 3785 vcpu->arch.exception.payload; 3786 } 3787 3788 /* 3789 * Certain VM-exits set the 'pending debug exceptions' field to indicate a 3790 * recognized #DB (data or single-step) that has yet to be delivered. Since KVM 3791 * represents these debug traps with a payload that is said to be compatible 3792 * with the 'pending debug exceptions' field, write the payload to the VMCS 3793 * field if a VM-exit is delivered before the debug trap. 3794 */ 3795 static void nested_vmx_update_pending_dbg(struct kvm_vcpu *vcpu) 3796 { 3797 if (vmx_pending_dbg_trap(vcpu)) 3798 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 3799 vcpu->arch.exception.payload); 3800 } 3801 3802 static bool nested_vmx_preemption_timer_pending(struct kvm_vcpu *vcpu) 3803 { 3804 return nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && 3805 to_vmx(vcpu)->nested.preemption_timer_expired; 3806 } 3807 3808 static int vmx_check_nested_events(struct kvm_vcpu *vcpu) 3809 { 3810 struct vcpu_vmx *vmx = to_vmx(vcpu); 3811 unsigned long exit_qual; 3812 bool block_nested_events = 3813 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu); 3814 bool mtf_pending = vmx->nested.mtf_pending; 3815 struct kvm_lapic *apic = vcpu->arch.apic; 3816 3817 /* 3818 * Clear the MTF state. If a higher priority VM-exit is delivered first, 3819 * this state is discarded. 3820 */ 3821 if (!block_nested_events) 3822 vmx->nested.mtf_pending = false; 3823 3824 if (lapic_in_kernel(vcpu) && 3825 test_bit(KVM_APIC_INIT, &apic->pending_events)) { 3826 if (block_nested_events) 3827 return -EBUSY; 3828 nested_vmx_update_pending_dbg(vcpu); 3829 clear_bit(KVM_APIC_INIT, &apic->pending_events); 3830 if (vcpu->arch.mp_state != KVM_MP_STATE_INIT_RECEIVED) 3831 nested_vmx_vmexit(vcpu, EXIT_REASON_INIT_SIGNAL, 0, 0); 3832 return 0; 3833 } 3834 3835 if (lapic_in_kernel(vcpu) && 3836 test_bit(KVM_APIC_SIPI, &apic->pending_events)) { 3837 if (block_nested_events) 3838 return -EBUSY; 3839 3840 clear_bit(KVM_APIC_SIPI, &apic->pending_events); 3841 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3842 nested_vmx_vmexit(vcpu, EXIT_REASON_SIPI_SIGNAL, 0, 3843 apic->sipi_vector & 0xFFUL); 3844 return 0; 3845 } 3846 3847 /* 3848 * Process any exceptions that are not debug traps before MTF. 3849 */ 3850 if (vcpu->arch.exception.pending && !vmx_pending_dbg_trap(vcpu)) { 3851 if (block_nested_events) 3852 return -EBUSY; 3853 if (!nested_vmx_check_exception(vcpu, &exit_qual)) 3854 goto no_vmexit; 3855 nested_vmx_inject_exception_vmexit(vcpu, exit_qual); 3856 return 0; 3857 } 3858 3859 if (mtf_pending) { 3860 if (block_nested_events) 3861 return -EBUSY; 3862 nested_vmx_update_pending_dbg(vcpu); 3863 nested_vmx_vmexit(vcpu, EXIT_REASON_MONITOR_TRAP_FLAG, 0, 0); 3864 return 0; 3865 } 3866 3867 if (vcpu->arch.exception.pending) { 3868 if (block_nested_events) 3869 return -EBUSY; 3870 if (!nested_vmx_check_exception(vcpu, &exit_qual)) 3871 goto no_vmexit; 3872 nested_vmx_inject_exception_vmexit(vcpu, exit_qual); 3873 return 0; 3874 } 3875 3876 if (nested_vmx_preemption_timer_pending(vcpu)) { 3877 if (block_nested_events) 3878 return -EBUSY; 3879 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); 3880 return 0; 3881 } 3882 3883 if (vcpu->arch.smi_pending && !is_smm(vcpu)) { 3884 if (block_nested_events) 3885 return -EBUSY; 3886 goto no_vmexit; 3887 } 3888 3889 if (vcpu->arch.nmi_pending && !vmx_nmi_blocked(vcpu)) { 3890 if (block_nested_events) 3891 return -EBUSY; 3892 if (!nested_exit_on_nmi(vcpu)) 3893 goto no_vmexit; 3894 3895 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, 3896 NMI_VECTOR | INTR_TYPE_NMI_INTR | 3897 INTR_INFO_VALID_MASK, 0); 3898 /* 3899 * The NMI-triggered VM exit counts as injection: 3900 * clear this one and block further NMIs. 3901 */ 3902 vcpu->arch.nmi_pending = 0; 3903 vmx_set_nmi_mask(vcpu, true); 3904 return 0; 3905 } 3906 3907 if (kvm_cpu_has_interrupt(vcpu) && !vmx_interrupt_blocked(vcpu)) { 3908 if (block_nested_events) 3909 return -EBUSY; 3910 if (!nested_exit_on_intr(vcpu)) 3911 goto no_vmexit; 3912 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); 3913 return 0; 3914 } 3915 3916 no_vmexit: 3917 vmx_complete_nested_posted_interrupt(vcpu); 3918 return 0; 3919 } 3920 3921 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) 3922 { 3923 ktime_t remaining = 3924 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); 3925 u64 value; 3926 3927 if (ktime_to_ns(remaining) <= 0) 3928 return 0; 3929 3930 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; 3931 do_div(value, 1000000); 3932 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; 3933 } 3934 3935 static bool is_vmcs12_ext_field(unsigned long field) 3936 { 3937 switch (field) { 3938 case GUEST_ES_SELECTOR: 3939 case GUEST_CS_SELECTOR: 3940 case GUEST_SS_SELECTOR: 3941 case GUEST_DS_SELECTOR: 3942 case GUEST_FS_SELECTOR: 3943 case GUEST_GS_SELECTOR: 3944 case GUEST_LDTR_SELECTOR: 3945 case GUEST_TR_SELECTOR: 3946 case GUEST_ES_LIMIT: 3947 case GUEST_CS_LIMIT: 3948 case GUEST_SS_LIMIT: 3949 case GUEST_DS_LIMIT: 3950 case GUEST_FS_LIMIT: 3951 case GUEST_GS_LIMIT: 3952 case GUEST_LDTR_LIMIT: 3953 case GUEST_TR_LIMIT: 3954 case GUEST_GDTR_LIMIT: 3955 case GUEST_IDTR_LIMIT: 3956 case GUEST_ES_AR_BYTES: 3957 case GUEST_DS_AR_BYTES: 3958 case GUEST_FS_AR_BYTES: 3959 case GUEST_GS_AR_BYTES: 3960 case GUEST_LDTR_AR_BYTES: 3961 case GUEST_TR_AR_BYTES: 3962 case GUEST_ES_BASE: 3963 case GUEST_CS_BASE: 3964 case GUEST_SS_BASE: 3965 case GUEST_DS_BASE: 3966 case GUEST_FS_BASE: 3967 case GUEST_GS_BASE: 3968 case GUEST_LDTR_BASE: 3969 case GUEST_TR_BASE: 3970 case GUEST_GDTR_BASE: 3971 case GUEST_IDTR_BASE: 3972 case GUEST_PENDING_DBG_EXCEPTIONS: 3973 case GUEST_BNDCFGS: 3974 return true; 3975 default: 3976 break; 3977 } 3978 3979 return false; 3980 } 3981 3982 static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu, 3983 struct vmcs12 *vmcs12) 3984 { 3985 struct vcpu_vmx *vmx = to_vmx(vcpu); 3986 3987 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); 3988 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); 3989 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); 3990 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); 3991 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); 3992 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); 3993 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); 3994 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); 3995 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); 3996 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); 3997 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); 3998 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); 3999 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); 4000 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); 4001 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); 4002 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); 4003 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); 4004 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); 4005 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); 4006 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); 4007 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); 4008 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); 4009 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); 4010 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); 4011 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); 4012 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); 4013 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); 4014 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); 4015 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); 4016 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); 4017 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); 4018 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); 4019 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); 4020 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); 4021 vmcs12->guest_pending_dbg_exceptions = 4022 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); 4023 if (kvm_mpx_supported()) 4024 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); 4025 4026 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false; 4027 } 4028 4029 static void copy_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu, 4030 struct vmcs12 *vmcs12) 4031 { 4032 struct vcpu_vmx *vmx = to_vmx(vcpu); 4033 int cpu; 4034 4035 if (!vmx->nested.need_sync_vmcs02_to_vmcs12_rare) 4036 return; 4037 4038 4039 WARN_ON_ONCE(vmx->loaded_vmcs != &vmx->vmcs01); 4040 4041 cpu = get_cpu(); 4042 vmx->loaded_vmcs = &vmx->nested.vmcs02; 4043 vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->vmcs01); 4044 4045 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 4046 4047 vmx->loaded_vmcs = &vmx->vmcs01; 4048 vmx_vcpu_load_vmcs(vcpu, cpu, &vmx->nested.vmcs02); 4049 put_cpu(); 4050 } 4051 4052 /* 4053 * Update the guest state fields of vmcs12 to reflect changes that 4054 * occurred while L2 was running. (The "IA-32e mode guest" bit of the 4055 * VM-entry controls is also updated, since this is really a guest 4056 * state bit.) 4057 */ 4058 static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) 4059 { 4060 struct vcpu_vmx *vmx = to_vmx(vcpu); 4061 4062 if (vmx->nested.hv_evmcs) 4063 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 4064 4065 vmx->nested.need_sync_vmcs02_to_vmcs12_rare = !vmx->nested.hv_evmcs; 4066 4067 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); 4068 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); 4069 4070 vmcs12->guest_rsp = kvm_rsp_read(vcpu); 4071 vmcs12->guest_rip = kvm_rip_read(vcpu); 4072 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); 4073 4074 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); 4075 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); 4076 4077 vmcs12->guest_interruptibility_info = 4078 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 4079 4080 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 4081 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; 4082 else if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4083 vmcs12->guest_activity_state = GUEST_ACTIVITY_WAIT_SIPI; 4084 else 4085 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; 4086 4087 if (nested_cpu_has_preemption_timer(vmcs12) && 4088 vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER && 4089 !vmx->nested.nested_run_pending) 4090 vmcs12->vmx_preemption_timer_value = 4091 vmx_get_preemption_timer_value(vcpu); 4092 4093 /* 4094 * In some cases (usually, nested EPT), L2 is allowed to change its 4095 * own CR3 without exiting. If it has changed it, we must keep it. 4096 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined 4097 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. 4098 * 4099 * Additionally, restore L2's PDPTR to vmcs12. 4100 */ 4101 if (enable_ept) { 4102 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); 4103 if (nested_cpu_has_ept(vmcs12) && is_pae_paging(vcpu)) { 4104 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); 4105 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); 4106 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); 4107 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); 4108 } 4109 } 4110 4111 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); 4112 4113 if (nested_cpu_has_vid(vmcs12)) 4114 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); 4115 4116 vmcs12->vm_entry_controls = 4117 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | 4118 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); 4119 4120 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) 4121 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); 4122 4123 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) 4124 vmcs12->guest_ia32_efer = vcpu->arch.efer; 4125 } 4126 4127 /* 4128 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits 4129 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), 4130 * and this function updates it to reflect the changes to the guest state while 4131 * L2 was running (and perhaps made some exits which were handled directly by L0 4132 * without going back to L1), and to reflect the exit reason. 4133 * Note that we do not have to copy here all VMCS fields, just those that 4134 * could have changed by the L2 guest or the exit - i.e., the guest-state and 4135 * exit-information fields only. Other fields are modified by L1 with VMWRITE, 4136 * which already writes to vmcs12 directly. 4137 */ 4138 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, 4139 u32 vm_exit_reason, u32 exit_intr_info, 4140 unsigned long exit_qualification) 4141 { 4142 /* update exit information fields: */ 4143 vmcs12->vm_exit_reason = vm_exit_reason; 4144 vmcs12->exit_qualification = exit_qualification; 4145 vmcs12->vm_exit_intr_info = exit_intr_info; 4146 4147 vmcs12->idt_vectoring_info_field = 0; 4148 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4149 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 4150 4151 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { 4152 vmcs12->launch_state = 1; 4153 4154 /* vm_entry_intr_info_field is cleared on exit. Emulate this 4155 * instead of reading the real value. */ 4156 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; 4157 4158 /* 4159 * Transfer the event that L0 or L1 may wanted to inject into 4160 * L2 to IDT_VECTORING_INFO_FIELD. 4161 */ 4162 vmcs12_save_pending_event(vcpu, vmcs12); 4163 4164 /* 4165 * According to spec, there's no need to store the guest's 4166 * MSRs if the exit is due to a VM-entry failure that occurs 4167 * during or after loading the guest state. Since this exit 4168 * does not fall in that category, we need to save the MSRs. 4169 */ 4170 if (nested_vmx_store_msr(vcpu, 4171 vmcs12->vm_exit_msr_store_addr, 4172 vmcs12->vm_exit_msr_store_count)) 4173 nested_vmx_abort(vcpu, 4174 VMX_ABORT_SAVE_GUEST_MSR_FAIL); 4175 } 4176 4177 /* 4178 * Drop what we picked up for L2 via vmx_complete_interrupts. It is 4179 * preserved above and would only end up incorrectly in L1. 4180 */ 4181 vcpu->arch.nmi_injected = false; 4182 kvm_clear_exception_queue(vcpu); 4183 kvm_clear_interrupt_queue(vcpu); 4184 } 4185 4186 /* 4187 * A part of what we need to when the nested L2 guest exits and we want to 4188 * run its L1 parent, is to reset L1's guest state to the host state specified 4189 * in vmcs12. 4190 * This function is to be called not only on normal nested exit, but also on 4191 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry 4192 * Failures During or After Loading Guest State"). 4193 * This function should be called when the active VMCS is L1's (vmcs01). 4194 */ 4195 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, 4196 struct vmcs12 *vmcs12) 4197 { 4198 enum vm_entry_failure_code ignored; 4199 struct kvm_segment seg; 4200 4201 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) 4202 vcpu->arch.efer = vmcs12->host_ia32_efer; 4203 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) 4204 vcpu->arch.efer |= (EFER_LMA | EFER_LME); 4205 else 4206 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); 4207 vmx_set_efer(vcpu, vcpu->arch.efer); 4208 4209 kvm_rsp_write(vcpu, vmcs12->host_rsp); 4210 kvm_rip_write(vcpu, vmcs12->host_rip); 4211 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); 4212 vmx_set_interrupt_shadow(vcpu, 0); 4213 4214 /* 4215 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't 4216 * actually changed, because vmx_set_cr0 refers to efer set above. 4217 * 4218 * CR0_GUEST_HOST_MASK is already set in the original vmcs01 4219 * (KVM doesn't change it); 4220 */ 4221 vcpu->arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS; 4222 vmx_set_cr0(vcpu, vmcs12->host_cr0); 4223 4224 /* Same as above - no reason to call set_cr4_guest_host_mask(). */ 4225 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); 4226 vmx_set_cr4(vcpu, vmcs12->host_cr4); 4227 4228 nested_ept_uninit_mmu_context(vcpu); 4229 4230 /* 4231 * Only PDPTE load can fail as the value of cr3 was checked on entry and 4232 * couldn't have changed. 4233 */ 4234 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &ignored)) 4235 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); 4236 4237 if (!enable_ept) 4238 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; 4239 4240 nested_vmx_transition_tlb_flush(vcpu, vmcs12, false); 4241 4242 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); 4243 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); 4244 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); 4245 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); 4246 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); 4247 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF); 4248 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF); 4249 4250 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ 4251 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) 4252 vmcs_write64(GUEST_BNDCFGS, 0); 4253 4254 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { 4255 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); 4256 vcpu->arch.pat = vmcs12->host_ia32_pat; 4257 } 4258 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 4259 WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, 4260 vmcs12->host_ia32_perf_global_ctrl)); 4261 4262 /* Set L1 segment info according to Intel SDM 4263 27.5.2 Loading Host Segment and Descriptor-Table Registers */ 4264 seg = (struct kvm_segment) { 4265 .base = 0, 4266 .limit = 0xFFFFFFFF, 4267 .selector = vmcs12->host_cs_selector, 4268 .type = 11, 4269 .present = 1, 4270 .s = 1, 4271 .g = 1 4272 }; 4273 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) 4274 seg.l = 1; 4275 else 4276 seg.db = 1; 4277 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); 4278 seg = (struct kvm_segment) { 4279 .base = 0, 4280 .limit = 0xFFFFFFFF, 4281 .type = 3, 4282 .present = 1, 4283 .s = 1, 4284 .db = 1, 4285 .g = 1 4286 }; 4287 seg.selector = vmcs12->host_ds_selector; 4288 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); 4289 seg.selector = vmcs12->host_es_selector; 4290 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); 4291 seg.selector = vmcs12->host_ss_selector; 4292 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); 4293 seg.selector = vmcs12->host_fs_selector; 4294 seg.base = vmcs12->host_fs_base; 4295 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); 4296 seg.selector = vmcs12->host_gs_selector; 4297 seg.base = vmcs12->host_gs_base; 4298 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); 4299 seg = (struct kvm_segment) { 4300 .base = vmcs12->host_tr_base, 4301 .limit = 0x67, 4302 .selector = vmcs12->host_tr_selector, 4303 .type = 11, 4304 .present = 1 4305 }; 4306 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); 4307 4308 kvm_set_dr(vcpu, 7, 0x400); 4309 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4310 4311 if (cpu_has_vmx_msr_bitmap()) 4312 vmx_update_msr_bitmap(vcpu); 4313 4314 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, 4315 vmcs12->vm_exit_msr_load_count)) 4316 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); 4317 } 4318 4319 static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx) 4320 { 4321 struct vmx_uret_msr *efer_msr; 4322 unsigned int i; 4323 4324 if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER) 4325 return vmcs_read64(GUEST_IA32_EFER); 4326 4327 if (cpu_has_load_ia32_efer()) 4328 return host_efer; 4329 4330 for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) { 4331 if (vmx->msr_autoload.guest.val[i].index == MSR_EFER) 4332 return vmx->msr_autoload.guest.val[i].value; 4333 } 4334 4335 efer_msr = vmx_find_uret_msr(vmx, MSR_EFER); 4336 if (efer_msr) 4337 return efer_msr->data; 4338 4339 return host_efer; 4340 } 4341 4342 static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu) 4343 { 4344 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4345 struct vcpu_vmx *vmx = to_vmx(vcpu); 4346 struct vmx_msr_entry g, h; 4347 gpa_t gpa; 4348 u32 i, j; 4349 4350 vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT); 4351 4352 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { 4353 /* 4354 * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set 4355 * as vmcs01.GUEST_DR7 contains a userspace defined value 4356 * and vcpu->arch.dr7 is not squirreled away before the 4357 * nested VMENTER (not worth adding a variable in nested_vmx). 4358 */ 4359 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 4360 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 4361 else 4362 WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7))); 4363 } 4364 4365 /* 4366 * Note that calling vmx_set_{efer,cr0,cr4} is important as they 4367 * handle a variety of side effects to KVM's software model. 4368 */ 4369 vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx)); 4370 4371 vcpu->arch.cr0_guest_owned_bits = KVM_POSSIBLE_CR0_GUEST_BITS; 4372 vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW)); 4373 4374 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); 4375 vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW)); 4376 4377 nested_ept_uninit_mmu_context(vcpu); 4378 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 4379 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 4380 4381 /* 4382 * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs 4383 * from vmcs01 (if necessary). The PDPTRs are not loaded on 4384 * VMFail, like everything else we just need to ensure our 4385 * software model is up-to-date. 4386 */ 4387 if (enable_ept && is_pae_paging(vcpu)) 4388 ept_save_pdptrs(vcpu); 4389 4390 kvm_mmu_reset_context(vcpu); 4391 4392 if (cpu_has_vmx_msr_bitmap()) 4393 vmx_update_msr_bitmap(vcpu); 4394 4395 /* 4396 * This nasty bit of open coding is a compromise between blindly 4397 * loading L1's MSRs using the exit load lists (incorrect emulation 4398 * of VMFail), leaving the nested VM's MSRs in the software model 4399 * (incorrect behavior) and snapshotting the modified MSRs (too 4400 * expensive since the lists are unbound by hardware). For each 4401 * MSR that was (prematurely) loaded from the nested VMEntry load 4402 * list, reload it from the exit load list if it exists and differs 4403 * from the guest value. The intent is to stuff host state as 4404 * silently as possible, not to fully process the exit load list. 4405 */ 4406 for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) { 4407 gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g)); 4408 if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) { 4409 pr_debug_ratelimited( 4410 "%s read MSR index failed (%u, 0x%08llx)\n", 4411 __func__, i, gpa); 4412 goto vmabort; 4413 } 4414 4415 for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) { 4416 gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h)); 4417 if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) { 4418 pr_debug_ratelimited( 4419 "%s read MSR failed (%u, 0x%08llx)\n", 4420 __func__, j, gpa); 4421 goto vmabort; 4422 } 4423 if (h.index != g.index) 4424 continue; 4425 if (h.value == g.value) 4426 break; 4427 4428 if (nested_vmx_load_msr_check(vcpu, &h)) { 4429 pr_debug_ratelimited( 4430 "%s check failed (%u, 0x%x, 0x%x)\n", 4431 __func__, j, h.index, h.reserved); 4432 goto vmabort; 4433 } 4434 4435 if (kvm_set_msr(vcpu, h.index, h.value)) { 4436 pr_debug_ratelimited( 4437 "%s WRMSR failed (%u, 0x%x, 0x%llx)\n", 4438 __func__, j, h.index, h.value); 4439 goto vmabort; 4440 } 4441 } 4442 } 4443 4444 return; 4445 4446 vmabort: 4447 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); 4448 } 4449 4450 /* 4451 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 4452 * and modify vmcs12 to make it see what it would expect to see there if 4453 * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) 4454 */ 4455 void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, 4456 u32 exit_intr_info, unsigned long exit_qualification) 4457 { 4458 struct vcpu_vmx *vmx = to_vmx(vcpu); 4459 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4460 4461 /* trying to cancel vmlaunch/vmresume is a bug */ 4462 WARN_ON_ONCE(vmx->nested.nested_run_pending); 4463 4464 kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 4465 4466 /* Service the TLB flush request for L2 before switching to L1. */ 4467 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 4468 kvm_vcpu_flush_tlb_current(vcpu); 4469 4470 /* 4471 * VCPU_EXREG_PDPTR will be clobbered in arch/x86/kvm/vmx/vmx.h between 4472 * now and the new vmentry. Ensure that the VMCS02 PDPTR fields are 4473 * up-to-date before switching to L1. 4474 */ 4475 if (enable_ept && is_pae_paging(vcpu)) 4476 vmx_ept_load_pdptrs(vcpu); 4477 4478 leave_guest_mode(vcpu); 4479 4480 if (nested_cpu_has_preemption_timer(vmcs12)) 4481 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); 4482 4483 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING) 4484 vcpu->arch.tsc_offset -= vmcs12->tsc_offset; 4485 4486 if (likely(!vmx->fail)) { 4487 sync_vmcs02_to_vmcs12(vcpu, vmcs12); 4488 4489 if (vm_exit_reason != -1) 4490 prepare_vmcs12(vcpu, vmcs12, vm_exit_reason, 4491 exit_intr_info, exit_qualification); 4492 4493 /* 4494 * Must happen outside of sync_vmcs02_to_vmcs12() as it will 4495 * also be used to capture vmcs12 cache as part of 4496 * capturing nVMX state for snapshot (migration). 4497 * 4498 * Otherwise, this flush will dirty guest memory at a 4499 * point it is already assumed by user-space to be 4500 * immutable. 4501 */ 4502 nested_flush_cached_shadow_vmcs12(vcpu, vmcs12); 4503 } else { 4504 /* 4505 * The only expected VM-instruction error is "VM entry with 4506 * invalid control field(s)." Anything else indicates a 4507 * problem with L0. And we should never get here with a 4508 * VMFail of any type if early consistency checks are enabled. 4509 */ 4510 WARN_ON_ONCE(vmcs_read32(VM_INSTRUCTION_ERROR) != 4511 VMXERR_ENTRY_INVALID_CONTROL_FIELD); 4512 WARN_ON_ONCE(nested_early_check); 4513 } 4514 4515 vmx_switch_vmcs(vcpu, &vmx->vmcs01); 4516 4517 /* Update any VMCS fields that might have changed while L2 ran */ 4518 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); 4519 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); 4520 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); 4521 if (vmx->nested.l1_tpr_threshold != -1) 4522 vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold); 4523 4524 if (kvm_has_tsc_control) 4525 decache_tsc_multiplier(vmx); 4526 4527 if (vmx->nested.change_vmcs01_virtual_apic_mode) { 4528 vmx->nested.change_vmcs01_virtual_apic_mode = false; 4529 vmx_set_virtual_apic_mode(vcpu); 4530 } 4531 4532 /* Unpin physical memory we referred to in vmcs02 */ 4533 if (vmx->nested.apic_access_page) { 4534 kvm_release_page_clean(vmx->nested.apic_access_page); 4535 vmx->nested.apic_access_page = NULL; 4536 } 4537 kvm_vcpu_unmap(vcpu, &vmx->nested.virtual_apic_map, true); 4538 kvm_vcpu_unmap(vcpu, &vmx->nested.pi_desc_map, true); 4539 vmx->nested.pi_desc = NULL; 4540 4541 if (vmx->nested.reload_vmcs01_apic_access_page) { 4542 vmx->nested.reload_vmcs01_apic_access_page = false; 4543 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4544 } 4545 4546 if ((vm_exit_reason != -1) && 4547 (enable_shadow_vmcs || vmx->nested.hv_evmcs)) 4548 vmx->nested.need_vmcs12_to_shadow_sync = true; 4549 4550 /* in case we halted in L2 */ 4551 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 4552 4553 if (likely(!vmx->fail)) { 4554 if ((u16)vm_exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && 4555 nested_exit_intr_ack_set(vcpu)) { 4556 int irq = kvm_cpu_get_interrupt(vcpu); 4557 WARN_ON(irq < 0); 4558 vmcs12->vm_exit_intr_info = irq | 4559 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; 4560 } 4561 4562 if (vm_exit_reason != -1) 4563 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, 4564 vmcs12->exit_qualification, 4565 vmcs12->idt_vectoring_info_field, 4566 vmcs12->vm_exit_intr_info, 4567 vmcs12->vm_exit_intr_error_code, 4568 KVM_ISA_VMX); 4569 4570 load_vmcs12_host_state(vcpu, vmcs12); 4571 4572 return; 4573 } 4574 4575 /* 4576 * After an early L2 VM-entry failure, we're now back 4577 * in L1 which thinks it just finished a VMLAUNCH or 4578 * VMRESUME instruction, so we need to set the failure 4579 * flag and the VM-instruction error field of the VMCS 4580 * accordingly, and skip the emulated instruction. 4581 */ 4582 (void)nested_vmx_fail(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); 4583 4584 /* 4585 * Restore L1's host state to KVM's software model. We're here 4586 * because a consistency check was caught by hardware, which 4587 * means some amount of guest state has been propagated to KVM's 4588 * model and needs to be unwound to the host's state. 4589 */ 4590 nested_vmx_restore_host_state(vcpu); 4591 4592 vmx->fail = 0; 4593 } 4594 4595 /* 4596 * Decode the memory-address operand of a vmx instruction, as recorded on an 4597 * exit caused by such an instruction (run by a guest hypervisor). 4598 * On success, returns 0. When the operand is invalid, returns 1 and throws 4599 * #UD, #GP, or #SS. 4600 */ 4601 int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification, 4602 u32 vmx_instruction_info, bool wr, int len, gva_t *ret) 4603 { 4604 gva_t off; 4605 bool exn; 4606 struct kvm_segment s; 4607 4608 /* 4609 * According to Vol. 3B, "Information for VM Exits Due to Instruction 4610 * Execution", on an exit, vmx_instruction_info holds most of the 4611 * addressing components of the operand. Only the displacement part 4612 * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). 4613 * For how an actual address is calculated from all these components, 4614 * refer to Vol. 1, "Operand Addressing". 4615 */ 4616 int scaling = vmx_instruction_info & 3; 4617 int addr_size = (vmx_instruction_info >> 7) & 7; 4618 bool is_reg = vmx_instruction_info & (1u << 10); 4619 int seg_reg = (vmx_instruction_info >> 15) & 7; 4620 int index_reg = (vmx_instruction_info >> 18) & 0xf; 4621 bool index_is_valid = !(vmx_instruction_info & (1u << 22)); 4622 int base_reg = (vmx_instruction_info >> 23) & 0xf; 4623 bool base_is_valid = !(vmx_instruction_info & (1u << 27)); 4624 4625 if (is_reg) { 4626 kvm_queue_exception(vcpu, UD_VECTOR); 4627 return 1; 4628 } 4629 4630 /* Addr = segment_base + offset */ 4631 /* offset = base + [index * scale] + displacement */ 4632 off = exit_qualification; /* holds the displacement */ 4633 if (addr_size == 1) 4634 off = (gva_t)sign_extend64(off, 31); 4635 else if (addr_size == 0) 4636 off = (gva_t)sign_extend64(off, 15); 4637 if (base_is_valid) 4638 off += kvm_register_read(vcpu, base_reg); 4639 if (index_is_valid) 4640 off += kvm_register_read(vcpu, index_reg) << scaling; 4641 vmx_get_segment(vcpu, &s, seg_reg); 4642 4643 /* 4644 * The effective address, i.e. @off, of a memory operand is truncated 4645 * based on the address size of the instruction. Note that this is 4646 * the *effective address*, i.e. the address prior to accounting for 4647 * the segment's base. 4648 */ 4649 if (addr_size == 1) /* 32 bit */ 4650 off &= 0xffffffff; 4651 else if (addr_size == 0) /* 16 bit */ 4652 off &= 0xffff; 4653 4654 /* Checks for #GP/#SS exceptions. */ 4655 exn = false; 4656 if (is_long_mode(vcpu)) { 4657 /* 4658 * The virtual/linear address is never truncated in 64-bit 4659 * mode, e.g. a 32-bit address size can yield a 64-bit virtual 4660 * address when using FS/GS with a non-zero base. 4661 */ 4662 if (seg_reg == VCPU_SREG_FS || seg_reg == VCPU_SREG_GS) 4663 *ret = s.base + off; 4664 else 4665 *ret = off; 4666 4667 /* Long mode: #GP(0)/#SS(0) if the memory address is in a 4668 * non-canonical form. This is the only check on the memory 4669 * destination for long mode! 4670 */ 4671 exn = is_noncanonical_address(*ret, vcpu); 4672 } else { 4673 /* 4674 * When not in long mode, the virtual/linear address is 4675 * unconditionally truncated to 32 bits regardless of the 4676 * address size. 4677 */ 4678 *ret = (s.base + off) & 0xffffffff; 4679 4680 /* Protected mode: apply checks for segment validity in the 4681 * following order: 4682 * - segment type check (#GP(0) may be thrown) 4683 * - usability check (#GP(0)/#SS(0)) 4684 * - limit check (#GP(0)/#SS(0)) 4685 */ 4686 if (wr) 4687 /* #GP(0) if the destination operand is located in a 4688 * read-only data segment or any code segment. 4689 */ 4690 exn = ((s.type & 0xa) == 0 || (s.type & 8)); 4691 else 4692 /* #GP(0) if the source operand is located in an 4693 * execute-only code segment 4694 */ 4695 exn = ((s.type & 0xa) == 8); 4696 if (exn) { 4697 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 4698 return 1; 4699 } 4700 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. 4701 */ 4702 exn = (s.unusable != 0); 4703 4704 /* 4705 * Protected mode: #GP(0)/#SS(0) if the memory operand is 4706 * outside the segment limit. All CPUs that support VMX ignore 4707 * limit checks for flat segments, i.e. segments with base==0, 4708 * limit==0xffffffff and of type expand-up data or code. 4709 */ 4710 if (!(s.base == 0 && s.limit == 0xffffffff && 4711 ((s.type & 8) || !(s.type & 4)))) 4712 exn = exn || ((u64)off + len - 1 > s.limit); 4713 } 4714 if (exn) { 4715 kvm_queue_exception_e(vcpu, 4716 seg_reg == VCPU_SREG_SS ? 4717 SS_VECTOR : GP_VECTOR, 4718 0); 4719 return 1; 4720 } 4721 4722 return 0; 4723 } 4724 4725 void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 4726 { 4727 struct vcpu_vmx *vmx; 4728 4729 if (!nested_vmx_allowed(vcpu)) 4730 return; 4731 4732 vmx = to_vmx(vcpu); 4733 if (kvm_x86_ops.pmu_ops->is_valid_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL)) { 4734 vmx->nested.msrs.entry_ctls_high |= 4735 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 4736 vmx->nested.msrs.exit_ctls_high |= 4737 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 4738 } else { 4739 vmx->nested.msrs.entry_ctls_high &= 4740 ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 4741 vmx->nested.msrs.exit_ctls_high &= 4742 ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 4743 } 4744 } 4745 4746 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer, 4747 int *ret) 4748 { 4749 gva_t gva; 4750 struct x86_exception e; 4751 int r; 4752 4753 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), 4754 vmcs_read32(VMX_INSTRUCTION_INFO), false, 4755 sizeof(*vmpointer), &gva)) { 4756 *ret = 1; 4757 return -EINVAL; 4758 } 4759 4760 r = kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e); 4761 if (r != X86EMUL_CONTINUE) { 4762 *ret = kvm_handle_memory_failure(vcpu, r, &e); 4763 return -EINVAL; 4764 } 4765 4766 return 0; 4767 } 4768 4769 /* 4770 * Allocate a shadow VMCS and associate it with the currently loaded 4771 * VMCS, unless such a shadow VMCS already exists. The newly allocated 4772 * VMCS is also VMCLEARed, so that it is ready for use. 4773 */ 4774 static struct vmcs *alloc_shadow_vmcs(struct kvm_vcpu *vcpu) 4775 { 4776 struct vcpu_vmx *vmx = to_vmx(vcpu); 4777 struct loaded_vmcs *loaded_vmcs = vmx->loaded_vmcs; 4778 4779 /* 4780 * We should allocate a shadow vmcs for vmcs01 only when L1 4781 * executes VMXON and free it when L1 executes VMXOFF. 4782 * As it is invalid to execute VMXON twice, we shouldn't reach 4783 * here when vmcs01 already have an allocated shadow vmcs. 4784 */ 4785 WARN_ON(loaded_vmcs == &vmx->vmcs01 && loaded_vmcs->shadow_vmcs); 4786 4787 if (!loaded_vmcs->shadow_vmcs) { 4788 loaded_vmcs->shadow_vmcs = alloc_vmcs(true); 4789 if (loaded_vmcs->shadow_vmcs) 4790 vmcs_clear(loaded_vmcs->shadow_vmcs); 4791 } 4792 return loaded_vmcs->shadow_vmcs; 4793 } 4794 4795 static int enter_vmx_operation(struct kvm_vcpu *vcpu) 4796 { 4797 struct vcpu_vmx *vmx = to_vmx(vcpu); 4798 int r; 4799 4800 r = alloc_loaded_vmcs(&vmx->nested.vmcs02); 4801 if (r < 0) 4802 goto out_vmcs02; 4803 4804 vmx->nested.cached_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT); 4805 if (!vmx->nested.cached_vmcs12) 4806 goto out_cached_vmcs12; 4807 4808 vmx->nested.cached_shadow_vmcs12 = kzalloc(VMCS12_SIZE, GFP_KERNEL_ACCOUNT); 4809 if (!vmx->nested.cached_shadow_vmcs12) 4810 goto out_cached_shadow_vmcs12; 4811 4812 if (enable_shadow_vmcs && !alloc_shadow_vmcs(vcpu)) 4813 goto out_shadow_vmcs; 4814 4815 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, 4816 HRTIMER_MODE_ABS_PINNED); 4817 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; 4818 4819 vmx->nested.vpid02 = allocate_vpid(); 4820 4821 vmx->nested.vmcs02_initialized = false; 4822 vmx->nested.vmxon = true; 4823 4824 if (vmx_pt_mode_is_host_guest()) { 4825 vmx->pt_desc.guest.ctl = 0; 4826 pt_update_intercept_for_msr(vcpu); 4827 } 4828 4829 return 0; 4830 4831 out_shadow_vmcs: 4832 kfree(vmx->nested.cached_shadow_vmcs12); 4833 4834 out_cached_shadow_vmcs12: 4835 kfree(vmx->nested.cached_vmcs12); 4836 4837 out_cached_vmcs12: 4838 free_loaded_vmcs(&vmx->nested.vmcs02); 4839 4840 out_vmcs02: 4841 return -ENOMEM; 4842 } 4843 4844 /* 4845 * Emulate the VMXON instruction. 4846 * Currently, we just remember that VMX is active, and do not save or even 4847 * inspect the argument to VMXON (the so-called "VMXON pointer") because we 4848 * do not currently need to store anything in that guest-allocated memory 4849 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their 4850 * argument is different from the VMXON pointer (which the spec says they do). 4851 */ 4852 static int handle_vmon(struct kvm_vcpu *vcpu) 4853 { 4854 int ret; 4855 gpa_t vmptr; 4856 uint32_t revision; 4857 struct vcpu_vmx *vmx = to_vmx(vcpu); 4858 const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED 4859 | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 4860 4861 /* 4862 * The Intel VMX Instruction Reference lists a bunch of bits that are 4863 * prerequisite to running VMXON, most notably cr4.VMXE must be set to 4864 * 1 (see vmx_is_valid_cr4() for when we allow the guest to set this). 4865 * Otherwise, we should fail with #UD. But most faulting conditions 4866 * have already been checked by hardware, prior to the VM-exit for 4867 * VMXON. We do test guest cr4.VMXE because processor CR4 always has 4868 * that bit set to 1 in non-root mode. 4869 */ 4870 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { 4871 kvm_queue_exception(vcpu, UD_VECTOR); 4872 return 1; 4873 } 4874 4875 /* CPL=0 must be checked manually. */ 4876 if (vmx_get_cpl(vcpu)) { 4877 kvm_inject_gp(vcpu, 0); 4878 return 1; 4879 } 4880 4881 if (vmx->nested.vmxon) 4882 return nested_vmx_fail(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); 4883 4884 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) 4885 != VMXON_NEEDED_FEATURES) { 4886 kvm_inject_gp(vcpu, 0); 4887 return 1; 4888 } 4889 4890 if (nested_vmx_get_vmptr(vcpu, &vmptr, &ret)) 4891 return ret; 4892 4893 /* 4894 * SDM 3: 24.11.5 4895 * The first 4 bytes of VMXON region contain the supported 4896 * VMCS revision identifier 4897 * 4898 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; 4899 * which replaces physical address width with 32 4900 */ 4901 if (!page_address_valid(vcpu, vmptr)) 4902 return nested_vmx_failInvalid(vcpu); 4903 4904 if (kvm_read_guest(vcpu->kvm, vmptr, &revision, sizeof(revision)) || 4905 revision != VMCS12_REVISION) 4906 return nested_vmx_failInvalid(vcpu); 4907 4908 vmx->nested.vmxon_ptr = vmptr; 4909 ret = enter_vmx_operation(vcpu); 4910 if (ret) 4911 return ret; 4912 4913 return nested_vmx_succeed(vcpu); 4914 } 4915 4916 static inline void nested_release_vmcs12(struct kvm_vcpu *vcpu) 4917 { 4918 struct vcpu_vmx *vmx = to_vmx(vcpu); 4919 4920 if (vmx->nested.current_vmptr == -1ull) 4921 return; 4922 4923 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu)); 4924 4925 if (enable_shadow_vmcs) { 4926 /* copy to memory all shadowed fields in case 4927 they were modified */ 4928 copy_shadow_to_vmcs12(vmx); 4929 vmx_disable_shadow_vmcs(vmx); 4930 } 4931 vmx->nested.posted_intr_nv = -1; 4932 4933 /* Flush VMCS12 to guest memory */ 4934 kvm_vcpu_write_guest_page(vcpu, 4935 vmx->nested.current_vmptr >> PAGE_SHIFT, 4936 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); 4937 4938 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); 4939 4940 vmx->nested.current_vmptr = -1ull; 4941 } 4942 4943 /* Emulate the VMXOFF instruction */ 4944 static int handle_vmoff(struct kvm_vcpu *vcpu) 4945 { 4946 if (!nested_vmx_check_permission(vcpu)) 4947 return 1; 4948 4949 free_nested(vcpu); 4950 4951 /* Process a latched INIT during time CPU was in VMX operation */ 4952 kvm_make_request(KVM_REQ_EVENT, vcpu); 4953 4954 return nested_vmx_succeed(vcpu); 4955 } 4956 4957 /* Emulate the VMCLEAR instruction */ 4958 static int handle_vmclear(struct kvm_vcpu *vcpu) 4959 { 4960 struct vcpu_vmx *vmx = to_vmx(vcpu); 4961 u32 zero = 0; 4962 gpa_t vmptr; 4963 u64 evmcs_gpa; 4964 int r; 4965 4966 if (!nested_vmx_check_permission(vcpu)) 4967 return 1; 4968 4969 if (nested_vmx_get_vmptr(vcpu, &vmptr, &r)) 4970 return r; 4971 4972 if (!page_address_valid(vcpu, vmptr)) 4973 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); 4974 4975 if (vmptr == vmx->nested.vmxon_ptr) 4976 return nested_vmx_fail(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); 4977 4978 /* 4979 * When Enlightened VMEntry is enabled on the calling CPU we treat 4980 * memory area pointer by vmptr as Enlightened VMCS (as there's no good 4981 * way to distinguish it from VMCS12) and we must not corrupt it by 4982 * writing to the non-existent 'launch_state' field. The area doesn't 4983 * have to be the currently active EVMCS on the calling CPU and there's 4984 * nothing KVM has to do to transition it from 'active' to 'non-active' 4985 * state. It is possible that the area will stay mapped as 4986 * vmx->nested.hv_evmcs but this shouldn't be a problem. 4987 */ 4988 if (likely(!vmx->nested.enlightened_vmcs_enabled || 4989 !nested_enlightened_vmentry(vcpu, &evmcs_gpa))) { 4990 if (vmptr == vmx->nested.current_vmptr) 4991 nested_release_vmcs12(vcpu); 4992 4993 kvm_vcpu_write_guest(vcpu, 4994 vmptr + offsetof(struct vmcs12, 4995 launch_state), 4996 &zero, sizeof(zero)); 4997 } 4998 4999 return nested_vmx_succeed(vcpu); 5000 } 5001 5002 /* Emulate the VMLAUNCH instruction */ 5003 static int handle_vmlaunch(struct kvm_vcpu *vcpu) 5004 { 5005 return nested_vmx_run(vcpu, true); 5006 } 5007 5008 /* Emulate the VMRESUME instruction */ 5009 static int handle_vmresume(struct kvm_vcpu *vcpu) 5010 { 5011 5012 return nested_vmx_run(vcpu, false); 5013 } 5014 5015 static int handle_vmread(struct kvm_vcpu *vcpu) 5016 { 5017 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu) 5018 : get_vmcs12(vcpu); 5019 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5020 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5021 struct vcpu_vmx *vmx = to_vmx(vcpu); 5022 struct x86_exception e; 5023 unsigned long field; 5024 u64 value; 5025 gva_t gva = 0; 5026 short offset; 5027 int len, r; 5028 5029 if (!nested_vmx_check_permission(vcpu)) 5030 return 1; 5031 5032 /* 5033 * In VMX non-root operation, when the VMCS-link pointer is -1ull, 5034 * any VMREAD sets the ALU flags for VMfailInvalid. 5035 */ 5036 if (vmx->nested.current_vmptr == -1ull || 5037 (is_guest_mode(vcpu) && 5038 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull)) 5039 return nested_vmx_failInvalid(vcpu); 5040 5041 /* Decode instruction info and find the field to read */ 5042 field = kvm_register_readl(vcpu, (((instr_info) >> 28) & 0xf)); 5043 5044 offset = vmcs_field_to_offset(field); 5045 if (offset < 0) 5046 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5047 5048 if (!is_guest_mode(vcpu) && is_vmcs12_ext_field(field)) 5049 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 5050 5051 /* Read the field, zero-extended to a u64 value */ 5052 value = vmcs12_read_any(vmcs12, field, offset); 5053 5054 /* 5055 * Now copy part of this value to register or memory, as requested. 5056 * Note that the number of bits actually copied is 32 or 64 depending 5057 * on the guest's mode (32 or 64 bit), not on the given field's length. 5058 */ 5059 if (instr_info & BIT(10)) { 5060 kvm_register_writel(vcpu, (((instr_info) >> 3) & 0xf), value); 5061 } else { 5062 len = is_64_bit_mode(vcpu) ? 8 : 4; 5063 if (get_vmx_mem_address(vcpu, exit_qualification, 5064 instr_info, true, len, &gva)) 5065 return 1; 5066 /* _system ok, nested_vmx_check_permission has verified cpl=0 */ 5067 r = kvm_write_guest_virt_system(vcpu, gva, &value, len, &e); 5068 if (r != X86EMUL_CONTINUE) 5069 return kvm_handle_memory_failure(vcpu, r, &e); 5070 } 5071 5072 return nested_vmx_succeed(vcpu); 5073 } 5074 5075 static bool is_shadow_field_rw(unsigned long field) 5076 { 5077 switch (field) { 5078 #define SHADOW_FIELD_RW(x, y) case x: 5079 #include "vmcs_shadow_fields.h" 5080 return true; 5081 default: 5082 break; 5083 } 5084 return false; 5085 } 5086 5087 static bool is_shadow_field_ro(unsigned long field) 5088 { 5089 switch (field) { 5090 #define SHADOW_FIELD_RO(x, y) case x: 5091 #include "vmcs_shadow_fields.h" 5092 return true; 5093 default: 5094 break; 5095 } 5096 return false; 5097 } 5098 5099 static int handle_vmwrite(struct kvm_vcpu *vcpu) 5100 { 5101 struct vmcs12 *vmcs12 = is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu) 5102 : get_vmcs12(vcpu); 5103 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5104 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5105 struct vcpu_vmx *vmx = to_vmx(vcpu); 5106 struct x86_exception e; 5107 unsigned long field; 5108 short offset; 5109 gva_t gva; 5110 int len, r; 5111 5112 /* 5113 * The value to write might be 32 or 64 bits, depending on L1's long 5114 * mode, and eventually we need to write that into a field of several 5115 * possible lengths. The code below first zero-extends the value to 64 5116 * bit (value), and then copies only the appropriate number of 5117 * bits into the vmcs12 field. 5118 */ 5119 u64 value = 0; 5120 5121 if (!nested_vmx_check_permission(vcpu)) 5122 return 1; 5123 5124 /* 5125 * In VMX non-root operation, when the VMCS-link pointer is -1ull, 5126 * any VMWRITE sets the ALU flags for VMfailInvalid. 5127 */ 5128 if (vmx->nested.current_vmptr == -1ull || 5129 (is_guest_mode(vcpu) && 5130 get_vmcs12(vcpu)->vmcs_link_pointer == -1ull)) 5131 return nested_vmx_failInvalid(vcpu); 5132 5133 if (instr_info & BIT(10)) 5134 value = kvm_register_readl(vcpu, (((instr_info) >> 3) & 0xf)); 5135 else { 5136 len = is_64_bit_mode(vcpu) ? 8 : 4; 5137 if (get_vmx_mem_address(vcpu, exit_qualification, 5138 instr_info, false, len, &gva)) 5139 return 1; 5140 r = kvm_read_guest_virt(vcpu, gva, &value, len, &e); 5141 if (r != X86EMUL_CONTINUE) 5142 return kvm_handle_memory_failure(vcpu, r, &e); 5143 } 5144 5145 field = kvm_register_readl(vcpu, (((instr_info) >> 28) & 0xf)); 5146 5147 offset = vmcs_field_to_offset(field); 5148 if (offset < 0) 5149 return nested_vmx_fail(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5150 5151 /* 5152 * If the vCPU supports "VMWRITE to any supported field in the 5153 * VMCS," then the "read-only" fields are actually read/write. 5154 */ 5155 if (vmcs_field_readonly(field) && 5156 !nested_cpu_has_vmwrite_any_field(vcpu)) 5157 return nested_vmx_fail(vcpu, VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); 5158 5159 /* 5160 * Ensure vmcs12 is up-to-date before any VMWRITE that dirties 5161 * vmcs12, else we may crush a field or consume a stale value. 5162 */ 5163 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) 5164 copy_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 5165 5166 /* 5167 * Some Intel CPUs intentionally drop the reserved bits of the AR byte 5168 * fields on VMWRITE. Emulate this behavior to ensure consistent KVM 5169 * behavior regardless of the underlying hardware, e.g. if an AR_BYTE 5170 * field is intercepted for VMWRITE but not VMREAD (in L1), then VMREAD 5171 * from L1 will return a different value than VMREAD from L2 (L1 sees 5172 * the stripped down value, L2 sees the full value as stored by KVM). 5173 */ 5174 if (field >= GUEST_ES_AR_BYTES && field <= GUEST_TR_AR_BYTES) 5175 value &= 0x1f0ff; 5176 5177 vmcs12_write_any(vmcs12, field, offset, value); 5178 5179 /* 5180 * Do not track vmcs12 dirty-state if in guest-mode as we actually 5181 * dirty shadow vmcs12 instead of vmcs12. Fields that can be updated 5182 * by L1 without a vmexit are always updated in the vmcs02, i.e. don't 5183 * "dirty" vmcs12, all others go down the prepare_vmcs02() slow path. 5184 */ 5185 if (!is_guest_mode(vcpu) && !is_shadow_field_rw(field)) { 5186 /* 5187 * L1 can read these fields without exiting, ensure the 5188 * shadow VMCS is up-to-date. 5189 */ 5190 if (enable_shadow_vmcs && is_shadow_field_ro(field)) { 5191 preempt_disable(); 5192 vmcs_load(vmx->vmcs01.shadow_vmcs); 5193 5194 __vmcs_writel(field, value); 5195 5196 vmcs_clear(vmx->vmcs01.shadow_vmcs); 5197 vmcs_load(vmx->loaded_vmcs->vmcs); 5198 preempt_enable(); 5199 } 5200 vmx->nested.dirty_vmcs12 = true; 5201 } 5202 5203 return nested_vmx_succeed(vcpu); 5204 } 5205 5206 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) 5207 { 5208 vmx->nested.current_vmptr = vmptr; 5209 if (enable_shadow_vmcs) { 5210 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_SHADOW_VMCS); 5211 vmcs_write64(VMCS_LINK_POINTER, 5212 __pa(vmx->vmcs01.shadow_vmcs)); 5213 vmx->nested.need_vmcs12_to_shadow_sync = true; 5214 } 5215 vmx->nested.dirty_vmcs12 = true; 5216 } 5217 5218 /* Emulate the VMPTRLD instruction */ 5219 static int handle_vmptrld(struct kvm_vcpu *vcpu) 5220 { 5221 struct vcpu_vmx *vmx = to_vmx(vcpu); 5222 gpa_t vmptr; 5223 int r; 5224 5225 if (!nested_vmx_check_permission(vcpu)) 5226 return 1; 5227 5228 if (nested_vmx_get_vmptr(vcpu, &vmptr, &r)) 5229 return r; 5230 5231 if (!page_address_valid(vcpu, vmptr)) 5232 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); 5233 5234 if (vmptr == vmx->nested.vmxon_ptr) 5235 return nested_vmx_fail(vcpu, VMXERR_VMPTRLD_VMXON_POINTER); 5236 5237 /* Forbid normal VMPTRLD if Enlightened version was used */ 5238 if (vmx->nested.hv_evmcs) 5239 return 1; 5240 5241 if (vmx->nested.current_vmptr != vmptr) { 5242 struct kvm_host_map map; 5243 struct vmcs12 *new_vmcs12; 5244 5245 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmptr), &map)) { 5246 /* 5247 * Reads from an unbacked page return all 1s, 5248 * which means that the 32 bits located at the 5249 * given physical address won't match the required 5250 * VMCS12_REVISION identifier. 5251 */ 5252 return nested_vmx_fail(vcpu, 5253 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); 5254 } 5255 5256 new_vmcs12 = map.hva; 5257 5258 if (new_vmcs12->hdr.revision_id != VMCS12_REVISION || 5259 (new_vmcs12->hdr.shadow_vmcs && 5260 !nested_cpu_has_vmx_shadow_vmcs(vcpu))) { 5261 kvm_vcpu_unmap(vcpu, &map, false); 5262 return nested_vmx_fail(vcpu, 5263 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); 5264 } 5265 5266 nested_release_vmcs12(vcpu); 5267 5268 /* 5269 * Load VMCS12 from guest memory since it is not already 5270 * cached. 5271 */ 5272 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE); 5273 kvm_vcpu_unmap(vcpu, &map, false); 5274 5275 set_current_vmptr(vmx, vmptr); 5276 } 5277 5278 return nested_vmx_succeed(vcpu); 5279 } 5280 5281 /* Emulate the VMPTRST instruction */ 5282 static int handle_vmptrst(struct kvm_vcpu *vcpu) 5283 { 5284 unsigned long exit_qual = vmx_get_exit_qual(vcpu); 5285 u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5286 gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr; 5287 struct x86_exception e; 5288 gva_t gva; 5289 int r; 5290 5291 if (!nested_vmx_check_permission(vcpu)) 5292 return 1; 5293 5294 if (unlikely(to_vmx(vcpu)->nested.hv_evmcs)) 5295 return 1; 5296 5297 if (get_vmx_mem_address(vcpu, exit_qual, instr_info, 5298 true, sizeof(gpa_t), &gva)) 5299 return 1; 5300 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */ 5301 r = kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr, 5302 sizeof(gpa_t), &e); 5303 if (r != X86EMUL_CONTINUE) 5304 return kvm_handle_memory_failure(vcpu, r, &e); 5305 5306 return nested_vmx_succeed(vcpu); 5307 } 5308 5309 #define EPTP_PA_MASK GENMASK_ULL(51, 12) 5310 5311 static bool nested_ept_root_matches(hpa_t root_hpa, u64 root_eptp, u64 eptp) 5312 { 5313 return VALID_PAGE(root_hpa) && 5314 ((root_eptp & EPTP_PA_MASK) == (eptp & EPTP_PA_MASK)); 5315 } 5316 5317 /* Emulate the INVEPT instruction */ 5318 static int handle_invept(struct kvm_vcpu *vcpu) 5319 { 5320 struct vcpu_vmx *vmx = to_vmx(vcpu); 5321 u32 vmx_instruction_info, types; 5322 unsigned long type, roots_to_free; 5323 struct kvm_mmu *mmu; 5324 gva_t gva; 5325 struct x86_exception e; 5326 struct { 5327 u64 eptp, gpa; 5328 } operand; 5329 int i, r; 5330 5331 if (!(vmx->nested.msrs.secondary_ctls_high & 5332 SECONDARY_EXEC_ENABLE_EPT) || 5333 !(vmx->nested.msrs.ept_caps & VMX_EPT_INVEPT_BIT)) { 5334 kvm_queue_exception(vcpu, UD_VECTOR); 5335 return 1; 5336 } 5337 5338 if (!nested_vmx_check_permission(vcpu)) 5339 return 1; 5340 5341 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5342 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5343 5344 types = (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; 5345 5346 if (type >= 32 || !(types & (1 << type))) 5347 return nested_vmx_fail(vcpu, VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5348 5349 /* According to the Intel VMX instruction reference, the memory 5350 * operand is read even if it isn't needed (e.g., for type==global) 5351 */ 5352 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), 5353 vmx_instruction_info, false, sizeof(operand), &gva)) 5354 return 1; 5355 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 5356 if (r != X86EMUL_CONTINUE) 5357 return kvm_handle_memory_failure(vcpu, r, &e); 5358 5359 /* 5360 * Nested EPT roots are always held through guest_mmu, 5361 * not root_mmu. 5362 */ 5363 mmu = &vcpu->arch.guest_mmu; 5364 5365 switch (type) { 5366 case VMX_EPT_EXTENT_CONTEXT: 5367 if (!nested_vmx_check_eptp(vcpu, operand.eptp)) 5368 return nested_vmx_fail(vcpu, 5369 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5370 5371 roots_to_free = 0; 5372 if (nested_ept_root_matches(mmu->root_hpa, mmu->root_pgd, 5373 operand.eptp)) 5374 roots_to_free |= KVM_MMU_ROOT_CURRENT; 5375 5376 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { 5377 if (nested_ept_root_matches(mmu->prev_roots[i].hpa, 5378 mmu->prev_roots[i].pgd, 5379 operand.eptp)) 5380 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5381 } 5382 break; 5383 case VMX_EPT_EXTENT_GLOBAL: 5384 roots_to_free = KVM_MMU_ROOTS_ALL; 5385 break; 5386 default: 5387 BUG(); 5388 break; 5389 } 5390 5391 if (roots_to_free) 5392 kvm_mmu_free_roots(vcpu, mmu, roots_to_free); 5393 5394 return nested_vmx_succeed(vcpu); 5395 } 5396 5397 static int handle_invvpid(struct kvm_vcpu *vcpu) 5398 { 5399 struct vcpu_vmx *vmx = to_vmx(vcpu); 5400 u32 vmx_instruction_info; 5401 unsigned long type, types; 5402 gva_t gva; 5403 struct x86_exception e; 5404 struct { 5405 u64 vpid; 5406 u64 gla; 5407 } operand; 5408 u16 vpid02; 5409 int r; 5410 5411 if (!(vmx->nested.msrs.secondary_ctls_high & 5412 SECONDARY_EXEC_ENABLE_VPID) || 5413 !(vmx->nested.msrs.vpid_caps & VMX_VPID_INVVPID_BIT)) { 5414 kvm_queue_exception(vcpu, UD_VECTOR); 5415 return 1; 5416 } 5417 5418 if (!nested_vmx_check_permission(vcpu)) 5419 return 1; 5420 5421 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5422 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5423 5424 types = (vmx->nested.msrs.vpid_caps & 5425 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; 5426 5427 if (type >= 32 || !(types & (1 << type))) 5428 return nested_vmx_fail(vcpu, 5429 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5430 5431 /* according to the intel vmx instruction reference, the memory 5432 * operand is read even if it isn't needed (e.g., for type==global) 5433 */ 5434 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), 5435 vmx_instruction_info, false, sizeof(operand), &gva)) 5436 return 1; 5437 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 5438 if (r != X86EMUL_CONTINUE) 5439 return kvm_handle_memory_failure(vcpu, r, &e); 5440 5441 if (operand.vpid >> 16) 5442 return nested_vmx_fail(vcpu, 5443 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5444 5445 vpid02 = nested_get_vpid02(vcpu); 5446 switch (type) { 5447 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: 5448 if (!operand.vpid || 5449 is_noncanonical_address(operand.gla, vcpu)) 5450 return nested_vmx_fail(vcpu, 5451 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5452 vpid_sync_vcpu_addr(vpid02, operand.gla); 5453 break; 5454 case VMX_VPID_EXTENT_SINGLE_CONTEXT: 5455 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: 5456 if (!operand.vpid) 5457 return nested_vmx_fail(vcpu, 5458 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); 5459 vpid_sync_context(vpid02); 5460 break; 5461 case VMX_VPID_EXTENT_ALL_CONTEXT: 5462 vpid_sync_context(vpid02); 5463 break; 5464 default: 5465 WARN_ON_ONCE(1); 5466 return kvm_skip_emulated_instruction(vcpu); 5467 } 5468 5469 /* 5470 * Sync the shadow page tables if EPT is disabled, L1 is invalidating 5471 * linear mappings for L2 (tagged with L2's VPID). Free all roots as 5472 * VPIDs are not tracked in the MMU role. 5473 * 5474 * Note, this operates on root_mmu, not guest_mmu, as L1 and L2 share 5475 * an MMU when EPT is disabled. 5476 * 5477 * TODO: sync only the affected SPTEs for INVDIVIDUAL_ADDR. 5478 */ 5479 if (!enable_ept) 5480 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, 5481 KVM_MMU_ROOTS_ALL); 5482 5483 return nested_vmx_succeed(vcpu); 5484 } 5485 5486 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, 5487 struct vmcs12 *vmcs12) 5488 { 5489 u32 index = kvm_rcx_read(vcpu); 5490 u64 new_eptp; 5491 bool accessed_dirty; 5492 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 5493 5494 if (!nested_cpu_has_eptp_switching(vmcs12) || 5495 !nested_cpu_has_ept(vmcs12)) 5496 return 1; 5497 5498 if (index >= VMFUNC_EPTP_ENTRIES) 5499 return 1; 5500 5501 5502 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, 5503 &new_eptp, index * 8, 8)) 5504 return 1; 5505 5506 accessed_dirty = !!(new_eptp & VMX_EPTP_AD_ENABLE_BIT); 5507 5508 /* 5509 * If the (L2) guest does a vmfunc to the currently 5510 * active ept pointer, we don't have to do anything else 5511 */ 5512 if (vmcs12->ept_pointer != new_eptp) { 5513 if (!nested_vmx_check_eptp(vcpu, new_eptp)) 5514 return 1; 5515 5516 kvm_mmu_unload(vcpu); 5517 mmu->ept_ad = accessed_dirty; 5518 mmu->mmu_role.base.ad_disabled = !accessed_dirty; 5519 vmcs12->ept_pointer = new_eptp; 5520 /* 5521 * TODO: Check what's the correct approach in case 5522 * mmu reload fails. Currently, we just let the next 5523 * reload potentially fail 5524 */ 5525 kvm_mmu_reload(vcpu); 5526 } 5527 5528 return 0; 5529 } 5530 5531 static int handle_vmfunc(struct kvm_vcpu *vcpu) 5532 { 5533 struct vcpu_vmx *vmx = to_vmx(vcpu); 5534 struct vmcs12 *vmcs12; 5535 u32 function = kvm_rax_read(vcpu); 5536 5537 /* 5538 * VMFUNC is only supported for nested guests, but we always enable the 5539 * secondary control for simplicity; for non-nested mode, fake that we 5540 * didn't by injecting #UD. 5541 */ 5542 if (!is_guest_mode(vcpu)) { 5543 kvm_queue_exception(vcpu, UD_VECTOR); 5544 return 1; 5545 } 5546 5547 vmcs12 = get_vmcs12(vcpu); 5548 if ((vmcs12->vm_function_control & (1 << function)) == 0) 5549 goto fail; 5550 5551 switch (function) { 5552 case 0: 5553 if (nested_vmx_eptp_switching(vcpu, vmcs12)) 5554 goto fail; 5555 break; 5556 default: 5557 goto fail; 5558 } 5559 return kvm_skip_emulated_instruction(vcpu); 5560 5561 fail: 5562 nested_vmx_vmexit(vcpu, vmx->exit_reason, 5563 vmx_get_intr_info(vcpu), 5564 vmx_get_exit_qual(vcpu)); 5565 return 1; 5566 } 5567 5568 /* 5569 * Return true if an IO instruction with the specified port and size should cause 5570 * a VM-exit into L1. 5571 */ 5572 bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, 5573 int size) 5574 { 5575 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5576 gpa_t bitmap, last_bitmap; 5577 u8 b; 5578 5579 last_bitmap = (gpa_t)-1; 5580 b = -1; 5581 5582 while (size > 0) { 5583 if (port < 0x8000) 5584 bitmap = vmcs12->io_bitmap_a; 5585 else if (port < 0x10000) 5586 bitmap = vmcs12->io_bitmap_b; 5587 else 5588 return true; 5589 bitmap += (port & 0x7fff) / 8; 5590 5591 if (last_bitmap != bitmap) 5592 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) 5593 return true; 5594 if (b & (1 << (port & 7))) 5595 return true; 5596 5597 port++; 5598 size--; 5599 last_bitmap = bitmap; 5600 } 5601 5602 return false; 5603 } 5604 5605 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, 5606 struct vmcs12 *vmcs12) 5607 { 5608 unsigned long exit_qualification; 5609 unsigned short port; 5610 int size; 5611 5612 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 5613 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); 5614 5615 exit_qualification = vmx_get_exit_qual(vcpu); 5616 5617 port = exit_qualification >> 16; 5618 size = (exit_qualification & 7) + 1; 5619 5620 return nested_vmx_check_io_bitmaps(vcpu, port, size); 5621 } 5622 5623 /* 5624 * Return 1 if we should exit from L2 to L1 to handle an MSR access, 5625 * rather than handle it ourselves in L0. I.e., check whether L1 expressed 5626 * disinterest in the current event (read or write a specific MSR) by using an 5627 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. 5628 */ 5629 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, 5630 struct vmcs12 *vmcs12, u32 exit_reason) 5631 { 5632 u32 msr_index = kvm_rcx_read(vcpu); 5633 gpa_t bitmap; 5634 5635 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) 5636 return true; 5637 5638 /* 5639 * The MSR_BITMAP page is divided into four 1024-byte bitmaps, 5640 * for the four combinations of read/write and low/high MSR numbers. 5641 * First we need to figure out which of the four to use: 5642 */ 5643 bitmap = vmcs12->msr_bitmap; 5644 if (exit_reason == EXIT_REASON_MSR_WRITE) 5645 bitmap += 2048; 5646 if (msr_index >= 0xc0000000) { 5647 msr_index -= 0xc0000000; 5648 bitmap += 1024; 5649 } 5650 5651 /* Then read the msr_index'th bit from this bitmap: */ 5652 if (msr_index < 1024*8) { 5653 unsigned char b; 5654 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) 5655 return true; 5656 return 1 & (b >> (msr_index & 7)); 5657 } else 5658 return true; /* let L1 handle the wrong parameter */ 5659 } 5660 5661 /* 5662 * Return 1 if we should exit from L2 to L1 to handle a CR access exit, 5663 * rather than handle it ourselves in L0. I.e., check if L1 wanted to 5664 * intercept (via guest_host_mask etc.) the current event. 5665 */ 5666 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, 5667 struct vmcs12 *vmcs12) 5668 { 5669 unsigned long exit_qualification = vmx_get_exit_qual(vcpu); 5670 int cr = exit_qualification & 15; 5671 int reg; 5672 unsigned long val; 5673 5674 switch ((exit_qualification >> 4) & 3) { 5675 case 0: /* mov to cr */ 5676 reg = (exit_qualification >> 8) & 15; 5677 val = kvm_register_readl(vcpu, reg); 5678 switch (cr) { 5679 case 0: 5680 if (vmcs12->cr0_guest_host_mask & 5681 (val ^ vmcs12->cr0_read_shadow)) 5682 return true; 5683 break; 5684 case 3: 5685 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) 5686 return true; 5687 break; 5688 case 4: 5689 if (vmcs12->cr4_guest_host_mask & 5690 (vmcs12->cr4_read_shadow ^ val)) 5691 return true; 5692 break; 5693 case 8: 5694 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) 5695 return true; 5696 break; 5697 } 5698 break; 5699 case 2: /* clts */ 5700 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && 5701 (vmcs12->cr0_read_shadow & X86_CR0_TS)) 5702 return true; 5703 break; 5704 case 1: /* mov from cr */ 5705 switch (cr) { 5706 case 3: 5707 if (vmcs12->cpu_based_vm_exec_control & 5708 CPU_BASED_CR3_STORE_EXITING) 5709 return true; 5710 break; 5711 case 8: 5712 if (vmcs12->cpu_based_vm_exec_control & 5713 CPU_BASED_CR8_STORE_EXITING) 5714 return true; 5715 break; 5716 } 5717 break; 5718 case 3: /* lmsw */ 5719 /* 5720 * lmsw can change bits 1..3 of cr0, and only set bit 0 of 5721 * cr0. Other attempted changes are ignored, with no exit. 5722 */ 5723 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 5724 if (vmcs12->cr0_guest_host_mask & 0xe & 5725 (val ^ vmcs12->cr0_read_shadow)) 5726 return true; 5727 if ((vmcs12->cr0_guest_host_mask & 0x1) && 5728 !(vmcs12->cr0_read_shadow & 0x1) && 5729 (val & 0x1)) 5730 return true; 5731 break; 5732 } 5733 return false; 5734 } 5735 5736 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu, 5737 struct vmcs12 *vmcs12, gpa_t bitmap) 5738 { 5739 u32 vmx_instruction_info; 5740 unsigned long field; 5741 u8 b; 5742 5743 if (!nested_cpu_has_shadow_vmcs(vmcs12)) 5744 return true; 5745 5746 /* Decode instruction info and find the field to access */ 5747 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5748 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); 5749 5750 /* Out-of-range fields always cause a VM exit from L2 to L1 */ 5751 if (field >> 15) 5752 return true; 5753 5754 if (kvm_vcpu_read_guest(vcpu, bitmap + field/8, &b, 1)) 5755 return true; 5756 5757 return 1 & (b >> (field & 7)); 5758 } 5759 5760 static bool nested_vmx_exit_handled_mtf(struct vmcs12 *vmcs12) 5761 { 5762 u32 entry_intr_info = vmcs12->vm_entry_intr_info_field; 5763 5764 if (nested_cpu_has_mtf(vmcs12)) 5765 return true; 5766 5767 /* 5768 * An MTF VM-exit may be injected into the guest by setting the 5769 * interruption-type to 7 (other event) and the vector field to 0. Such 5770 * is the case regardless of the 'monitor trap flag' VM-execution 5771 * control. 5772 */ 5773 return entry_intr_info == (INTR_INFO_VALID_MASK 5774 | INTR_TYPE_OTHER_EVENT); 5775 } 5776 5777 /* 5778 * Return true if L0 wants to handle an exit from L2 regardless of whether or not 5779 * L1 wants the exit. Only call this when in is_guest_mode (L2). 5780 */ 5781 static bool nested_vmx_l0_wants_exit(struct kvm_vcpu *vcpu, u32 exit_reason) 5782 { 5783 u32 intr_info; 5784 5785 switch ((u16)exit_reason) { 5786 case EXIT_REASON_EXCEPTION_NMI: 5787 intr_info = vmx_get_intr_info(vcpu); 5788 if (is_nmi(intr_info)) 5789 return true; 5790 else if (is_page_fault(intr_info)) 5791 return vcpu->arch.apf.host_apf_flags || !enable_ept; 5792 else if (is_debug(intr_info) && 5793 vcpu->guest_debug & 5794 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 5795 return true; 5796 else if (is_breakpoint(intr_info) && 5797 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 5798 return true; 5799 return false; 5800 case EXIT_REASON_EXTERNAL_INTERRUPT: 5801 return true; 5802 case EXIT_REASON_MCE_DURING_VMENTRY: 5803 return true; 5804 case EXIT_REASON_EPT_VIOLATION: 5805 /* 5806 * L0 always deals with the EPT violation. If nested EPT is 5807 * used, and the nested mmu code discovers that the address is 5808 * missing in the guest EPT table (EPT12), the EPT violation 5809 * will be injected with nested_ept_inject_page_fault() 5810 */ 5811 return true; 5812 case EXIT_REASON_EPT_MISCONFIG: 5813 /* 5814 * L2 never uses directly L1's EPT, but rather L0's own EPT 5815 * table (shadow on EPT) or a merged EPT table that L0 built 5816 * (EPT on EPT). So any problems with the structure of the 5817 * table is L0's fault. 5818 */ 5819 return true; 5820 case EXIT_REASON_PREEMPTION_TIMER: 5821 return true; 5822 case EXIT_REASON_PML_FULL: 5823 /* We emulate PML support to L1. */ 5824 return true; 5825 case EXIT_REASON_VMFUNC: 5826 /* VM functions are emulated through L2->L0 vmexits. */ 5827 return true; 5828 case EXIT_REASON_ENCLS: 5829 /* SGX is never exposed to L1 */ 5830 return true; 5831 default: 5832 break; 5833 } 5834 return false; 5835 } 5836 5837 /* 5838 * Return 1 if L1 wants to intercept an exit from L2. Only call this when in 5839 * is_guest_mode (L2). 5840 */ 5841 static bool nested_vmx_l1_wants_exit(struct kvm_vcpu *vcpu, u32 exit_reason) 5842 { 5843 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5844 u32 intr_info; 5845 5846 switch ((u16)exit_reason) { 5847 case EXIT_REASON_EXCEPTION_NMI: 5848 intr_info = vmx_get_intr_info(vcpu); 5849 if (is_nmi(intr_info)) 5850 return true; 5851 else if (is_page_fault(intr_info)) 5852 return true; 5853 return vmcs12->exception_bitmap & 5854 (1u << (intr_info & INTR_INFO_VECTOR_MASK)); 5855 case EXIT_REASON_EXTERNAL_INTERRUPT: 5856 return nested_exit_on_intr(vcpu); 5857 case EXIT_REASON_TRIPLE_FAULT: 5858 return true; 5859 case EXIT_REASON_INTERRUPT_WINDOW: 5860 return nested_cpu_has(vmcs12, CPU_BASED_INTR_WINDOW_EXITING); 5861 case EXIT_REASON_NMI_WINDOW: 5862 return nested_cpu_has(vmcs12, CPU_BASED_NMI_WINDOW_EXITING); 5863 case EXIT_REASON_TASK_SWITCH: 5864 return true; 5865 case EXIT_REASON_CPUID: 5866 return true; 5867 case EXIT_REASON_HLT: 5868 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); 5869 case EXIT_REASON_INVD: 5870 return true; 5871 case EXIT_REASON_INVLPG: 5872 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); 5873 case EXIT_REASON_RDPMC: 5874 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); 5875 case EXIT_REASON_RDRAND: 5876 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); 5877 case EXIT_REASON_RDSEED: 5878 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); 5879 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: 5880 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); 5881 case EXIT_REASON_VMREAD: 5882 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12, 5883 vmcs12->vmread_bitmap); 5884 case EXIT_REASON_VMWRITE: 5885 return nested_vmx_exit_handled_vmcs_access(vcpu, vmcs12, 5886 vmcs12->vmwrite_bitmap); 5887 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: 5888 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: 5889 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMRESUME: 5890 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: 5891 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: 5892 /* 5893 * VMX instructions trap unconditionally. This allows L1 to 5894 * emulate them for its L2 guest, i.e., allows 3-level nesting! 5895 */ 5896 return true; 5897 case EXIT_REASON_CR_ACCESS: 5898 return nested_vmx_exit_handled_cr(vcpu, vmcs12); 5899 case EXIT_REASON_DR_ACCESS: 5900 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); 5901 case EXIT_REASON_IO_INSTRUCTION: 5902 return nested_vmx_exit_handled_io(vcpu, vmcs12); 5903 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: 5904 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); 5905 case EXIT_REASON_MSR_READ: 5906 case EXIT_REASON_MSR_WRITE: 5907 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); 5908 case EXIT_REASON_INVALID_STATE: 5909 return true; 5910 case EXIT_REASON_MWAIT_INSTRUCTION: 5911 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); 5912 case EXIT_REASON_MONITOR_TRAP_FLAG: 5913 return nested_vmx_exit_handled_mtf(vmcs12); 5914 case EXIT_REASON_MONITOR_INSTRUCTION: 5915 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); 5916 case EXIT_REASON_PAUSE_INSTRUCTION: 5917 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || 5918 nested_cpu_has2(vmcs12, 5919 SECONDARY_EXEC_PAUSE_LOOP_EXITING); 5920 case EXIT_REASON_MCE_DURING_VMENTRY: 5921 return true; 5922 case EXIT_REASON_TPR_BELOW_THRESHOLD: 5923 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); 5924 case EXIT_REASON_APIC_ACCESS: 5925 case EXIT_REASON_APIC_WRITE: 5926 case EXIT_REASON_EOI_INDUCED: 5927 /* 5928 * The controls for "virtualize APIC accesses," "APIC- 5929 * register virtualization," and "virtual-interrupt 5930 * delivery" only come from vmcs12. 5931 */ 5932 return true; 5933 case EXIT_REASON_INVPCID: 5934 return 5935 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && 5936 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); 5937 case EXIT_REASON_WBINVD: 5938 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); 5939 case EXIT_REASON_XSETBV: 5940 return true; 5941 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: 5942 /* 5943 * This should never happen, since it is not possible to 5944 * set XSS to a non-zero value---neither in L1 nor in L2. 5945 * If if it were, XSS would have to be checked against 5946 * the XSS exit bitmap in vmcs12. 5947 */ 5948 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); 5949 case EXIT_REASON_UMWAIT: 5950 case EXIT_REASON_TPAUSE: 5951 return nested_cpu_has2(vmcs12, 5952 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE); 5953 default: 5954 return true; 5955 } 5956 } 5957 5958 /* 5959 * Conditionally reflect a VM-Exit into L1. Returns %true if the VM-Exit was 5960 * reflected into L1. 5961 */ 5962 bool nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu) 5963 { 5964 struct vcpu_vmx *vmx = to_vmx(vcpu); 5965 u32 exit_reason = vmx->exit_reason; 5966 unsigned long exit_qual; 5967 u32 exit_intr_info; 5968 5969 WARN_ON_ONCE(vmx->nested.nested_run_pending); 5970 5971 /* 5972 * Late nested VM-Fail shares the same flow as nested VM-Exit since KVM 5973 * has already loaded L2's state. 5974 */ 5975 if (unlikely(vmx->fail)) { 5976 trace_kvm_nested_vmenter_failed( 5977 "hardware VM-instruction error: ", 5978 vmcs_read32(VM_INSTRUCTION_ERROR)); 5979 exit_intr_info = 0; 5980 exit_qual = 0; 5981 goto reflect_vmexit; 5982 } 5983 5984 trace_kvm_nested_vmexit(exit_reason, vcpu, KVM_ISA_VMX); 5985 5986 /* If L0 (KVM) wants the exit, it trumps L1's desires. */ 5987 if (nested_vmx_l0_wants_exit(vcpu, exit_reason)) 5988 return false; 5989 5990 /* If L1 doesn't want the exit, handle it in L0. */ 5991 if (!nested_vmx_l1_wants_exit(vcpu, exit_reason)) 5992 return false; 5993 5994 /* 5995 * vmcs.VM_EXIT_INTR_INFO is only valid for EXCEPTION_NMI exits. For 5996 * EXTERNAL_INTERRUPT, the value for vmcs12->vm_exit_intr_info would 5997 * need to be synthesized by querying the in-kernel LAPIC, but external 5998 * interrupts are never reflected to L1 so it's a non-issue. 5999 */ 6000 exit_intr_info = vmx_get_intr_info(vcpu); 6001 if (is_exception_with_error_code(exit_intr_info)) { 6002 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6003 6004 vmcs12->vm_exit_intr_error_code = 6005 vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 6006 } 6007 exit_qual = vmx_get_exit_qual(vcpu); 6008 6009 reflect_vmexit: 6010 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info, exit_qual); 6011 return true; 6012 } 6013 6014 static int vmx_get_nested_state(struct kvm_vcpu *vcpu, 6015 struct kvm_nested_state __user *user_kvm_nested_state, 6016 u32 user_data_size) 6017 { 6018 struct vcpu_vmx *vmx; 6019 struct vmcs12 *vmcs12; 6020 struct kvm_nested_state kvm_state = { 6021 .flags = 0, 6022 .format = KVM_STATE_NESTED_FORMAT_VMX, 6023 .size = sizeof(kvm_state), 6024 .hdr.vmx.flags = 0, 6025 .hdr.vmx.vmxon_pa = -1ull, 6026 .hdr.vmx.vmcs12_pa = -1ull, 6027 .hdr.vmx.preemption_timer_deadline = 0, 6028 }; 6029 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state = 6030 &user_kvm_nested_state->data.vmx[0]; 6031 6032 if (!vcpu) 6033 return kvm_state.size + sizeof(*user_vmx_nested_state); 6034 6035 vmx = to_vmx(vcpu); 6036 vmcs12 = get_vmcs12(vcpu); 6037 6038 if (nested_vmx_allowed(vcpu) && 6039 (vmx->nested.vmxon || vmx->nested.smm.vmxon)) { 6040 kvm_state.hdr.vmx.vmxon_pa = vmx->nested.vmxon_ptr; 6041 kvm_state.hdr.vmx.vmcs12_pa = vmx->nested.current_vmptr; 6042 6043 if (vmx_has_valid_vmcs12(vcpu)) { 6044 kvm_state.size += sizeof(user_vmx_nested_state->vmcs12); 6045 6046 if (vmx->nested.hv_evmcs) 6047 kvm_state.flags |= KVM_STATE_NESTED_EVMCS; 6048 6049 if (is_guest_mode(vcpu) && 6050 nested_cpu_has_shadow_vmcs(vmcs12) && 6051 vmcs12->vmcs_link_pointer != -1ull) 6052 kvm_state.size += sizeof(user_vmx_nested_state->shadow_vmcs12); 6053 } 6054 6055 if (vmx->nested.smm.vmxon) 6056 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_VMXON; 6057 6058 if (vmx->nested.smm.guest_mode) 6059 kvm_state.hdr.vmx.smm.flags |= KVM_STATE_NESTED_SMM_GUEST_MODE; 6060 6061 if (is_guest_mode(vcpu)) { 6062 kvm_state.flags |= KVM_STATE_NESTED_GUEST_MODE; 6063 6064 if (vmx->nested.nested_run_pending) 6065 kvm_state.flags |= KVM_STATE_NESTED_RUN_PENDING; 6066 6067 if (vmx->nested.mtf_pending) 6068 kvm_state.flags |= KVM_STATE_NESTED_MTF_PENDING; 6069 6070 if (nested_cpu_has_preemption_timer(vmcs12) && 6071 vmx->nested.has_preemption_timer_deadline) { 6072 kvm_state.hdr.vmx.flags |= 6073 KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE; 6074 kvm_state.hdr.vmx.preemption_timer_deadline = 6075 vmx->nested.preemption_timer_deadline; 6076 } 6077 } 6078 } 6079 6080 if (user_data_size < kvm_state.size) 6081 goto out; 6082 6083 if (copy_to_user(user_kvm_nested_state, &kvm_state, sizeof(kvm_state))) 6084 return -EFAULT; 6085 6086 if (!vmx_has_valid_vmcs12(vcpu)) 6087 goto out; 6088 6089 /* 6090 * When running L2, the authoritative vmcs12 state is in the 6091 * vmcs02. When running L1, the authoritative vmcs12 state is 6092 * in the shadow or enlightened vmcs linked to vmcs01, unless 6093 * need_vmcs12_to_shadow_sync is set, in which case, the authoritative 6094 * vmcs12 state is in the vmcs12 already. 6095 */ 6096 if (is_guest_mode(vcpu)) { 6097 sync_vmcs02_to_vmcs12(vcpu, vmcs12); 6098 sync_vmcs02_to_vmcs12_rare(vcpu, vmcs12); 6099 } else { 6100 copy_vmcs02_to_vmcs12_rare(vcpu, get_vmcs12(vcpu)); 6101 if (!vmx->nested.need_vmcs12_to_shadow_sync) { 6102 if (vmx->nested.hv_evmcs) 6103 copy_enlightened_to_vmcs12(vmx); 6104 else if (enable_shadow_vmcs) 6105 copy_shadow_to_vmcs12(vmx); 6106 } 6107 } 6108 6109 BUILD_BUG_ON(sizeof(user_vmx_nested_state->vmcs12) < VMCS12_SIZE); 6110 BUILD_BUG_ON(sizeof(user_vmx_nested_state->shadow_vmcs12) < VMCS12_SIZE); 6111 6112 /* 6113 * Copy over the full allocated size of vmcs12 rather than just the size 6114 * of the struct. 6115 */ 6116 if (copy_to_user(user_vmx_nested_state->vmcs12, vmcs12, VMCS12_SIZE)) 6117 return -EFAULT; 6118 6119 if (nested_cpu_has_shadow_vmcs(vmcs12) && 6120 vmcs12->vmcs_link_pointer != -1ull) { 6121 if (copy_to_user(user_vmx_nested_state->shadow_vmcs12, 6122 get_shadow_vmcs12(vcpu), VMCS12_SIZE)) 6123 return -EFAULT; 6124 } 6125 out: 6126 return kvm_state.size; 6127 } 6128 6129 /* 6130 * Forcibly leave nested mode in order to be able to reset the VCPU later on. 6131 */ 6132 void vmx_leave_nested(struct kvm_vcpu *vcpu) 6133 { 6134 if (is_guest_mode(vcpu)) { 6135 to_vmx(vcpu)->nested.nested_run_pending = 0; 6136 nested_vmx_vmexit(vcpu, -1, 0, 0); 6137 } 6138 free_nested(vcpu); 6139 } 6140 6141 static int vmx_set_nested_state(struct kvm_vcpu *vcpu, 6142 struct kvm_nested_state __user *user_kvm_nested_state, 6143 struct kvm_nested_state *kvm_state) 6144 { 6145 struct vcpu_vmx *vmx = to_vmx(vcpu); 6146 struct vmcs12 *vmcs12; 6147 enum vm_entry_failure_code ignored; 6148 struct kvm_vmx_nested_state_data __user *user_vmx_nested_state = 6149 &user_kvm_nested_state->data.vmx[0]; 6150 int ret; 6151 6152 if (kvm_state->format != KVM_STATE_NESTED_FORMAT_VMX) 6153 return -EINVAL; 6154 6155 if (kvm_state->hdr.vmx.vmxon_pa == -1ull) { 6156 if (kvm_state->hdr.vmx.smm.flags) 6157 return -EINVAL; 6158 6159 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull) 6160 return -EINVAL; 6161 6162 /* 6163 * KVM_STATE_NESTED_EVMCS used to signal that KVM should 6164 * enable eVMCS capability on vCPU. However, since then 6165 * code was changed such that flag signals vmcs12 should 6166 * be copied into eVMCS in guest memory. 6167 * 6168 * To preserve backwards compatability, allow user 6169 * to set this flag even when there is no VMXON region. 6170 */ 6171 if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS) 6172 return -EINVAL; 6173 } else { 6174 if (!nested_vmx_allowed(vcpu)) 6175 return -EINVAL; 6176 6177 if (!page_address_valid(vcpu, kvm_state->hdr.vmx.vmxon_pa)) 6178 return -EINVAL; 6179 } 6180 6181 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) && 6182 (kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE)) 6183 return -EINVAL; 6184 6185 if (kvm_state->hdr.vmx.smm.flags & 6186 ~(KVM_STATE_NESTED_SMM_GUEST_MODE | KVM_STATE_NESTED_SMM_VMXON)) 6187 return -EINVAL; 6188 6189 if (kvm_state->hdr.vmx.flags & ~KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE) 6190 return -EINVAL; 6191 6192 /* 6193 * SMM temporarily disables VMX, so we cannot be in guest mode, 6194 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags 6195 * must be zero. 6196 */ 6197 if (is_smm(vcpu) ? 6198 (kvm_state->flags & 6199 (KVM_STATE_NESTED_GUEST_MODE | KVM_STATE_NESTED_RUN_PENDING)) 6200 : kvm_state->hdr.vmx.smm.flags) 6201 return -EINVAL; 6202 6203 if ((kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) && 6204 !(kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON)) 6205 return -EINVAL; 6206 6207 if ((kvm_state->flags & KVM_STATE_NESTED_EVMCS) && 6208 (!nested_vmx_allowed(vcpu) || !vmx->nested.enlightened_vmcs_enabled)) 6209 return -EINVAL; 6210 6211 vmx_leave_nested(vcpu); 6212 6213 if (kvm_state->hdr.vmx.vmxon_pa == -1ull) 6214 return 0; 6215 6216 vmx->nested.vmxon_ptr = kvm_state->hdr.vmx.vmxon_pa; 6217 ret = enter_vmx_operation(vcpu); 6218 if (ret) 6219 return ret; 6220 6221 /* Empty 'VMXON' state is permitted if no VMCS loaded */ 6222 if (kvm_state->size < sizeof(*kvm_state) + sizeof(*vmcs12)) { 6223 /* See vmx_has_valid_vmcs12. */ 6224 if ((kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE) || 6225 (kvm_state->flags & KVM_STATE_NESTED_EVMCS) || 6226 (kvm_state->hdr.vmx.vmcs12_pa != -1ull)) 6227 return -EINVAL; 6228 else 6229 return 0; 6230 } 6231 6232 if (kvm_state->hdr.vmx.vmcs12_pa != -1ull) { 6233 if (kvm_state->hdr.vmx.vmcs12_pa == kvm_state->hdr.vmx.vmxon_pa || 6234 !page_address_valid(vcpu, kvm_state->hdr.vmx.vmcs12_pa)) 6235 return -EINVAL; 6236 6237 set_current_vmptr(vmx, kvm_state->hdr.vmx.vmcs12_pa); 6238 } else if (kvm_state->flags & KVM_STATE_NESTED_EVMCS) { 6239 /* 6240 * nested_vmx_handle_enlightened_vmptrld() cannot be called 6241 * directly from here as HV_X64_MSR_VP_ASSIST_PAGE may not be 6242 * restored yet. EVMCS will be mapped from 6243 * nested_get_vmcs12_pages(). 6244 */ 6245 kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); 6246 } else { 6247 return -EINVAL; 6248 } 6249 6250 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON) { 6251 vmx->nested.smm.vmxon = true; 6252 vmx->nested.vmxon = false; 6253 6254 if (kvm_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_GUEST_MODE) 6255 vmx->nested.smm.guest_mode = true; 6256 } 6257 6258 vmcs12 = get_vmcs12(vcpu); 6259 if (copy_from_user(vmcs12, user_vmx_nested_state->vmcs12, sizeof(*vmcs12))) 6260 return -EFAULT; 6261 6262 if (vmcs12->hdr.revision_id != VMCS12_REVISION) 6263 return -EINVAL; 6264 6265 if (!(kvm_state->flags & KVM_STATE_NESTED_GUEST_MODE)) 6266 return 0; 6267 6268 vmx->nested.nested_run_pending = 6269 !!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING); 6270 6271 vmx->nested.mtf_pending = 6272 !!(kvm_state->flags & KVM_STATE_NESTED_MTF_PENDING); 6273 6274 ret = -EINVAL; 6275 if (nested_cpu_has_shadow_vmcs(vmcs12) && 6276 vmcs12->vmcs_link_pointer != -1ull) { 6277 struct vmcs12 *shadow_vmcs12 = get_shadow_vmcs12(vcpu); 6278 6279 if (kvm_state->size < 6280 sizeof(*kvm_state) + 6281 sizeof(user_vmx_nested_state->vmcs12) + sizeof(*shadow_vmcs12)) 6282 goto error_guest_mode; 6283 6284 if (copy_from_user(shadow_vmcs12, 6285 user_vmx_nested_state->shadow_vmcs12, 6286 sizeof(*shadow_vmcs12))) { 6287 ret = -EFAULT; 6288 goto error_guest_mode; 6289 } 6290 6291 if (shadow_vmcs12->hdr.revision_id != VMCS12_REVISION || 6292 !shadow_vmcs12->hdr.shadow_vmcs) 6293 goto error_guest_mode; 6294 } 6295 6296 vmx->nested.has_preemption_timer_deadline = false; 6297 if (kvm_state->hdr.vmx.flags & KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE) { 6298 vmx->nested.has_preemption_timer_deadline = true; 6299 vmx->nested.preemption_timer_deadline = 6300 kvm_state->hdr.vmx.preemption_timer_deadline; 6301 } 6302 6303 if (nested_vmx_check_controls(vcpu, vmcs12) || 6304 nested_vmx_check_host_state(vcpu, vmcs12) || 6305 nested_vmx_check_guest_state(vcpu, vmcs12, &ignored)) 6306 goto error_guest_mode; 6307 6308 vmx->nested.dirty_vmcs12 = true; 6309 ret = nested_vmx_enter_non_root_mode(vcpu, false); 6310 if (ret) 6311 goto error_guest_mode; 6312 6313 return 0; 6314 6315 error_guest_mode: 6316 vmx->nested.nested_run_pending = 0; 6317 return ret; 6318 } 6319 6320 void nested_vmx_set_vmcs_shadowing_bitmap(void) 6321 { 6322 if (enable_shadow_vmcs) { 6323 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); 6324 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); 6325 } 6326 } 6327 6328 /* 6329 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be 6330 * returned for the various VMX controls MSRs when nested VMX is enabled. 6331 * The same values should also be used to verify that vmcs12 control fields are 6332 * valid during nested entry from L1 to L2. 6333 * Each of these control msrs has a low and high 32-bit half: A low bit is on 6334 * if the corresponding bit in the (32-bit) control field *must* be on, and a 6335 * bit in the high half is on if the corresponding bit in the control field 6336 * may be on. See also vmx_control_verify(). 6337 */ 6338 void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps) 6339 { 6340 /* 6341 * Note that as a general rule, the high half of the MSRs (bits in 6342 * the control fields which may be 1) should be initialized by the 6343 * intersection of the underlying hardware's MSR (i.e., features which 6344 * can be supported) and the list of features we want to expose - 6345 * because they are known to be properly supported in our code. 6346 * Also, usually, the low half of the MSRs (bits which must be 1) can 6347 * be set to 0, meaning that L1 may turn off any of these bits. The 6348 * reason is that if one of these bits is necessary, it will appear 6349 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control 6350 * fields of vmcs01 and vmcs02, will turn these bits off - and 6351 * nested_vmx_l1_wants_exit() will not pass related exits to L1. 6352 * These rules have exceptions below. 6353 */ 6354 6355 /* pin-based controls */ 6356 rdmsr(MSR_IA32_VMX_PINBASED_CTLS, 6357 msrs->pinbased_ctls_low, 6358 msrs->pinbased_ctls_high); 6359 msrs->pinbased_ctls_low |= 6360 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 6361 msrs->pinbased_ctls_high &= 6362 PIN_BASED_EXT_INTR_MASK | 6363 PIN_BASED_NMI_EXITING | 6364 PIN_BASED_VIRTUAL_NMIS | 6365 (enable_apicv ? PIN_BASED_POSTED_INTR : 0); 6366 msrs->pinbased_ctls_high |= 6367 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | 6368 PIN_BASED_VMX_PREEMPTION_TIMER; 6369 6370 /* exit controls */ 6371 rdmsr(MSR_IA32_VMX_EXIT_CTLS, 6372 msrs->exit_ctls_low, 6373 msrs->exit_ctls_high); 6374 msrs->exit_ctls_low = 6375 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; 6376 6377 msrs->exit_ctls_high &= 6378 #ifdef CONFIG_X86_64 6379 VM_EXIT_HOST_ADDR_SPACE_SIZE | 6380 #endif 6381 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT | 6382 VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 6383 msrs->exit_ctls_high |= 6384 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | 6385 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | 6386 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; 6387 6388 /* We support free control of debug control saving. */ 6389 msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; 6390 6391 /* entry controls */ 6392 rdmsr(MSR_IA32_VMX_ENTRY_CTLS, 6393 msrs->entry_ctls_low, 6394 msrs->entry_ctls_high); 6395 msrs->entry_ctls_low = 6396 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; 6397 msrs->entry_ctls_high &= 6398 #ifdef CONFIG_X86_64 6399 VM_ENTRY_IA32E_MODE | 6400 #endif 6401 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS | 6402 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 6403 msrs->entry_ctls_high |= 6404 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); 6405 6406 /* We support free control of debug control loading. */ 6407 msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; 6408 6409 /* cpu-based controls */ 6410 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, 6411 msrs->procbased_ctls_low, 6412 msrs->procbased_ctls_high); 6413 msrs->procbased_ctls_low = 6414 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; 6415 msrs->procbased_ctls_high &= 6416 CPU_BASED_INTR_WINDOW_EXITING | 6417 CPU_BASED_NMI_WINDOW_EXITING | CPU_BASED_USE_TSC_OFFSETTING | 6418 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | 6419 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | 6420 CPU_BASED_CR3_STORE_EXITING | 6421 #ifdef CONFIG_X86_64 6422 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | 6423 #endif 6424 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | 6425 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | 6426 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | 6427 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | 6428 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 6429 /* 6430 * We can allow some features even when not supported by the 6431 * hardware. For example, L1 can specify an MSR bitmap - and we 6432 * can use it to avoid exits to L1 - even when L0 runs L2 6433 * without MSR bitmaps. 6434 */ 6435 msrs->procbased_ctls_high |= 6436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | 6437 CPU_BASED_USE_MSR_BITMAPS; 6438 6439 /* We support free control of CR3 access interception. */ 6440 msrs->procbased_ctls_low &= 6441 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); 6442 6443 /* 6444 * secondary cpu-based controls. Do not include those that 6445 * depend on CPUID bits, they are added later by 6446 * vmx_vcpu_after_set_cpuid. 6447 */ 6448 if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) 6449 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 6450 msrs->secondary_ctls_low, 6451 msrs->secondary_ctls_high); 6452 6453 msrs->secondary_ctls_low = 0; 6454 msrs->secondary_ctls_high &= 6455 SECONDARY_EXEC_DESC | 6456 SECONDARY_EXEC_ENABLE_RDTSCP | 6457 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6458 SECONDARY_EXEC_WBINVD_EXITING | 6459 SECONDARY_EXEC_APIC_REGISTER_VIRT | 6460 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 6461 SECONDARY_EXEC_RDRAND_EXITING | 6462 SECONDARY_EXEC_ENABLE_INVPCID | 6463 SECONDARY_EXEC_RDSEED_EXITING | 6464 SECONDARY_EXEC_XSAVES; 6465 6466 /* 6467 * We can emulate "VMCS shadowing," even if the hardware 6468 * doesn't support it. 6469 */ 6470 msrs->secondary_ctls_high |= 6471 SECONDARY_EXEC_SHADOW_VMCS; 6472 6473 if (enable_ept) { 6474 /* nested EPT: emulate EPT also to L1 */ 6475 msrs->secondary_ctls_high |= 6476 SECONDARY_EXEC_ENABLE_EPT; 6477 msrs->ept_caps = 6478 VMX_EPT_PAGE_WALK_4_BIT | 6479 VMX_EPT_PAGE_WALK_5_BIT | 6480 VMX_EPTP_WB_BIT | 6481 VMX_EPT_INVEPT_BIT | 6482 VMX_EPT_EXECUTE_ONLY_BIT; 6483 6484 msrs->ept_caps &= ept_caps; 6485 msrs->ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | 6486 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | 6487 VMX_EPT_1GB_PAGE_BIT; 6488 if (enable_ept_ad_bits) { 6489 msrs->secondary_ctls_high |= 6490 SECONDARY_EXEC_ENABLE_PML; 6491 msrs->ept_caps |= VMX_EPT_AD_BIT; 6492 } 6493 } 6494 6495 if (cpu_has_vmx_vmfunc()) { 6496 msrs->secondary_ctls_high |= 6497 SECONDARY_EXEC_ENABLE_VMFUNC; 6498 /* 6499 * Advertise EPTP switching unconditionally 6500 * since we emulate it 6501 */ 6502 if (enable_ept) 6503 msrs->vmfunc_controls = 6504 VMX_VMFUNC_EPTP_SWITCHING; 6505 } 6506 6507 /* 6508 * Old versions of KVM use the single-context version without 6509 * checking for support, so declare that it is supported even 6510 * though it is treated as global context. The alternative is 6511 * not failing the single-context invvpid, and it is worse. 6512 */ 6513 if (enable_vpid) { 6514 msrs->secondary_ctls_high |= 6515 SECONDARY_EXEC_ENABLE_VPID; 6516 msrs->vpid_caps = VMX_VPID_INVVPID_BIT | 6517 VMX_VPID_EXTENT_SUPPORTED_MASK; 6518 } 6519 6520 if (enable_unrestricted_guest) 6521 msrs->secondary_ctls_high |= 6522 SECONDARY_EXEC_UNRESTRICTED_GUEST; 6523 6524 if (flexpriority_enabled) 6525 msrs->secondary_ctls_high |= 6526 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6527 6528 /* miscellaneous data */ 6529 rdmsr(MSR_IA32_VMX_MISC, 6530 msrs->misc_low, 6531 msrs->misc_high); 6532 msrs->misc_low &= VMX_MISC_SAVE_EFER_LMA; 6533 msrs->misc_low |= 6534 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS | 6535 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | 6536 VMX_MISC_ACTIVITY_HLT | 6537 VMX_MISC_ACTIVITY_WAIT_SIPI; 6538 msrs->misc_high = 0; 6539 6540 /* 6541 * This MSR reports some information about VMX support. We 6542 * should return information about the VMX we emulate for the 6543 * guest, and the VMCS structure we give it - not about the 6544 * VMX support of the underlying hardware. 6545 */ 6546 msrs->basic = 6547 VMCS12_REVISION | 6548 VMX_BASIC_TRUE_CTLS | 6549 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | 6550 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); 6551 6552 if (cpu_has_vmx_basic_inout()) 6553 msrs->basic |= VMX_BASIC_INOUT; 6554 6555 /* 6556 * These MSRs specify bits which the guest must keep fixed on 6557 * while L1 is in VMXON mode (in L1's root mode, or running an L2). 6558 * We picked the standard core2 setting. 6559 */ 6560 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) 6561 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE 6562 msrs->cr0_fixed0 = VMXON_CR0_ALWAYSON; 6563 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON; 6564 6565 /* These MSRs specify bits which the guest must keep fixed off. */ 6566 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1); 6567 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1); 6568 6569 /* highest index: VMX_PREEMPTION_TIMER_VALUE */ 6570 msrs->vmcs_enum = VMCS12_MAX_FIELD_INDEX << 1; 6571 } 6572 6573 void nested_vmx_hardware_unsetup(void) 6574 { 6575 int i; 6576 6577 if (enable_shadow_vmcs) { 6578 for (i = 0; i < VMX_BITMAP_NR; i++) 6579 free_page((unsigned long)vmx_bitmap[i]); 6580 } 6581 } 6582 6583 __init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *)) 6584 { 6585 int i; 6586 6587 if (!cpu_has_vmx_shadow_vmcs()) 6588 enable_shadow_vmcs = 0; 6589 if (enable_shadow_vmcs) { 6590 for (i = 0; i < VMX_BITMAP_NR; i++) { 6591 /* 6592 * The vmx_bitmap is not tied to a VM and so should 6593 * not be charged to a memcg. 6594 */ 6595 vmx_bitmap[i] = (unsigned long *) 6596 __get_free_page(GFP_KERNEL); 6597 if (!vmx_bitmap[i]) { 6598 nested_vmx_hardware_unsetup(); 6599 return -ENOMEM; 6600 } 6601 } 6602 6603 init_vmcs_shadow_fields(); 6604 } 6605 6606 exit_handlers[EXIT_REASON_VMCLEAR] = handle_vmclear; 6607 exit_handlers[EXIT_REASON_VMLAUNCH] = handle_vmlaunch; 6608 exit_handlers[EXIT_REASON_VMPTRLD] = handle_vmptrld; 6609 exit_handlers[EXIT_REASON_VMPTRST] = handle_vmptrst; 6610 exit_handlers[EXIT_REASON_VMREAD] = handle_vmread; 6611 exit_handlers[EXIT_REASON_VMRESUME] = handle_vmresume; 6612 exit_handlers[EXIT_REASON_VMWRITE] = handle_vmwrite; 6613 exit_handlers[EXIT_REASON_VMOFF] = handle_vmoff; 6614 exit_handlers[EXIT_REASON_VMON] = handle_vmon; 6615 exit_handlers[EXIT_REASON_INVEPT] = handle_invept; 6616 exit_handlers[EXIT_REASON_INVVPID] = handle_invvpid; 6617 exit_handlers[EXIT_REASON_VMFUNC] = handle_vmfunc; 6618 6619 return 0; 6620 } 6621 6622 struct kvm_x86_nested_ops vmx_nested_ops = { 6623 .check_events = vmx_check_nested_events, 6624 .hv_timer_pending = nested_vmx_preemption_timer_pending, 6625 .get_state = vmx_get_nested_state, 6626 .set_state = vmx_set_nested_state, 6627 .get_nested_state_pages = vmx_get_nested_state_pages, 6628 .write_log_dirty = nested_vmx_write_pml_buffer, 6629 .enable_evmcs = nested_enable_evmcs, 6630 .get_evmcs_version = nested_get_evmcs_version, 6631 }; 6632