1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_CAPS_H 3 #define __KVM_X86_VMX_CAPS_H 4 5 #include <asm/vmx.h> 6 7 #include "lapic.h" 8 9 extern bool __read_mostly enable_vpid; 10 extern bool __read_mostly flexpriority_enabled; 11 extern bool __read_mostly enable_ept; 12 extern bool __read_mostly enable_unrestricted_guest; 13 extern bool __read_mostly enable_ept_ad_bits; 14 extern bool __read_mostly enable_pml; 15 extern bool __read_mostly enable_apicv; 16 extern int __read_mostly pt_mode; 17 18 #define PT_MODE_SYSTEM 0 19 #define PT_MODE_HOST_GUEST 1 20 21 struct nested_vmx_msrs { 22 /* 23 * We only store the "true" versions of the VMX capability MSRs. We 24 * generate the "non-true" versions by setting the must-be-1 bits 25 * according to the SDM. 26 */ 27 u32 procbased_ctls_low; 28 u32 procbased_ctls_high; 29 u32 secondary_ctls_low; 30 u32 secondary_ctls_high; 31 u32 pinbased_ctls_low; 32 u32 pinbased_ctls_high; 33 u32 exit_ctls_low; 34 u32 exit_ctls_high; 35 u32 entry_ctls_low; 36 u32 entry_ctls_high; 37 u32 misc_low; 38 u32 misc_high; 39 u32 ept_caps; 40 u32 vpid_caps; 41 u64 basic; 42 u64 cr0_fixed0; 43 u64 cr0_fixed1; 44 u64 cr4_fixed0; 45 u64 cr4_fixed1; 46 u64 vmcs_enum; 47 u64 vmfunc_controls; 48 }; 49 50 struct vmcs_config { 51 int size; 52 int order; 53 u32 basic_cap; 54 u32 revision_id; 55 u32 pin_based_exec_ctrl; 56 u32 cpu_based_exec_ctrl; 57 u32 cpu_based_2nd_exec_ctrl; 58 u32 vmexit_ctrl; 59 u32 vmentry_ctrl; 60 struct nested_vmx_msrs nested; 61 }; 62 extern struct vmcs_config vmcs_config; 63 64 struct vmx_capability { 65 u32 ept; 66 u32 vpid; 67 }; 68 extern struct vmx_capability vmx_capability; 69 70 static inline bool cpu_has_vmx_basic_inout(void) 71 { 72 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); 73 } 74 75 static inline bool cpu_has_virtual_nmis(void) 76 { 77 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; 78 } 79 80 static inline bool cpu_has_vmx_preemption_timer(void) 81 { 82 return vmcs_config.pin_based_exec_ctrl & 83 PIN_BASED_VMX_PREEMPTION_TIMER; 84 } 85 86 static inline bool cpu_has_vmx_posted_intr(void) 87 { 88 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && 89 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; 90 } 91 92 static inline bool cpu_has_load_ia32_efer(void) 93 { 94 return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER) && 95 (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_EFER); 96 } 97 98 static inline bool cpu_has_load_perf_global_ctrl(void) 99 { 100 return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && 101 (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 102 } 103 104 static inline bool cpu_has_vmx_mpx(void) 105 { 106 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && 107 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); 108 } 109 110 static inline bool cpu_has_vmx_tpr_shadow(void) 111 { 112 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; 113 } 114 115 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) 116 { 117 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); 118 } 119 120 static inline bool cpu_has_vmx_msr_bitmap(void) 121 { 122 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; 123 } 124 125 static inline bool cpu_has_secondary_exec_ctrls(void) 126 { 127 return vmcs_config.cpu_based_exec_ctrl & 128 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 129 } 130 131 static inline bool cpu_has_vmx_virtualize_apic_accesses(void) 132 { 133 return vmcs_config.cpu_based_2nd_exec_ctrl & 134 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 135 } 136 137 static inline bool cpu_has_vmx_ept(void) 138 { 139 return vmcs_config.cpu_based_2nd_exec_ctrl & 140 SECONDARY_EXEC_ENABLE_EPT; 141 } 142 143 static inline bool vmx_umip_emulated(void) 144 { 145 return vmcs_config.cpu_based_2nd_exec_ctrl & 146 SECONDARY_EXEC_DESC; 147 } 148 149 static inline bool cpu_has_vmx_rdtscp(void) 150 { 151 return vmcs_config.cpu_based_2nd_exec_ctrl & 152 SECONDARY_EXEC_RDTSCP; 153 } 154 155 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) 156 { 157 return vmcs_config.cpu_based_2nd_exec_ctrl & 158 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 159 } 160 161 static inline bool cpu_has_vmx_vpid(void) 162 { 163 return vmcs_config.cpu_based_2nd_exec_ctrl & 164 SECONDARY_EXEC_ENABLE_VPID; 165 } 166 167 static inline bool cpu_has_vmx_wbinvd_exit(void) 168 { 169 return vmcs_config.cpu_based_2nd_exec_ctrl & 170 SECONDARY_EXEC_WBINVD_EXITING; 171 } 172 173 static inline bool cpu_has_vmx_unrestricted_guest(void) 174 { 175 return vmcs_config.cpu_based_2nd_exec_ctrl & 176 SECONDARY_EXEC_UNRESTRICTED_GUEST; 177 } 178 179 static inline bool cpu_has_vmx_apic_register_virt(void) 180 { 181 return vmcs_config.cpu_based_2nd_exec_ctrl & 182 SECONDARY_EXEC_APIC_REGISTER_VIRT; 183 } 184 185 static inline bool cpu_has_vmx_virtual_intr_delivery(void) 186 { 187 return vmcs_config.cpu_based_2nd_exec_ctrl & 188 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; 189 } 190 191 static inline bool cpu_has_vmx_ple(void) 192 { 193 return vmcs_config.cpu_based_2nd_exec_ctrl & 194 SECONDARY_EXEC_PAUSE_LOOP_EXITING; 195 } 196 197 static inline bool vmx_rdrand_supported(void) 198 { 199 return vmcs_config.cpu_based_2nd_exec_ctrl & 200 SECONDARY_EXEC_RDRAND_EXITING; 201 } 202 203 static inline bool cpu_has_vmx_invpcid(void) 204 { 205 return vmcs_config.cpu_based_2nd_exec_ctrl & 206 SECONDARY_EXEC_ENABLE_INVPCID; 207 } 208 209 static inline bool cpu_has_vmx_vmfunc(void) 210 { 211 return vmcs_config.cpu_based_2nd_exec_ctrl & 212 SECONDARY_EXEC_ENABLE_VMFUNC; 213 } 214 215 static inline bool cpu_has_vmx_shadow_vmcs(void) 216 { 217 u64 vmx_msr; 218 219 /* check if the cpu supports writing r/o exit information fields */ 220 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 221 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) 222 return false; 223 224 return vmcs_config.cpu_based_2nd_exec_ctrl & 225 SECONDARY_EXEC_SHADOW_VMCS; 226 } 227 228 static inline bool cpu_has_vmx_encls_vmexit(void) 229 { 230 return vmcs_config.cpu_based_2nd_exec_ctrl & 231 SECONDARY_EXEC_ENCLS_EXITING; 232 } 233 234 static inline bool vmx_rdseed_supported(void) 235 { 236 return vmcs_config.cpu_based_2nd_exec_ctrl & 237 SECONDARY_EXEC_RDSEED_EXITING; 238 } 239 240 static inline bool cpu_has_vmx_pml(void) 241 { 242 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; 243 } 244 245 static inline bool vmx_xsaves_supported(void) 246 { 247 return vmcs_config.cpu_based_2nd_exec_ctrl & 248 SECONDARY_EXEC_XSAVES; 249 } 250 251 static inline bool vmx_waitpkg_supported(void) 252 { 253 return vmcs_config.cpu_based_2nd_exec_ctrl & 254 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 255 } 256 257 static inline bool cpu_has_vmx_tsc_scaling(void) 258 { 259 return vmcs_config.cpu_based_2nd_exec_ctrl & 260 SECONDARY_EXEC_TSC_SCALING; 261 } 262 263 static inline bool cpu_has_vmx_apicv(void) 264 { 265 return cpu_has_vmx_apic_register_virt() && 266 cpu_has_vmx_virtual_intr_delivery() && 267 cpu_has_vmx_posted_intr(); 268 } 269 270 static inline bool cpu_has_vmx_flexpriority(void) 271 { 272 return cpu_has_vmx_tpr_shadow() && 273 cpu_has_vmx_virtualize_apic_accesses(); 274 } 275 276 static inline bool cpu_has_vmx_ept_execute_only(void) 277 { 278 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; 279 } 280 281 static inline bool cpu_has_vmx_ept_4levels(void) 282 { 283 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; 284 } 285 286 static inline bool cpu_has_vmx_ept_5levels(void) 287 { 288 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; 289 } 290 291 static inline bool cpu_has_vmx_ept_mt_wb(void) 292 { 293 return vmx_capability.ept & VMX_EPTP_WB_BIT; 294 } 295 296 static inline bool cpu_has_vmx_ept_2m_page(void) 297 { 298 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; 299 } 300 301 static inline bool cpu_has_vmx_ept_1g_page(void) 302 { 303 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; 304 } 305 306 static inline bool cpu_has_vmx_ept_ad_bits(void) 307 { 308 return vmx_capability.ept & VMX_EPT_AD_BIT; 309 } 310 311 static inline bool cpu_has_vmx_invept_context(void) 312 { 313 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; 314 } 315 316 static inline bool cpu_has_vmx_invept_global(void) 317 { 318 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; 319 } 320 321 static inline bool cpu_has_vmx_invvpid(void) 322 { 323 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; 324 } 325 326 static inline bool cpu_has_vmx_invvpid_individual_addr(void) 327 { 328 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT; 329 } 330 331 static inline bool cpu_has_vmx_invvpid_single(void) 332 { 333 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; 334 } 335 336 static inline bool cpu_has_vmx_invvpid_global(void) 337 { 338 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; 339 } 340 341 static inline bool cpu_has_vmx_intel_pt(void) 342 { 343 u64 vmx_msr; 344 345 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 346 return (vmx_msr & MSR_IA32_VMX_MISC_INTEL_PT) && 347 (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) && 348 (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_IA32_RTIT_CTL) && 349 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL); 350 } 351 352 /* 353 * Processor Trace can operate in one of three modes: 354 * a. system-wide: trace both host/guest and output to host buffer 355 * b. host-only: only trace host and output to host buffer 356 * c. host-guest: trace host and guest simultaneously and output to their 357 * respective buffer 358 * 359 * KVM currently only supports (a) and (c). 360 */ 361 static inline bool vmx_pt_mode_is_system(void) 362 { 363 return pt_mode == PT_MODE_SYSTEM; 364 } 365 static inline bool vmx_pt_mode_is_host_guest(void) 366 { 367 return pt_mode == PT_MODE_HOST_GUEST; 368 } 369 370 #endif /* __KVM_X86_VMX_CAPS_H */ 371