1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 24 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) 25 26 #define IOPM_SIZE PAGE_SIZE * 3 27 #define MSRPM_SIZE PAGE_SIZE * 2 28 29 #define MAX_DIRECT_ACCESS_MSRS 20 30 #define MSRPM_OFFSETS 16 31 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 32 extern bool npt_enabled; 33 34 enum { 35 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 36 pause filter count */ 37 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 38 VMCB_ASID, /* ASID */ 39 VMCB_INTR, /* int_ctl, int_vector */ 40 VMCB_NPT, /* npt_en, nCR3, gPAT */ 41 VMCB_CR, /* CR0, CR3, CR4, EFER */ 42 VMCB_DR, /* DR6, DR7 */ 43 VMCB_DT, /* GDT, IDT */ 44 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 45 VMCB_CR2, /* CR2 only */ 46 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 47 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 48 * AVIC PHYSICAL_TABLE pointer, 49 * AVIC LOGICAL_TABLE pointer 50 */ 51 VMCB_DIRTY_MAX, 52 }; 53 54 /* TPR and CR2 are always written before VMRUN */ 55 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 56 57 struct kvm_sev_info { 58 bool active; /* SEV enabled guest */ 59 bool es_active; /* SEV-ES enabled guest */ 60 unsigned int asid; /* ASID used for this guest */ 61 unsigned int handle; /* SEV firmware handle */ 62 int fd; /* SEV device fd */ 63 unsigned long pages_locked; /* Number of pages locked */ 64 struct list_head regions_list; /* List of registered regions */ 65 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 66 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 67 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 68 }; 69 70 struct kvm_svm { 71 struct kvm kvm; 72 73 /* Struct members for AVIC */ 74 u32 avic_vm_id; 75 struct page *avic_logical_id_table_page; 76 struct page *avic_physical_id_table_page; 77 struct hlist_node hnode; 78 79 struct kvm_sev_info sev_info; 80 }; 81 82 struct kvm_vcpu; 83 84 struct kvm_vmcb_info { 85 struct vmcb *ptr; 86 unsigned long pa; 87 int cpu; 88 uint64_t asid_generation; 89 }; 90 91 struct svm_nested_state { 92 struct kvm_vmcb_info vmcb02; 93 u64 hsave_msr; 94 u64 vm_cr_msr; 95 u64 vmcb12_gpa; 96 u64 last_vmcb12_gpa; 97 98 /* These are the merged vectors */ 99 u32 *msrpm; 100 101 /* A VMRUN has started but has not yet been performed, so 102 * we cannot inject a nested vmexit yet. */ 103 bool nested_run_pending; 104 105 /* cache for control fields of the guest */ 106 struct vmcb_control_area ctl; 107 108 bool initialized; 109 }; 110 111 struct vcpu_svm { 112 struct kvm_vcpu vcpu; 113 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 114 struct vmcb *vmcb; 115 struct kvm_vmcb_info vmcb01; 116 struct kvm_vmcb_info *current_vmcb; 117 struct svm_cpu_data *svm_data; 118 u32 asid; 119 u32 sysenter_esp_hi; 120 u32 sysenter_eip_hi; 121 uint64_t tsc_aux; 122 123 u64 msr_decfg; 124 125 u64 next_rip; 126 127 u64 spec_ctrl; 128 /* 129 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 130 * translated into the appropriate L2_CFG bits on the host to 131 * perform speculative control. 132 */ 133 u64 virt_spec_ctrl; 134 135 u32 *msrpm; 136 137 ulong nmi_iret_rip; 138 139 struct svm_nested_state nested; 140 141 bool nmi_singlestep; 142 u64 nmi_singlestep_guest_rflags; 143 144 unsigned int3_injected; 145 unsigned long int3_rip; 146 147 /* cached guest cpuid flags for faster access */ 148 bool nrips_enabled : 1; 149 150 u32 ldr_reg; 151 u32 dfr_reg; 152 struct page *avic_backing_page; 153 u64 *avic_physical_id_cache; 154 bool avic_is_running; 155 156 /* 157 * Per-vcpu list of struct amd_svm_iommu_ir: 158 * This is used mainly to store interrupt remapping information used 159 * when update the vcpu affinity. This avoids the need to scan for 160 * IRTE and try to match ga_tag in the IOMMU driver. 161 */ 162 struct list_head ir_list; 163 spinlock_t ir_list_lock; 164 165 /* Save desired MSR intercept (read: pass-through) state */ 166 struct { 167 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); 168 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); 169 } shadow_msr_intercept; 170 171 /* SEV-ES support */ 172 struct vmcb_save_area *vmsa; 173 struct ghcb *ghcb; 174 struct kvm_host_map ghcb_map; 175 bool received_first_sipi; 176 177 /* SEV-ES scratch area support */ 178 void *ghcb_sa; 179 u64 ghcb_sa_len; 180 bool ghcb_sa_sync; 181 bool ghcb_sa_free; 182 183 bool guest_state_loaded; 184 }; 185 186 struct svm_cpu_data { 187 int cpu; 188 189 u64 asid_generation; 190 u32 max_asid; 191 u32 next_asid; 192 u32 min_asid; 193 struct kvm_ldttss_desc *tss_desc; 194 195 struct page *save_area; 196 struct vmcb *current_vmcb; 197 198 /* index = sev_asid, value = vmcb pointer */ 199 struct vmcb **sev_vmcbs; 200 }; 201 202 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data); 203 204 void recalc_intercepts(struct vcpu_svm *svm); 205 206 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 207 { 208 return container_of(kvm, struct kvm_svm, kvm); 209 } 210 211 static inline bool sev_guest(struct kvm *kvm) 212 { 213 #ifdef CONFIG_KVM_AMD_SEV 214 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 215 216 return sev->active; 217 #else 218 return false; 219 #endif 220 } 221 222 static inline bool sev_es_guest(struct kvm *kvm) 223 { 224 #ifdef CONFIG_KVM_AMD_SEV 225 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 226 227 return sev_guest(kvm) && sev->es_active; 228 #else 229 return false; 230 #endif 231 } 232 233 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 234 { 235 vmcb->control.clean = 0; 236 } 237 238 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 239 { 240 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) 241 & ~VMCB_ALWAYS_DIRTY_MASK; 242 } 243 244 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 245 { 246 vmcb->control.clean &= ~(1 << bit); 247 } 248 249 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit) 250 { 251 return !test_bit(bit, (unsigned long *)&vmcb->control.clean); 252 } 253 254 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 255 { 256 return container_of(vcpu, struct vcpu_svm, vcpu); 257 } 258 259 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 260 { 261 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 262 __set_bit(bit, (unsigned long *)&control->intercepts); 263 } 264 265 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 266 { 267 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 268 __clear_bit(bit, (unsigned long *)&control->intercepts); 269 } 270 271 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 272 { 273 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 274 return test_bit(bit, (unsigned long *)&control->intercepts); 275 } 276 277 static inline void set_dr_intercepts(struct vcpu_svm *svm) 278 { 279 struct vmcb *vmcb = svm->vmcb01.ptr; 280 281 if (!sev_es_guest(svm->vcpu.kvm)) { 282 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ); 283 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ); 284 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ); 285 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ); 286 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ); 287 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ); 288 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ); 289 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE); 290 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE); 291 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE); 292 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE); 293 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE); 294 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE); 295 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); 296 } 297 298 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 299 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 300 301 recalc_intercepts(svm); 302 } 303 304 static inline void clr_dr_intercepts(struct vcpu_svm *svm) 305 { 306 struct vmcb *vmcb = svm->vmcb01.ptr; 307 308 vmcb->control.intercepts[INTERCEPT_DR] = 0; 309 310 /* DR7 access must remain intercepted for an SEV-ES guest */ 311 if (sev_es_guest(svm->vcpu.kvm)) { 312 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 313 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 314 } 315 316 recalc_intercepts(svm); 317 } 318 319 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 320 { 321 struct vmcb *vmcb = svm->vmcb01.ptr; 322 323 WARN_ON_ONCE(bit >= 32); 324 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 325 326 recalc_intercepts(svm); 327 } 328 329 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 330 { 331 struct vmcb *vmcb = svm->vmcb01.ptr; 332 333 WARN_ON_ONCE(bit >= 32); 334 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 335 336 recalc_intercepts(svm); 337 } 338 339 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 340 { 341 struct vmcb *vmcb = svm->vmcb01.ptr; 342 343 vmcb_set_intercept(&vmcb->control, bit); 344 345 recalc_intercepts(svm); 346 } 347 348 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 349 { 350 struct vmcb *vmcb = svm->vmcb01.ptr; 351 352 vmcb_clr_intercept(&vmcb->control, bit); 353 354 recalc_intercepts(svm); 355 } 356 357 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 358 { 359 return vmcb_is_intercept(&svm->vmcb->control, bit); 360 } 361 362 static inline bool vgif_enabled(struct vcpu_svm *svm) 363 { 364 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); 365 } 366 367 static inline void enable_gif(struct vcpu_svm *svm) 368 { 369 if (vgif_enabled(svm)) 370 svm->vmcb->control.int_ctl |= V_GIF_MASK; 371 else 372 svm->vcpu.arch.hflags |= HF_GIF_MASK; 373 } 374 375 static inline void disable_gif(struct vcpu_svm *svm) 376 { 377 if (vgif_enabled(svm)) 378 svm->vmcb->control.int_ctl &= ~V_GIF_MASK; 379 else 380 svm->vcpu.arch.hflags &= ~HF_GIF_MASK; 381 } 382 383 static inline bool gif_set(struct vcpu_svm *svm) 384 { 385 if (vgif_enabled(svm)) 386 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); 387 else 388 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); 389 } 390 391 /* svm.c */ 392 #define MSR_INVALID 0xffffffffU 393 394 extern bool dump_invalid_vmcb; 395 396 u32 svm_msrpm_offset(u32 msr); 397 u32 *svm_vcpu_alloc_msrpm(void); 398 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); 399 void svm_vcpu_free_msrpm(u32 *msrpm); 400 401 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 402 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 403 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 404 void svm_flush_tlb(struct kvm_vcpu *vcpu); 405 void disable_nmi_singlestep(struct vcpu_svm *svm); 406 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 407 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 408 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 409 void svm_set_gif(struct vcpu_svm *svm, bool value); 410 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 411 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 412 int read, int write); 413 414 /* nested.c */ 415 416 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 417 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 418 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 419 420 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 421 { 422 struct vcpu_svm *svm = to_svm(vcpu); 423 424 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 425 } 426 427 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 428 { 429 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 430 } 431 432 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 433 { 434 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 435 } 436 437 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 438 { 439 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 440 } 441 442 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, u64 vmcb_gpa, struct vmcb *vmcb12); 443 void svm_leave_nested(struct vcpu_svm *svm); 444 void svm_free_nested(struct vcpu_svm *svm); 445 int svm_allocate_nested(struct vcpu_svm *svm); 446 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 447 void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb); 448 int nested_svm_vmexit(struct vcpu_svm *svm); 449 450 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 451 { 452 svm->vmcb->control.exit_code = exit_code; 453 svm->vmcb->control.exit_info_1 = 0; 454 svm->vmcb->control.exit_info_2 = 0; 455 return nested_svm_vmexit(svm); 456 } 457 458 int nested_svm_exit_handled(struct vcpu_svm *svm); 459 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 460 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 461 bool has_error_code, u32 error_code); 462 int nested_svm_exit_special(struct vcpu_svm *svm); 463 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 464 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 465 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 466 467 extern struct kvm_x86_nested_ops svm_nested_ops; 468 469 /* avic.c */ 470 471 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) 472 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 473 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) 474 475 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) 476 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) 477 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) 478 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) 479 480 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 481 482 extern int avic; 483 484 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) 485 { 486 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; 487 vmcb_mark_dirty(svm->vmcb, VMCB_AVIC); 488 } 489 490 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) 491 { 492 struct vcpu_svm *svm = to_svm(vcpu); 493 u64 *entry = svm->avic_physical_id_cache; 494 495 if (!entry) 496 return false; 497 498 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); 499 } 500 501 int avic_ga_log_notifier(u32 ga_tag); 502 void avic_vm_destroy(struct kvm *kvm); 503 int avic_vm_init(struct kvm *kvm); 504 void avic_init_vmcb(struct vcpu_svm *svm); 505 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate); 506 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 507 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 508 int avic_init_vcpu(struct vcpu_svm *svm); 509 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 510 void avic_vcpu_put(struct kvm_vcpu *vcpu); 511 void avic_post_state_restore(struct kvm_vcpu *vcpu); 512 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 513 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 514 bool svm_check_apicv_inhibit_reasons(ulong bit); 515 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate); 516 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 517 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr); 518 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr); 519 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec); 520 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu); 521 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 522 uint32_t guest_irq, bool set); 523 void svm_vcpu_blocking(struct kvm_vcpu *vcpu); 524 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); 525 526 /* sev.c */ 527 528 #define GHCB_VERSION_MAX 1ULL 529 #define GHCB_VERSION_MIN 1ULL 530 531 #define GHCB_MSR_INFO_POS 0 532 #define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1) 533 534 #define GHCB_MSR_SEV_INFO_RESP 0x001 535 #define GHCB_MSR_SEV_INFO_REQ 0x002 536 #define GHCB_MSR_VER_MAX_POS 48 537 #define GHCB_MSR_VER_MAX_MASK 0xffff 538 #define GHCB_MSR_VER_MIN_POS 32 539 #define GHCB_MSR_VER_MIN_MASK 0xffff 540 #define GHCB_MSR_CBIT_POS 24 541 #define GHCB_MSR_CBIT_MASK 0xff 542 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ 543 ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ 544 (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ 545 (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ 546 GHCB_MSR_SEV_INFO_RESP) 547 548 #define GHCB_MSR_CPUID_REQ 0x004 549 #define GHCB_MSR_CPUID_RESP 0x005 550 #define GHCB_MSR_CPUID_FUNC_POS 32 551 #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff 552 #define GHCB_MSR_CPUID_VALUE_POS 32 553 #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff 554 #define GHCB_MSR_CPUID_REG_POS 30 555 #define GHCB_MSR_CPUID_REG_MASK 0x3 556 557 #define GHCB_MSR_TERM_REQ 0x100 558 #define GHCB_MSR_TERM_REASON_SET_POS 12 559 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf 560 #define GHCB_MSR_TERM_REASON_POS 16 561 #define GHCB_MSR_TERM_REASON_MASK 0xff 562 563 extern unsigned int max_sev_asid; 564 565 void sev_vm_destroy(struct kvm *kvm); 566 int svm_mem_enc_op(struct kvm *kvm, void __user *argp); 567 int svm_register_enc_region(struct kvm *kvm, 568 struct kvm_enc_region *range); 569 int svm_unregister_enc_region(struct kvm *kvm, 570 struct kvm_enc_region *range); 571 int svm_vm_copy_asid_from(struct kvm *kvm, unsigned int source_fd); 572 void pre_sev_run(struct vcpu_svm *svm, int cpu); 573 void __init sev_set_cpu_caps(void); 574 void __init sev_hardware_setup(void); 575 void sev_hardware_teardown(void); 576 int sev_cpu_init(struct svm_cpu_data *sd); 577 void sev_free_vcpu(struct kvm_vcpu *vcpu); 578 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 579 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 580 void sev_es_init_vmcb(struct vcpu_svm *svm); 581 void sev_es_create_vcpu(struct vcpu_svm *svm); 582 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 583 void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu); 584 585 /* vmenter.S */ 586 587 void __svm_sev_es_vcpu_run(unsigned long vmcb_pa); 588 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs); 589 590 #endif 591