1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #include "kvm_cache_regs.h" 26 27 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) 28 29 #define IOPM_SIZE PAGE_SIZE * 3 30 #define MSRPM_SIZE PAGE_SIZE * 2 31 32 #define MAX_DIRECT_ACCESS_MSRS 46 33 #define MSRPM_OFFSETS 32 34 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 35 extern bool npt_enabled; 36 extern int vgif; 37 extern bool intercept_smi; 38 extern bool x2avic_enabled; 39 40 /* 41 * Clean bits in VMCB. 42 * VMCB_ALL_CLEAN_MASK might also need to 43 * be updated if this enum is modified. 44 */ 45 enum { 46 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 47 pause filter count */ 48 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 49 VMCB_ASID, /* ASID */ 50 VMCB_INTR, /* int_ctl, int_vector */ 51 VMCB_NPT, /* npt_en, nCR3, gPAT */ 52 VMCB_CR, /* CR0, CR3, CR4, EFER */ 53 VMCB_DR, /* DR6, DR7 */ 54 VMCB_DT, /* GDT, IDT */ 55 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 56 VMCB_CR2, /* CR2 only */ 57 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 58 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 59 * AVIC PHYSICAL_TABLE pointer, 60 * AVIC LOGICAL_TABLE pointer 61 */ 62 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 63 }; 64 65 #define VMCB_ALL_CLEAN_MASK ( \ 66 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 67 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 68 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 69 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 70 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | \ 71 (1U << VMCB_SW)) 72 73 /* TPR and CR2 are always written before VMRUN */ 74 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 75 76 struct kvm_sev_info { 77 bool active; /* SEV enabled guest */ 78 bool es_active; /* SEV-ES enabled guest */ 79 unsigned int asid; /* ASID used for this guest */ 80 unsigned int handle; /* SEV firmware handle */ 81 int fd; /* SEV device fd */ 82 unsigned long pages_locked; /* Number of pages locked */ 83 struct list_head regions_list; /* List of registered regions */ 84 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 85 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 86 struct list_head mirror_vms; /* List of VMs mirroring */ 87 struct list_head mirror_entry; /* Use as a list entry of mirrors */ 88 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 89 atomic_t migration_in_progress; 90 }; 91 92 struct kvm_svm { 93 struct kvm kvm; 94 95 /* Struct members for AVIC */ 96 u32 avic_vm_id; 97 struct page *avic_logical_id_table_page; 98 struct page *avic_physical_id_table_page; 99 struct hlist_node hnode; 100 101 struct kvm_sev_info sev_info; 102 }; 103 104 struct kvm_vcpu; 105 106 struct kvm_vmcb_info { 107 struct vmcb *ptr; 108 unsigned long pa; 109 int cpu; 110 uint64_t asid_generation; 111 }; 112 113 struct vmcb_save_area_cached { 114 u64 efer; 115 u64 cr4; 116 u64 cr3; 117 u64 cr0; 118 u64 dr7; 119 u64 dr6; 120 }; 121 122 struct vmcb_ctrl_area_cached { 123 u32 intercepts[MAX_INTERCEPT]; 124 u16 pause_filter_thresh; 125 u16 pause_filter_count; 126 u64 iopm_base_pa; 127 u64 msrpm_base_pa; 128 u64 tsc_offset; 129 u32 asid; 130 u8 tlb_ctl; 131 u32 int_ctl; 132 u32 int_vector; 133 u32 int_state; 134 u32 exit_code; 135 u32 exit_code_hi; 136 u64 exit_info_1; 137 u64 exit_info_2; 138 u32 exit_int_info; 139 u32 exit_int_info_err; 140 u64 nested_ctl; 141 u32 event_inj; 142 u32 event_inj_err; 143 u64 next_rip; 144 u64 nested_cr3; 145 u64 virt_ext; 146 u32 clean; 147 union { 148 struct hv_vmcb_enlightenments hv_enlightenments; 149 u8 reserved_sw[32]; 150 }; 151 }; 152 153 struct svm_nested_state { 154 struct kvm_vmcb_info vmcb02; 155 u64 hsave_msr; 156 u64 vm_cr_msr; 157 u64 vmcb12_gpa; 158 u64 last_vmcb12_gpa; 159 160 /* These are the merged vectors */ 161 u32 *msrpm; 162 163 /* A VMRUN has started but has not yet been performed, so 164 * we cannot inject a nested vmexit yet. */ 165 bool nested_run_pending; 166 167 /* cache for control fields of the guest */ 168 struct vmcb_ctrl_area_cached ctl; 169 170 /* 171 * Note: this struct is not kept up-to-date while L2 runs; it is only 172 * valid within nested_svm_vmrun. 173 */ 174 struct vmcb_save_area_cached save; 175 176 bool initialized; 177 178 /* 179 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 180 * changes in MSR bitmap for L1 or switching to a different L2. Note, 181 * this flag can only be used reliably in conjunction with a paravirt L1 182 * which informs L0 whether any changes to MSR bitmap for L2 were done 183 * on its side. 184 */ 185 bool force_msr_bitmap_recalc; 186 }; 187 188 struct vcpu_sev_es_state { 189 /* SEV-ES support */ 190 struct sev_es_save_area *vmsa; 191 struct ghcb *ghcb; 192 struct kvm_host_map ghcb_map; 193 bool received_first_sipi; 194 195 /* SEV-ES scratch area support */ 196 void *ghcb_sa; 197 u32 ghcb_sa_len; 198 bool ghcb_sa_sync; 199 bool ghcb_sa_free; 200 }; 201 202 struct vcpu_svm { 203 struct kvm_vcpu vcpu; 204 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 205 struct vmcb *vmcb; 206 struct kvm_vmcb_info vmcb01; 207 struct kvm_vmcb_info *current_vmcb; 208 u32 asid; 209 u32 sysenter_esp_hi; 210 u32 sysenter_eip_hi; 211 uint64_t tsc_aux; 212 213 u64 msr_decfg; 214 215 u64 next_rip; 216 217 u64 spec_ctrl; 218 219 u64 tsc_ratio_msr; 220 /* 221 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 222 * translated into the appropriate L2_CFG bits on the host to 223 * perform speculative control. 224 */ 225 u64 virt_spec_ctrl; 226 227 u32 *msrpm; 228 229 ulong nmi_iret_rip; 230 231 struct svm_nested_state nested; 232 233 /* NMI mask value, used when vNMI is not enabled */ 234 bool nmi_masked; 235 236 /* 237 * True when NMIs are still masked but guest IRET was just intercepted 238 * and KVM is waiting for RIP to change, which will signal that the 239 * intercepted IRET was retired and thus NMI can be unmasked. 240 */ 241 bool awaiting_iret_completion; 242 243 /* 244 * Set when KVM is awaiting IRET completion and needs to inject NMIs as 245 * soon as the IRET completes (e.g. NMI is pending injection). KVM 246 * temporarily steals RFLAGS.TF to single-step the guest in this case 247 * in order to regain control as soon as the NMI-blocking condition 248 * goes away. 249 */ 250 bool nmi_singlestep; 251 u64 nmi_singlestep_guest_rflags; 252 253 bool nmi_l1_to_l2; 254 255 unsigned long soft_int_csbase; 256 unsigned long soft_int_old_rip; 257 unsigned long soft_int_next_rip; 258 bool soft_int_injected; 259 260 /* optional nested SVM features that are enabled for this guest */ 261 bool nrips_enabled : 1; 262 bool tsc_scaling_enabled : 1; 263 bool v_vmload_vmsave_enabled : 1; 264 bool lbrv_enabled : 1; 265 bool pause_filter_enabled : 1; 266 bool pause_threshold_enabled : 1; 267 bool vgif_enabled : 1; 268 269 u32 ldr_reg; 270 u32 dfr_reg; 271 struct page *avic_backing_page; 272 u64 *avic_physical_id_cache; 273 274 /* 275 * Per-vcpu list of struct amd_svm_iommu_ir: 276 * This is used mainly to store interrupt remapping information used 277 * when update the vcpu affinity. This avoids the need to scan for 278 * IRTE and try to match ga_tag in the IOMMU driver. 279 */ 280 struct list_head ir_list; 281 spinlock_t ir_list_lock; 282 283 /* Save desired MSR intercept (read: pass-through) state */ 284 struct { 285 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); 286 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); 287 } shadow_msr_intercept; 288 289 struct vcpu_sev_es_state sev_es; 290 291 bool guest_state_loaded; 292 293 bool x2avic_msrs_intercepted; 294 295 /* Guest GIF value, used when vGIF is not enabled */ 296 bool guest_gif; 297 }; 298 299 struct svm_cpu_data { 300 u64 asid_generation; 301 u32 max_asid; 302 u32 next_asid; 303 u32 min_asid; 304 struct kvm_ldttss_desc *tss_desc; 305 306 struct page *save_area; 307 unsigned long save_area_pa; 308 309 struct vmcb *current_vmcb; 310 311 /* index = sev_asid, value = vmcb pointer */ 312 struct vmcb **sev_vmcbs; 313 }; 314 315 DECLARE_PER_CPU(struct svm_cpu_data, svm_data); 316 317 void recalc_intercepts(struct vcpu_svm *svm); 318 319 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 320 { 321 return container_of(kvm, struct kvm_svm, kvm); 322 } 323 324 static __always_inline bool sev_guest(struct kvm *kvm) 325 { 326 #ifdef CONFIG_KVM_AMD_SEV 327 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 328 329 return sev->active; 330 #else 331 return false; 332 #endif 333 } 334 335 static __always_inline bool sev_es_guest(struct kvm *kvm) 336 { 337 #ifdef CONFIG_KVM_AMD_SEV 338 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 339 340 return sev->es_active && !WARN_ON_ONCE(!sev->active); 341 #else 342 return false; 343 #endif 344 } 345 346 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 347 { 348 vmcb->control.clean = 0; 349 } 350 351 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 352 { 353 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 354 & ~VMCB_ALWAYS_DIRTY_MASK; 355 } 356 357 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 358 { 359 vmcb->control.clean &= ~(1 << bit); 360 } 361 362 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit) 363 { 364 return !test_bit(bit, (unsigned long *)&vmcb->control.clean); 365 } 366 367 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 368 { 369 return container_of(vcpu, struct vcpu_svm, vcpu); 370 } 371 372 /* 373 * Only the PDPTRs are loaded on demand into the shadow MMU. All other 374 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap. 375 * 376 * CR3 might be out of date in the VMCB but it is not marked dirty; instead, 377 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3 378 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB. 379 */ 380 #define SVM_REGS_LAZY_LOAD_SET (1 << VCPU_EXREG_PDPTR) 381 382 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 383 { 384 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 385 __set_bit(bit, (unsigned long *)&control->intercepts); 386 } 387 388 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 389 { 390 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 391 __clear_bit(bit, (unsigned long *)&control->intercepts); 392 } 393 394 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 395 { 396 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 397 return test_bit(bit, (unsigned long *)&control->intercepts); 398 } 399 400 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 401 { 402 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 403 return test_bit(bit, (unsigned long *)&control->intercepts); 404 } 405 406 static inline void set_dr_intercepts(struct vcpu_svm *svm) 407 { 408 struct vmcb *vmcb = svm->vmcb01.ptr; 409 410 if (!sev_es_guest(svm->vcpu.kvm)) { 411 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ); 412 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ); 413 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ); 414 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ); 415 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ); 416 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ); 417 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ); 418 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE); 419 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE); 420 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE); 421 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE); 422 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE); 423 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE); 424 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); 425 } 426 427 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 428 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 429 430 recalc_intercepts(svm); 431 } 432 433 static inline void clr_dr_intercepts(struct vcpu_svm *svm) 434 { 435 struct vmcb *vmcb = svm->vmcb01.ptr; 436 437 vmcb->control.intercepts[INTERCEPT_DR] = 0; 438 439 /* DR7 access must remain intercepted for an SEV-ES guest */ 440 if (sev_es_guest(svm->vcpu.kvm)) { 441 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 442 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 443 } 444 445 recalc_intercepts(svm); 446 } 447 448 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 449 { 450 struct vmcb *vmcb = svm->vmcb01.ptr; 451 452 WARN_ON_ONCE(bit >= 32); 453 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 454 455 recalc_intercepts(svm); 456 } 457 458 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 459 { 460 struct vmcb *vmcb = svm->vmcb01.ptr; 461 462 WARN_ON_ONCE(bit >= 32); 463 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 464 465 recalc_intercepts(svm); 466 } 467 468 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 469 { 470 struct vmcb *vmcb = svm->vmcb01.ptr; 471 472 vmcb_set_intercept(&vmcb->control, bit); 473 474 recalc_intercepts(svm); 475 } 476 477 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 478 { 479 struct vmcb *vmcb = svm->vmcb01.ptr; 480 481 vmcb_clr_intercept(&vmcb->control, bit); 482 483 recalc_intercepts(svm); 484 } 485 486 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 487 { 488 return vmcb_is_intercept(&svm->vmcb->control, bit); 489 } 490 491 static inline bool nested_vgif_enabled(struct vcpu_svm *svm) 492 { 493 return svm->vgif_enabled && (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); 494 } 495 496 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm) 497 { 498 if (!vgif) 499 return NULL; 500 501 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm)) 502 return svm->nested.vmcb02.ptr; 503 else 504 return svm->vmcb01.ptr; 505 } 506 507 static inline void enable_gif(struct vcpu_svm *svm) 508 { 509 struct vmcb *vmcb = get_vgif_vmcb(svm); 510 511 if (vmcb) 512 vmcb->control.int_ctl |= V_GIF_MASK; 513 else 514 svm->guest_gif = true; 515 } 516 517 static inline void disable_gif(struct vcpu_svm *svm) 518 { 519 struct vmcb *vmcb = get_vgif_vmcb(svm); 520 521 if (vmcb) 522 vmcb->control.int_ctl &= ~V_GIF_MASK; 523 else 524 svm->guest_gif = false; 525 } 526 527 static inline bool gif_set(struct vcpu_svm *svm) 528 { 529 struct vmcb *vmcb = get_vgif_vmcb(svm); 530 531 if (vmcb) 532 return !!(vmcb->control.int_ctl & V_GIF_MASK); 533 else 534 return svm->guest_gif; 535 } 536 537 static inline bool nested_npt_enabled(struct vcpu_svm *svm) 538 { 539 return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE; 540 } 541 542 static inline bool is_x2apic_msrpm_offset(u32 offset) 543 { 544 /* 4 msrs per u8, and 4 u8 in u32 */ 545 u32 msr = offset * 16; 546 547 return (msr >= APIC_BASE_MSR) && 548 (msr < (APIC_BASE_MSR + 0x100)); 549 } 550 551 /* svm.c */ 552 #define MSR_INVALID 0xffffffffU 553 554 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) 555 556 extern bool dump_invalid_vmcb; 557 558 u32 svm_msrpm_offset(u32 msr); 559 u32 *svm_vcpu_alloc_msrpm(void); 560 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); 561 void svm_vcpu_free_msrpm(u32 *msrpm); 562 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 563 void svm_update_lbrv(struct kvm_vcpu *vcpu); 564 565 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 566 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 567 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 568 void disable_nmi_singlestep(struct vcpu_svm *svm); 569 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 570 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 571 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 572 void svm_set_gif(struct vcpu_svm *svm, bool value); 573 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 574 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 575 int read, int write); 576 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool disable); 577 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 578 int trig_mode, int vec); 579 580 /* nested.c */ 581 582 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 583 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 584 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 585 586 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 587 { 588 struct vcpu_svm *svm = to_svm(vcpu); 589 590 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 591 } 592 593 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 594 { 595 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 596 } 597 598 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 599 { 600 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 601 } 602 603 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 604 { 605 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 606 } 607 608 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, 609 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun); 610 void svm_leave_nested(struct kvm_vcpu *vcpu); 611 void svm_free_nested(struct vcpu_svm *svm); 612 int svm_allocate_nested(struct vcpu_svm *svm); 613 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 614 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 615 struct vmcb_save_area *from_save); 616 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 617 int nested_svm_vmexit(struct vcpu_svm *svm); 618 619 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 620 { 621 svm->vmcb->control.exit_code = exit_code; 622 svm->vmcb->control.exit_info_1 = 0; 623 svm->vmcb->control.exit_info_2 = 0; 624 return nested_svm_vmexit(svm); 625 } 626 627 int nested_svm_exit_handled(struct vcpu_svm *svm); 628 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 629 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 630 bool has_error_code, u32 error_code); 631 int nested_svm_exit_special(struct vcpu_svm *svm); 632 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 633 void __svm_write_tsc_multiplier(u64 multiplier); 634 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 635 struct vmcb_control_area *control); 636 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 637 struct vmcb_save_area *save); 638 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 639 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 640 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 641 642 extern struct kvm_x86_nested_ops svm_nested_ops; 643 644 /* avic.c */ 645 #define AVIC_REQUIRED_APICV_INHIBITS \ 646 ( \ 647 BIT(APICV_INHIBIT_REASON_DISABLE) | \ 648 BIT(APICV_INHIBIT_REASON_ABSENT) | \ 649 BIT(APICV_INHIBIT_REASON_HYPERV) | \ 650 BIT(APICV_INHIBIT_REASON_NESTED) | \ 651 BIT(APICV_INHIBIT_REASON_IRQWIN) | \ 652 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \ 653 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \ 654 BIT(APICV_INHIBIT_REASON_SEV) | \ 655 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ 656 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ 657 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ 658 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) \ 659 ) 660 661 bool avic_hardware_setup(void); 662 int avic_ga_log_notifier(u32 ga_tag); 663 void avic_vm_destroy(struct kvm *kvm); 664 int avic_vm_init(struct kvm *kvm); 665 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); 666 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 667 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 668 int avic_init_vcpu(struct vcpu_svm *svm); 669 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 670 void avic_vcpu_put(struct kvm_vcpu *vcpu); 671 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); 672 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 673 int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq, 674 uint32_t guest_irq, bool set); 675 void avic_vcpu_blocking(struct kvm_vcpu *vcpu); 676 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); 677 void avic_ring_doorbell(struct kvm_vcpu *vcpu); 678 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu); 679 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu); 680 681 682 /* sev.c */ 683 684 #define GHCB_VERSION_MAX 1ULL 685 #define GHCB_VERSION_MIN 1ULL 686 687 688 extern unsigned int max_sev_asid; 689 690 void sev_vm_destroy(struct kvm *kvm); 691 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp); 692 int sev_mem_enc_register_region(struct kvm *kvm, 693 struct kvm_enc_region *range); 694 int sev_mem_enc_unregister_region(struct kvm *kvm, 695 struct kvm_enc_region *range); 696 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd); 697 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd); 698 void sev_guest_memory_reclaimed(struct kvm *kvm); 699 700 void pre_sev_run(struct vcpu_svm *svm, int cpu); 701 void __init sev_set_cpu_caps(void); 702 void __init sev_hardware_setup(void); 703 void sev_hardware_unsetup(void); 704 int sev_cpu_init(struct svm_cpu_data *sd); 705 void sev_init_vmcb(struct vcpu_svm *svm); 706 void sev_free_vcpu(struct kvm_vcpu *vcpu); 707 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 708 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 709 void sev_es_vcpu_reset(struct vcpu_svm *svm); 710 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 711 void sev_es_prepare_switch_to_guest(struct sev_es_save_area *hostsa); 712 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 713 714 /* vmenter.S */ 715 716 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 717 void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 718 719 #endif 720