1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 24 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) 25 26 static const u32 host_save_user_msrs[] = { 27 MSR_TSC_AUX, 28 }; 29 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) 30 31 #define MAX_DIRECT_ACCESS_MSRS 18 32 #define MSRPM_OFFSETS 16 33 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 34 extern bool npt_enabled; 35 36 enum { 37 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 38 pause filter count */ 39 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 40 VMCB_ASID, /* ASID */ 41 VMCB_INTR, /* int_ctl, int_vector */ 42 VMCB_NPT, /* npt_en, nCR3, gPAT */ 43 VMCB_CR, /* CR0, CR3, CR4, EFER */ 44 VMCB_DR, /* DR6, DR7 */ 45 VMCB_DT, /* GDT, IDT */ 46 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 47 VMCB_CR2, /* CR2 only */ 48 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 49 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 50 * AVIC PHYSICAL_TABLE pointer, 51 * AVIC LOGICAL_TABLE pointer 52 */ 53 VMCB_DIRTY_MAX, 54 }; 55 56 /* TPR and CR2 are always written before VMRUN */ 57 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 58 59 struct kvm_sev_info { 60 bool active; /* SEV enabled guest */ 61 bool es_active; /* SEV-ES enabled guest */ 62 unsigned int asid; /* ASID used for this guest */ 63 unsigned int handle; /* SEV firmware handle */ 64 int fd; /* SEV device fd */ 65 unsigned long pages_locked; /* Number of pages locked */ 66 struct list_head regions_list; /* List of registered regions */ 67 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 68 }; 69 70 struct kvm_svm { 71 struct kvm kvm; 72 73 /* Struct members for AVIC */ 74 u32 avic_vm_id; 75 struct page *avic_logical_id_table_page; 76 struct page *avic_physical_id_table_page; 77 struct hlist_node hnode; 78 79 struct kvm_sev_info sev_info; 80 }; 81 82 struct kvm_vcpu; 83 84 struct svm_nested_state { 85 struct vmcb *hsave; 86 u64 hsave_msr; 87 u64 vm_cr_msr; 88 u64 vmcb12_gpa; 89 90 /* These are the merged vectors */ 91 u32 *msrpm; 92 93 /* A VMRUN has started but has not yet been performed, so 94 * we cannot inject a nested vmexit yet. */ 95 bool nested_run_pending; 96 97 /* cache for control fields of the guest */ 98 struct vmcb_control_area ctl; 99 100 bool initialized; 101 }; 102 103 struct vcpu_svm { 104 struct kvm_vcpu vcpu; 105 struct vmcb *vmcb; 106 unsigned long vmcb_pa; 107 struct svm_cpu_data *svm_data; 108 u32 asid; 109 uint64_t asid_generation; 110 uint64_t sysenter_esp; 111 uint64_t sysenter_eip; 112 uint64_t tsc_aux; 113 114 u64 msr_decfg; 115 116 u64 next_rip; 117 118 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; 119 120 u64 spec_ctrl; 121 /* 122 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 123 * translated into the appropriate L2_CFG bits on the host to 124 * perform speculative control. 125 */ 126 u64 virt_spec_ctrl; 127 128 u32 *msrpm; 129 130 ulong nmi_iret_rip; 131 132 struct svm_nested_state nested; 133 134 bool nmi_singlestep; 135 u64 nmi_singlestep_guest_rflags; 136 137 unsigned int3_injected; 138 unsigned long int3_rip; 139 140 /* cached guest cpuid flags for faster access */ 141 bool nrips_enabled : 1; 142 143 u32 ldr_reg; 144 u32 dfr_reg; 145 struct page *avic_backing_page; 146 u64 *avic_physical_id_cache; 147 bool avic_is_running; 148 149 /* 150 * Per-vcpu list of struct amd_svm_iommu_ir: 151 * This is used mainly to store interrupt remapping information used 152 * when update the vcpu affinity. This avoids the need to scan for 153 * IRTE and try to match ga_tag in the IOMMU driver. 154 */ 155 struct list_head ir_list; 156 spinlock_t ir_list_lock; 157 158 /* Save desired MSR intercept (read: pass-through) state */ 159 struct { 160 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); 161 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); 162 } shadow_msr_intercept; 163 164 /* SEV-ES support */ 165 struct vmcb_save_area *vmsa; 166 struct ghcb *ghcb; 167 struct kvm_host_map ghcb_map; 168 bool received_first_sipi; 169 170 /* SEV-ES scratch area support */ 171 void *ghcb_sa; 172 u64 ghcb_sa_len; 173 bool ghcb_sa_sync; 174 bool ghcb_sa_free; 175 176 bool guest_state_loaded; 177 }; 178 179 struct svm_cpu_data { 180 int cpu; 181 182 u64 asid_generation; 183 u32 max_asid; 184 u32 next_asid; 185 u32 min_asid; 186 struct kvm_ldttss_desc *tss_desc; 187 188 struct page *save_area; 189 struct vmcb *current_vmcb; 190 191 /* index = sev_asid, value = vmcb pointer */ 192 struct vmcb **sev_vmcbs; 193 }; 194 195 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data); 196 197 void recalc_intercepts(struct vcpu_svm *svm); 198 199 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 200 { 201 return container_of(kvm, struct kvm_svm, kvm); 202 } 203 204 static inline bool sev_guest(struct kvm *kvm) 205 { 206 #ifdef CONFIG_KVM_AMD_SEV 207 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 208 209 return sev->active; 210 #else 211 return false; 212 #endif 213 } 214 215 static inline bool sev_es_guest(struct kvm *kvm) 216 { 217 #ifdef CONFIG_KVM_AMD_SEV 218 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 219 220 return sev_guest(kvm) && sev->es_active; 221 #else 222 return false; 223 #endif 224 } 225 226 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 227 { 228 vmcb->control.clean = 0; 229 } 230 231 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 232 { 233 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) 234 & ~VMCB_ALWAYS_DIRTY_MASK; 235 } 236 237 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 238 { 239 vmcb->control.clean &= ~(1 << bit); 240 } 241 242 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 243 { 244 return container_of(vcpu, struct vcpu_svm, vcpu); 245 } 246 247 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) 248 { 249 if (is_guest_mode(&svm->vcpu)) 250 return svm->nested.hsave; 251 else 252 return svm->vmcb; 253 } 254 255 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 256 { 257 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 258 __set_bit(bit, (unsigned long *)&control->intercepts); 259 } 260 261 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 262 { 263 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 264 __clear_bit(bit, (unsigned long *)&control->intercepts); 265 } 266 267 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 268 { 269 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 270 return test_bit(bit, (unsigned long *)&control->intercepts); 271 } 272 273 static inline void set_dr_intercepts(struct vcpu_svm *svm) 274 { 275 struct vmcb *vmcb = get_host_vmcb(svm); 276 277 if (!sev_es_guest(svm->vcpu.kvm)) { 278 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ); 279 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ); 280 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ); 281 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ); 282 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ); 283 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ); 284 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ); 285 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE); 286 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE); 287 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE); 288 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE); 289 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE); 290 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE); 291 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); 292 } 293 294 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 295 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 296 297 recalc_intercepts(svm); 298 } 299 300 static inline void clr_dr_intercepts(struct vcpu_svm *svm) 301 { 302 struct vmcb *vmcb = get_host_vmcb(svm); 303 304 vmcb->control.intercepts[INTERCEPT_DR] = 0; 305 306 /* DR7 access must remain intercepted for an SEV-ES guest */ 307 if (sev_es_guest(svm->vcpu.kvm)) { 308 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 309 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 310 } 311 312 recalc_intercepts(svm); 313 } 314 315 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 316 { 317 struct vmcb *vmcb = get_host_vmcb(svm); 318 319 WARN_ON_ONCE(bit >= 32); 320 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 321 322 recalc_intercepts(svm); 323 } 324 325 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 326 { 327 struct vmcb *vmcb = get_host_vmcb(svm); 328 329 WARN_ON_ONCE(bit >= 32); 330 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 331 332 recalc_intercepts(svm); 333 } 334 335 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 336 { 337 struct vmcb *vmcb = get_host_vmcb(svm); 338 339 vmcb_set_intercept(&vmcb->control, bit); 340 341 recalc_intercepts(svm); 342 } 343 344 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 345 { 346 struct vmcb *vmcb = get_host_vmcb(svm); 347 348 vmcb_clr_intercept(&vmcb->control, bit); 349 350 recalc_intercepts(svm); 351 } 352 353 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 354 { 355 return vmcb_is_intercept(&svm->vmcb->control, bit); 356 } 357 358 static inline bool vgif_enabled(struct vcpu_svm *svm) 359 { 360 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); 361 } 362 363 static inline void enable_gif(struct vcpu_svm *svm) 364 { 365 if (vgif_enabled(svm)) 366 svm->vmcb->control.int_ctl |= V_GIF_MASK; 367 else 368 svm->vcpu.arch.hflags |= HF_GIF_MASK; 369 } 370 371 static inline void disable_gif(struct vcpu_svm *svm) 372 { 373 if (vgif_enabled(svm)) 374 svm->vmcb->control.int_ctl &= ~V_GIF_MASK; 375 else 376 svm->vcpu.arch.hflags &= ~HF_GIF_MASK; 377 } 378 379 static inline bool gif_set(struct vcpu_svm *svm) 380 { 381 if (vgif_enabled(svm)) 382 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); 383 else 384 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); 385 } 386 387 /* svm.c */ 388 #define MSR_INVALID 0xffffffffU 389 390 extern int sev; 391 extern int sev_es; 392 extern bool dump_invalid_vmcb; 393 394 u32 svm_msrpm_offset(u32 msr); 395 u32 *svm_vcpu_alloc_msrpm(void); 396 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); 397 void svm_vcpu_free_msrpm(u32 *msrpm); 398 399 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 400 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 401 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 402 void svm_flush_tlb(struct kvm_vcpu *vcpu); 403 void disable_nmi_singlestep(struct vcpu_svm *svm); 404 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 405 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 406 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 407 void svm_set_gif(struct vcpu_svm *svm, bool value); 408 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code); 409 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 410 int read, int write); 411 412 /* nested.c */ 413 414 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 415 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 416 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 417 418 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 419 { 420 struct vcpu_svm *svm = to_svm(vcpu); 421 422 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 423 } 424 425 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 426 { 427 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 428 } 429 430 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 431 { 432 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 433 } 434 435 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 436 { 437 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 438 } 439 440 int enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, 441 struct vmcb *nested_vmcb); 442 void svm_leave_nested(struct vcpu_svm *svm); 443 void svm_free_nested(struct vcpu_svm *svm); 444 int svm_allocate_nested(struct vcpu_svm *svm); 445 int nested_svm_vmrun(struct vcpu_svm *svm); 446 void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb); 447 int nested_svm_vmexit(struct vcpu_svm *svm); 448 int nested_svm_exit_handled(struct vcpu_svm *svm); 449 int nested_svm_check_permissions(struct vcpu_svm *svm); 450 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 451 bool has_error_code, u32 error_code); 452 int nested_svm_exit_special(struct vcpu_svm *svm); 453 void sync_nested_vmcb_control(struct vcpu_svm *svm); 454 455 extern struct kvm_x86_nested_ops svm_nested_ops; 456 457 /* avic.c */ 458 459 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) 460 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 461 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) 462 463 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) 464 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) 465 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) 466 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) 467 468 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 469 470 extern int avic; 471 472 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) 473 { 474 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; 475 vmcb_mark_dirty(svm->vmcb, VMCB_AVIC); 476 } 477 478 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) 479 { 480 struct vcpu_svm *svm = to_svm(vcpu); 481 u64 *entry = svm->avic_physical_id_cache; 482 483 if (!entry) 484 return false; 485 486 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); 487 } 488 489 int avic_ga_log_notifier(u32 ga_tag); 490 void avic_vm_destroy(struct kvm *kvm); 491 int avic_vm_init(struct kvm *kvm); 492 void avic_init_vmcb(struct vcpu_svm *svm); 493 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate); 494 int avic_incomplete_ipi_interception(struct vcpu_svm *svm); 495 int avic_unaccelerated_access_interception(struct vcpu_svm *svm); 496 int avic_init_vcpu(struct vcpu_svm *svm); 497 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 498 void avic_vcpu_put(struct kvm_vcpu *vcpu); 499 void avic_post_state_restore(struct kvm_vcpu *vcpu); 500 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 501 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 502 bool svm_check_apicv_inhibit_reasons(ulong bit); 503 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate); 504 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 505 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr); 506 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr); 507 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec); 508 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu); 509 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 510 uint32_t guest_irq, bool set); 511 void svm_vcpu_blocking(struct kvm_vcpu *vcpu); 512 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); 513 514 /* sev.c */ 515 516 #define GHCB_VERSION_MAX 1ULL 517 #define GHCB_VERSION_MIN 1ULL 518 519 #define GHCB_MSR_INFO_POS 0 520 #define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1) 521 522 #define GHCB_MSR_SEV_INFO_RESP 0x001 523 #define GHCB_MSR_SEV_INFO_REQ 0x002 524 #define GHCB_MSR_VER_MAX_POS 48 525 #define GHCB_MSR_VER_MAX_MASK 0xffff 526 #define GHCB_MSR_VER_MIN_POS 32 527 #define GHCB_MSR_VER_MIN_MASK 0xffff 528 #define GHCB_MSR_CBIT_POS 24 529 #define GHCB_MSR_CBIT_MASK 0xff 530 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ 531 ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ 532 (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ 533 (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ 534 GHCB_MSR_SEV_INFO_RESP) 535 536 #define GHCB_MSR_CPUID_REQ 0x004 537 #define GHCB_MSR_CPUID_RESP 0x005 538 #define GHCB_MSR_CPUID_FUNC_POS 32 539 #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff 540 #define GHCB_MSR_CPUID_VALUE_POS 32 541 #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff 542 #define GHCB_MSR_CPUID_REG_POS 30 543 #define GHCB_MSR_CPUID_REG_MASK 0x3 544 545 #define GHCB_MSR_TERM_REQ 0x100 546 #define GHCB_MSR_TERM_REASON_SET_POS 12 547 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf 548 #define GHCB_MSR_TERM_REASON_POS 16 549 #define GHCB_MSR_TERM_REASON_MASK 0xff 550 551 extern unsigned int max_sev_asid; 552 553 static inline bool svm_sev_enabled(void) 554 { 555 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0; 556 } 557 558 void sev_vm_destroy(struct kvm *kvm); 559 int svm_mem_enc_op(struct kvm *kvm, void __user *argp); 560 int svm_register_enc_region(struct kvm *kvm, 561 struct kvm_enc_region *range); 562 int svm_unregister_enc_region(struct kvm *kvm, 563 struct kvm_enc_region *range); 564 void pre_sev_run(struct vcpu_svm *svm, int cpu); 565 void __init sev_hardware_setup(void); 566 void sev_hardware_teardown(void); 567 void sev_free_vcpu(struct kvm_vcpu *vcpu); 568 int sev_handle_vmgexit(struct vcpu_svm *svm); 569 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 570 void sev_es_init_vmcb(struct vcpu_svm *svm); 571 void sev_es_create_vcpu(struct vcpu_svm *svm); 572 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 573 void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu); 574 575 /* vmenter.S */ 576 577 void __svm_sev_es_vcpu_run(unsigned long vmcb_pa); 578 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs); 579 580 #endif 581