1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) 26 27 #define IOPM_SIZE PAGE_SIZE * 3 28 #define MSRPM_SIZE PAGE_SIZE * 2 29 30 #define MAX_DIRECT_ACCESS_MSRS 20 31 #define MSRPM_OFFSETS 16 32 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 33 extern bool npt_enabled; 34 extern bool intercept_smi; 35 36 /* 37 * Clean bits in VMCB. 38 * VMCB_ALL_CLEAN_MASK might also need to 39 * be updated if this enum is modified. 40 */ 41 enum { 42 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 43 pause filter count */ 44 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 45 VMCB_ASID, /* ASID */ 46 VMCB_INTR, /* int_ctl, int_vector */ 47 VMCB_NPT, /* npt_en, nCR3, gPAT */ 48 VMCB_CR, /* CR0, CR3, CR4, EFER */ 49 VMCB_DR, /* DR6, DR7 */ 50 VMCB_DT, /* GDT, IDT */ 51 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 52 VMCB_CR2, /* CR2 only */ 53 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 54 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 55 * AVIC PHYSICAL_TABLE pointer, 56 * AVIC LOGICAL_TABLE pointer 57 */ 58 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 59 }; 60 61 #define VMCB_ALL_CLEAN_MASK ( \ 62 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 63 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 64 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 65 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 66 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | \ 67 (1U << VMCB_SW)) 68 69 /* TPR and CR2 are always written before VMRUN */ 70 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 71 72 struct kvm_sev_info { 73 bool active; /* SEV enabled guest */ 74 bool es_active; /* SEV-ES enabled guest */ 75 unsigned int asid; /* ASID used for this guest */ 76 unsigned int handle; /* SEV firmware handle */ 77 int fd; /* SEV device fd */ 78 unsigned long pages_locked; /* Number of pages locked */ 79 struct list_head regions_list; /* List of registered regions */ 80 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 81 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 82 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 83 atomic_t migration_in_progress; 84 }; 85 86 struct kvm_svm { 87 struct kvm kvm; 88 89 /* Struct members for AVIC */ 90 u32 avic_vm_id; 91 struct page *avic_logical_id_table_page; 92 struct page *avic_physical_id_table_page; 93 struct hlist_node hnode; 94 95 struct kvm_sev_info sev_info; 96 }; 97 98 struct kvm_vcpu; 99 100 struct kvm_vmcb_info { 101 struct vmcb *ptr; 102 unsigned long pa; 103 int cpu; 104 uint64_t asid_generation; 105 }; 106 107 struct svm_nested_state { 108 struct kvm_vmcb_info vmcb02; 109 u64 hsave_msr; 110 u64 vm_cr_msr; 111 u64 vmcb12_gpa; 112 u64 last_vmcb12_gpa; 113 114 /* These are the merged vectors */ 115 u32 *msrpm; 116 117 /* A VMRUN has started but has not yet been performed, so 118 * we cannot inject a nested vmexit yet. */ 119 bool nested_run_pending; 120 121 /* cache for control fields of the guest */ 122 struct vmcb_control_area ctl; 123 124 bool initialized; 125 }; 126 127 struct vcpu_sev_es_state { 128 /* SEV-ES support */ 129 struct vmcb_save_area *vmsa; 130 struct ghcb *ghcb; 131 struct kvm_host_map ghcb_map; 132 bool received_first_sipi; 133 134 /* SEV-ES scratch area support */ 135 void *ghcb_sa; 136 u32 ghcb_sa_len; 137 bool ghcb_sa_sync; 138 bool ghcb_sa_free; 139 }; 140 141 struct vcpu_svm { 142 struct kvm_vcpu vcpu; 143 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 144 struct vmcb *vmcb; 145 struct kvm_vmcb_info vmcb01; 146 struct kvm_vmcb_info *current_vmcb; 147 struct svm_cpu_data *svm_data; 148 u32 asid; 149 u32 sysenter_esp_hi; 150 u32 sysenter_eip_hi; 151 uint64_t tsc_aux; 152 153 u64 msr_decfg; 154 155 u64 next_rip; 156 157 u64 spec_ctrl; 158 159 u64 tsc_ratio_msr; 160 /* 161 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 162 * translated into the appropriate L2_CFG bits on the host to 163 * perform speculative control. 164 */ 165 u64 virt_spec_ctrl; 166 167 u32 *msrpm; 168 169 ulong nmi_iret_rip; 170 171 struct svm_nested_state nested; 172 173 bool nmi_singlestep; 174 u64 nmi_singlestep_guest_rflags; 175 176 unsigned int3_injected; 177 unsigned long int3_rip; 178 179 /* cached guest cpuid flags for faster access */ 180 bool nrips_enabled : 1; 181 bool tsc_scaling_enabled : 1; 182 183 u32 ldr_reg; 184 u32 dfr_reg; 185 struct page *avic_backing_page; 186 u64 *avic_physical_id_cache; 187 bool avic_is_running; 188 189 /* 190 * Per-vcpu list of struct amd_svm_iommu_ir: 191 * This is used mainly to store interrupt remapping information used 192 * when update the vcpu affinity. This avoids the need to scan for 193 * IRTE and try to match ga_tag in the IOMMU driver. 194 */ 195 struct list_head ir_list; 196 spinlock_t ir_list_lock; 197 198 /* Save desired MSR intercept (read: pass-through) state */ 199 struct { 200 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); 201 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); 202 } shadow_msr_intercept; 203 204 struct vcpu_sev_es_state sev_es; 205 206 bool guest_state_loaded; 207 }; 208 209 struct svm_cpu_data { 210 int cpu; 211 212 u64 asid_generation; 213 u32 max_asid; 214 u32 next_asid; 215 u32 min_asid; 216 struct kvm_ldttss_desc *tss_desc; 217 218 struct page *save_area; 219 struct vmcb *current_vmcb; 220 221 /* index = sev_asid, value = vmcb pointer */ 222 struct vmcb **sev_vmcbs; 223 }; 224 225 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data); 226 227 void recalc_intercepts(struct vcpu_svm *svm); 228 229 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 230 { 231 return container_of(kvm, struct kvm_svm, kvm); 232 } 233 234 static __always_inline bool sev_guest(struct kvm *kvm) 235 { 236 #ifdef CONFIG_KVM_AMD_SEV 237 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 238 239 return sev->active; 240 #else 241 return false; 242 #endif 243 } 244 245 static __always_inline bool sev_es_guest(struct kvm *kvm) 246 { 247 #ifdef CONFIG_KVM_AMD_SEV 248 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 249 250 return sev->es_active && !WARN_ON_ONCE(!sev->active); 251 #else 252 return false; 253 #endif 254 } 255 256 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 257 { 258 vmcb->control.clean = 0; 259 } 260 261 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 262 { 263 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 264 & ~VMCB_ALWAYS_DIRTY_MASK; 265 } 266 267 static inline bool vmcb_is_clean(struct vmcb *vmcb, int bit) 268 { 269 return (vmcb->control.clean & (1 << bit)); 270 } 271 272 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 273 { 274 vmcb->control.clean &= ~(1 << bit); 275 } 276 277 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit) 278 { 279 return !test_bit(bit, (unsigned long *)&vmcb->control.clean); 280 } 281 282 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 283 { 284 return container_of(vcpu, struct vcpu_svm, vcpu); 285 } 286 287 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 288 { 289 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 290 __set_bit(bit, (unsigned long *)&control->intercepts); 291 } 292 293 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 294 { 295 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 296 __clear_bit(bit, (unsigned long *)&control->intercepts); 297 } 298 299 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 300 { 301 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 302 return test_bit(bit, (unsigned long *)&control->intercepts); 303 } 304 305 static inline void set_dr_intercepts(struct vcpu_svm *svm) 306 { 307 struct vmcb *vmcb = svm->vmcb01.ptr; 308 309 if (!sev_es_guest(svm->vcpu.kvm)) { 310 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ); 311 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ); 312 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ); 313 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ); 314 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ); 315 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ); 316 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ); 317 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE); 318 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE); 319 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE); 320 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE); 321 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE); 322 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE); 323 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); 324 } 325 326 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 327 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 328 329 recalc_intercepts(svm); 330 } 331 332 static inline void clr_dr_intercepts(struct vcpu_svm *svm) 333 { 334 struct vmcb *vmcb = svm->vmcb01.ptr; 335 336 vmcb->control.intercepts[INTERCEPT_DR] = 0; 337 338 /* DR7 access must remain intercepted for an SEV-ES guest */ 339 if (sev_es_guest(svm->vcpu.kvm)) { 340 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 341 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 342 } 343 344 recalc_intercepts(svm); 345 } 346 347 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 348 { 349 struct vmcb *vmcb = svm->vmcb01.ptr; 350 351 WARN_ON_ONCE(bit >= 32); 352 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 353 354 recalc_intercepts(svm); 355 } 356 357 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 358 { 359 struct vmcb *vmcb = svm->vmcb01.ptr; 360 361 WARN_ON_ONCE(bit >= 32); 362 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 363 364 recalc_intercepts(svm); 365 } 366 367 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 368 { 369 struct vmcb *vmcb = svm->vmcb01.ptr; 370 371 vmcb_set_intercept(&vmcb->control, bit); 372 373 recalc_intercepts(svm); 374 } 375 376 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 377 { 378 struct vmcb *vmcb = svm->vmcb01.ptr; 379 380 vmcb_clr_intercept(&vmcb->control, bit); 381 382 recalc_intercepts(svm); 383 } 384 385 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 386 { 387 return vmcb_is_intercept(&svm->vmcb->control, bit); 388 } 389 390 static inline bool vgif_enabled(struct vcpu_svm *svm) 391 { 392 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); 393 } 394 395 static inline void enable_gif(struct vcpu_svm *svm) 396 { 397 if (vgif_enabled(svm)) 398 svm->vmcb->control.int_ctl |= V_GIF_MASK; 399 else 400 svm->vcpu.arch.hflags |= HF_GIF_MASK; 401 } 402 403 static inline void disable_gif(struct vcpu_svm *svm) 404 { 405 if (vgif_enabled(svm)) 406 svm->vmcb->control.int_ctl &= ~V_GIF_MASK; 407 else 408 svm->vcpu.arch.hflags &= ~HF_GIF_MASK; 409 } 410 411 static inline bool gif_set(struct vcpu_svm *svm) 412 { 413 if (vgif_enabled(svm)) 414 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); 415 else 416 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); 417 } 418 419 /* svm.c */ 420 #define MSR_INVALID 0xffffffffU 421 422 extern bool dump_invalid_vmcb; 423 424 u32 svm_msrpm_offset(u32 msr); 425 u32 *svm_vcpu_alloc_msrpm(void); 426 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); 427 void svm_vcpu_free_msrpm(u32 *msrpm); 428 429 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 430 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 431 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 432 void svm_flush_tlb(struct kvm_vcpu *vcpu); 433 void disable_nmi_singlestep(struct vcpu_svm *svm); 434 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 435 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 436 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 437 void svm_set_gif(struct vcpu_svm *svm, bool value); 438 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 439 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 440 int read, int write); 441 442 /* nested.c */ 443 444 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 445 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 446 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 447 448 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 449 { 450 struct vcpu_svm *svm = to_svm(vcpu); 451 452 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 453 } 454 455 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 456 { 457 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 458 } 459 460 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 461 { 462 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 463 } 464 465 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 466 { 467 return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 468 } 469 470 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, 471 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun); 472 void svm_leave_nested(struct vcpu_svm *svm); 473 void svm_free_nested(struct vcpu_svm *svm); 474 int svm_allocate_nested(struct vcpu_svm *svm); 475 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 476 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 477 struct vmcb_save_area *from_save); 478 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 479 int nested_svm_vmexit(struct vcpu_svm *svm); 480 481 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 482 { 483 svm->vmcb->control.exit_code = exit_code; 484 svm->vmcb->control.exit_info_1 = 0; 485 svm->vmcb->control.exit_info_2 = 0; 486 return nested_svm_vmexit(svm); 487 } 488 489 int nested_svm_exit_handled(struct vcpu_svm *svm); 490 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 491 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 492 bool has_error_code, u32 error_code); 493 int nested_svm_exit_special(struct vcpu_svm *svm); 494 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 495 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier); 496 void nested_load_control_from_vmcb12(struct vcpu_svm *svm, 497 struct vmcb_control_area *control); 498 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 499 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 500 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 501 502 extern struct kvm_x86_nested_ops svm_nested_ops; 503 504 /* avic.c */ 505 506 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) 507 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 508 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) 509 510 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) 511 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) 512 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) 513 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) 514 515 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 516 517 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) 518 { 519 struct vcpu_svm *svm = to_svm(vcpu); 520 u64 *entry = svm->avic_physical_id_cache; 521 522 if (!entry) 523 return false; 524 525 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); 526 } 527 528 int avic_ga_log_notifier(u32 ga_tag); 529 void avic_vm_destroy(struct kvm *kvm); 530 int avic_vm_init(struct kvm *kvm); 531 void avic_init_vmcb(struct vcpu_svm *svm); 532 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 533 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 534 int avic_init_vcpu(struct vcpu_svm *svm); 535 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 536 void avic_vcpu_put(struct kvm_vcpu *vcpu); 537 void avic_post_state_restore(struct kvm_vcpu *vcpu); 538 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 539 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 540 bool svm_check_apicv_inhibit_reasons(ulong bit); 541 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 542 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr); 543 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr); 544 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec); 545 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu); 546 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 547 uint32_t guest_irq, bool set); 548 void svm_vcpu_blocking(struct kvm_vcpu *vcpu); 549 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); 550 551 /* sev.c */ 552 553 #define GHCB_VERSION_MAX 1ULL 554 #define GHCB_VERSION_MIN 1ULL 555 556 557 extern unsigned int max_sev_asid; 558 559 void sev_vm_destroy(struct kvm *kvm); 560 int svm_mem_enc_op(struct kvm *kvm, void __user *argp); 561 int svm_register_enc_region(struct kvm *kvm, 562 struct kvm_enc_region *range); 563 int svm_unregister_enc_region(struct kvm *kvm, 564 struct kvm_enc_region *range); 565 int svm_vm_copy_asid_from(struct kvm *kvm, unsigned int source_fd); 566 int svm_vm_migrate_from(struct kvm *kvm, unsigned int source_fd); 567 void pre_sev_run(struct vcpu_svm *svm, int cpu); 568 void __init sev_set_cpu_caps(void); 569 void __init sev_hardware_setup(void); 570 void sev_hardware_teardown(void); 571 int sev_cpu_init(struct svm_cpu_data *sd); 572 void sev_free_vcpu(struct kvm_vcpu *vcpu); 573 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 574 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 575 void sev_es_init_vmcb(struct vcpu_svm *svm); 576 void sev_es_vcpu_reset(struct vcpu_svm *svm); 577 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 578 void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu); 579 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 580 581 /* vmenter.S */ 582 583 void __svm_sev_es_vcpu_run(unsigned long vmcb_pa); 584 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs); 585 586 #endif 587