1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 #include <linux/bits.h> 21 22 #include <asm/svm.h> 23 #include <asm/sev-common.h> 24 25 #include "kvm_cache_regs.h" 26 27 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT) 28 29 #define IOPM_SIZE PAGE_SIZE * 3 30 #define MSRPM_SIZE PAGE_SIZE * 2 31 32 #define MAX_DIRECT_ACCESS_MSRS 46 33 #define MSRPM_OFFSETS 32 34 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 35 extern bool npt_enabled; 36 extern int vgif; 37 extern bool intercept_smi; 38 extern bool x2avic_enabled; 39 extern bool vnmi; 40 41 /* 42 * Clean bits in VMCB. 43 * VMCB_ALL_CLEAN_MASK might also need to 44 * be updated if this enum is modified. 45 */ 46 enum { 47 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 48 pause filter count */ 49 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 50 VMCB_ASID, /* ASID */ 51 VMCB_INTR, /* int_ctl, int_vector */ 52 VMCB_NPT, /* npt_en, nCR3, gPAT */ 53 VMCB_CR, /* CR0, CR3, CR4, EFER */ 54 VMCB_DR, /* DR6, DR7 */ 55 VMCB_DT, /* GDT, IDT */ 56 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 57 VMCB_CR2, /* CR2 only */ 58 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 59 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 60 * AVIC PHYSICAL_TABLE pointer, 61 * AVIC LOGICAL_TABLE pointer 62 */ 63 VMCB_SW = 31, /* Reserved for hypervisor/software use */ 64 }; 65 66 #define VMCB_ALL_CLEAN_MASK ( \ 67 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \ 68 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \ 69 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \ 70 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \ 71 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | \ 72 (1U << VMCB_SW)) 73 74 /* TPR and CR2 are always written before VMRUN */ 75 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 76 77 struct kvm_sev_info { 78 bool active; /* SEV enabled guest */ 79 bool es_active; /* SEV-ES enabled guest */ 80 unsigned int asid; /* ASID used for this guest */ 81 unsigned int handle; /* SEV firmware handle */ 82 int fd; /* SEV device fd */ 83 unsigned long pages_locked; /* Number of pages locked */ 84 struct list_head regions_list; /* List of registered regions */ 85 u64 ap_jump_table; /* SEV-ES AP Jump Table address */ 86 struct kvm *enc_context_owner; /* Owner of copied encryption context */ 87 struct list_head mirror_vms; /* List of VMs mirroring */ 88 struct list_head mirror_entry; /* Use as a list entry of mirrors */ 89 struct misc_cg *misc_cg; /* For misc cgroup accounting */ 90 atomic_t migration_in_progress; 91 }; 92 93 struct kvm_svm { 94 struct kvm kvm; 95 96 /* Struct members for AVIC */ 97 u32 avic_vm_id; 98 struct page *avic_logical_id_table_page; 99 struct page *avic_physical_id_table_page; 100 struct hlist_node hnode; 101 102 struct kvm_sev_info sev_info; 103 }; 104 105 struct kvm_vcpu; 106 107 struct kvm_vmcb_info { 108 struct vmcb *ptr; 109 unsigned long pa; 110 int cpu; 111 uint64_t asid_generation; 112 }; 113 114 struct vmcb_save_area_cached { 115 u64 efer; 116 u64 cr4; 117 u64 cr3; 118 u64 cr0; 119 u64 dr7; 120 u64 dr6; 121 }; 122 123 struct vmcb_ctrl_area_cached { 124 u32 intercepts[MAX_INTERCEPT]; 125 u16 pause_filter_thresh; 126 u16 pause_filter_count; 127 u64 iopm_base_pa; 128 u64 msrpm_base_pa; 129 u64 tsc_offset; 130 u32 asid; 131 u8 tlb_ctl; 132 u32 int_ctl; 133 u32 int_vector; 134 u32 int_state; 135 u32 exit_code; 136 u32 exit_code_hi; 137 u64 exit_info_1; 138 u64 exit_info_2; 139 u32 exit_int_info; 140 u32 exit_int_info_err; 141 u64 nested_ctl; 142 u32 event_inj; 143 u32 event_inj_err; 144 u64 next_rip; 145 u64 nested_cr3; 146 u64 virt_ext; 147 u32 clean; 148 union { 149 struct hv_vmcb_enlightenments hv_enlightenments; 150 u8 reserved_sw[32]; 151 }; 152 }; 153 154 struct svm_nested_state { 155 struct kvm_vmcb_info vmcb02; 156 u64 hsave_msr; 157 u64 vm_cr_msr; 158 u64 vmcb12_gpa; 159 u64 last_vmcb12_gpa; 160 161 /* These are the merged vectors */ 162 u32 *msrpm; 163 164 /* A VMRUN has started but has not yet been performed, so 165 * we cannot inject a nested vmexit yet. */ 166 bool nested_run_pending; 167 168 /* cache for control fields of the guest */ 169 struct vmcb_ctrl_area_cached ctl; 170 171 /* 172 * Note: this struct is not kept up-to-date while L2 runs; it is only 173 * valid within nested_svm_vmrun. 174 */ 175 struct vmcb_save_area_cached save; 176 177 bool initialized; 178 179 /* 180 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 181 * changes in MSR bitmap for L1 or switching to a different L2. Note, 182 * this flag can only be used reliably in conjunction with a paravirt L1 183 * which informs L0 whether any changes to MSR bitmap for L2 were done 184 * on its side. 185 */ 186 bool force_msr_bitmap_recalc; 187 }; 188 189 struct vcpu_sev_es_state { 190 /* SEV-ES support */ 191 struct sev_es_save_area *vmsa; 192 struct ghcb *ghcb; 193 struct kvm_host_map ghcb_map; 194 bool received_first_sipi; 195 196 /* SEV-ES scratch area support */ 197 void *ghcb_sa; 198 u32 ghcb_sa_len; 199 bool ghcb_sa_sync; 200 bool ghcb_sa_free; 201 }; 202 203 struct vcpu_svm { 204 struct kvm_vcpu vcpu; 205 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */ 206 struct vmcb *vmcb; 207 struct kvm_vmcb_info vmcb01; 208 struct kvm_vmcb_info *current_vmcb; 209 u32 asid; 210 u32 sysenter_esp_hi; 211 u32 sysenter_eip_hi; 212 uint64_t tsc_aux; 213 214 u64 msr_decfg; 215 216 u64 next_rip; 217 218 u64 spec_ctrl; 219 220 u64 tsc_ratio_msr; 221 /* 222 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 223 * translated into the appropriate L2_CFG bits on the host to 224 * perform speculative control. 225 */ 226 u64 virt_spec_ctrl; 227 228 u32 *msrpm; 229 230 ulong nmi_iret_rip; 231 232 struct svm_nested_state nested; 233 234 /* NMI mask value, used when vNMI is not enabled */ 235 bool nmi_masked; 236 237 /* 238 * True when NMIs are still masked but guest IRET was just intercepted 239 * and KVM is waiting for RIP to change, which will signal that the 240 * intercepted IRET was retired and thus NMI can be unmasked. 241 */ 242 bool awaiting_iret_completion; 243 244 /* 245 * Set when KVM is awaiting IRET completion and needs to inject NMIs as 246 * soon as the IRET completes (e.g. NMI is pending injection). KVM 247 * temporarily steals RFLAGS.TF to single-step the guest in this case 248 * in order to regain control as soon as the NMI-blocking condition 249 * goes away. 250 */ 251 bool nmi_singlestep; 252 u64 nmi_singlestep_guest_rflags; 253 254 bool nmi_l1_to_l2; 255 256 unsigned long soft_int_csbase; 257 unsigned long soft_int_old_rip; 258 unsigned long soft_int_next_rip; 259 bool soft_int_injected; 260 261 /* optional nested SVM features that are enabled for this guest */ 262 bool nrips_enabled : 1; 263 bool tsc_scaling_enabled : 1; 264 bool v_vmload_vmsave_enabled : 1; 265 bool lbrv_enabled : 1; 266 bool pause_filter_enabled : 1; 267 bool pause_threshold_enabled : 1; 268 bool vgif_enabled : 1; 269 bool vnmi_enabled : 1; 270 271 u32 ldr_reg; 272 u32 dfr_reg; 273 struct page *avic_backing_page; 274 u64 *avic_physical_id_cache; 275 276 /* 277 * Per-vcpu list of struct amd_svm_iommu_ir: 278 * This is used mainly to store interrupt remapping information used 279 * when update the vcpu affinity. This avoids the need to scan for 280 * IRTE and try to match ga_tag in the IOMMU driver. 281 */ 282 struct list_head ir_list; 283 spinlock_t ir_list_lock; 284 285 /* Save desired MSR intercept (read: pass-through) state */ 286 struct { 287 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS); 288 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS); 289 } shadow_msr_intercept; 290 291 struct vcpu_sev_es_state sev_es; 292 293 bool guest_state_loaded; 294 295 bool x2avic_msrs_intercepted; 296 297 /* Guest GIF value, used when vGIF is not enabled */ 298 bool guest_gif; 299 }; 300 301 struct svm_cpu_data { 302 u64 asid_generation; 303 u32 max_asid; 304 u32 next_asid; 305 u32 min_asid; 306 struct kvm_ldttss_desc *tss_desc; 307 308 struct page *save_area; 309 unsigned long save_area_pa; 310 311 struct vmcb *current_vmcb; 312 313 /* index = sev_asid, value = vmcb pointer */ 314 struct vmcb **sev_vmcbs; 315 }; 316 317 DECLARE_PER_CPU(struct svm_cpu_data, svm_data); 318 319 void recalc_intercepts(struct vcpu_svm *svm); 320 321 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 322 { 323 return container_of(kvm, struct kvm_svm, kvm); 324 } 325 326 static __always_inline bool sev_guest(struct kvm *kvm) 327 { 328 #ifdef CONFIG_KVM_AMD_SEV 329 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 330 331 return sev->active; 332 #else 333 return false; 334 #endif 335 } 336 337 static __always_inline bool sev_es_guest(struct kvm *kvm) 338 { 339 #ifdef CONFIG_KVM_AMD_SEV 340 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 341 342 return sev->es_active && !WARN_ON_ONCE(!sev->active); 343 #else 344 return false; 345 #endif 346 } 347 348 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) 349 { 350 vmcb->control.clean = 0; 351 } 352 353 static inline void vmcb_mark_all_clean(struct vmcb *vmcb) 354 { 355 vmcb->control.clean = VMCB_ALL_CLEAN_MASK 356 & ~VMCB_ALWAYS_DIRTY_MASK; 357 } 358 359 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) 360 { 361 vmcb->control.clean &= ~(1 << bit); 362 } 363 364 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit) 365 { 366 return !test_bit(bit, (unsigned long *)&vmcb->control.clean); 367 } 368 369 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 370 { 371 return container_of(vcpu, struct vcpu_svm, vcpu); 372 } 373 374 /* 375 * Only the PDPTRs are loaded on demand into the shadow MMU. All other 376 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap. 377 * 378 * CR3 might be out of date in the VMCB but it is not marked dirty; instead, 379 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3 380 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB. 381 */ 382 #define SVM_REGS_LAZY_LOAD_SET (1 << VCPU_EXREG_PDPTR) 383 384 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit) 385 { 386 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 387 __set_bit(bit, (unsigned long *)&control->intercepts); 388 } 389 390 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit) 391 { 392 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 393 __clear_bit(bit, (unsigned long *)&control->intercepts); 394 } 395 396 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit) 397 { 398 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 399 return test_bit(bit, (unsigned long *)&control->intercepts); 400 } 401 402 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit) 403 { 404 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT); 405 return test_bit(bit, (unsigned long *)&control->intercepts); 406 } 407 408 static inline void set_dr_intercepts(struct vcpu_svm *svm) 409 { 410 struct vmcb *vmcb = svm->vmcb01.ptr; 411 412 if (!sev_es_guest(svm->vcpu.kvm)) { 413 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ); 414 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ); 415 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ); 416 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ); 417 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ); 418 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ); 419 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ); 420 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE); 421 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE); 422 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE); 423 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE); 424 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE); 425 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE); 426 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); 427 } 428 429 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 430 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 431 432 recalc_intercepts(svm); 433 } 434 435 static inline void clr_dr_intercepts(struct vcpu_svm *svm) 436 { 437 struct vmcb *vmcb = svm->vmcb01.ptr; 438 439 vmcb->control.intercepts[INTERCEPT_DR] = 0; 440 441 /* DR7 access must remain intercepted for an SEV-ES guest */ 442 if (sev_es_guest(svm->vcpu.kvm)) { 443 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); 444 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); 445 } 446 447 recalc_intercepts(svm); 448 } 449 450 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit) 451 { 452 struct vmcb *vmcb = svm->vmcb01.ptr; 453 454 WARN_ON_ONCE(bit >= 32); 455 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 456 457 recalc_intercepts(svm); 458 } 459 460 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit) 461 { 462 struct vmcb *vmcb = svm->vmcb01.ptr; 463 464 WARN_ON_ONCE(bit >= 32); 465 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit); 466 467 recalc_intercepts(svm); 468 } 469 470 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit) 471 { 472 struct vmcb *vmcb = svm->vmcb01.ptr; 473 474 vmcb_set_intercept(&vmcb->control, bit); 475 476 recalc_intercepts(svm); 477 } 478 479 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit) 480 { 481 struct vmcb *vmcb = svm->vmcb01.ptr; 482 483 vmcb_clr_intercept(&vmcb->control, bit); 484 485 recalc_intercepts(svm); 486 } 487 488 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit) 489 { 490 return vmcb_is_intercept(&svm->vmcb->control, bit); 491 } 492 493 static inline bool nested_vgif_enabled(struct vcpu_svm *svm) 494 { 495 return svm->vgif_enabled && (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); 496 } 497 498 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm) 499 { 500 if (!vgif) 501 return NULL; 502 503 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm)) 504 return svm->nested.vmcb02.ptr; 505 else 506 return svm->vmcb01.ptr; 507 } 508 509 static inline void enable_gif(struct vcpu_svm *svm) 510 { 511 struct vmcb *vmcb = get_vgif_vmcb(svm); 512 513 if (vmcb) 514 vmcb->control.int_ctl |= V_GIF_MASK; 515 else 516 svm->guest_gif = true; 517 } 518 519 static inline void disable_gif(struct vcpu_svm *svm) 520 { 521 struct vmcb *vmcb = get_vgif_vmcb(svm); 522 523 if (vmcb) 524 vmcb->control.int_ctl &= ~V_GIF_MASK; 525 else 526 svm->guest_gif = false; 527 } 528 529 static inline bool gif_set(struct vcpu_svm *svm) 530 { 531 struct vmcb *vmcb = get_vgif_vmcb(svm); 532 533 if (vmcb) 534 return !!(vmcb->control.int_ctl & V_GIF_MASK); 535 else 536 return svm->guest_gif; 537 } 538 539 static inline bool nested_npt_enabled(struct vcpu_svm *svm) 540 { 541 return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE; 542 } 543 544 static inline bool nested_vnmi_enabled(struct vcpu_svm *svm) 545 { 546 return svm->vnmi_enabled && 547 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK); 548 } 549 550 static inline bool is_x2apic_msrpm_offset(u32 offset) 551 { 552 /* 4 msrs per u8, and 4 u8 in u32 */ 553 u32 msr = offset * 16; 554 555 return (msr >= APIC_BASE_MSR) && 556 (msr < (APIC_BASE_MSR + 0x100)); 557 } 558 559 static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm) 560 { 561 if (!vnmi) 562 return NULL; 563 564 if (is_guest_mode(&svm->vcpu)) 565 return NULL; 566 else 567 return svm->vmcb01.ptr; 568 } 569 570 static inline bool is_vnmi_enabled(struct vcpu_svm *svm) 571 { 572 struct vmcb *vmcb = get_vnmi_vmcb_l1(svm); 573 574 if (vmcb) 575 return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK); 576 else 577 return false; 578 } 579 580 /* svm.c */ 581 #define MSR_INVALID 0xffffffffU 582 583 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) 584 585 extern bool dump_invalid_vmcb; 586 587 u32 svm_msrpm_offset(u32 msr); 588 u32 *svm_vcpu_alloc_msrpm(void); 589 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); 590 void svm_vcpu_free_msrpm(u32 *msrpm); 591 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 592 void svm_update_lbrv(struct kvm_vcpu *vcpu); 593 594 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 595 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 596 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 597 void disable_nmi_singlestep(struct vcpu_svm *svm); 598 bool svm_smi_blocked(struct kvm_vcpu *vcpu); 599 bool svm_nmi_blocked(struct kvm_vcpu *vcpu); 600 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); 601 void svm_set_gif(struct vcpu_svm *svm, bool value); 602 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); 603 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr, 604 int read, int write); 605 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool disable); 606 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode, 607 int trig_mode, int vec); 608 609 /* nested.c */ 610 611 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 612 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 613 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 614 615 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu) 616 { 617 struct vcpu_svm *svm = to_svm(vcpu); 618 619 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); 620 } 621 622 static inline bool nested_exit_on_smi(struct vcpu_svm *svm) 623 { 624 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); 625 } 626 627 static inline bool nested_exit_on_intr(struct vcpu_svm *svm) 628 { 629 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); 630 } 631 632 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm) 633 { 634 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); 635 } 636 637 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, 638 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun); 639 void svm_leave_nested(struct kvm_vcpu *vcpu); 640 void svm_free_nested(struct vcpu_svm *svm); 641 int svm_allocate_nested(struct vcpu_svm *svm); 642 int nested_svm_vmrun(struct kvm_vcpu *vcpu); 643 void svm_copy_vmrun_state(struct vmcb_save_area *to_save, 644 struct vmcb_save_area *from_save); 645 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); 646 int nested_svm_vmexit(struct vcpu_svm *svm); 647 648 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) 649 { 650 svm->vmcb->control.exit_code = exit_code; 651 svm->vmcb->control.exit_info_1 = 0; 652 svm->vmcb->control.exit_info_2 = 0; 653 return nested_svm_vmexit(svm); 654 } 655 656 int nested_svm_exit_handled(struct vcpu_svm *svm); 657 int nested_svm_check_permissions(struct kvm_vcpu *vcpu); 658 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 659 bool has_error_code, u32 error_code); 660 int nested_svm_exit_special(struct vcpu_svm *svm); 661 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu); 662 void __svm_write_tsc_multiplier(u64 multiplier); 663 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm, 664 struct vmcb_control_area *control); 665 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm, 666 struct vmcb_save_area *save); 667 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); 668 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); 669 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); 670 671 extern struct kvm_x86_nested_ops svm_nested_ops; 672 673 /* avic.c */ 674 #define AVIC_REQUIRED_APICV_INHIBITS \ 675 ( \ 676 BIT(APICV_INHIBIT_REASON_DISABLE) | \ 677 BIT(APICV_INHIBIT_REASON_ABSENT) | \ 678 BIT(APICV_INHIBIT_REASON_HYPERV) | \ 679 BIT(APICV_INHIBIT_REASON_NESTED) | \ 680 BIT(APICV_INHIBIT_REASON_IRQWIN) | \ 681 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \ 682 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \ 683 BIT(APICV_INHIBIT_REASON_SEV) | \ 684 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ 685 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ 686 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ 687 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) \ 688 ) 689 690 bool avic_hardware_setup(void); 691 int avic_ga_log_notifier(u32 ga_tag); 692 void avic_vm_destroy(struct kvm *kvm); 693 int avic_vm_init(struct kvm *kvm); 694 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); 695 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu); 696 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu); 697 int avic_init_vcpu(struct vcpu_svm *svm); 698 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 699 void avic_vcpu_put(struct kvm_vcpu *vcpu); 700 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); 701 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 702 int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq, 703 uint32_t guest_irq, bool set); 704 void avic_vcpu_blocking(struct kvm_vcpu *vcpu); 705 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); 706 void avic_ring_doorbell(struct kvm_vcpu *vcpu); 707 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu); 708 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu); 709 710 711 /* sev.c */ 712 713 #define GHCB_VERSION_MAX 1ULL 714 #define GHCB_VERSION_MIN 1ULL 715 716 717 extern unsigned int max_sev_asid; 718 719 void sev_vm_destroy(struct kvm *kvm); 720 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp); 721 int sev_mem_enc_register_region(struct kvm *kvm, 722 struct kvm_enc_region *range); 723 int sev_mem_enc_unregister_region(struct kvm *kvm, 724 struct kvm_enc_region *range); 725 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd); 726 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd); 727 void sev_guest_memory_reclaimed(struct kvm *kvm); 728 729 void pre_sev_run(struct vcpu_svm *svm, int cpu); 730 void __init sev_set_cpu_caps(void); 731 void __init sev_hardware_setup(void); 732 void sev_hardware_unsetup(void); 733 int sev_cpu_init(struct svm_cpu_data *sd); 734 void sev_init_vmcb(struct vcpu_svm *svm); 735 void sev_free_vcpu(struct kvm_vcpu *vcpu); 736 int sev_handle_vmgexit(struct kvm_vcpu *vcpu); 737 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in); 738 void sev_es_vcpu_reset(struct vcpu_svm *svm); 739 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); 740 void sev_es_prepare_switch_to_guest(struct sev_es_save_area *hostsa); 741 void sev_es_unmap_ghcb(struct vcpu_svm *svm); 742 743 /* vmenter.S */ 744 745 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 746 void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted); 747 748 #endif 749