1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #define pr_fmt(fmt) "SVM: " fmt 16 17 #include <linux/kvm_types.h> 18 #include <linux/hashtable.h> 19 #include <linux/amd-iommu.h> 20 #include <linux/kvm_host.h> 21 22 #include <asm/irq_remapping.h> 23 24 #include "trace.h" 25 #include "lapic.h" 26 #include "x86.h" 27 #include "irq.h" 28 #include "svm.h" 29 30 /* enable / disable AVIC */ 31 int avic; 32 #ifdef CONFIG_X86_LOCAL_APIC 33 module_param(avic, int, S_IRUGO); 34 #endif 35 36 #define SVM_AVIC_DOORBELL 0xc001011b 37 38 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) 39 40 /* 41 * 0xff is broadcast, so the max index allowed for physical APIC ID 42 * table is 0xfe. APIC IDs above 0xff are reserved. 43 */ 44 #define AVIC_MAX_PHYSICAL_ID_COUNT 255 45 46 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 47 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 48 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF 49 50 /* AVIC GATAG is encoded using VM and VCPU IDs */ 51 #define AVIC_VCPU_ID_BITS 8 52 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1) 53 54 #define AVIC_VM_ID_BITS 24 55 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS) 56 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1) 57 58 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \ 59 (y & AVIC_VCPU_ID_MASK)) 60 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK) 61 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) 62 63 /* Note: 64 * This hash table is used to map VM_ID to a struct kvm_svm, 65 * when handling AMD IOMMU GALOG notification to schedule in 66 * a particular vCPU. 67 */ 68 #define SVM_VM_DATA_HASH_BITS 8 69 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS); 70 static u32 next_vm_id = 0; 71 static bool next_vm_id_wrapped = 0; 72 static DEFINE_SPINLOCK(svm_vm_data_hash_lock); 73 74 /* 75 * This is a wrapper of struct amd_iommu_ir_data. 76 */ 77 struct amd_svm_iommu_ir { 78 struct list_head node; /* Used by SVM for per-vcpu ir_list */ 79 void *data; /* Storing pointer to struct amd_ir_data */ 80 }; 81 82 enum avic_ipi_failure_cause { 83 AVIC_IPI_FAILURE_INVALID_INT_TYPE, 84 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, 85 AVIC_IPI_FAILURE_INVALID_TARGET, 86 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, 87 }; 88 89 /* Note: 90 * This function is called from IOMMU driver to notify 91 * SVM to schedule in a particular vCPU of a particular VM. 92 */ 93 int avic_ga_log_notifier(u32 ga_tag) 94 { 95 unsigned long flags; 96 struct kvm_svm *kvm_svm; 97 struct kvm_vcpu *vcpu = NULL; 98 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag); 99 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag); 100 101 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id); 102 trace_kvm_avic_ga_log(vm_id, vcpu_id); 103 104 spin_lock_irqsave(&svm_vm_data_hash_lock, flags); 105 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) { 106 if (kvm_svm->avic_vm_id != vm_id) 107 continue; 108 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id); 109 break; 110 } 111 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); 112 113 /* Note: 114 * At this point, the IOMMU should have already set the pending 115 * bit in the vAPIC backing page. So, we just need to schedule 116 * in the vcpu. 117 */ 118 if (vcpu) 119 kvm_vcpu_wake_up(vcpu); 120 121 return 0; 122 } 123 124 void avic_vm_destroy(struct kvm *kvm) 125 { 126 unsigned long flags; 127 struct kvm_svm *kvm_svm = to_kvm_svm(kvm); 128 129 if (!avic) 130 return; 131 132 if (kvm_svm->avic_logical_id_table_page) 133 __free_page(kvm_svm->avic_logical_id_table_page); 134 if (kvm_svm->avic_physical_id_table_page) 135 __free_page(kvm_svm->avic_physical_id_table_page); 136 137 spin_lock_irqsave(&svm_vm_data_hash_lock, flags); 138 hash_del(&kvm_svm->hnode); 139 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); 140 } 141 142 int avic_vm_init(struct kvm *kvm) 143 { 144 unsigned long flags; 145 int err = -ENOMEM; 146 struct kvm_svm *kvm_svm = to_kvm_svm(kvm); 147 struct kvm_svm *k2; 148 struct page *p_page; 149 struct page *l_page; 150 u32 vm_id; 151 152 if (!avic) 153 return 0; 154 155 /* Allocating physical APIC ID table (4KB) */ 156 p_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 157 if (!p_page) 158 goto free_avic; 159 160 kvm_svm->avic_physical_id_table_page = p_page; 161 162 /* Allocating logical APIC ID table (4KB) */ 163 l_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 164 if (!l_page) 165 goto free_avic; 166 167 kvm_svm->avic_logical_id_table_page = l_page; 168 169 spin_lock_irqsave(&svm_vm_data_hash_lock, flags); 170 again: 171 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK; 172 if (vm_id == 0) { /* id is 1-based, zero is not okay */ 173 next_vm_id_wrapped = 1; 174 goto again; 175 } 176 /* Is it still in use? Only possible if wrapped at least once */ 177 if (next_vm_id_wrapped) { 178 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) { 179 if (k2->avic_vm_id == vm_id) 180 goto again; 181 } 182 } 183 kvm_svm->avic_vm_id = vm_id; 184 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id); 185 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); 186 187 return 0; 188 189 free_avic: 190 avic_vm_destroy(kvm); 191 return err; 192 } 193 194 void avic_init_vmcb(struct vcpu_svm *svm) 195 { 196 struct vmcb *vmcb = svm->vmcb; 197 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm); 198 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page)); 199 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page)); 200 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page)); 201 202 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK; 203 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK; 204 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK; 205 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT; 206 if (kvm_apicv_activated(svm->vcpu.kvm)) 207 vmcb->control.int_ctl |= AVIC_ENABLE_MASK; 208 else 209 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; 210 } 211 212 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, 213 unsigned int index) 214 { 215 u64 *avic_physical_id_table; 216 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm); 217 218 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT) 219 return NULL; 220 221 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page); 222 223 return &avic_physical_id_table[index]; 224 } 225 226 /** 227 * Note: 228 * AVIC hardware walks the nested page table to check permissions, 229 * but does not use the SPA address specified in the leaf page 230 * table entry since it uses address in the AVIC_BACKING_PAGE pointer 231 * field of the VMCB. Therefore, we set up the 232 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here. 233 */ 234 static int avic_update_access_page(struct kvm *kvm, bool activate) 235 { 236 void __user *ret; 237 int r = 0; 238 239 mutex_lock(&kvm->slots_lock); 240 /* 241 * During kvm_destroy_vm(), kvm_pit_set_reinject() could trigger 242 * APICv mode change, which update APIC_ACCESS_PAGE_PRIVATE_MEMSLOT 243 * memory region. So, we need to ensure that kvm->mm == current->mm. 244 */ 245 if ((kvm->arch.apic_access_page_done == activate) || 246 (kvm->mm != current->mm)) 247 goto out; 248 249 ret = __x86_set_memory_region(kvm, 250 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 251 APIC_DEFAULT_PHYS_BASE, 252 activate ? PAGE_SIZE : 0); 253 if (IS_ERR(ret)) { 254 r = PTR_ERR(ret); 255 goto out; 256 } 257 258 kvm->arch.apic_access_page_done = activate; 259 out: 260 mutex_unlock(&kvm->slots_lock); 261 return r; 262 } 263 264 static int avic_init_backing_page(struct kvm_vcpu *vcpu) 265 { 266 u64 *entry, new_entry; 267 int id = vcpu->vcpu_id; 268 struct vcpu_svm *svm = to_svm(vcpu); 269 270 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT) 271 return -EINVAL; 272 273 if (!svm->vcpu.arch.apic->regs) 274 return -EINVAL; 275 276 if (kvm_apicv_activated(vcpu->kvm)) { 277 int ret; 278 279 ret = avic_update_access_page(vcpu->kvm, true); 280 if (ret) 281 return ret; 282 } 283 284 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); 285 286 /* Setting AVIC backing page address in the phy APIC ID table */ 287 entry = avic_get_physical_id_entry(vcpu, id); 288 if (!entry) 289 return -EINVAL; 290 291 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) & 292 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | 293 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); 294 WRITE_ONCE(*entry, new_entry); 295 296 svm->avic_physical_id_cache = entry; 297 298 return 0; 299 } 300 301 int avic_incomplete_ipi_interception(struct vcpu_svm *svm) 302 { 303 u32 icrh = svm->vmcb->control.exit_info_1 >> 32; 304 u32 icrl = svm->vmcb->control.exit_info_1; 305 u32 id = svm->vmcb->control.exit_info_2 >> 32; 306 u32 index = svm->vmcb->control.exit_info_2 & 0xFF; 307 struct kvm_lapic *apic = svm->vcpu.arch.apic; 308 309 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index); 310 311 switch (id) { 312 case AVIC_IPI_FAILURE_INVALID_INT_TYPE: 313 /* 314 * AVIC hardware handles the generation of 315 * IPIs when the specified Message Type is Fixed 316 * (also known as fixed delivery mode) and 317 * the Trigger Mode is edge-triggered. The hardware 318 * also supports self and broadcast delivery modes 319 * specified via the Destination Shorthand(DSH) 320 * field of the ICRL. Logical and physical APIC ID 321 * formats are supported. All other IPI types cause 322 * a #VMEXIT, which needs to emulated. 323 */ 324 kvm_lapic_reg_write(apic, APIC_ICR2, icrh); 325 kvm_lapic_reg_write(apic, APIC_ICR, icrl); 326 break; 327 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: { 328 int i; 329 struct kvm_vcpu *vcpu; 330 struct kvm *kvm = svm->vcpu.kvm; 331 struct kvm_lapic *apic = svm->vcpu.arch.apic; 332 333 /* 334 * At this point, we expect that the AVIC HW has already 335 * set the appropriate IRR bits on the valid target 336 * vcpus. So, we just need to kick the appropriate vcpu. 337 */ 338 kvm_for_each_vcpu(i, vcpu, kvm) { 339 bool m = kvm_apic_match_dest(vcpu, apic, 340 icrl & APIC_SHORT_MASK, 341 GET_APIC_DEST_FIELD(icrh), 342 icrl & APIC_DEST_MASK); 343 344 if (m && !avic_vcpu_is_running(vcpu)) 345 kvm_vcpu_wake_up(vcpu); 346 } 347 break; 348 } 349 case AVIC_IPI_FAILURE_INVALID_TARGET: 350 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n", 351 index, svm->vcpu.vcpu_id, icrh, icrl); 352 break; 353 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE: 354 WARN_ONCE(1, "Invalid backing page\n"); 355 break; 356 default: 357 pr_err("Unknown IPI interception\n"); 358 } 359 360 return 1; 361 } 362 363 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat) 364 { 365 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm); 366 int index; 367 u32 *logical_apic_id_table; 368 int dlid = GET_APIC_LOGICAL_ID(ldr); 369 370 if (!dlid) 371 return NULL; 372 373 if (flat) { /* flat */ 374 index = ffs(dlid) - 1; 375 if (index > 7) 376 return NULL; 377 } else { /* cluster */ 378 int cluster = (dlid & 0xf0) >> 4; 379 int apic = ffs(dlid & 0x0f) - 1; 380 381 if ((apic < 0) || (apic > 7) || 382 (cluster >= 0xf)) 383 return NULL; 384 index = (cluster << 2) + apic; 385 } 386 387 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page); 388 389 return &logical_apic_id_table[index]; 390 } 391 392 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr) 393 { 394 bool flat; 395 u32 *entry, new_entry; 396 397 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; 398 entry = avic_get_logical_id_entry(vcpu, ldr, flat); 399 if (!entry) 400 return -EINVAL; 401 402 new_entry = READ_ONCE(*entry); 403 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK; 404 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK); 405 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK; 406 WRITE_ONCE(*entry, new_entry); 407 408 return 0; 409 } 410 411 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu) 412 { 413 struct vcpu_svm *svm = to_svm(vcpu); 414 bool flat = svm->dfr_reg == APIC_DFR_FLAT; 415 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat); 416 417 if (entry) 418 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry); 419 } 420 421 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu) 422 { 423 int ret = 0; 424 struct vcpu_svm *svm = to_svm(vcpu); 425 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); 426 u32 id = kvm_xapic_id(vcpu->arch.apic); 427 428 if (ldr == svm->ldr_reg) 429 return 0; 430 431 avic_invalidate_logical_id_entry(vcpu); 432 433 if (ldr) 434 ret = avic_ldr_write(vcpu, id, ldr); 435 436 if (!ret) 437 svm->ldr_reg = ldr; 438 439 return ret; 440 } 441 442 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu) 443 { 444 u64 *old, *new; 445 struct vcpu_svm *svm = to_svm(vcpu); 446 u32 id = kvm_xapic_id(vcpu->arch.apic); 447 448 if (vcpu->vcpu_id == id) 449 return 0; 450 451 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id); 452 new = avic_get_physical_id_entry(vcpu, id); 453 if (!new || !old) 454 return 1; 455 456 /* We need to move physical_id_entry to new offset */ 457 *new = *old; 458 *old = 0ULL; 459 to_svm(vcpu)->avic_physical_id_cache = new; 460 461 /* 462 * Also update the guest physical APIC ID in the logical 463 * APIC ID table entry if already setup the LDR. 464 */ 465 if (svm->ldr_reg) 466 avic_handle_ldr_update(vcpu); 467 468 return 0; 469 } 470 471 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu) 472 { 473 struct vcpu_svm *svm = to_svm(vcpu); 474 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); 475 476 if (svm->dfr_reg == dfr) 477 return; 478 479 avic_invalidate_logical_id_entry(vcpu); 480 svm->dfr_reg = dfr; 481 } 482 483 static int avic_unaccel_trap_write(struct vcpu_svm *svm) 484 { 485 struct kvm_lapic *apic = svm->vcpu.arch.apic; 486 u32 offset = svm->vmcb->control.exit_info_1 & 487 AVIC_UNACCEL_ACCESS_OFFSET_MASK; 488 489 switch (offset) { 490 case APIC_ID: 491 if (avic_handle_apic_id_update(&svm->vcpu)) 492 return 0; 493 break; 494 case APIC_LDR: 495 if (avic_handle_ldr_update(&svm->vcpu)) 496 return 0; 497 break; 498 case APIC_DFR: 499 avic_handle_dfr_update(&svm->vcpu); 500 break; 501 default: 502 break; 503 } 504 505 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); 506 507 return 1; 508 } 509 510 static bool is_avic_unaccelerated_access_trap(u32 offset) 511 { 512 bool ret = false; 513 514 switch (offset) { 515 case APIC_ID: 516 case APIC_EOI: 517 case APIC_RRR: 518 case APIC_LDR: 519 case APIC_DFR: 520 case APIC_SPIV: 521 case APIC_ESR: 522 case APIC_ICR: 523 case APIC_LVTT: 524 case APIC_LVTTHMR: 525 case APIC_LVTPC: 526 case APIC_LVT0: 527 case APIC_LVT1: 528 case APIC_LVTERR: 529 case APIC_TMICT: 530 case APIC_TDCR: 531 ret = true; 532 break; 533 default: 534 break; 535 } 536 return ret; 537 } 538 539 int avic_unaccelerated_access_interception(struct vcpu_svm *svm) 540 { 541 int ret = 0; 542 u32 offset = svm->vmcb->control.exit_info_1 & 543 AVIC_UNACCEL_ACCESS_OFFSET_MASK; 544 u32 vector = svm->vmcb->control.exit_info_2 & 545 AVIC_UNACCEL_ACCESS_VECTOR_MASK; 546 bool write = (svm->vmcb->control.exit_info_1 >> 32) & 547 AVIC_UNACCEL_ACCESS_WRITE_MASK; 548 bool trap = is_avic_unaccelerated_access_trap(offset); 549 550 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset, 551 trap, write, vector); 552 if (trap) { 553 /* Handling Trap */ 554 WARN_ONCE(!write, "svm: Handling trap read.\n"); 555 ret = avic_unaccel_trap_write(svm); 556 } else { 557 /* Handling Fault */ 558 ret = kvm_emulate_instruction(&svm->vcpu, 0); 559 } 560 561 return ret; 562 } 563 564 int avic_init_vcpu(struct vcpu_svm *svm) 565 { 566 int ret; 567 struct kvm_vcpu *vcpu = &svm->vcpu; 568 569 if (!avic || !irqchip_in_kernel(vcpu->kvm)) 570 return 0; 571 572 ret = avic_init_backing_page(&svm->vcpu); 573 if (ret) 574 return ret; 575 576 INIT_LIST_HEAD(&svm->ir_list); 577 spin_lock_init(&svm->ir_list_lock); 578 svm->dfr_reg = APIC_DFR_FLAT; 579 580 return ret; 581 } 582 583 void avic_post_state_restore(struct kvm_vcpu *vcpu) 584 { 585 if (avic_handle_apic_id_update(vcpu) != 0) 586 return; 587 avic_handle_dfr_update(vcpu); 588 avic_handle_ldr_update(vcpu); 589 } 590 591 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate) 592 { 593 if (!avic || !lapic_in_kernel(vcpu)) 594 return; 595 596 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 597 kvm_request_apicv_update(vcpu->kvm, activate, 598 APICV_INHIBIT_REASON_IRQWIN); 599 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 600 } 601 602 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 603 { 604 return; 605 } 606 607 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 608 { 609 } 610 611 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 612 { 613 } 614 615 static int svm_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) 616 { 617 int ret = 0; 618 unsigned long flags; 619 struct amd_svm_iommu_ir *ir; 620 struct vcpu_svm *svm = to_svm(vcpu); 621 622 if (!kvm_arch_has_assigned_device(vcpu->kvm)) 623 return 0; 624 625 /* 626 * Here, we go through the per-vcpu ir_list to update all existing 627 * interrupt remapping table entry targeting this vcpu. 628 */ 629 spin_lock_irqsave(&svm->ir_list_lock, flags); 630 631 if (list_empty(&svm->ir_list)) 632 goto out; 633 634 list_for_each_entry(ir, &svm->ir_list, node) { 635 if (activate) 636 ret = amd_iommu_activate_guest_mode(ir->data); 637 else 638 ret = amd_iommu_deactivate_guest_mode(ir->data); 639 if (ret) 640 break; 641 } 642 out: 643 spin_unlock_irqrestore(&svm->ir_list_lock, flags); 644 return ret; 645 } 646 647 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 648 { 649 struct vcpu_svm *svm = to_svm(vcpu); 650 struct vmcb *vmcb = svm->vmcb; 651 bool activated = kvm_vcpu_apicv_active(vcpu); 652 653 if (!avic) 654 return; 655 656 if (activated) { 657 /** 658 * During AVIC temporary deactivation, guest could update 659 * APIC ID, DFR and LDR registers, which would not be trapped 660 * by avic_unaccelerated_access_interception(). In this case, 661 * we need to check and update the AVIC logical APIC ID table 662 * accordingly before re-activating. 663 */ 664 avic_post_state_restore(vcpu); 665 vmcb->control.int_ctl |= AVIC_ENABLE_MASK; 666 } else { 667 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK; 668 } 669 vmcb_mark_dirty(vmcb, VMCB_AVIC); 670 671 svm_set_pi_irte_mode(vcpu, activated); 672 } 673 674 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 675 { 676 return; 677 } 678 679 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) 680 { 681 if (!vcpu->arch.apicv_active) 682 return -1; 683 684 kvm_lapic_set_irr(vec, vcpu->arch.apic); 685 smp_mb__after_atomic(); 686 687 if (avic_vcpu_is_running(vcpu)) { 688 int cpuid = vcpu->cpu; 689 690 if (cpuid != get_cpu()) 691 wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid)); 692 put_cpu(); 693 } else 694 kvm_vcpu_wake_up(vcpu); 695 696 return 0; 697 } 698 699 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 700 { 701 return false; 702 } 703 704 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) 705 { 706 unsigned long flags; 707 struct amd_svm_iommu_ir *cur; 708 709 spin_lock_irqsave(&svm->ir_list_lock, flags); 710 list_for_each_entry(cur, &svm->ir_list, node) { 711 if (cur->data != pi->ir_data) 712 continue; 713 list_del(&cur->node); 714 kfree(cur); 715 break; 716 } 717 spin_unlock_irqrestore(&svm->ir_list_lock, flags); 718 } 719 720 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) 721 { 722 int ret = 0; 723 unsigned long flags; 724 struct amd_svm_iommu_ir *ir; 725 726 /** 727 * In some cases, the existing irte is updaed and re-set, 728 * so we need to check here if it's already been * added 729 * to the ir_list. 730 */ 731 if (pi->ir_data && (pi->prev_ga_tag != 0)) { 732 struct kvm *kvm = svm->vcpu.kvm; 733 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); 734 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id); 735 struct vcpu_svm *prev_svm; 736 737 if (!prev_vcpu) { 738 ret = -EINVAL; 739 goto out; 740 } 741 742 prev_svm = to_svm(prev_vcpu); 743 svm_ir_list_del(prev_svm, pi); 744 } 745 746 /** 747 * Allocating new amd_iommu_pi_data, which will get 748 * add to the per-vcpu ir_list. 749 */ 750 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT); 751 if (!ir) { 752 ret = -ENOMEM; 753 goto out; 754 } 755 ir->data = pi->ir_data; 756 757 spin_lock_irqsave(&svm->ir_list_lock, flags); 758 list_add(&ir->node, &svm->ir_list); 759 spin_unlock_irqrestore(&svm->ir_list_lock, flags); 760 out: 761 return ret; 762 } 763 764 /** 765 * Note: 766 * The HW cannot support posting multicast/broadcast 767 * interrupts to a vCPU. So, we still use legacy interrupt 768 * remapping for these kind of interrupts. 769 * 770 * For lowest-priority interrupts, we only support 771 * those with single CPU as the destination, e.g. user 772 * configures the interrupts via /proc/irq or uses 773 * irqbalance to make the interrupts single-CPU. 774 */ 775 static int 776 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, 777 struct vcpu_data *vcpu_info, struct vcpu_svm **svm) 778 { 779 struct kvm_lapic_irq irq; 780 struct kvm_vcpu *vcpu = NULL; 781 782 kvm_set_msi_irq(kvm, e, &irq); 783 784 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 785 !kvm_irq_is_postable(&irq)) { 786 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", 787 __func__, irq.vector); 788 return -1; 789 } 790 791 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, 792 irq.vector); 793 *svm = to_svm(vcpu); 794 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page)); 795 vcpu_info->vector = irq.vector; 796 797 return 0; 798 } 799 800 /* 801 * svm_update_pi_irte - set IRTE for Posted-Interrupts 802 * 803 * @kvm: kvm 804 * @host_irq: host irq of the interrupt 805 * @guest_irq: gsi of the interrupt 806 * @set: set or unset PI 807 * returns 0 on success, < 0 on failure 808 */ 809 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 810 uint32_t guest_irq, bool set) 811 { 812 struct kvm_kernel_irq_routing_entry *e; 813 struct kvm_irq_routing_table *irq_rt; 814 int idx, ret = -EINVAL; 815 816 if (!kvm_arch_has_assigned_device(kvm) || 817 !irq_remapping_cap(IRQ_POSTING_CAP)) 818 return 0; 819 820 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n", 821 __func__, host_irq, guest_irq, set); 822 823 idx = srcu_read_lock(&kvm->irq_srcu); 824 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 825 WARN_ON(guest_irq >= irq_rt->nr_rt_entries); 826 827 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 828 struct vcpu_data vcpu_info; 829 struct vcpu_svm *svm = NULL; 830 831 if (e->type != KVM_IRQ_ROUTING_MSI) 832 continue; 833 834 /** 835 * Here, we setup with legacy mode in the following cases: 836 * 1. When cannot target interrupt to a specific vcpu. 837 * 2. Unsetting posted interrupt. 838 * 3. APIC virtialization is disabled for the vcpu. 839 * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) 840 */ 841 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && 842 kvm_vcpu_apicv_active(&svm->vcpu)) { 843 struct amd_iommu_pi_data pi; 844 845 /* Try to enable guest_mode in IRTE */ 846 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) & 847 AVIC_HPA_MASK); 848 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, 849 svm->vcpu.vcpu_id); 850 pi.is_guest_mode = true; 851 pi.vcpu_data = &vcpu_info; 852 ret = irq_set_vcpu_affinity(host_irq, &pi); 853 854 /** 855 * Here, we successfully setting up vcpu affinity in 856 * IOMMU guest mode. Now, we need to store the posted 857 * interrupt information in a per-vcpu ir_list so that 858 * we can reference to them directly when we update vcpu 859 * scheduling information in IOMMU irte. 860 */ 861 if (!ret && pi.is_guest_mode) 862 svm_ir_list_add(svm, &pi); 863 } else { 864 /* Use legacy mode in IRTE */ 865 struct amd_iommu_pi_data pi; 866 867 /** 868 * Here, pi is used to: 869 * - Tell IOMMU to use legacy mode for this interrupt. 870 * - Retrieve ga_tag of prior interrupt remapping data. 871 */ 872 pi.prev_ga_tag = 0; 873 pi.is_guest_mode = false; 874 ret = irq_set_vcpu_affinity(host_irq, &pi); 875 876 /** 877 * Check if the posted interrupt was previously 878 * setup with the guest_mode by checking if the ga_tag 879 * was cached. If so, we need to clean up the per-vcpu 880 * ir_list. 881 */ 882 if (!ret && pi.prev_ga_tag) { 883 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); 884 struct kvm_vcpu *vcpu; 885 886 vcpu = kvm_get_vcpu_by_id(kvm, id); 887 if (vcpu) 888 svm_ir_list_del(to_svm(vcpu), &pi); 889 } 890 } 891 892 if (!ret && svm) { 893 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id, 894 e->gsi, vcpu_info.vector, 895 vcpu_info.pi_desc_addr, set); 896 } 897 898 if (ret < 0) { 899 pr_err("%s: failed to update PI IRTE\n", __func__); 900 goto out; 901 } 902 } 903 904 ret = 0; 905 out: 906 srcu_read_unlock(&kvm->irq_srcu, idx); 907 return ret; 908 } 909 910 bool svm_check_apicv_inhibit_reasons(ulong bit) 911 { 912 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 913 BIT(APICV_INHIBIT_REASON_HYPERV) | 914 BIT(APICV_INHIBIT_REASON_NESTED) | 915 BIT(APICV_INHIBIT_REASON_IRQWIN) | 916 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | 917 BIT(APICV_INHIBIT_REASON_X2APIC); 918 919 return supported & BIT(bit); 920 } 921 922 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate) 923 { 924 avic_update_access_page(kvm, activate); 925 } 926 927 static inline int 928 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) 929 { 930 int ret = 0; 931 unsigned long flags; 932 struct amd_svm_iommu_ir *ir; 933 struct vcpu_svm *svm = to_svm(vcpu); 934 935 if (!kvm_arch_has_assigned_device(vcpu->kvm)) 936 return 0; 937 938 /* 939 * Here, we go through the per-vcpu ir_list to update all existing 940 * interrupt remapping table entry targeting this vcpu. 941 */ 942 spin_lock_irqsave(&svm->ir_list_lock, flags); 943 944 if (list_empty(&svm->ir_list)) 945 goto out; 946 947 list_for_each_entry(ir, &svm->ir_list, node) { 948 ret = amd_iommu_update_ga(cpu, r, ir->data); 949 if (ret) 950 break; 951 } 952 out: 953 spin_unlock_irqrestore(&svm->ir_list_lock, flags); 954 return ret; 955 } 956 957 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 958 { 959 u64 entry; 960 /* ID = 0xff (broadcast), ID > 0xff (reserved) */ 961 int h_physical_id = kvm_cpu_get_apicid(cpu); 962 struct vcpu_svm *svm = to_svm(vcpu); 963 964 if (!kvm_vcpu_apicv_active(vcpu)) 965 return; 966 967 /* 968 * Since the host physical APIC id is 8 bits, 969 * we can support host APIC ID upto 255. 970 */ 971 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK)) 972 return; 973 974 entry = READ_ONCE(*(svm->avic_physical_id_cache)); 975 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); 976 977 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; 978 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); 979 980 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; 981 if (svm->avic_is_running) 982 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; 983 984 WRITE_ONCE(*(svm->avic_physical_id_cache), entry); 985 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, 986 svm->avic_is_running); 987 } 988 989 void avic_vcpu_put(struct kvm_vcpu *vcpu) 990 { 991 u64 entry; 992 struct vcpu_svm *svm = to_svm(vcpu); 993 994 if (!kvm_vcpu_apicv_active(vcpu)) 995 return; 996 997 entry = READ_ONCE(*(svm->avic_physical_id_cache)); 998 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) 999 avic_update_iommu_vcpu_affinity(vcpu, -1, 0); 1000 1001 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; 1002 WRITE_ONCE(*(svm->avic_physical_id_cache), entry); 1003 } 1004 1005 /** 1006 * This function is called during VCPU halt/unhalt. 1007 */ 1008 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run) 1009 { 1010 struct vcpu_svm *svm = to_svm(vcpu); 1011 1012 svm->avic_is_running = is_run; 1013 if (is_run) 1014 avic_vcpu_load(vcpu, vcpu->cpu); 1015 else 1016 avic_vcpu_put(vcpu); 1017 } 1018 1019 void svm_vcpu_blocking(struct kvm_vcpu *vcpu) 1020 { 1021 avic_set_running(vcpu, false); 1022 } 1023 1024 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu) 1025 { 1026 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 1027 kvm_vcpu_update_apicv(vcpu); 1028 avic_set_running(vcpu, true); 1029 } 1030