1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_PMU_H 3 #define __KVM_X86_PMU_H 4 5 #include <linux/nospec.h> 6 7 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu) 8 #define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu)) 9 #define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu) 10 11 /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */ 12 #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf) 13 14 #define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000 15 #define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001 16 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002 17 18 #define MAX_FIXED_COUNTERS 3 19 20 struct kvm_event_hw_type_mapping { 21 u8 eventsel; 22 u8 unit_mask; 23 unsigned event_type; 24 }; 25 26 struct kvm_pmu_ops { 27 unsigned (*find_arch_event)(struct kvm_pmu *pmu, u8 event_select, 28 u8 unit_mask); 29 unsigned (*find_fixed_event)(int idx); 30 bool (*pmc_is_enabled)(struct kvm_pmc *pmc); 31 struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); 32 struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, 33 unsigned int idx, u64 *mask); 34 struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr); 35 int (*is_valid_rdpmc_ecx)(struct kvm_vcpu *vcpu, unsigned int idx); 36 bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr); 37 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 38 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 39 void (*refresh)(struct kvm_vcpu *vcpu); 40 void (*init)(struct kvm_vcpu *vcpu); 41 void (*reset)(struct kvm_vcpu *vcpu); 42 }; 43 44 static inline u64 pmc_bitmask(struct kvm_pmc *pmc) 45 { 46 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 47 48 return pmu->counter_bitmask[pmc->type]; 49 } 50 51 static inline u64 pmc_read_counter(struct kvm_pmc *pmc) 52 { 53 u64 counter, enabled, running; 54 55 counter = pmc->counter; 56 if (pmc->perf_event) 57 counter += perf_event_read_value(pmc->perf_event, 58 &enabled, &running); 59 /* FIXME: Scaling needed? */ 60 return counter & pmc_bitmask(pmc); 61 } 62 63 static inline void pmc_release_perf_event(struct kvm_pmc *pmc) 64 { 65 if (pmc->perf_event) { 66 perf_event_release_kernel(pmc->perf_event); 67 pmc->perf_event = NULL; 68 pmc->current_config = 0; 69 pmc_to_pmu(pmc)->event_count--; 70 } 71 } 72 73 static inline void pmc_stop_counter(struct kvm_pmc *pmc) 74 { 75 if (pmc->perf_event) { 76 pmc->counter = pmc_read_counter(pmc); 77 pmc_release_perf_event(pmc); 78 } 79 } 80 81 static inline bool pmc_is_gp(struct kvm_pmc *pmc) 82 { 83 return pmc->type == KVM_PMC_GP; 84 } 85 86 static inline bool pmc_is_fixed(struct kvm_pmc *pmc) 87 { 88 return pmc->type == KVM_PMC_FIXED; 89 } 90 91 static inline bool pmc_is_enabled(struct kvm_pmc *pmc) 92 { 93 return kvm_x86_ops.pmu_ops->pmc_is_enabled(pmc); 94 } 95 96 static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu, 97 u64 data) 98 { 99 return !(pmu->global_ctrl_mask & data); 100 } 101 102 /* returns general purpose PMC with the specified MSR. Note that it can be 103 * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a 104 * paramenter to tell them apart. 105 */ 106 static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr, 107 u32 base) 108 { 109 if (msr >= base && msr < base + pmu->nr_arch_gp_counters) { 110 u32 index = array_index_nospec(msr - base, 111 pmu->nr_arch_gp_counters); 112 113 return &pmu->gp_counters[index]; 114 } 115 116 return NULL; 117 } 118 119 /* returns fixed PMC with the specified MSR */ 120 static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr) 121 { 122 int base = MSR_CORE_PERF_FIXED_CTR0; 123 124 if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) { 125 u32 index = array_index_nospec(msr - base, 126 pmu->nr_arch_fixed_counters); 127 128 return &pmu->fixed_counters[index]; 129 } 130 131 return NULL; 132 } 133 134 static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value) 135 { 136 u64 sample_period = (-counter_value) & pmc_bitmask(pmc); 137 138 if (!sample_period) 139 sample_period = pmc_bitmask(pmc) + 1; 140 return sample_period; 141 } 142 143 void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel); 144 void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx); 145 void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx); 146 147 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); 148 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); 149 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); 150 int kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx); 151 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr); 152 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 153 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 154 void kvm_pmu_refresh(struct kvm_vcpu *vcpu); 155 void kvm_pmu_reset(struct kvm_vcpu *vcpu); 156 void kvm_pmu_init(struct kvm_vcpu *vcpu); 157 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu); 158 void kvm_pmu_destroy(struct kvm_vcpu *vcpu); 159 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp); 160 161 bool is_vmware_backdoor_pmc(u32 pmc_idx); 162 163 extern struct kvm_pmu_ops intel_pmu_ops; 164 extern struct kvm_pmu_ops amd_pmu_ops; 165 #endif /* __KVM_X86_PMU_H */ 166