1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_PMU_H 3 #define __KVM_X86_PMU_H 4 5 #include <linux/nospec.h> 6 7 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu) 8 #define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu)) 9 #define pmc_to_pmu(pmc) (&(pmc)->vcpu->arch.pmu) 10 11 #define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | \ 12 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL) 13 14 /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */ 15 #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf) 16 17 #define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000 18 #define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001 19 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002 20 21 struct kvm_pmu_ops { 22 bool (*hw_event_available)(struct kvm_pmc *pmc); 23 struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); 24 struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, 25 unsigned int idx, u64 *mask); 26 struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, u32 msr); 27 bool (*is_valid_rdpmc_ecx)(struct kvm_vcpu *vcpu, unsigned int idx); 28 bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr); 29 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 30 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 31 void (*refresh)(struct kvm_vcpu *vcpu); 32 void (*init)(struct kvm_vcpu *vcpu); 33 void (*reset)(struct kvm_vcpu *vcpu); 34 void (*deliver_pmi)(struct kvm_vcpu *vcpu); 35 void (*cleanup)(struct kvm_vcpu *vcpu); 36 37 const u64 EVENTSEL_EVENT; 38 const int MAX_NR_GP_COUNTERS; 39 const int MIN_NR_GP_COUNTERS; 40 }; 41 42 void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops); 43 44 static inline bool kvm_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu) 45 { 46 /* 47 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is 48 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is 49 * greater than zero. However, KVM only exposes and emulates the MSR 50 * to/for the guest if the guest PMU supports at least "Architectural 51 * Performance Monitoring Version 2". 52 * 53 * AMD's version of PERF_GLOBAL_CTRL conveniently shows up with v2. 54 */ 55 return pmu->version > 1; 56 } 57 58 static inline u64 pmc_bitmask(struct kvm_pmc *pmc) 59 { 60 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 61 62 return pmu->counter_bitmask[pmc->type]; 63 } 64 65 static inline u64 pmc_read_counter(struct kvm_pmc *pmc) 66 { 67 u64 counter, enabled, running; 68 69 counter = pmc->counter; 70 if (pmc->perf_event && !pmc->is_paused) 71 counter += perf_event_read_value(pmc->perf_event, 72 &enabled, &running); 73 /* FIXME: Scaling needed? */ 74 return counter & pmc_bitmask(pmc); 75 } 76 77 static inline void pmc_release_perf_event(struct kvm_pmc *pmc) 78 { 79 if (pmc->perf_event) { 80 perf_event_release_kernel(pmc->perf_event); 81 pmc->perf_event = NULL; 82 pmc->current_config = 0; 83 pmc_to_pmu(pmc)->event_count--; 84 } 85 } 86 87 static inline void pmc_stop_counter(struct kvm_pmc *pmc) 88 { 89 if (pmc->perf_event) { 90 pmc->counter = pmc_read_counter(pmc); 91 pmc_release_perf_event(pmc); 92 } 93 } 94 95 static inline bool pmc_is_gp(struct kvm_pmc *pmc) 96 { 97 return pmc->type == KVM_PMC_GP; 98 } 99 100 static inline bool pmc_is_fixed(struct kvm_pmc *pmc) 101 { 102 return pmc->type == KVM_PMC_FIXED; 103 } 104 105 static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu, 106 u64 data) 107 { 108 return !(pmu->global_ctrl_mask & data); 109 } 110 111 /* returns general purpose PMC with the specified MSR. Note that it can be 112 * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a 113 * parameter to tell them apart. 114 */ 115 static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr, 116 u32 base) 117 { 118 if (msr >= base && msr < base + pmu->nr_arch_gp_counters) { 119 u32 index = array_index_nospec(msr - base, 120 pmu->nr_arch_gp_counters); 121 122 return &pmu->gp_counters[index]; 123 } 124 125 return NULL; 126 } 127 128 /* returns fixed PMC with the specified MSR */ 129 static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr) 130 { 131 int base = MSR_CORE_PERF_FIXED_CTR0; 132 133 if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) { 134 u32 index = array_index_nospec(msr - base, 135 pmu->nr_arch_fixed_counters); 136 137 return &pmu->fixed_counters[index]; 138 } 139 140 return NULL; 141 } 142 143 static inline u64 get_sample_period(struct kvm_pmc *pmc, u64 counter_value) 144 { 145 u64 sample_period = (-counter_value) & pmc_bitmask(pmc); 146 147 if (!sample_period) 148 sample_period = pmc_bitmask(pmc) + 1; 149 return sample_period; 150 } 151 152 static inline void pmc_update_sample_period(struct kvm_pmc *pmc) 153 { 154 if (!pmc->perf_event || pmc->is_paused || 155 !is_sampling_event(pmc->perf_event)) 156 return; 157 158 perf_event_period(pmc->perf_event, 159 get_sample_period(pmc, pmc->counter)); 160 } 161 162 static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc) 163 { 164 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 165 166 if (pmc_is_fixed(pmc)) 167 return fixed_ctrl_field(pmu->fixed_ctr_ctrl, 168 pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3; 169 170 return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE; 171 } 172 173 extern struct x86_pmu_capability kvm_pmu_cap; 174 175 static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops) 176 { 177 bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL; 178 int min_nr_gp_ctrs = pmu_ops->MIN_NR_GP_COUNTERS; 179 180 /* 181 * Hybrid PMUs don't play nice with virtualization without careful 182 * configuration by userspace, and KVM's APIs for reporting supported 183 * vPMU features do not account for hybrid PMUs. Disable vPMU support 184 * for hybrid PMUs until KVM gains a way to let userspace opt-in. 185 */ 186 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 187 enable_pmu = false; 188 189 if (enable_pmu) { 190 perf_get_x86_pmu_capability(&kvm_pmu_cap); 191 192 /* 193 * WARN if perf did NOT disable hardware PMU if the number of 194 * architecturally required GP counters aren't present, i.e. if 195 * there are a non-zero number of counters, but fewer than what 196 * is architecturally required. 197 */ 198 if (!kvm_pmu_cap.num_counters_gp || 199 WARN_ON_ONCE(kvm_pmu_cap.num_counters_gp < min_nr_gp_ctrs)) 200 enable_pmu = false; 201 else if (is_intel && !kvm_pmu_cap.version) 202 enable_pmu = false; 203 } 204 205 if (!enable_pmu) { 206 memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap)); 207 return; 208 } 209 210 kvm_pmu_cap.version = min(kvm_pmu_cap.version, 2); 211 kvm_pmu_cap.num_counters_gp = min(kvm_pmu_cap.num_counters_gp, 212 pmu_ops->MAX_NR_GP_COUNTERS); 213 kvm_pmu_cap.num_counters_fixed = min(kvm_pmu_cap.num_counters_fixed, 214 KVM_PMC_MAX_FIXED); 215 } 216 217 static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) 218 { 219 set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi); 220 kvm_make_request(KVM_REQ_PMU, pmc->vcpu); 221 } 222 223 static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff) 224 { 225 int bit; 226 227 if (!diff) 228 return; 229 230 for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) 231 set_bit(bit, pmu->reprogram_pmi); 232 kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); 233 } 234 235 /* 236 * Check if a PMC is enabled by comparing it against global_ctrl bits. 237 * 238 * If the vPMU doesn't have global_ctrl MSR, all vPMCs are enabled. 239 */ 240 static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) 241 { 242 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 243 244 if (!kvm_pmu_has_perf_global_ctrl(pmu)) 245 return true; 246 247 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); 248 } 249 250 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); 251 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); 252 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); 253 bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx); 254 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr); 255 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 256 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 257 void kvm_pmu_refresh(struct kvm_vcpu *vcpu); 258 void kvm_pmu_reset(struct kvm_vcpu *vcpu); 259 void kvm_pmu_init(struct kvm_vcpu *vcpu); 260 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu); 261 void kvm_pmu_destroy(struct kvm_vcpu *vcpu); 262 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp); 263 void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id); 264 265 bool is_vmware_backdoor_pmc(u32 pmc_idx); 266 267 extern struct kvm_pmu_ops intel_pmu_ops; 268 extern struct kvm_pmu_ops amd_pmu_ops; 269 #endif /* __KVM_X86_PMU_H */ 270