1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine -- Performance Monitoring Unit support 4 * 5 * Copyright 2015 Red Hat, Inc. and/or its affiliates. 6 * 7 * Authors: 8 * Avi Kivity <avi@redhat.com> 9 * Gleb Natapov <gleb@redhat.com> 10 * Wei Huang <wei@redhat.com> 11 */ 12 13 #include <linux/types.h> 14 #include <linux/kvm_host.h> 15 #include <linux/perf_event.h> 16 #include <asm/perf_event.h> 17 #include "x86.h" 18 #include "cpuid.h" 19 #include "lapic.h" 20 #include "pmu.h" 21 22 /* NOTE: 23 * - Each perf counter is defined as "struct kvm_pmc"; 24 * - There are two types of perf counters: general purpose (gp) and fixed. 25 * gp counters are stored in gp_counters[] and fixed counters are stored 26 * in fixed_counters[] respectively. Both of them are part of "struct 27 * kvm_pmu"; 28 * - pmu.c understands the difference between gp counters and fixed counters. 29 * However AMD doesn't support fixed-counters; 30 * - There are three types of index to access perf counters (PMC): 31 * 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD 32 * has MSR_K7_PERFCTRn. 33 * 2. MSR Index (named idx): This normally is used by RDPMC instruction. 34 * For instance AMD RDPMC instruction uses 0000_0003h in ECX to access 35 * C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except 36 * that it also supports fixed counters. idx can be used to as index to 37 * gp and fixed counters. 38 * 3. Global PMC Index (named pmc): pmc is an index specific to PMU 39 * code. Each pmc, stored in kvm_pmc.idx field, is unique across 40 * all perf counters (both gp and fixed). The mapping relationship 41 * between pmc and perf counters is as the following: 42 * * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters 43 * [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed 44 * * AMD: [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters 45 */ 46 47 static void kvm_pmi_trigger_fn(struct irq_work *irq_work) 48 { 49 struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work); 50 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu); 51 52 kvm_pmu_deliver_pmi(vcpu); 53 } 54 55 static void kvm_perf_overflow(struct perf_event *perf_event, 56 struct perf_sample_data *data, 57 struct pt_regs *regs) 58 { 59 struct kvm_pmc *pmc = perf_event->overflow_handler_context; 60 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 61 62 if (!test_and_set_bit(pmc->idx, 63 (unsigned long *)&pmu->reprogram_pmi)) { 64 __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); 65 kvm_make_request(KVM_REQ_PMU, pmc->vcpu); 66 } 67 } 68 69 static void kvm_perf_overflow_intr(struct perf_event *perf_event, 70 struct perf_sample_data *data, 71 struct pt_regs *regs) 72 { 73 struct kvm_pmc *pmc = perf_event->overflow_handler_context; 74 struct kvm_pmu *pmu = pmc_to_pmu(pmc); 75 76 if (!test_and_set_bit(pmc->idx, 77 (unsigned long *)&pmu->reprogram_pmi)) { 78 __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); 79 kvm_make_request(KVM_REQ_PMU, pmc->vcpu); 80 81 /* 82 * Inject PMI. If vcpu was in a guest mode during NMI PMI 83 * can be ejected on a guest mode re-entry. Otherwise we can't 84 * be sure that vcpu wasn't executing hlt instruction at the 85 * time of vmexit and is not going to re-enter guest mode until 86 * woken up. So we should wake it, but this is impossible from 87 * NMI context. Do it from irq work instead. 88 */ 89 if (!kvm_is_in_guest()) 90 irq_work_queue(&pmc_to_pmu(pmc)->irq_work); 91 else 92 kvm_make_request(KVM_REQ_PMI, pmc->vcpu); 93 } 94 } 95 96 static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, 97 unsigned config, bool exclude_user, 98 bool exclude_kernel, bool intr, 99 bool in_tx, bool in_tx_cp) 100 { 101 struct perf_event *event; 102 struct perf_event_attr attr = { 103 .type = type, 104 .size = sizeof(attr), 105 .pinned = true, 106 .exclude_idle = true, 107 .exclude_host = 1, 108 .exclude_user = exclude_user, 109 .exclude_kernel = exclude_kernel, 110 .config = config, 111 }; 112 113 attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc); 114 115 if (in_tx) 116 attr.config |= HSW_IN_TX; 117 if (in_tx_cp) { 118 /* 119 * HSW_IN_TX_CHECKPOINTED is not supported with nonzero 120 * period. Just clear the sample period so at least 121 * allocating the counter doesn't fail. 122 */ 123 attr.sample_period = 0; 124 attr.config |= HSW_IN_TX_CHECKPOINTED; 125 } 126 127 event = perf_event_create_kernel_counter(&attr, -1, current, 128 intr ? kvm_perf_overflow_intr : 129 kvm_perf_overflow, pmc); 130 if (IS_ERR(event)) { 131 printk_once("kvm_pmu: event creation failed %ld\n", 132 PTR_ERR(event)); 133 return; 134 } 135 136 pmc->perf_event = event; 137 clear_bit(pmc->idx, (unsigned long*)&pmc_to_pmu(pmc)->reprogram_pmi); 138 } 139 140 void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel) 141 { 142 unsigned config, type = PERF_TYPE_RAW; 143 u8 event_select, unit_mask; 144 145 if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) 146 printk_once("kvm pmu: pin control bit is ignored\n"); 147 148 pmc->eventsel = eventsel; 149 150 pmc_stop_counter(pmc); 151 152 if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc)) 153 return; 154 155 event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT; 156 unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; 157 158 if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE | 159 ARCH_PERFMON_EVENTSEL_INV | 160 ARCH_PERFMON_EVENTSEL_CMASK | 161 HSW_IN_TX | 162 HSW_IN_TX_CHECKPOINTED))) { 163 config = kvm_x86_ops->pmu_ops->find_arch_event(pmc_to_pmu(pmc), 164 event_select, 165 unit_mask); 166 if (config != PERF_COUNT_HW_MAX) 167 type = PERF_TYPE_HARDWARE; 168 } 169 170 if (type == PERF_TYPE_RAW) 171 config = eventsel & X86_RAW_EVENT_MASK; 172 173 pmc_reprogram_counter(pmc, type, config, 174 !(eventsel & ARCH_PERFMON_EVENTSEL_USR), 175 !(eventsel & ARCH_PERFMON_EVENTSEL_OS), 176 eventsel & ARCH_PERFMON_EVENTSEL_INT, 177 (eventsel & HSW_IN_TX), 178 (eventsel & HSW_IN_TX_CHECKPOINTED)); 179 } 180 EXPORT_SYMBOL_GPL(reprogram_gp_counter); 181 182 void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx) 183 { 184 unsigned en_field = ctrl & 0x3; 185 bool pmi = ctrl & 0x8; 186 187 pmc_stop_counter(pmc); 188 189 if (!en_field || !pmc_is_enabled(pmc)) 190 return; 191 192 pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE, 193 kvm_x86_ops->pmu_ops->find_fixed_event(idx), 194 !(en_field & 0x2), /* exclude user */ 195 !(en_field & 0x1), /* exclude kernel */ 196 pmi, false, false); 197 } 198 EXPORT_SYMBOL_GPL(reprogram_fixed_counter); 199 200 void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx) 201 { 202 struct kvm_pmc *pmc = kvm_x86_ops->pmu_ops->pmc_idx_to_pmc(pmu, pmc_idx); 203 204 if (!pmc) 205 return; 206 207 if (pmc_is_gp(pmc)) 208 reprogram_gp_counter(pmc, pmc->eventsel); 209 else { 210 int idx = pmc_idx - INTEL_PMC_IDX_FIXED; 211 u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx); 212 213 reprogram_fixed_counter(pmc, ctrl, idx); 214 } 215 } 216 EXPORT_SYMBOL_GPL(reprogram_counter); 217 218 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) 219 { 220 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 221 u64 bitmask; 222 int bit; 223 224 bitmask = pmu->reprogram_pmi; 225 226 for_each_set_bit(bit, (unsigned long *)&bitmask, X86_PMC_IDX_MAX) { 227 struct kvm_pmc *pmc = kvm_x86_ops->pmu_ops->pmc_idx_to_pmc(pmu, bit); 228 229 if (unlikely(!pmc || !pmc->perf_event)) { 230 clear_bit(bit, (unsigned long *)&pmu->reprogram_pmi); 231 continue; 232 } 233 234 reprogram_counter(pmu, bit); 235 } 236 } 237 238 /* check if idx is a valid index to access PMU */ 239 int kvm_pmu_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx) 240 { 241 return kvm_x86_ops->pmu_ops->is_valid_msr_idx(vcpu, idx); 242 } 243 244 bool is_vmware_backdoor_pmc(u32 pmc_idx) 245 { 246 switch (pmc_idx) { 247 case VMWARE_BACKDOOR_PMC_HOST_TSC: 248 case VMWARE_BACKDOOR_PMC_REAL_TIME: 249 case VMWARE_BACKDOOR_PMC_APPARENT_TIME: 250 return true; 251 } 252 return false; 253 } 254 255 static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data) 256 { 257 u64 ctr_val; 258 259 switch (idx) { 260 case VMWARE_BACKDOOR_PMC_HOST_TSC: 261 ctr_val = rdtsc(); 262 break; 263 case VMWARE_BACKDOOR_PMC_REAL_TIME: 264 ctr_val = ktime_get_boot_ns(); 265 break; 266 case VMWARE_BACKDOOR_PMC_APPARENT_TIME: 267 ctr_val = ktime_get_boot_ns() + 268 vcpu->kvm->arch.kvmclock_offset; 269 break; 270 default: 271 return 1; 272 } 273 274 *data = ctr_val; 275 return 0; 276 } 277 278 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data) 279 { 280 bool fast_mode = idx & (1u << 31); 281 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 282 struct kvm_pmc *pmc; 283 u64 mask = fast_mode ? ~0u : ~0ull; 284 285 if (!pmu->version) 286 return 1; 287 288 if (is_vmware_backdoor_pmc(idx)) 289 return kvm_pmu_rdpmc_vmware(vcpu, idx, data); 290 291 pmc = kvm_x86_ops->pmu_ops->msr_idx_to_pmc(vcpu, idx, &mask); 292 if (!pmc) 293 return 1; 294 295 *data = pmc_read_counter(pmc) & mask; 296 return 0; 297 } 298 299 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu) 300 { 301 if (lapic_in_kernel(vcpu)) 302 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC); 303 } 304 305 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) 306 { 307 return kvm_x86_ops->pmu_ops->is_valid_msr(vcpu, msr); 308 } 309 310 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data) 311 { 312 return kvm_x86_ops->pmu_ops->get_msr(vcpu, msr, data); 313 } 314 315 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 316 { 317 return kvm_x86_ops->pmu_ops->set_msr(vcpu, msr_info); 318 } 319 320 /* refresh PMU settings. This function generally is called when underlying 321 * settings are changed (such as changes of PMU CPUID by guest VMs), which 322 * should rarely happen. 323 */ 324 void kvm_pmu_refresh(struct kvm_vcpu *vcpu) 325 { 326 kvm_x86_ops->pmu_ops->refresh(vcpu); 327 } 328 329 void kvm_pmu_reset(struct kvm_vcpu *vcpu) 330 { 331 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 332 333 irq_work_sync(&pmu->irq_work); 334 kvm_x86_ops->pmu_ops->reset(vcpu); 335 } 336 337 void kvm_pmu_init(struct kvm_vcpu *vcpu) 338 { 339 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 340 341 memset(pmu, 0, sizeof(*pmu)); 342 kvm_x86_ops->pmu_ops->init(vcpu); 343 init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn); 344 kvm_pmu_refresh(vcpu); 345 } 346 347 void kvm_pmu_destroy(struct kvm_vcpu *vcpu) 348 { 349 kvm_pmu_reset(vcpu); 350 } 351