1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * Macros and functions to access KVM PTEs (also known as SPTEs) 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2020 Red Hat, Inc. and/or its affiliates. 9 */ 10 11 12 #include <linux/kvm_host.h> 13 #include "mmu.h" 14 #include "mmu_internal.h" 15 #include "x86.h" 16 #include "spte.h" 17 18 #include <asm/e820/api.h> 19 #include <asm/memtype.h> 20 #include <asm/vmx.h> 21 22 static bool __read_mostly enable_mmio_caching = true; 23 module_param_named(mmio_caching, enable_mmio_caching, bool, 0444); 24 25 u64 __read_mostly shadow_host_writable_mask; 26 u64 __read_mostly shadow_mmu_writable_mask; 27 u64 __read_mostly shadow_nx_mask; 28 u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ 29 u64 __read_mostly shadow_user_mask; 30 u64 __read_mostly shadow_accessed_mask; 31 u64 __read_mostly shadow_dirty_mask; 32 u64 __read_mostly shadow_mmio_value; 33 u64 __read_mostly shadow_mmio_mask; 34 u64 __read_mostly shadow_mmio_access_mask; 35 u64 __read_mostly shadow_present_mask; 36 u64 __read_mostly shadow_me_mask; 37 u64 __read_mostly shadow_acc_track_mask; 38 39 u64 __read_mostly shadow_nonpresent_or_rsvd_mask; 40 u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; 41 42 u8 __read_mostly shadow_phys_bits; 43 44 static u64 generation_mmio_spte_mask(u64 gen) 45 { 46 u64 mask; 47 48 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK); 49 50 mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK; 51 mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK; 52 return mask; 53 } 54 55 u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access) 56 { 57 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; 58 u64 spte = generation_mmio_spte_mask(gen); 59 u64 gpa = gfn << PAGE_SHIFT; 60 61 WARN_ON_ONCE(!shadow_mmio_value); 62 63 access &= shadow_mmio_access_mask; 64 spte |= shadow_mmio_value | access; 65 spte |= gpa | shadow_nonpresent_or_rsvd_mask; 66 spte |= (gpa & shadow_nonpresent_or_rsvd_mask) 67 << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 68 69 return spte; 70 } 71 72 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) 73 { 74 if (pfn_valid(pfn)) 75 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && 76 /* 77 * Some reserved pages, such as those from NVDIMM 78 * DAX devices, are not for MMIO, and can be mapped 79 * with cached memory type for better performance. 80 * However, the above check misconceives those pages 81 * as MMIO, and results in KVM mapping them with UC 82 * memory type, which would hurt the performance. 83 * Therefore, we check the host memory type in addition 84 * and only treat UC/UC-/WC pages as MMIO. 85 */ 86 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); 87 88 return !e820__mapped_raw_any(pfn_to_hpa(pfn), 89 pfn_to_hpa(pfn + 1) - 1, 90 E820_TYPE_RAM); 91 } 92 93 /* 94 * Returns true if the SPTE has bits that may be set without holding mmu_lock. 95 * The caller is responsible for checking if the SPTE is shadow-present, and 96 * for determining whether or not the caller cares about non-leaf SPTEs. 97 */ 98 bool spte_has_volatile_bits(u64 spte) 99 { 100 /* 101 * Always atomically update spte if it can be updated 102 * out of mmu-lock, it can ensure dirty bit is not lost, 103 * also, it can help us to get a stable is_writable_pte() 104 * to ensure tlb flush is not missed. 105 */ 106 if (!is_writable_pte(spte) && is_mmu_writable_spte(spte)) 107 return true; 108 109 if (is_access_track_spte(spte)) 110 return true; 111 112 if (spte_ad_enabled(spte)) { 113 if (!(spte & shadow_accessed_mask) || 114 (is_writable_pte(spte) && !(spte & shadow_dirty_mask))) 115 return true; 116 } 117 118 return false; 119 } 120 121 bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 122 const struct kvm_memory_slot *slot, 123 unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn, 124 u64 old_spte, bool prefetch, bool can_unsync, 125 bool host_writable, u64 *new_spte) 126 { 127 int level = sp->role.level; 128 u64 spte = SPTE_MMU_PRESENT_MASK; 129 bool wrprot = false; 130 131 if (sp->role.ad_disabled) 132 spte |= SPTE_TDP_AD_DISABLED_MASK; 133 else if (kvm_mmu_page_ad_need_write_protect(sp)) 134 spte |= SPTE_TDP_AD_WRPROT_ONLY_MASK; 135 136 /* 137 * For the EPT case, shadow_present_mask is 0 if hardware 138 * supports exec-only page table entries. In that case, 139 * ACC_USER_MASK and shadow_user_mask are used to represent 140 * read access. See FNAME(gpte_access) in paging_tmpl.h. 141 */ 142 spte |= shadow_present_mask; 143 if (!prefetch) 144 spte |= spte_shadow_accessed_mask(spte); 145 146 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) && 147 is_nx_huge_page_enabled()) { 148 pte_access &= ~ACC_EXEC_MASK; 149 } 150 151 if (pte_access & ACC_EXEC_MASK) 152 spte |= shadow_x_mask; 153 else 154 spte |= shadow_nx_mask; 155 156 if (pte_access & ACC_USER_MASK) 157 spte |= shadow_user_mask; 158 159 if (level > PG_LEVEL_4K) 160 spte |= PT_PAGE_SIZE_MASK; 161 if (tdp_enabled) 162 spte |= static_call(kvm_x86_get_mt_mask)(vcpu, gfn, 163 kvm_is_mmio_pfn(pfn)); 164 165 if (host_writable) 166 spte |= shadow_host_writable_mask; 167 else 168 pte_access &= ~ACC_WRITE_MASK; 169 170 if (!kvm_is_mmio_pfn(pfn)) 171 spte |= shadow_me_mask; 172 173 spte |= (u64)pfn << PAGE_SHIFT; 174 175 if (pte_access & ACC_WRITE_MASK) { 176 spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask; 177 178 /* 179 * Optimization: for pte sync, if spte was writable the hash 180 * lookup is unnecessary (and expensive). Write protection 181 * is responsibility of kvm_mmu_get_page / kvm_mmu_sync_roots. 182 * Same reasoning can be applied to dirty page accounting. 183 */ 184 if (is_writable_pte(old_spte)) 185 goto out; 186 187 /* 188 * Unsync shadow pages that are reachable by the new, writable 189 * SPTE. Write-protect the SPTE if the page can't be unsync'd, 190 * e.g. it's write-tracked (upper-level SPs) or has one or more 191 * shadow pages and unsync'ing pages is not allowed. 192 */ 193 if (mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, can_unsync, prefetch)) { 194 pgprintk("%s: found shadow page for %llx, marking ro\n", 195 __func__, gfn); 196 wrprot = true; 197 pte_access &= ~ACC_WRITE_MASK; 198 spte &= ~(PT_WRITABLE_MASK | shadow_mmu_writable_mask); 199 } 200 } 201 202 if (pte_access & ACC_WRITE_MASK) 203 spte |= spte_shadow_dirty_mask(spte); 204 205 out: 206 if (prefetch) 207 spte = mark_spte_for_access_track(spte); 208 209 WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level), 210 "spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level, 211 get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level)); 212 213 if ((spte & PT_WRITABLE_MASK) && kvm_slot_dirty_track_enabled(slot)) { 214 /* Enforced by kvm_mmu_hugepage_adjust. */ 215 WARN_ON(level > PG_LEVEL_4K); 216 mark_page_dirty_in_slot(vcpu->kvm, slot, gfn); 217 } 218 219 *new_spte = spte; 220 return wrprot; 221 } 222 223 static u64 make_spte_executable(u64 spte) 224 { 225 bool is_access_track = is_access_track_spte(spte); 226 227 if (is_access_track) 228 spte = restore_acc_track_spte(spte); 229 230 spte &= ~shadow_nx_mask; 231 spte |= shadow_x_mask; 232 233 if (is_access_track) 234 spte = mark_spte_for_access_track(spte); 235 236 return spte; 237 } 238 239 /* 240 * Construct an SPTE that maps a sub-page of the given huge page SPTE where 241 * `index` identifies which sub-page. 242 * 243 * This is used during huge page splitting to build the SPTEs that make up the 244 * new page table. 245 */ 246 u64 make_huge_page_split_spte(u64 huge_spte, int huge_level, int index) 247 { 248 u64 child_spte; 249 int child_level; 250 251 if (WARN_ON_ONCE(!is_shadow_present_pte(huge_spte))) 252 return 0; 253 254 if (WARN_ON_ONCE(!is_large_pte(huge_spte))) 255 return 0; 256 257 child_spte = huge_spte; 258 child_level = huge_level - 1; 259 260 /* 261 * The child_spte already has the base address of the huge page being 262 * split. So we just have to OR in the offset to the page at the next 263 * lower level for the given index. 264 */ 265 child_spte |= (index * KVM_PAGES_PER_HPAGE(child_level)) << PAGE_SHIFT; 266 267 if (child_level == PG_LEVEL_4K) { 268 child_spte &= ~PT_PAGE_SIZE_MASK; 269 270 /* 271 * When splitting to a 4K page, mark the page executable as the 272 * NX hugepage mitigation no longer applies. 273 */ 274 if (is_nx_huge_page_enabled()) 275 child_spte = make_spte_executable(child_spte); 276 } 277 278 return child_spte; 279 } 280 281 282 u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled) 283 { 284 u64 spte = SPTE_MMU_PRESENT_MASK; 285 286 spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK | 287 shadow_user_mask | shadow_x_mask | shadow_me_mask; 288 289 if (ad_disabled) 290 spte |= SPTE_TDP_AD_DISABLED_MASK; 291 else 292 spte |= shadow_accessed_mask; 293 294 return spte; 295 } 296 297 u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn) 298 { 299 u64 new_spte; 300 301 new_spte = old_spte & ~PT64_BASE_ADDR_MASK; 302 new_spte |= (u64)new_pfn << PAGE_SHIFT; 303 304 new_spte &= ~PT_WRITABLE_MASK; 305 new_spte &= ~shadow_host_writable_mask; 306 new_spte &= ~shadow_mmu_writable_mask; 307 308 new_spte = mark_spte_for_access_track(new_spte); 309 310 return new_spte; 311 } 312 313 static u8 kvm_get_shadow_phys_bits(void) 314 { 315 /* 316 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected 317 * in CPU detection code, but the processor treats those reduced bits as 318 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at 319 * the physical address bits reported by CPUID. 320 */ 321 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008)) 322 return cpuid_eax(0x80000008) & 0xff; 323 324 /* 325 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with 326 * custom CPUID. Proceed with whatever the kernel found since these features 327 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008). 328 */ 329 return boot_cpu_data.x86_phys_bits; 330 } 331 332 u64 mark_spte_for_access_track(u64 spte) 333 { 334 if (spte_ad_enabled(spte)) 335 return spte & ~shadow_accessed_mask; 336 337 if (is_access_track_spte(spte)) 338 return spte; 339 340 check_spte_writable_invariants(spte); 341 342 WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK << 343 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT), 344 "kvm: Access Tracking saved bit locations are not zero\n"); 345 346 spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) << 347 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT; 348 spte &= ~shadow_acc_track_mask; 349 350 return spte; 351 } 352 353 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask) 354 { 355 BUG_ON((u64)(unsigned)access_mask != access_mask); 356 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask); 357 358 if (!enable_mmio_caching) 359 mmio_value = 0; 360 361 /* 362 * Disable MMIO caching if the MMIO value collides with the bits that 363 * are used to hold the relocated GFN when the L1TF mitigation is 364 * enabled. This should never fire as there is no known hardware that 365 * can trigger this condition, e.g. SME/SEV CPUs that require a custom 366 * MMIO value are not susceptible to L1TF. 367 */ 368 if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << 369 SHADOW_NONPRESENT_OR_RSVD_MASK_LEN))) 370 mmio_value = 0; 371 372 /* 373 * The masked MMIO value must obviously match itself and a removed SPTE 374 * must not get a false positive. Removed SPTEs and MMIO SPTEs should 375 * never collide as MMIO must set some RWX bits, and removed SPTEs must 376 * not set any RWX bits. 377 */ 378 if (WARN_ON((mmio_value & mmio_mask) != mmio_value) || 379 WARN_ON(mmio_value && (REMOVED_SPTE & mmio_mask) == mmio_value)) 380 mmio_value = 0; 381 382 shadow_mmio_value = mmio_value; 383 shadow_mmio_mask = mmio_mask; 384 shadow_mmio_access_mask = access_mask; 385 } 386 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); 387 388 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) 389 { 390 shadow_user_mask = VMX_EPT_READABLE_MASK; 391 shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull; 392 shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull; 393 shadow_nx_mask = 0ull; 394 shadow_x_mask = VMX_EPT_EXECUTABLE_MASK; 395 shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK; 396 shadow_acc_track_mask = VMX_EPT_RWX_MASK; 397 shadow_me_mask = 0ull; 398 399 shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE; 400 shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE; 401 402 /* 403 * EPT Misconfigurations are generated if the value of bits 2:0 404 * of an EPT paging-structure entry is 110b (write/execute). 405 */ 406 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 407 VMX_EPT_RWX_MASK, 0); 408 } 409 EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks); 410 411 void kvm_mmu_reset_all_pte_masks(void) 412 { 413 u8 low_phys_bits; 414 u64 mask; 415 416 shadow_phys_bits = kvm_get_shadow_phys_bits(); 417 418 /* 419 * If the CPU has 46 or less physical address bits, then set an 420 * appropriate mask to guard against L1TF attacks. Otherwise, it is 421 * assumed that the CPU is not vulnerable to L1TF. 422 * 423 * Some Intel CPUs address the L1 cache using more PA bits than are 424 * reported by CPUID. Use the PA width of the L1 cache when possible 425 * to achieve more effective mitigation, e.g. if system RAM overlaps 426 * the most significant bits of legal physical address space. 427 */ 428 shadow_nonpresent_or_rsvd_mask = 0; 429 low_phys_bits = boot_cpu_data.x86_phys_bits; 430 if (boot_cpu_has_bug(X86_BUG_L1TF) && 431 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >= 432 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) { 433 low_phys_bits = boot_cpu_data.x86_cache_bits 434 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 435 shadow_nonpresent_or_rsvd_mask = 436 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1); 437 } 438 439 shadow_nonpresent_or_rsvd_lower_gfn_mask = 440 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); 441 442 shadow_user_mask = PT_USER_MASK; 443 shadow_accessed_mask = PT_ACCESSED_MASK; 444 shadow_dirty_mask = PT_DIRTY_MASK; 445 shadow_nx_mask = PT64_NX_MASK; 446 shadow_x_mask = 0; 447 shadow_present_mask = PT_PRESENT_MASK; 448 shadow_acc_track_mask = 0; 449 shadow_me_mask = sme_me_mask; 450 451 shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITABLE; 452 shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITABLE; 453 454 /* 455 * Set a reserved PA bit in MMIO SPTEs to generate page faults with 456 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT 457 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports 458 * 52-bit physical addresses then there are no reserved PA bits in the 459 * PTEs and so the reserved PA approach must be disabled. 460 */ 461 if (shadow_phys_bits < 52) 462 mask = BIT_ULL(51) | PT_PRESENT_MASK; 463 else 464 mask = 0; 465 466 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); 467 } 468