1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * Macros and functions to access KVM PTEs (also known as SPTEs) 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2020 Red Hat, Inc. and/or its affiliates. 9 */ 10 11 12 #include <linux/kvm_host.h> 13 #include "mmu.h" 14 #include "mmu_internal.h" 15 #include "x86.h" 16 #include "spte.h" 17 18 #include <asm/e820/api.h> 19 #include <asm/memtype.h> 20 #include <asm/vmx.h> 21 22 bool __read_mostly enable_mmio_caching = true; 23 module_param_named(mmio_caching, enable_mmio_caching, bool, 0444); 24 25 u64 __read_mostly shadow_host_writable_mask; 26 u64 __read_mostly shadow_mmu_writable_mask; 27 u64 __read_mostly shadow_nx_mask; 28 u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ 29 u64 __read_mostly shadow_user_mask; 30 u64 __read_mostly shadow_accessed_mask; 31 u64 __read_mostly shadow_dirty_mask; 32 u64 __read_mostly shadow_mmio_value; 33 u64 __read_mostly shadow_mmio_mask; 34 u64 __read_mostly shadow_mmio_access_mask; 35 u64 __read_mostly shadow_present_mask; 36 u64 __read_mostly shadow_me_value; 37 u64 __read_mostly shadow_me_mask; 38 u64 __read_mostly shadow_acc_track_mask; 39 40 u64 __read_mostly shadow_nonpresent_or_rsvd_mask; 41 u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; 42 43 u8 __read_mostly shadow_phys_bits; 44 45 static u64 generation_mmio_spte_mask(u64 gen) 46 { 47 u64 mask; 48 49 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK); 50 51 mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK; 52 mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK; 53 return mask; 54 } 55 56 u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access) 57 { 58 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; 59 u64 spte = generation_mmio_spte_mask(gen); 60 u64 gpa = gfn << PAGE_SHIFT; 61 62 WARN_ON_ONCE(!shadow_mmio_value); 63 64 access &= shadow_mmio_access_mask; 65 spte |= shadow_mmio_value | access; 66 spte |= gpa | shadow_nonpresent_or_rsvd_mask; 67 spte |= (gpa & shadow_nonpresent_or_rsvd_mask) 68 << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 69 70 return spte; 71 } 72 73 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) 74 { 75 if (pfn_valid(pfn)) 76 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && 77 /* 78 * Some reserved pages, such as those from NVDIMM 79 * DAX devices, are not for MMIO, and can be mapped 80 * with cached memory type for better performance. 81 * However, the above check misconceives those pages 82 * as MMIO, and results in KVM mapping them with UC 83 * memory type, which would hurt the performance. 84 * Therefore, we check the host memory type in addition 85 * and only treat UC/UC-/WC pages as MMIO. 86 */ 87 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); 88 89 return !e820__mapped_raw_any(pfn_to_hpa(pfn), 90 pfn_to_hpa(pfn + 1) - 1, 91 E820_TYPE_RAM); 92 } 93 94 /* 95 * Returns true if the SPTE has bits that may be set without holding mmu_lock. 96 * The caller is responsible for checking if the SPTE is shadow-present, and 97 * for determining whether or not the caller cares about non-leaf SPTEs. 98 */ 99 bool spte_has_volatile_bits(u64 spte) 100 { 101 /* 102 * Always atomically update spte if it can be updated 103 * out of mmu-lock, it can ensure dirty bit is not lost, 104 * also, it can help us to get a stable is_writable_pte() 105 * to ensure tlb flush is not missed. 106 */ 107 if (!is_writable_pte(spte) && is_mmu_writable_spte(spte)) 108 return true; 109 110 if (is_access_track_spte(spte)) 111 return true; 112 113 if (spte_ad_enabled(spte)) { 114 if (!(spte & shadow_accessed_mask) || 115 (is_writable_pte(spte) && !(spte & shadow_dirty_mask))) 116 return true; 117 } 118 119 return false; 120 } 121 122 bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 123 const struct kvm_memory_slot *slot, 124 unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn, 125 u64 old_spte, bool prefetch, bool can_unsync, 126 bool host_writable, u64 *new_spte) 127 { 128 int level = sp->role.level; 129 u64 spte = SPTE_MMU_PRESENT_MASK; 130 bool wrprot = false; 131 132 WARN_ON_ONCE(!pte_access && !shadow_present_mask); 133 134 if (sp->role.ad_disabled) 135 spte |= SPTE_TDP_AD_DISABLED_MASK; 136 else if (kvm_mmu_page_ad_need_write_protect(sp)) 137 spte |= SPTE_TDP_AD_WRPROT_ONLY_MASK; 138 139 /* 140 * For the EPT case, shadow_present_mask is 0 if hardware 141 * supports exec-only page table entries. In that case, 142 * ACC_USER_MASK and shadow_user_mask are used to represent 143 * read access. See FNAME(gpte_access) in paging_tmpl.h. 144 */ 145 spte |= shadow_present_mask; 146 if (!prefetch) 147 spte |= spte_shadow_accessed_mask(spte); 148 149 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) && 150 is_nx_huge_page_enabled()) { 151 pte_access &= ~ACC_EXEC_MASK; 152 } 153 154 if (pte_access & ACC_EXEC_MASK) 155 spte |= shadow_x_mask; 156 else 157 spte |= shadow_nx_mask; 158 159 if (pte_access & ACC_USER_MASK) 160 spte |= shadow_user_mask; 161 162 if (level > PG_LEVEL_4K) 163 spte |= PT_PAGE_SIZE_MASK; 164 if (tdp_enabled) 165 spte |= static_call(kvm_x86_get_mt_mask)(vcpu, gfn, 166 kvm_is_mmio_pfn(pfn)); 167 168 if (host_writable) 169 spte |= shadow_host_writable_mask; 170 else 171 pte_access &= ~ACC_WRITE_MASK; 172 173 if (shadow_me_value && !kvm_is_mmio_pfn(pfn)) 174 spte |= shadow_me_value; 175 176 spte |= (u64)pfn << PAGE_SHIFT; 177 178 if (pte_access & ACC_WRITE_MASK) { 179 spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask; 180 181 /* 182 * Optimization: for pte sync, if spte was writable the hash 183 * lookup is unnecessary (and expensive). Write protection 184 * is responsibility of kvm_mmu_get_page / kvm_mmu_sync_roots. 185 * Same reasoning can be applied to dirty page accounting. 186 */ 187 if (is_writable_pte(old_spte)) 188 goto out; 189 190 /* 191 * Unsync shadow pages that are reachable by the new, writable 192 * SPTE. Write-protect the SPTE if the page can't be unsync'd, 193 * e.g. it's write-tracked (upper-level SPs) or has one or more 194 * shadow pages and unsync'ing pages is not allowed. 195 */ 196 if (mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, can_unsync, prefetch)) { 197 pgprintk("%s: found shadow page for %llx, marking ro\n", 198 __func__, gfn); 199 wrprot = true; 200 pte_access &= ~ACC_WRITE_MASK; 201 spte &= ~(PT_WRITABLE_MASK | shadow_mmu_writable_mask); 202 } 203 } 204 205 if (pte_access & ACC_WRITE_MASK) 206 spte |= spte_shadow_dirty_mask(spte); 207 208 out: 209 if (prefetch) 210 spte = mark_spte_for_access_track(spte); 211 212 WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level), 213 "spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level, 214 get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level)); 215 216 if ((spte & PT_WRITABLE_MASK) && kvm_slot_dirty_track_enabled(slot)) { 217 /* Enforced by kvm_mmu_hugepage_adjust. */ 218 WARN_ON(level > PG_LEVEL_4K); 219 mark_page_dirty_in_slot(vcpu->kvm, slot, gfn); 220 } 221 222 *new_spte = spte; 223 return wrprot; 224 } 225 226 static u64 make_spte_executable(u64 spte) 227 { 228 bool is_access_track = is_access_track_spte(spte); 229 230 if (is_access_track) 231 spte = restore_acc_track_spte(spte); 232 233 spte &= ~shadow_nx_mask; 234 spte |= shadow_x_mask; 235 236 if (is_access_track) 237 spte = mark_spte_for_access_track(spte); 238 239 return spte; 240 } 241 242 /* 243 * Construct an SPTE that maps a sub-page of the given huge page SPTE where 244 * `index` identifies which sub-page. 245 * 246 * This is used during huge page splitting to build the SPTEs that make up the 247 * new page table. 248 */ 249 u64 make_huge_page_split_spte(u64 huge_spte, int huge_level, int index) 250 { 251 u64 child_spte; 252 int child_level; 253 254 if (WARN_ON_ONCE(!is_shadow_present_pte(huge_spte))) 255 return 0; 256 257 if (WARN_ON_ONCE(!is_large_pte(huge_spte))) 258 return 0; 259 260 child_spte = huge_spte; 261 child_level = huge_level - 1; 262 263 /* 264 * The child_spte already has the base address of the huge page being 265 * split. So we just have to OR in the offset to the page at the next 266 * lower level for the given index. 267 */ 268 child_spte |= (index * KVM_PAGES_PER_HPAGE(child_level)) << PAGE_SHIFT; 269 270 if (child_level == PG_LEVEL_4K) { 271 child_spte &= ~PT_PAGE_SIZE_MASK; 272 273 /* 274 * When splitting to a 4K page, mark the page executable as the 275 * NX hugepage mitigation no longer applies. 276 */ 277 if (is_nx_huge_page_enabled()) 278 child_spte = make_spte_executable(child_spte); 279 } 280 281 return child_spte; 282 } 283 284 285 u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled) 286 { 287 u64 spte = SPTE_MMU_PRESENT_MASK; 288 289 spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK | 290 shadow_user_mask | shadow_x_mask | shadow_me_value; 291 292 if (ad_disabled) 293 spte |= SPTE_TDP_AD_DISABLED_MASK; 294 else 295 spte |= shadow_accessed_mask; 296 297 return spte; 298 } 299 300 u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn) 301 { 302 u64 new_spte; 303 304 new_spte = old_spte & ~PT64_BASE_ADDR_MASK; 305 new_spte |= (u64)new_pfn << PAGE_SHIFT; 306 307 new_spte &= ~PT_WRITABLE_MASK; 308 new_spte &= ~shadow_host_writable_mask; 309 new_spte &= ~shadow_mmu_writable_mask; 310 311 new_spte = mark_spte_for_access_track(new_spte); 312 313 return new_spte; 314 } 315 316 u64 mark_spte_for_access_track(u64 spte) 317 { 318 if (spte_ad_enabled(spte)) 319 return spte & ~shadow_accessed_mask; 320 321 if (is_access_track_spte(spte)) 322 return spte; 323 324 check_spte_writable_invariants(spte); 325 326 WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK << 327 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT), 328 "kvm: Access Tracking saved bit locations are not zero\n"); 329 330 spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) << 331 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT; 332 spte &= ~shadow_acc_track_mask; 333 334 return spte; 335 } 336 337 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask) 338 { 339 BUG_ON((u64)(unsigned)access_mask != access_mask); 340 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask); 341 342 if (!enable_mmio_caching) 343 mmio_value = 0; 344 345 /* 346 * Disable MMIO caching if the MMIO value collides with the bits that 347 * are used to hold the relocated GFN when the L1TF mitigation is 348 * enabled. This should never fire as there is no known hardware that 349 * can trigger this condition, e.g. SME/SEV CPUs that require a custom 350 * MMIO value are not susceptible to L1TF. 351 */ 352 if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << 353 SHADOW_NONPRESENT_OR_RSVD_MASK_LEN))) 354 mmio_value = 0; 355 356 /* 357 * The masked MMIO value must obviously match itself and a removed SPTE 358 * must not get a false positive. Removed SPTEs and MMIO SPTEs should 359 * never collide as MMIO must set some RWX bits, and removed SPTEs must 360 * not set any RWX bits. 361 */ 362 if (WARN_ON((mmio_value & mmio_mask) != mmio_value) || 363 WARN_ON(mmio_value && (REMOVED_SPTE & mmio_mask) == mmio_value)) 364 mmio_value = 0; 365 366 if (!mmio_value) 367 enable_mmio_caching = false; 368 369 shadow_mmio_value = mmio_value; 370 shadow_mmio_mask = mmio_mask; 371 shadow_mmio_access_mask = access_mask; 372 } 373 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); 374 375 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask) 376 { 377 /* shadow_me_value must be a subset of shadow_me_mask */ 378 if (WARN_ON(me_value & ~me_mask)) 379 me_value = me_mask = 0; 380 381 shadow_me_value = me_value; 382 shadow_me_mask = me_mask; 383 } 384 EXPORT_SYMBOL_GPL(kvm_mmu_set_me_spte_mask); 385 386 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) 387 { 388 shadow_user_mask = VMX_EPT_READABLE_MASK; 389 shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull; 390 shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull; 391 shadow_nx_mask = 0ull; 392 shadow_x_mask = VMX_EPT_EXECUTABLE_MASK; 393 shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK; 394 shadow_acc_track_mask = VMX_EPT_RWX_MASK; 395 shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE; 396 shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE; 397 398 /* 399 * EPT Misconfigurations are generated if the value of bits 2:0 400 * of an EPT paging-structure entry is 110b (write/execute). 401 */ 402 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 403 VMX_EPT_RWX_MASK, 0); 404 } 405 EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks); 406 407 void kvm_mmu_reset_all_pte_masks(void) 408 { 409 u8 low_phys_bits; 410 u64 mask; 411 412 shadow_phys_bits = kvm_get_shadow_phys_bits(); 413 414 /* 415 * If the CPU has 46 or less physical address bits, then set an 416 * appropriate mask to guard against L1TF attacks. Otherwise, it is 417 * assumed that the CPU is not vulnerable to L1TF. 418 * 419 * Some Intel CPUs address the L1 cache using more PA bits than are 420 * reported by CPUID. Use the PA width of the L1 cache when possible 421 * to achieve more effective mitigation, e.g. if system RAM overlaps 422 * the most significant bits of legal physical address space. 423 */ 424 shadow_nonpresent_or_rsvd_mask = 0; 425 low_phys_bits = boot_cpu_data.x86_phys_bits; 426 if (boot_cpu_has_bug(X86_BUG_L1TF) && 427 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >= 428 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) { 429 low_phys_bits = boot_cpu_data.x86_cache_bits 430 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 431 shadow_nonpresent_or_rsvd_mask = 432 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1); 433 } 434 435 shadow_nonpresent_or_rsvd_lower_gfn_mask = 436 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); 437 438 shadow_user_mask = PT_USER_MASK; 439 shadow_accessed_mask = PT_ACCESSED_MASK; 440 shadow_dirty_mask = PT_DIRTY_MASK; 441 shadow_nx_mask = PT64_NX_MASK; 442 shadow_x_mask = 0; 443 shadow_present_mask = PT_PRESENT_MASK; 444 shadow_acc_track_mask = 0; 445 shadow_me_mask = 0; 446 shadow_me_value = 0; 447 448 shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITABLE; 449 shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITABLE; 450 451 /* 452 * Set a reserved PA bit in MMIO SPTEs to generate page faults with 453 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT 454 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports 455 * 52-bit physical addresses then there are no reserved PA bits in the 456 * PTEs and so the reserved PA approach must be disabled. 457 */ 458 if (shadow_phys_bits < 52) 459 mask = BIT_ULL(51) | PT_PRESENT_MASK; 460 else 461 mask = 0; 462 463 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); 464 } 465