1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * Macros and functions to access KVM PTEs (also known as SPTEs) 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2020 Red Hat, Inc. and/or its affiliates. 9 */ 10 11 12 #include <linux/kvm_host.h> 13 #include "mmu.h" 14 #include "mmu_internal.h" 15 #include "x86.h" 16 #include "spte.h" 17 18 #include <asm/e820/api.h> 19 #include <asm/memtype.h> 20 #include <asm/vmx.h> 21 22 static bool __read_mostly enable_mmio_caching = true; 23 module_param_named(mmio_caching, enable_mmio_caching, bool, 0444); 24 25 u64 __read_mostly shadow_host_writable_mask; 26 u64 __read_mostly shadow_mmu_writable_mask; 27 u64 __read_mostly shadow_nx_mask; 28 u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ 29 u64 __read_mostly shadow_user_mask; 30 u64 __read_mostly shadow_accessed_mask; 31 u64 __read_mostly shadow_dirty_mask; 32 u64 __read_mostly shadow_mmio_value; 33 u64 __read_mostly shadow_mmio_mask; 34 u64 __read_mostly shadow_mmio_access_mask; 35 u64 __read_mostly shadow_present_mask; 36 u64 __read_mostly shadow_me_mask; 37 u64 __read_mostly shadow_acc_track_mask; 38 39 u64 __read_mostly shadow_nonpresent_or_rsvd_mask; 40 u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; 41 42 u8 __read_mostly shadow_phys_bits; 43 44 static u64 generation_mmio_spte_mask(u64 gen) 45 { 46 u64 mask; 47 48 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK); 49 50 mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK; 51 mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK; 52 return mask; 53 } 54 55 u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access) 56 { 57 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; 58 u64 spte = generation_mmio_spte_mask(gen); 59 u64 gpa = gfn << PAGE_SHIFT; 60 61 WARN_ON_ONCE(!shadow_mmio_value); 62 63 access &= shadow_mmio_access_mask; 64 spte |= shadow_mmio_value | access; 65 spte |= gpa | shadow_nonpresent_or_rsvd_mask; 66 spte |= (gpa & shadow_nonpresent_or_rsvd_mask) 67 << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 68 69 return spte; 70 } 71 72 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) 73 { 74 if (pfn_valid(pfn)) 75 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && 76 /* 77 * Some reserved pages, such as those from NVDIMM 78 * DAX devices, are not for MMIO, and can be mapped 79 * with cached memory type for better performance. 80 * However, the above check misconceives those pages 81 * as MMIO, and results in KVM mapping them with UC 82 * memory type, which would hurt the performance. 83 * Therefore, we check the host memory type in addition 84 * and only treat UC/UC-/WC pages as MMIO. 85 */ 86 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); 87 88 return !e820__mapped_raw_any(pfn_to_hpa(pfn), 89 pfn_to_hpa(pfn + 1) - 1, 90 E820_TYPE_RAM); 91 } 92 93 bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 94 const struct kvm_memory_slot *slot, 95 unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn, 96 u64 old_spte, bool prefetch, bool can_unsync, 97 bool host_writable, u64 *new_spte) 98 { 99 int level = sp->role.level; 100 u64 spte = SPTE_MMU_PRESENT_MASK; 101 bool wrprot = false; 102 103 if (sp->role.ad_disabled) 104 spte |= SPTE_TDP_AD_DISABLED_MASK; 105 else if (kvm_mmu_page_ad_need_write_protect(sp)) 106 spte |= SPTE_TDP_AD_WRPROT_ONLY_MASK; 107 108 /* 109 * For the EPT case, shadow_present_mask is 0 if hardware 110 * supports exec-only page table entries. In that case, 111 * ACC_USER_MASK and shadow_user_mask are used to represent 112 * read access. See FNAME(gpte_access) in paging_tmpl.h. 113 */ 114 spte |= shadow_present_mask; 115 if (!prefetch) 116 spte |= spte_shadow_accessed_mask(spte); 117 118 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) && 119 is_nx_huge_page_enabled()) { 120 pte_access &= ~ACC_EXEC_MASK; 121 } 122 123 if (pte_access & ACC_EXEC_MASK) 124 spte |= shadow_x_mask; 125 else 126 spte |= shadow_nx_mask; 127 128 if (pte_access & ACC_USER_MASK) 129 spte |= shadow_user_mask; 130 131 if (level > PG_LEVEL_4K) 132 spte |= PT_PAGE_SIZE_MASK; 133 if (tdp_enabled) 134 spte |= static_call(kvm_x86_get_mt_mask)(vcpu, gfn, 135 kvm_is_mmio_pfn(pfn)); 136 137 if (host_writable) 138 spte |= shadow_host_writable_mask; 139 else 140 pte_access &= ~ACC_WRITE_MASK; 141 142 if (!kvm_is_mmio_pfn(pfn)) 143 spte |= shadow_me_mask; 144 145 spte |= (u64)pfn << PAGE_SHIFT; 146 147 if (pte_access & ACC_WRITE_MASK) { 148 spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask; 149 150 /* 151 * Optimization: for pte sync, if spte was writable the hash 152 * lookup is unnecessary (and expensive). Write protection 153 * is responsibility of kvm_mmu_get_page / kvm_mmu_sync_roots. 154 * Same reasoning can be applied to dirty page accounting. 155 */ 156 if (is_writable_pte(old_spte)) 157 goto out; 158 159 /* 160 * Unsync shadow pages that are reachable by the new, writable 161 * SPTE. Write-protect the SPTE if the page can't be unsync'd, 162 * e.g. it's write-tracked (upper-level SPs) or has one or more 163 * shadow pages and unsync'ing pages is not allowed. 164 */ 165 if (mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, can_unsync, prefetch)) { 166 pgprintk("%s: found shadow page for %llx, marking ro\n", 167 __func__, gfn); 168 wrprot = true; 169 pte_access &= ~ACC_WRITE_MASK; 170 spte &= ~(PT_WRITABLE_MASK | shadow_mmu_writable_mask); 171 } 172 } 173 174 if (pte_access & ACC_WRITE_MASK) 175 spte |= spte_shadow_dirty_mask(spte); 176 177 out: 178 if (prefetch) 179 spte = mark_spte_for_access_track(spte); 180 181 WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level), 182 "spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level, 183 get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level)); 184 185 if ((spte & PT_WRITABLE_MASK) && kvm_slot_dirty_track_enabled(slot)) { 186 /* Enforced by kvm_mmu_hugepage_adjust. */ 187 WARN_ON(level > PG_LEVEL_4K); 188 mark_page_dirty_in_slot(vcpu->kvm, slot, gfn); 189 } 190 191 *new_spte = spte; 192 return wrprot; 193 } 194 195 u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled) 196 { 197 u64 spte = SPTE_MMU_PRESENT_MASK; 198 199 spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK | 200 shadow_user_mask | shadow_x_mask | shadow_me_mask; 201 202 if (ad_disabled) 203 spte |= SPTE_TDP_AD_DISABLED_MASK; 204 else 205 spte |= shadow_accessed_mask; 206 207 return spte; 208 } 209 210 u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn) 211 { 212 u64 new_spte; 213 214 new_spte = old_spte & ~PT64_BASE_ADDR_MASK; 215 new_spte |= (u64)new_pfn << PAGE_SHIFT; 216 217 new_spte &= ~PT_WRITABLE_MASK; 218 new_spte &= ~shadow_host_writable_mask; 219 new_spte &= ~shadow_mmu_writable_mask; 220 221 new_spte = mark_spte_for_access_track(new_spte); 222 223 return new_spte; 224 } 225 226 static u8 kvm_get_shadow_phys_bits(void) 227 { 228 /* 229 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected 230 * in CPU detection code, but the processor treats those reduced bits as 231 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at 232 * the physical address bits reported by CPUID. 233 */ 234 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008)) 235 return cpuid_eax(0x80000008) & 0xff; 236 237 /* 238 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with 239 * custom CPUID. Proceed with whatever the kernel found since these features 240 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008). 241 */ 242 return boot_cpu_data.x86_phys_bits; 243 } 244 245 u64 mark_spte_for_access_track(u64 spte) 246 { 247 if (spte_ad_enabled(spte)) 248 return spte & ~shadow_accessed_mask; 249 250 if (is_access_track_spte(spte)) 251 return spte; 252 253 /* 254 * Making an Access Tracking PTE will result in removal of write access 255 * from the PTE. So, verify that we will be able to restore the write 256 * access in the fast page fault path later on. 257 */ 258 WARN_ONCE((spte & PT_WRITABLE_MASK) && 259 !spte_can_locklessly_be_made_writable(spte), 260 "kvm: Writable SPTE is not locklessly dirty-trackable\n"); 261 262 WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK << 263 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT), 264 "kvm: Access Tracking saved bit locations are not zero\n"); 265 266 spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) << 267 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT; 268 spte &= ~shadow_acc_track_mask; 269 270 return spte; 271 } 272 273 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask) 274 { 275 BUG_ON((u64)(unsigned)access_mask != access_mask); 276 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask); 277 278 if (!enable_mmio_caching) 279 mmio_value = 0; 280 281 /* 282 * Disable MMIO caching if the MMIO value collides with the bits that 283 * are used to hold the relocated GFN when the L1TF mitigation is 284 * enabled. This should never fire as there is no known hardware that 285 * can trigger this condition, e.g. SME/SEV CPUs that require a custom 286 * MMIO value are not susceptible to L1TF. 287 */ 288 if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << 289 SHADOW_NONPRESENT_OR_RSVD_MASK_LEN))) 290 mmio_value = 0; 291 292 /* 293 * The masked MMIO value must obviously match itself and a removed SPTE 294 * must not get a false positive. Removed SPTEs and MMIO SPTEs should 295 * never collide as MMIO must set some RWX bits, and removed SPTEs must 296 * not set any RWX bits. 297 */ 298 if (WARN_ON((mmio_value & mmio_mask) != mmio_value) || 299 WARN_ON(mmio_value && (REMOVED_SPTE & mmio_mask) == mmio_value)) 300 mmio_value = 0; 301 302 shadow_mmio_value = mmio_value; 303 shadow_mmio_mask = mmio_mask; 304 shadow_mmio_access_mask = access_mask; 305 } 306 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); 307 308 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) 309 { 310 shadow_user_mask = VMX_EPT_READABLE_MASK; 311 shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull; 312 shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull; 313 shadow_nx_mask = 0ull; 314 shadow_x_mask = VMX_EPT_EXECUTABLE_MASK; 315 shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK; 316 shadow_acc_track_mask = VMX_EPT_RWX_MASK; 317 shadow_me_mask = 0ull; 318 319 shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE; 320 shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE; 321 322 /* 323 * EPT Misconfigurations are generated if the value of bits 2:0 324 * of an EPT paging-structure entry is 110b (write/execute). 325 */ 326 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 327 VMX_EPT_RWX_MASK, 0); 328 } 329 EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks); 330 331 void kvm_mmu_reset_all_pte_masks(void) 332 { 333 u8 low_phys_bits; 334 u64 mask; 335 336 shadow_phys_bits = kvm_get_shadow_phys_bits(); 337 338 /* 339 * If the CPU has 46 or less physical address bits, then set an 340 * appropriate mask to guard against L1TF attacks. Otherwise, it is 341 * assumed that the CPU is not vulnerable to L1TF. 342 * 343 * Some Intel CPUs address the L1 cache using more PA bits than are 344 * reported by CPUID. Use the PA width of the L1 cache when possible 345 * to achieve more effective mitigation, e.g. if system RAM overlaps 346 * the most significant bits of legal physical address space. 347 */ 348 shadow_nonpresent_or_rsvd_mask = 0; 349 low_phys_bits = boot_cpu_data.x86_phys_bits; 350 if (boot_cpu_has_bug(X86_BUG_L1TF) && 351 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >= 352 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) { 353 low_phys_bits = boot_cpu_data.x86_cache_bits 354 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 355 shadow_nonpresent_or_rsvd_mask = 356 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1); 357 } 358 359 shadow_nonpresent_or_rsvd_lower_gfn_mask = 360 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); 361 362 shadow_user_mask = PT_USER_MASK; 363 shadow_accessed_mask = PT_ACCESSED_MASK; 364 shadow_dirty_mask = PT_DIRTY_MASK; 365 shadow_nx_mask = PT64_NX_MASK; 366 shadow_x_mask = 0; 367 shadow_present_mask = PT_PRESENT_MASK; 368 shadow_acc_track_mask = 0; 369 shadow_me_mask = sme_me_mask; 370 371 shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITEABLE; 372 shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITEABLE; 373 374 /* 375 * Set a reserved PA bit in MMIO SPTEs to generate page faults with 376 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT 377 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports 378 * 52-bit physical addresses then there are no reserved PA bits in the 379 * PTEs and so the reserved PA approach must be disabled. 380 */ 381 if (shadow_phys_bits < 52) 382 mask = BIT_ULL(51) | PT_PRESENT_MASK; 383 else 384 mask = 0; 385 386 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); 387 } 388