1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * Macros and functions to access KVM PTEs (also known as SPTEs) 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2020 Red Hat, Inc. and/or its affiliates. 9 */ 10 11 12 #include <linux/kvm_host.h> 13 #include "mmu.h" 14 #include "mmu_internal.h" 15 #include "x86.h" 16 #include "spte.h" 17 18 #include <asm/e820/api.h> 19 #include <asm/memtype.h> 20 #include <asm/vmx.h> 21 22 static bool __read_mostly enable_mmio_caching = true; 23 module_param_named(mmio_caching, enable_mmio_caching, bool, 0444); 24 25 u64 __read_mostly shadow_host_writable_mask; 26 u64 __read_mostly shadow_mmu_writable_mask; 27 u64 __read_mostly shadow_nx_mask; 28 u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ 29 u64 __read_mostly shadow_user_mask; 30 u64 __read_mostly shadow_accessed_mask; 31 u64 __read_mostly shadow_dirty_mask; 32 u64 __read_mostly shadow_mmio_value; 33 u64 __read_mostly shadow_mmio_mask; 34 u64 __read_mostly shadow_mmio_access_mask; 35 u64 __read_mostly shadow_present_mask; 36 u64 __read_mostly shadow_me_mask; 37 u64 __read_mostly shadow_acc_track_mask; 38 39 u64 __read_mostly shadow_nonpresent_or_rsvd_mask; 40 u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; 41 42 u8 __read_mostly shadow_phys_bits; 43 44 static u64 generation_mmio_spte_mask(u64 gen) 45 { 46 u64 mask; 47 48 WARN_ON(gen & ~MMIO_SPTE_GEN_MASK); 49 50 mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK; 51 mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK; 52 return mask; 53 } 54 55 u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access) 56 { 57 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; 58 u64 spte = generation_mmio_spte_mask(gen); 59 u64 gpa = gfn << PAGE_SHIFT; 60 61 WARN_ON_ONCE(!shadow_mmio_value); 62 63 access &= shadow_mmio_access_mask; 64 spte |= shadow_mmio_value | access; 65 spte |= gpa | shadow_nonpresent_or_rsvd_mask; 66 spte |= (gpa & shadow_nonpresent_or_rsvd_mask) 67 << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 68 69 return spte; 70 } 71 72 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) 73 { 74 if (pfn_valid(pfn)) 75 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && 76 /* 77 * Some reserved pages, such as those from NVDIMM 78 * DAX devices, are not for MMIO, and can be mapped 79 * with cached memory type for better performance. 80 * However, the above check misconceives those pages 81 * as MMIO, and results in KVM mapping them with UC 82 * memory type, which would hurt the performance. 83 * Therefore, we check the host memory type in addition 84 * and only treat UC/UC-/WC pages as MMIO. 85 */ 86 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); 87 88 return !e820__mapped_raw_any(pfn_to_hpa(pfn), 89 pfn_to_hpa(pfn + 1) - 1, 90 E820_TYPE_RAM); 91 } 92 93 bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 94 const struct kvm_memory_slot *slot, 95 unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn, 96 u64 old_spte, bool prefetch, bool can_unsync, 97 bool host_writable, u64 *new_spte) 98 { 99 int level = sp->role.level; 100 u64 spte = SPTE_MMU_PRESENT_MASK; 101 bool wrprot = false; 102 103 if (sp->role.ad_disabled) 104 spte |= SPTE_TDP_AD_DISABLED_MASK; 105 else if (kvm_mmu_page_ad_need_write_protect(sp)) 106 spte |= SPTE_TDP_AD_WRPROT_ONLY_MASK; 107 108 /* 109 * For the EPT case, shadow_present_mask is 0 if hardware 110 * supports exec-only page table entries. In that case, 111 * ACC_USER_MASK and shadow_user_mask are used to represent 112 * read access. See FNAME(gpte_access) in paging_tmpl.h. 113 */ 114 spte |= shadow_present_mask; 115 if (!prefetch) 116 spte |= spte_shadow_accessed_mask(spte); 117 118 if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) && 119 is_nx_huge_page_enabled()) { 120 pte_access &= ~ACC_EXEC_MASK; 121 } 122 123 if (pte_access & ACC_EXEC_MASK) 124 spte |= shadow_x_mask; 125 else 126 spte |= shadow_nx_mask; 127 128 if (pte_access & ACC_USER_MASK) 129 spte |= shadow_user_mask; 130 131 if (level > PG_LEVEL_4K) 132 spte |= PT_PAGE_SIZE_MASK; 133 if (tdp_enabled) 134 spte |= static_call(kvm_x86_get_mt_mask)(vcpu, gfn, 135 kvm_is_mmio_pfn(pfn)); 136 137 if (host_writable) 138 spte |= shadow_host_writable_mask; 139 else 140 pte_access &= ~ACC_WRITE_MASK; 141 142 if (!kvm_is_mmio_pfn(pfn)) 143 spte |= shadow_me_mask; 144 145 spte |= (u64)pfn << PAGE_SHIFT; 146 147 if (pte_access & ACC_WRITE_MASK) { 148 spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask; 149 150 /* 151 * Optimization: for pte sync, if spte was writable the hash 152 * lookup is unnecessary (and expensive). Write protection 153 * is responsibility of kvm_mmu_get_page / kvm_mmu_sync_roots. 154 * Same reasoning can be applied to dirty page accounting. 155 */ 156 if (is_writable_pte(old_spte)) 157 goto out; 158 159 /* 160 * Unsync shadow pages that are reachable by the new, writable 161 * SPTE. Write-protect the SPTE if the page can't be unsync'd, 162 * e.g. it's write-tracked (upper-level SPs) or has one or more 163 * shadow pages and unsync'ing pages is not allowed. 164 */ 165 if (mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, can_unsync, prefetch)) { 166 pgprintk("%s: found shadow page for %llx, marking ro\n", 167 __func__, gfn); 168 wrprot = true; 169 pte_access &= ~ACC_WRITE_MASK; 170 spte &= ~(PT_WRITABLE_MASK | shadow_mmu_writable_mask); 171 } 172 } 173 174 if (pte_access & ACC_WRITE_MASK) 175 spte |= spte_shadow_dirty_mask(spte); 176 177 out: 178 if (prefetch) 179 spte = mark_spte_for_access_track(spte); 180 181 WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level), 182 "spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level, 183 get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level)); 184 185 if ((spte & PT_WRITABLE_MASK) && kvm_slot_dirty_track_enabled(slot)) { 186 /* Enforced by kvm_mmu_hugepage_adjust. */ 187 WARN_ON(level > PG_LEVEL_4K); 188 mark_page_dirty_in_slot(vcpu->kvm, slot, gfn); 189 } 190 191 *new_spte = spte; 192 return wrprot; 193 } 194 195 static u64 make_spte_executable(u64 spte) 196 { 197 bool is_access_track = is_access_track_spte(spte); 198 199 if (is_access_track) 200 spte = restore_acc_track_spte(spte); 201 202 spte &= ~shadow_nx_mask; 203 spte |= shadow_x_mask; 204 205 if (is_access_track) 206 spte = mark_spte_for_access_track(spte); 207 208 return spte; 209 } 210 211 /* 212 * Construct an SPTE that maps a sub-page of the given huge page SPTE where 213 * `index` identifies which sub-page. 214 * 215 * This is used during huge page splitting to build the SPTEs that make up the 216 * new page table. 217 */ 218 u64 make_huge_page_split_spte(u64 huge_spte, int huge_level, int index) 219 { 220 u64 child_spte; 221 int child_level; 222 223 if (WARN_ON_ONCE(!is_shadow_present_pte(huge_spte))) 224 return 0; 225 226 if (WARN_ON_ONCE(!is_large_pte(huge_spte))) 227 return 0; 228 229 child_spte = huge_spte; 230 child_level = huge_level - 1; 231 232 /* 233 * The child_spte already has the base address of the huge page being 234 * split. So we just have to OR in the offset to the page at the next 235 * lower level for the given index. 236 */ 237 child_spte |= (index * KVM_PAGES_PER_HPAGE(child_level)) << PAGE_SHIFT; 238 239 if (child_level == PG_LEVEL_4K) { 240 child_spte &= ~PT_PAGE_SIZE_MASK; 241 242 /* 243 * When splitting to a 4K page, mark the page executable as the 244 * NX hugepage mitigation no longer applies. 245 */ 246 if (is_nx_huge_page_enabled()) 247 child_spte = make_spte_executable(child_spte); 248 } 249 250 return child_spte; 251 } 252 253 254 u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled) 255 { 256 u64 spte = SPTE_MMU_PRESENT_MASK; 257 258 spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK | 259 shadow_user_mask | shadow_x_mask | shadow_me_mask; 260 261 if (ad_disabled) 262 spte |= SPTE_TDP_AD_DISABLED_MASK; 263 else 264 spte |= shadow_accessed_mask; 265 266 return spte; 267 } 268 269 u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn) 270 { 271 u64 new_spte; 272 273 new_spte = old_spte & ~PT64_BASE_ADDR_MASK; 274 new_spte |= (u64)new_pfn << PAGE_SHIFT; 275 276 new_spte &= ~PT_WRITABLE_MASK; 277 new_spte &= ~shadow_host_writable_mask; 278 new_spte &= ~shadow_mmu_writable_mask; 279 280 new_spte = mark_spte_for_access_track(new_spte); 281 282 return new_spte; 283 } 284 285 static u8 kvm_get_shadow_phys_bits(void) 286 { 287 /* 288 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected 289 * in CPU detection code, but the processor treats those reduced bits as 290 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at 291 * the physical address bits reported by CPUID. 292 */ 293 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008)) 294 return cpuid_eax(0x80000008) & 0xff; 295 296 /* 297 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with 298 * custom CPUID. Proceed with whatever the kernel found since these features 299 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008). 300 */ 301 return boot_cpu_data.x86_phys_bits; 302 } 303 304 u64 mark_spte_for_access_track(u64 spte) 305 { 306 if (spte_ad_enabled(spte)) 307 return spte & ~shadow_accessed_mask; 308 309 if (is_access_track_spte(spte)) 310 return spte; 311 312 check_spte_writable_invariants(spte); 313 314 WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK << 315 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT), 316 "kvm: Access Tracking saved bit locations are not zero\n"); 317 318 spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) << 319 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT; 320 spte &= ~shadow_acc_track_mask; 321 322 return spte; 323 } 324 325 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask) 326 { 327 BUG_ON((u64)(unsigned)access_mask != access_mask); 328 WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask); 329 330 if (!enable_mmio_caching) 331 mmio_value = 0; 332 333 /* 334 * Disable MMIO caching if the MMIO value collides with the bits that 335 * are used to hold the relocated GFN when the L1TF mitigation is 336 * enabled. This should never fire as there is no known hardware that 337 * can trigger this condition, e.g. SME/SEV CPUs that require a custom 338 * MMIO value are not susceptible to L1TF. 339 */ 340 if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << 341 SHADOW_NONPRESENT_OR_RSVD_MASK_LEN))) 342 mmio_value = 0; 343 344 /* 345 * The masked MMIO value must obviously match itself and a removed SPTE 346 * must not get a false positive. Removed SPTEs and MMIO SPTEs should 347 * never collide as MMIO must set some RWX bits, and removed SPTEs must 348 * not set any RWX bits. 349 */ 350 if (WARN_ON((mmio_value & mmio_mask) != mmio_value) || 351 WARN_ON(mmio_value && (REMOVED_SPTE & mmio_mask) == mmio_value)) 352 mmio_value = 0; 353 354 shadow_mmio_value = mmio_value; 355 shadow_mmio_mask = mmio_mask; 356 shadow_mmio_access_mask = access_mask; 357 } 358 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); 359 360 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) 361 { 362 shadow_user_mask = VMX_EPT_READABLE_MASK; 363 shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull; 364 shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull; 365 shadow_nx_mask = 0ull; 366 shadow_x_mask = VMX_EPT_EXECUTABLE_MASK; 367 shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK; 368 shadow_acc_track_mask = VMX_EPT_RWX_MASK; 369 shadow_me_mask = 0ull; 370 371 shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE; 372 shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE; 373 374 /* 375 * EPT Misconfigurations are generated if the value of bits 2:0 376 * of an EPT paging-structure entry is 110b (write/execute). 377 */ 378 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 379 VMX_EPT_RWX_MASK, 0); 380 } 381 EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks); 382 383 void kvm_mmu_reset_all_pte_masks(void) 384 { 385 u8 low_phys_bits; 386 u64 mask; 387 388 shadow_phys_bits = kvm_get_shadow_phys_bits(); 389 390 /* 391 * If the CPU has 46 or less physical address bits, then set an 392 * appropriate mask to guard against L1TF attacks. Otherwise, it is 393 * assumed that the CPU is not vulnerable to L1TF. 394 * 395 * Some Intel CPUs address the L1 cache using more PA bits than are 396 * reported by CPUID. Use the PA width of the L1 cache when possible 397 * to achieve more effective mitigation, e.g. if system RAM overlaps 398 * the most significant bits of legal physical address space. 399 */ 400 shadow_nonpresent_or_rsvd_mask = 0; 401 low_phys_bits = boot_cpu_data.x86_phys_bits; 402 if (boot_cpu_has_bug(X86_BUG_L1TF) && 403 !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >= 404 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) { 405 low_phys_bits = boot_cpu_data.x86_cache_bits 406 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 407 shadow_nonpresent_or_rsvd_mask = 408 rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1); 409 } 410 411 shadow_nonpresent_or_rsvd_lower_gfn_mask = 412 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); 413 414 shadow_user_mask = PT_USER_MASK; 415 shadow_accessed_mask = PT_ACCESSED_MASK; 416 shadow_dirty_mask = PT_DIRTY_MASK; 417 shadow_nx_mask = PT64_NX_MASK; 418 shadow_x_mask = 0; 419 shadow_present_mask = PT_PRESENT_MASK; 420 shadow_acc_track_mask = 0; 421 shadow_me_mask = sme_me_mask; 422 423 shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITABLE; 424 shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITABLE; 425 426 /* 427 * Set a reserved PA bit in MMIO SPTEs to generate page faults with 428 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT 429 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports 430 * 52-bit physical addresses then there are no reserved PA bits in the 431 * PTEs and so the reserved PA approach must be disabled. 432 */ 433 if (shadow_phys_bits < 52) 434 mask = BIT_ULL(51) | PT_PRESENT_MASK; 435 else 436 mask = 0; 437 438 kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); 439 } 440