15a9624afSPaolo Bonzini // SPDX-License-Identifier: GPL-2.0-only 25a9624afSPaolo Bonzini /* 35a9624afSPaolo Bonzini * Kernel-based Virtual Machine driver for Linux 45a9624afSPaolo Bonzini * 55a9624afSPaolo Bonzini * Macros and functions to access KVM PTEs (also known as SPTEs) 65a9624afSPaolo Bonzini * 75a9624afSPaolo Bonzini * Copyright (C) 2006 Qumranet, Inc. 85a9624afSPaolo Bonzini * Copyright 2020 Red Hat, Inc. and/or its affiliates. 95a9624afSPaolo Bonzini */ 105a9624afSPaolo Bonzini 115a9624afSPaolo Bonzini 125a9624afSPaolo Bonzini #include <linux/kvm_host.h> 135a9624afSPaolo Bonzini #include "mmu.h" 145a9624afSPaolo Bonzini #include "mmu_internal.h" 155a9624afSPaolo Bonzini #include "x86.h" 165a9624afSPaolo Bonzini #include "spte.h" 175a9624afSPaolo Bonzini 185a9624afSPaolo Bonzini #include <asm/e820/api.h> 194d5cff69SChristoph Hellwig #include <asm/memtype.h> 20e7b7bdeaSSean Christopherson #include <asm/vmx.h> 215a9624afSPaolo Bonzini 228b9e74bfSSean Christopherson bool __read_mostly enable_mmio_caching = true; 23c3e0c8c2SSean Christopherson static bool __ro_after_init allow_mmio_caching; 24b09763daSSean Christopherson module_param_named(mmio_caching, enable_mmio_caching, bool, 0444); 25*0c29397aSSean Christopherson EXPORT_SYMBOL_GPL(enable_mmio_caching); 26b09763daSSean Christopherson 275fc3424fSSean Christopherson u64 __read_mostly shadow_host_writable_mask; 285fc3424fSSean Christopherson u64 __read_mostly shadow_mmu_writable_mask; 295a9624afSPaolo Bonzini u64 __read_mostly shadow_nx_mask; 305a9624afSPaolo Bonzini u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ 315a9624afSPaolo Bonzini u64 __read_mostly shadow_user_mask; 325a9624afSPaolo Bonzini u64 __read_mostly shadow_accessed_mask; 335a9624afSPaolo Bonzini u64 __read_mostly shadow_dirty_mask; 345a9624afSPaolo Bonzini u64 __read_mostly shadow_mmio_value; 358120337aSSean Christopherson u64 __read_mostly shadow_mmio_mask; 365a9624afSPaolo Bonzini u64 __read_mostly shadow_mmio_access_mask; 375a9624afSPaolo Bonzini u64 __read_mostly shadow_present_mask; 3838bf9d7bSSean Christopherson u64 __read_mostly shadow_memtype_mask; 39e54f1ff2SKai Huang u64 __read_mostly shadow_me_value; 405a9624afSPaolo Bonzini u64 __read_mostly shadow_me_mask; 415a9624afSPaolo Bonzini u64 __read_mostly shadow_acc_track_mask; 425a9624afSPaolo Bonzini 435a9624afSPaolo Bonzini u64 __read_mostly shadow_nonpresent_or_rsvd_mask; 445a9624afSPaolo Bonzini u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; 455a9624afSPaolo Bonzini 465a9624afSPaolo Bonzini u8 __read_mostly shadow_phys_bits; 475a9624afSPaolo Bonzini 48c3e0c8c2SSean Christopherson void __init kvm_mmu_spte_module_init(void) 49c3e0c8c2SSean Christopherson { 50c3e0c8c2SSean Christopherson /* 51c3e0c8c2SSean Christopherson * Snapshot userspace's desire to allow MMIO caching. Whether or not 52c3e0c8c2SSean Christopherson * KVM can actually enable MMIO caching depends on vendor-specific 53c3e0c8c2SSean Christopherson * hardware capabilities and other module params that can't be resolved 54c3e0c8c2SSean Christopherson * until the vendor module is loaded, i.e. enable_mmio_caching can and 55c3e0c8c2SSean Christopherson * will change when the vendor module is (re)loaded. 56c3e0c8c2SSean Christopherson */ 57c3e0c8c2SSean Christopherson allow_mmio_caching = enable_mmio_caching; 58c3e0c8c2SSean Christopherson } 59c3e0c8c2SSean Christopherson 605a9624afSPaolo Bonzini static u64 generation_mmio_spte_mask(u64 gen) 615a9624afSPaolo Bonzini { 625a9624afSPaolo Bonzini u64 mask; 635a9624afSPaolo Bonzini 645a9624afSPaolo Bonzini WARN_ON(gen & ~MMIO_SPTE_GEN_MASK); 655a9624afSPaolo Bonzini 6634c0f6f2SMaciej S. Szmigiero mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK; 6734c0f6f2SMaciej S. Szmigiero mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK; 685a9624afSPaolo Bonzini return mask; 695a9624afSPaolo Bonzini } 705a9624afSPaolo Bonzini 715a9624afSPaolo Bonzini u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access) 725a9624afSPaolo Bonzini { 735a9624afSPaolo Bonzini u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; 74c236d962SSean Christopherson u64 spte = generation_mmio_spte_mask(gen); 755a9624afSPaolo Bonzini u64 gpa = gfn << PAGE_SHIFT; 765a9624afSPaolo Bonzini 7730ab5901SSean Christopherson WARN_ON_ONCE(!shadow_mmio_value); 7830ab5901SSean Christopherson 795a9624afSPaolo Bonzini access &= shadow_mmio_access_mask; 80c236d962SSean Christopherson spte |= shadow_mmio_value | access; 81c236d962SSean Christopherson spte |= gpa | shadow_nonpresent_or_rsvd_mask; 82c236d962SSean Christopherson spte |= (gpa & shadow_nonpresent_or_rsvd_mask) 838a967d65SPaolo Bonzini << SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 845a9624afSPaolo Bonzini 85c236d962SSean Christopherson return spte; 865a9624afSPaolo Bonzini } 875a9624afSPaolo Bonzini 885a9624afSPaolo Bonzini static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) 895a9624afSPaolo Bonzini { 905a9624afSPaolo Bonzini if (pfn_valid(pfn)) 915a9624afSPaolo Bonzini return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && 925a9624afSPaolo Bonzini /* 935a9624afSPaolo Bonzini * Some reserved pages, such as those from NVDIMM 945a9624afSPaolo Bonzini * DAX devices, are not for MMIO, and can be mapped 955a9624afSPaolo Bonzini * with cached memory type for better performance. 965a9624afSPaolo Bonzini * However, the above check misconceives those pages 975a9624afSPaolo Bonzini * as MMIO, and results in KVM mapping them with UC 985a9624afSPaolo Bonzini * memory type, which would hurt the performance. 995a9624afSPaolo Bonzini * Therefore, we check the host memory type in addition 1005a9624afSPaolo Bonzini * and only treat UC/UC-/WC pages as MMIO. 1015a9624afSPaolo Bonzini */ 1025a9624afSPaolo Bonzini (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); 1035a9624afSPaolo Bonzini 1045a9624afSPaolo Bonzini return !e820__mapped_raw_any(pfn_to_hpa(pfn), 1055a9624afSPaolo Bonzini pfn_to_hpa(pfn + 1) - 1, 1065a9624afSPaolo Bonzini E820_TYPE_RAM); 1075a9624afSPaolo Bonzini } 1085a9624afSPaolo Bonzini 10954eb3ef5SSean Christopherson /* 11054eb3ef5SSean Christopherson * Returns true if the SPTE has bits that may be set without holding mmu_lock. 11154eb3ef5SSean Christopherson * The caller is responsible for checking if the SPTE is shadow-present, and 11254eb3ef5SSean Christopherson * for determining whether or not the caller cares about non-leaf SPTEs. 11354eb3ef5SSean Christopherson */ 11454eb3ef5SSean Christopherson bool spte_has_volatile_bits(u64 spte) 11554eb3ef5SSean Christopherson { 11654eb3ef5SSean Christopherson /* 11754eb3ef5SSean Christopherson * Always atomically update spte if it can be updated 11854eb3ef5SSean Christopherson * out of mmu-lock, it can ensure dirty bit is not lost, 11954eb3ef5SSean Christopherson * also, it can help us to get a stable is_writable_pte() 12054eb3ef5SSean Christopherson * to ensure tlb flush is not missed. 12154eb3ef5SSean Christopherson */ 12254eb3ef5SSean Christopherson if (!is_writable_pte(spte) && is_mmu_writable_spte(spte)) 12354eb3ef5SSean Christopherson return true; 12454eb3ef5SSean Christopherson 12554eb3ef5SSean Christopherson if (is_access_track_spte(spte)) 12654eb3ef5SSean Christopherson return true; 12754eb3ef5SSean Christopherson 12854eb3ef5SSean Christopherson if (spte_ad_enabled(spte)) { 12954eb3ef5SSean Christopherson if (!(spte & shadow_accessed_mask) || 13054eb3ef5SSean Christopherson (is_writable_pte(spte) && !(spte & shadow_dirty_mask))) 13154eb3ef5SSean Christopherson return true; 13254eb3ef5SSean Christopherson } 13354eb3ef5SSean Christopherson 13454eb3ef5SSean Christopherson return false; 13554eb3ef5SSean Christopherson } 13654eb3ef5SSean Christopherson 1377158bee4SPaolo Bonzini bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, 1388283e36aSBen Gardon const struct kvm_memory_slot *slot, 1397158bee4SPaolo Bonzini unsigned int pte_access, gfn_t gfn, kvm_pfn_t pfn, 1402839180cSPaolo Bonzini u64 old_spte, bool prefetch, bool can_unsync, 1417158bee4SPaolo Bonzini bool host_writable, u64 *new_spte) 1425a9624afSPaolo Bonzini { 1437158bee4SPaolo Bonzini int level = sp->role.level; 144edea7c4fSSean Christopherson u64 spte = SPTE_MMU_PRESENT_MASK; 145ad67e480SPaolo Bonzini bool wrprot = false; 1465a9624afSPaolo Bonzini 1479fb35657SSean Christopherson WARN_ON_ONCE(!pte_access && !shadow_present_mask); 1489fb35657SSean Christopherson 1497158bee4SPaolo Bonzini if (sp->role.ad_disabled) 1508a406c89SSean Christopherson spte |= SPTE_TDP_AD_DISABLED_MASK; 151ce92ef76SSean Christopherson else if (kvm_mmu_page_ad_need_write_protect(sp)) 1528a406c89SSean Christopherson spte |= SPTE_TDP_AD_WRPROT_ONLY_MASK; 1538a406c89SSean Christopherson 1548a406c89SSean Christopherson /* 1555a9624afSPaolo Bonzini * For the EPT case, shadow_present_mask is 0 if hardware 1565a9624afSPaolo Bonzini * supports exec-only page table entries. In that case, 1575a9624afSPaolo Bonzini * ACC_USER_MASK and shadow_user_mask are used to represent 1585a9624afSPaolo Bonzini * read access. See FNAME(gpte_access) in paging_tmpl.h. 1595a9624afSPaolo Bonzini */ 1605a9624afSPaolo Bonzini spte |= shadow_present_mask; 1612839180cSPaolo Bonzini if (!prefetch) 1625a9624afSPaolo Bonzini spte |= spte_shadow_accessed_mask(spte); 1635a9624afSPaolo Bonzini 1645a9624afSPaolo Bonzini if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) && 165084cc29fSBen Gardon is_nx_huge_page_enabled(vcpu->kvm)) { 1665a9624afSPaolo Bonzini pte_access &= ~ACC_EXEC_MASK; 1675a9624afSPaolo Bonzini } 1685a9624afSPaolo Bonzini 1695a9624afSPaolo Bonzini if (pte_access & ACC_EXEC_MASK) 1705a9624afSPaolo Bonzini spte |= shadow_x_mask; 1715a9624afSPaolo Bonzini else 1725a9624afSPaolo Bonzini spte |= shadow_nx_mask; 1735a9624afSPaolo Bonzini 1745a9624afSPaolo Bonzini if (pte_access & ACC_USER_MASK) 1755a9624afSPaolo Bonzini spte |= shadow_user_mask; 1765a9624afSPaolo Bonzini 1775a9624afSPaolo Bonzini if (level > PG_LEVEL_4K) 1785a9624afSPaolo Bonzini spte |= PT_PAGE_SIZE_MASK; 17938bf9d7bSSean Christopherson 18038bf9d7bSSean Christopherson if (shadow_memtype_mask) 181b3646477SJason Baron spte |= static_call(kvm_x86_get_mt_mask)(vcpu, gfn, 1825a9624afSPaolo Bonzini kvm_is_mmio_pfn(pfn)); 1835a9624afSPaolo Bonzini if (host_writable) 1845fc3424fSSean Christopherson spte |= shadow_host_writable_mask; 1855a9624afSPaolo Bonzini else 1865a9624afSPaolo Bonzini pte_access &= ~ACC_WRITE_MASK; 1875a9624afSPaolo Bonzini 188e54f1ff2SKai Huang if (shadow_me_value && !kvm_is_mmio_pfn(pfn)) 189e54f1ff2SKai Huang spte |= shadow_me_value; 1905a9624afSPaolo Bonzini 1915a9624afSPaolo Bonzini spte |= (u64)pfn << PAGE_SHIFT; 1925a9624afSPaolo Bonzini 1935a9624afSPaolo Bonzini if (pte_access & ACC_WRITE_MASK) { 1945fc3424fSSean Christopherson spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask; 1955a9624afSPaolo Bonzini 1965a9624afSPaolo Bonzini /* 1975a9624afSPaolo Bonzini * Optimization: for pte sync, if spte was writable the hash 1985a9624afSPaolo Bonzini * lookup is unnecessary (and expensive). Write protection 1990337f585SSean Christopherson * is responsibility of kvm_mmu_get_page / kvm_mmu_sync_roots. 2005a9624afSPaolo Bonzini * Same reasoning can be applied to dirty page accounting. 2015a9624afSPaolo Bonzini */ 2028b8f9d75SLai Jiangshan if (is_writable_pte(old_spte)) 2035a9624afSPaolo Bonzini goto out; 2045a9624afSPaolo Bonzini 2050337f585SSean Christopherson /* 2060337f585SSean Christopherson * Unsync shadow pages that are reachable by the new, writable 2070337f585SSean Christopherson * SPTE. Write-protect the SPTE if the page can't be unsync'd, 2080337f585SSean Christopherson * e.g. it's write-tracked (upper-level SPs) or has one or more 2090337f585SSean Christopherson * shadow pages and unsync'ing pages is not allowed. 2100337f585SSean Christopherson */ 2114d78d0b3SBen Gardon if (mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, can_unsync, prefetch)) { 2125a9624afSPaolo Bonzini pgprintk("%s: found shadow page for %llx, marking ro\n", 2135a9624afSPaolo Bonzini __func__, gfn); 214ad67e480SPaolo Bonzini wrprot = true; 2155a9624afSPaolo Bonzini pte_access &= ~ACC_WRITE_MASK; 2165fc3424fSSean Christopherson spte &= ~(PT_WRITABLE_MASK | shadow_mmu_writable_mask); 2175a9624afSPaolo Bonzini } 2185a9624afSPaolo Bonzini } 2195a9624afSPaolo Bonzini 2205a9624afSPaolo Bonzini if (pte_access & ACC_WRITE_MASK) 2215a9624afSPaolo Bonzini spte |= spte_shadow_dirty_mask(spte); 2225a9624afSPaolo Bonzini 2238b8f9d75SLai Jiangshan out: 2242839180cSPaolo Bonzini if (prefetch) 2255a9624afSPaolo Bonzini spte = mark_spte_for_access_track(spte); 2265a9624afSPaolo Bonzini 2273b77daa5SSean Christopherson WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level), 2283b77daa5SSean Christopherson "spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level, 2293b77daa5SSean Christopherson get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level)); 2303b77daa5SSean Christopherson 23153597858SDavid Matlack if ((spte & PT_WRITABLE_MASK) && kvm_slot_dirty_track_enabled(slot)) { 23253597858SDavid Matlack /* Enforced by kvm_mmu_hugepage_adjust. */ 23353597858SDavid Matlack WARN_ON(level > PG_LEVEL_4K); 23453597858SDavid Matlack mark_page_dirty_in_slot(vcpu->kvm, slot, gfn); 23553597858SDavid Matlack } 236bcc4f2bcSPaolo Bonzini 2375a9624afSPaolo Bonzini *new_spte = spte; 238ad67e480SPaolo Bonzini return wrprot; 2395a9624afSPaolo Bonzini } 2405a9624afSPaolo Bonzini 241a3fe5dbdSDavid Matlack static u64 make_spte_executable(u64 spte) 242a3fe5dbdSDavid Matlack { 243a3fe5dbdSDavid Matlack bool is_access_track = is_access_track_spte(spte); 244a3fe5dbdSDavid Matlack 245a3fe5dbdSDavid Matlack if (is_access_track) 246a3fe5dbdSDavid Matlack spte = restore_acc_track_spte(spte); 247a3fe5dbdSDavid Matlack 248a3fe5dbdSDavid Matlack spte &= ~shadow_nx_mask; 249a3fe5dbdSDavid Matlack spte |= shadow_x_mask; 250a3fe5dbdSDavid Matlack 251a3fe5dbdSDavid Matlack if (is_access_track) 252a3fe5dbdSDavid Matlack spte = mark_spte_for_access_track(spte); 253a3fe5dbdSDavid Matlack 254a3fe5dbdSDavid Matlack return spte; 255a3fe5dbdSDavid Matlack } 256a3fe5dbdSDavid Matlack 257a3fe5dbdSDavid Matlack /* 258a3fe5dbdSDavid Matlack * Construct an SPTE that maps a sub-page of the given huge page SPTE where 259a3fe5dbdSDavid Matlack * `index` identifies which sub-page. 260a3fe5dbdSDavid Matlack * 261a3fe5dbdSDavid Matlack * This is used during huge page splitting to build the SPTEs that make up the 262a3fe5dbdSDavid Matlack * new page table. 263a3fe5dbdSDavid Matlack */ 26447855da0SDavid Matlack u64 make_huge_page_split_spte(struct kvm *kvm, u64 huge_spte, union kvm_mmu_page_role role, 265084cc29fSBen Gardon int index) 266a3fe5dbdSDavid Matlack { 267a3fe5dbdSDavid Matlack u64 child_spte; 268a3fe5dbdSDavid Matlack 269a3fe5dbdSDavid Matlack if (WARN_ON_ONCE(!is_shadow_present_pte(huge_spte))) 270a3fe5dbdSDavid Matlack return 0; 271a3fe5dbdSDavid Matlack 272a3fe5dbdSDavid Matlack if (WARN_ON_ONCE(!is_large_pte(huge_spte))) 273a3fe5dbdSDavid Matlack return 0; 274a3fe5dbdSDavid Matlack 275a3fe5dbdSDavid Matlack child_spte = huge_spte; 276a3fe5dbdSDavid Matlack 277a3fe5dbdSDavid Matlack /* 278a3fe5dbdSDavid Matlack * The child_spte already has the base address of the huge page being 279a3fe5dbdSDavid Matlack * split. So we just have to OR in the offset to the page at the next 280a3fe5dbdSDavid Matlack * lower level for the given index. 281a3fe5dbdSDavid Matlack */ 28247855da0SDavid Matlack child_spte |= (index * KVM_PAGES_PER_HPAGE(role.level)) << PAGE_SHIFT; 283a3fe5dbdSDavid Matlack 28447855da0SDavid Matlack if (role.level == PG_LEVEL_4K) { 285a3fe5dbdSDavid Matlack child_spte &= ~PT_PAGE_SIZE_MASK; 286a3fe5dbdSDavid Matlack 287a3fe5dbdSDavid Matlack /* 28847855da0SDavid Matlack * When splitting to a 4K page where execution is allowed, mark 28947855da0SDavid Matlack * the page executable as the NX hugepage mitigation no longer 29047855da0SDavid Matlack * applies. 291a3fe5dbdSDavid Matlack */ 29247855da0SDavid Matlack if ((role.access & ACC_EXEC_MASK) && is_nx_huge_page_enabled(kvm)) 293a3fe5dbdSDavid Matlack child_spte = make_spte_executable(child_spte); 294a3fe5dbdSDavid Matlack } 295a3fe5dbdSDavid Matlack 296a3fe5dbdSDavid Matlack return child_spte; 297a3fe5dbdSDavid Matlack } 298a3fe5dbdSDavid Matlack 299a3fe5dbdSDavid Matlack 3005a9624afSPaolo Bonzini u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled) 3015a9624afSPaolo Bonzini { 302edea7c4fSSean Christopherson u64 spte = SPTE_MMU_PRESENT_MASK; 3035a9624afSPaolo Bonzini 304edea7c4fSSean Christopherson spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK | 305e54f1ff2SKai Huang shadow_user_mask | shadow_x_mask | shadow_me_value; 3065a9624afSPaolo Bonzini 3075a9624afSPaolo Bonzini if (ad_disabled) 3088a406c89SSean Christopherson spte |= SPTE_TDP_AD_DISABLED_MASK; 3095a9624afSPaolo Bonzini else 3105a9624afSPaolo Bonzini spte |= shadow_accessed_mask; 3115a9624afSPaolo Bonzini 3125a9624afSPaolo Bonzini return spte; 3135a9624afSPaolo Bonzini } 3145a9624afSPaolo Bonzini 3155a9624afSPaolo Bonzini u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn) 3165a9624afSPaolo Bonzini { 3175a9624afSPaolo Bonzini u64 new_spte; 3185a9624afSPaolo Bonzini 3192ca3129eSSean Christopherson new_spte = old_spte & ~SPTE_BASE_ADDR_MASK; 3205a9624afSPaolo Bonzini new_spte |= (u64)new_pfn << PAGE_SHIFT; 3215a9624afSPaolo Bonzini 3225a9624afSPaolo Bonzini new_spte &= ~PT_WRITABLE_MASK; 3235fc3424fSSean Christopherson new_spte &= ~shadow_host_writable_mask; 324f082d86eSDavid Matlack new_spte &= ~shadow_mmu_writable_mask; 3255a9624afSPaolo Bonzini 3265a9624afSPaolo Bonzini new_spte = mark_spte_for_access_track(new_spte); 3275a9624afSPaolo Bonzini 3285a9624afSPaolo Bonzini return new_spte; 3295a9624afSPaolo Bonzini } 3305a9624afSPaolo Bonzini 3315a9624afSPaolo Bonzini u64 mark_spte_for_access_track(u64 spte) 3325a9624afSPaolo Bonzini { 3335a9624afSPaolo Bonzini if (spte_ad_enabled(spte)) 3345a9624afSPaolo Bonzini return spte & ~shadow_accessed_mask; 3355a9624afSPaolo Bonzini 3365a9624afSPaolo Bonzini if (is_access_track_spte(spte)) 3375a9624afSPaolo Bonzini return spte; 3385a9624afSPaolo Bonzini 339115111efSDavid Matlack check_spte_writable_invariants(spte); 3405a9624afSPaolo Bonzini 3418a967d65SPaolo Bonzini WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK << 3428a967d65SPaolo Bonzini SHADOW_ACC_TRACK_SAVED_BITS_SHIFT), 3435a9624afSPaolo Bonzini "kvm: Access Tracking saved bit locations are not zero\n"); 3445a9624afSPaolo Bonzini 3458a967d65SPaolo Bonzini spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) << 3468a967d65SPaolo Bonzini SHADOW_ACC_TRACK_SAVED_BITS_SHIFT; 3475a9624afSPaolo Bonzini spte &= ~shadow_acc_track_mask; 3485a9624afSPaolo Bonzini 3495a9624afSPaolo Bonzini return spte; 3505a9624afSPaolo Bonzini } 3515a9624afSPaolo Bonzini 3528120337aSSean Christopherson void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask) 3535a9624afSPaolo Bonzini { 3545a9624afSPaolo Bonzini BUG_ON((u64)(unsigned)access_mask != access_mask); 3555a9624afSPaolo Bonzini WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask); 35644aaa015SSean Christopherson 357c3e0c8c2SSean Christopherson /* 358c3e0c8c2SSean Christopherson * Reset to the original module param value to honor userspace's desire 359c3e0c8c2SSean Christopherson * to (dis)allow MMIO caching. Update the param itself so that 360c3e0c8c2SSean Christopherson * userspace can see whether or not KVM is actually using MMIO caching. 361c3e0c8c2SSean Christopherson */ 362c3e0c8c2SSean Christopherson enable_mmio_caching = allow_mmio_caching; 363b09763daSSean Christopherson if (!enable_mmio_caching) 364b09763daSSean Christopherson mmio_value = 0; 365b09763daSSean Christopherson 36644aaa015SSean Christopherson /* 36744aaa015SSean Christopherson * Disable MMIO caching if the MMIO value collides with the bits that 36844aaa015SSean Christopherson * are used to hold the relocated GFN when the L1TF mitigation is 36944aaa015SSean Christopherson * enabled. This should never fire as there is no known hardware that 37044aaa015SSean Christopherson * can trigger this condition, e.g. SME/SEV CPUs that require a custom 37144aaa015SSean Christopherson * MMIO value are not susceptible to L1TF. 37244aaa015SSean Christopherson */ 37344aaa015SSean Christopherson if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask << 37444aaa015SSean Christopherson SHADOW_NONPRESENT_OR_RSVD_MASK_LEN))) 37544aaa015SSean Christopherson mmio_value = 0; 37644aaa015SSean Christopherson 377715f1079SSean Christopherson /* 378715f1079SSean Christopherson * The masked MMIO value must obviously match itself and a removed SPTE 379715f1079SSean Christopherson * must not get a false positive. Removed SPTEs and MMIO SPTEs should 380715f1079SSean Christopherson * never collide as MMIO must set some RWX bits, and removed SPTEs must 381715f1079SSean Christopherson * not set any RWX bits. 382715f1079SSean Christopherson */ 383715f1079SSean Christopherson if (WARN_ON((mmio_value & mmio_mask) != mmio_value) || 384715f1079SSean Christopherson WARN_ON(mmio_value && (REMOVED_SPTE & mmio_mask) == mmio_value)) 385715f1079SSean Christopherson mmio_value = 0; 386715f1079SSean Christopherson 3878b9e74bfSSean Christopherson if (!mmio_value) 3888b9e74bfSSean Christopherson enable_mmio_caching = false; 3898b9e74bfSSean Christopherson 3908120337aSSean Christopherson shadow_mmio_value = mmio_value; 3918120337aSSean Christopherson shadow_mmio_mask = mmio_mask; 3925a9624afSPaolo Bonzini shadow_mmio_access_mask = access_mask; 3935a9624afSPaolo Bonzini } 3945a9624afSPaolo Bonzini EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); 3955a9624afSPaolo Bonzini 396e54f1ff2SKai Huang void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask) 397e54f1ff2SKai Huang { 398e54f1ff2SKai Huang /* shadow_me_value must be a subset of shadow_me_mask */ 399e54f1ff2SKai Huang if (WARN_ON(me_value & ~me_mask)) 400e54f1ff2SKai Huang me_value = me_mask = 0; 401e54f1ff2SKai Huang 402e54f1ff2SKai Huang shadow_me_value = me_value; 403e54f1ff2SKai Huang shadow_me_mask = me_mask; 404e54f1ff2SKai Huang } 405e54f1ff2SKai Huang EXPORT_SYMBOL_GPL(kvm_mmu_set_me_spte_mask); 406e54f1ff2SKai Huang 407e7b7bdeaSSean Christopherson void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only) 4085a9624afSPaolo Bonzini { 409e7b7bdeaSSean Christopherson shadow_user_mask = VMX_EPT_READABLE_MASK; 410e7b7bdeaSSean Christopherson shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull; 411e7b7bdeaSSean Christopherson shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull; 412e7b7bdeaSSean Christopherson shadow_nx_mask = 0ull; 413e7b7bdeaSSean Christopherson shadow_x_mask = VMX_EPT_EXECUTABLE_MASK; 414e7b7bdeaSSean Christopherson shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK; 41538bf9d7bSSean Christopherson /* 41638bf9d7bSSean Christopherson * EPT overrides the host MTRRs, and so KVM must program the desired 41738bf9d7bSSean Christopherson * memtype directly into the SPTEs. Note, this mask is just the mask 41838bf9d7bSSean Christopherson * of all bits that factor into the memtype, the actual memtype must be 41938bf9d7bSSean Christopherson * dynamically calculated, e.g. to ensure host MMIO is mapped UC. 42038bf9d7bSSean Christopherson */ 42138bf9d7bSSean Christopherson shadow_memtype_mask = VMX_EPT_MT_MASK | VMX_EPT_IPAT_BIT; 422e7b7bdeaSSean Christopherson shadow_acc_track_mask = VMX_EPT_RWX_MASK; 423613a3f37SSean Christopherson shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE; 424613a3f37SSean Christopherson shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE; 425613a3f37SSean Christopherson 426e7b7bdeaSSean Christopherson /* 427e7b7bdeaSSean Christopherson * EPT Misconfigurations are generated if the value of bits 2:0 428e7b7bdeaSSean Christopherson * of an EPT paging-structure entry is 110b (write/execute). 429e7b7bdeaSSean Christopherson */ 430e7b7bdeaSSean Christopherson kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE, 431e7b7bdeaSSean Christopherson VMX_EPT_RWX_MASK, 0); 4325a9624afSPaolo Bonzini } 433e7b7bdeaSSean Christopherson EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks); 4345a9624afSPaolo Bonzini 4355a9624afSPaolo Bonzini void kvm_mmu_reset_all_pte_masks(void) 4365a9624afSPaolo Bonzini { 4375a9624afSPaolo Bonzini u8 low_phys_bits; 438d6b87f25SSean Christopherson u64 mask; 4395a9624afSPaolo Bonzini 4405a9624afSPaolo Bonzini shadow_phys_bits = kvm_get_shadow_phys_bits(); 4415a9624afSPaolo Bonzini 4425a9624afSPaolo Bonzini /* 4435a9624afSPaolo Bonzini * If the CPU has 46 or less physical address bits, then set an 4445a9624afSPaolo Bonzini * appropriate mask to guard against L1TF attacks. Otherwise, it is 4455a9624afSPaolo Bonzini * assumed that the CPU is not vulnerable to L1TF. 4465a9624afSPaolo Bonzini * 4475a9624afSPaolo Bonzini * Some Intel CPUs address the L1 cache using more PA bits than are 4485a9624afSPaolo Bonzini * reported by CPUID. Use the PA width of the L1 cache when possible 4495a9624afSPaolo Bonzini * to achieve more effective mitigation, e.g. if system RAM overlaps 4505a9624afSPaolo Bonzini * the most significant bits of legal physical address space. 4515a9624afSPaolo Bonzini */ 4525a9624afSPaolo Bonzini shadow_nonpresent_or_rsvd_mask = 0; 4535a9624afSPaolo Bonzini low_phys_bits = boot_cpu_data.x86_phys_bits; 4545a9624afSPaolo Bonzini if (boot_cpu_has_bug(X86_BUG_L1TF) && 4555a9624afSPaolo Bonzini !WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >= 4568a967d65SPaolo Bonzini 52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) { 4575a9624afSPaolo Bonzini low_phys_bits = boot_cpu_data.x86_cache_bits 4588a967d65SPaolo Bonzini - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN; 4595a9624afSPaolo Bonzini shadow_nonpresent_or_rsvd_mask = 4605a9624afSPaolo Bonzini rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1); 4615a9624afSPaolo Bonzini } 4625a9624afSPaolo Bonzini 4635a9624afSPaolo Bonzini shadow_nonpresent_or_rsvd_lower_gfn_mask = 4645a9624afSPaolo Bonzini GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); 465d6b87f25SSean Christopherson 466e7b7bdeaSSean Christopherson shadow_user_mask = PT_USER_MASK; 467e7b7bdeaSSean Christopherson shadow_accessed_mask = PT_ACCESSED_MASK; 468e7b7bdeaSSean Christopherson shadow_dirty_mask = PT_DIRTY_MASK; 469e7b7bdeaSSean Christopherson shadow_nx_mask = PT64_NX_MASK; 470e7b7bdeaSSean Christopherson shadow_x_mask = 0; 471e7b7bdeaSSean Christopherson shadow_present_mask = PT_PRESENT_MASK; 47238bf9d7bSSean Christopherson 47338bf9d7bSSean Christopherson /* 47438bf9d7bSSean Christopherson * For shadow paging and NPT, KVM uses PAT entry '0' to encode WB 47538bf9d7bSSean Christopherson * memtype in the SPTEs, i.e. relies on host MTRRs to provide the 47638bf9d7bSSean Christopherson * correct memtype (WB is the "weakest" memtype). 47738bf9d7bSSean Christopherson */ 47838bf9d7bSSean Christopherson shadow_memtype_mask = 0; 479e7b7bdeaSSean Christopherson shadow_acc_track_mask = 0; 480e54f1ff2SKai Huang shadow_me_mask = 0; 481e54f1ff2SKai Huang shadow_me_value = 0; 482e7b7bdeaSSean Christopherson 4831ca87e01SDavid Matlack shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITABLE; 4841ca87e01SDavid Matlack shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITABLE; 4855fc3424fSSean Christopherson 486d6b87f25SSean Christopherson /* 487d6b87f25SSean Christopherson * Set a reserved PA bit in MMIO SPTEs to generate page faults with 488d6b87f25SSean Christopherson * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT 489d6b87f25SSean Christopherson * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports 490d6b87f25SSean Christopherson * 52-bit physical addresses then there are no reserved PA bits in the 491d6b87f25SSean Christopherson * PTEs and so the reserved PA approach must be disabled. 492d6b87f25SSean Christopherson */ 493d6b87f25SSean Christopherson if (shadow_phys_bits < 52) 494d6b87f25SSean Christopherson mask = BIT_ULL(51) | PT_PRESENT_MASK; 495d6b87f25SSean Christopherson else 496d6b87f25SSean Christopherson mask = 0; 497d6b87f25SSean Christopherson 498d6b87f25SSean Christopherson kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); 4995a9624afSPaolo Bonzini } 500