1 #ifndef __KVM_X86_MMU_H 2 #define __KVM_X86_MMU_H 3 4 #include <linux/kvm_host.h> 5 #include "kvm_cache_regs.h" 6 7 #define PT64_PT_BITS 9 8 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS) 9 #define PT32_PT_BITS 10 10 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS) 11 12 #define PT_WRITABLE_SHIFT 1 13 14 #define PT_PRESENT_MASK (1ULL << 0) 15 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT) 16 #define PT_USER_MASK (1ULL << 2) 17 #define PT_PWT_MASK (1ULL << 3) 18 #define PT_PCD_MASK (1ULL << 4) 19 #define PT_ACCESSED_SHIFT 5 20 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT) 21 #define PT_DIRTY_SHIFT 6 22 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT) 23 #define PT_PAGE_SIZE_SHIFT 7 24 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT) 25 #define PT_PAT_MASK (1ULL << 7) 26 #define PT_GLOBAL_MASK (1ULL << 8) 27 #define PT64_NX_SHIFT 63 28 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT) 29 30 #define PT_PAT_SHIFT 7 31 #define PT_DIR_PAT_SHIFT 12 32 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT) 33 34 #define PT32_DIR_PSE36_SIZE 4 35 #define PT32_DIR_PSE36_SHIFT 13 36 #define PT32_DIR_PSE36_MASK \ 37 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT) 38 39 #define PT64_ROOT_LEVEL 4 40 #define PT32_ROOT_LEVEL 2 41 #define PT32E_ROOT_LEVEL 3 42 43 #define PT_PDPE_LEVEL 3 44 #define PT_DIRECTORY_LEVEL 2 45 #define PT_PAGE_TABLE_LEVEL 1 46 47 #define PFERR_PRESENT_BIT 0 48 #define PFERR_WRITE_BIT 1 49 #define PFERR_USER_BIT 2 50 #define PFERR_RSVD_BIT 3 51 #define PFERR_FETCH_BIT 4 52 53 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) 54 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) 55 #define PFERR_USER_MASK (1U << PFERR_USER_BIT) 56 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) 57 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) 58 59 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]); 60 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask); 61 62 /* 63 * Return values of handle_mmio_page_fault_common: 64 * RET_MMIO_PF_EMULATE: it is a real mmio page fault, emulate the instruction 65 * directly. 66 * RET_MMIO_PF_INVALID: invalid spte is detected then let the real page 67 * fault path update the mmio spte. 68 * RET_MMIO_PF_RETRY: let CPU fault again on the address. 69 * RET_MMIO_PF_BUG: bug is detected. 70 */ 71 enum { 72 RET_MMIO_PF_EMULATE = 1, 73 RET_MMIO_PF_INVALID = 2, 74 RET_MMIO_PF_RETRY = 0, 75 RET_MMIO_PF_BUG = -1 76 }; 77 78 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct); 79 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context); 80 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context, 81 bool execonly); 82 void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 83 bool ept); 84 85 static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm) 86 { 87 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages) 88 return kvm->arch.n_max_mmu_pages - 89 kvm->arch.n_used_mmu_pages; 90 91 return 0; 92 } 93 94 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu) 95 { 96 if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE)) 97 return 0; 98 99 return kvm_mmu_load(vcpu); 100 } 101 102 static inline int is_present_gpte(unsigned long pte) 103 { 104 return pte & PT_PRESENT_MASK; 105 } 106 107 /* 108 * Currently, we have two sorts of write-protection, a) the first one 109 * write-protects guest page to sync the guest modification, b) another one is 110 * used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences 111 * between these two sorts are: 112 * 1) the first case clears SPTE_MMU_WRITEABLE bit. 113 * 2) the first case requires flushing tlb immediately avoiding corrupting 114 * shadow page table between all vcpus so it should be in the protection of 115 * mmu-lock. And the another case does not need to flush tlb until returning 116 * the dirty bitmap to userspace since it only write-protects the page 117 * logged in the bitmap, that means the page in the dirty bitmap is not 118 * missed, so it can flush tlb out of mmu-lock. 119 * 120 * So, there is the problem: the first case can meet the corrupted tlb caused 121 * by another case which write-protects pages but without flush tlb 122 * immediately. In order to making the first case be aware this problem we let 123 * it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit 124 * is set, it works since another case never touches SPTE_MMU_WRITEABLE bit. 125 * 126 * Anyway, whenever a spte is updated (only permission and status bits are 127 * changed) we need to check whether the spte with SPTE_MMU_WRITEABLE becomes 128 * readonly, if that happens, we need to flush tlb. Fortunately, 129 * mmu_spte_update() has already handled it perfectly. 130 * 131 * The rules to use SPTE_MMU_WRITEABLE and PT_WRITABLE_MASK: 132 * - if we want to see if it has writable tlb entry or if the spte can be 133 * writable on the mmu mapping, check SPTE_MMU_WRITEABLE, this is the most 134 * case, otherwise 135 * - if we fix page fault on the spte or do write-protection by dirty logging, 136 * check PT_WRITABLE_MASK. 137 * 138 * TODO: introduce APIs to split these two cases. 139 */ 140 static inline int is_writable_pte(unsigned long pte) 141 { 142 return pte & PT_WRITABLE_MASK; 143 } 144 145 static inline bool is_write_protection(struct kvm_vcpu *vcpu) 146 { 147 return kvm_read_cr0_bits(vcpu, X86_CR0_WP); 148 } 149 150 /* 151 * Will a fault with a given page-fault error code (pfec) cause a permission 152 * fault with the given access (in ACC_* format)? 153 */ 154 static inline bool permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 155 unsigned pte_access, unsigned pfec) 156 { 157 int cpl = kvm_x86_ops->get_cpl(vcpu); 158 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 159 160 /* 161 * If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1. 162 * 163 * If CPL = 3, SMAP applies to all supervisor-mode data accesses 164 * (these are implicit supervisor accesses) regardless of the value 165 * of EFLAGS.AC. 166 * 167 * This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving 168 * the result in X86_EFLAGS_AC. We then insert it in place of 169 * the PFERR_RSVD_MASK bit; this bit will always be zero in pfec, 170 * but it will be one in index if SMAP checks are being overridden. 171 * It is important to keep this branchless. 172 */ 173 unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC); 174 int index = (pfec >> 1) + 175 (smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1)); 176 177 return (mmu->permissions[index] >> pte_access) & 1; 178 } 179 180 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm); 181 #endif 182