1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_MMU_H 3 #define __KVM_X86_MMU_H 4 5 #include <linux/kvm_host.h> 6 #include "kvm_cache_regs.h" 7 #include "cpuid.h" 8 9 #define PT64_PT_BITS 9 10 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS) 11 #define PT32_PT_BITS 10 12 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS) 13 14 #define PT_WRITABLE_SHIFT 1 15 #define PT_USER_SHIFT 2 16 17 #define PT_PRESENT_MASK (1ULL << 0) 18 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT) 19 #define PT_USER_MASK (1ULL << PT_USER_SHIFT) 20 #define PT_PWT_MASK (1ULL << 3) 21 #define PT_PCD_MASK (1ULL << 4) 22 #define PT_ACCESSED_SHIFT 5 23 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT) 24 #define PT_DIRTY_SHIFT 6 25 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT) 26 #define PT_PAGE_SIZE_SHIFT 7 27 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT) 28 #define PT_PAT_MASK (1ULL << 7) 29 #define PT_GLOBAL_MASK (1ULL << 8) 30 #define PT64_NX_SHIFT 63 31 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT) 32 33 #define PT_PAT_SHIFT 7 34 #define PT_DIR_PAT_SHIFT 12 35 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT) 36 37 #define PT32_DIR_PSE36_SIZE 4 38 #define PT32_DIR_PSE36_SHIFT 13 39 #define PT32_DIR_PSE36_MASK \ 40 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT) 41 42 #define PT64_ROOT_5LEVEL 5 43 #define PT64_ROOT_4LEVEL 4 44 #define PT32_ROOT_LEVEL 2 45 #define PT32E_ROOT_LEVEL 3 46 47 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \ 48 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE) 49 50 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP) 51 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX) 52 53 static __always_inline u64 rsvd_bits(int s, int e) 54 { 55 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s); 56 57 if (__builtin_constant_p(e)) 58 BUILD_BUG_ON(e > 63); 59 else 60 e &= 63; 61 62 if (e < s) 63 return 0; 64 65 return ((2ULL << (e - s)) - 1) << s; 66 } 67 68 /* 69 * The number of non-reserved physical address bits irrespective of features 70 * that repurpose legal bits, e.g. MKTME. 71 */ 72 extern u8 __read_mostly shadow_phys_bits; 73 74 static inline gfn_t kvm_mmu_max_gfn(void) 75 { 76 /* 77 * Note that this uses the host MAXPHYADDR, not the guest's. 78 * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR; 79 * assuming KVM is running on bare metal, guest accesses beyond 80 * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit 81 * (either EPT Violation/Misconfig or #NPF), and so KVM will never 82 * install a SPTE for such addresses. If KVM is running as a VM 83 * itself, on the other hand, it might see a MAXPHYADDR that is less 84 * than hardware's real MAXPHYADDR. Using the host MAXPHYADDR 85 * disallows such SPTEs entirely and simplifies the TDP MMU. 86 */ 87 int max_gpa_bits = likely(tdp_enabled) ? shadow_phys_bits : 52; 88 89 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1; 90 } 91 92 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask); 93 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only); 94 95 void kvm_init_mmu(struct kvm_vcpu *vcpu); 96 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0, 97 unsigned long cr4, u64 efer, gpa_t nested_cr3); 98 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, 99 int huge_page_level, bool accessed_dirty, 100 gpa_t new_eptp); 101 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu); 102 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, 103 u64 fault_address, char *insn, int insn_len); 104 105 int kvm_mmu_load(struct kvm_vcpu *vcpu); 106 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 107 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu); 108 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 109 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu); 110 111 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu) 112 { 113 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE)) 114 return 0; 115 116 return kvm_mmu_load(vcpu); 117 } 118 119 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3) 120 { 121 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0); 122 123 return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE) 124 ? cr3 & X86_CR3_PCID_MASK 125 : 0; 126 } 127 128 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu) 129 { 130 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu)); 131 } 132 133 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) 134 { 135 u64 root_hpa = vcpu->arch.mmu->root.hpa; 136 137 if (!VALID_PAGE(root_hpa)) 138 return; 139 140 static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa, 141 vcpu->arch.mmu->shadow_root_level); 142 } 143 144 struct kvm_page_fault { 145 /* arguments to kvm_mmu_do_page_fault. */ 146 const gpa_t addr; 147 const u32 error_code; 148 const bool prefetch; 149 150 /* Derived from error_code. */ 151 const bool exec; 152 const bool write; 153 const bool present; 154 const bool rsvd; 155 const bool user; 156 157 /* Derived from mmu and global state. */ 158 const bool is_tdp; 159 const bool nx_huge_page_workaround_enabled; 160 161 /* 162 * Whether a >4KB mapping can be created or is forbidden due to NX 163 * hugepages. 164 */ 165 bool huge_page_disallowed; 166 167 /* 168 * Maximum page size that can be created for this fault; input to 169 * FNAME(fetch), __direct_map and kvm_tdp_mmu_map. 170 */ 171 u8 max_level; 172 173 /* 174 * Page size that can be created based on the max_level and the 175 * page size used by the host mapping. 176 */ 177 u8 req_level; 178 179 /* 180 * Page size that will be created based on the req_level and 181 * huge_page_disallowed. 182 */ 183 u8 goal_level; 184 185 /* Shifted addr, or result of guest page table walk if addr is a gva. */ 186 gfn_t gfn; 187 188 /* The memslot containing gfn. May be NULL. */ 189 struct kvm_memory_slot *slot; 190 191 /* Outputs of kvm_faultin_pfn. */ 192 kvm_pfn_t pfn; 193 hva_t hva; 194 bool map_writable; 195 }; 196 197 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault); 198 199 extern int nx_huge_pages; 200 static inline bool is_nx_huge_page_enabled(void) 201 { 202 return READ_ONCE(nx_huge_pages); 203 } 204 205 static inline int kvm_mmu_do_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 206 u32 err, bool prefetch) 207 { 208 struct kvm_page_fault fault = { 209 .addr = cr2_or_gpa, 210 .error_code = err, 211 .exec = err & PFERR_FETCH_MASK, 212 .write = err & PFERR_WRITE_MASK, 213 .present = err & PFERR_PRESENT_MASK, 214 .rsvd = err & PFERR_RSVD_MASK, 215 .user = err & PFERR_USER_MASK, 216 .prefetch = prefetch, 217 .is_tdp = likely(vcpu->arch.mmu->page_fault == kvm_tdp_page_fault), 218 .nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(), 219 220 .max_level = KVM_MAX_HUGEPAGE_LEVEL, 221 .req_level = PG_LEVEL_4K, 222 .goal_level = PG_LEVEL_4K, 223 }; 224 #ifdef CONFIG_RETPOLINE 225 if (fault.is_tdp) 226 return kvm_tdp_page_fault(vcpu, &fault); 227 #endif 228 return vcpu->arch.mmu->page_fault(vcpu, &fault); 229 } 230 231 /* 232 * Check if a given access (described through the I/D, W/R and U/S bits of a 233 * page fault error code pfec) causes a permission fault with the given PTE 234 * access rights (in ACC_* format). 235 * 236 * Return zero if the access does not fault; return the page fault error code 237 * if the access faults. 238 */ 239 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 240 unsigned pte_access, unsigned pte_pkey, 241 u64 access) 242 { 243 /* strip nested paging fault error codes */ 244 unsigned int pfec = access; 245 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 246 247 /* 248 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1. 249 * For implicit supervisor accesses, SMAP cannot be overridden. 250 * 251 * SMAP works on supervisor accesses only, and not_smap can 252 * be set or not set when user access with neither has any bearing 253 * on the result. 254 * 255 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit; 256 * this bit will always be zero in pfec, but it will be one in index 257 * if SMAP checks are being disabled. 258 */ 259 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS; 260 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC; 261 int index = (pfec + (not_smap << PFERR_RSVD_BIT)) >> 1; 262 bool fault = (mmu->permissions[index] >> pte_access) & 1; 263 u32 errcode = PFERR_PRESENT_MASK; 264 265 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK)); 266 if (unlikely(mmu->pkru_mask)) { 267 u32 pkru_bits, offset; 268 269 /* 270 * PKRU defines 32 bits, there are 16 domains and 2 271 * attribute bits per domain in pkru. pte_pkey is the 272 * index of the protection domain, so pte_pkey * 2 is 273 * is the index of the first bit for the domain. 274 */ 275 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3; 276 277 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */ 278 offset = (pfec & ~1) + 279 ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT)); 280 281 pkru_bits &= mmu->pkru_mask >> offset; 282 errcode |= -pkru_bits & PFERR_PK_MASK; 283 fault |= (pkru_bits != 0); 284 } 285 286 return -(u32)fault & errcode; 287 } 288 289 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end); 290 291 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu); 292 293 int kvm_mmu_post_init_vm(struct kvm *kvm); 294 void kvm_mmu_pre_destroy_vm(struct kvm *kvm); 295 296 static inline bool kvm_shadow_root_allocated(struct kvm *kvm) 297 { 298 /* 299 * Read shadow_root_allocated before related pointers. Hence, threads 300 * reading shadow_root_allocated in any lock context are guaranteed to 301 * see the pointers. Pairs with smp_store_release in 302 * mmu_first_shadow_root_alloc. 303 */ 304 return smp_load_acquire(&kvm->arch.shadow_root_allocated); 305 } 306 307 #ifdef CONFIG_X86_64 308 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return kvm->arch.tdp_mmu_enabled; } 309 #else 310 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return false; } 311 #endif 312 313 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm) 314 { 315 return !is_tdp_mmu_enabled(kvm) || kvm_shadow_root_allocated(kvm); 316 } 317 318 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 319 { 320 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */ 321 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 322 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 323 } 324 325 static inline unsigned long 326 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages, 327 int level) 328 { 329 return gfn_to_index(slot->base_gfn + npages - 1, 330 slot->base_gfn, level) + 1; 331 } 332 333 static inline unsigned long 334 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level) 335 { 336 return __kvm_mmu_slot_lpages(slot, slot->npages, level); 337 } 338 339 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count) 340 { 341 atomic64_add(count, &kvm->stat.pages[level - 1]); 342 } 343 344 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, 345 struct x86_exception *exception); 346 347 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu, 348 struct kvm_mmu *mmu, 349 gpa_t gpa, u64 access, 350 struct x86_exception *exception) 351 { 352 if (mmu != &vcpu->arch.nested_mmu) 353 return gpa; 354 return translate_nested_gpa(vcpu, gpa, access, exception); 355 } 356 #endif 357