1 #ifndef __KVM_X86_LAPIC_H 2 #define __KVM_X86_LAPIC_H 3 4 #include "iodev.h" 5 6 #include <linux/kvm_host.h> 7 8 #define KVM_APIC_INIT 0 9 #define KVM_APIC_SIPI 1 10 11 struct kvm_timer { 12 struct hrtimer timer; 13 s64 period; /* unit: ns */ 14 u32 timer_mode_mask; 15 u64 tscdeadline; 16 atomic_t pending; /* accumulated triggered timers */ 17 }; 18 19 struct kvm_lapic { 20 unsigned long base_address; 21 struct kvm_io_device dev; 22 struct kvm_timer lapic_timer; 23 u32 divide_count; 24 struct kvm_vcpu *vcpu; 25 bool irr_pending; 26 /* Number of bits set in ISR. */ 27 s16 isr_count; 28 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 29 int highest_isr_cache; 30 /** 31 * APIC register page. The layout matches the register layout seen by 32 * the guest 1:1, because it is accessed by the vmx microcode. 33 * Note: Only one register, the TPR, is used by the microcode. 34 */ 35 void *regs; 36 gpa_t vapic_addr; 37 struct gfn_to_hva_cache vapic_cache; 38 unsigned long pending_events; 39 unsigned int sipi_vector; 40 }; 41 int kvm_create_lapic(struct kvm_vcpu *vcpu); 42 void kvm_free_lapic(struct kvm_vcpu *vcpu); 43 44 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 45 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 46 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); 47 void kvm_apic_accept_events(struct kvm_vcpu *vcpu); 48 void kvm_lapic_reset(struct kvm_vcpu *vcpu); 49 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 50 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 51 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 52 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); 53 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); 54 void kvm_apic_set_version(struct kvm_vcpu *vcpu); 55 56 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr); 57 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); 58 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest); 59 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda); 60 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 61 unsigned long *dest_map); 62 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 63 64 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 65 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map); 66 67 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); 68 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 69 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, 70 struct kvm_lapic_state *s); 71 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 72 73 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 74 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 75 76 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 77 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 78 79 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 80 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 81 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 82 83 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 84 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 85 86 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 87 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 88 89 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) 90 { 91 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; 92 } 93 94 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); 95 void kvm_lapic_init(void); 96 97 static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off) 98 { 99 return *((u32 *) (apic->regs + reg_off)); 100 } 101 102 extern struct static_key kvm_no_apic_vcpu; 103 104 static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu) 105 { 106 if (static_key_false(&kvm_no_apic_vcpu)) 107 return vcpu->arch.apic; 108 return true; 109 } 110 111 extern struct static_key_deferred apic_hw_disabled; 112 113 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) 114 { 115 if (static_key_false(&apic_hw_disabled.key)) 116 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 117 return MSR_IA32_APICBASE_ENABLE; 118 } 119 120 extern struct static_key_deferred apic_sw_disabled; 121 122 static inline int kvm_apic_sw_enabled(struct kvm_lapic *apic) 123 { 124 if (static_key_false(&apic_sw_disabled.key)) 125 return kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; 126 return APIC_SPIV_APIC_ENABLED; 127 } 128 129 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 130 { 131 return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 132 } 133 134 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 135 { 136 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 137 } 138 139 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 140 { 141 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 142 } 143 144 static inline bool kvm_apic_vid_enabled(struct kvm *kvm) 145 { 146 return kvm_x86_ops->vm_has_apicv(kvm); 147 } 148 149 static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr) 150 { 151 u16 cid; 152 ldr >>= 32 - map->ldr_bits; 153 cid = (ldr >> map->cid_shift) & map->cid_mask; 154 155 BUG_ON(cid >= ARRAY_SIZE(map->logical_map)); 156 157 return cid; 158 } 159 160 static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr) 161 { 162 ldr >>= (32 - map->ldr_bits); 163 return ldr & map->lid_mask; 164 } 165 166 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) 167 { 168 return vcpu->arch.apic->pending_events; 169 } 170 171 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 172 173 #endif 174