xref: /openbmc/linux/arch/x86/kvm/lapic.h (revision 4da722ca)
1 #ifndef __KVM_X86_LAPIC_H
2 #define __KVM_X86_LAPIC_H
3 
4 #include <kvm/iodev.h>
5 
6 #include <linux/kvm_host.h>
7 
8 #define KVM_APIC_INIT		0
9 #define KVM_APIC_SIPI		1
10 #define KVM_APIC_LVT_NUM	6
11 
12 #define KVM_APIC_SHORT_MASK	0xc0000
13 #define KVM_APIC_DEST_MASK	0x800
14 
15 struct kvm_timer {
16 	struct hrtimer timer;
17 	s64 period; 				/* unit: ns */
18 	ktime_t target_expiration;
19 	u32 timer_mode;
20 	u32 timer_mode_mask;
21 	u64 tscdeadline;
22 	u64 expired_tscdeadline;
23 	atomic_t pending;			/* accumulated triggered timers */
24 	bool hv_timer_in_use;
25 };
26 
27 struct kvm_lapic {
28 	unsigned long base_address;
29 	struct kvm_io_device dev;
30 	struct kvm_timer lapic_timer;
31 	u32 divide_count;
32 	struct kvm_vcpu *vcpu;
33 	bool sw_enabled;
34 	bool irr_pending;
35 	bool lvt0_in_nmi_mode;
36 	/* Number of bits set in ISR. */
37 	s16 isr_count;
38 	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
39 	int highest_isr_cache;
40 	/**
41 	 * APIC register page.  The layout matches the register layout seen by
42 	 * the guest 1:1, because it is accessed by the vmx microcode.
43 	 * Note: Only one register, the TPR, is used by the microcode.
44 	 */
45 	void *regs;
46 	gpa_t vapic_addr;
47 	struct gfn_to_hva_cache vapic_cache;
48 	unsigned long pending_events;
49 	unsigned int sipi_vector;
50 };
51 
52 struct dest_map;
53 
54 int kvm_create_lapic(struct kvm_vcpu *vcpu);
55 void kvm_free_lapic(struct kvm_vcpu *vcpu);
56 
57 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
58 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
59 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
60 void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
61 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
62 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
63 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
64 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
65 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
66 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
67 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
68 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
69 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
70 		       void *data);
71 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
72 			   int short_hand, unsigned int dest, int dest_mode);
73 
74 int __kvm_apic_update_irr(u32 *pir, void *regs);
75 int kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
76 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
77 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
78 		     struct dest_map *dest_map);
79 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
80 
81 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
82 		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
83 
84 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
85 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
86 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
87 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
88 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
89 
90 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
91 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
92 
93 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
94 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
95 
96 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
97 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
98 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
99 
100 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
101 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
102 
103 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
104 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
105 
106 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
107 {
108 	return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
109 }
110 
111 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
112 void kvm_lapic_init(void);
113 void kvm_lapic_exit(void);
114 
115 #define VEC_POS(v) ((v) & (32 - 1))
116 #define REG_POS(v) (((v) >> 5) << 4)
117 
118 static inline void kvm_lapic_set_vector(int vec, void *bitmap)
119 {
120 	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
121 }
122 
123 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
124 {
125 	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
126 	/*
127 	 * irr_pending must be true if any interrupt is pending; set it after
128 	 * APIC_IRR to avoid race with apic_clear_irr
129 	 */
130 	apic->irr_pending = true;
131 }
132 
133 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
134 {
135 	return *((u32 *) (apic->regs + reg_off));
136 }
137 
138 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
139 {
140 	*((u32 *) (apic->regs + reg_off)) = val;
141 }
142 
143 extern struct static_key kvm_no_apic_vcpu;
144 
145 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
146 {
147 	if (static_key_false(&kvm_no_apic_vcpu))
148 		return vcpu->arch.apic;
149 	return true;
150 }
151 
152 extern struct static_key_deferred apic_hw_disabled;
153 
154 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
155 {
156 	if (static_key_false(&apic_hw_disabled.key))
157 		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
158 	return MSR_IA32_APICBASE_ENABLE;
159 }
160 
161 extern struct static_key_deferred apic_sw_disabled;
162 
163 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
164 {
165 	if (static_key_false(&apic_sw_disabled.key))
166 		return apic->sw_enabled;
167 	return true;
168 }
169 
170 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
171 {
172 	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
173 }
174 
175 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
176 {
177 	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
178 }
179 
180 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
181 {
182 	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
183 }
184 
185 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
186 {
187 	return vcpu->arch.apic && vcpu->arch.apicv_active;
188 }
189 
190 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
191 {
192 	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
193 }
194 
195 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
196 {
197 	return (irq->delivery_mode == APIC_DM_LOWEST ||
198 			irq->msi_redir_hint);
199 }
200 
201 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
202 {
203 	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
204 }
205 
206 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
207 
208 void wait_lapic_expire(struct kvm_vcpu *vcpu);
209 
210 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
211 			struct kvm_vcpu **dest_vcpu);
212 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
213 			const unsigned long *bitmap, u32 bitmap_size);
214 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
215 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
216 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
217 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
218 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
219 #endif
220