1 2 /* 3 * Local APIC virtualization 4 * 5 * Copyright (C) 2006 Qumranet, Inc. 6 * Copyright (C) 2007 Novell 7 * Copyright (C) 2007 Intel 8 * 9 * Authors: 10 * Dor Laor <dor.laor@qumranet.com> 11 * Gregory Haskins <ghaskins@novell.com> 12 * Yaozu (Eddie) Dong <eddie.dong@intel.com> 13 * 14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. 15 * 16 * This work is licensed under the terms of the GNU GPL, version 2. See 17 * the COPYING file in the top-level directory. 18 */ 19 20 #include <linux/kvm_host.h> 21 #include <linux/kvm.h> 22 #include <linux/mm.h> 23 #include <linux/highmem.h> 24 #include <linux/smp.h> 25 #include <linux/hrtimer.h> 26 #include <linux/io.h> 27 #include <linux/module.h> 28 #include <linux/math64.h> 29 #include <asm/processor.h> 30 #include <asm/msr.h> 31 #include <asm/page.h> 32 #include <asm/current.h> 33 #include <asm/apicdef.h> 34 #include <asm/atomic.h> 35 #include "kvm_cache_regs.h" 36 #include "irq.h" 37 #include "trace.h" 38 #include "x86.h" 39 40 #ifndef CONFIG_X86_64 41 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) 42 #else 43 #define mod_64(x, y) ((x) % (y)) 44 #endif 45 46 #define PRId64 "d" 47 #define PRIx64 "llx" 48 #define PRIu64 "u" 49 #define PRIo64 "o" 50 51 #define APIC_BUS_CYCLE_NS 1 52 53 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ 54 #define apic_debug(fmt, arg...) 55 56 #define APIC_LVT_NUM 6 57 /* 14 is the version for Xeon and Pentium 8.4.8*/ 58 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) 59 #define LAPIC_MMIO_LENGTH (1 << 12) 60 /* followed define is not in apicdef.h */ 61 #define APIC_SHORT_MASK 0xc0000 62 #define APIC_DEST_NOSHORT 0x0 63 #define APIC_DEST_MASK 0x800 64 #define MAX_APIC_VECTOR 256 65 66 #define VEC_POS(v) ((v) & (32 - 1)) 67 #define REG_POS(v) (((v) >> 5) << 4) 68 69 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off) 70 { 71 return *((u32 *) (apic->regs + reg_off)); 72 } 73 74 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 75 { 76 *((u32 *) (apic->regs + reg_off)) = val; 77 } 78 79 static inline int apic_test_and_set_vector(int vec, void *bitmap) 80 { 81 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 82 } 83 84 static inline int apic_test_and_clear_vector(int vec, void *bitmap) 85 { 86 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 87 } 88 89 static inline void apic_set_vector(int vec, void *bitmap) 90 { 91 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 92 } 93 94 static inline void apic_clear_vector(int vec, void *bitmap) 95 { 96 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 97 } 98 99 static inline int apic_hw_enabled(struct kvm_lapic *apic) 100 { 101 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 102 } 103 104 static inline int apic_sw_enabled(struct kvm_lapic *apic) 105 { 106 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; 107 } 108 109 static inline int apic_enabled(struct kvm_lapic *apic) 110 { 111 return apic_sw_enabled(apic) && apic_hw_enabled(apic); 112 } 113 114 #define LVT_MASK \ 115 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) 116 117 #define LINT_MASK \ 118 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ 119 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) 120 121 static inline int kvm_apic_id(struct kvm_lapic *apic) 122 { 123 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff; 124 } 125 126 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) 127 { 128 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); 129 } 130 131 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) 132 { 133 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; 134 } 135 136 static inline int apic_lvtt_period(struct kvm_lapic *apic) 137 { 138 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC; 139 } 140 141 static inline int apic_lvt_nmi_mode(u32 lvt_val) 142 { 143 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; 144 } 145 146 void kvm_apic_set_version(struct kvm_vcpu *vcpu) 147 { 148 struct kvm_lapic *apic = vcpu->arch.apic; 149 struct kvm_cpuid_entry2 *feat; 150 u32 v = APIC_VERSION; 151 152 if (!irqchip_in_kernel(vcpu->kvm)) 153 return; 154 155 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); 156 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) 157 v |= APIC_LVR_DIRECTED_EOI; 158 apic_set_reg(apic, APIC_LVR, v); 159 } 160 161 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 162 { 163 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 164 } 165 166 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = { 167 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */ 168 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ 169 LVT_MASK | APIC_MODE_MASK, /* LVTPC */ 170 LINT_MASK, LINT_MASK, /* LVT0-1 */ 171 LVT_MASK /* LVTERR */ 172 }; 173 174 static int find_highest_vector(void *bitmap) 175 { 176 u32 *word = bitmap; 177 int word_offset = MAX_APIC_VECTOR >> 5; 178 179 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0)) 180 continue; 181 182 if (likely(!word_offset && !word[0])) 183 return -1; 184 else 185 return fls(word[word_offset << 2]) - 1 + (word_offset << 5); 186 } 187 188 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic) 189 { 190 apic->irr_pending = true; 191 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR); 192 } 193 194 static inline int apic_search_irr(struct kvm_lapic *apic) 195 { 196 return find_highest_vector(apic->regs + APIC_IRR); 197 } 198 199 static inline int apic_find_highest_irr(struct kvm_lapic *apic) 200 { 201 int result; 202 203 if (!apic->irr_pending) 204 return -1; 205 206 result = apic_search_irr(apic); 207 ASSERT(result == -1 || result >= 16); 208 209 return result; 210 } 211 212 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) 213 { 214 apic->irr_pending = false; 215 apic_clear_vector(vec, apic->regs + APIC_IRR); 216 if (apic_search_irr(apic) != -1) 217 apic->irr_pending = true; 218 } 219 220 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) 221 { 222 struct kvm_lapic *apic = vcpu->arch.apic; 223 int highest_irr; 224 225 /* This may race with setting of irr in __apic_accept_irq() and 226 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq 227 * will cause vmexit immediately and the value will be recalculated 228 * on the next vmentry. 229 */ 230 if (!apic) 231 return 0; 232 highest_irr = apic_find_highest_irr(apic); 233 234 return highest_irr; 235 } 236 237 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 238 int vector, int level, int trig_mode); 239 240 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq) 241 { 242 struct kvm_lapic *apic = vcpu->arch.apic; 243 244 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, 245 irq->level, irq->trig_mode); 246 } 247 248 static inline int apic_find_highest_isr(struct kvm_lapic *apic) 249 { 250 int result; 251 252 result = find_highest_vector(apic->regs + APIC_ISR); 253 ASSERT(result == -1 || result >= 16); 254 255 return result; 256 } 257 258 static void apic_update_ppr(struct kvm_lapic *apic) 259 { 260 u32 tpr, isrv, ppr; 261 int isr; 262 263 tpr = apic_get_reg(apic, APIC_TASKPRI); 264 isr = apic_find_highest_isr(apic); 265 isrv = (isr != -1) ? isr : 0; 266 267 if ((tpr & 0xf0) >= (isrv & 0xf0)) 268 ppr = tpr & 0xff; 269 else 270 ppr = isrv & 0xf0; 271 272 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", 273 apic, ppr, isr, isrv); 274 275 apic_set_reg(apic, APIC_PROCPRI, ppr); 276 } 277 278 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) 279 { 280 apic_set_reg(apic, APIC_TASKPRI, tpr); 281 apic_update_ppr(apic); 282 } 283 284 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest) 285 { 286 return dest == 0xff || kvm_apic_id(apic) == dest; 287 } 288 289 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda) 290 { 291 int result = 0; 292 u32 logical_id; 293 294 if (apic_x2apic_mode(apic)) { 295 logical_id = apic_get_reg(apic, APIC_LDR); 296 return logical_id & mda; 297 } 298 299 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR)); 300 301 switch (apic_get_reg(apic, APIC_DFR)) { 302 case APIC_DFR_FLAT: 303 if (logical_id & mda) 304 result = 1; 305 break; 306 case APIC_DFR_CLUSTER: 307 if (((logical_id >> 4) == (mda >> 0x4)) 308 && (logical_id & mda & 0xf)) 309 result = 1; 310 break; 311 default: 312 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n", 313 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR)); 314 break; 315 } 316 317 return result; 318 } 319 320 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 321 int short_hand, int dest, int dest_mode) 322 { 323 int result = 0; 324 struct kvm_lapic *target = vcpu->arch.apic; 325 326 apic_debug("target %p, source %p, dest 0x%x, " 327 "dest_mode 0x%x, short_hand 0x%x\n", 328 target, source, dest, dest_mode, short_hand); 329 330 ASSERT(!target); 331 switch (short_hand) { 332 case APIC_DEST_NOSHORT: 333 if (dest_mode == 0) 334 /* Physical mode. */ 335 result = kvm_apic_match_physical_addr(target, dest); 336 else 337 /* Logical mode. */ 338 result = kvm_apic_match_logical_addr(target, dest); 339 break; 340 case APIC_DEST_SELF: 341 result = (target == source); 342 break; 343 case APIC_DEST_ALLINC: 344 result = 1; 345 break; 346 case APIC_DEST_ALLBUT: 347 result = (target != source); 348 break; 349 default: 350 printk(KERN_WARNING "Bad dest shorthand value %x\n", 351 short_hand); 352 break; 353 } 354 355 return result; 356 } 357 358 /* 359 * Add a pending IRQ into lapic. 360 * Return 1 if successfully added and 0 if discarded. 361 */ 362 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 363 int vector, int level, int trig_mode) 364 { 365 int result = 0; 366 struct kvm_vcpu *vcpu = apic->vcpu; 367 368 switch (delivery_mode) { 369 case APIC_DM_LOWEST: 370 vcpu->arch.apic_arb_prio++; 371 case APIC_DM_FIXED: 372 /* FIXME add logic for vcpu on reset */ 373 if (unlikely(!apic_enabled(apic))) 374 break; 375 376 result = !apic_test_and_set_irr(vector, apic); 377 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, 378 trig_mode, vector, !result); 379 if (!result) { 380 if (trig_mode) 381 apic_debug("level trig mode repeatedly for " 382 "vector %d", vector); 383 break; 384 } 385 386 if (trig_mode) { 387 apic_debug("level trig mode for vector %d", vector); 388 apic_set_vector(vector, apic->regs + APIC_TMR); 389 } else 390 apic_clear_vector(vector, apic->regs + APIC_TMR); 391 kvm_vcpu_kick(vcpu); 392 break; 393 394 case APIC_DM_REMRD: 395 printk(KERN_DEBUG "Ignoring delivery mode 3\n"); 396 break; 397 398 case APIC_DM_SMI: 399 printk(KERN_DEBUG "Ignoring guest SMI\n"); 400 break; 401 402 case APIC_DM_NMI: 403 result = 1; 404 kvm_inject_nmi(vcpu); 405 kvm_vcpu_kick(vcpu); 406 break; 407 408 case APIC_DM_INIT: 409 if (level) { 410 result = 1; 411 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) 412 printk(KERN_DEBUG 413 "INIT on a runnable vcpu %d\n", 414 vcpu->vcpu_id); 415 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 416 kvm_vcpu_kick(vcpu); 417 } else { 418 apic_debug("Ignoring de-assert INIT to vcpu %d\n", 419 vcpu->vcpu_id); 420 } 421 break; 422 423 case APIC_DM_STARTUP: 424 apic_debug("SIPI to vcpu %d vector 0x%02x\n", 425 vcpu->vcpu_id, vector); 426 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 427 result = 1; 428 vcpu->arch.sipi_vector = vector; 429 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED; 430 kvm_vcpu_kick(vcpu); 431 } 432 break; 433 434 case APIC_DM_EXTINT: 435 /* 436 * Should only be called by kvm_apic_local_deliver() with LVT0, 437 * before NMI watchdog was enabled. Already handled by 438 * kvm_apic_accept_pic_intr(). 439 */ 440 break; 441 442 default: 443 printk(KERN_ERR "TODO: unsupported delivery mode %x\n", 444 delivery_mode); 445 break; 446 } 447 return result; 448 } 449 450 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) 451 { 452 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; 453 } 454 455 static void apic_set_eoi(struct kvm_lapic *apic) 456 { 457 int vector = apic_find_highest_isr(apic); 458 int trigger_mode; 459 /* 460 * Not every write EOI will has corresponding ISR, 461 * one example is when Kernel check timer on setup_IO_APIC 462 */ 463 if (vector == -1) 464 return; 465 466 apic_clear_vector(vector, apic->regs + APIC_ISR); 467 apic_update_ppr(apic); 468 469 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR)) 470 trigger_mode = IOAPIC_LEVEL_TRIG; 471 else 472 trigger_mode = IOAPIC_EDGE_TRIG; 473 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)) 474 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode); 475 } 476 477 static void apic_send_ipi(struct kvm_lapic *apic) 478 { 479 u32 icr_low = apic_get_reg(apic, APIC_ICR); 480 u32 icr_high = apic_get_reg(apic, APIC_ICR2); 481 struct kvm_lapic_irq irq; 482 483 irq.vector = icr_low & APIC_VECTOR_MASK; 484 irq.delivery_mode = icr_low & APIC_MODE_MASK; 485 irq.dest_mode = icr_low & APIC_DEST_MASK; 486 irq.level = icr_low & APIC_INT_ASSERT; 487 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; 488 irq.shorthand = icr_low & APIC_SHORT_MASK; 489 if (apic_x2apic_mode(apic)) 490 irq.dest_id = icr_high; 491 else 492 irq.dest_id = GET_APIC_DEST_FIELD(icr_high); 493 494 trace_kvm_apic_ipi(icr_low, irq.dest_id); 495 496 apic_debug("icr_high 0x%x, icr_low 0x%x, " 497 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " 498 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", 499 icr_high, icr_low, irq.shorthand, irq.dest_id, 500 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, 501 irq.vector); 502 503 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq); 504 } 505 506 static u32 apic_get_tmcct(struct kvm_lapic *apic) 507 { 508 ktime_t remaining; 509 s64 ns; 510 u32 tmcct; 511 512 ASSERT(apic != NULL); 513 514 /* if initial count is 0, current count should also be 0 */ 515 if (apic_get_reg(apic, APIC_TMICT) == 0) 516 return 0; 517 518 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); 519 if (ktime_to_ns(remaining) < 0) 520 remaining = ktime_set(0, 0); 521 522 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); 523 tmcct = div64_u64(ns, 524 (APIC_BUS_CYCLE_NS * apic->divide_count)); 525 526 return tmcct; 527 } 528 529 static void __report_tpr_access(struct kvm_lapic *apic, bool write) 530 { 531 struct kvm_vcpu *vcpu = apic->vcpu; 532 struct kvm_run *run = vcpu->run; 533 534 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests); 535 run->tpr_access.rip = kvm_rip_read(vcpu); 536 run->tpr_access.is_write = write; 537 } 538 539 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) 540 { 541 if (apic->vcpu->arch.tpr_access_reporting) 542 __report_tpr_access(apic, write); 543 } 544 545 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) 546 { 547 u32 val = 0; 548 549 if (offset >= LAPIC_MMIO_LENGTH) 550 return 0; 551 552 switch (offset) { 553 case APIC_ID: 554 if (apic_x2apic_mode(apic)) 555 val = kvm_apic_id(apic); 556 else 557 val = kvm_apic_id(apic) << 24; 558 break; 559 case APIC_ARBPRI: 560 printk(KERN_WARNING "Access APIC ARBPRI register " 561 "which is for P6\n"); 562 break; 563 564 case APIC_TMCCT: /* Timer CCR */ 565 val = apic_get_tmcct(apic); 566 break; 567 568 case APIC_TASKPRI: 569 report_tpr_access(apic, false); 570 /* fall thru */ 571 default: 572 apic_update_ppr(apic); 573 val = apic_get_reg(apic, offset); 574 break; 575 } 576 577 return val; 578 } 579 580 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) 581 { 582 return container_of(dev, struct kvm_lapic, dev); 583 } 584 585 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, 586 void *data) 587 { 588 unsigned char alignment = offset & 0xf; 589 u32 result; 590 /* this bitmask has a bit cleared for each reserver register */ 591 static const u64 rmask = 0x43ff01ffffffe70cULL; 592 593 if ((alignment + len) > 4) { 594 apic_debug("KVM_APIC_READ: alignment error %x %d\n", 595 offset, len); 596 return 1; 597 } 598 599 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { 600 apic_debug("KVM_APIC_READ: read reserved register %x\n", 601 offset); 602 return 1; 603 } 604 605 result = __apic_read(apic, offset & ~0xf); 606 607 trace_kvm_apic_read(offset, result); 608 609 switch (len) { 610 case 1: 611 case 2: 612 case 4: 613 memcpy(data, (char *)&result + alignment, len); 614 break; 615 default: 616 printk(KERN_ERR "Local APIC read with len = %x, " 617 "should be 1,2, or 4 instead\n", len); 618 break; 619 } 620 return 0; 621 } 622 623 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) 624 { 625 return apic_hw_enabled(apic) && 626 addr >= apic->base_address && 627 addr < apic->base_address + LAPIC_MMIO_LENGTH; 628 } 629 630 static int apic_mmio_read(struct kvm_io_device *this, 631 gpa_t address, int len, void *data) 632 { 633 struct kvm_lapic *apic = to_lapic(this); 634 u32 offset = address - apic->base_address; 635 636 if (!apic_mmio_in_range(apic, address)) 637 return -EOPNOTSUPP; 638 639 apic_reg_read(apic, offset, len, data); 640 641 return 0; 642 } 643 644 static void update_divide_count(struct kvm_lapic *apic) 645 { 646 u32 tmp1, tmp2, tdcr; 647 648 tdcr = apic_get_reg(apic, APIC_TDCR); 649 tmp1 = tdcr & 0xf; 650 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; 651 apic->divide_count = 0x1 << (tmp2 & 0x7); 652 653 apic_debug("timer divide count is 0x%x\n", 654 apic->divide_count); 655 } 656 657 static void start_apic_timer(struct kvm_lapic *apic) 658 { 659 ktime_t now = apic->lapic_timer.timer.base->get_time(); 660 661 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) * 662 APIC_BUS_CYCLE_NS * apic->divide_count; 663 atomic_set(&apic->lapic_timer.pending, 0); 664 665 if (!apic->lapic_timer.period) 666 return; 667 /* 668 * Do not allow the guest to program periodic timers with small 669 * interval, since the hrtimers are not throttled by the host 670 * scheduler. 671 */ 672 if (apic_lvtt_period(apic)) { 673 if (apic->lapic_timer.period < NSEC_PER_MSEC/2) 674 apic->lapic_timer.period = NSEC_PER_MSEC/2; 675 } 676 677 hrtimer_start(&apic->lapic_timer.timer, 678 ktime_add_ns(now, apic->lapic_timer.period), 679 HRTIMER_MODE_ABS); 680 681 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" 682 PRIx64 ", " 683 "timer initial count 0x%x, period %lldns, " 684 "expire @ 0x%016" PRIx64 ".\n", __func__, 685 APIC_BUS_CYCLE_NS, ktime_to_ns(now), 686 apic_get_reg(apic, APIC_TMICT), 687 apic->lapic_timer.period, 688 ktime_to_ns(ktime_add_ns(now, 689 apic->lapic_timer.period))); 690 } 691 692 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) 693 { 694 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0)); 695 696 if (apic_lvt_nmi_mode(lvt0_val)) { 697 if (!nmi_wd_enabled) { 698 apic_debug("Receive NMI setting on APIC_LVT0 " 699 "for cpu %d\n", apic->vcpu->vcpu_id); 700 apic->vcpu->kvm->arch.vapics_in_nmi_mode++; 701 } 702 } else if (nmi_wd_enabled) 703 apic->vcpu->kvm->arch.vapics_in_nmi_mode--; 704 } 705 706 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) 707 { 708 int ret = 0; 709 710 trace_kvm_apic_write(reg, val); 711 712 switch (reg) { 713 case APIC_ID: /* Local APIC ID */ 714 if (!apic_x2apic_mode(apic)) 715 apic_set_reg(apic, APIC_ID, val); 716 else 717 ret = 1; 718 break; 719 720 case APIC_TASKPRI: 721 report_tpr_access(apic, true); 722 apic_set_tpr(apic, val & 0xff); 723 break; 724 725 case APIC_EOI: 726 apic_set_eoi(apic); 727 break; 728 729 case APIC_LDR: 730 if (!apic_x2apic_mode(apic)) 731 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK); 732 else 733 ret = 1; 734 break; 735 736 case APIC_DFR: 737 if (!apic_x2apic_mode(apic)) 738 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); 739 else 740 ret = 1; 741 break; 742 743 case APIC_SPIV: { 744 u32 mask = 0x3ff; 745 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) 746 mask |= APIC_SPIV_DIRECTED_EOI; 747 apic_set_reg(apic, APIC_SPIV, val & mask); 748 if (!(val & APIC_SPIV_APIC_ENABLED)) { 749 int i; 750 u32 lvt_val; 751 752 for (i = 0; i < APIC_LVT_NUM; i++) { 753 lvt_val = apic_get_reg(apic, 754 APIC_LVTT + 0x10 * i); 755 apic_set_reg(apic, APIC_LVTT + 0x10 * i, 756 lvt_val | APIC_LVT_MASKED); 757 } 758 atomic_set(&apic->lapic_timer.pending, 0); 759 760 } 761 break; 762 } 763 case APIC_ICR: 764 /* No delay here, so we always clear the pending bit */ 765 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); 766 apic_send_ipi(apic); 767 break; 768 769 case APIC_ICR2: 770 if (!apic_x2apic_mode(apic)) 771 val &= 0xff000000; 772 apic_set_reg(apic, APIC_ICR2, val); 773 break; 774 775 case APIC_LVT0: 776 apic_manage_nmi_watchdog(apic, val); 777 case APIC_LVTT: 778 case APIC_LVTTHMR: 779 case APIC_LVTPC: 780 case APIC_LVT1: 781 case APIC_LVTERR: 782 /* TODO: Check vector */ 783 if (!apic_sw_enabled(apic)) 784 val |= APIC_LVT_MASKED; 785 786 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; 787 apic_set_reg(apic, reg, val); 788 789 break; 790 791 case APIC_TMICT: 792 hrtimer_cancel(&apic->lapic_timer.timer); 793 apic_set_reg(apic, APIC_TMICT, val); 794 start_apic_timer(apic); 795 break; 796 797 case APIC_TDCR: 798 if (val & 4) 799 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val); 800 apic_set_reg(apic, APIC_TDCR, val); 801 update_divide_count(apic); 802 break; 803 804 case APIC_ESR: 805 if (apic_x2apic_mode(apic) && val != 0) { 806 printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val); 807 ret = 1; 808 } 809 break; 810 811 case APIC_SELF_IPI: 812 if (apic_x2apic_mode(apic)) { 813 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); 814 } else 815 ret = 1; 816 break; 817 default: 818 ret = 1; 819 break; 820 } 821 if (ret) 822 apic_debug("Local APIC Write to read-only register %x\n", reg); 823 return ret; 824 } 825 826 static int apic_mmio_write(struct kvm_io_device *this, 827 gpa_t address, int len, const void *data) 828 { 829 struct kvm_lapic *apic = to_lapic(this); 830 unsigned int offset = address - apic->base_address; 831 u32 val; 832 833 if (!apic_mmio_in_range(apic, address)) 834 return -EOPNOTSUPP; 835 836 /* 837 * APIC register must be aligned on 128-bits boundary. 838 * 32/64/128 bits registers must be accessed thru 32 bits. 839 * Refer SDM 8.4.1 840 */ 841 if (len != 4 || (offset & 0xf)) { 842 /* Don't shout loud, $infamous_os would cause only noise. */ 843 apic_debug("apic write: bad size=%d %lx\n", len, (long)address); 844 return 0; 845 } 846 847 val = *(u32*)data; 848 849 /* too common printing */ 850 if (offset != APIC_EOI) 851 apic_debug("%s: offset 0x%x with length 0x%x, and value is " 852 "0x%x\n", __func__, offset, len, val); 853 854 apic_reg_write(apic, offset & 0xff0, val); 855 856 return 0; 857 } 858 859 void kvm_free_lapic(struct kvm_vcpu *vcpu) 860 { 861 if (!vcpu->arch.apic) 862 return; 863 864 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer); 865 866 if (vcpu->arch.apic->regs_page) 867 __free_page(vcpu->arch.apic->regs_page); 868 869 kfree(vcpu->arch.apic); 870 } 871 872 /* 873 *---------------------------------------------------------------------- 874 * LAPIC interface 875 *---------------------------------------------------------------------- 876 */ 877 878 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) 879 { 880 struct kvm_lapic *apic = vcpu->arch.apic; 881 882 if (!apic) 883 return; 884 apic_set_tpr(apic, ((cr8 & 0x0f) << 4) 885 | (apic_get_reg(apic, APIC_TASKPRI) & 4)); 886 } 887 888 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) 889 { 890 struct kvm_lapic *apic = vcpu->arch.apic; 891 u64 tpr; 892 893 if (!apic) 894 return 0; 895 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI); 896 897 return (tpr & 0xf0) >> 4; 898 } 899 900 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) 901 { 902 struct kvm_lapic *apic = vcpu->arch.apic; 903 904 if (!apic) { 905 value |= MSR_IA32_APICBASE_BSP; 906 vcpu->arch.apic_base = value; 907 return; 908 } 909 910 if (!kvm_vcpu_is_bsp(apic->vcpu)) 911 value &= ~MSR_IA32_APICBASE_BSP; 912 913 vcpu->arch.apic_base = value; 914 if (apic_x2apic_mode(apic)) { 915 u32 id = kvm_apic_id(apic); 916 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf)); 917 apic_set_reg(apic, APIC_LDR, ldr); 918 } 919 apic->base_address = apic->vcpu->arch.apic_base & 920 MSR_IA32_APICBASE_BASE; 921 922 /* with FSB delivery interrupt, we can restart APIC functionality */ 923 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " 924 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); 925 926 } 927 928 void kvm_lapic_reset(struct kvm_vcpu *vcpu) 929 { 930 struct kvm_lapic *apic; 931 int i; 932 933 apic_debug("%s\n", __func__); 934 935 ASSERT(vcpu); 936 apic = vcpu->arch.apic; 937 ASSERT(apic != NULL); 938 939 /* Stop the timer in case it's a reset to an active apic */ 940 hrtimer_cancel(&apic->lapic_timer.timer); 941 942 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24); 943 kvm_apic_set_version(apic->vcpu); 944 945 for (i = 0; i < APIC_LVT_NUM; i++) 946 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); 947 apic_set_reg(apic, APIC_LVT0, 948 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); 949 950 apic_set_reg(apic, APIC_DFR, 0xffffffffU); 951 apic_set_reg(apic, APIC_SPIV, 0xff); 952 apic_set_reg(apic, APIC_TASKPRI, 0); 953 apic_set_reg(apic, APIC_LDR, 0); 954 apic_set_reg(apic, APIC_ESR, 0); 955 apic_set_reg(apic, APIC_ICR, 0); 956 apic_set_reg(apic, APIC_ICR2, 0); 957 apic_set_reg(apic, APIC_TDCR, 0); 958 apic_set_reg(apic, APIC_TMICT, 0); 959 for (i = 0; i < 8; i++) { 960 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); 961 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); 962 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); 963 } 964 apic->irr_pending = false; 965 update_divide_count(apic); 966 atomic_set(&apic->lapic_timer.pending, 0); 967 if (kvm_vcpu_is_bsp(vcpu)) 968 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP; 969 apic_update_ppr(apic); 970 971 vcpu->arch.apic_arb_prio = 0; 972 973 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr=" 974 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, 975 vcpu, kvm_apic_id(apic), 976 vcpu->arch.apic_base, apic->base_address); 977 } 978 979 bool kvm_apic_present(struct kvm_vcpu *vcpu) 980 { 981 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic); 982 } 983 984 int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 985 { 986 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic); 987 } 988 989 /* 990 *---------------------------------------------------------------------- 991 * timer interface 992 *---------------------------------------------------------------------- 993 */ 994 995 static bool lapic_is_periodic(struct kvm_timer *ktimer) 996 { 997 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, 998 lapic_timer); 999 return apic_lvtt_period(apic); 1000 } 1001 1002 int apic_has_pending_timer(struct kvm_vcpu *vcpu) 1003 { 1004 struct kvm_lapic *lapic = vcpu->arch.apic; 1005 1006 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT)) 1007 return atomic_read(&lapic->lapic_timer.pending); 1008 1009 return 0; 1010 } 1011 1012 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) 1013 { 1014 u32 reg = apic_get_reg(apic, lvt_type); 1015 int vector, mode, trig_mode; 1016 1017 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { 1018 vector = reg & APIC_VECTOR_MASK; 1019 mode = reg & APIC_MODE_MASK; 1020 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; 1021 return __apic_accept_irq(apic, mode, vector, 1, trig_mode); 1022 } 1023 return 0; 1024 } 1025 1026 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) 1027 { 1028 struct kvm_lapic *apic = vcpu->arch.apic; 1029 1030 if (apic) 1031 kvm_apic_local_deliver(apic, APIC_LVT0); 1032 } 1033 1034 static struct kvm_timer_ops lapic_timer_ops = { 1035 .is_periodic = lapic_is_periodic, 1036 }; 1037 1038 static const struct kvm_io_device_ops apic_mmio_ops = { 1039 .read = apic_mmio_read, 1040 .write = apic_mmio_write, 1041 }; 1042 1043 int kvm_create_lapic(struct kvm_vcpu *vcpu) 1044 { 1045 struct kvm_lapic *apic; 1046 1047 ASSERT(vcpu != NULL); 1048 apic_debug("apic_init %d\n", vcpu->vcpu_id); 1049 1050 apic = kzalloc(sizeof(*apic), GFP_KERNEL); 1051 if (!apic) 1052 goto nomem; 1053 1054 vcpu->arch.apic = apic; 1055 1056 apic->regs_page = alloc_page(GFP_KERNEL); 1057 if (apic->regs_page == NULL) { 1058 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", 1059 vcpu->vcpu_id); 1060 goto nomem_free_apic; 1061 } 1062 apic->regs = page_address(apic->regs_page); 1063 memset(apic->regs, 0, PAGE_SIZE); 1064 apic->vcpu = vcpu; 1065 1066 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, 1067 HRTIMER_MODE_ABS); 1068 apic->lapic_timer.timer.function = kvm_timer_fn; 1069 apic->lapic_timer.t_ops = &lapic_timer_ops; 1070 apic->lapic_timer.kvm = vcpu->kvm; 1071 apic->lapic_timer.vcpu = vcpu; 1072 1073 apic->base_address = APIC_DEFAULT_PHYS_BASE; 1074 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE; 1075 1076 kvm_lapic_reset(vcpu); 1077 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); 1078 1079 return 0; 1080 nomem_free_apic: 1081 kfree(apic); 1082 nomem: 1083 return -ENOMEM; 1084 } 1085 1086 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) 1087 { 1088 struct kvm_lapic *apic = vcpu->arch.apic; 1089 int highest_irr; 1090 1091 if (!apic || !apic_enabled(apic)) 1092 return -1; 1093 1094 apic_update_ppr(apic); 1095 highest_irr = apic_find_highest_irr(apic); 1096 if ((highest_irr == -1) || 1097 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI))) 1098 return -1; 1099 return highest_irr; 1100 } 1101 1102 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) 1103 { 1104 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0); 1105 int r = 0; 1106 1107 if (kvm_vcpu_is_bsp(vcpu)) { 1108 if (!apic_hw_enabled(vcpu->arch.apic)) 1109 r = 1; 1110 if ((lvt0 & APIC_LVT_MASKED) == 0 && 1111 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) 1112 r = 1; 1113 } 1114 return r; 1115 } 1116 1117 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) 1118 { 1119 struct kvm_lapic *apic = vcpu->arch.apic; 1120 1121 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) { 1122 if (kvm_apic_local_deliver(apic, APIC_LVTT)) 1123 atomic_dec(&apic->lapic_timer.pending); 1124 } 1125 } 1126 1127 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) 1128 { 1129 int vector = kvm_apic_has_interrupt(vcpu); 1130 struct kvm_lapic *apic = vcpu->arch.apic; 1131 1132 if (vector == -1) 1133 return -1; 1134 1135 apic_set_vector(vector, apic->regs + APIC_ISR); 1136 apic_update_ppr(apic); 1137 apic_clear_irr(vector, apic); 1138 return vector; 1139 } 1140 1141 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu) 1142 { 1143 struct kvm_lapic *apic = vcpu->arch.apic; 1144 1145 apic->base_address = vcpu->arch.apic_base & 1146 MSR_IA32_APICBASE_BASE; 1147 kvm_apic_set_version(vcpu); 1148 1149 apic_update_ppr(apic); 1150 hrtimer_cancel(&apic->lapic_timer.timer); 1151 update_divide_count(apic); 1152 start_apic_timer(apic); 1153 apic->irr_pending = true; 1154 } 1155 1156 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) 1157 { 1158 struct kvm_lapic *apic = vcpu->arch.apic; 1159 struct hrtimer *timer; 1160 1161 if (!apic) 1162 return; 1163 1164 timer = &apic->lapic_timer.timer; 1165 if (hrtimer_cancel(timer)) 1166 hrtimer_start_expires(timer, HRTIMER_MODE_ABS); 1167 } 1168 1169 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) 1170 { 1171 u32 data; 1172 void *vapic; 1173 1174 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) 1175 return; 1176 1177 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); 1178 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)); 1179 kunmap_atomic(vapic, KM_USER0); 1180 1181 apic_set_tpr(vcpu->arch.apic, data & 0xff); 1182 } 1183 1184 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) 1185 { 1186 u32 data, tpr; 1187 int max_irr, max_isr; 1188 struct kvm_lapic *apic; 1189 void *vapic; 1190 1191 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) 1192 return; 1193 1194 apic = vcpu->arch.apic; 1195 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff; 1196 max_irr = apic_find_highest_irr(apic); 1197 if (max_irr < 0) 1198 max_irr = 0; 1199 max_isr = apic_find_highest_isr(apic); 1200 if (max_isr < 0) 1201 max_isr = 0; 1202 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); 1203 1204 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); 1205 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data; 1206 kunmap_atomic(vapic, KM_USER0); 1207 } 1208 1209 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) 1210 { 1211 if (!irqchip_in_kernel(vcpu->kvm)) 1212 return; 1213 1214 vcpu->arch.apic->vapic_addr = vapic_addr; 1215 } 1216 1217 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1218 { 1219 struct kvm_lapic *apic = vcpu->arch.apic; 1220 u32 reg = (msr - APIC_BASE_MSR) << 4; 1221 1222 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) 1223 return 1; 1224 1225 /* if this is ICR write vector before command */ 1226 if (msr == 0x830) 1227 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 1228 return apic_reg_write(apic, reg, (u32)data); 1229 } 1230 1231 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) 1232 { 1233 struct kvm_lapic *apic = vcpu->arch.apic; 1234 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; 1235 1236 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) 1237 return 1; 1238 1239 if (apic_reg_read(apic, reg, 4, &low)) 1240 return 1; 1241 if (msr == 0x830) 1242 apic_reg_read(apic, APIC_ICR2, 4, &high); 1243 1244 *data = (((u64)high) << 32) | low; 1245 1246 return 0; 1247 } 1248