1 2 /* 3 * Local APIC virtualization 4 * 5 * Copyright (C) 2006 Qumranet, Inc. 6 * Copyright (C) 2007 Novell 7 * Copyright (C) 2007 Intel 8 * 9 * Authors: 10 * Dor Laor <dor.laor@qumranet.com> 11 * Gregory Haskins <ghaskins@novell.com> 12 * Yaozu (Eddie) Dong <eddie.dong@intel.com> 13 * 14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. 15 * 16 * This work is licensed under the terms of the GNU GPL, version 2. See 17 * the COPYING file in the top-level directory. 18 */ 19 20 #include <linux/kvm_host.h> 21 #include <linux/kvm.h> 22 #include <linux/mm.h> 23 #include <linux/highmem.h> 24 #include <linux/smp.h> 25 #include <linux/hrtimer.h> 26 #include <linux/io.h> 27 #include <linux/module.h> 28 #include <linux/math64.h> 29 #include <asm/processor.h> 30 #include <asm/msr.h> 31 #include <asm/page.h> 32 #include <asm/current.h> 33 #include <asm/apicdef.h> 34 #include <asm/atomic.h> 35 #include "kvm_cache_regs.h" 36 #include "irq.h" 37 38 #ifndef CONFIG_X86_64 39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) 40 #else 41 #define mod_64(x, y) ((x) % (y)) 42 #endif 43 44 #define PRId64 "d" 45 #define PRIx64 "llx" 46 #define PRIu64 "u" 47 #define PRIo64 "o" 48 49 #define APIC_BUS_CYCLE_NS 1 50 51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ 52 #define apic_debug(fmt, arg...) 53 54 #define APIC_LVT_NUM 6 55 /* 14 is the version for Xeon and Pentium 8.4.8*/ 56 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) 57 #define LAPIC_MMIO_LENGTH (1 << 12) 58 /* followed define is not in apicdef.h */ 59 #define APIC_SHORT_MASK 0xc0000 60 #define APIC_DEST_NOSHORT 0x0 61 #define APIC_DEST_MASK 0x800 62 #define MAX_APIC_VECTOR 256 63 64 #define VEC_POS(v) ((v) & (32 - 1)) 65 #define REG_POS(v) (((v) >> 5) << 4) 66 67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off) 68 { 69 return *((u32 *) (apic->regs + reg_off)); 70 } 71 72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 73 { 74 *((u32 *) (apic->regs + reg_off)) = val; 75 } 76 77 static inline int apic_test_and_set_vector(int vec, void *bitmap) 78 { 79 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 80 } 81 82 static inline int apic_test_and_clear_vector(int vec, void *bitmap) 83 { 84 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 85 } 86 87 static inline void apic_set_vector(int vec, void *bitmap) 88 { 89 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 90 } 91 92 static inline void apic_clear_vector(int vec, void *bitmap) 93 { 94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 95 } 96 97 static inline int apic_hw_enabled(struct kvm_lapic *apic) 98 { 99 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 100 } 101 102 static inline int apic_sw_enabled(struct kvm_lapic *apic) 103 { 104 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; 105 } 106 107 static inline int apic_enabled(struct kvm_lapic *apic) 108 { 109 return apic_sw_enabled(apic) && apic_hw_enabled(apic); 110 } 111 112 #define LVT_MASK \ 113 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) 114 115 #define LINT_MASK \ 116 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ 117 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) 118 119 static inline int kvm_apic_id(struct kvm_lapic *apic) 120 { 121 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff; 122 } 123 124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) 125 { 126 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); 127 } 128 129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) 130 { 131 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; 132 } 133 134 static inline int apic_lvtt_period(struct kvm_lapic *apic) 135 { 136 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC; 137 } 138 139 static inline int apic_lvt_nmi_mode(u32 lvt_val) 140 { 141 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; 142 } 143 144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = { 145 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */ 146 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ 147 LVT_MASK | APIC_MODE_MASK, /* LVTPC */ 148 LINT_MASK, LINT_MASK, /* LVT0-1 */ 149 LVT_MASK /* LVTERR */ 150 }; 151 152 static int find_highest_vector(void *bitmap) 153 { 154 u32 *word = bitmap; 155 int word_offset = MAX_APIC_VECTOR >> 5; 156 157 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0)) 158 continue; 159 160 if (likely(!word_offset && !word[0])) 161 return -1; 162 else 163 return fls(word[word_offset << 2]) - 1 + (word_offset << 5); 164 } 165 166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic) 167 { 168 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR); 169 } 170 171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) 172 { 173 apic_clear_vector(vec, apic->regs + APIC_IRR); 174 } 175 176 static inline int apic_find_highest_irr(struct kvm_lapic *apic) 177 { 178 int result; 179 180 result = find_highest_vector(apic->regs + APIC_IRR); 181 ASSERT(result == -1 || result >= 16); 182 183 return result; 184 } 185 186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) 187 { 188 struct kvm_lapic *apic = vcpu->arch.apic; 189 int highest_irr; 190 191 if (!apic) 192 return 0; 193 highest_irr = apic_find_highest_irr(apic); 194 195 return highest_irr; 196 } 197 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); 198 199 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 200 int vector, int level, int trig_mode); 201 202 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq) 203 { 204 struct kvm_lapic *apic = vcpu->arch.apic; 205 206 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, 207 irq->level, irq->trig_mode); 208 } 209 210 static inline int apic_find_highest_isr(struct kvm_lapic *apic) 211 { 212 int result; 213 214 result = find_highest_vector(apic->regs + APIC_ISR); 215 ASSERT(result == -1 || result >= 16); 216 217 return result; 218 } 219 220 static void apic_update_ppr(struct kvm_lapic *apic) 221 { 222 u32 tpr, isrv, ppr; 223 int isr; 224 225 tpr = apic_get_reg(apic, APIC_TASKPRI); 226 isr = apic_find_highest_isr(apic); 227 isrv = (isr != -1) ? isr : 0; 228 229 if ((tpr & 0xf0) >= (isrv & 0xf0)) 230 ppr = tpr & 0xff; 231 else 232 ppr = isrv & 0xf0; 233 234 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", 235 apic, ppr, isr, isrv); 236 237 apic_set_reg(apic, APIC_PROCPRI, ppr); 238 } 239 240 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) 241 { 242 apic_set_reg(apic, APIC_TASKPRI, tpr); 243 apic_update_ppr(apic); 244 } 245 246 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest) 247 { 248 return dest == 0xff || kvm_apic_id(apic) == dest; 249 } 250 251 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda) 252 { 253 int result = 0; 254 u8 logical_id; 255 256 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR)); 257 258 switch (apic_get_reg(apic, APIC_DFR)) { 259 case APIC_DFR_FLAT: 260 if (logical_id & mda) 261 result = 1; 262 break; 263 case APIC_DFR_CLUSTER: 264 if (((logical_id >> 4) == (mda >> 0x4)) 265 && (logical_id & mda & 0xf)) 266 result = 1; 267 break; 268 default: 269 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n", 270 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR)); 271 break; 272 } 273 274 return result; 275 } 276 277 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 278 int short_hand, int dest, int dest_mode) 279 { 280 int result = 0; 281 struct kvm_lapic *target = vcpu->arch.apic; 282 283 apic_debug("target %p, source %p, dest 0x%x, " 284 "dest_mode 0x%x, short_hand 0x%x\n", 285 target, source, dest, dest_mode, short_hand); 286 287 ASSERT(!target); 288 switch (short_hand) { 289 case APIC_DEST_NOSHORT: 290 if (dest_mode == 0) 291 /* Physical mode. */ 292 result = kvm_apic_match_physical_addr(target, dest); 293 else 294 /* Logical mode. */ 295 result = kvm_apic_match_logical_addr(target, dest); 296 break; 297 case APIC_DEST_SELF: 298 result = (target == source); 299 break; 300 case APIC_DEST_ALLINC: 301 result = 1; 302 break; 303 case APIC_DEST_ALLBUT: 304 result = (target != source); 305 break; 306 default: 307 printk(KERN_WARNING "Bad dest shorthand value %x\n", 308 short_hand); 309 break; 310 } 311 312 return result; 313 } 314 315 /* 316 * Add a pending IRQ into lapic. 317 * Return 1 if successfully added and 0 if discarded. 318 */ 319 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 320 int vector, int level, int trig_mode) 321 { 322 int result = 0; 323 struct kvm_vcpu *vcpu = apic->vcpu; 324 325 switch (delivery_mode) { 326 case APIC_DM_LOWEST: 327 vcpu->arch.apic_arb_prio++; 328 case APIC_DM_FIXED: 329 /* FIXME add logic for vcpu on reset */ 330 if (unlikely(!apic_enabled(apic))) 331 break; 332 333 result = !apic_test_and_set_irr(vector, apic); 334 if (!result) { 335 if (trig_mode) 336 apic_debug("level trig mode repeatedly for " 337 "vector %d", vector); 338 break; 339 } 340 341 if (trig_mode) { 342 apic_debug("level trig mode for vector %d", vector); 343 apic_set_vector(vector, apic->regs + APIC_TMR); 344 } else 345 apic_clear_vector(vector, apic->regs + APIC_TMR); 346 kvm_vcpu_kick(vcpu); 347 break; 348 349 case APIC_DM_REMRD: 350 printk(KERN_DEBUG "Ignoring delivery mode 3\n"); 351 break; 352 353 case APIC_DM_SMI: 354 printk(KERN_DEBUG "Ignoring guest SMI\n"); 355 break; 356 357 case APIC_DM_NMI: 358 result = 1; 359 kvm_inject_nmi(vcpu); 360 kvm_vcpu_kick(vcpu); 361 break; 362 363 case APIC_DM_INIT: 364 if (level) { 365 result = 1; 366 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) 367 printk(KERN_DEBUG 368 "INIT on a runnable vcpu %d\n", 369 vcpu->vcpu_id); 370 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 371 kvm_vcpu_kick(vcpu); 372 } else { 373 apic_debug("Ignoring de-assert INIT to vcpu %d\n", 374 vcpu->vcpu_id); 375 } 376 break; 377 378 case APIC_DM_STARTUP: 379 apic_debug("SIPI to vcpu %d vector 0x%02x\n", 380 vcpu->vcpu_id, vector); 381 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 382 result = 1; 383 vcpu->arch.sipi_vector = vector; 384 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED; 385 kvm_vcpu_kick(vcpu); 386 } 387 break; 388 389 case APIC_DM_EXTINT: 390 /* 391 * Should only be called by kvm_apic_local_deliver() with LVT0, 392 * before NMI watchdog was enabled. Already handled by 393 * kvm_apic_accept_pic_intr(). 394 */ 395 break; 396 397 default: 398 printk(KERN_ERR "TODO: unsupported delivery mode %x\n", 399 delivery_mode); 400 break; 401 } 402 return result; 403 } 404 405 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) 406 { 407 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; 408 } 409 410 static void apic_set_eoi(struct kvm_lapic *apic) 411 { 412 int vector = apic_find_highest_isr(apic); 413 int trigger_mode; 414 /* 415 * Not every write EOI will has corresponding ISR, 416 * one example is when Kernel check timer on setup_IO_APIC 417 */ 418 if (vector == -1) 419 return; 420 421 apic_clear_vector(vector, apic->regs + APIC_ISR); 422 apic_update_ppr(apic); 423 424 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR)) 425 trigger_mode = IOAPIC_LEVEL_TRIG; 426 else 427 trigger_mode = IOAPIC_EDGE_TRIG; 428 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode); 429 } 430 431 static void apic_send_ipi(struct kvm_lapic *apic) 432 { 433 u32 icr_low = apic_get_reg(apic, APIC_ICR); 434 u32 icr_high = apic_get_reg(apic, APIC_ICR2); 435 struct kvm_lapic_irq irq; 436 437 irq.vector = icr_low & APIC_VECTOR_MASK; 438 irq.delivery_mode = icr_low & APIC_MODE_MASK; 439 irq.dest_mode = icr_low & APIC_DEST_MASK; 440 irq.level = icr_low & APIC_INT_ASSERT; 441 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; 442 irq.shorthand = icr_low & APIC_SHORT_MASK; 443 irq.dest_id = GET_APIC_DEST_FIELD(icr_high); 444 445 apic_debug("icr_high 0x%x, icr_low 0x%x, " 446 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " 447 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", 448 icr_high, icr_low, irq.shorthand, irq.dest_id, 449 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, 450 irq.vector); 451 452 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq); 453 } 454 455 static u32 apic_get_tmcct(struct kvm_lapic *apic) 456 { 457 ktime_t remaining; 458 s64 ns; 459 u32 tmcct; 460 461 ASSERT(apic != NULL); 462 463 /* if initial count is 0, current count should also be 0 */ 464 if (apic_get_reg(apic, APIC_TMICT) == 0) 465 return 0; 466 467 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer); 468 if (ktime_to_ns(remaining) < 0) 469 remaining = ktime_set(0, 0); 470 471 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); 472 tmcct = div64_u64(ns, 473 (APIC_BUS_CYCLE_NS * apic->divide_count)); 474 475 return tmcct; 476 } 477 478 static void __report_tpr_access(struct kvm_lapic *apic, bool write) 479 { 480 struct kvm_vcpu *vcpu = apic->vcpu; 481 struct kvm_run *run = vcpu->run; 482 483 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests); 484 run->tpr_access.rip = kvm_rip_read(vcpu); 485 run->tpr_access.is_write = write; 486 } 487 488 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) 489 { 490 if (apic->vcpu->arch.tpr_access_reporting) 491 __report_tpr_access(apic, write); 492 } 493 494 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) 495 { 496 u32 val = 0; 497 498 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler); 499 500 if (offset >= LAPIC_MMIO_LENGTH) 501 return 0; 502 503 switch (offset) { 504 case APIC_ARBPRI: 505 printk(KERN_WARNING "Access APIC ARBPRI register " 506 "which is for P6\n"); 507 break; 508 509 case APIC_TMCCT: /* Timer CCR */ 510 val = apic_get_tmcct(apic); 511 break; 512 513 case APIC_TASKPRI: 514 report_tpr_access(apic, false); 515 /* fall thru */ 516 default: 517 apic_update_ppr(apic); 518 val = apic_get_reg(apic, offset); 519 break; 520 } 521 522 return val; 523 } 524 525 static void apic_mmio_read(struct kvm_io_device *this, 526 gpa_t address, int len, void *data) 527 { 528 struct kvm_lapic *apic = (struct kvm_lapic *)this->private; 529 unsigned int offset = address - apic->base_address; 530 unsigned char alignment = offset & 0xf; 531 u32 result; 532 533 if ((alignment + len) > 4) { 534 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d", 535 (unsigned long)address, len); 536 return; 537 } 538 result = __apic_read(apic, offset & ~0xf); 539 540 switch (len) { 541 case 1: 542 case 2: 543 case 4: 544 memcpy(data, (char *)&result + alignment, len); 545 break; 546 default: 547 printk(KERN_ERR "Local APIC read with len = %x, " 548 "should be 1,2, or 4 instead\n", len); 549 break; 550 } 551 } 552 553 static void update_divide_count(struct kvm_lapic *apic) 554 { 555 u32 tmp1, tmp2, tdcr; 556 557 tdcr = apic_get_reg(apic, APIC_TDCR); 558 tmp1 = tdcr & 0xf; 559 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; 560 apic->divide_count = 0x1 << (tmp2 & 0x7); 561 562 apic_debug("timer divide count is 0x%x\n", 563 apic->divide_count); 564 } 565 566 static void start_apic_timer(struct kvm_lapic *apic) 567 { 568 ktime_t now = apic->lapic_timer.timer.base->get_time(); 569 570 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) * 571 APIC_BUS_CYCLE_NS * apic->divide_count; 572 atomic_set(&apic->lapic_timer.pending, 0); 573 574 if (!apic->lapic_timer.period) 575 return; 576 577 hrtimer_start(&apic->lapic_timer.timer, 578 ktime_add_ns(now, apic->lapic_timer.period), 579 HRTIMER_MODE_ABS); 580 581 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" 582 PRIx64 ", " 583 "timer initial count 0x%x, period %lldns, " 584 "expire @ 0x%016" PRIx64 ".\n", __func__, 585 APIC_BUS_CYCLE_NS, ktime_to_ns(now), 586 apic_get_reg(apic, APIC_TMICT), 587 apic->lapic_timer.period, 588 ktime_to_ns(ktime_add_ns(now, 589 apic->lapic_timer.period))); 590 } 591 592 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) 593 { 594 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0)); 595 596 if (apic_lvt_nmi_mode(lvt0_val)) { 597 if (!nmi_wd_enabled) { 598 apic_debug("Receive NMI setting on APIC_LVT0 " 599 "for cpu %d\n", apic->vcpu->vcpu_id); 600 apic->vcpu->kvm->arch.vapics_in_nmi_mode++; 601 } 602 } else if (nmi_wd_enabled) 603 apic->vcpu->kvm->arch.vapics_in_nmi_mode--; 604 } 605 606 static void apic_mmio_write(struct kvm_io_device *this, 607 gpa_t address, int len, const void *data) 608 { 609 struct kvm_lapic *apic = (struct kvm_lapic *)this->private; 610 unsigned int offset = address - apic->base_address; 611 unsigned char alignment = offset & 0xf; 612 u32 val; 613 614 /* 615 * APIC register must be aligned on 128-bits boundary. 616 * 32/64/128 bits registers must be accessed thru 32 bits. 617 * Refer SDM 8.4.1 618 */ 619 if (len != 4 || alignment) { 620 /* Don't shout loud, $infamous_os would cause only noise. */ 621 apic_debug("apic write: bad size=%d %lx\n", 622 len, (long)address); 623 return; 624 } 625 626 val = *(u32 *) data; 627 628 /* too common printing */ 629 if (offset != APIC_EOI) 630 apic_debug("%s: offset 0x%x with length 0x%x, and value is " 631 "0x%x\n", __func__, offset, len, val); 632 633 offset &= 0xff0; 634 635 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler); 636 637 switch (offset) { 638 case APIC_ID: /* Local APIC ID */ 639 apic_set_reg(apic, APIC_ID, val); 640 break; 641 642 case APIC_TASKPRI: 643 report_tpr_access(apic, true); 644 apic_set_tpr(apic, val & 0xff); 645 break; 646 647 case APIC_EOI: 648 apic_set_eoi(apic); 649 break; 650 651 case APIC_LDR: 652 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK); 653 break; 654 655 case APIC_DFR: 656 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); 657 break; 658 659 case APIC_SPIV: 660 apic_set_reg(apic, APIC_SPIV, val & 0x3ff); 661 if (!(val & APIC_SPIV_APIC_ENABLED)) { 662 int i; 663 u32 lvt_val; 664 665 for (i = 0; i < APIC_LVT_NUM; i++) { 666 lvt_val = apic_get_reg(apic, 667 APIC_LVTT + 0x10 * i); 668 apic_set_reg(apic, APIC_LVTT + 0x10 * i, 669 lvt_val | APIC_LVT_MASKED); 670 } 671 atomic_set(&apic->lapic_timer.pending, 0); 672 673 } 674 break; 675 676 case APIC_ICR: 677 /* No delay here, so we always clear the pending bit */ 678 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); 679 apic_send_ipi(apic); 680 break; 681 682 case APIC_ICR2: 683 apic_set_reg(apic, APIC_ICR2, val & 0xff000000); 684 break; 685 686 case APIC_LVT0: 687 apic_manage_nmi_watchdog(apic, val); 688 case APIC_LVTT: 689 case APIC_LVTTHMR: 690 case APIC_LVTPC: 691 case APIC_LVT1: 692 case APIC_LVTERR: 693 /* TODO: Check vector */ 694 if (!apic_sw_enabled(apic)) 695 val |= APIC_LVT_MASKED; 696 697 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4]; 698 apic_set_reg(apic, offset, val); 699 700 break; 701 702 case APIC_TMICT: 703 hrtimer_cancel(&apic->lapic_timer.timer); 704 apic_set_reg(apic, APIC_TMICT, val); 705 start_apic_timer(apic); 706 return; 707 708 case APIC_TDCR: 709 if (val & 4) 710 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val); 711 apic_set_reg(apic, APIC_TDCR, val); 712 update_divide_count(apic); 713 break; 714 715 default: 716 apic_debug("Local APIC Write to read-only register %x\n", 717 offset); 718 break; 719 } 720 721 } 722 723 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr, 724 int len, int size) 725 { 726 struct kvm_lapic *apic = (struct kvm_lapic *)this->private; 727 int ret = 0; 728 729 730 if (apic_hw_enabled(apic) && 731 (addr >= apic->base_address) && 732 (addr < (apic->base_address + LAPIC_MMIO_LENGTH))) 733 ret = 1; 734 735 return ret; 736 } 737 738 void kvm_free_lapic(struct kvm_vcpu *vcpu) 739 { 740 if (!vcpu->arch.apic) 741 return; 742 743 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer); 744 745 if (vcpu->arch.apic->regs_page) 746 __free_page(vcpu->arch.apic->regs_page); 747 748 kfree(vcpu->arch.apic); 749 } 750 751 /* 752 *---------------------------------------------------------------------- 753 * LAPIC interface 754 *---------------------------------------------------------------------- 755 */ 756 757 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) 758 { 759 struct kvm_lapic *apic = vcpu->arch.apic; 760 761 if (!apic) 762 return; 763 apic_set_tpr(apic, ((cr8 & 0x0f) << 4) 764 | (apic_get_reg(apic, APIC_TASKPRI) & 4)); 765 } 766 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr); 767 768 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) 769 { 770 struct kvm_lapic *apic = vcpu->arch.apic; 771 u64 tpr; 772 773 if (!apic) 774 return 0; 775 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI); 776 777 return (tpr & 0xf0) >> 4; 778 } 779 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8); 780 781 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) 782 { 783 struct kvm_lapic *apic = vcpu->arch.apic; 784 785 if (!apic) { 786 value |= MSR_IA32_APICBASE_BSP; 787 vcpu->arch.apic_base = value; 788 return; 789 } 790 if (apic->vcpu->vcpu_id) 791 value &= ~MSR_IA32_APICBASE_BSP; 792 793 vcpu->arch.apic_base = value; 794 apic->base_address = apic->vcpu->arch.apic_base & 795 MSR_IA32_APICBASE_BASE; 796 797 /* with FSB delivery interrupt, we can restart APIC functionality */ 798 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " 799 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); 800 801 } 802 803 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu) 804 { 805 return vcpu->arch.apic_base; 806 } 807 EXPORT_SYMBOL_GPL(kvm_lapic_get_base); 808 809 void kvm_lapic_reset(struct kvm_vcpu *vcpu) 810 { 811 struct kvm_lapic *apic; 812 int i; 813 814 apic_debug("%s\n", __func__); 815 816 ASSERT(vcpu); 817 apic = vcpu->arch.apic; 818 ASSERT(apic != NULL); 819 820 /* Stop the timer in case it's a reset to an active apic */ 821 hrtimer_cancel(&apic->lapic_timer.timer); 822 823 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24); 824 apic_set_reg(apic, APIC_LVR, APIC_VERSION); 825 826 for (i = 0; i < APIC_LVT_NUM; i++) 827 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); 828 apic_set_reg(apic, APIC_LVT0, 829 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); 830 831 apic_set_reg(apic, APIC_DFR, 0xffffffffU); 832 apic_set_reg(apic, APIC_SPIV, 0xff); 833 apic_set_reg(apic, APIC_TASKPRI, 0); 834 apic_set_reg(apic, APIC_LDR, 0); 835 apic_set_reg(apic, APIC_ESR, 0); 836 apic_set_reg(apic, APIC_ICR, 0); 837 apic_set_reg(apic, APIC_ICR2, 0); 838 apic_set_reg(apic, APIC_TDCR, 0); 839 apic_set_reg(apic, APIC_TMICT, 0); 840 for (i = 0; i < 8; i++) { 841 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); 842 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); 843 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); 844 } 845 update_divide_count(apic); 846 atomic_set(&apic->lapic_timer.pending, 0); 847 if (vcpu->vcpu_id == 0) 848 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP; 849 apic_update_ppr(apic); 850 851 vcpu->arch.apic_arb_prio = 0; 852 853 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr=" 854 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, 855 vcpu, kvm_apic_id(apic), 856 vcpu->arch.apic_base, apic->base_address); 857 } 858 EXPORT_SYMBOL_GPL(kvm_lapic_reset); 859 860 bool kvm_apic_present(struct kvm_vcpu *vcpu) 861 { 862 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic); 863 } 864 865 int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 866 { 867 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic); 868 } 869 EXPORT_SYMBOL_GPL(kvm_lapic_enabled); 870 871 /* 872 *---------------------------------------------------------------------- 873 * timer interface 874 *---------------------------------------------------------------------- 875 */ 876 877 static bool lapic_is_periodic(struct kvm_timer *ktimer) 878 { 879 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, 880 lapic_timer); 881 return apic_lvtt_period(apic); 882 } 883 884 int apic_has_pending_timer(struct kvm_vcpu *vcpu) 885 { 886 struct kvm_lapic *lapic = vcpu->arch.apic; 887 888 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT)) 889 return atomic_read(&lapic->lapic_timer.pending); 890 891 return 0; 892 } 893 894 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) 895 { 896 u32 reg = apic_get_reg(apic, lvt_type); 897 int vector, mode, trig_mode; 898 899 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { 900 vector = reg & APIC_VECTOR_MASK; 901 mode = reg & APIC_MODE_MASK; 902 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; 903 return __apic_accept_irq(apic, mode, vector, 1, trig_mode); 904 } 905 return 0; 906 } 907 908 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) 909 { 910 struct kvm_lapic *apic = vcpu->arch.apic; 911 912 if (apic) 913 kvm_apic_local_deliver(apic, APIC_LVT0); 914 } 915 916 static struct kvm_timer_ops lapic_timer_ops = { 917 .is_periodic = lapic_is_periodic, 918 }; 919 920 int kvm_create_lapic(struct kvm_vcpu *vcpu) 921 { 922 struct kvm_lapic *apic; 923 924 ASSERT(vcpu != NULL); 925 apic_debug("apic_init %d\n", vcpu->vcpu_id); 926 927 apic = kzalloc(sizeof(*apic), GFP_KERNEL); 928 if (!apic) 929 goto nomem; 930 931 vcpu->arch.apic = apic; 932 933 apic->regs_page = alloc_page(GFP_KERNEL); 934 if (apic->regs_page == NULL) { 935 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", 936 vcpu->vcpu_id); 937 goto nomem_free_apic; 938 } 939 apic->regs = page_address(apic->regs_page); 940 memset(apic->regs, 0, PAGE_SIZE); 941 apic->vcpu = vcpu; 942 943 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, 944 HRTIMER_MODE_ABS); 945 apic->lapic_timer.timer.function = kvm_timer_fn; 946 apic->lapic_timer.t_ops = &lapic_timer_ops; 947 apic->lapic_timer.kvm = vcpu->kvm; 948 apic->lapic_timer.vcpu_id = vcpu->vcpu_id; 949 950 apic->base_address = APIC_DEFAULT_PHYS_BASE; 951 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE; 952 953 kvm_lapic_reset(vcpu); 954 apic->dev.read = apic_mmio_read; 955 apic->dev.write = apic_mmio_write; 956 apic->dev.in_range = apic_mmio_range; 957 apic->dev.private = apic; 958 959 return 0; 960 nomem_free_apic: 961 kfree(apic); 962 nomem: 963 return -ENOMEM; 964 } 965 EXPORT_SYMBOL_GPL(kvm_create_lapic); 966 967 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) 968 { 969 struct kvm_lapic *apic = vcpu->arch.apic; 970 int highest_irr; 971 972 if (!apic || !apic_enabled(apic)) 973 return -1; 974 975 apic_update_ppr(apic); 976 highest_irr = apic_find_highest_irr(apic); 977 if ((highest_irr == -1) || 978 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI))) 979 return -1; 980 return highest_irr; 981 } 982 983 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) 984 { 985 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0); 986 int r = 0; 987 988 if (vcpu->vcpu_id == 0) { 989 if (!apic_hw_enabled(vcpu->arch.apic)) 990 r = 1; 991 if ((lvt0 & APIC_LVT_MASKED) == 0 && 992 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) 993 r = 1; 994 } 995 return r; 996 } 997 998 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) 999 { 1000 struct kvm_lapic *apic = vcpu->arch.apic; 1001 1002 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) { 1003 if (kvm_apic_local_deliver(apic, APIC_LVTT)) 1004 atomic_dec(&apic->lapic_timer.pending); 1005 } 1006 } 1007 1008 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) 1009 { 1010 int vector = kvm_apic_has_interrupt(vcpu); 1011 struct kvm_lapic *apic = vcpu->arch.apic; 1012 1013 if (vector == -1) 1014 return -1; 1015 1016 apic_set_vector(vector, apic->regs + APIC_ISR); 1017 apic_update_ppr(apic); 1018 apic_clear_irr(vector, apic); 1019 return vector; 1020 } 1021 1022 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu) 1023 { 1024 struct kvm_lapic *apic = vcpu->arch.apic; 1025 1026 apic->base_address = vcpu->arch.apic_base & 1027 MSR_IA32_APICBASE_BASE; 1028 apic_set_reg(apic, APIC_LVR, APIC_VERSION); 1029 apic_update_ppr(apic); 1030 hrtimer_cancel(&apic->lapic_timer.timer); 1031 update_divide_count(apic); 1032 start_apic_timer(apic); 1033 } 1034 1035 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) 1036 { 1037 struct kvm_lapic *apic = vcpu->arch.apic; 1038 struct hrtimer *timer; 1039 1040 if (!apic) 1041 return; 1042 1043 timer = &apic->lapic_timer.timer; 1044 if (hrtimer_cancel(timer)) 1045 hrtimer_start_expires(timer, HRTIMER_MODE_ABS); 1046 } 1047 1048 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) 1049 { 1050 u32 data; 1051 void *vapic; 1052 1053 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) 1054 return; 1055 1056 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); 1057 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)); 1058 kunmap_atomic(vapic, KM_USER0); 1059 1060 apic_set_tpr(vcpu->arch.apic, data & 0xff); 1061 } 1062 1063 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) 1064 { 1065 u32 data, tpr; 1066 int max_irr, max_isr; 1067 struct kvm_lapic *apic; 1068 void *vapic; 1069 1070 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) 1071 return; 1072 1073 apic = vcpu->arch.apic; 1074 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff; 1075 max_irr = apic_find_highest_irr(apic); 1076 if (max_irr < 0) 1077 max_irr = 0; 1078 max_isr = apic_find_highest_isr(apic); 1079 if (max_isr < 0) 1080 max_isr = 0; 1081 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); 1082 1083 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); 1084 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data; 1085 kunmap_atomic(vapic, KM_USER0); 1086 } 1087 1088 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) 1089 { 1090 if (!irqchip_in_kernel(vcpu->kvm)) 1091 return; 1092 1093 vcpu->arch.apic->vapic_addr = vapic_addr; 1094 } 1095