1 2 /* 3 * Local APIC virtualization 4 * 5 * Copyright (C) 2006 Qumranet, Inc. 6 * Copyright (C) 2007 Novell 7 * Copyright (C) 2007 Intel 8 * 9 * Authors: 10 * Dor Laor <dor.laor@qumranet.com> 11 * Gregory Haskins <ghaskins@novell.com> 12 * Yaozu (Eddie) Dong <eddie.dong@intel.com> 13 * 14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. 15 * 16 * This work is licensed under the terms of the GNU GPL, version 2. See 17 * the COPYING file in the top-level directory. 18 */ 19 20 #include <linux/kvm_host.h> 21 #include <linux/kvm.h> 22 #include <linux/mm.h> 23 #include <linux/highmem.h> 24 #include <linux/smp.h> 25 #include <linux/hrtimer.h> 26 #include <linux/io.h> 27 #include <linux/module.h> 28 #include <linux/math64.h> 29 #include <asm/processor.h> 30 #include <asm/msr.h> 31 #include <asm/page.h> 32 #include <asm/current.h> 33 #include <asm/apicdef.h> 34 #include <asm/atomic.h> 35 #include "irq.h" 36 37 #define PRId64 "d" 38 #define PRIx64 "llx" 39 #define PRIu64 "u" 40 #define PRIo64 "o" 41 42 #define APIC_BUS_CYCLE_NS 1 43 44 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ 45 #define apic_debug(fmt, arg...) 46 47 #define APIC_LVT_NUM 6 48 /* 14 is the version for Xeon and Pentium 8.4.8*/ 49 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) 50 #define LAPIC_MMIO_LENGTH (1 << 12) 51 /* followed define is not in apicdef.h */ 52 #define APIC_SHORT_MASK 0xc0000 53 #define APIC_DEST_NOSHORT 0x0 54 #define APIC_DEST_MASK 0x800 55 #define MAX_APIC_VECTOR 256 56 57 #define VEC_POS(v) ((v) & (32 - 1)) 58 #define REG_POS(v) (((v) >> 5) << 4) 59 60 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off) 61 { 62 return *((u32 *) (apic->regs + reg_off)); 63 } 64 65 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 66 { 67 *((u32 *) (apic->regs + reg_off)) = val; 68 } 69 70 static inline int apic_test_and_set_vector(int vec, void *bitmap) 71 { 72 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 73 } 74 75 static inline int apic_test_and_clear_vector(int vec, void *bitmap) 76 { 77 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 78 } 79 80 static inline void apic_set_vector(int vec, void *bitmap) 81 { 82 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 83 } 84 85 static inline void apic_clear_vector(int vec, void *bitmap) 86 { 87 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 88 } 89 90 static inline int apic_hw_enabled(struct kvm_lapic *apic) 91 { 92 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 93 } 94 95 static inline int apic_sw_enabled(struct kvm_lapic *apic) 96 { 97 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; 98 } 99 100 static inline int apic_enabled(struct kvm_lapic *apic) 101 { 102 return apic_sw_enabled(apic) && apic_hw_enabled(apic); 103 } 104 105 #define LVT_MASK \ 106 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) 107 108 #define LINT_MASK \ 109 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ 110 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) 111 112 static inline int kvm_apic_id(struct kvm_lapic *apic) 113 { 114 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff; 115 } 116 117 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) 118 { 119 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); 120 } 121 122 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) 123 { 124 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; 125 } 126 127 static inline int apic_lvtt_period(struct kvm_lapic *apic) 128 { 129 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC; 130 } 131 132 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = { 133 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */ 134 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ 135 LVT_MASK | APIC_MODE_MASK, /* LVTPC */ 136 LINT_MASK, LINT_MASK, /* LVT0-1 */ 137 LVT_MASK /* LVTERR */ 138 }; 139 140 static int find_highest_vector(void *bitmap) 141 { 142 u32 *word = bitmap; 143 int word_offset = MAX_APIC_VECTOR >> 5; 144 145 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0)) 146 continue; 147 148 if (likely(!word_offset && !word[0])) 149 return -1; 150 else 151 return fls(word[word_offset << 2]) - 1 + (word_offset << 5); 152 } 153 154 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic) 155 { 156 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR); 157 } 158 159 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) 160 { 161 apic_clear_vector(vec, apic->regs + APIC_IRR); 162 } 163 164 static inline int apic_find_highest_irr(struct kvm_lapic *apic) 165 { 166 int result; 167 168 result = find_highest_vector(apic->regs + APIC_IRR); 169 ASSERT(result == -1 || result >= 16); 170 171 return result; 172 } 173 174 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) 175 { 176 struct kvm_lapic *apic = vcpu->arch.apic; 177 int highest_irr; 178 179 if (!apic) 180 return 0; 181 highest_irr = apic_find_highest_irr(apic); 182 183 return highest_irr; 184 } 185 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); 186 187 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig) 188 { 189 struct kvm_lapic *apic = vcpu->arch.apic; 190 191 if (!apic_test_and_set_irr(vec, apic)) { 192 /* a new pending irq is set in IRR */ 193 if (trig) 194 apic_set_vector(vec, apic->regs + APIC_TMR); 195 else 196 apic_clear_vector(vec, apic->regs + APIC_TMR); 197 kvm_vcpu_kick(apic->vcpu); 198 return 1; 199 } 200 return 0; 201 } 202 203 static inline int apic_find_highest_isr(struct kvm_lapic *apic) 204 { 205 int result; 206 207 result = find_highest_vector(apic->regs + APIC_ISR); 208 ASSERT(result == -1 || result >= 16); 209 210 return result; 211 } 212 213 static void apic_update_ppr(struct kvm_lapic *apic) 214 { 215 u32 tpr, isrv, ppr; 216 int isr; 217 218 tpr = apic_get_reg(apic, APIC_TASKPRI); 219 isr = apic_find_highest_isr(apic); 220 isrv = (isr != -1) ? isr : 0; 221 222 if ((tpr & 0xf0) >= (isrv & 0xf0)) 223 ppr = tpr & 0xff; 224 else 225 ppr = isrv & 0xf0; 226 227 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", 228 apic, ppr, isr, isrv); 229 230 apic_set_reg(apic, APIC_PROCPRI, ppr); 231 } 232 233 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) 234 { 235 apic_set_reg(apic, APIC_TASKPRI, tpr); 236 apic_update_ppr(apic); 237 } 238 239 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest) 240 { 241 return kvm_apic_id(apic) == dest; 242 } 243 244 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda) 245 { 246 int result = 0; 247 u8 logical_id; 248 249 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR)); 250 251 switch (apic_get_reg(apic, APIC_DFR)) { 252 case APIC_DFR_FLAT: 253 if (logical_id & mda) 254 result = 1; 255 break; 256 case APIC_DFR_CLUSTER: 257 if (((logical_id >> 4) == (mda >> 0x4)) 258 && (logical_id & mda & 0xf)) 259 result = 1; 260 break; 261 default: 262 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n", 263 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR)); 264 break; 265 } 266 267 return result; 268 } 269 270 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 271 int short_hand, int dest, int dest_mode) 272 { 273 int result = 0; 274 struct kvm_lapic *target = vcpu->arch.apic; 275 276 apic_debug("target %p, source %p, dest 0x%x, " 277 "dest_mode 0x%x, short_hand 0x%x", 278 target, source, dest, dest_mode, short_hand); 279 280 ASSERT(!target); 281 switch (short_hand) { 282 case APIC_DEST_NOSHORT: 283 if (dest_mode == 0) { 284 /* Physical mode. */ 285 if ((dest == 0xFF) || (dest == kvm_apic_id(target))) 286 result = 1; 287 } else 288 /* Logical mode. */ 289 result = kvm_apic_match_logical_addr(target, dest); 290 break; 291 case APIC_DEST_SELF: 292 if (target == source) 293 result = 1; 294 break; 295 case APIC_DEST_ALLINC: 296 result = 1; 297 break; 298 case APIC_DEST_ALLBUT: 299 if (target != source) 300 result = 1; 301 break; 302 default: 303 printk(KERN_WARNING "Bad dest shorthand value %x\n", 304 short_hand); 305 break; 306 } 307 308 return result; 309 } 310 311 /* 312 * Add a pending IRQ into lapic. 313 * Return 1 if successfully added and 0 if discarded. 314 */ 315 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 316 int vector, int level, int trig_mode) 317 { 318 int orig_irr, result = 0; 319 struct kvm_vcpu *vcpu = apic->vcpu; 320 321 switch (delivery_mode) { 322 case APIC_DM_FIXED: 323 case APIC_DM_LOWEST: 324 /* FIXME add logic for vcpu on reset */ 325 if (unlikely(!apic_enabled(apic))) 326 break; 327 328 orig_irr = apic_test_and_set_irr(vector, apic); 329 if (orig_irr && trig_mode) { 330 apic_debug("level trig mode repeatedly for vector %d", 331 vector); 332 break; 333 } 334 335 if (trig_mode) { 336 apic_debug("level trig mode for vector %d", vector); 337 apic_set_vector(vector, apic->regs + APIC_TMR); 338 } else 339 apic_clear_vector(vector, apic->regs + APIC_TMR); 340 341 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) 342 kvm_vcpu_kick(vcpu); 343 else if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) { 344 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 345 if (waitqueue_active(&vcpu->wq)) 346 wake_up_interruptible(&vcpu->wq); 347 } 348 349 result = (orig_irr == 0); 350 break; 351 352 case APIC_DM_REMRD: 353 printk(KERN_DEBUG "Ignoring delivery mode 3\n"); 354 break; 355 356 case APIC_DM_SMI: 357 printk(KERN_DEBUG "Ignoring guest SMI\n"); 358 break; 359 360 case APIC_DM_NMI: 361 kvm_inject_nmi(vcpu); 362 break; 363 364 case APIC_DM_INIT: 365 if (level) { 366 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) 367 printk(KERN_DEBUG 368 "INIT on a runnable vcpu %d\n", 369 vcpu->vcpu_id); 370 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 371 kvm_vcpu_kick(vcpu); 372 } else { 373 printk(KERN_DEBUG 374 "Ignoring de-assert INIT to vcpu %d\n", 375 vcpu->vcpu_id); 376 } 377 378 break; 379 380 case APIC_DM_STARTUP: 381 printk(KERN_DEBUG "SIPI to vcpu %d vector 0x%02x\n", 382 vcpu->vcpu_id, vector); 383 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 384 vcpu->arch.sipi_vector = vector; 385 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED; 386 if (waitqueue_active(&vcpu->wq)) 387 wake_up_interruptible(&vcpu->wq); 388 } 389 break; 390 391 default: 392 printk(KERN_ERR "TODO: unsupported delivery mode %x\n", 393 delivery_mode); 394 break; 395 } 396 return result; 397 } 398 399 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector, 400 unsigned long bitmap) 401 { 402 int last; 403 int next; 404 struct kvm_lapic *apic = NULL; 405 406 last = kvm->arch.round_robin_prev_vcpu; 407 next = last; 408 409 do { 410 if (++next == KVM_MAX_VCPUS) 411 next = 0; 412 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap)) 413 continue; 414 apic = kvm->vcpus[next]->arch.apic; 415 if (apic && apic_enabled(apic)) 416 break; 417 apic = NULL; 418 } while (next != last); 419 kvm->arch.round_robin_prev_vcpu = next; 420 421 if (!apic) 422 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n"); 423 424 return apic; 425 } 426 427 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector, 428 unsigned long bitmap) 429 { 430 struct kvm_lapic *apic; 431 432 apic = kvm_apic_round_robin(kvm, vector, bitmap); 433 if (apic) 434 return apic->vcpu; 435 return NULL; 436 } 437 438 static void apic_set_eoi(struct kvm_lapic *apic) 439 { 440 int vector = apic_find_highest_isr(apic); 441 442 /* 443 * Not every write EOI will has corresponding ISR, 444 * one example is when Kernel check timer on setup_IO_APIC 445 */ 446 if (vector == -1) 447 return; 448 449 apic_clear_vector(vector, apic->regs + APIC_ISR); 450 apic_update_ppr(apic); 451 452 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR)) 453 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector); 454 } 455 456 static void apic_send_ipi(struct kvm_lapic *apic) 457 { 458 u32 icr_low = apic_get_reg(apic, APIC_ICR); 459 u32 icr_high = apic_get_reg(apic, APIC_ICR2); 460 461 unsigned int dest = GET_APIC_DEST_FIELD(icr_high); 462 unsigned int short_hand = icr_low & APIC_SHORT_MASK; 463 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG; 464 unsigned int level = icr_low & APIC_INT_ASSERT; 465 unsigned int dest_mode = icr_low & APIC_DEST_MASK; 466 unsigned int delivery_mode = icr_low & APIC_MODE_MASK; 467 unsigned int vector = icr_low & APIC_VECTOR_MASK; 468 469 struct kvm_vcpu *target; 470 struct kvm_vcpu *vcpu; 471 unsigned long lpr_map = 0; 472 int i; 473 474 apic_debug("icr_high 0x%x, icr_low 0x%x, " 475 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " 476 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", 477 icr_high, icr_low, short_hand, dest, 478 trig_mode, level, dest_mode, delivery_mode, vector); 479 480 for (i = 0; i < KVM_MAX_VCPUS; i++) { 481 vcpu = apic->vcpu->kvm->vcpus[i]; 482 if (!vcpu) 483 continue; 484 485 if (vcpu->arch.apic && 486 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) { 487 if (delivery_mode == APIC_DM_LOWEST) 488 set_bit(vcpu->vcpu_id, &lpr_map); 489 else 490 __apic_accept_irq(vcpu->arch.apic, delivery_mode, 491 vector, level, trig_mode); 492 } 493 } 494 495 if (delivery_mode == APIC_DM_LOWEST) { 496 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map); 497 if (target != NULL) 498 __apic_accept_irq(target->arch.apic, delivery_mode, 499 vector, level, trig_mode); 500 } 501 } 502 503 static u32 apic_get_tmcct(struct kvm_lapic *apic) 504 { 505 u64 counter_passed; 506 ktime_t passed, now; 507 u32 tmcct; 508 509 ASSERT(apic != NULL); 510 511 now = apic->timer.dev.base->get_time(); 512 tmcct = apic_get_reg(apic, APIC_TMICT); 513 514 /* if initial count is 0, current count should also be 0 */ 515 if (tmcct == 0) 516 return 0; 517 518 if (unlikely(ktime_to_ns(now) <= 519 ktime_to_ns(apic->timer.last_update))) { 520 /* Wrap around */ 521 passed = ktime_add(( { 522 (ktime_t) { 523 .tv64 = KTIME_MAX - 524 (apic->timer.last_update).tv64}; } 525 ), now); 526 apic_debug("time elapsed\n"); 527 } else 528 passed = ktime_sub(now, apic->timer.last_update); 529 530 counter_passed = div64_u64(ktime_to_ns(passed), 531 (APIC_BUS_CYCLE_NS * apic->timer.divide_count)); 532 533 if (counter_passed > tmcct) { 534 if (unlikely(!apic_lvtt_period(apic))) { 535 /* one-shot timers stick at 0 until reset */ 536 tmcct = 0; 537 } else { 538 /* 539 * periodic timers reset to APIC_TMICT when they 540 * hit 0. The while loop simulates this happening N 541 * times. (counter_passed %= tmcct) would also work, 542 * but might be slower or not work on 32-bit?? 543 */ 544 while (counter_passed > tmcct) 545 counter_passed -= tmcct; 546 tmcct -= counter_passed; 547 } 548 } else { 549 tmcct -= counter_passed; 550 } 551 552 return tmcct; 553 } 554 555 static void __report_tpr_access(struct kvm_lapic *apic, bool write) 556 { 557 struct kvm_vcpu *vcpu = apic->vcpu; 558 struct kvm_run *run = vcpu->run; 559 560 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests); 561 kvm_x86_ops->cache_regs(vcpu); 562 run->tpr_access.rip = vcpu->arch.rip; 563 run->tpr_access.is_write = write; 564 } 565 566 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) 567 { 568 if (apic->vcpu->arch.tpr_access_reporting) 569 __report_tpr_access(apic, write); 570 } 571 572 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) 573 { 574 u32 val = 0; 575 576 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler); 577 578 if (offset >= LAPIC_MMIO_LENGTH) 579 return 0; 580 581 switch (offset) { 582 case APIC_ARBPRI: 583 printk(KERN_WARNING "Access APIC ARBPRI register " 584 "which is for P6\n"); 585 break; 586 587 case APIC_TMCCT: /* Timer CCR */ 588 val = apic_get_tmcct(apic); 589 break; 590 591 case APIC_TASKPRI: 592 report_tpr_access(apic, false); 593 /* fall thru */ 594 default: 595 apic_update_ppr(apic); 596 val = apic_get_reg(apic, offset); 597 break; 598 } 599 600 return val; 601 } 602 603 static void apic_mmio_read(struct kvm_io_device *this, 604 gpa_t address, int len, void *data) 605 { 606 struct kvm_lapic *apic = (struct kvm_lapic *)this->private; 607 unsigned int offset = address - apic->base_address; 608 unsigned char alignment = offset & 0xf; 609 u32 result; 610 611 if ((alignment + len) > 4) { 612 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d", 613 (unsigned long)address, len); 614 return; 615 } 616 result = __apic_read(apic, offset & ~0xf); 617 618 switch (len) { 619 case 1: 620 case 2: 621 case 4: 622 memcpy(data, (char *)&result + alignment, len); 623 break; 624 default: 625 printk(KERN_ERR "Local APIC read with len = %x, " 626 "should be 1,2, or 4 instead\n", len); 627 break; 628 } 629 } 630 631 static void update_divide_count(struct kvm_lapic *apic) 632 { 633 u32 tmp1, tmp2, tdcr; 634 635 tdcr = apic_get_reg(apic, APIC_TDCR); 636 tmp1 = tdcr & 0xf; 637 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; 638 apic->timer.divide_count = 0x1 << (tmp2 & 0x7); 639 640 apic_debug("timer divide count is 0x%x\n", 641 apic->timer.divide_count); 642 } 643 644 static void start_apic_timer(struct kvm_lapic *apic) 645 { 646 ktime_t now = apic->timer.dev.base->get_time(); 647 648 apic->timer.last_update = now; 649 650 apic->timer.period = apic_get_reg(apic, APIC_TMICT) * 651 APIC_BUS_CYCLE_NS * apic->timer.divide_count; 652 atomic_set(&apic->timer.pending, 0); 653 654 if (!apic->timer.period) 655 return; 656 657 hrtimer_start(&apic->timer.dev, 658 ktime_add_ns(now, apic->timer.period), 659 HRTIMER_MODE_ABS); 660 661 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" 662 PRIx64 ", " 663 "timer initial count 0x%x, period %lldns, " 664 "expire @ 0x%016" PRIx64 ".\n", __func__, 665 APIC_BUS_CYCLE_NS, ktime_to_ns(now), 666 apic_get_reg(apic, APIC_TMICT), 667 apic->timer.period, 668 ktime_to_ns(ktime_add_ns(now, 669 apic->timer.period))); 670 } 671 672 static void apic_mmio_write(struct kvm_io_device *this, 673 gpa_t address, int len, const void *data) 674 { 675 struct kvm_lapic *apic = (struct kvm_lapic *)this->private; 676 unsigned int offset = address - apic->base_address; 677 unsigned char alignment = offset & 0xf; 678 u32 val; 679 680 /* 681 * APIC register must be aligned on 128-bits boundary. 682 * 32/64/128 bits registers must be accessed thru 32 bits. 683 * Refer SDM 8.4.1 684 */ 685 if (len != 4 || alignment) { 686 if (printk_ratelimit()) 687 printk(KERN_ERR "apic write: bad size=%d %lx\n", 688 len, (long)address); 689 return; 690 } 691 692 val = *(u32 *) data; 693 694 /* too common printing */ 695 if (offset != APIC_EOI) 696 apic_debug("%s: offset 0x%x with length 0x%x, and value is " 697 "0x%x\n", __func__, offset, len, val); 698 699 offset &= 0xff0; 700 701 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler); 702 703 switch (offset) { 704 case APIC_ID: /* Local APIC ID */ 705 apic_set_reg(apic, APIC_ID, val); 706 break; 707 708 case APIC_TASKPRI: 709 report_tpr_access(apic, true); 710 apic_set_tpr(apic, val & 0xff); 711 break; 712 713 case APIC_EOI: 714 apic_set_eoi(apic); 715 break; 716 717 case APIC_LDR: 718 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK); 719 break; 720 721 case APIC_DFR: 722 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); 723 break; 724 725 case APIC_SPIV: 726 apic_set_reg(apic, APIC_SPIV, val & 0x3ff); 727 if (!(val & APIC_SPIV_APIC_ENABLED)) { 728 int i; 729 u32 lvt_val; 730 731 for (i = 0; i < APIC_LVT_NUM; i++) { 732 lvt_val = apic_get_reg(apic, 733 APIC_LVTT + 0x10 * i); 734 apic_set_reg(apic, APIC_LVTT + 0x10 * i, 735 lvt_val | APIC_LVT_MASKED); 736 } 737 atomic_set(&apic->timer.pending, 0); 738 739 } 740 break; 741 742 case APIC_ICR: 743 /* No delay here, so we always clear the pending bit */ 744 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); 745 apic_send_ipi(apic); 746 break; 747 748 case APIC_ICR2: 749 apic_set_reg(apic, APIC_ICR2, val & 0xff000000); 750 break; 751 752 case APIC_LVTT: 753 case APIC_LVTTHMR: 754 case APIC_LVTPC: 755 case APIC_LVT0: 756 case APIC_LVT1: 757 case APIC_LVTERR: 758 /* TODO: Check vector */ 759 if (!apic_sw_enabled(apic)) 760 val |= APIC_LVT_MASKED; 761 762 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4]; 763 apic_set_reg(apic, offset, val); 764 765 break; 766 767 case APIC_TMICT: 768 hrtimer_cancel(&apic->timer.dev); 769 apic_set_reg(apic, APIC_TMICT, val); 770 start_apic_timer(apic); 771 return; 772 773 case APIC_TDCR: 774 if (val & 4) 775 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val); 776 apic_set_reg(apic, APIC_TDCR, val); 777 update_divide_count(apic); 778 break; 779 780 default: 781 apic_debug("Local APIC Write to read-only register %x\n", 782 offset); 783 break; 784 } 785 786 } 787 788 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr, 789 int len, int size) 790 { 791 struct kvm_lapic *apic = (struct kvm_lapic *)this->private; 792 int ret = 0; 793 794 795 if (apic_hw_enabled(apic) && 796 (addr >= apic->base_address) && 797 (addr < (apic->base_address + LAPIC_MMIO_LENGTH))) 798 ret = 1; 799 800 return ret; 801 } 802 803 void kvm_free_lapic(struct kvm_vcpu *vcpu) 804 { 805 if (!vcpu->arch.apic) 806 return; 807 808 hrtimer_cancel(&vcpu->arch.apic->timer.dev); 809 810 if (vcpu->arch.apic->regs_page) 811 __free_page(vcpu->arch.apic->regs_page); 812 813 kfree(vcpu->arch.apic); 814 } 815 816 /* 817 *---------------------------------------------------------------------- 818 * LAPIC interface 819 *---------------------------------------------------------------------- 820 */ 821 822 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) 823 { 824 struct kvm_lapic *apic = vcpu->arch.apic; 825 826 if (!apic) 827 return; 828 apic_set_tpr(apic, ((cr8 & 0x0f) << 4) 829 | (apic_get_reg(apic, APIC_TASKPRI) & 4)); 830 } 831 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr); 832 833 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) 834 { 835 struct kvm_lapic *apic = vcpu->arch.apic; 836 u64 tpr; 837 838 if (!apic) 839 return 0; 840 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI); 841 842 return (tpr & 0xf0) >> 4; 843 } 844 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8); 845 846 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) 847 { 848 struct kvm_lapic *apic = vcpu->arch.apic; 849 850 if (!apic) { 851 value |= MSR_IA32_APICBASE_BSP; 852 vcpu->arch.apic_base = value; 853 return; 854 } 855 if (apic->vcpu->vcpu_id) 856 value &= ~MSR_IA32_APICBASE_BSP; 857 858 vcpu->arch.apic_base = value; 859 apic->base_address = apic->vcpu->arch.apic_base & 860 MSR_IA32_APICBASE_BASE; 861 862 /* with FSB delivery interrupt, we can restart APIC functionality */ 863 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " 864 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); 865 866 } 867 868 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu) 869 { 870 return vcpu->arch.apic_base; 871 } 872 EXPORT_SYMBOL_GPL(kvm_lapic_get_base); 873 874 void kvm_lapic_reset(struct kvm_vcpu *vcpu) 875 { 876 struct kvm_lapic *apic; 877 int i; 878 879 apic_debug("%s\n", __func__); 880 881 ASSERT(vcpu); 882 apic = vcpu->arch.apic; 883 ASSERT(apic != NULL); 884 885 /* Stop the timer in case it's a reset to an active apic */ 886 hrtimer_cancel(&apic->timer.dev); 887 888 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24); 889 apic_set_reg(apic, APIC_LVR, APIC_VERSION); 890 891 for (i = 0; i < APIC_LVT_NUM; i++) 892 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); 893 apic_set_reg(apic, APIC_LVT0, 894 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); 895 896 apic_set_reg(apic, APIC_DFR, 0xffffffffU); 897 apic_set_reg(apic, APIC_SPIV, 0xff); 898 apic_set_reg(apic, APIC_TASKPRI, 0); 899 apic_set_reg(apic, APIC_LDR, 0); 900 apic_set_reg(apic, APIC_ESR, 0); 901 apic_set_reg(apic, APIC_ICR, 0); 902 apic_set_reg(apic, APIC_ICR2, 0); 903 apic_set_reg(apic, APIC_TDCR, 0); 904 apic_set_reg(apic, APIC_TMICT, 0); 905 for (i = 0; i < 8; i++) { 906 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); 907 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); 908 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); 909 } 910 update_divide_count(apic); 911 atomic_set(&apic->timer.pending, 0); 912 if (vcpu->vcpu_id == 0) 913 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP; 914 apic_update_ppr(apic); 915 916 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr=" 917 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, 918 vcpu, kvm_apic_id(apic), 919 vcpu->arch.apic_base, apic->base_address); 920 } 921 EXPORT_SYMBOL_GPL(kvm_lapic_reset); 922 923 int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 924 { 925 struct kvm_lapic *apic = vcpu->arch.apic; 926 int ret = 0; 927 928 if (!apic) 929 return 0; 930 ret = apic_enabled(apic); 931 932 return ret; 933 } 934 EXPORT_SYMBOL_GPL(kvm_lapic_enabled); 935 936 /* 937 *---------------------------------------------------------------------- 938 * timer interface 939 *---------------------------------------------------------------------- 940 */ 941 942 /* TODO: make sure __apic_timer_fn runs in current pCPU */ 943 static int __apic_timer_fn(struct kvm_lapic *apic) 944 { 945 int result = 0; 946 wait_queue_head_t *q = &apic->vcpu->wq; 947 948 if(!atomic_inc_and_test(&apic->timer.pending)) 949 set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests); 950 if (waitqueue_active(q)) { 951 apic->vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 952 wake_up_interruptible(q); 953 } 954 if (apic_lvtt_period(apic)) { 955 result = 1; 956 apic->timer.dev.expires = ktime_add_ns( 957 apic->timer.dev.expires, 958 apic->timer.period); 959 } 960 return result; 961 } 962 963 int apic_has_pending_timer(struct kvm_vcpu *vcpu) 964 { 965 struct kvm_lapic *lapic = vcpu->arch.apic; 966 967 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT)) 968 return atomic_read(&lapic->timer.pending); 969 970 return 0; 971 } 972 973 static int __inject_apic_timer_irq(struct kvm_lapic *apic) 974 { 975 int vector; 976 977 vector = apic_lvt_vector(apic, APIC_LVTT); 978 return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0); 979 } 980 981 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) 982 { 983 struct kvm_lapic *apic; 984 int restart_timer = 0; 985 986 apic = container_of(data, struct kvm_lapic, timer.dev); 987 988 restart_timer = __apic_timer_fn(apic); 989 990 if (restart_timer) 991 return HRTIMER_RESTART; 992 else 993 return HRTIMER_NORESTART; 994 } 995 996 int kvm_create_lapic(struct kvm_vcpu *vcpu) 997 { 998 struct kvm_lapic *apic; 999 1000 ASSERT(vcpu != NULL); 1001 apic_debug("apic_init %d\n", vcpu->vcpu_id); 1002 1003 apic = kzalloc(sizeof(*apic), GFP_KERNEL); 1004 if (!apic) 1005 goto nomem; 1006 1007 vcpu->arch.apic = apic; 1008 1009 apic->regs_page = alloc_page(GFP_KERNEL); 1010 if (apic->regs_page == NULL) { 1011 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", 1012 vcpu->vcpu_id); 1013 goto nomem_free_apic; 1014 } 1015 apic->regs = page_address(apic->regs_page); 1016 memset(apic->regs, 0, PAGE_SIZE); 1017 apic->vcpu = vcpu; 1018 1019 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 1020 apic->timer.dev.function = apic_timer_fn; 1021 apic->base_address = APIC_DEFAULT_PHYS_BASE; 1022 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE; 1023 1024 kvm_lapic_reset(vcpu); 1025 apic->dev.read = apic_mmio_read; 1026 apic->dev.write = apic_mmio_write; 1027 apic->dev.in_range = apic_mmio_range; 1028 apic->dev.private = apic; 1029 1030 return 0; 1031 nomem_free_apic: 1032 kfree(apic); 1033 nomem: 1034 return -ENOMEM; 1035 } 1036 EXPORT_SYMBOL_GPL(kvm_create_lapic); 1037 1038 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) 1039 { 1040 struct kvm_lapic *apic = vcpu->arch.apic; 1041 int highest_irr; 1042 1043 if (!apic || !apic_enabled(apic)) 1044 return -1; 1045 1046 apic_update_ppr(apic); 1047 highest_irr = apic_find_highest_irr(apic); 1048 if ((highest_irr == -1) || 1049 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI))) 1050 return -1; 1051 return highest_irr; 1052 } 1053 1054 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) 1055 { 1056 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0); 1057 int r = 0; 1058 1059 if (vcpu->vcpu_id == 0) { 1060 if (!apic_hw_enabled(vcpu->arch.apic)) 1061 r = 1; 1062 if ((lvt0 & APIC_LVT_MASKED) == 0 && 1063 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) 1064 r = 1; 1065 } 1066 return r; 1067 } 1068 1069 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) 1070 { 1071 struct kvm_lapic *apic = vcpu->arch.apic; 1072 1073 if (apic && apic_lvt_enabled(apic, APIC_LVTT) && 1074 atomic_read(&apic->timer.pending) > 0) { 1075 if (__inject_apic_timer_irq(apic)) 1076 atomic_dec(&apic->timer.pending); 1077 } 1078 } 1079 1080 void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec) 1081 { 1082 struct kvm_lapic *apic = vcpu->arch.apic; 1083 1084 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec) 1085 apic->timer.last_update = ktime_add_ns( 1086 apic->timer.last_update, 1087 apic->timer.period); 1088 } 1089 1090 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) 1091 { 1092 int vector = kvm_apic_has_interrupt(vcpu); 1093 struct kvm_lapic *apic = vcpu->arch.apic; 1094 1095 if (vector == -1) 1096 return -1; 1097 1098 apic_set_vector(vector, apic->regs + APIC_ISR); 1099 apic_update_ppr(apic); 1100 apic_clear_irr(vector, apic); 1101 return vector; 1102 } 1103 1104 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu) 1105 { 1106 struct kvm_lapic *apic = vcpu->arch.apic; 1107 1108 apic->base_address = vcpu->arch.apic_base & 1109 MSR_IA32_APICBASE_BASE; 1110 apic_set_reg(apic, APIC_LVR, APIC_VERSION); 1111 apic_update_ppr(apic); 1112 hrtimer_cancel(&apic->timer.dev); 1113 update_divide_count(apic); 1114 start_apic_timer(apic); 1115 } 1116 1117 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) 1118 { 1119 struct kvm_lapic *apic = vcpu->arch.apic; 1120 struct hrtimer *timer; 1121 1122 if (!apic) 1123 return; 1124 1125 timer = &apic->timer.dev; 1126 if (hrtimer_cancel(timer)) 1127 hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS); 1128 } 1129 1130 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) 1131 { 1132 u32 data; 1133 void *vapic; 1134 1135 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) 1136 return; 1137 1138 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); 1139 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)); 1140 kunmap_atomic(vapic, KM_USER0); 1141 1142 apic_set_tpr(vcpu->arch.apic, data & 0xff); 1143 } 1144 1145 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) 1146 { 1147 u32 data, tpr; 1148 int max_irr, max_isr; 1149 struct kvm_lapic *apic; 1150 void *vapic; 1151 1152 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) 1153 return; 1154 1155 apic = vcpu->arch.apic; 1156 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff; 1157 max_irr = apic_find_highest_irr(apic); 1158 if (max_irr < 0) 1159 max_irr = 0; 1160 max_isr = apic_find_highest_isr(apic); 1161 if (max_isr < 0) 1162 max_isr = 0; 1163 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); 1164 1165 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); 1166 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data; 1167 kunmap_atomic(vapic, KM_USER0); 1168 } 1169 1170 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) 1171 { 1172 if (!irqchip_in_kernel(vcpu->kvm)) 1173 return; 1174 1175 vcpu->arch.apic->vapic_addr = vapic_addr; 1176 } 1177