1 #ifndef ASM_KVM_CACHE_REGS_H 2 #define ASM_KVM_CACHE_REGS_H 3 4 #define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS 5 #define KVM_POSSIBLE_CR4_GUEST_BITS \ 6 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 7 | X86_CR4_OSXMMEXCPT | X86_CR4_PGE) 8 9 static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, 10 enum kvm_reg reg) 11 { 12 if (!test_bit(reg, (unsigned long *)&vcpu->arch.regs_avail)) 13 kvm_x86_ops->cache_reg(vcpu, reg); 14 15 return vcpu->arch.regs[reg]; 16 } 17 18 static inline void kvm_register_write(struct kvm_vcpu *vcpu, 19 enum kvm_reg reg, 20 unsigned long val) 21 { 22 vcpu->arch.regs[reg] = val; 23 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty); 24 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); 25 } 26 27 static inline unsigned long kvm_rip_read(struct kvm_vcpu *vcpu) 28 { 29 return kvm_register_read(vcpu, VCPU_REGS_RIP); 30 } 31 32 static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val) 33 { 34 kvm_register_write(vcpu, VCPU_REGS_RIP, val); 35 } 36 37 static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index) 38 { 39 if (!test_bit(VCPU_EXREG_PDPTR, 40 (unsigned long *)&vcpu->arch.regs_avail)) 41 kvm_x86_ops->cache_reg(vcpu, VCPU_EXREG_PDPTR); 42 43 return vcpu->arch.pdptrs[index]; 44 } 45 46 static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask) 47 { 48 ulong tmask = mask & KVM_POSSIBLE_CR0_GUEST_BITS; 49 if (tmask & vcpu->arch.cr0_guest_owned_bits) 50 kvm_x86_ops->decache_cr0_guest_bits(vcpu); 51 return vcpu->arch.cr0 & mask; 52 } 53 54 static inline ulong kvm_read_cr0(struct kvm_vcpu *vcpu) 55 { 56 return kvm_read_cr0_bits(vcpu, ~0UL); 57 } 58 59 static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask) 60 { 61 ulong tmask = mask & KVM_POSSIBLE_CR4_GUEST_BITS; 62 if (tmask & vcpu->arch.cr4_guest_owned_bits) 63 kvm_x86_ops->decache_cr4_guest_bits(vcpu); 64 return vcpu->arch.cr4 & mask; 65 } 66 67 static inline ulong kvm_read_cr4(struct kvm_vcpu *vcpu) 68 { 69 return kvm_read_cr4_bits(vcpu, ~0UL); 70 } 71 72 #endif 73