1 /* 2 * 8259 interrupt controller emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2007 Intel Corporation 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * Authors: 25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com> 26 * Port from Qemu. 27 */ 28 #include <linux/mm.h> 29 #include <linux/bitops.h> 30 #include "irq.h" 31 32 #include <linux/kvm_host.h> 33 34 static void pic_lock(struct kvm_pic *s) 35 __acquires(&s->lock) 36 { 37 spin_lock(&s->lock); 38 } 39 40 static void pic_unlock(struct kvm_pic *s) 41 __releases(&s->lock) 42 { 43 struct kvm *kvm = s->kvm; 44 unsigned acks = s->pending_acks; 45 bool wakeup = s->wakeup_needed; 46 struct kvm_vcpu *vcpu; 47 48 s->pending_acks = 0; 49 s->wakeup_needed = false; 50 51 spin_unlock(&s->lock); 52 53 while (acks) { 54 kvm_notify_acked_irq(kvm, SELECT_PIC(__ffs(acks)), 55 __ffs(acks)); 56 acks &= acks - 1; 57 } 58 59 if (wakeup) { 60 vcpu = s->kvm->vcpus[0]; 61 if (vcpu) 62 kvm_vcpu_kick(vcpu); 63 } 64 } 65 66 static void pic_clear_isr(struct kvm_kpic_state *s, int irq) 67 { 68 s->isr &= ~(1 << irq); 69 s->isr_ack |= (1 << irq); 70 } 71 72 void kvm_pic_clear_isr_ack(struct kvm *kvm) 73 { 74 struct kvm_pic *s = pic_irqchip(kvm); 75 pic_lock(s); 76 s->pics[0].isr_ack = 0xff; 77 s->pics[1].isr_ack = 0xff; 78 pic_unlock(s); 79 } 80 81 /* 82 * set irq level. If an edge is detected, then the IRR is set to 1 83 */ 84 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level) 85 { 86 int mask, ret = 1; 87 mask = 1 << irq; 88 if (s->elcr & mask) /* level triggered */ 89 if (level) { 90 ret = !(s->irr & mask); 91 s->irr |= mask; 92 s->last_irr |= mask; 93 } else { 94 s->irr &= ~mask; 95 s->last_irr &= ~mask; 96 } 97 else /* edge triggered */ 98 if (level) { 99 if ((s->last_irr & mask) == 0) { 100 ret = !(s->irr & mask); 101 s->irr |= mask; 102 } 103 s->last_irr |= mask; 104 } else 105 s->last_irr &= ~mask; 106 107 return (s->imr & mask) ? -1 : ret; 108 } 109 110 /* 111 * return the highest priority found in mask (highest = smallest 112 * number). Return 8 if no irq 113 */ 114 static inline int get_priority(struct kvm_kpic_state *s, int mask) 115 { 116 int priority; 117 if (mask == 0) 118 return 8; 119 priority = 0; 120 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) 121 priority++; 122 return priority; 123 } 124 125 /* 126 * return the pic wanted interrupt. return -1 if none 127 */ 128 static int pic_get_irq(struct kvm_kpic_state *s) 129 { 130 int mask, cur_priority, priority; 131 132 mask = s->irr & ~s->imr; 133 priority = get_priority(s, mask); 134 if (priority == 8) 135 return -1; 136 /* 137 * compute current priority. If special fully nested mode on the 138 * master, the IRQ coming from the slave is not taken into account 139 * for the priority computation. 140 */ 141 mask = s->isr; 142 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) 143 mask &= ~(1 << 2); 144 cur_priority = get_priority(s, mask); 145 if (priority < cur_priority) 146 /* 147 * higher priority found: an irq should be generated 148 */ 149 return (priority + s->priority_add) & 7; 150 else 151 return -1; 152 } 153 154 /* 155 * raise irq to CPU if necessary. must be called every time the active 156 * irq may change 157 */ 158 static void pic_update_irq(struct kvm_pic *s) 159 { 160 int irq2, irq; 161 162 irq2 = pic_get_irq(&s->pics[1]); 163 if (irq2 >= 0) { 164 /* 165 * if irq request by slave pic, signal master PIC 166 */ 167 pic_set_irq1(&s->pics[0], 2, 1); 168 pic_set_irq1(&s->pics[0], 2, 0); 169 } 170 irq = pic_get_irq(&s->pics[0]); 171 if (irq >= 0) 172 s->irq_request(s->irq_request_opaque, 1); 173 else 174 s->irq_request(s->irq_request_opaque, 0); 175 } 176 177 void kvm_pic_update_irq(struct kvm_pic *s) 178 { 179 pic_lock(s); 180 pic_update_irq(s); 181 pic_unlock(s); 182 } 183 184 int kvm_pic_set_irq(void *opaque, int irq, int level) 185 { 186 struct kvm_pic *s = opaque; 187 int ret = -1; 188 189 pic_lock(s); 190 if (irq >= 0 && irq < PIC_NUM_PINS) { 191 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); 192 pic_update_irq(s); 193 } 194 pic_unlock(s); 195 196 return ret; 197 } 198 199 /* 200 * acknowledge interrupt 'irq' 201 */ 202 static inline void pic_intack(struct kvm_kpic_state *s, int irq) 203 { 204 s->isr |= 1 << irq; 205 if (s->auto_eoi) { 206 if (s->rotate_on_auto_eoi) 207 s->priority_add = (irq + 1) & 7; 208 pic_clear_isr(s, irq); 209 } 210 /* 211 * We don't clear a level sensitive interrupt here 212 */ 213 if (!(s->elcr & (1 << irq))) 214 s->irr &= ~(1 << irq); 215 } 216 217 int kvm_pic_read_irq(struct kvm *kvm) 218 { 219 int irq, irq2, intno; 220 struct kvm_pic *s = pic_irqchip(kvm); 221 222 pic_lock(s); 223 irq = pic_get_irq(&s->pics[0]); 224 if (irq >= 0) { 225 pic_intack(&s->pics[0], irq); 226 if (irq == 2) { 227 irq2 = pic_get_irq(&s->pics[1]); 228 if (irq2 >= 0) 229 pic_intack(&s->pics[1], irq2); 230 else 231 /* 232 * spurious IRQ on slave controller 233 */ 234 irq2 = 7; 235 intno = s->pics[1].irq_base + irq2; 236 irq = irq2 + 8; 237 } else 238 intno = s->pics[0].irq_base + irq; 239 } else { 240 /* 241 * spurious IRQ on host controller 242 */ 243 irq = 7; 244 intno = s->pics[0].irq_base + irq; 245 } 246 pic_update_irq(s); 247 pic_unlock(s); 248 kvm_notify_acked_irq(kvm, SELECT_PIC(irq), irq); 249 250 return intno; 251 } 252 253 void kvm_pic_reset(struct kvm_kpic_state *s) 254 { 255 int irq, irqbase, n; 256 struct kvm *kvm = s->pics_state->irq_request_opaque; 257 struct kvm_vcpu *vcpu0 = kvm->vcpus[0]; 258 259 if (s == &s->pics_state->pics[0]) 260 irqbase = 0; 261 else 262 irqbase = 8; 263 264 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) { 265 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0)) 266 if (s->irr & (1 << irq) || s->isr & (1 << irq)) { 267 n = irq + irqbase; 268 s->pics_state->pending_acks |= 1 << n; 269 } 270 } 271 s->last_irr = 0; 272 s->irr = 0; 273 s->imr = 0; 274 s->isr = 0; 275 s->isr_ack = 0xff; 276 s->priority_add = 0; 277 s->irq_base = 0; 278 s->read_reg_select = 0; 279 s->poll = 0; 280 s->special_mask = 0; 281 s->init_state = 0; 282 s->auto_eoi = 0; 283 s->rotate_on_auto_eoi = 0; 284 s->special_fully_nested_mode = 0; 285 s->init4 = 0; 286 } 287 288 static void pic_ioport_write(void *opaque, u32 addr, u32 val) 289 { 290 struct kvm_kpic_state *s = opaque; 291 int priority, cmd, irq; 292 293 addr &= 1; 294 if (addr == 0) { 295 if (val & 0x10) { 296 kvm_pic_reset(s); /* init */ 297 /* 298 * deassert a pending interrupt 299 */ 300 s->pics_state->irq_request(s->pics_state-> 301 irq_request_opaque, 0); 302 s->init_state = 1; 303 s->init4 = val & 1; 304 if (val & 0x02) 305 printk(KERN_ERR "single mode not supported"); 306 if (val & 0x08) 307 printk(KERN_ERR 308 "level sensitive irq not supported"); 309 } else if (val & 0x08) { 310 if (val & 0x04) 311 s->poll = 1; 312 if (val & 0x02) 313 s->read_reg_select = val & 1; 314 if (val & 0x40) 315 s->special_mask = (val >> 5) & 1; 316 } else { 317 cmd = val >> 5; 318 switch (cmd) { 319 case 0: 320 case 4: 321 s->rotate_on_auto_eoi = cmd >> 2; 322 break; 323 case 1: /* end of interrupt */ 324 case 5: 325 priority = get_priority(s, s->isr); 326 if (priority != 8) { 327 irq = (priority + s->priority_add) & 7; 328 pic_clear_isr(s, irq); 329 if (cmd == 5) 330 s->priority_add = (irq + 1) & 7; 331 pic_update_irq(s->pics_state); 332 } 333 break; 334 case 3: 335 irq = val & 7; 336 pic_clear_isr(s, irq); 337 pic_update_irq(s->pics_state); 338 break; 339 case 6: 340 s->priority_add = (val + 1) & 7; 341 pic_update_irq(s->pics_state); 342 break; 343 case 7: 344 irq = val & 7; 345 s->priority_add = (irq + 1) & 7; 346 pic_clear_isr(s, irq); 347 pic_update_irq(s->pics_state); 348 break; 349 default: 350 break; /* no operation */ 351 } 352 } 353 } else 354 switch (s->init_state) { 355 case 0: /* normal mode */ 356 s->imr = val; 357 pic_update_irq(s->pics_state); 358 break; 359 case 1: 360 s->irq_base = val & 0xf8; 361 s->init_state = 2; 362 break; 363 case 2: 364 if (s->init4) 365 s->init_state = 3; 366 else 367 s->init_state = 0; 368 break; 369 case 3: 370 s->special_fully_nested_mode = (val >> 4) & 1; 371 s->auto_eoi = (val >> 1) & 1; 372 s->init_state = 0; 373 break; 374 } 375 } 376 377 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1) 378 { 379 int ret; 380 381 ret = pic_get_irq(s); 382 if (ret >= 0) { 383 if (addr1 >> 7) { 384 s->pics_state->pics[0].isr &= ~(1 << 2); 385 s->pics_state->pics[0].irr &= ~(1 << 2); 386 } 387 s->irr &= ~(1 << ret); 388 pic_clear_isr(s, ret); 389 if (addr1 >> 7 || ret != 2) 390 pic_update_irq(s->pics_state); 391 } else { 392 ret = 0x07; 393 pic_update_irq(s->pics_state); 394 } 395 396 return ret; 397 } 398 399 static u32 pic_ioport_read(void *opaque, u32 addr1) 400 { 401 struct kvm_kpic_state *s = opaque; 402 unsigned int addr; 403 int ret; 404 405 addr = addr1; 406 addr &= 1; 407 if (s->poll) { 408 ret = pic_poll_read(s, addr1); 409 s->poll = 0; 410 } else 411 if (addr == 0) 412 if (s->read_reg_select) 413 ret = s->isr; 414 else 415 ret = s->irr; 416 else 417 ret = s->imr; 418 return ret; 419 } 420 421 static void elcr_ioport_write(void *opaque, u32 addr, u32 val) 422 { 423 struct kvm_kpic_state *s = opaque; 424 s->elcr = val & s->elcr_mask; 425 } 426 427 static u32 elcr_ioport_read(void *opaque, u32 addr1) 428 { 429 struct kvm_kpic_state *s = opaque; 430 return s->elcr; 431 } 432 433 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr, 434 int len, int is_write) 435 { 436 switch (addr) { 437 case 0x20: 438 case 0x21: 439 case 0xa0: 440 case 0xa1: 441 case 0x4d0: 442 case 0x4d1: 443 return 1; 444 default: 445 return 0; 446 } 447 } 448 449 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev) 450 { 451 return container_of(dev, struct kvm_pic, dev); 452 } 453 454 static void picdev_write(struct kvm_io_device *this, 455 gpa_t addr, int len, const void *val) 456 { 457 struct kvm_pic *s = to_pic(this); 458 unsigned char data = *(unsigned char *)val; 459 460 if (len != 1) { 461 if (printk_ratelimit()) 462 printk(KERN_ERR "PIC: non byte write\n"); 463 return; 464 } 465 pic_lock(s); 466 switch (addr) { 467 case 0x20: 468 case 0x21: 469 case 0xa0: 470 case 0xa1: 471 pic_ioport_write(&s->pics[addr >> 7], addr, data); 472 break; 473 case 0x4d0: 474 case 0x4d1: 475 elcr_ioport_write(&s->pics[addr & 1], addr, data); 476 break; 477 } 478 pic_unlock(s); 479 } 480 481 static void picdev_read(struct kvm_io_device *this, 482 gpa_t addr, int len, void *val) 483 { 484 struct kvm_pic *s = to_pic(this); 485 unsigned char data = 0; 486 487 if (len != 1) { 488 if (printk_ratelimit()) 489 printk(KERN_ERR "PIC: non byte read\n"); 490 return; 491 } 492 pic_lock(s); 493 switch (addr) { 494 case 0x20: 495 case 0x21: 496 case 0xa0: 497 case 0xa1: 498 data = pic_ioport_read(&s->pics[addr >> 7], addr); 499 break; 500 case 0x4d0: 501 case 0x4d1: 502 data = elcr_ioport_read(&s->pics[addr & 1], addr); 503 break; 504 } 505 *(unsigned char *)val = data; 506 pic_unlock(s); 507 } 508 509 /* 510 * callback when PIC0 irq status changed 511 */ 512 static void pic_irq_request(void *opaque, int level) 513 { 514 struct kvm *kvm = opaque; 515 struct kvm_vcpu *vcpu = kvm->vcpus[0]; 516 struct kvm_pic *s = pic_irqchip(kvm); 517 int irq = pic_get_irq(&s->pics[0]); 518 519 s->output = level; 520 if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) { 521 s->pics[0].isr_ack &= ~(1 << irq); 522 s->wakeup_needed = true; 523 } 524 } 525 526 static const struct kvm_io_device_ops picdev_ops = { 527 .read = picdev_read, 528 .write = picdev_write, 529 .in_range = picdev_in_range, 530 }; 531 532 struct kvm_pic *kvm_create_pic(struct kvm *kvm) 533 { 534 struct kvm_pic *s; 535 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL); 536 if (!s) 537 return NULL; 538 spin_lock_init(&s->lock); 539 s->kvm = kvm; 540 s->pics[0].elcr_mask = 0xf8; 541 s->pics[1].elcr_mask = 0xde; 542 s->irq_request = pic_irq_request; 543 s->irq_request_opaque = kvm; 544 s->pics[0].pics_state = s; 545 s->pics[1].pics_state = s; 546 547 /* 548 * Initialize PIO device 549 */ 550 kvm_iodevice_init(&s->dev, &picdev_ops); 551 kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev); 552 return s; 553 } 554