1 /* 2 * 8259 interrupt controller emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2007 Intel Corporation 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * Authors: 25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com> 26 * Port from Qemu. 27 */ 28 #include <linux/mm.h> 29 #include <linux/bitops.h> 30 #include "irq.h" 31 32 #include <linux/kvm_host.h> 33 #include "trace.h" 34 35 static void pic_clear_isr(struct kvm_kpic_state *s, int irq) 36 { 37 s->isr &= ~(1 << irq); 38 s->isr_ack |= (1 << irq); 39 if (s != &s->pics_state->pics[0]) 40 irq += 8; 41 kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq); 42 } 43 44 void kvm_pic_clear_isr_ack(struct kvm *kvm) 45 { 46 struct kvm_pic *s = pic_irqchip(kvm); 47 spin_lock(&s->lock); 48 s->pics[0].isr_ack = 0xff; 49 s->pics[1].isr_ack = 0xff; 50 spin_unlock(&s->lock); 51 } 52 53 /* 54 * set irq level. If an edge is detected, then the IRR is set to 1 55 */ 56 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level) 57 { 58 int mask, ret = 1; 59 mask = 1 << irq; 60 if (s->elcr & mask) /* level triggered */ 61 if (level) { 62 ret = !(s->irr & mask); 63 s->irr |= mask; 64 s->last_irr |= mask; 65 } else { 66 s->irr &= ~mask; 67 s->last_irr &= ~mask; 68 } 69 else /* edge triggered */ 70 if (level) { 71 if ((s->last_irr & mask) == 0) { 72 ret = !(s->irr & mask); 73 s->irr |= mask; 74 } 75 s->last_irr |= mask; 76 } else 77 s->last_irr &= ~mask; 78 79 return (s->imr & mask) ? -1 : ret; 80 } 81 82 /* 83 * return the highest priority found in mask (highest = smallest 84 * number). Return 8 if no irq 85 */ 86 static inline int get_priority(struct kvm_kpic_state *s, int mask) 87 { 88 int priority; 89 if (mask == 0) 90 return 8; 91 priority = 0; 92 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) 93 priority++; 94 return priority; 95 } 96 97 /* 98 * return the pic wanted interrupt. return -1 if none 99 */ 100 static int pic_get_irq(struct kvm_kpic_state *s) 101 { 102 int mask, cur_priority, priority; 103 104 mask = s->irr & ~s->imr; 105 priority = get_priority(s, mask); 106 if (priority == 8) 107 return -1; 108 /* 109 * compute current priority. If special fully nested mode on the 110 * master, the IRQ coming from the slave is not taken into account 111 * for the priority computation. 112 */ 113 mask = s->isr; 114 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) 115 mask &= ~(1 << 2); 116 cur_priority = get_priority(s, mask); 117 if (priority < cur_priority) 118 /* 119 * higher priority found: an irq should be generated 120 */ 121 return (priority + s->priority_add) & 7; 122 else 123 return -1; 124 } 125 126 /* 127 * raise irq to CPU if necessary. must be called every time the active 128 * irq may change 129 */ 130 static void pic_update_irq(struct kvm_pic *s) 131 { 132 int irq2, irq; 133 134 irq2 = pic_get_irq(&s->pics[1]); 135 if (irq2 >= 0) { 136 /* 137 * if irq request by slave pic, signal master PIC 138 */ 139 pic_set_irq1(&s->pics[0], 2, 1); 140 pic_set_irq1(&s->pics[0], 2, 0); 141 } 142 irq = pic_get_irq(&s->pics[0]); 143 if (irq >= 0) 144 s->irq_request(s->irq_request_opaque, 1); 145 else 146 s->irq_request(s->irq_request_opaque, 0); 147 } 148 149 void kvm_pic_update_irq(struct kvm_pic *s) 150 { 151 spin_lock(&s->lock); 152 pic_update_irq(s); 153 spin_unlock(&s->lock); 154 } 155 156 int kvm_pic_set_irq(void *opaque, int irq, int level) 157 { 158 struct kvm_pic *s = opaque; 159 int ret = -1; 160 161 spin_lock(&s->lock); 162 if (irq >= 0 && irq < PIC_NUM_PINS) { 163 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); 164 pic_update_irq(s); 165 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr, 166 s->pics[irq >> 3].imr, ret == 0); 167 } 168 spin_unlock(&s->lock); 169 170 return ret; 171 } 172 173 /* 174 * acknowledge interrupt 'irq' 175 */ 176 static inline void pic_intack(struct kvm_kpic_state *s, int irq) 177 { 178 s->isr |= 1 << irq; 179 if (s->auto_eoi) { 180 if (s->rotate_on_auto_eoi) 181 s->priority_add = (irq + 1) & 7; 182 pic_clear_isr(s, irq); 183 } 184 /* 185 * We don't clear a level sensitive interrupt here 186 */ 187 if (!(s->elcr & (1 << irq))) 188 s->irr &= ~(1 << irq); 189 } 190 191 int kvm_pic_read_irq(struct kvm *kvm) 192 { 193 int irq, irq2, intno; 194 struct kvm_pic *s = pic_irqchip(kvm); 195 196 spin_lock(&s->lock); 197 irq = pic_get_irq(&s->pics[0]); 198 if (irq >= 0) { 199 pic_intack(&s->pics[0], irq); 200 if (irq == 2) { 201 irq2 = pic_get_irq(&s->pics[1]); 202 if (irq2 >= 0) 203 pic_intack(&s->pics[1], irq2); 204 else 205 /* 206 * spurious IRQ on slave controller 207 */ 208 irq2 = 7; 209 intno = s->pics[1].irq_base + irq2; 210 irq = irq2 + 8; 211 } else 212 intno = s->pics[0].irq_base + irq; 213 } else { 214 /* 215 * spurious IRQ on host controller 216 */ 217 irq = 7; 218 intno = s->pics[0].irq_base + irq; 219 } 220 pic_update_irq(s); 221 spin_unlock(&s->lock); 222 223 return intno; 224 } 225 226 void kvm_pic_reset(struct kvm_kpic_state *s) 227 { 228 int irq, irqbase, n; 229 struct kvm *kvm = s->pics_state->irq_request_opaque; 230 struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu; 231 232 if (s == &s->pics_state->pics[0]) 233 irqbase = 0; 234 else 235 irqbase = 8; 236 237 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) { 238 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0)) 239 if (s->irr & (1 << irq) || s->isr & (1 << irq)) { 240 n = irq + irqbase; 241 kvm_notify_acked_irq(kvm, SELECT_PIC(n), n); 242 } 243 } 244 s->last_irr = 0; 245 s->irr = 0; 246 s->imr = 0; 247 s->isr = 0; 248 s->isr_ack = 0xff; 249 s->priority_add = 0; 250 s->irq_base = 0; 251 s->read_reg_select = 0; 252 s->poll = 0; 253 s->special_mask = 0; 254 s->init_state = 0; 255 s->auto_eoi = 0; 256 s->rotate_on_auto_eoi = 0; 257 s->special_fully_nested_mode = 0; 258 s->init4 = 0; 259 } 260 261 static void pic_ioport_write(void *opaque, u32 addr, u32 val) 262 { 263 struct kvm_kpic_state *s = opaque; 264 int priority, cmd, irq; 265 266 addr &= 1; 267 if (addr == 0) { 268 if (val & 0x10) { 269 kvm_pic_reset(s); /* init */ 270 /* 271 * deassert a pending interrupt 272 */ 273 s->pics_state->irq_request(s->pics_state-> 274 irq_request_opaque, 0); 275 s->init_state = 1; 276 s->init4 = val & 1; 277 if (val & 0x02) 278 printk(KERN_ERR "single mode not supported"); 279 if (val & 0x08) 280 printk(KERN_ERR 281 "level sensitive irq not supported"); 282 } else if (val & 0x08) { 283 if (val & 0x04) 284 s->poll = 1; 285 if (val & 0x02) 286 s->read_reg_select = val & 1; 287 if (val & 0x40) 288 s->special_mask = (val >> 5) & 1; 289 } else { 290 cmd = val >> 5; 291 switch (cmd) { 292 case 0: 293 case 4: 294 s->rotate_on_auto_eoi = cmd >> 2; 295 break; 296 case 1: /* end of interrupt */ 297 case 5: 298 priority = get_priority(s, s->isr); 299 if (priority != 8) { 300 irq = (priority + s->priority_add) & 7; 301 pic_clear_isr(s, irq); 302 if (cmd == 5) 303 s->priority_add = (irq + 1) & 7; 304 pic_update_irq(s->pics_state); 305 } 306 break; 307 case 3: 308 irq = val & 7; 309 pic_clear_isr(s, irq); 310 pic_update_irq(s->pics_state); 311 break; 312 case 6: 313 s->priority_add = (val + 1) & 7; 314 pic_update_irq(s->pics_state); 315 break; 316 case 7: 317 irq = val & 7; 318 s->priority_add = (irq + 1) & 7; 319 pic_clear_isr(s, irq); 320 pic_update_irq(s->pics_state); 321 break; 322 default: 323 break; /* no operation */ 324 } 325 } 326 } else 327 switch (s->init_state) { 328 case 0: /* normal mode */ 329 s->imr = val; 330 pic_update_irq(s->pics_state); 331 break; 332 case 1: 333 s->irq_base = val & 0xf8; 334 s->init_state = 2; 335 break; 336 case 2: 337 if (s->init4) 338 s->init_state = 3; 339 else 340 s->init_state = 0; 341 break; 342 case 3: 343 s->special_fully_nested_mode = (val >> 4) & 1; 344 s->auto_eoi = (val >> 1) & 1; 345 s->init_state = 0; 346 break; 347 } 348 } 349 350 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1) 351 { 352 int ret; 353 354 ret = pic_get_irq(s); 355 if (ret >= 0) { 356 if (addr1 >> 7) { 357 s->pics_state->pics[0].isr &= ~(1 << 2); 358 s->pics_state->pics[0].irr &= ~(1 << 2); 359 } 360 s->irr &= ~(1 << ret); 361 pic_clear_isr(s, ret); 362 if (addr1 >> 7 || ret != 2) 363 pic_update_irq(s->pics_state); 364 } else { 365 ret = 0x07; 366 pic_update_irq(s->pics_state); 367 } 368 369 return ret; 370 } 371 372 static u32 pic_ioport_read(void *opaque, u32 addr1) 373 { 374 struct kvm_kpic_state *s = opaque; 375 unsigned int addr; 376 int ret; 377 378 addr = addr1; 379 addr &= 1; 380 if (s->poll) { 381 ret = pic_poll_read(s, addr1); 382 s->poll = 0; 383 } else 384 if (addr == 0) 385 if (s->read_reg_select) 386 ret = s->isr; 387 else 388 ret = s->irr; 389 else 390 ret = s->imr; 391 return ret; 392 } 393 394 static void elcr_ioport_write(void *opaque, u32 addr, u32 val) 395 { 396 struct kvm_kpic_state *s = opaque; 397 s->elcr = val & s->elcr_mask; 398 } 399 400 static u32 elcr_ioport_read(void *opaque, u32 addr1) 401 { 402 struct kvm_kpic_state *s = opaque; 403 return s->elcr; 404 } 405 406 static int picdev_in_range(gpa_t addr) 407 { 408 switch (addr) { 409 case 0x20: 410 case 0x21: 411 case 0xa0: 412 case 0xa1: 413 case 0x4d0: 414 case 0x4d1: 415 return 1; 416 default: 417 return 0; 418 } 419 } 420 421 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev) 422 { 423 return container_of(dev, struct kvm_pic, dev); 424 } 425 426 static int picdev_write(struct kvm_io_device *this, 427 gpa_t addr, int len, const void *val) 428 { 429 struct kvm_pic *s = to_pic(this); 430 unsigned char data = *(unsigned char *)val; 431 if (!picdev_in_range(addr)) 432 return -EOPNOTSUPP; 433 434 if (len != 1) { 435 if (printk_ratelimit()) 436 printk(KERN_ERR "PIC: non byte write\n"); 437 return 0; 438 } 439 spin_lock(&s->lock); 440 switch (addr) { 441 case 0x20: 442 case 0x21: 443 case 0xa0: 444 case 0xa1: 445 pic_ioport_write(&s->pics[addr >> 7], addr, data); 446 break; 447 case 0x4d0: 448 case 0x4d1: 449 elcr_ioport_write(&s->pics[addr & 1], addr, data); 450 break; 451 } 452 spin_unlock(&s->lock); 453 return 0; 454 } 455 456 static int picdev_read(struct kvm_io_device *this, 457 gpa_t addr, int len, void *val) 458 { 459 struct kvm_pic *s = to_pic(this); 460 unsigned char data = 0; 461 if (!picdev_in_range(addr)) 462 return -EOPNOTSUPP; 463 464 if (len != 1) { 465 if (printk_ratelimit()) 466 printk(KERN_ERR "PIC: non byte read\n"); 467 return 0; 468 } 469 spin_lock(&s->lock); 470 switch (addr) { 471 case 0x20: 472 case 0x21: 473 case 0xa0: 474 case 0xa1: 475 data = pic_ioport_read(&s->pics[addr >> 7], addr); 476 break; 477 case 0x4d0: 478 case 0x4d1: 479 data = elcr_ioport_read(&s->pics[addr & 1], addr); 480 break; 481 } 482 *(unsigned char *)val = data; 483 spin_unlock(&s->lock); 484 return 0; 485 } 486 487 /* 488 * callback when PIC0 irq status changed 489 */ 490 static void pic_irq_request(void *opaque, int level) 491 { 492 struct kvm *kvm = opaque; 493 struct kvm_vcpu *vcpu = kvm->bsp_vcpu; 494 struct kvm_pic *s = pic_irqchip(kvm); 495 int irq = pic_get_irq(&s->pics[0]); 496 497 s->output = level; 498 if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) { 499 s->pics[0].isr_ack &= ~(1 << irq); 500 kvm_vcpu_kick(vcpu); 501 } 502 } 503 504 static const struct kvm_io_device_ops picdev_ops = { 505 .read = picdev_read, 506 .write = picdev_write, 507 }; 508 509 struct kvm_pic *kvm_create_pic(struct kvm *kvm) 510 { 511 struct kvm_pic *s; 512 int ret; 513 514 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL); 515 if (!s) 516 return NULL; 517 spin_lock_init(&s->lock); 518 s->kvm = kvm; 519 s->pics[0].elcr_mask = 0xf8; 520 s->pics[1].elcr_mask = 0xde; 521 s->irq_request = pic_irq_request; 522 s->irq_request_opaque = kvm; 523 s->pics[0].pics_state = s; 524 s->pics[1].pics_state = s; 525 526 /* 527 * Initialize PIO device 528 */ 529 kvm_iodevice_init(&s->dev, &picdev_ops); 530 ret = kvm_io_bus_register_dev(kvm, &kvm->pio_bus, &s->dev); 531 if (ret < 0) { 532 kfree(s); 533 return NULL; 534 } 535 536 return s; 537 } 538