1 /* 2 * 8259 interrupt controller emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2007 Intel Corporation 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * Authors: 25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com> 26 * Port from Qemu. 27 */ 28 #include <linux/mm.h> 29 #include "irq.h" 30 31 #include <linux/kvm_host.h> 32 33 static void pic_clear_isr(struct kvm_kpic_state *s, int irq) 34 { 35 s->isr &= ~(1 << irq); 36 } 37 38 /* 39 * set irq level. If an edge is detected, then the IRR is set to 1 40 */ 41 static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level) 42 { 43 int mask; 44 mask = 1 << irq; 45 if (s->elcr & mask) /* level triggered */ 46 if (level) { 47 s->irr |= mask; 48 s->last_irr |= mask; 49 } else { 50 s->irr &= ~mask; 51 s->last_irr &= ~mask; 52 } 53 else /* edge triggered */ 54 if (level) { 55 if ((s->last_irr & mask) == 0) 56 s->irr |= mask; 57 s->last_irr |= mask; 58 } else 59 s->last_irr &= ~mask; 60 } 61 62 /* 63 * return the highest priority found in mask (highest = smallest 64 * number). Return 8 if no irq 65 */ 66 static inline int get_priority(struct kvm_kpic_state *s, int mask) 67 { 68 int priority; 69 if (mask == 0) 70 return 8; 71 priority = 0; 72 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) 73 priority++; 74 return priority; 75 } 76 77 /* 78 * return the pic wanted interrupt. return -1 if none 79 */ 80 static int pic_get_irq(struct kvm_kpic_state *s) 81 { 82 int mask, cur_priority, priority; 83 84 mask = s->irr & ~s->imr; 85 priority = get_priority(s, mask); 86 if (priority == 8) 87 return -1; 88 /* 89 * compute current priority. If special fully nested mode on the 90 * master, the IRQ coming from the slave is not taken into account 91 * for the priority computation. 92 */ 93 mask = s->isr; 94 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) 95 mask &= ~(1 << 2); 96 cur_priority = get_priority(s, mask); 97 if (priority < cur_priority) 98 /* 99 * higher priority found: an irq should be generated 100 */ 101 return (priority + s->priority_add) & 7; 102 else 103 return -1; 104 } 105 106 /* 107 * raise irq to CPU if necessary. must be called every time the active 108 * irq may change 109 */ 110 static void pic_update_irq(struct kvm_pic *s) 111 { 112 int irq2, irq; 113 114 irq2 = pic_get_irq(&s->pics[1]); 115 if (irq2 >= 0) { 116 /* 117 * if irq request by slave pic, signal master PIC 118 */ 119 pic_set_irq1(&s->pics[0], 2, 1); 120 pic_set_irq1(&s->pics[0], 2, 0); 121 } 122 irq = pic_get_irq(&s->pics[0]); 123 if (irq >= 0) 124 s->irq_request(s->irq_request_opaque, 1); 125 else 126 s->irq_request(s->irq_request_opaque, 0); 127 } 128 129 void kvm_pic_update_irq(struct kvm_pic *s) 130 { 131 pic_update_irq(s); 132 } 133 134 void kvm_pic_set_irq(void *opaque, int irq, int level) 135 { 136 struct kvm_pic *s = opaque; 137 138 if (irq >= 0 && irq < PIC_NUM_PINS) { 139 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); 140 pic_update_irq(s); 141 } 142 } 143 144 /* 145 * acknowledge interrupt 'irq' 146 */ 147 static inline void pic_intack(struct kvm_kpic_state *s, int irq) 148 { 149 s->isr |= 1 << irq; 150 if (s->auto_eoi) { 151 if (s->rotate_on_auto_eoi) 152 s->priority_add = (irq + 1) & 7; 153 pic_clear_isr(s, irq); 154 } 155 /* 156 * We don't clear a level sensitive interrupt here 157 */ 158 if (!(s->elcr & (1 << irq))) 159 s->irr &= ~(1 << irq); 160 } 161 162 int kvm_pic_read_irq(struct kvm *kvm) 163 { 164 int irq, irq2, intno; 165 struct kvm_pic *s = pic_irqchip(kvm); 166 167 irq = pic_get_irq(&s->pics[0]); 168 if (irq >= 0) { 169 pic_intack(&s->pics[0], irq); 170 if (irq == 2) { 171 irq2 = pic_get_irq(&s->pics[1]); 172 if (irq2 >= 0) 173 pic_intack(&s->pics[1], irq2); 174 else 175 /* 176 * spurious IRQ on slave controller 177 */ 178 irq2 = 7; 179 intno = s->pics[1].irq_base + irq2; 180 irq = irq2 + 8; 181 } else 182 intno = s->pics[0].irq_base + irq; 183 } else { 184 /* 185 * spurious IRQ on host controller 186 */ 187 irq = 7; 188 intno = s->pics[0].irq_base + irq; 189 } 190 pic_update_irq(s); 191 kvm_notify_acked_irq(kvm, irq); 192 193 return intno; 194 } 195 196 void kvm_pic_reset(struct kvm_kpic_state *s) 197 { 198 int irq, irqbase; 199 struct kvm *kvm = s->pics_state->irq_request_opaque; 200 struct kvm_vcpu *vcpu0 = kvm->vcpus[0]; 201 202 if (s == &s->pics_state->pics[0]) 203 irqbase = 0; 204 else 205 irqbase = 8; 206 207 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) { 208 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0)) 209 if (s->irr & (1 << irq) || s->isr & (1 << irq)) 210 kvm_notify_acked_irq(kvm, irq+irqbase); 211 } 212 s->last_irr = 0; 213 s->irr = 0; 214 s->imr = 0; 215 s->isr = 0; 216 s->priority_add = 0; 217 s->irq_base = 0; 218 s->read_reg_select = 0; 219 s->poll = 0; 220 s->special_mask = 0; 221 s->init_state = 0; 222 s->auto_eoi = 0; 223 s->rotate_on_auto_eoi = 0; 224 s->special_fully_nested_mode = 0; 225 s->init4 = 0; 226 } 227 228 static void pic_ioport_write(void *opaque, u32 addr, u32 val) 229 { 230 struct kvm_kpic_state *s = opaque; 231 int priority, cmd, irq; 232 233 addr &= 1; 234 if (addr == 0) { 235 if (val & 0x10) { 236 kvm_pic_reset(s); /* init */ 237 /* 238 * deassert a pending interrupt 239 */ 240 s->pics_state->irq_request(s->pics_state-> 241 irq_request_opaque, 0); 242 s->init_state = 1; 243 s->init4 = val & 1; 244 if (val & 0x02) 245 printk(KERN_ERR "single mode not supported"); 246 if (val & 0x08) 247 printk(KERN_ERR 248 "level sensitive irq not supported"); 249 } else if (val & 0x08) { 250 if (val & 0x04) 251 s->poll = 1; 252 if (val & 0x02) 253 s->read_reg_select = val & 1; 254 if (val & 0x40) 255 s->special_mask = (val >> 5) & 1; 256 } else { 257 cmd = val >> 5; 258 switch (cmd) { 259 case 0: 260 case 4: 261 s->rotate_on_auto_eoi = cmd >> 2; 262 break; 263 case 1: /* end of interrupt */ 264 case 5: 265 priority = get_priority(s, s->isr); 266 if (priority != 8) { 267 irq = (priority + s->priority_add) & 7; 268 pic_clear_isr(s, irq); 269 if (cmd == 5) 270 s->priority_add = (irq + 1) & 7; 271 pic_update_irq(s->pics_state); 272 } 273 break; 274 case 3: 275 irq = val & 7; 276 pic_clear_isr(s, irq); 277 pic_update_irq(s->pics_state); 278 break; 279 case 6: 280 s->priority_add = (val + 1) & 7; 281 pic_update_irq(s->pics_state); 282 break; 283 case 7: 284 irq = val & 7; 285 s->priority_add = (irq + 1) & 7; 286 pic_clear_isr(s, irq); 287 pic_update_irq(s->pics_state); 288 break; 289 default: 290 break; /* no operation */ 291 } 292 } 293 } else 294 switch (s->init_state) { 295 case 0: /* normal mode */ 296 s->imr = val; 297 pic_update_irq(s->pics_state); 298 break; 299 case 1: 300 s->irq_base = val & 0xf8; 301 s->init_state = 2; 302 break; 303 case 2: 304 if (s->init4) 305 s->init_state = 3; 306 else 307 s->init_state = 0; 308 break; 309 case 3: 310 s->special_fully_nested_mode = (val >> 4) & 1; 311 s->auto_eoi = (val >> 1) & 1; 312 s->init_state = 0; 313 break; 314 } 315 } 316 317 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1) 318 { 319 int ret; 320 321 ret = pic_get_irq(s); 322 if (ret >= 0) { 323 if (addr1 >> 7) { 324 s->pics_state->pics[0].isr &= ~(1 << 2); 325 s->pics_state->pics[0].irr &= ~(1 << 2); 326 } 327 s->irr &= ~(1 << ret); 328 pic_clear_isr(s, ret); 329 if (addr1 >> 7 || ret != 2) 330 pic_update_irq(s->pics_state); 331 } else { 332 ret = 0x07; 333 pic_update_irq(s->pics_state); 334 } 335 336 return ret; 337 } 338 339 static u32 pic_ioport_read(void *opaque, u32 addr1) 340 { 341 struct kvm_kpic_state *s = opaque; 342 unsigned int addr; 343 int ret; 344 345 addr = addr1; 346 addr &= 1; 347 if (s->poll) { 348 ret = pic_poll_read(s, addr1); 349 s->poll = 0; 350 } else 351 if (addr == 0) 352 if (s->read_reg_select) 353 ret = s->isr; 354 else 355 ret = s->irr; 356 else 357 ret = s->imr; 358 return ret; 359 } 360 361 static void elcr_ioport_write(void *opaque, u32 addr, u32 val) 362 { 363 struct kvm_kpic_state *s = opaque; 364 s->elcr = val & s->elcr_mask; 365 } 366 367 static u32 elcr_ioport_read(void *opaque, u32 addr1) 368 { 369 struct kvm_kpic_state *s = opaque; 370 return s->elcr; 371 } 372 373 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr, 374 int len, int is_write) 375 { 376 switch (addr) { 377 case 0x20: 378 case 0x21: 379 case 0xa0: 380 case 0xa1: 381 case 0x4d0: 382 case 0x4d1: 383 return 1; 384 default: 385 return 0; 386 } 387 } 388 389 static void picdev_write(struct kvm_io_device *this, 390 gpa_t addr, int len, const void *val) 391 { 392 struct kvm_pic *s = this->private; 393 unsigned char data = *(unsigned char *)val; 394 395 if (len != 1) { 396 if (printk_ratelimit()) 397 printk(KERN_ERR "PIC: non byte write\n"); 398 return; 399 } 400 switch (addr) { 401 case 0x20: 402 case 0x21: 403 case 0xa0: 404 case 0xa1: 405 pic_ioport_write(&s->pics[addr >> 7], addr, data); 406 break; 407 case 0x4d0: 408 case 0x4d1: 409 elcr_ioport_write(&s->pics[addr & 1], addr, data); 410 break; 411 } 412 } 413 414 static void picdev_read(struct kvm_io_device *this, 415 gpa_t addr, int len, void *val) 416 { 417 struct kvm_pic *s = this->private; 418 unsigned char data = 0; 419 420 if (len != 1) { 421 if (printk_ratelimit()) 422 printk(KERN_ERR "PIC: non byte read\n"); 423 return; 424 } 425 switch (addr) { 426 case 0x20: 427 case 0x21: 428 case 0xa0: 429 case 0xa1: 430 data = pic_ioport_read(&s->pics[addr >> 7], addr); 431 break; 432 case 0x4d0: 433 case 0x4d1: 434 data = elcr_ioport_read(&s->pics[addr & 1], addr); 435 break; 436 } 437 *(unsigned char *)val = data; 438 } 439 440 /* 441 * callback when PIC0 irq status changed 442 */ 443 static void pic_irq_request(void *opaque, int level) 444 { 445 struct kvm *kvm = opaque; 446 struct kvm_vcpu *vcpu = kvm->vcpus[0]; 447 448 pic_irqchip(kvm)->output = level; 449 if (vcpu) 450 kvm_vcpu_kick(vcpu); 451 } 452 453 struct kvm_pic *kvm_create_pic(struct kvm *kvm) 454 { 455 struct kvm_pic *s; 456 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL); 457 if (!s) 458 return NULL; 459 s->pics[0].elcr_mask = 0xf8; 460 s->pics[1].elcr_mask = 0xde; 461 s->irq_request = pic_irq_request; 462 s->irq_request_opaque = kvm; 463 s->pics[0].pics_state = s; 464 s->pics[1].pics_state = s; 465 466 /* 467 * Initialize PIO device 468 */ 469 s->dev.read = picdev_read; 470 s->dev.write = picdev_write; 471 s->dev.in_range = picdev_in_range; 472 s->dev.private = s; 473 kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev); 474 return s; 475 } 476